diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
index 59dcd6c..c2a66a6 100644
--- a/project/template_2/riscvsingle.vhdl
+++ b/project/template_2/riscvsingle.vhdl
@@ -606,6 +606,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
 
+
 entity shifter is -- shifter
   port(a, b : in  STD_ULOGIC_VECTOR(31 downto 0);
        y:     out STD_ULOGIC_VECTOR(31 downto 0));
@@ -613,7 +614,8 @@ end;
 
 architecture behave of shifter is  -- shift a left by b (as int)
 begin
-  y <= a sll to_integer(unsigned(b));
+  --y <= a sll to_integer(unsigned(b));
+  y <= shift_left(a, b);
 end;