From d4807ce265144f1467ea2cb7f9444b903a30e8e4 Mon Sep 17 00:00:00 2001
From: michael9186 <31957225+michael9186@users.noreply.github.com>
Date: Fri, 2 Jun 2023 18:08:31 +0200
Subject: [PATCH] Update riscvsingle.vhdl

---
 project/template_2/riscvsingle.vhdl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/project/template_2/riscvsingle.vhdl b/project/template_2/riscvsingle.vhdl
index 7a8a337..661963b 100644
--- a/project/template_2/riscvsingle.vhdl
+++ b/project/template_2/riscvsingle.vhdl
@@ -204,8 +204,8 @@ architecture struct of controller is
   signal Branch: STD_ULOGIC;
   signal Jump_s : STD_ULOGIC;
 begin
-  md: maindec port map(op, funct3, ResultSrc, MemWrite, Branch,
-                       ALUSrc, RegWrite, Jump_s, ImmSrc, ALUOp);
+  md: maindec port map(op, funct3, ResultSrc, ALUSrc, MemWrite, Branch, 
+                      RegWrite, Jump_s, ImmSrc, ALUOp);
   ad: aludec port map(op(5), funct3, funct7b5, ALUOp, ALUControl);
   
   PCSrc <= (Branch and Zero) or Jump_s;