Atari800_Q13.srf

{ "" "" "" "Ignored filter at sys_top.sdc(18): vip\|output_inst\|vid_clk could not be matched with a net" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(17): Argument <targets> is an empty collection" {  } {  } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic." {  } {  } 0 12030 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" {  } {  } 0 205009 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" {  } {  } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}