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aq_ptp.c
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aq_ptp.c
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// SPDX-License-Identifier: GPL-2.0-only
/* Atlantic Network Driver
*
* Copyright (C) 2014-2019 aQuantia Corporation
* Copyright (C) 2019-2020 Marvell International Ltd.
*/
/* File aq_ptp.c:
* Definition of functions for Linux PTP support.
*/
#include <linux/version.h>
#include <linux/moduleparam.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/ptp_classify.h>
#include <linux/interrupt.h>
#include <linux/clocksource.h>
#include "aq_hw_utils.h"
#include "aq_nic.h"
#include "aq_ptp.h"
#include "aq_ring.h"
#include "aq_phy.h"
#include "aq_ethtool.h"
#include "aq_filters.h"
#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
#include <linux/moduleparam.h>
#include <linux/ptp_clock_kernel.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0) || RHEL_RELEASE_CODE
#include <linux/timecounter.h>
#endif
#include <linux/clocksource.h>
#define AQ_PTP_TX_TIMEOUT (HZ * 10)
static unsigned int aq_ptp_offset_forced = 0;
module_param(aq_ptp_offset_forced, uint, 0644);
MODULE_PARM_DESC(aq_ptp_offset_forced, "Force to use the driver parameters");
static unsigned int aq_ptp_offset_100 = 0;
module_param(aq_ptp_offset_100, uint, 0644);
MODULE_PARM_DESC(aq_ptp_offset_100, "PTP offset for 100M");
static unsigned int aq_ptp_offset_1000 = 0;
module_param(aq_ptp_offset_1000, uint, 0644);
MODULE_PARM_DESC(aq_ptp_offset_1000, "PTP offset for 1G");
static unsigned int aq_ptp_offset_2500 = 0;
module_param(aq_ptp_offset_2500, uint, 0644);
MODULE_PARM_DESC(aq_ptp_offset_2500, "PTP offset for 2,5G");
static unsigned int aq_ptp_offset_5000 = 0;
module_param(aq_ptp_offset_5000, uint, 0644);
MODULE_PARM_DESC(aq_ptp_offset_5000, "PTP offset for 5G");
static unsigned int aq_ptp_offset_10000 = 0;
module_param(aq_ptp_offset_10000, uint, 0644);
MODULE_PARM_DESC(aq_ptp_offset_10000, "PTP offset for 10G");
#define POLL_SYNC_TIMER_MS 15
/* Coefficients of PID. Multiplier and divider are used for distinguish
* more accuracy while calculating PID parts
*/
#define PTP_MULT_COEF_P 15LL
#define PTP_MULT_COEF_I 5LL
#define PTP_MULT_COEF_D 1LL
#define PTP_DIV_COEF 10LL
#define PTP_DIV_RATIO 100LL
#define ACCURACY 20
#define PTP_UDP_FILTERS_CNT 4
#define PTP_IPV4_MC_ADDR1 0xE0000181
#define PTP_IPV4_MC_ADDR2 0xE000006B
#define PTP_IPV6_MC_ADDR10 0xFF0E
#define PTP_IPV6_MC_ADDR14 0x0181
#define PTP_IPV6_MC_ADDR20 0xFF02
#define PTP_IPV6_MC_ADDR24 0x006B
static unsigned int aq_ptp_gpio_hightime = 100000;
module_param_named(aq_ptp_gpio_hightime, aq_ptp_gpio_hightime, uint, 0644);
MODULE_PARM_DESC(aq_ptp_gpio_hightime, "PTP GPIO high time");
enum ptp_extts_action {
ptp_extts_disabled = 0,
ptp_extts_user,
ptp_extts_timesync,
ptp_extts_freqsync
};
enum ptp_perout_action {
ptp_perout_disabled = 0,
ptp_perout_enabled,
ptp_perout_pps,
};
enum ptp_speed_offsets {
ptp_offset_idx_10 = 0,
ptp_offset_idx_100,
ptp_offset_idx_1000,
ptp_offset_idx_2500,
ptp_offset_idx_5000,
ptp_offset_idx_10000,
};
struct ptp_skb_ring {
struct sk_buff **buff;
spinlock_t lock;
unsigned int size;
unsigned int head;
unsigned int tail;
};
struct ptp_tx_timeout {
spinlock_t lock;
bool active;
unsigned long tx_start;
};
struct aq_ptp_pid {
bool first_diff;
uint64_t last_sync1588_ts;
u64 ext_sync_period;
/*PID related values*/
s64 delta[3];
s64 adjust[2];
/*Describes ratio of current period to 1s*/
s64 multiplier;
s64 divider;
};
struct ptp_tm_offset {
unsigned int mbps;
int egress;
int ingress;
};
struct aq_ptp_s {
struct aq_nic_s *aq_nic;
struct hwtstamp_config hwtstamp_config;
spinlock_t ptp_lock;
spinlock_t ptp_ring_lock;
struct ptp_clock *ptp_clock;
struct ptp_clock_info ptp_info;
atomic_t offset_egress;
atomic_t offset_ingress;
struct aq_ring_param_s ptp_ring_param;
struct ptp_tx_timeout ptp_tx_timeout;
unsigned int idx_ptp_vector;
unsigned int idx_gpio_vector;
struct napi_struct napi;
struct aq_ring_s ptp_tx;
struct aq_ring_s ptp_rx;
struct aq_ring_s hwts_rx; //ATL1 FW
struct ptp_skb_ring skb_ring;
struct aq_rx_filter_l3l4 udp_filter[PTP_UDP_FILTERS_CNT];
struct aq_rx_filter_l2 eth_type_filter;
struct delayed_work poll_sync;
u32 poll_timeout_ms;
bool extts_pin_enabled;
u64 sync_time_value;
/* TSG clock selection: 0 - PTP, 1 - PTM */
u32 ptp_clock_sel;
struct aq_ptp_pid pid;
bool a1_ptp;
bool a2_ptp;
struct ptp_tm_offset ptp_offset[6];
};
static int aq_ptp_extts_pin_configure(struct ptp_clock_info *ptp,
u32 n_pin, enum ptp_extts_action action);
static int aq_pps_reconfigure(struct aq_ptp_s *aq_ptp);
void aq_ptp_offset_get(struct aq_ptp_s *aq_ptp,
unsigned int mbps, int *egress, int *ingress)
{
int i;
for (i = 0; i < ARRAY_SIZE(aq_ptp->ptp_offset); i++) {
if (mbps == aq_ptp->ptp_offset[i].mbps) {
*egress = aq_ptp->ptp_offset[i].egress;
*ingress = aq_ptp->ptp_offset[i].ingress;
break;
}
}
}
void aq_ptp_tm_offset_set(struct aq_nic_s *aq_nic, unsigned int mbps)
{
struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
int i, egress, ingress;
if (!aq_ptp)
return;
egress = 0;
ingress = 0;
for (i = 0; i < ARRAY_SIZE(aq_ptp->ptp_offset); i++) {
if (mbps == aq_ptp->ptp_offset[i].mbps) {
egress = aq_ptp->ptp_offset[i].egress;
ingress = aq_ptp->ptp_offset[i].ingress;
break;
}
}
atomic_set(&aq_ptp->offset_egress, egress);
atomic_set(&aq_ptp->offset_ingress, ingress);
aq_pr_verbose(aq_nic, AQ_MSG_PTP, "Offsets: egress = %d ingress = %d\n", egress, ingress);
}
static int __aq_ptp_skb_put(struct ptp_skb_ring *ring, struct sk_buff *skb)
{
unsigned int next_head = (ring->head + 1) % ring->size;
if (next_head == ring->tail)
return -ENOMEM;
ring->buff[ring->head] = skb_get(skb);
ring->head = next_head;
return 0;
}
static int aq_ptp_skb_put(struct ptp_skb_ring *ring, struct sk_buff *skb)
{
unsigned long flags;
int ret;
spin_lock_irqsave(&ring->lock, flags);
ret = __aq_ptp_skb_put(ring, skb);
spin_unlock_irqrestore(&ring->lock, flags);
return ret;
}
static struct sk_buff *__aq_ptp_skb_get(struct ptp_skb_ring *ring)
{
struct sk_buff *skb;
if (ring->tail == ring->head)
return NULL;
skb = ring->buff[ring->tail];
ring->tail = (ring->tail + 1) % ring->size;
return skb;
}
static struct sk_buff *aq_ptp_skb_get(struct ptp_skb_ring *ring)
{
unsigned long flags;
struct sk_buff *skb;
spin_lock_irqsave(&ring->lock, flags);
skb = __aq_ptp_skb_get(ring);
spin_unlock_irqrestore(&ring->lock, flags);
return skb;
}
static unsigned int aq_ptp_skb_buf_len(struct ptp_skb_ring *ring)
{
unsigned long flags;
unsigned int len;
spin_lock_irqsave(&ring->lock, flags);
len = (ring->head >= ring->tail) ?
ring->head - ring->tail :
ring->size - ring->tail + ring->head;
spin_unlock_irqrestore(&ring->lock, flags);
return len;
}
static int aq_ptp_skb_ring_init(struct ptp_skb_ring *ring, unsigned int size)
{
struct sk_buff **buff = kmalloc(sizeof(*buff) * size, GFP_KERNEL);
if (!buff)
return -ENOMEM;
spin_lock_init(&ring->lock);
ring->buff = buff;
ring->size = size;
ring->head = 0;
ring->tail = 0;
return 0;
}
static void aq_ptp_skb_ring_clean(struct ptp_skb_ring *ring)
{
struct sk_buff *skb;
while ((skb = aq_ptp_skb_get(ring)) != NULL)
dev_kfree_skb_any(skb);
}
static void aq_ptp_skb_ring_release(struct ptp_skb_ring *ring)
{
if (ring->buff) {
aq_ptp_skb_ring_clean(ring);
kfree(ring->buff);
ring->buff = NULL;
}
}
static void aq_ptp_tx_timeout_init(struct ptp_tx_timeout *timeout)
{
spin_lock_init(&timeout->lock);
timeout->active = false;
}
static void aq_ptp_tx_timeout_start(struct aq_ptp_s *aq_ptp)
{
struct ptp_tx_timeout *timeout = &aq_ptp->ptp_tx_timeout;
unsigned long flags;
spin_lock_irqsave(&timeout->lock, flags);
timeout->active = true;
timeout->tx_start = jiffies;
spin_unlock_irqrestore(&timeout->lock, flags);
}
static void aq_ptp_tx_timeout_update(struct aq_ptp_s *aq_ptp)
{
if (!aq_ptp_skb_buf_len(&aq_ptp->skb_ring)) {
struct ptp_tx_timeout *timeout = &aq_ptp->ptp_tx_timeout;
unsigned long flags;
spin_lock_irqsave(&timeout->lock, flags);
timeout->active = false;
spin_unlock_irqrestore(&timeout->lock, flags);
}
}
static void aq_ptp_tx_timeout_check(struct aq_ptp_s *aq_ptp)
{
struct ptp_tx_timeout *timeout = &aq_ptp->ptp_tx_timeout;
unsigned long flags;
bool timeout_flag;
timeout_flag = false;
spin_lock_irqsave(&timeout->lock, flags);
if (timeout->active) {
timeout_flag = time_is_before_jiffies(timeout->tx_start +
AQ_PTP_TX_TIMEOUT);
/* reset active flag if timeout detected */
if (timeout_flag)
timeout->active = false;
}
spin_unlock_irqrestore(&timeout->lock, flags);
if (timeout_flag) {
aq_ptp_skb_ring_clean(&aq_ptp->skb_ring);
netdev_err(aq_ptp->aq_nic->ndev,
"PTP Timeout. Clearing Tx Timestamp SKBs\n");
}
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)
/* aq_ptp_adjfine
* @ptp: the ptp clock structure
* @ppb: parts per billion adjustment from base
*
* adjust the frequency of the ptp cycle counter by the
* indicated ppb from the base frequency.
*/
static int aq_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
mutex_lock(&aq_nic->fwreq_mutex);
aq_nic->aq_hw_ops->hw_adj_clock_freq(aq_nic->aq_hw,
scaled_ppm_to_ppb(scaled_ppm));
mutex_unlock(&aq_nic->fwreq_mutex);
return 0;
}
#endif
static int aq_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
aq_pr_verbose(aq_nic, AQ_MSG_PTP, "AQ PTP Adj Freq 0x%x\n", ppb);
mutex_lock(&aq_nic->fwreq_mutex);
aq_nic->aq_hw_ops->hw_adj_clock_freq(aq_nic->aq_hw, ppb);
mutex_unlock(&aq_nic->fwreq_mutex);
return 0;
}
/* aq_ptp_adjtime
* @ptp: the ptp clock structure
* @delta: offset to adjust the cycle counter by
*
* adjust the timer by resetting the timecounter structure.
*/
static int aq_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
unsigned long flags;
aq_pr_verbose(aq_nic, AQ_MSG_PTP, "AQ PTP Adj Time 0x%llx\n", delta);
spin_lock_irqsave(&aq_ptp->ptp_lock, flags);
aq_nic->aq_hw_ops->hw_adj_sys_clock(aq_nic->aq_hw, delta);
spin_unlock_irqrestore(&aq_ptp->ptp_lock, flags);
aq_pps_reconfigure(aq_ptp);
return 0;
}
/* aq_ptp_gettime
* @ptp: the ptp clock structure
* @ts: timespec structure to hold the current time value
*
* read the timecounter and return the correct value on ns,
* after converting it into a struct timespec.
*/
static int aq_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
unsigned long flags;
u64 ns;
spin_lock_irqsave(&aq_ptp->ptp_lock, flags);
aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &ns);
spin_unlock_irqrestore(&aq_ptp->ptp_lock, flags);
*ts = ns_to_timespec64(ns);
return 0;
}
/* aq_ptp_settime
* @ptp: the ptp clock structure
* @ts: the timespec containing the new time for the cycle counter
*
* reset the timecounter to use a new base value instead of the kernel
* wall timer value.
*/
static int aq_ptp_settime(struct ptp_clock_info *ptp,
const struct timespec64 *ts)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
unsigned long flags;
u64 ns = timespec64_to_ns(ts);
u64 now;
spin_lock_irqsave(&aq_ptp->ptp_lock, flags);
aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &now);
aq_nic->aq_hw_ops->hw_adj_sys_clock(aq_nic->aq_hw, (s64)ns - (s64)now);
spin_unlock_irqrestore(&aq_ptp->ptp_lock, flags);
aq_pps_reconfigure(aq_ptp);
aq_pr_verbose(aq_nic, AQ_MSG_PTP, "AQ PTP Set time: new %llu\n", ns);
return 0;
}
static void aq_ptp_convert_to_hwtstamp(struct aq_ptp_s *aq_ptp,
struct skb_shared_hwtstamps *hwtstamp,
u64 timestamp)
{
memset(hwtstamp, 0, sizeof(*hwtstamp));
hwtstamp->hwtstamp = ns_to_ktime(timestamp);
}
static bool aq_ptp_event_ts_updated(struct aq_ptp_s *aq_ptp, u32 clk_sel,
u64 prev_ts, u64 *new_ts, u32 *cnt)
{
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
uint64_t event_ts2;
uint64_t event_ts;
event_ts = aq_nic->aq_hw_ops->hw_ptp_gpio_get_event(aq_nic->aq_hw,
clk_sel, cnt);
if (event_ts != prev_ts) {
event_ts2 =
aq_nic->aq_hw_ops->hw_ptp_gpio_get_event(aq_nic->aq_hw,
clk_sel,
cnt);
if (event_ts != event_ts2) {
event_ts = event_ts2;
event_ts2 = aq_nic->aq_hw_ops->hw_ptp_gpio_get_event(
aq_nic->aq_hw, clk_sel, cnt);
if (event_ts != event_ts2) {
netdev_err(aq_nic->ndev,
"%s: Unable to get correct GPIO TS",
__func__);
event_ts = 0;
}
}
*new_ts = event_ts;
return true;
}
return false;
}
bool aq_ptp_ts_valid(struct aq_ptp_pid *aq_pid, u64 diff)
{
/* check we get valid TS, let's use simple check: if difference of
* ts_diff and expected period more than half of expected period it
* means we've got invalid TS
*/
return abs((int64_t)diff - aq_pid->ext_sync_period) <
div_u64(aq_pid->ext_sync_period, 3);
}
static void aq_ptp_pid_reset(struct aq_ptp_pid *aq_pid)
{
memset(aq_pid->delta, 0, sizeof(aq_pid->delta));
memset(aq_pid->adjust, 0, sizeof(aq_pid->adjust));
aq_pid->first_diff = true;
}
static int aq_ptp_pid(struct aq_ptp_s *aq_ptp, u64 ts_diff)
{
s64 p, integral, diff;
struct aq_ptp_pid *aq_pid = &aq_ptp->pid;
if (aq_pid->first_diff) {
aq_pid->first_diff = false;
return 0;
}
if (!aq_ptp_ts_valid(aq_pid, ts_diff)) {
netdev_err(aq_ptp->aq_nic->ndev,
"Invalid TS got, reset synchronization"
" algorithm: TS diff: %llu,"
" expected: about %llu",
ts_diff, aq_pid->ext_sync_period);
aq_ptp_pid_reset(aq_pid);
aq_ptp_adjfreq(&aq_ptp->ptp_info, 0);
return 0;
}
aq_pid->delta[0] += ts_diff;
aq_pid->delta[0] -= aq_pid->ext_sync_period;
p = PTP_MULT_COEF_P * aq_pid->multiplier *
(aq_pid->delta[0] - aq_pid->delta[1]);
integral = PTP_MULT_COEF_I * aq_pid->multiplier * aq_pid->delta[1];
diff = PTP_MULT_COEF_D * aq_pid->multiplier *
(aq_pid->delta[0] - 2 * aq_pid->delta[1] +
aq_pid->delta[2]);
aq_pr_verbose(aq_ptp->aq_nic, AQ_MSG_PTP,
"p = %lld, integral = %lld, diff = %lld",
div_s64(p, mul_u32_u32(PTP_DIV_COEF, aq_pid->divider)),
div_s64(integral, mul_u32_u32(PTP_DIV_COEF,
aq_pid->divider)),
div_s64(diff, mul_u32_u32(PTP_DIV_COEF, aq_pid->divider)));
aq_pid->adjust[0] = div_s64((p + integral + diff),
mul_u32_u32(PTP_DIV_COEF,
aq_pid->divider)) +
aq_pid->adjust[1];
aq_pid->adjust[1] = aq_pid->adjust[0];
aq_pid->delta[2] = aq_pid->delta[1];
aq_pid->delta[1] = aq_pid->delta[0];
aq_pr_verbose(aq_ptp->aq_nic, AQ_MSG_PTP, "delta = %lld, adjust = %lld",
aq_pid->delta[0], aq_pid->adjust[0]);
/* Apply adjust in case if current delta more than 20 or
* changing of delta more than 20 (speed of delta
* changing)
*/
if (abs(aq_pid->delta[0]) > ACCURACY ||
abs(aq_pid->delta[1] - aq_pid->delta[2]) > ACCURACY)
aq_ptp_adjfreq(&aq_ptp->ptp_info,
-aq_pid->adjust[0]);
return 0;
}
/* Check whether sync1588 pin was triggered, and set stored new PTP time */
static int aq_ptp_check_ext_gpio_event(struct aq_ptp_s *aq_ptp)
{
struct ptp_clock_info *clock_info = &aq_ptp->ptp_info;
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
int repeat_event = 0;
int n_pin;
for (n_pin = 0; n_pin < aq_ptp->ptp_info.n_pins; n_pin++) {
struct ptp_pin_desc *pin_desc =
&aq_ptp->ptp_info.pin_config[n_pin];
if (pin_desc->func == PTP_PF_EXTTS) {
enum ptp_extts_action action = pin_desc->rsv[2];
u64 prev_ts = ((uint64_t *)pin_desc->rsv)[0];
u64 ts = prev_ts;
u32 cnt = 0;
repeat_event = 1;
/* Sync1588 pin was triggered */
if (aq_ptp_event_ts_updated(aq_ptp,
aq_ptp->ptp_clock_sel,
prev_ts, &ts, &cnt)) {
u64 ts_diff = ts - prev_ts;
aq_pr_verbose(aq_nic, AQ_MSG_PTP,
"%s: pin %d with act %x triggered TS: %llu, prev TS %llu, diff %llu",
__func__, n_pin, action,
ts, prev_ts, ts_diff);
switch (action) {
case ptp_extts_timesync: {
unsigned long flags;
spin_lock_irqsave(&aq_ptp->ptp_lock,
flags);
aq_nic->aq_hw_ops->hw_set_sys_clock(
aq_nic->aq_hw,
aq_ptp->sync_time_value,
ts);
spin_unlock_irqrestore(
&aq_ptp->ptp_lock,
flags);
if (aq_ptp->extts_pin_enabled)
action = ptp_extts_user;
else
action = ptp_extts_disabled;
repeat_event = 0;
}
break;
case ptp_extts_freqsync:
if (aq_ptp_pid(aq_ptp, ts_diff))
repeat_event = 0;
break;
default:
break;
}
if (aq_ptp->extts_pin_enabled) {
struct ptp_clock_event ptp_event;
u64 time = 0;
aq_nic->aq_hw_ops->hw_ts_to_sys_clock(
aq_nic->aq_hw,
ts, &time);
ptp_event.type = PTP_CLOCK_EXTTS;
ptp_event.index =
aq_ptp->a2_ptp ?
n_pin : clock_info->n_pins - 1;
ptp_event.timestamp = time;
ptp_clock_event(aq_ptp->ptp_clock,
&ptp_event);
}
((uint64_t *)pin_desc->rsv)[0] = ts;
pin_desc->rsv[2] = action;
}
}
}
return repeat_event;
}
/* PTP external GPIO nanoseconds count */
static void aq_ptp_poll_sync_work_cb(struct work_struct *w)
{
struct delayed_work *dw = to_delayed_work(w);
struct aq_ptp_s *aq_ptp = container_of(dw, struct aq_ptp_s, poll_sync);
if (aq_ptp_check_ext_gpio_event(aq_ptp)) {
unsigned long timeout = msecs_to_jiffies(
aq_ptp->poll_timeout_ms);
schedule_delayed_work(&aq_ptp->poll_sync, timeout);
}
}
static int aq_ptp_hw_pin_conf(struct aq_nic_s *aq_nic, u32 pin_index,
u64 start, u64 period)
{
struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
aq_pr_verbose(aq_nic, AQ_MSG_PTP,
"%sable GPIO %d pulsing, start time %llu, period %u\n",
period ? "En" : "Dis", pin_index, start, (u32)period);
/* Notify hardware of request to being sending pulses.
* If period is ZERO then pulsen is disabled.
*/
mutex_lock(&aq_nic->fwreq_mutex);
aq_nic->aq_hw_ops->hw_gpio_pulse(aq_nic->aq_hw, pin_index,
aq_ptp->ptp_clock_sel, start,
(u32)period, aq_ptp_gpio_hightime);
mutex_unlock(&aq_nic->fwreq_mutex);
return 0;
}
static int aq_ptp_perout_pin_configure(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct ptp_clock_time *t = &rq->perout.period;
struct ptp_clock_time *s = &rq->perout.start;
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
u32 n_pin = rq->perout.index;
u64 start, period;
aq_pr_verbose(aq_nic, AQ_MSG_PTP,
"n_pin = %d t->sec = %lld t->nsec = %d enable = %d",
n_pin, t->sec, t->nsec, on);
/* verify the request channel is there */
if (n_pin >= ptp->n_per_out)
return -EINVAL;
if (aq_ptp->ptp_info.pin_config[n_pin].func != PTP_PF_PEROUT)
return -EINVAL;
/* we cannot support periods greater
* than 4 seconds due to reg limit
*/
if (t->sec > 4 || t->sec < 0)
return -ERANGE;
/* convert to unsigned 64b ns,
* verify we can put it in a 32b register
*/
period = on ? t->sec * NSEC_PER_SEC + t->nsec : 0;
/* verify the value is in range supported by hardware */
if (period > U32_MAX)
return -ERANGE;
/* convert to unsigned 64b ns */
/* TODO convert to AQ time */
start = on ? s->sec * NSEC_PER_SEC + s->nsec : 0;
aq_ptp->ptp_info.pin_config[n_pin].rsv[2] = on ? ptp_perout_enabled :
ptp_perout_disabled;
aq_ptp_hw_pin_conf(aq_nic, aq_ptp->ptp_info.pin_config[n_pin].rsv[3],
start, period);
return 0;
}
static int aq_ptp_pps_pin_configure(struct ptp_clock_info *ptp, int on)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
u64 start, period;
u32 rest = 0;
u32 n_pin;
aq_pr_verbose(aq_nic, AQ_MSG_PTP, "PPS pin enable = %d\n", on);
for (n_pin = 0; n_pin < ptp->n_per_out; n_pin++) {
if (aq_ptp->ptp_info.pin_config[n_pin].func == PTP_PF_PEROUT)
break;
}
/* verify the request channel is there */
if (n_pin >= ptp->n_per_out)
return -EINVAL;
aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &start);
div_u64_rem(start, NSEC_PER_SEC, &rest);
period = on ? NSEC_PER_SEC : 0; /* PPS - pulse per second */
start = on ? start - rest + NSEC_PER_SEC *
(rest > 990000000LL ? 2 : 1) : 0;
aq_ptp->ptp_info.pin_config[n_pin].rsv[2] = on ? ptp_perout_pps :
ptp_perout_disabled;
aq_ptp_hw_pin_conf(aq_nic, aq_ptp->ptp_info.pin_config[n_pin].rsv[3],
start, period);
return 0;
}
static int aq_ptp_extts_pin_configure(struct ptp_clock_info *ptp,
u32 n_pin, enum ptp_extts_action action)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
u32 on = (action != ptp_extts_disabled) || aq_ptp->extts_pin_enabled;
aq_pr_verbose(aq_nic, AQ_MSG_PTP, "n_pin = %d action = %d\n", n_pin, action);
if (!aq_ptp->ptp_info.n_ext_ts ||
n_pin >= (aq_ptp->ptp_info.n_ext_ts +
aq_ptp->ptp_info.n_per_out))
return -EINVAL;
if (aq_ptp->ptp_info.pin_config[n_pin].func != PTP_PF_EXTTS) {
netdev_err(aq_nic->ndev, "Pin has invalid function %d instead of %d\n",
aq_ptp->ptp_info.pin_config[n_pin].func,
PTP_PF_EXTTS);
return -EINVAL;
}
if (aq_ptp->a1_ptp) {
cancel_delayed_work_sync(&aq_ptp->poll_sync);
} else {
if (aq_nic->aq_hw_ops->hw_ext_interrupr_en) {
aq_nic->aq_hw_ops->hw_ext_interrupr_en(aq_nic->aq_hw,
on, AQ_HW_PTP_EXT_INT_GPIO0 << n_pin);
}
}
if (action == ptp_extts_disabled && aq_ptp->extts_pin_enabled) {
action = ptp_extts_user;
aq_ptp->ptp_info.pin_config[n_pin].rsv[2] = action;
} else if (action != ptp_extts_user)
aq_ptp->ptp_info.pin_config[n_pin].rsv[2] = action;
else if (aq_ptp->ptp_info.pin_config[n_pin].rsv[2] == ptp_extts_disabled)
aq_ptp->ptp_info.pin_config[n_pin].rsv[2] = action;
((uint64_t *)aq_ptp->ptp_info.pin_config[n_pin].rsv)[0] =
aq_nic->aq_hw_ops->hw_ptp_gpio_get_event(aq_nic->aq_hw,
aq_ptp->ptp_clock_sel, NULL);
netdev_info(aq_nic->ndev, "GPIO %d input event: %s.\n", n_pin,
action == ptp_extts_disabled ? "disabled" :
action == ptp_extts_user ? "requested" :
action == ptp_extts_timesync ? "time sync" :
action == ptp_extts_freqsync ? "freq sync" : "unknown");
aq_nic->aq_hw_ops->hw_extts_gpio_enable(aq_nic->aq_hw,
aq_ptp->ptp_info.pin_config[n_pin].rsv[3],
aq_ptp->ptp_clock_sel, on);
if (aq_ptp->a1_ptp && on && aq_nic->aq_hw->aq_link_status.mbps) {
if (action != ptp_extts_freqsync)
aq_ptp->poll_timeout_ms = POLL_SYNC_TIMER_MS;
/* Here should be request interrupt from firmware */
schedule_delayed_work(&aq_ptp->poll_sync,
msecs_to_jiffies(aq_ptp->poll_timeout_ms));
}
return 0;
}
/* aq_ptp_gpio_feature_enable
* @ptp: the ptp clock structure
* @rq: the requested feature to change
* @on: whether to enable or disable the feature
*/
static int aq_ptp_gpio_feature_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
int pin;
switch (rq->type) {
case PTP_CLK_REQ_EXTTS:
pin = ptp_find_pin(aq_ptp->ptp_clock, PTP_PF_EXTTS,
rq->extts.index);
if (pin < 0) {
netdev_err(aq_ptp->aq_nic->ndev, "There is no EXTTS pin configured");
return -EINVAL;
}
aq_ptp->extts_pin_enabled = !!on;
return aq_ptp_extts_pin_configure(ptp, pin,
on ? ptp_extts_user :
aq_ptp->ptp_info.pin_config[pin].rsv[2]);
case PTP_CLK_REQ_PEROUT:
return aq_ptp_perout_pin_configure(ptp, rq, on);
case PTP_CLK_REQ_PPS:
return aq_ptp_pps_pin_configure(ptp, on);
default:
return -EOPNOTSUPP;
}
return 0;
}
/* Store new PTP time and wait until gpio pin triggered */
int aq_ptp_configure_ext_gpio(struct net_device *ndev,
struct aq_ptp_ext_gpio_event *ext_gpio_event)
{
enum ptp_extts_action action = ptp_extts_disabled;
u32 n_pin = ext_gpio_event->gpio_index;
struct aq_ptp_s *aq_ptp = NULL;
struct aq_nic_s *aq_nic = NULL;
int err = 0;
if (!ndev)
return -EINVAL;
if (ndev->ethtool_ops != &aq_ethtool_ops)
return -EINVAL;
aq_nic = netdev_priv(ndev);
if (!aq_nic)
return -EINVAL;
aq_ptp = aq_nic->aq_ptp;
if (!aq_ptp) {
err = -EOPNOTSUPP;
goto err_exit;
}
if (!aq_ptp->ptp_info.n_ext_ts ||
n_pin >= (aq_ptp->ptp_info.n_ext_ts +
aq_ptp->ptp_info.n_per_out)) {
netdev_info(aq_nic->ndev,
"Not supported, selected EXT TS pin was not advertised");
err = -EOPNOTSUPP;
goto err_exit;
}
if (aq_ptp->a1_ptp) {
//Not required if FW supports
cancel_delayed_work_sync(&aq_ptp->poll_sync);
aq_ptp->poll_timeout_ms = POLL_SYNC_TIMER_MS;
}
switch (ext_gpio_event->action) {
case aq_sync_cntr_set:
netdev_info(aq_nic->ndev, "Enable sync time on event:%llu",
ext_gpio_event->time_ns);
action = ptp_extts_timesync;
aq_ptp->sync_time_value = ext_gpio_event->time_ns;
break;
case 0:
break;
default:
err = -EOPNOTSUPP;
goto err_exit;
}
if (ext_gpio_event->clock_sync_en) {
if (ext_gpio_event->sync_pulse_ms < 50 ||
ext_gpio_event->sync_pulse_ms > MSEC_PER_SEC) {
netdev_err(aq_nic->ndev,
"Sync pulse ms should not be equal less"
" than 50ms or higher than 1s");
err = -EINVAL;
goto err_exit;
}
netdev_info(aq_nic->ndev,
"Enable sync clock with ext signal with period: %u",
ext_gpio_event->sync_pulse_ms);
action = ptp_extts_freqsync;
aq_ptp->pid.ext_sync_period =
(uint64_t)ext_gpio_event->sync_pulse_ms *
NSEC_PER_MSEC;
aq_ptp->pid.multiplier = div_u64(mul_u32_u32(NSEC_PER_SEC,
PTP_DIV_RATIO),
aq_ptp->pid.ext_sync_period);
aq_ptp->pid.divider = PTP_DIV_RATIO;
/* If we need only clock sync poll TS at least
* 3 times per period
*/
aq_ptp->poll_timeout_ms = div_u64(ext_gpio_event->sync_pulse_ms,
3);
}
if (action == ptp_extts_disabled) {
netdev_info(aq_nic->ndev, "Disable sync time/freq on event");
aq_ptp_pid_reset(&aq_ptp->pid);
}
err = aq_ptp_extts_pin_configure(&aq_ptp->ptp_info,