diff --git a/OCR-example/Text-angle-classification-example/Makefile b/OCR-example/Text-angle-classification-example/Makefile deleted file mode 100644 index cf7d375..0000000 --- a/OCR-example/Text-angle-classification-example/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -# Makefile to build demo - -# Setup build environment -BUILD_DIR := build - -ARM_CPU = ARMCM55 -ETHOSU_PATH = /opt/arm/ethosu -CMSIS_PATH ?= ${ETHOSU_PATH}/cmsis -ETHOSU_PLATFORM_PATH ?= ${ETHOSU_PATH}/core_platform -STANDALONE_CRT_PATH := $(abspath $(BUILD_DIR))/runtime -CORSTONE_300_PATH = ${ETHOSU_PLATFORM_PATH}/targets/corstone-300 -PKG_COMPILE_OPTS = -g -Wall -O2 -Wno-incompatible-pointer-types -Wno-format -mcpu=cortex-m55 -mthumb -mfloat-abi=hard -std=gnu99 -CMAKE ?= cmake -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib -PKG_CFLAGS = ${PKG_COMPILE_OPTS} \ - -I${STANDALONE_CRT_PATH}/include \ - -I${STANDALONE_CRT_PATH}/src/runtime/crt/include \ - -I${PWD}/include \ - -I${CORSTONE_300_PATH} \ - -I${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Include/ \ - -I${CMSIS_PATH}/CMSIS/Core/Include \ - -I${CMSIS_PATH}/CMSIS/NN/Include \ - -I${CMSIS_PATH}/CMSIS/DSP/Include \ - -I$(abspath $(BUILD_DIR))/codegen/host/include -CMSIS_NN_CMAKE_FLAGS = -DCMAKE_TOOLCHAIN_FILE=$(abspath $(BUILD_DIR))/../arm-none-eabi-gcc.cmake \ - -DTARGET_CPU=cortex-m55 \ - -DBUILD_CMSIS_NN_FUNCTIONS=YES -PKG_LDFLAGS = -lm -specs=nosys.specs -static -T corstone300.ld - -$(ifeq VERBOSE,1) -QUIET ?= -$(else) -QUIET ?= @ -$(endif) - -DEMO_MAIN = src/demo_bare_metal.c -CODEGEN_SRCS = $(wildcard $(abspath $(BUILD_DIR))/codegen/host/src/*.c) -CODEGEN_OBJS = $(subst .c,.o,$(CODEGEN_SRCS)) -CMSIS_STARTUP_SRCS = $(wildcard ${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Source/*.c) -UART_SRCS = $(wildcard ${CORSTONE_300_PATH}/*.c) - -demo: $(BUILD_DIR)/demo - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/crt_backend_api.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/common/crt_backend_api.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -# Build generated code -$(BUILD_DIR)/libcodegen.a: $(CODEGEN_SRCS) - $(QUIET)cd $(abspath $(BUILD_DIR)/codegen/host/src) && $(CC) -c $(PKG_CFLAGS) $(CODEGEN_SRCS) - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcodegen.a) $(CODEGEN_OBJS) - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcodegen.a) - -# Build CMSIS startup code -${BUILD_DIR}/libcmsis_startup.a: $(CMSIS_STARTUP_SRCS) - $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libcmsis_startup) - $(QUIET)cd $(abspath $(BUILD_DIR)/libcmsis_startup) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcmsis_startup.a) $(abspath $(BUILD_DIR))/libcmsis_startup/*.o - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcmsis_startup.a) - -CMSIS_SHA_FILE=${CMSIS_PATH}/977abe9849781a2e788b02282986480ff4e25ea6.sha -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -else -# Build CMSIS-NN -${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -endif - -# Build demo application -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a ${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -else -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a \ - ${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a \ - ${BUILD_DIR}/cmsis_nn/Source/FullyConnectedFunctions/libCMSISNNFullyConnected.a \ - ${BUILD_DIR}/cmsis_nn/Source/SVDFunctions/libCMSISNNSVDF.a \ - ${BUILD_DIR}/cmsis_nn/Source/ReshapeFunctions/libCMSISNNReshape.a \ - ${BUILD_DIR}/cmsis_nn/Source/ActivationFunctions/libCMSISNNActivation.a \ - ${BUILD_DIR}/cmsis_nn/Source/NNSupportFunctions/libCMSISNNSupport.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConcatenationFunctions/libCMSISNNConcatenation.a \ - ${BUILD_DIR}/cmsis_nn/Source/BasicMathFunctions/libCMSISNNBasicMaths.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConvolutionFunctions/libCMSISNNConvolutions.a \ - ${BUILD_DIR}/cmsis_nn/Source/PoolingFunctions/libCMSISNNPooling.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -endif - -clean: - $(QUIET)rm -rf $(BUILD_DIR)/codegen - -cleanall: - $(QUIET)rm -rf $(BUILD_DIR) - -.SUFFIXES: - -.DEFAULT: demo diff --git a/OCR-example/Text-angle-classification-example/README.md b/OCR-example/Text-angle-classification-example/README.md deleted file mode 100644 index 2873188..0000000 --- a/OCR-example/Text-angle-classification-example/README.md +++ /dev/null @@ -1,51 +0,0 @@ -# Running PaddleOCR text angle classification model on bare metal Arm(R) Cortex(R)-M55 CPU using Arm Virtual Hardware - -This folder contains an example of how to run a PaddleOCR-Cls model on bare -metal [Cortex(R)-M55 CPU](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55) -using [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware). - -## Prepare the operating environment - -If the demo is run in Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by [AWS](https://aws.amazon.com/marketplace/pp/prodview-urbpq7yo5va7g?sr=0-1&ref_=beagle&applicationId=AWSMPContessa)/[AWS China](https://awsmarketplace.amazonaws.cn/marketplace/pp/prodview-2y7nefntbmybu), the following software will be installed through [configure_avh.sh](configure_avh.sh) script. It will install automatically when you run the application through [run_demo.sh](run_demo.sh) script. -You can refer to this [guide](https://arm-software.github.io/AVH/main/examples/html/MicroSpeech.html#amilaunch) to launch an Arm Virtual Hardware AMI instance. - -You can quickly install the development environment through the following script. - -```bash -sudo ./configure_avh.sh -``` - -## Running the demo application - -You can use run_demo script for rapid development. - -With [run_demo.sh](run_demo.sh) to run the demo application, it will: -- Set up running environment by installing the required prerequisites automatically if running in Arm Virtual Hardware Amazon AMI instance(not specify --enable_FVP to 1) -- Download a PaddleOCR text recognition model -- Use tvmc to compile the text recognition model for Cortex(R)-M55 CPU and CMSIS-NN -- Create a C header file inputs.c containing the image data as a C array -- Create a C header file outputs.c containing a C array where the output of inference will be stored -- Build the demo application -- Run the demo application on a Arm Virtual Hardware based on Arm(R) Corstone(TM)-300 software -- The application will report the text on the image and the corresponding score. - -```bash -./run_demo.sh -``` - -## Use your own image - -Please modify line 174 of this file. For example, you can make the following modifications: - -```text -python3 ./convert_image.py path/to/picture -``` - -Model description ------------------ -The example is built on [PP-OCRv3](https://github.com/PaddlePaddle/PaddleOCR/blob/dygraph/doc/doc_ch/PP-OCRv3_introduction.md) English recognition model released by [PaddleOCR](https://github.com/PaddlePaddle/PaddleOCR). - -PP-OCRv3 is the third version of the PP-OCR series model. This series of models has the following features: - - PP-OCRv3: ultra-lightweight OCR system: detection (3.6M) + direction classifier (1.4M) + recognition (12M) = 17.0M - - Support more than 80 kinds of multi-language recognition models, including English, Chinese, French, German, Arabic, Korean, Japanese and so on. For details - - Support vertical text recognition, and long text recognition \ No newline at end of file diff --git a/OCR-example/Text-angle-classification-example/arm-none-eabi-gcc.cmake b/OCR-example/Text-angle-classification-example/arm-none-eabi-gcc.cmake deleted file mode 100644 index 415b313..0000000 --- a/OCR-example/Text-angle-classification-example/arm-none-eabi-gcc.cmake +++ /dev/null @@ -1,79 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -if (__TOOLCHAIN_LOADED) - return() -endif() -set(__TOOLCHAIN_LOADED TRUE) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_SYSTEM_PROCESSOR "cortex-m55" CACHE STRING "Select Arm(R) Cortex(R)-M architecture. (cortex-m0, cortex-m3, cortex-m33, cortex-m4, cortex-m55, cortex-m7, etc)") - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_STANDARD 99) -set(CMAKE_CXX_STANDARD 14) - -# The system processor could for example be set to cortex-m33+nodsp+nofp. -set(__CPU_COMPILE_TARGET ${CMAKE_SYSTEM_PROCESSOR}) -string(REPLACE "+" ";" __CPU_FEATURES ${__CPU_COMPILE_TARGET}) -list(POP_FRONT __CPU_FEATURES CMAKE_SYSTEM_PROCESSOR) - -string(FIND ${__CPU_COMPILE_TARGET} "+" __OFFSET) -if(__OFFSET GREATER_EQUAL 0) - string(SUBSTRING ${__CPU_COMPILE_TARGET} ${__OFFSET} -1 CPU_FEATURES) -endif() - -# Add -mcpu to the compile options to override the -mcpu the CMake toolchain adds -add_compile_options(-mcpu=${__CPU_COMPILE_TARGET}) - -# Set floating point unit -if("${__CPU_COMPILE_TARGET}" MATCHES "\\+fp") - set(FLOAT hard) -elseif("${__CPU_COMPILE_TARGET}" MATCHES "\\+nofp") - set(FLOAT soft) -elseif("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m33" OR - "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55") - set(FLOAT hard) -else() - set(FLOAT soft) -endif() - -add_compile_options(-mfloat-abi=${FLOAT}) -add_link_options(-mfloat-abi=${FLOAT}) - -# Link target -add_link_options(-mcpu=${__CPU_COMPILE_TARGET}) -add_link_options(-Xlinker -Map=output.map) - -# -# Compile options -# -set(cxx_flags "-fno-unwind-tables;-fno-rtti;-fno-exceptions") - -add_compile_options("-Wall;-Wextra;-Wsign-compare;-Wunused;-Wswitch-default;\ --Wdouble-promotion;-Wredundant-decls;-Wshadow;-Wnull-dereference;\ --Wno-format-extra-args;-Wno-unused-function;-Wno-unused-label;\ --Wno-missing-field-initializers;-Wno-return-type;-Wno-format;-Wno-int-conversion" - "$<$:${cxx_flags}>" -) diff --git a/OCR-example/Text-angle-classification-example/configure_avh.sh b/OCR-example/Text-angle-classification-example/configure_avh.sh deleted file mode 100755 index 8042fd8..0000000 --- a/OCR-example/Text-angle-classification-example/configure_avh.sh +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/bash -# Copyright (c) 2022 Arm Limited and Contributors. All rights reserved. -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat < Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00080000; - -/*--------------------- DTCM RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00080000; - -/*----------------------- Data SRAM Configuration ------------------------------ - Data SRAM Configuration - DATA_SRAM Base Address <0x0-0xFFFFFFFF:8> - DATA_SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DATA_SRAM_BASE = 0x01000000; -__DATA_SRAM_SIZE = 0x00200000; - -/*--------------------- Embedded SRAM Configuration ---------------------------- - SRAM Configuration - SRAM Base Address <0x0-0xFFFFFFFF:8> - SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__SRAM_BASE = 0x21000000; -__SRAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00008000; -__HEAP_SIZE = 0x00008000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - DDR Configuration - DDR Base Address <0x0-0xFFFFFFFF:8> - DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DDR_BASE = 0x60000000; -__DDR_SIZE = 0x02000000; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - DATA_SRAM (rwx) : ORIGIN = __DATA_SRAM_BASE, LENGTH = __DATA_SRAM_SIZE - SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE - DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - /* .ddr is placed before .text so that .rodata.tvm is encountered before .rodata* */ - .ddr : - { - . = ALIGN (16); - *(.rodata.tvm) - . = ALIGN (16); - *(.data.tvm); - . = ALIGN(16); - } > DDR - - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > ITCM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - /* Add each additional data section here */ - __copy_table_end__ = .; - } > ITCM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > ITCM - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .sram : - { - . = ALIGN(16); - } > SRAM AT > SRAM - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > DTCM - - .bss.noinit (NOLOAD): - { - . = ALIGN(16); - *(.bss.noinit.*) - . = ALIGN(16); - } > SRAM AT > SRAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DTCM AT > DTCM - - .data_sram : - { - . = ALIGN(16); - } > DATA_SRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - - /* Check if data + stack exceeds DTCM limit */ - ASSERT(__StackLimit >= __bss_end__, "region DTCM overflowed with stack") -} diff --git a/OCR-example/Text-angle-classification-example/requirements.txt b/OCR-example/Text-angle-classification-example/requirements.txt deleted file mode 100644 index d4fa373..0000000 --- a/OCR-example/Text-angle-classification-example/requirements.txt +++ /dev/null @@ -1,4 +0,0 @@ -paddlepaddle -numpy -opencv-python -typing-extensions \ No newline at end of file diff --git a/OCR-example/Text-angle-classification-example/run_demo.sh b/OCR-example/Text-angle-classification-example/run_demo.sh deleted file mode 100755 index b405cff..0000000 --- a/OCR-example/Text-angle-classification-example/run_demo.sh +++ /dev/null @@ -1,188 +0,0 @@ -#!/bin/bash -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat <&2 - show_usage >&2 - exit 1 - fi - ;; - - --ethosu_platform_path) - if [ $# -gt 1 ] - then - export ETHOSU_PLATFORM_PATH="$2" - shift 2 - else - echo 'ERROR: --ethosu_platform_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --fvp_path) - if [ $# -gt 1 ] - then - export PATH="$2/models/Linux64_GCC-6.4:$PATH" - shift 2 - else - echo 'ERROR: --fvp_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --cmake_path) - if [ $# -gt 1 ] - then - export CMAKE="$2" - shift 2 - else - echo 'ERROR: --cmake_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --enable_FVP) - if [ $# -gt 1 ] && [ "$2" == "1" -o "$2" == "0" ]; - then - FVP_enable="$2" - shift 2 - else - echo 'ERROR: --enable_FVP requires a right argument 1 or 0' >&2 - show_usage >&2 - exit 1 - fi - ;; - - -*|--*) - echo "Error: Unknown flag: $1" >&2 - show_usage >&2 - exit 1 - ;; - esac -done - -# Choose running environment: cloud(default) or local environment -Platform="VHT_Corstone_SSE-300_Ethos-U55" -if [ $FVP_enable == "1" ]; then - Platform="FVP_Corstone_SSE-300_Ethos-U55" - echo -e "\e[36mRun application on local Fixed Virtual Platforms (FVPs)\e[0m" -else - if [ ! -d "/opt/arm/" ]; then - sudo ./configure_avh.sh - fi -fi - -# Directories -script_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )" - -# Make build directory -make cleanall -mkdir -p build -cd build - -# Get PaddlePaddle inference model -echo -e "\e[36mDownload PaddlePaddle inference model\e[0m" -wget https://paddleocr.bj.bcebos.com/dygraph_v2.0/ch/ch_ppocr_mobile_v2.0_cls_infer.tar -tar -xf ch_ppocr_mobile_v2.0_cls_infer.tar - -# rename -mv ch_ppocr_mobile_v2.0_cls_infer angle_cls - -# Compile model for Arm(R) Cortex(R)-M55 CPU and CMSIS-NN -# An alternative to using "python3 -m tvm.driver.tvmc" is to call -# "tvmc" directly once TVM has been pip installed. -python3 -m tvm.driver.tvmc compile \ - --target=cmsis-nn,c \ - --target-cmsis-nn-mcpu=cortex-m55 \ - --target-c-mcpu=cortex-m55 \ - --runtime=crt \ - --executor=aot \ - --executor-aot-interface-api=c \ - --executor-aot-unpacked-api=1 \ - --pass-config tir.usmp.enable=1 \ - --pass-config tir.usmp.algorithm=hill_climb \ - --pass-config tir.disable_storage_rewrite=1 \ - --pass-config tir.disable_vectorize=1 angle_cls/inference.pdmodel \ - --output-format=mlf \ - --model-format=paddle \ - --module-name=text_angle_cls \ - --input-shapes "x:[1,3,48,192]" \ - --output=text_angle_cls.tar -tar -xf text_angle_cls.tar - -# Create C header files -cd .. -python3 ./convert_image.py imgs/horizontal.png - -# Build demo executable -cd ${script_dir} -echo ${script_dir} -make - -# Run demo executable on the AVH -$Platform -C cpu0.CFGDTCMSZ=15 \ --C cpu0.CFGITCMSZ=15 -C mps3_board.uart0.out_file=\"-\" -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ --C mps3_board.visualisation.disable-visualisation=1 -C mps3_board.telnetterminal0.start_telnet=0 \ --C mps3_board.telnetterminal1.start_telnet=0 -C mps3_board.telnetterminal2.start_telnet=0 -C mps3_board.telnetterminal5.start_telnet=0 \ -./build/demo --stat diff --git a/OCR-example/Text-recognition-example-m85/Makefile b/OCR-example/Text-recognition-example-m85/Makefile deleted file mode 100644 index 852443f..0000000 --- a/OCR-example/Text-recognition-example-m85/Makefile +++ /dev/null @@ -1,146 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -# Makefile to build demo - -# Setup build environment -BUILD_DIR := build - -ARM_CPU = ARMCM85 -ETHOSU_PATH = /opt/arm/ethosu -CMSIS_PATH ?= ${ETHOSU_PATH}/cmsis -ETHOSU_PLATFORM_PATH ?= ${ETHOSU_PATH}/core_platform -STANDALONE_CRT_PATH := $(abspath $(BUILD_DIR))/runtime -CORSTONE_310_PATH = ${ETHOSU_PLATFORM_PATH}/targets/corstone-310 -PKG_COMPILE_OPTS = -g -Wall -O2 -Wno-incompatible-pointer-types -Wno-format -mcpu=cortex-m85 -mthumb -mfloat-abi=hard -std=gnu99 -CMAKE ?= cmake -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib -PKG_CFLAGS = ${PKG_COMPILE_OPTS} \ - -I${STANDALONE_CRT_PATH}/include \ - -I${STANDALONE_CRT_PATH}/src/runtime/crt/include \ - -I${PWD}/include \ - -I${ETHOSU_PLATFORM_PATH}/drivers/uart/include \ - -I${CORSTONE_310_PATH} \ - -I${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Include/ \ - -I${CMSIS_PATH}/CMSIS/Core/Include \ - -I${CMSIS_PATH}/CMSIS/NN/Include \ - -I${CMSIS_PATH}/CMSIS/DSP/Include \ - -I$(abspath $(BUILD_DIR))/codegen/host/include -CMSIS_NN_CMAKE_FLAGS = -DCMAKE_TOOLCHAIN_FILE=$(abspath $(BUILD_DIR))/../arm-none-eabi-gcc.cmake \ - -DTARGET_CPU=cortex-m85 \ - -DBUILD_CMSIS_NN_FUNCTIONS=YES -PKG_LDFLAGS = -lm -specs=nosys.specs -static -T corstone310.ld - -$(ifeq VERBOSE,1) -QUIET ?= -$(else) -QUIET ?= @ -$(endif) - -DEMO_MAIN = src/demo_bare_metal.c -CODEGEN_SRCS = $(wildcard $(abspath $(BUILD_DIR))/codegen/host/src/*.c) -CODEGEN_OBJS = $(subst .c,.o,$(CODEGEN_SRCS)) -CMSIS_STARTUP_SRCS = $(wildcard ${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Source/*.c) -UART_DRIVER_SRCS = $(wildcard ${ETHOSU_PLATFORM_PATH}/drivers/uart/src/*.c) -UART_SRCS = $(wildcard ${CORSTONE_310_PATH}/*.c) - -demo: $(BUILD_DIR)/demo - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/crt_backend_api.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/common/crt_backend_api.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -${BUILD_DIR}/uart_cmsdk_apb.o: ${ETHOSU_PLATFORM_PATH}/drivers/uart/src/uart_cmsdk_apb.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -# Build generated code -$(BUILD_DIR)/libcodegen.a: $(CODEGEN_SRCS) - $(QUIET)cd $(abspath $(BUILD_DIR)/codegen/host/src) && $(CC) -c $(PKG_CFLAGS) $(CODEGEN_SRCS) - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcodegen.a) $(CODEGEN_OBJS) - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcodegen.a) - -# Build CMSIS startup code -${BUILD_DIR}/libcmsis_startup.a: $(CMSIS_STARTUP_SRCS) - $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libcmsis_startup) - $(QUIET)cd $(abspath $(BUILD_DIR)/libcmsis_startup) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcmsis_startup.a) $(abspath $(BUILD_DIR))/libcmsis_startup/*.o - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcmsis_startup.a) - -#${BUILD_DIR}/libuart_driver.a: $(UART_DRIVER_SRCS) -# $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libuart_driver) -# $(QUIET)cd $(abspath $(BUILD_DIR)/libuart_driver) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ -# $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libuart_driver.a) $(abspath $(BUILD_DIR))/libuart_driver/*.o -# $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libuart_driver.a) - -CMSIS_SHA_FILE=${CMSIS_PATH}/51263182d16c92649a48144ba56c0945f9fce60e.sha -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -else -# Build CMSIS-NN -${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -endif - -# Build demo application -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a ${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a \ - ${BUILD_DIR}/uart_cmsdk_apb.o - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -else -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a \ - ${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a \ - ${BUILD_DIR}/cmsis_nn/Source/FullyConnectedFunctions/libCMSISNNFullyConnected.a \ - ${BUILD_DIR}/cmsis_nn/Source/SVDFunctions/libCMSISNNSVDF.a \ - ${BUILD_DIR}/cmsis_nn/Source/ReshapeFunctions/libCMSISNNReshape.a \ - ${BUILD_DIR}/cmsis_nn/Source/ActivationFunctions/libCMSISNNActivation.a \ - ${BUILD_DIR}/cmsis_nn/Source/NNSupportFunctions/libCMSISNNSupport.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConcatenationFunctions/libCMSISNNConcatenation.a \ - ${BUILD_DIR}/cmsis_nn/Source/BasicMathFunctions/libCMSISNNBasicMaths.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConvolutionFunctions/libCMSISNNConvolutions.a \ - ${BUILD_DIR}/cmsis_nn/Source/PoolingFunctions/libCMSISNNPooling.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -endif - -clean: - $(QUIET)rm -rf $(BUILD_DIR)/codegen - -cleanall: - $(QUIET)rm -rf $(BUILD_DIR) - -.SUFFIXES: - -.DEFAULT: demo \ No newline at end of file diff --git a/OCR-example/Text-recognition-example-m85/arm-none-eabi-gcc.cmake b/OCR-example/Text-recognition-example-m85/arm-none-eabi-gcc.cmake deleted file mode 100644 index 415b313..0000000 --- a/OCR-example/Text-recognition-example-m85/arm-none-eabi-gcc.cmake +++ /dev/null @@ -1,79 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -if (__TOOLCHAIN_LOADED) - return() -endif() -set(__TOOLCHAIN_LOADED TRUE) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_SYSTEM_PROCESSOR "cortex-m55" CACHE STRING "Select Arm(R) Cortex(R)-M architecture. (cortex-m0, cortex-m3, cortex-m33, cortex-m4, cortex-m55, cortex-m7, etc)") - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_STANDARD 99) -set(CMAKE_CXX_STANDARD 14) - -# The system processor could for example be set to cortex-m33+nodsp+nofp. -set(__CPU_COMPILE_TARGET ${CMAKE_SYSTEM_PROCESSOR}) -string(REPLACE "+" ";" __CPU_FEATURES ${__CPU_COMPILE_TARGET}) -list(POP_FRONT __CPU_FEATURES CMAKE_SYSTEM_PROCESSOR) - -string(FIND ${__CPU_COMPILE_TARGET} "+" __OFFSET) -if(__OFFSET GREATER_EQUAL 0) - string(SUBSTRING ${__CPU_COMPILE_TARGET} ${__OFFSET} -1 CPU_FEATURES) -endif() - -# Add -mcpu to the compile options to override the -mcpu the CMake toolchain adds -add_compile_options(-mcpu=${__CPU_COMPILE_TARGET}) - -# Set floating point unit -if("${__CPU_COMPILE_TARGET}" MATCHES "\\+fp") - set(FLOAT hard) -elseif("${__CPU_COMPILE_TARGET}" MATCHES "\\+nofp") - set(FLOAT soft) -elseif("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m33" OR - "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55") - set(FLOAT hard) -else() - set(FLOAT soft) -endif() - -add_compile_options(-mfloat-abi=${FLOAT}) -add_link_options(-mfloat-abi=${FLOAT}) - -# Link target -add_link_options(-mcpu=${__CPU_COMPILE_TARGET}) -add_link_options(-Xlinker -Map=output.map) - -# -# Compile options -# -set(cxx_flags "-fno-unwind-tables;-fno-rtti;-fno-exceptions") - -add_compile_options("-Wall;-Wextra;-Wsign-compare;-Wunused;-Wswitch-default;\ --Wdouble-promotion;-Wredundant-decls;-Wshadow;-Wnull-dereference;\ --Wno-format-extra-args;-Wno-unused-function;-Wno-unused-label;\ --Wno-missing-field-initializers;-Wno-return-type;-Wno-format;-Wno-int-conversion" - "$<$:${cxx_flags}>" -) diff --git a/OCR-example/Text-recognition-example-m85/configure_avh.sh b/OCR-example/Text-recognition-example-m85/configure_avh.sh deleted file mode 100755 index 0ef0a8e..0000000 --- a/OCR-example/Text-recognition-example-m85/configure_avh.sh +++ /dev/null @@ -1,85 +0,0 @@ -#!/bin/bash -# Copyright (c) 2022 Arm Limited and Contributors. All rights reserved. -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat < imgW: - resized_w = imgW - else: - resized_w = int(math.ceil(imgH * ratio)) - resized_image = cv2.resize(img, (resized_w, imgH)) - resized_image = resized_image.astype('float32') - if image_shape[0] == 1: - resized_image = resized_image / 255 - resized_image = resized_image[np.newaxis, :] - else: - resized_image = resized_image.transpose((2, 0, 1)) / 255 - resized_image -= 0.5 - resized_image /= 0.5 - padding_im = np.zeros((imgC, imgH, imgW), dtype=np.float32) - padding_im[:, :, 0:resized_w] = resized_image - return padding_im - - -def create_header_file(name, tensor_name, tensor_data, output_path): - """ - This function generates a header file containing the data from the numpy array provided. - """ - file_path = pathlib.Path(f"{output_path}/" + name).resolve() - # Create header file with npy_data as a C array - raw_path = file_path.with_suffix(".h").resolve() - with open(raw_path, "w") as header_file: - header_file.write( - "\n" - + f"const size_t {tensor_name}_len = {tensor_data.size};\n" - + f'__attribute__((section(".data.tvm"), aligned(16))) float {tensor_name}[] = ' - ) - - header_file.write("{") - for i in np.ndindex(tensor_data.shape): - header_file.write(f"{tensor_data[i]}, ") - header_file.write("};\n\n") - - -def create_headers(image_name): - """ - This function generates C header files for the input and output arrays required to run inferences - """ - img_path = os.path.join("./", f"{image_name}") - - # Resize image to 32x320 - img = cv2.imread(img_path) - img = resize_norm_img(img, [3,32,320]) - img_data = img.astype("float32") - - # # Add the batch dimension, as we are expecting 4-dimensional input: NCHW. - img_data = np.expand_dims(img_data, axis=0) - - # Create input header file - create_header_file("inputs", "input", img_data, "include") - # Create output header file - output_data = np.zeros([7760], np.float) - create_header_file( - "outputs", - "output", - output_data, - "include", - ) - - -if __name__ == "__main__": - create_headers(sys.argv[1]) diff --git a/OCR-example/Text-recognition-example-m85/corstone310.ld b/OCR-example/Text-recognition-example-m85/corstone310.ld deleted file mode 100644 index e0fb348..0000000 --- a/OCR-example/Text-recognition-example-m85/corstone310.ld +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -/*------------------ Reference System Memories ------------- - +===================+============+=======+============+============+ - | Memory | Address | Size | CPU Access | NPU Access | - +===================+============+=======+============+============+ - | ITCM | 0x00000000 | 32kiB | Yes (RO) | No | - +-------------------+------------+-------+------------+------------+ - | DTCM | 0x20000000 | 32kiB | Yes (R/W) | No | - +-------------------+------------+-------+------------+------------+ - | SSE-300 SRAM | 0x21000000 | 4MiB | Yes (R/W) | Yes (R/W) | - +-------------------+------------+-------+------------+------------+ - | Data SRAM | 0x01000000 | 2MiB | Yes (R/W) | Yes (R/W) | - +-------------------+------------+-------+------------+------------+ - | DDR | 0x60000000 |256MiB | Yes (R/W) | Yes (R/W) | - +-------------------+------------+-------+------------+------------+ */ - -/*---------------------- ITCM Configuration ---------------------------------- - Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00008000; - -/*--------------------- DTCM RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00008000; - -/*----------------------- Data SRAM Configuration ------------------------------ - Data SRAM Configuration - DATA_SRAM Base Address <0x0-0xFFFFFFFF:8> - DATA_SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DATA_SRAM_BASE = 0x01000000; -__DATA_SRAM_SIZE = 0x00200000; - -/*--------------------- Embedded SRAM Configuration ---------------------------- - SRAM Configuration - SRAM Base Address <0x0-0xFFFFFFFF:8> - SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__SRAM_BASE = 0x21000000; -__SRAM_SIZE = 0x00400000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00008000; -__HEAP_SIZE = 0x00008000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - DDR Configuration - DDR Base Address <0x0-0xFFFFFFFF:8> - DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DDR_BASE = 0x60000000; -__DDR_SIZE = 0x10000000; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - DATA_SRAM (rwx) : ORIGIN = __DATA_SRAM_BASE, LENGTH = __DATA_SRAM_SIZE - SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE - DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - /* .ddr is placed before .text so that .rodata.tvm is encountered before .rodata* */ - .ddr : - { - . = ALIGN (16); - *(.rodata.tvm) - . = ALIGN (16); - *(.data.tvm); - . = ALIGN(16); - } > DDR - - .text : - { - KEEP(*(.vectors)) - *(.text*) - *startup_ARMCM85.c.obj (.text*) - *system_ARMCM85.c.obj (.text*) -/* *target.cpp.obj (.text*)*/ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > DATA_SRAM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - /* Add each additional data section here */ - __copy_table_end__ = .; - } > ITCM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > ITCM - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .sram : - { - . = ALIGN(16); - } > SRAM AT > SRAM - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > DATA_SRAM - - .bss.noinit (NOLOAD): - { - . = ALIGN(16); - *(.bss.noinit.*) - . = ALIGN(16); - } > DDR AT > DDR - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DATA_SRAM AT > DATA_SRAM - - .data_sram : - { - . = ALIGN(16); - } > DATA_SRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - - /* Check if data + stack exceeds DTCM limit */ - ASSERT(__StackLimit >= __bss_end__, "region DTCM overflowed with stack") -} \ No newline at end of file diff --git a/OCR-example/Text-recognition-example-m85/include/uart_config.h b/OCR-example/Text-recognition-example-m85/include/uart_config.h deleted file mode 100644 index 5c3bb2e..0000000 --- a/OCR-example/Text-recognition-example-m85/include/uart_config.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#pragma once - -#define UART0_BASE 0x49303000 -#define UART0_BAUDRATE 115200 -#define SYSTEM_CORE_CLOCK 25000000 \ No newline at end of file diff --git a/OCR-example/Text-recognition-example-m85/requirements.txt b/OCR-example/Text-recognition-example-m85/requirements.txt deleted file mode 100644 index d4fa373..0000000 --- a/OCR-example/Text-recognition-example-m85/requirements.txt +++ /dev/null @@ -1,4 +0,0 @@ -paddlepaddle -numpy -opencv-python -typing-extensions \ No newline at end of file diff --git a/OCR-example/Text-recognition-example-m85/run_demo.sh b/OCR-example/Text-recognition-example-m85/run_demo.sh deleted file mode 100755 index 5a2dccf..0000000 --- a/OCR-example/Text-recognition-example-m85/run_demo.sh +++ /dev/null @@ -1,179 +0,0 @@ -#!/bin/bash -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat <&2 - show_usage >&2 - exit 1 - fi - ;; - - --ethosu_platform_path) - if [ $# -gt 1 ] - then - export ETHOSU_PLATFORM_PATH="$2" - shift 2 - else - echo 'ERROR: --ethosu_platform_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --fvp_path) - if [ $# -gt 1 ] - then - export PATH="$2/models/Linux64_GCC-6.4:$PATH" - shift 2 - else - echo 'ERROR: --fvp_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --cmake_path) - if [ $# -gt 1 ] - then - export CMAKE="$2" - shift 2 - else - echo 'ERROR: --cmake_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --enable_FVP) - if [ $# -gt 1 ] && [ "$2" == "1" -o "$2" == "0" ]; - then - FVP_enable="$2" - shift 2 - else - echo 'ERROR: --enable_FVP requires a right argument 1 or 0' >&2 - show_usage >&2 - exit 1 - fi - ;; - - -*|--*) - echo "Error: Unknown flag: $1" >&2 - show_usage >&2 - exit 1 - ;; - esac -done - -# Choose running environment: cloud(default) or local environment -Platform="VHT_Corstone_SSE-310" -if [ ! -d "/opt/arm/" ]; then - sudo ./configure_avh.sh -fi - -# Directories -script_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )" - -# Make build directory -make cleanall -mkdir -p build -cd build - -# Get PaddlePaddle inference model -echo -e "\e[36mDownload PaddlePaddle inference model\e[0m" -wget https://paddleocr.bj.bcebos.com/tvm/ocr_en.tar -tar -xf ocr_en.tar - -# Compile model for Arm(R) Cortex(R)-M55 CPU and CMSIS-NN -# An alternative to using "python3 -m tvm.driver.tvmc" is to call -# "tvmc" directly once TVM has been pip installed. -python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ - --target-cmsis-nn-mcpu=cortex-m85 \ - --target-c-mcpu=cortex-m85 \ - --runtime=crt \ - --executor=aot \ - --executor-aot-interface-api=c \ - --executor-aot-unpacked-api=1 \ - --pass-config tir.usmp.enable=1 \ - --pass-config tir.usmp.algorithm=hill_climb \ - --pass-config tir.disable_storage_rewrite=1 \ - --pass-config tir.disable_vectorize=1 ocr_en/inference.pdmodel \ - --output-format=mlf \ - --model-format=paddle \ - --module-name=rec \ - --input-shapes x:[1,3,32,320] \ - --output=rec.tar -tar -xf rec.tar - -# Create C header files -cd .. -python3 ./convert_image.py imgs_words_en/word_116.png - -# Build demo executable -cd ${script_dir} -echo ${script_dir} -make - -# Run demo executable on the AVH -$Platform -C cpu0.CFGDTCMSZ=15 \ --C cpu0.CFGITCMSZ=15 -C mps3_board.uart0.out_file=\"-\" -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ --C mps3_board.visualisation.disable-visualisation=1 -C mps3_board.telnetterminal0.start_telnet=0 \ --C mps3_board.telnetterminal1.start_telnet=0 -C mps3_board.telnetterminal2.start_telnet=0 -C mps3_board.telnetterminal5.start_telnet=0 \ -./build/demo --stat diff --git a/OCR-example/Text-recognition-example-m85/src/demo_bare_metal.c b/OCR-example/Text-recognition-example-m85/src/demo_bare_metal.c deleted file mode 100644 index 921c18e..0000000 --- a/OCR-example/Text-recognition-example-m85/src/demo_bare_metal.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include - -// Header files generated by convert_image.py -#include "inputs.h" -#include "outputs.h" - -extern void UartStdOutInit(void); - -int main(int argc, char** argv) { - UartStdOutInit(); - char dict[]={"#0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~!\"#$%&'()*+,-./ "}; - int char_dict_nums = 97; - printf("Starting ocr rec inference\n"); - struct tvmgen_rec_outputs rec_outputs = { - .output = output, - }; - struct tvmgen_rec_inputs rec_inputs = { - .x = input, - }; - - tvmgen_rec_run(&rec_inputs, &rec_outputs); - - // post process - int char_nums = output_len / char_dict_nums; - - int last_index = 0; - float score = 0.f; - int count = 0; - - printf("text: "); - for (int i = 0; i < char_nums; i++) { - int argmax_idx = 0; - float max_value = 0.0f; - for (int j = 0; j < char_dict_nums; j++){ - if (output[i * char_dict_nums + j] > max_value){ - max_value = output[i * char_dict_nums + j]; - argmax_idx = j; - } - } - if (argmax_idx > 0 && (!(i > 0 && argmax_idx == last_index))) { - score += max_value; - count += 1; - // printf("%d，%f，%c\n", argmax_idx, max_value, dict[argmax_idx]); - printf("%c", dict[argmax_idx]); - } - last_index = argmax_idx; - } - score /= count; - printf(", score: %f\n", score); - - // The FVP will shut down when it receives "EXITTHESIM" on the UART - printf("EXITTHESIM\n"); - while (1 == 1) - ; - return 0; -} diff --git a/OCR-example/Text-recognition-example/Makefile b/OCR-example/Text-recognition-example/Makefile deleted file mode 100644 index cf7d375..0000000 --- a/OCR-example/Text-recognition-example/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -# Makefile to build demo - -# Setup build environment -BUILD_DIR := build - -ARM_CPU = ARMCM55 -ETHOSU_PATH = /opt/arm/ethosu -CMSIS_PATH ?= ${ETHOSU_PATH}/cmsis -ETHOSU_PLATFORM_PATH ?= ${ETHOSU_PATH}/core_platform -STANDALONE_CRT_PATH := $(abspath $(BUILD_DIR))/runtime -CORSTONE_300_PATH = ${ETHOSU_PLATFORM_PATH}/targets/corstone-300 -PKG_COMPILE_OPTS = -g -Wall -O2 -Wno-incompatible-pointer-types -Wno-format -mcpu=cortex-m55 -mthumb -mfloat-abi=hard -std=gnu99 -CMAKE ?= cmake -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib -PKG_CFLAGS = ${PKG_COMPILE_OPTS} \ - -I${STANDALONE_CRT_PATH}/include \ - -I${STANDALONE_CRT_PATH}/src/runtime/crt/include \ - -I${PWD}/include \ - -I${CORSTONE_300_PATH} \ - -I${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Include/ \ - -I${CMSIS_PATH}/CMSIS/Core/Include \ - -I${CMSIS_PATH}/CMSIS/NN/Include \ - -I${CMSIS_PATH}/CMSIS/DSP/Include \ - -I$(abspath $(BUILD_DIR))/codegen/host/include -CMSIS_NN_CMAKE_FLAGS = -DCMAKE_TOOLCHAIN_FILE=$(abspath $(BUILD_DIR))/../arm-none-eabi-gcc.cmake \ - -DTARGET_CPU=cortex-m55 \ - -DBUILD_CMSIS_NN_FUNCTIONS=YES -PKG_LDFLAGS = -lm -specs=nosys.specs -static -T corstone300.ld - -$(ifeq VERBOSE,1) -QUIET ?= -$(else) -QUIET ?= @ -$(endif) - -DEMO_MAIN = src/demo_bare_metal.c -CODEGEN_SRCS = $(wildcard $(abspath $(BUILD_DIR))/codegen/host/src/*.c) -CODEGEN_OBJS = $(subst .c,.o,$(CODEGEN_SRCS)) -CMSIS_STARTUP_SRCS = $(wildcard ${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Source/*.c) -UART_SRCS = $(wildcard ${CORSTONE_300_PATH}/*.c) - -demo: $(BUILD_DIR)/demo - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/crt_backend_api.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/common/crt_backend_api.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -# Build generated code -$(BUILD_DIR)/libcodegen.a: $(CODEGEN_SRCS) - $(QUIET)cd $(abspath $(BUILD_DIR)/codegen/host/src) && $(CC) -c $(PKG_CFLAGS) $(CODEGEN_SRCS) - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcodegen.a) $(CODEGEN_OBJS) - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcodegen.a) - -# Build CMSIS startup code -${BUILD_DIR}/libcmsis_startup.a: $(CMSIS_STARTUP_SRCS) - $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libcmsis_startup) - $(QUIET)cd $(abspath $(BUILD_DIR)/libcmsis_startup) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcmsis_startup.a) $(abspath $(BUILD_DIR))/libcmsis_startup/*.o - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcmsis_startup.a) - -CMSIS_SHA_FILE=${CMSIS_PATH}/977abe9849781a2e788b02282986480ff4e25ea6.sha -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -else -# Build CMSIS-NN -${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -endif - -# Build demo application -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a ${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -else -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a \ - ${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a \ - ${BUILD_DIR}/cmsis_nn/Source/FullyConnectedFunctions/libCMSISNNFullyConnected.a \ - ${BUILD_DIR}/cmsis_nn/Source/SVDFunctions/libCMSISNNSVDF.a \ - ${BUILD_DIR}/cmsis_nn/Source/ReshapeFunctions/libCMSISNNReshape.a \ - ${BUILD_DIR}/cmsis_nn/Source/ActivationFunctions/libCMSISNNActivation.a \ - ${BUILD_DIR}/cmsis_nn/Source/NNSupportFunctions/libCMSISNNSupport.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConcatenationFunctions/libCMSISNNConcatenation.a \ - ${BUILD_DIR}/cmsis_nn/Source/BasicMathFunctions/libCMSISNNBasicMaths.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConvolutionFunctions/libCMSISNNConvolutions.a \ - ${BUILD_DIR}/cmsis_nn/Source/PoolingFunctions/libCMSISNNPooling.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -endif - -clean: - $(QUIET)rm -rf $(BUILD_DIR)/codegen - -cleanall: - $(QUIET)rm -rf $(BUILD_DIR) - -.SUFFIXES: - -.DEFAULT: demo diff --git a/OCR-example/Text-recognition-example/README.md b/OCR-example/Text-recognition-example/README.md deleted file mode 100644 index 5b8415e..0000000 --- a/OCR-example/Text-recognition-example/README.md +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - -Running PaddleOCR text recognition model on bare metal Arm(R) Cortex(R)-M55 CPU using Arm Virtual Hardware -====================================================================== - -This folder contains an example of how to run a PaddleOCR model on bare metal [Cortex(R)-M55 CPU](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55) using [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware). - - -Running environment and prerequisites -------------- -Case 1: If the demo is run in Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by [AWS](https://aws.amazon.com/marketplace/pp/prodview-urbpq7yo5va7g?sr=0-1&ref_=beagle&applicationId=AWSMPContessa)/[AWS China](https://awsmarketplace.amazonaws.cn/marketplace/pp/prodview-2y7nefntbmybu), the following software will be installed through [configure_avh.sh](configure_avh.sh) script. It will install automatically when you run the application through [run_demo.sh](run_demo.sh) script. -You can refer to this [guide](https://arm-software.github.io/AVH/main/examples/html/MicroSpeech.html#amilaunch) to launch an Arm Virtual Hardware AMI instance. - -Case 2: If the demo is run in the [ci_cpu Docker container](https://github.com/apache/tvm/blob/main/docker/Dockerfile.ci_cpu) provided with [TVM](https://github.com/apache/tvm), then the following software will already be installed. - -Case 3: If the demo is not run in the ci_cpu Docker container, then you will need the following: -- Software required to build and run the demo (These can all be installed by running - tvm/docker/install/ubuntu_install_ethosu_driver_stack.sh.) - - [Fixed Virtual Platform (FVP) based on Arm(R) Corstone(TM)-300 software](https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps) - - [cmake 3.19.5](https://github.com/Kitware/CMake/releases/) - - [GCC toolchain from Arm(R)](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2) - - [Arm(R) Ethos(TM)-U NPU driver stack](https://review.mlplatform.org) - - [CMSIS](https://github.com/ARM-software/CMSIS_5) -- The python libraries listed in the requirements.txt of this directory - - These can be installed by running the following from the current directory: - ```bash - pip install -r ./requirements.txt - ``` - -In case2 and case3: - -You will need to update your PATH environment variable to include the path to cmake 3.19.5 and the FVP. -For example if you've installed these in ```/opt/arm``` , then you would do the following: -```bash -export PATH=/opt/arm/FVP_Corstone_SSE-300/models/Linux64_GCC-6.4:/opt/arm/cmake/bin:$PATH -``` - -You will also need TVM which can either be: - - Installed from TLCPack(see [TLCPack](https://tlcpack.ai/)) - - Built from source (see [Install from Source](https://tvm.apache.org/docs/install/from_source.html)) - - When building from source, the following need to be set in config.cmake: - - set(USE_CMSISNN ON) - - set(USE_MICRO ON) - - set(USE_LLVM ON) - - -Running the demo application ----------------------------- -Type the following command to run the bare metal text recognition application ([src/demo_bare_metal.c](src/demo_bare_metal.c)): - -```bash -./run_demo.sh -``` - -If you are not able to use Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by AWS/AWS China, specify argument --enable_FVP to 1 to make the application run on local Fixed Virtual Platforms (FVPs) executables. - -```bash -./run_demo.sh --enable_FVP 1 -``` - -If the Ethos(TM)-U platform and/or CMSIS have not been installed in /opt/arm/ethosu then -the locations for these can be specified as arguments to run_demo.sh, for example: - -```bash -./run_demo.sh --cmsis_path /home/tvm-user/cmsis \ ---ethosu_platform_path /home/tvm-user/ethosu/core_platform -``` - -With [run_demo.sh](run_demo.sh) to run the demo application, it will: -- Set up running environment by installing the required prerequisites automatically if running in Arm Virtual Hardware Amazon AMI instance(not specify --enable_FVP to 1) -- Download a PaddleOCR text recognition model -- Use tvmc to compile the text recognition model for Cortex(R)-M55 CPU and CMSIS-NN -- Create a C header file inputs.c containing the image data as a C array -- Create a C header file outputs.c containing a C array where the output of inference will be stored -- Build the demo application -- Run the demo application on a Arm Virtual Hardware based on Arm(R) Corstone(TM)-300 software -- The application will report the text on the image and the corresponding score. - -Using your own image --------------------- -The create_image.py script takes a single argument on the command line which is the path of the -image to be converted into an array of bytes for consumption by the model. - -The demo can be modified to use an image of your choice by changing the following line in run_demo.sh - -```bash -python3 ./convert_image.py path/to/image -``` - -Model description ------------------ -The example is built on [PP-OCRv3](https://github.com/PaddlePaddle/PaddleOCR/blob/dygraph/doc/doc_ch/PP-OCRv3_introduction.md) English recognition model released by [PaddleOCR](https://github.com/PaddlePaddle/PaddleOCR). Since Arm(R) Cortex(R)-M55 CPU does not support rnn operator, we delete the unsupported operator based on the PP-OCRv3 text recognition model to obtain the current 2.7M English recognition model. - -PP-OCRv3 is the third version of the PP-OCR series model. This series of models has the following features: - - PP-OCRv3: ultra-lightweight OCR system: detection (3.6M) + direction classifier (1.4M) + recognition (12M) = 17.0M - - Support more than 80 kinds of multi-language recognition models, including English, Chinese, French, German, Arabic, Korean, Japanese and so on. For details - - Support vertical text recognition, and long text recognition - - diff --git a/OCR-example/Text-recognition-example/arm-none-eabi-gcc.cmake b/OCR-example/Text-recognition-example/arm-none-eabi-gcc.cmake deleted file mode 100644 index 415b313..0000000 --- a/OCR-example/Text-recognition-example/arm-none-eabi-gcc.cmake +++ /dev/null @@ -1,79 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -if (__TOOLCHAIN_LOADED) - return() -endif() -set(__TOOLCHAIN_LOADED TRUE) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_SYSTEM_PROCESSOR "cortex-m55" CACHE STRING "Select Arm(R) Cortex(R)-M architecture. (cortex-m0, cortex-m3, cortex-m33, cortex-m4, cortex-m55, cortex-m7, etc)") - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_STANDARD 99) -set(CMAKE_CXX_STANDARD 14) - -# The system processor could for example be set to cortex-m33+nodsp+nofp. -set(__CPU_COMPILE_TARGET ${CMAKE_SYSTEM_PROCESSOR}) -string(REPLACE "+" ";" __CPU_FEATURES ${__CPU_COMPILE_TARGET}) -list(POP_FRONT __CPU_FEATURES CMAKE_SYSTEM_PROCESSOR) - -string(FIND ${__CPU_COMPILE_TARGET} "+" __OFFSET) -if(__OFFSET GREATER_EQUAL 0) - string(SUBSTRING ${__CPU_COMPILE_TARGET} ${__OFFSET} -1 CPU_FEATURES) -endif() - -# Add -mcpu to the compile options to override the -mcpu the CMake toolchain adds -add_compile_options(-mcpu=${__CPU_COMPILE_TARGET}) - -# Set floating point unit -if("${__CPU_COMPILE_TARGET}" MATCHES "\\+fp") - set(FLOAT hard) -elseif("${__CPU_COMPILE_TARGET}" MATCHES "\\+nofp") - set(FLOAT soft) -elseif("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m33" OR - "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55") - set(FLOAT hard) -else() - set(FLOAT soft) -endif() - -add_compile_options(-mfloat-abi=${FLOAT}) -add_link_options(-mfloat-abi=${FLOAT}) - -# Link target -add_link_options(-mcpu=${__CPU_COMPILE_TARGET}) -add_link_options(-Xlinker -Map=output.map) - -# -# Compile options -# -set(cxx_flags "-fno-unwind-tables;-fno-rtti;-fno-exceptions") - -add_compile_options("-Wall;-Wextra;-Wsign-compare;-Wunused;-Wswitch-default;\ --Wdouble-promotion;-Wredundant-decls;-Wshadow;-Wnull-dereference;\ --Wno-format-extra-args;-Wno-unused-function;-Wno-unused-label;\ --Wno-missing-field-initializers;-Wno-return-type;-Wno-format;-Wno-int-conversion" - "$<$:${cxx_flags}>" -) diff --git a/OCR-example/Text-recognition-example/configure_avh.sh b/OCR-example/Text-recognition-example/configure_avh.sh deleted file mode 100755 index 8042fd8..0000000 --- a/OCR-example/Text-recognition-example/configure_avh.sh +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/bash -# Copyright (c) 2022 Arm Limited and Contributors. All rights reserved. -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat < Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00080000; - -/*--------------------- DTCM RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00080000; - -/*----------------------- Data SRAM Configuration ------------------------------ - Data SRAM Configuration - DATA_SRAM Base Address <0x0-0xFFFFFFFF:8> - DATA_SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DATA_SRAM_BASE = 0x01000000; -__DATA_SRAM_SIZE = 0x00200000; - -/*--------------------- Embedded SRAM Configuration ---------------------------- - SRAM Configuration - SRAM Base Address <0x0-0xFFFFFFFF:8> - SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__SRAM_BASE = 0x21000000; -__SRAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00008000; -__HEAP_SIZE = 0x00008000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - DDR Configuration - DDR Base Address <0x0-0xFFFFFFFF:8> - DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DDR_BASE = 0x60000000; -__DDR_SIZE = 0x02000000; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - DATA_SRAM (rwx) : ORIGIN = __DATA_SRAM_BASE, LENGTH = __DATA_SRAM_SIZE - SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE - DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - /* .ddr is placed before .text so that .rodata.tvm is encountered before .rodata* */ - .ddr : - { - . = ALIGN (16); - *(.rodata.tvm) - . = ALIGN (16); - *(.data.tvm); - . = ALIGN(16); - } > DDR - - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > ITCM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - /* Add each additional data section here */ - __copy_table_end__ = .; - } > ITCM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > ITCM - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .sram : - { - . = ALIGN(16); - } > SRAM AT > SRAM - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > DTCM - - .bss.noinit (NOLOAD): - { - . = ALIGN(16); - *(.bss.noinit.*) - . = ALIGN(16); - } > SRAM AT > SRAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DTCM AT > DTCM - - .data_sram : - { - . = ALIGN(16); - } > DATA_SRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - - /* Check if data + stack exceeds DTCM limit */ - ASSERT(__StackLimit >= __bss_end__, "region DTCM overflowed with stack") -} diff --git a/OCR-example/Text-recognition-example/imgs_words_en/README.md b/OCR-example/Text-recognition-example/imgs_words_en/README.md deleted file mode 100644 index f55f8e2..0000000 --- a/OCR-example/Text-recognition-example/imgs_words_en/README.md +++ /dev/null @@ -1,5 +0,0 @@ -# About Dataset -* The test image [word_116.png](word_116.png) / [word_10.png](word_10.png) for this example comes from the dataset `Test Set Word Images` -for [Task 4.3 Word Recognition](https://rrc.cvc.uab.es/?ch=4&com=tasks) of [Incidental Scene Text](https://rrc.cvc.uab.es/?ch=4&com=introduction) challenge from [Robust Reading Competition](https://rrc.cvc.uab.es/) (RR-2015) in 13th International Conference on Document Analysis and Recognition ([ICDAR 2015](https://iapr.org/archives/icdar2015/index.html)).It is used for verifying the inference results of PP-OCRv3 English recognition model running on AVH Corstone 300 platform with Cortex-M55 CPU. -* The `Test Set Word Images` dataset provides 2077 cut out word images corresponding to the axis oriented bounding boxes of the words are provided along with a single text file with the relative coordinates of the bounding shape within each word image. -* The "Incidental Scene Text" dataset and corresponding annotations are licensed under a [Creative Commons Attribution 4.0 License](https://rrc.cvc.uab.es/?com=downloads&action=download&ch=4&f=aHR0cHM6Ly9jcmVhdGl2ZWNvbW1vbnMub3JnL2xpY2Vuc2VzL2J5LzQuMC8=). \ No newline at end of file diff --git a/OCR-example/Text-recognition-example/imgs_words_en/word_10.png b/OCR-example/Text-recognition-example/imgs_words_en/word_10.png deleted file mode 100644 index 07370f7..0000000 Binary files a/OCR-example/Text-recognition-example/imgs_words_en/word_10.png and /dev/null differ diff --git a/OCR-example/Text-recognition-example/imgs_words_en/word_116.png b/OCR-example/Text-recognition-example/imgs_words_en/word_116.png deleted file mode 100644 index fd000ff..0000000 Binary files a/OCR-example/Text-recognition-example/imgs_words_en/word_116.png and /dev/null differ diff --git a/OCR-example/Text-recognition-example/requirements.txt b/OCR-example/Text-recognition-example/requirements.txt deleted file mode 100644 index d4fa373..0000000 --- a/OCR-example/Text-recognition-example/requirements.txt +++ /dev/null @@ -1,4 +0,0 @@ -paddlepaddle -numpy -opencv-python -typing-extensions \ No newline at end of file diff --git a/OCR-example/Text-recognition-example/run_demo.sh b/OCR-example/Text-recognition-example/run_demo.sh deleted file mode 100755 index 63de91a..0000000 --- a/OCR-example/Text-recognition-example/run_demo.sh +++ /dev/null @@ -1,184 +0,0 @@ -#!/bin/bash -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat <&2 - show_usage >&2 - exit 1 - fi - ;; - - --ethosu_platform_path) - if [ $# -gt 1 ] - then - export ETHOSU_PLATFORM_PATH="$2" - shift 2 - else - echo 'ERROR: --ethosu_platform_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --fvp_path) - if [ $# -gt 1 ] - then - export PATH="$2/models/Linux64_GCC-6.4:$PATH" - shift 2 - else - echo 'ERROR: --fvp_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --cmake_path) - if [ $# -gt 1 ] - then - export CMAKE="$2" - shift 2 - else - echo 'ERROR: --cmake_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --enable_FVP) - if [ $# -gt 1 ] && [ "$2" == "1" -o "$2" == "0" ]; - then - FVP_enable="$2" - shift 2 - else - echo 'ERROR: --enable_FVP requires a right argument 1 or 0' >&2 - show_usage >&2 - exit 1 - fi - ;; - - -*|--*) - echo "Error: Unknown flag: $1" >&2 - show_usage >&2 - exit 1 - ;; - esac -done - -# Choose running environment: cloud(default) or local environment -Platform="VHT_Corstone_SSE-300_Ethos-U55" -if [ $FVP_enable == "1" ]; then - Platform="FVP_Corstone_SSE-300_Ethos-U55" - echo -e "\e[36mRun application on local Fixed Virtual Platforms (FVPs)\e[0m" -else - if [ ! -d "/opt/arm/" ]; then - sudo ./configure_avh.sh - fi -fi - -# Directories -script_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )" - -# Make build directory -make cleanall -mkdir -p build -cd build - -# Get PaddlePaddle inference model -echo -e "\e[36mDownload PaddlePaddle inference model\e[0m" -wget https://paddleocr.bj.bcebos.com/tvm/ocr_en.tar -tar -xf ocr_en.tar - -# Compile model for Arm(R) Cortex(R)-M55 CPU and CMSIS-NN -# An alternative to using "python3 -m tvm.driver.tvmc" is to call -# "tvmc" directly once TVM has been pip installed. -python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ - --target-cmsis-nn-mcpu=cortex-m55 \ - --target-c-mcpu=cortex-m55 \ - --runtime=crt \ - --executor=aot \ - --executor-aot-interface-api=c \ - --executor-aot-unpacked-api=1 \ - --pass-config tir.usmp.enable=1 \ - --pass-config tir.usmp.algorithm=hill_climb \ - --pass-config tir.disable_storage_rewrite=1 \ - --pass-config tir.disable_vectorize=1 ocr_en/inference.pdmodel \ - --output-format=mlf \ - --model-format=paddle \ - --module-name=rec \ - --input-shapes x:[1,3,32,320] \ - --output=rec.tar -tar -xf rec.tar - -# Create C header files -cd .. -python3 ./convert_image.py imgs_words_en/word_116.png - -# Build demo executable -cd ${script_dir} -echo ${script_dir} -make - -# Run demo executable on the AVH -$Platform -C cpu0.CFGDTCMSZ=15 \ --C cpu0.CFGITCMSZ=15 -C mps3_board.uart0.out_file=\"-\" -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ --C mps3_board.visualisation.disable-visualisation=1 -C mps3_board.telnetterminal0.start_telnet=0 \ --C mps3_board.telnetterminal1.start_telnet=0 -C mps3_board.telnetterminal2.start_telnet=0 -C mps3_board.telnetterminal5.start_telnet=0 \ -./build/demo --stat diff --git a/Object-Classification-example/MobileNetV3_small_x0_35/Makefile b/Object-Classification-example/MobileNetV3_small_x0_35/Makefile deleted file mode 100644 index cf7d375..0000000 --- a/Object-Classification-example/MobileNetV3_small_x0_35/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -# Makefile to build demo - -# Setup build environment -BUILD_DIR := build - -ARM_CPU = ARMCM55 -ETHOSU_PATH = /opt/arm/ethosu -CMSIS_PATH ?= ${ETHOSU_PATH}/cmsis -ETHOSU_PLATFORM_PATH ?= ${ETHOSU_PATH}/core_platform -STANDALONE_CRT_PATH := $(abspath $(BUILD_DIR))/runtime -CORSTONE_300_PATH = ${ETHOSU_PLATFORM_PATH}/targets/corstone-300 -PKG_COMPILE_OPTS = -g -Wall -O2 -Wno-incompatible-pointer-types -Wno-format -mcpu=cortex-m55 -mthumb -mfloat-abi=hard -std=gnu99 -CMAKE ?= cmake -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib -PKG_CFLAGS = ${PKG_COMPILE_OPTS} \ - -I${STANDALONE_CRT_PATH}/include \ - -I${STANDALONE_CRT_PATH}/src/runtime/crt/include \ - -I${PWD}/include \ - -I${CORSTONE_300_PATH} \ - -I${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Include/ \ - -I${CMSIS_PATH}/CMSIS/Core/Include \ - -I${CMSIS_PATH}/CMSIS/NN/Include \ - -I${CMSIS_PATH}/CMSIS/DSP/Include \ - -I$(abspath $(BUILD_DIR))/codegen/host/include -CMSIS_NN_CMAKE_FLAGS = -DCMAKE_TOOLCHAIN_FILE=$(abspath $(BUILD_DIR))/../arm-none-eabi-gcc.cmake \ - -DTARGET_CPU=cortex-m55 \ - -DBUILD_CMSIS_NN_FUNCTIONS=YES -PKG_LDFLAGS = -lm -specs=nosys.specs -static -T corstone300.ld - -$(ifeq VERBOSE,1) -QUIET ?= -$(else) -QUIET ?= @ -$(endif) - -DEMO_MAIN = src/demo_bare_metal.c -CODEGEN_SRCS = $(wildcard $(abspath $(BUILD_DIR))/codegen/host/src/*.c) -CODEGEN_OBJS = $(subst .c,.o,$(CODEGEN_SRCS)) -CMSIS_STARTUP_SRCS = $(wildcard ${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Source/*.c) -UART_SRCS = $(wildcard ${CORSTONE_300_PATH}/*.c) - -demo: $(BUILD_DIR)/demo - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/crt_backend_api.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/common/crt_backend_api.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -# Build generated code -$(BUILD_DIR)/libcodegen.a: $(CODEGEN_SRCS) - $(QUIET)cd $(abspath $(BUILD_DIR)/codegen/host/src) && $(CC) -c $(PKG_CFLAGS) $(CODEGEN_SRCS) - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcodegen.a) $(CODEGEN_OBJS) - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcodegen.a) - -# Build CMSIS startup code -${BUILD_DIR}/libcmsis_startup.a: $(CMSIS_STARTUP_SRCS) - $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libcmsis_startup) - $(QUIET)cd $(abspath $(BUILD_DIR)/libcmsis_startup) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcmsis_startup.a) $(abspath $(BUILD_DIR))/libcmsis_startup/*.o - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcmsis_startup.a) - -CMSIS_SHA_FILE=${CMSIS_PATH}/977abe9849781a2e788b02282986480ff4e25ea6.sha -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -else -# Build CMSIS-NN -${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -endif - -# Build demo application -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a ${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -else -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a \ - ${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a \ - ${BUILD_DIR}/cmsis_nn/Source/FullyConnectedFunctions/libCMSISNNFullyConnected.a \ - ${BUILD_DIR}/cmsis_nn/Source/SVDFunctions/libCMSISNNSVDF.a \ - ${BUILD_DIR}/cmsis_nn/Source/ReshapeFunctions/libCMSISNNReshape.a \ - ${BUILD_DIR}/cmsis_nn/Source/ActivationFunctions/libCMSISNNActivation.a \ - ${BUILD_DIR}/cmsis_nn/Source/NNSupportFunctions/libCMSISNNSupport.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConcatenationFunctions/libCMSISNNConcatenation.a \ - ${BUILD_DIR}/cmsis_nn/Source/BasicMathFunctions/libCMSISNNBasicMaths.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConvolutionFunctions/libCMSISNNConvolutions.a \ - ${BUILD_DIR}/cmsis_nn/Source/PoolingFunctions/libCMSISNNPooling.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -endif - -clean: - $(QUIET)rm -rf $(BUILD_DIR)/codegen - -cleanall: - $(QUIET)rm -rf $(BUILD_DIR) - -.SUFFIXES: - -.DEFAULT: demo diff --git a/Object-Classification-example/MobileNetV3_small_x0_35/README.md b/Object-Classification-example/MobileNetV3_small_x0_35/README.md deleted file mode 100644 index 26bf83b..0000000 --- a/Object-Classification-example/MobileNetV3_small_x0_35/README.md +++ /dev/null @@ -1,114 +0,0 @@ - - - - - - - - - - - - - - - - - - -Running PaddleClas Classification model on bare metal Arm(R) Cortex(R)-M55 CPU using Arm Virtual Hardware -====================================================================== - -This folder contains an example of how to run a PaddleClas model on bare metal [Cortex(R)-M55 CPU](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55) using [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware). - - -Running environment and prerequisites -------------- -Case 1: If the demo is run in Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by [AWS](https://aws.amazon.com/marketplace/pp/prodview-urbpq7yo5va7g?sr=0-1&ref_=beagle&applicationId=AWSMPContessa)/[AWS China](https://awsmarketplace.amazonaws.cn/marketplace/pp/prodview-2y7nefntbmybu), the following software will be installed through [configure_avh.sh](configure_avh.sh) script. It will install automatically when you run the application through [run_demo.sh](run_demo.sh) script. -You can refer to this [guide](https://arm-software.github.io/AVH/main/examples/html/MicroSpeech.html#amilaunch) to launch an Arm Virtual Hardware AMI instance. - -Case 2: If the demo is run in the [ci_cpu Docker container](https://github.com/apache/tvm/blob/main/docker/Dockerfile.ci_cpu) provided with [TVM](https://github.com/apache/tvm), then the following software will already be installed. - -Case 3: If the demo is not run in the ci_cpu Docker container, then you will need the following: -- Software required to build and run the demo (These can all be installed by running - tvm/docker/install/ubuntu_install_ethosu_driver_stack.sh.) - - [Fixed Virtual Platform (FVP) based on Arm(R) Corstone(TM)-300 software](https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps) - - [cmake 3.19.5](https://github.com/Kitware/CMake/releases/) - - [GCC toolchain from Arm(R)](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2) - - [Arm(R) Ethos(TM)-U NPU driver stack](https://review.mlplatform.org) - - [CMSIS](https://github.com/ARM-software/CMSIS_5) -- The python libraries listed in the requirements.txt of this directory - - These can be installed by running the following from the current directory: - ```bash - pip install -r ./requirements.txt - ``` - -In case2 and case3: - -You will need to update your PATH environment variable to include the path to cmake 3.19.5 and the FVP. -For example if you've installed these in ```/opt/arm``` , then you would do the following: -```bash -export PATH=/opt/arm/FVP_Corstone_SSE-300/models/Linux64_GCC-6.4:/opt/arm/cmake/bin:$PATH -``` - -You will also need TVM which can either be: - - Installed from TLCPack(see [TLCPack](https://tlcpack.ai/)) - - Built from source (see [Install from Source](https://tvm.apache.org/docs/install/from_source.html)) - - When building from source, the following need to be set in config.cmake: - - set(USE_CMSISNN ON) - - set(USE_MICRO ON) - - set(USE_LLVM ON) - - -Running the demo application ----------------------------- -Type the following command to run the bare metal Classification application ([src/demo_bare_metal.c](src/demo_bare_metal.c)): - -```bash -./run_demo.sh -``` - -If you are not able to use Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by AWS/AWS China, specify argument --enable_FVP to 1 to make the application run on local Fixed Virtual Platforms (FVPs) executables. - -```bash -./run_demo.sh --enable_FVP 1 -``` - -If the Ethos(TM)-U platform and/or CMSIS have not been installed in /opt/arm/ethosu then -the locations for these can be specified as arguments to run_demo.sh, for example: - -```bash -./run_demo.sh --cmsis_path /home/tvm-user/cmsis \ ---ethosu_platform_path /home/tvm-user/ethosu/core_platform -``` - -With [run_demo.sh](run_demo.sh) to run the demo application, it will: -- Set up running environment by installing the required prerequisites automatically if running in Arm Virtual Hardware Amazon AMI instance(not specify --enable_FVP to 1) -- Download a PaddleClas classification model. -- Use tvmc to compile the classification model for Cortex(R)-M55 CPU and CMSIS-NN -- Create a C header file inputs.c containing the image data as a C array -- Create a C header file outputs.c containing a C array where the output of inference will be stored -- Build the demo application -- Run the demo application on a Arm Virtual Hardware based on Arm(R) Corstone(TM)-300 software -- The application will report the max index and score on the image and the corresponding score. - -Using your own image --------------------- -The create_image.py script takes a single argument on the command line which is the path of the -image to be converted into an array of bytes for consumption by the model. - -The demo can be modified to use an image of your choice by changing the following line in run_demo.sh - -```bash -python3 ./convert_image.py path/to/img_and_label -``` - -Post process of the inference results --------------------- -The `labels/label_list.txt` stores the label information of the model. -The `labels/convert_label.py` will correspond the output information transmitted from the serial port to the label one by one. - -Model description ------------------ -The example is built on [MobileNetV3_small_x0_35_ssld](https://github.com/PaddlePaddle/PaddleClas/tree/release/2.5/docs/zh_CN/models/ImageNet1k#Mobile) Classification model released by [PaddleClas](https://github.com/PaddlePaddle/PaddleClas). - diff --git a/Object-Classification-example/MobileNetV3_small_x0_35/arm-none-eabi-gcc.cmake b/Object-Classification-example/MobileNetV3_small_x0_35/arm-none-eabi-gcc.cmake deleted file mode 100644 index 415b313..0000000 --- a/Object-Classification-example/MobileNetV3_small_x0_35/arm-none-eabi-gcc.cmake +++ /dev/null @@ -1,79 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -if (__TOOLCHAIN_LOADED) - return() -endif() -set(__TOOLCHAIN_LOADED TRUE) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_SYSTEM_PROCESSOR "cortex-m55" CACHE STRING "Select Arm(R) Cortex(R)-M architecture. (cortex-m0, cortex-m3, cortex-m33, cortex-m4, cortex-m55, cortex-m7, etc)") - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_STANDARD 99) -set(CMAKE_CXX_STANDARD 14) - -# The system processor could for example be set to cortex-m33+nodsp+nofp. -set(__CPU_COMPILE_TARGET ${CMAKE_SYSTEM_PROCESSOR}) -string(REPLACE "+" ";" __CPU_FEATURES ${__CPU_COMPILE_TARGET}) -list(POP_FRONT __CPU_FEATURES CMAKE_SYSTEM_PROCESSOR) - -string(FIND ${__CPU_COMPILE_TARGET} "+" __OFFSET) -if(__OFFSET GREATER_EQUAL 0) - string(SUBSTRING ${__CPU_COMPILE_TARGET} ${__OFFSET} -1 CPU_FEATURES) -endif() - -# Add -mcpu to the compile options to override the -mcpu the CMake toolchain adds -add_compile_options(-mcpu=${__CPU_COMPILE_TARGET}) - -# Set floating point unit -if("${__CPU_COMPILE_TARGET}" MATCHES "\\+fp") - set(FLOAT hard) -elseif("${__CPU_COMPILE_TARGET}" MATCHES "\\+nofp") - set(FLOAT soft) -elseif("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m33" OR - "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55") - set(FLOAT hard) -else() - set(FLOAT soft) -endif() - -add_compile_options(-mfloat-abi=${FLOAT}) -add_link_options(-mfloat-abi=${FLOAT}) - -# Link target -add_link_options(-mcpu=${__CPU_COMPILE_TARGET}) -add_link_options(-Xlinker -Map=output.map) - -# -# Compile options -# -set(cxx_flags "-fno-unwind-tables;-fno-rtti;-fno-exceptions") - -add_compile_options("-Wall;-Wextra;-Wsign-compare;-Wunused;-Wswitch-default;\ --Wdouble-promotion;-Wredundant-decls;-Wshadow;-Wnull-dereference;\ --Wno-format-extra-args;-Wno-unused-function;-Wno-unused-label;\ --Wno-missing-field-initializers;-Wno-return-type;-Wno-format;-Wno-int-conversion" - "$<$:${cxx_flags}>" -) diff --git a/Object-Classification-example/MobileNetV3_small_x0_35/configure_avh.sh b/Object-Classification-example/MobileNetV3_small_x0_35/configure_avh.sh deleted file mode 100755 index 8042fd8..0000000 --- a/Object-Classification-example/MobileNetV3_small_x0_35/configure_avh.sh +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/bash -# Copyright (c) 2022 Arm Limited and Contributors. All rights reserved. -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat <&2 - show_usage >&2 - exit 1 - fi - ;; - - --ethosu_platform_path) - if [ $# -gt 1 ] - then - export ETHOSU_PLATFORM_PATH="$2" - shift 2 - else - echo 'ERROR: --ethosu_platform_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --fvp_path) - if [ $# -gt 1 ] - then - export PATH="$2/models/Linux64_GCC-6.4:$PATH" - shift 2 - else - echo 'ERROR: --fvp_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --cmake_path) - if [ $# -gt 1 ] - then - export CMAKE="$2" - shift 2 - else - echo 'ERROR: --cmake_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --enable_FVP) - if [ $# -gt 1 ] && [ "$2" == "1" -o "$2" == "0" ]; - then - FVP_enable="$2" - shift 2 - else - echo 'ERROR: --enable_FVP requires a right argument 1 or 0' >&2 - show_usage >&2 - exit 1 - fi - ;; - - -*|--*) - echo "Error: Unknown flag: $1" >&2 - show_usage >&2 - exit 1 - ;; - esac -done - -# Choose running environment: cloud(default) or local environment -Platform="VHT_Corstone_SSE-300_Ethos-U55" -if [ $FVP_enable == "1" ]; then - Platform="FVP_Corstone_SSE-300_Ethos-U55" - echo -e "\e[36mRun application on local Fixed Virtual Platforms (FVPs)\e[0m" -else - if [ ! -d "/opt/arm/" ]; then - sudo ./configure_avh.sh - fi -fi - -# Directories -script_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )" - -# Make build directory -make cleanall -mkdir -p build -cd build - -# Get PaddlePaddle inference model -echo -e "\e[36mDownload PaddlePaddle inference model\e[0m" -wget https://paddle-imagenet-models-name.bj.bcebos.com/dygraph/inference/MobileNetV3_small_x0_35_ssld_infer.tar -tar -xf MobileNetV3_small_x0_35_ssld_infer.tar - -# Compile model for Arm(R) Cortex(R)-M55 CPU and CMSIS-NN -# An alternative to using "python3 -m tvm.driver.tvmc" is to call -# "tvmc" directly once TVM has been pip installed. -python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ - --target-cmsis-nn-mcpu=cortex-m55 \ - --target-c-mcpu=cortex-m55 \ - --runtime=crt \ - --executor=aot \ - --executor-aot-interface-api=c \ - --executor-aot-unpacked-api=1 \ - --pass-config tir.usmp.enable=1 \ - --pass-config tir.usmp.algorithm=hill_climb \ - --pass-config tir.disable_storage_rewrite=1 \ - --pass-config tir.disable_vectorize=1 MobileNetV3_small_x0_35_ssld_infer/inference/inference.pdmodel \ - --output-format=mlf \ - --model-format=paddle \ - --module-name=cls \ - --input-shapes x:[1,3,224,224] \ - --output=cls.tar -tar -xf cls.tar - -# Create C header files -cd .. -python3 ./convert_image.py ./imgs/OIF-e2bexWrojgtQnAPPcUfOWQ.jpeg - -# Build demo executable -cd ${script_dir} -echo ${script_dir} -make - -# Run demo executable on the AVH -$Platform -C cpu0.CFGDTCMSZ=15 \ --C cpu0.CFGITCMSZ=15 -C mps3_board.uart0.out_file=\"./result.txt\" -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ --C mps3_board.visualisation.disable-visualisation=1 -C mps3_board.telnetterminal0.start_telnet=0 \ --C mps3_board.telnetterminal1.start_telnet=0 -C mps3_board.telnetterminal2.start_telnet=0 -C mps3_board.telnetterminal5.start_telnet=0 \ -./build/demo --stat - -python3 ./labels/convert_label.py ./labels/label_list.txt \ No newline at end of file diff --git a/Object-Classification-example/MobileNetV3_small_x0_35/src/demo_bare_metal.c b/Object-Classification-example/MobileNetV3_small_x0_35/src/demo_bare_metal.c deleted file mode 100644 index 2c5dca0..0000000 --- a/Object-Classification-example/MobileNetV3_small_x0_35/src/demo_bare_metal.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include -#include "uart.h" - -// Header files generated by convert_image.py -#include "inputs.h" -#include "outputs.h" - - -int main(int argc, char** argv) { - uart_init(); - printf("Starting cls inference\n"); - struct tvmgen_cls_outputs cls_outputs = { - .output = output, - }; - struct tvmgen_cls_inputs cls_inputs = { - .x = input, - }; - - tvmgen_cls_run(&cls_inputs, &cls_outputs); - - // post process - int index = 0; - for(int i = 0; i < output_len;i++){ - if(output[i] > output[index]){ - index = i; - } - } - printf("%d,%f\n", index, output[index]); - - // The FVP will shut down when it receives "EXITTHESIM" on the UART - printf("EXITTHESIM\n"); - while (1 == 1) - ; - return 0; -} \ No newline at end of file diff --git a/Object-Classification-example/PP-LCNet/.cproject b/Object-Classification-example/PP-LCNet/.cproject deleted file mode 100644 index c7b729f..0000000 --- a/Object-Classification-example/PP-LCNet/.cproject +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Object-Classification-example/PP-LCNet/.project b/Object-Classification-example/PP-LCNet/.project deleted file mode 100644 index e5e0cce..0000000 --- a/Object-Classification-example/PP-LCNet/.project +++ /dev/null @@ -1,27 +0,0 @@ - - - PP-LCNet - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/Object-Classification-example/PP-LCNet/Makefile b/Object-Classification-example/PP-LCNet/Makefile deleted file mode 100644 index cf7d375..0000000 --- a/Object-Classification-example/PP-LCNet/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -# Makefile to build demo - -# Setup build environment -BUILD_DIR := build - -ARM_CPU = ARMCM55 -ETHOSU_PATH = /opt/arm/ethosu -CMSIS_PATH ?= ${ETHOSU_PATH}/cmsis -ETHOSU_PLATFORM_PATH ?= ${ETHOSU_PATH}/core_platform -STANDALONE_CRT_PATH := $(abspath $(BUILD_DIR))/runtime -CORSTONE_300_PATH = ${ETHOSU_PLATFORM_PATH}/targets/corstone-300 -PKG_COMPILE_OPTS = -g -Wall -O2 -Wno-incompatible-pointer-types -Wno-format -mcpu=cortex-m55 -mthumb -mfloat-abi=hard -std=gnu99 -CMAKE ?= cmake -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib -PKG_CFLAGS = ${PKG_COMPILE_OPTS} \ - -I${STANDALONE_CRT_PATH}/include \ - -I${STANDALONE_CRT_PATH}/src/runtime/crt/include \ - -I${PWD}/include \ - -I${CORSTONE_300_PATH} \ - -I${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Include/ \ - -I${CMSIS_PATH}/CMSIS/Core/Include \ - -I${CMSIS_PATH}/CMSIS/NN/Include \ - -I${CMSIS_PATH}/CMSIS/DSP/Include \ - -I$(abspath $(BUILD_DIR))/codegen/host/include -CMSIS_NN_CMAKE_FLAGS = -DCMAKE_TOOLCHAIN_FILE=$(abspath $(BUILD_DIR))/../arm-none-eabi-gcc.cmake \ - -DTARGET_CPU=cortex-m55 \ - -DBUILD_CMSIS_NN_FUNCTIONS=YES -PKG_LDFLAGS = -lm -specs=nosys.specs -static -T corstone300.ld - -$(ifeq VERBOSE,1) -QUIET ?= -$(else) -QUIET ?= @ -$(endif) - -DEMO_MAIN = src/demo_bare_metal.c -CODEGEN_SRCS = $(wildcard $(abspath $(BUILD_DIR))/codegen/host/src/*.c) -CODEGEN_OBJS = $(subst .c,.o,$(CODEGEN_SRCS)) -CMSIS_STARTUP_SRCS = $(wildcard ${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Source/*.c) -UART_SRCS = $(wildcard ${CORSTONE_300_PATH}/*.c) - -demo: $(BUILD_DIR)/demo - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/crt_backend_api.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/common/crt_backend_api.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -# Build generated code -$(BUILD_DIR)/libcodegen.a: $(CODEGEN_SRCS) - $(QUIET)cd $(abspath $(BUILD_DIR)/codegen/host/src) && $(CC) -c $(PKG_CFLAGS) $(CODEGEN_SRCS) - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcodegen.a) $(CODEGEN_OBJS) - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcodegen.a) - -# Build CMSIS startup code -${BUILD_DIR}/libcmsis_startup.a: $(CMSIS_STARTUP_SRCS) - $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libcmsis_startup) - $(QUIET)cd $(abspath $(BUILD_DIR)/libcmsis_startup) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcmsis_startup.a) $(abspath $(BUILD_DIR))/libcmsis_startup/*.o - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcmsis_startup.a) - -CMSIS_SHA_FILE=${CMSIS_PATH}/977abe9849781a2e788b02282986480ff4e25ea6.sha -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -else -# Build CMSIS-NN -${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -endif - -# Build demo application -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a ${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -else -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a \ - ${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a \ - ${BUILD_DIR}/cmsis_nn/Source/FullyConnectedFunctions/libCMSISNNFullyConnected.a \ - ${BUILD_DIR}/cmsis_nn/Source/SVDFunctions/libCMSISNNSVDF.a \ - ${BUILD_DIR}/cmsis_nn/Source/ReshapeFunctions/libCMSISNNReshape.a \ - ${BUILD_DIR}/cmsis_nn/Source/ActivationFunctions/libCMSISNNActivation.a \ - ${BUILD_DIR}/cmsis_nn/Source/NNSupportFunctions/libCMSISNNSupport.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConcatenationFunctions/libCMSISNNConcatenation.a \ - ${BUILD_DIR}/cmsis_nn/Source/BasicMathFunctions/libCMSISNNBasicMaths.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConvolutionFunctions/libCMSISNNConvolutions.a \ - ${BUILD_DIR}/cmsis_nn/Source/PoolingFunctions/libCMSISNNPooling.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -endif - -clean: - $(QUIET)rm -rf $(BUILD_DIR)/codegen - -cleanall: - $(QUIET)rm -rf $(BUILD_DIR) - -.SUFFIXES: - -.DEFAULT: demo diff --git a/Object-Classification-example/PP-LCNet/README.md b/Object-Classification-example/PP-LCNet/README.md deleted file mode 100644 index 62fec96..0000000 --- a/Object-Classification-example/PP-LCNet/README.md +++ /dev/null @@ -1,116 +0,0 @@ - - - - - - - - - - - - - - - - - -English | [简体中文](README_ch.md) - -Running PaddleClas image classification model on bare metal Arm(R) Cortex(R)-M55 CPU using Arm Virtual Hardware -====================================================================== - -This folder contains an example of how to run a PaddleClas model on bare metal [Cortex(R)-M55 CPU](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55) using [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware). - - -Running environment and prerequisites -------------- -Case 1: If the demo is run in Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by [AWS](https://aws.amazon.com/marketplace/pp/prodview-urbpq7yo5va7g?sr=0-1&ref_=beagle&applicationId=AWSMPContessa)/[AWS China](https://awsmarketplace.amazonaws.cn/marketplace/pp/prodview-2y7nefntbmybu), the following software will be installed through [configure_avh.sh](./configure_avh.sh) script. It will install automatically when you run the application through [run_demo.sh](./run_demo.sh) script. -You can refer to this [guide](https://arm-software.github.io/AVH/main/examples/html/MicroSpeech.html#amilaunch) to launch an Arm Virtual Hardware AMI instance. - -Case 2: If the demo is run in the [ci_cpu Docker container](https://github.com/apache/tvm/blob/main/docker/Dockerfile.ci_cpu) provided with [TVM](https://github.com/apache/tvm), then the following software will already be installed. - -Case 3: If the demo is not run in the ci_cpu Docker container, then you will need the following: -- Software required to build and run the demo (These can all be installed by running - tvm/docker/install/ubuntu_install_ethosu_driver_stack.sh.) - - [Fixed Virtual Platform (FVP) based on Arm(R) Corstone(TM)-300 software](https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps) - - [cmake 3.19.5](https://github.com/Kitware/CMake/releases/) - - [GCC toolchain from Arm(R)](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2) - - [Arm(R) Ethos(TM)-U NPU driver stack](https://review.mlplatform.org) - - [CMSIS](https://github.com/ARM-software/CMSIS_5) -- The python libraries listed in the requirements.txt of this directory - - These can be installed by running the following from the current directory: - ```bash - pip install -r ./requirements.txt - ``` - -In case2 and case3: - -You will need to update your PATH environment variable to include the path to cmake 3.19.5 and the FVP. -For example if you've installed these in ```/opt/arm``` , then you would do the following: -```bash -export PATH=/opt/arm/FVP_Corstone_SSE-300/models/Linux64_GCC-6.4:/opt/arm/cmake/bin:$PATH -``` - -You will also need TVM which can either be: - - Installed from TLCPack(see [TLCPack](https://tlcpack.ai/)) - - Built from source (see [Install from Source](https://tvm.apache.org/docs/install/from_source.html)) - - When building from source, the following need to be set in config.cmake: - - set(USE_CMSISNN ON) - - set(USE_MICRO ON) - - set(USE_LLVM ON) - - -Running the demo application ----------------------------- -Type the following command to run the bare metal image classification application ([src/demo_bare_metal.c](./src/demo_bare_metal.c)): - -```bash -./run_demo.sh -``` - -If you are not able to use Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by AWS/AWS China, specify argument --enable_FVP to 1 to make the application run on local Fixed Virtual Platforms (FVPs) executables. - -```bash -./run_demo.sh --enable_FVP 1 -``` - -If the Ethos(TM)-U platform and/or CMSIS have not been installed in /opt/arm/ethosu then -the locations for these can be specified as arguments to run_demo.sh, for example: - -```bash -./run_demo.sh --cmsis_path /home/tvm-user/cmsis \ ---ethosu_platform_path /home/tvm-user/ethosu/core_platform -``` - -With [run_demo.sh](./run_demo.sh) to run the demo application, it will: -- Set up running environment by installing the required prerequisites automatically if running in Arm Virtual Hardware Amazon AMI instance(not specify --enable_FVP to 1) -- Download a PaddleClas image classification model -- Use tvmc to compile the image classification model for Cortex(R)-M55 CPU and CMSIS-NN -- Create a C header file inputs.c containing the image data as a C array -- Create a C header file outputs.c containing a C array where the output of inference will be stored -- Create a C header file labels.h containing the ImageNet labels as a C array -- Build the demo application -- Run the demo application on a Arm Virtual Hardware based on Arm(R) Corstone(TM)-300 software -- The application will report the classification result about the image and the score. - -Using your own image --------------------- -The create_image.py script takes a single argument on the command line which is the path of the -image to be converted into an array of bytes for consumption by the model. - -The demo can be modified to use an image of your choice by changing the following line in run_demo.sh - -```bash -python3 ./convert_image.py path/to/image -``` - -Model description ------------------ -The example is built on [PP-LCNet](https://github.com/PaddlePaddle/PaddleClas/blob/release/2.5/docs/zh_CN/models/ImageNet1k/PP-LCNet.md) Visual backbone network released by [PaddleClas](https://github.com/PaddlePaddle/PaddleClas). - -PP-LCNet is the first version of the PP-LCNet series model. This series of models has the following features: - - PP-LCNet: lightweight visual backbone network: PP-LCNet_x0_75 params=2.4M, Flops=99M, model size=526.15KB - - Pre-trained model on ImageNet dataset - - diff --git a/Object-Classification-example/PP-LCNet/arm-none-eabi-gcc.cmake b/Object-Classification-example/PP-LCNet/arm-none-eabi-gcc.cmake deleted file mode 100644 index 415b313..0000000 --- a/Object-Classification-example/PP-LCNet/arm-none-eabi-gcc.cmake +++ /dev/null @@ -1,79 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -if (__TOOLCHAIN_LOADED) - return() -endif() -set(__TOOLCHAIN_LOADED TRUE) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_SYSTEM_PROCESSOR "cortex-m55" CACHE STRING "Select Arm(R) Cortex(R)-M architecture. (cortex-m0, cortex-m3, cortex-m33, cortex-m4, cortex-m55, cortex-m7, etc)") - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_STANDARD 99) -set(CMAKE_CXX_STANDARD 14) - -# The system processor could for example be set to cortex-m33+nodsp+nofp. -set(__CPU_COMPILE_TARGET ${CMAKE_SYSTEM_PROCESSOR}) -string(REPLACE "+" ";" __CPU_FEATURES ${__CPU_COMPILE_TARGET}) -list(POP_FRONT __CPU_FEATURES CMAKE_SYSTEM_PROCESSOR) - -string(FIND ${__CPU_COMPILE_TARGET} "+" __OFFSET) -if(__OFFSET GREATER_EQUAL 0) - string(SUBSTRING ${__CPU_COMPILE_TARGET} ${__OFFSET} -1 CPU_FEATURES) -endif() - -# Add -mcpu to the compile options to override the -mcpu the CMake toolchain adds -add_compile_options(-mcpu=${__CPU_COMPILE_TARGET}) - -# Set floating point unit -if("${__CPU_COMPILE_TARGET}" MATCHES "\\+fp") - set(FLOAT hard) -elseif("${__CPU_COMPILE_TARGET}" MATCHES "\\+nofp") - set(FLOAT soft) -elseif("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m33" OR - "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55") - set(FLOAT hard) -else() - set(FLOAT soft) -endif() - -add_compile_options(-mfloat-abi=${FLOAT}) -add_link_options(-mfloat-abi=${FLOAT}) - -# Link target -add_link_options(-mcpu=${__CPU_COMPILE_TARGET}) -add_link_options(-Xlinker -Map=output.map) - -# -# Compile options -# -set(cxx_flags "-fno-unwind-tables;-fno-rtti;-fno-exceptions") - -add_compile_options("-Wall;-Wextra;-Wsign-compare;-Wunused;-Wswitch-default;\ --Wdouble-promotion;-Wredundant-decls;-Wshadow;-Wnull-dereference;\ --Wno-format-extra-args;-Wno-unused-function;-Wno-unused-label;\ --Wno-missing-field-initializers;-Wno-return-type;-Wno-format;-Wno-int-conversion" - "$<$:${cxx_flags}>" -) diff --git a/Object-Classification-example/PP-LCNet/configure_avh.sh b/Object-Classification-example/PP-LCNet/configure_avh.sh deleted file mode 100755 index 8042fd8..0000000 --- a/Object-Classification-example/PP-LCNet/configure_avh.sh +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/bash -# Copyright (c) 2022 Arm Limited and Contributors. All rights reserved. -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat < Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00080000; - -/*--------------------- DTCM RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00080000; - -/*----------------------- Data SRAM Configuration ------------------------------ - Data SRAM Configuration - DATA_SRAM Base Address <0x0-0xFFFFFFFF:8> - DATA_SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DATA_SRAM_BASE = 0x01000000; -__DATA_SRAM_SIZE = 0x00200000; - -/*--------------------- Embedded SRAM Configuration ---------------------------- - SRAM Configuration - SRAM Base Address <0x0-0xFFFFFFFF:8> - SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__SRAM_BASE = 0x21000000; -__SRAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00008000; -__HEAP_SIZE = 0x00008000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - DDR Configuration - DDR Base Address <0x0-0xFFFFFFFF:8> - DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DDR_BASE = 0x60000000; -__DDR_SIZE = 0x02000000; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - DATA_SRAM (rwx) : ORIGIN = __DATA_SRAM_BASE, LENGTH = __DATA_SRAM_SIZE - SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE - DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - /* .ddr is placed before .text so that .rodata.tvm is encountered before .rodata* */ - .ddr : - { - . = ALIGN (16); - *(.rodata.tvm) - . = ALIGN (16); - *(.data.tvm); - . = ALIGN(16); - } > DDR - - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > ITCM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - /* Add each additional data section here */ - __copy_table_end__ = .; - } > ITCM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > ITCM - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .sram : - { - . = ALIGN(16); - } > SRAM AT > SRAM - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > DTCM - - .bss.noinit (NOLOAD): - { - . = ALIGN(16); - *(.bss.noinit.*) - . = ALIGN(16); - } > SRAM AT > SRAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DTCM AT > DTCM - - .data_sram : - { - . = ALIGN(16); - } > DATA_SRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - - /* Check if data + stack exceeds DTCM limit */ - ASSERT(__StackLimit >= __bss_end__, "region DTCM overflowed with stack") -} diff --git a/Object-Classification-example/PP-LCNet/include/tvm_runtime.h b/Object-Classification-example/PP-LCNet/include/tvm_runtime.h deleted file mode 100644 index 2b59d93..0000000 --- a/Object-Classification-example/PP-LCNet/include/tvm_runtime.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void __attribute__((noreturn)) TVMPlatformAbort(tvm_crt_error_t error_code) { - printf("TVMPlatformAbort: %d\n", error_code); - printf("EXITTHESIM\n"); - exit(-1); -} - -tvm_crt_error_t TVMPlatformMemoryAllocate(size_t num_bytes, DLDevice dev, void** out_ptr) { - return kTvmErrorFunctionCallNotImplemented; -} - -tvm_crt_error_t TVMPlatformMemoryFree(void* ptr, DLDevice dev) { - return kTvmErrorFunctionCallNotImplemented; -} - -void TVMLogf(const char* msg, ...) { - va_list args; - va_start(args, msg); - vfprintf(stdout, msg, args); - va_end(args); -} - -TVM_DLL int TVMFuncRegisterGlobal(const char* name, TVMFunctionHandle f, int override) { return 0; } - -#ifdef __cplusplus -} -#endif diff --git a/Object-Classification-example/PP-LCNet/requirements.txt b/Object-Classification-example/PP-LCNet/requirements.txt deleted file mode 100644 index a1a8626..0000000 --- a/Object-Classification-example/PP-LCNet/requirements.txt +++ /dev/null @@ -1,4 +0,0 @@ -paddlepaddle -numpy -opencv-python -typing-extensions diff --git a/Object-Classification-example/PP-LCNet/run_demo.sh b/Object-Classification-example/PP-LCNet/run_demo.sh deleted file mode 100755 index 9843445..0000000 --- a/Object-Classification-example/PP-LCNet/run_demo.sh +++ /dev/null @@ -1,184 +0,0 @@ -#!/bin/bash -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat <&2 - show_usage >&2 - exit 1 - fi - ;; - - --ethosu_platform_path) - if [ $# -gt 1 ] - then - export ETHOSU_PLATFORM_PATH="$2" - shift 2 - else - echo 'ERROR: --ethosu_platform_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --fvp_path) - if [ $# -gt 1 ] - then - export PATH="$2/models/Linux64_GCC-6.4:$PATH" - shift 2 - else - echo 'ERROR: --fvp_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --cmake_path) - if [ $# -gt 1 ] - then - export CMAKE="$2" - shift 2 - else - echo 'ERROR: --cmake_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --enable_FVP) - if [ $# -gt 1 ] && [ "$2" == "1" -o "$2" == "0" ]; - then - FVP_enable="$2" - shift 2 - else - echo 'ERROR: --enable_FVP requires a right argument 1 or 0' >&2 - show_usage >&2 - exit 1 - fi - ;; - - -*|--*) - echo "Error: Unknown flag: $1" >&2 - show_usage >&2 - exit 1 - ;; - esac -done - -# Choose running environment: cloud(default) or local environment -Platform="VHT_Corstone_SSE-300_Ethos-U55" -if [ $FVP_enable == "1" ]; then - Platform="FVP_Corstone_SSE-300_Ethos-U55" - echo -e "\e[36mRun application on local Fixed Virtual Platforms (FVPs)\e[0m" -else - if [ ! -d "/opt/arm/" ]; then - sudo ./configure_avh.sh - fi -fi - -# Directories -script_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )" - -# Make build directory -make cleanall -mkdir -p build -cd build - -# Get PaddlePaddle inference model -wget https://paddle-imagenet-models-name.bj.bcebos.com/dygraph/inference/PPLCNet_x0_75_infer.tar -tar -xf PPLCNet_x0_75_infer.tar - -# Compile model for Arm(R) Cortex(R)-M55 CPU and CMSIS-NN -# An alternative to using "python3 -m tvm.driver.tvmc" is to call -# "tvmc" directly once TVM has been pip installed. -python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ - --target-cmsis-nn-mcpu=cortex-m55 \ - --target-c-mcpu=cortex-m55 \ - --runtime=crt \ - --executor=aot \ - --executor-aot-interface-api=c \ - --executor-aot-unpacked-api=1 \ - --pass-config tir.usmp.enable=1 \ - --pass-config tir.usmp.algorithm=hill_climb \ - --pass-config tir.disable_storage_rewrite=1 \ - --pass-config tir.disable_vectorize=1 PPLCNet_x0_75_infer/inference.pdmodel \ - --output-format=mlf \ - --model-format=paddle \ - --module-name=clas \ - --input-shapes x:[1,3,224,224] \ - --output=clas.tar -tar -xf clas.tar - -# Create C header files -cd .. -python3 labels/convert_labels.py labels/labels.txt -python3 ./convert_image.py image/ILSVRC2012_val_00020010.jpg - -# Build demo executable -cd ${script_dir} -echo ${script_dir} -make - -# Run demo executable on the AVH -$Platform -C cpu0.CFGDTCMSZ=15 \ --C cpu0.CFGITCMSZ=15 -C mps3_board.uart0.out_file=\"-\" -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ --C mps3_board.visualisation.disable-visualisation=1 -C mps3_board.telnetterminal0.start_telnet=0 \ --C mps3_board.telnetterminal1.start_telnet=0 -C mps3_board.telnetterminal2.start_telnet=0 -C mps3_board.telnetterminal5.start_telnet=0 \ -./build/demo --stat diff --git a/Object-Classification-example/PP-LCNet/src/demo_bare_metal.c b/Object-Classification-example/PP-LCNet/src/demo_bare_metal.c deleted file mode 100644 index 664f51c..0000000 --- a/Object-Classification-example/PP-LCNet/src/demo_bare_metal.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include - -#include "uart.h" - -// Header files generated by convert_image.py -#include "inputs.h" -#include "outputs.h" -#include "labels.h" - - -int main(int argc, char** argv) { - uart_init(); - printf("Starting image classification inference\n"); - struct tvmgen_clas_outputs clas_outputs = { - .output = output, - }; - struct tvmgen_clas_inputs clas_inputs = { - .x = input, - }; - - tvmgen_clas_run(&clas_inputs, &clas_outputs); - - // post process - int max_index = 0; - float max_value = 0.f; - - for (int i = 0; i < output_len; i++) { - max_index = output[i] > max_value ? i : max_index; - max_value = output[max_index]; - } - - printf("The image has been classified as '%s', class_index is %d, max_value is %f\n", labels[max_index], max_index, max_value); - - // The FVP will shut down when it receives "EXITTHESIM" on the UART - printf("EXITTHESIM\n"); - while (1 == 1) - ; - return 0; -} diff --git a/Object-Detection-example/Makefile b/Object-Detection-example/Makefile deleted file mode 100644 index cf7d375..0000000 --- a/Object-Detection-example/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -# Makefile to build demo - -# Setup build environment -BUILD_DIR := build - -ARM_CPU = ARMCM55 -ETHOSU_PATH = /opt/arm/ethosu -CMSIS_PATH ?= ${ETHOSU_PATH}/cmsis -ETHOSU_PLATFORM_PATH ?= ${ETHOSU_PATH}/core_platform -STANDALONE_CRT_PATH := $(abspath $(BUILD_DIR))/runtime -CORSTONE_300_PATH = ${ETHOSU_PLATFORM_PATH}/targets/corstone-300 -PKG_COMPILE_OPTS = -g -Wall -O2 -Wno-incompatible-pointer-types -Wno-format -mcpu=cortex-m55 -mthumb -mfloat-abi=hard -std=gnu99 -CMAKE ?= cmake -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib -PKG_CFLAGS = ${PKG_COMPILE_OPTS} \ - -I${STANDALONE_CRT_PATH}/include \ - -I${STANDALONE_CRT_PATH}/src/runtime/crt/include \ - -I${PWD}/include \ - -I${CORSTONE_300_PATH} \ - -I${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Include/ \ - -I${CMSIS_PATH}/CMSIS/Core/Include \ - -I${CMSIS_PATH}/CMSIS/NN/Include \ - -I${CMSIS_PATH}/CMSIS/DSP/Include \ - -I$(abspath $(BUILD_DIR))/codegen/host/include -CMSIS_NN_CMAKE_FLAGS = -DCMAKE_TOOLCHAIN_FILE=$(abspath $(BUILD_DIR))/../arm-none-eabi-gcc.cmake \ - -DTARGET_CPU=cortex-m55 \ - -DBUILD_CMSIS_NN_FUNCTIONS=YES -PKG_LDFLAGS = -lm -specs=nosys.specs -static -T corstone300.ld - -$(ifeq VERBOSE,1) -QUIET ?= -$(else) -QUIET ?= @ -$(endif) - -DEMO_MAIN = src/demo_bare_metal.c -CODEGEN_SRCS = $(wildcard $(abspath $(BUILD_DIR))/codegen/host/src/*.c) -CODEGEN_OBJS = $(subst .c,.o,$(CODEGEN_SRCS)) -CMSIS_STARTUP_SRCS = $(wildcard ${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Source/*.c) -UART_SRCS = $(wildcard ${CORSTONE_300_PATH}/*.c) - -demo: $(BUILD_DIR)/demo - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/crt_backend_api.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/common/crt_backend_api.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -# Build generated code -$(BUILD_DIR)/libcodegen.a: $(CODEGEN_SRCS) - $(QUIET)cd $(abspath $(BUILD_DIR)/codegen/host/src) && $(CC) -c $(PKG_CFLAGS) $(CODEGEN_SRCS) - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcodegen.a) $(CODEGEN_OBJS) - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcodegen.a) - -# Build CMSIS startup code -${BUILD_DIR}/libcmsis_startup.a: $(CMSIS_STARTUP_SRCS) - $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libcmsis_startup) - $(QUIET)cd $(abspath $(BUILD_DIR)/libcmsis_startup) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcmsis_startup.a) $(abspath $(BUILD_DIR))/libcmsis_startup/*.o - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcmsis_startup.a) - -CMSIS_SHA_FILE=${CMSIS_PATH}/977abe9849781a2e788b02282986480ff4e25ea6.sha -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -else -# Build CMSIS-NN -${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -endif - -# Build demo application -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a ${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -else -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a \ - ${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a \ - ${BUILD_DIR}/cmsis_nn/Source/FullyConnectedFunctions/libCMSISNNFullyConnected.a \ - ${BUILD_DIR}/cmsis_nn/Source/SVDFunctions/libCMSISNNSVDF.a \ - ${BUILD_DIR}/cmsis_nn/Source/ReshapeFunctions/libCMSISNNReshape.a \ - ${BUILD_DIR}/cmsis_nn/Source/ActivationFunctions/libCMSISNNActivation.a \ - ${BUILD_DIR}/cmsis_nn/Source/NNSupportFunctions/libCMSISNNSupport.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConcatenationFunctions/libCMSISNNConcatenation.a \ - ${BUILD_DIR}/cmsis_nn/Source/BasicMathFunctions/libCMSISNNBasicMaths.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConvolutionFunctions/libCMSISNNConvolutions.a \ - ${BUILD_DIR}/cmsis_nn/Source/PoolingFunctions/libCMSISNNPooling.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -endif - -clean: - $(QUIET)rm -rf $(BUILD_DIR)/codegen - -cleanall: - $(QUIET)rm -rf $(BUILD_DIR) - -.SUFFIXES: - -.DEFAULT: demo diff --git a/Object-Detection-example/README.md b/Object-Detection-example/README.md deleted file mode 100644 index 35dde08..0000000 --- a/Object-Detection-example/README.md +++ /dev/null @@ -1,107 +0,0 @@ - - - - - - - - - - - - - - - - - -Running PP-PicoDet object detection model on bare metal Arm(R) Cortex(R)-M55 CPU using Arm Virtual Hardware -====================================================================== - -This folder contains an example of how to run a PP-PicoDet model on bare metal [Cortex(R)-M55 CPU](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55) using [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware). - - -Running environment and prerequisites -------------- -Case 1: If the demo is run in Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by [AWS](https://aws.amazon.com/marketplace/pp/prodview-urbpq7yo5va7g?sr=0-1&ref_=beagle&applicationId=AWSMPContessa)/[AWS China](https://awsmarketplace.amazonaws.cn/marketplace/pp/prodview-2y7nefntbmybu), the following software will be installed through [configure_avh.sh](./configure_avh.sh) script. It will install automatically when you run the application through [run_demo.sh](./run_demo.sh) script. -You can refer to this [guide](https://arm-software.github.io/AVH/main/examples/html/MicroSpeech.html#amilaunch) to launch an Arm Virtual Hardware AMI instance. - -Case 2: If the demo is run in the [ci_cpu Docker container](https://github.com/apache/tvm/blob/main/docker/Dockerfile.ci_cpu) provided with [TVM](https://github.com/apache/tvm), then the following software will already be installed. - -Case 3: If the demo is not run in the ci_cpu Docker container, then you will need the following: -- Software required to build and run the demo (These can all be installed by running - tvm/docker/install/ubuntu_install_ethosu_driver_stack.sh.) - - [Fixed Virtual Platform (FVP) based on Arm(R) Corstone(TM)-300 software](https://release/2.5er.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps) - - [cmake 3.19.5](https://github.com/Kitware/CMake/releases/) - - [GCC toolchain from Arm(R)](https://release/2.5er.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2) - - [Arm(R) Ethos(TM)-U NPU driver stack](https://review.mlplatform.org) - - [CMSIS](https://github.com/ARM-software/CMSIS_5) -- The python libraries listed in the requirements.txt of this directory - - These can be installed by running the following from the current directory: - ```bash - pip install -r ./requirements.txt - ``` - -In case2 and case3: - -You will need to update your PATH environment variable to include the path to cmake 3.19.5 and the FVP. -For example if you've installed these in ```/opt/arm``` , then you would do the following: -```bash -export PATH=/opt/arm/FVP_Corstone_SSE-300/models/Linux64_GCC-6.4:/opt/arm/cmake/bin:$PATH -``` - -You will also need TVM which can either be: - - Installed from TLCPack(see [TLCPack](https://tlcpack.ai/)) - - Built from source (see [Install from Source](https://tvm.apache.org/docs/install/from_source.html)) - - When building from source, the following need to be set in config.cmake: - - set(USE_CMSISNN ON) - - set(USE_MICRO ON) - - set(USE_LLVM ON) - - -Running the demo application ----------------------------- -Type the following command to run the bare metal text recognition application ([src/demo_bare_metal.c](./src/demo_bare_metal.c)): - -```bash -./run_demo.sh -``` - -If you are not able to use Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by AWS/AWS China, specify argument --enable_FVP to 1 to make the application run on local Fixed Virtual Platforms (FVPs) executables. - -```bash -./run_demo.sh --enable_FVP 1 -``` - -If the Ethos(TM)-U platform and/or CMSIS have not been installed in /opt/arm/ethosu then -the locations for these can be specified as arguments to run_demo.sh, for example: - -```bash -./run_demo.sh --cmsis_path /home/tvm-user/cmsis \ ---ethosu_platform_path /home/tvm-user/ethosu/core_platform -``` - -With [run_demo.sh](./run_demo.sh) to run the demo application, it will: -- Set up running environment by installing the required prerequisites automatically if running in Arm Virtual Hardware Amazon AMI instance(not specify --enable_FVP to 1) -- Download a PP-PicoDet model -- Use tvmc to compile the text recognition model for Cortex(R)-M55 CPU and CMSIS-NN -- Create a C header file inputs.c containing the image data as a C array -- Create a C header file outputs.c containing a C array where the output of inference will be stored -- Build the demo application -- Run the demo application on a Arm Virtual Hardware based on Arm(R) Corstone(TM)-300 software -- The application will report the text on the image and the corresponding score. - -Using your own image --------------------- -The create_image.py script takes a single argument on the command line which is the path of the -image to be converted into an array of bytes for consumption by the model. - -The demo can be modified to use an image of your choice by changing the following line in run_demo.sh - -```bash -python3 ./convert_image.py path/to/image -``` - -Model description ------------------ -In this demo, the model we used is based on [PP-PicoDet](https://github.com/PaddlePaddle/PaddleDetection/tree/release/2.5/configs/picodet). Because of the excellent performance, PP-PicoDet are very suitable for deployment on mobile or CPU. And it is released by [PaddleDetection](https://github.com/PaddlePaddle/PaddleDetection). diff --git a/Object-Detection-example/arm-none-eabi-gcc.cmake b/Object-Detection-example/arm-none-eabi-gcc.cmake deleted file mode 100644 index 415b313..0000000 --- a/Object-Detection-example/arm-none-eabi-gcc.cmake +++ /dev/null @@ -1,79 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -if (__TOOLCHAIN_LOADED) - return() -endif() -set(__TOOLCHAIN_LOADED TRUE) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_SYSTEM_PROCESSOR "cortex-m55" CACHE STRING "Select Arm(R) Cortex(R)-M architecture. (cortex-m0, cortex-m3, cortex-m33, cortex-m4, cortex-m55, cortex-m7, etc)") - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_STANDARD 99) -set(CMAKE_CXX_STANDARD 14) - -# The system processor could for example be set to cortex-m33+nodsp+nofp. -set(__CPU_COMPILE_TARGET ${CMAKE_SYSTEM_PROCESSOR}) -string(REPLACE "+" ";" __CPU_FEATURES ${__CPU_COMPILE_TARGET}) -list(POP_FRONT __CPU_FEATURES CMAKE_SYSTEM_PROCESSOR) - -string(FIND ${__CPU_COMPILE_TARGET} "+" __OFFSET) -if(__OFFSET GREATER_EQUAL 0) - string(SUBSTRING ${__CPU_COMPILE_TARGET} ${__OFFSET} -1 CPU_FEATURES) -endif() - -# Add -mcpu to the compile options to override the -mcpu the CMake toolchain adds -add_compile_options(-mcpu=${__CPU_COMPILE_TARGET}) - -# Set floating point unit -if("${__CPU_COMPILE_TARGET}" MATCHES "\\+fp") - set(FLOAT hard) -elseif("${__CPU_COMPILE_TARGET}" MATCHES "\\+nofp") - set(FLOAT soft) -elseif("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m33" OR - "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55") - set(FLOAT hard) -else() - set(FLOAT soft) -endif() - -add_compile_options(-mfloat-abi=${FLOAT}) -add_link_options(-mfloat-abi=${FLOAT}) - -# Link target -add_link_options(-mcpu=${__CPU_COMPILE_TARGET}) -add_link_options(-Xlinker -Map=output.map) - -# -# Compile options -# -set(cxx_flags "-fno-unwind-tables;-fno-rtti;-fno-exceptions") - -add_compile_options("-Wall;-Wextra;-Wsign-compare;-Wunused;-Wswitch-default;\ --Wdouble-promotion;-Wredundant-decls;-Wshadow;-Wnull-dereference;\ --Wno-format-extra-args;-Wno-unused-function;-Wno-unused-label;\ --Wno-missing-field-initializers;-Wno-return-type;-Wno-format;-Wno-int-conversion" - "$<$:${cxx_flags}>" -) diff --git a/Object-Detection-example/configure_avh.sh b/Object-Detection-example/configure_avh.sh deleted file mode 100755 index 8042fd8..0000000 --- a/Object-Detection-example/configure_avh.sh +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/bash -# Copyright (c) 2022 Arm Limited and Contributors. All rights reserved. -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat < Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00080000; - -/*--------------------- DTCM RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00080000; - -/*----------------------- Data SRAM Configuration ------------------------------ - Data SRAM Configuration - DATA_SRAM Base Address <0x0-0xFFFFFFFF:8> - DATA_SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DATA_SRAM_BASE = 0x01000000; -__DATA_SRAM_SIZE = 0x00200000; - -/*--------------------- Embedded SRAM Configuration ---------------------------- - SRAM Configuration - SRAM Base Address <0x0-0xFFFFFFFF:8> - SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__SRAM_BASE = 0x21000000; -__SRAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00008000; -__HEAP_SIZE = 0x00008000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - DDR Configuration - DDR Base Address <0x0-0xFFFFFFFF:8> - DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DDR_BASE = 0x60000000; -__DDR_SIZE = 0x02000000; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - DATA_SRAM (rwx) : ORIGIN = __DATA_SRAM_BASE, LENGTH = __DATA_SRAM_SIZE - SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE - DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - /* .ddr is placed before .text so that .rodata.tvm is encountered before .rodata* */ - .ddr : - { - . = ALIGN (16); - *(.rodata.tvm) - . = ALIGN (16); - *(.data.tvm); - . = ALIGN(16); - } > DDR - - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > ITCM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - /* Add each additional data section here */ - __copy_table_end__ = .; - } > ITCM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > ITCM - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .sram : - { - . = ALIGN(16); - } > SRAM AT > SRAM - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > DTCM - - .bss.noinit (NOLOAD): - { - . = ALIGN(16); - *(.bss.noinit.*) - . = ALIGN(16); - } > DDR AT > DDR - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DTCM AT > DTCM - - .data_sram : - { - . = ALIGN(16); - } > DATA_SRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - - /* Check if data + stack exceeds DTCM limit */ - ASSERT(__StackLimit >= __bss_end__, "region DTCM overflowed with stack") -} diff --git a/Object-Detection-example/include/crt_config.h b/Object-Detection-example/include/crt_config.h deleted file mode 100644 index 2fd0ead..0000000 --- a/Object-Detection-example/include/crt_config.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef TVM_RUNTIME_CRT_CONFIG_H_ -#define TVM_RUNTIME_CRT_CONFIG_H_ - -/*! Log level of the CRT runtime */ -#define TVM_CRT_LOG_LEVEL TVM_CRT_LOG_LEVEL_DEBUG - -#endif // TVM_RUNTIME_CRT_CONFIG_H_ diff --git a/Object-Detection-example/requirements.txt b/Object-Detection-example/requirements.txt deleted file mode 100644 index d4fa373..0000000 --- a/Object-Detection-example/requirements.txt +++ /dev/null @@ -1,4 +0,0 @@ -paddlepaddle -numpy -opencv-python -typing-extensions \ No newline at end of file diff --git a/Object-Detection-example/run_demo.sh b/Object-Detection-example/run_demo.sh deleted file mode 100755 index dc9fefe..0000000 --- a/Object-Detection-example/run_demo.sh +++ /dev/null @@ -1,184 +0,0 @@ -#!/bin/bash -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat <&2 - show_usage >&2 - exit 1 - fi - ;; - - --ethosu_platform_path) - if [ $# -gt 1 ] - then - export ETHOSU_PLATFORM_PATH="$2" - shift 2 - else - echo 'ERROR: --ethosu_platform_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --fvp_path) - if [ $# -gt 1 ] - then - export PATH="$2/models/Linux64_GCC-6.4:$PATH" - shift 2 - else - echo 'ERROR: --fvp_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --cmake_path) - if [ $# -gt 1 ] - then - export CMAKE="$2" - shift 2 - else - echo 'ERROR: --cmake_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --enable_FVP) - if [ $# -gt 1 ] && [ "$2" == "1" -o "$2" == "0" ]; - then - FVP_enable="$2" - shift 2 - else - echo 'ERROR: --enable_FVP requires a right argument 1 or 0' >&2 - show_usage >&2 - exit 1 - fi - ;; - - -*|--*) - echo "Error: Unknown flag: $1" >&2 - show_usage >&2 - exit 1 - ;; - esac -done - -# Choose running environment: cloud(default) or local environment -Platform="VHT_Corstone_SSE-300_Ethos-U55" -if [ $FVP_enable == "1" ]; then - Platform="FVP_Corstone_SSE-300_Ethos-U55" - echo -e "\e[36mRun application on local Fixed Virtual Platforms (FVPs)\e[0m" -else - if [ ! -d "/opt/arm/" ]; then - sudo ./configure_avh.sh - fi -fi - -# Directories -script_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )" - -# Make build directory -make cleanall -mkdir -p build -cd build - -# Get PaddlePaddle inference model -echo -e "\e[36mDownload PaddlePaddle inference model\e[0m" -wget https://bj.bcebos.com/v1/paddledet/deploy/Inference/picodet_s_320_coco_lcnet_no_nms.tar -tar -xf picodet_s_320_coco_lcnet_no_nms.tar - -# Compile model for Arm(R) Cortex(R)-M55 CPU and CMSIS-NN -# An alternative to using "python3 -m tvm.driver.tvmc" is to call -# "tvmc" directly once TVM has been pip installed. -python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ - --target-cmsis-nn-mcpu=cortex-m55 \ - --target-c-mcpu=cortex-m55 \ - --runtime=crt \ - --executor=aot \ - --executor-aot-interface-api=c \ - --executor-aot-unpacked-api=1 \ - --pass-config tir.usmp.enable=1 \ - --pass-config tir.usmp.algorithm=hill_climb \ - --pass-config tir.disable_storage_rewrite=1 \ - --pass-config tir.disable_vectorize=1 picodet_s_320_coco_lcnet_no_nms/model.pdmodel \ - --output-format=mlf \ - --model-format=paddle \ - --module-name=picodet \ - --input-shapes image:[1,3,320,320] \ - --output=picodet.tar -tar -xf picodet.tar - -# Create C header files -cd .. -python3 ./convert_image.py ./image/000000014439_640x640.jpg - -# Build demo executable -cd ${script_dir} -echo ${script_dir} -make - -# Run demo executable on the AVH -$Platform -C cpu0.CFGDTCMSZ=15 \ --C cpu0.CFGITCMSZ=15 -C mps3_board.uart0.out_file=\"-\" -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ --C mps3_board.visualisation.disable-visualisation=1 -C mps3_board.telnetterminal0.start_telnet=0 \ --C mps3_board.telnetterminal1.start_telnet=0 -C mps3_board.telnetterminal2.start_telnet=0 -C mps3_board.telnetterminal5.start_telnet=0 \ -./build/demo --stat diff --git a/Semantic-Segmentation-example/PP-LiteSeg/Makefile b/Semantic-Segmentation-example/PP-LiteSeg/Makefile deleted file mode 100644 index cf7d375..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -# Makefile to build demo - -# Setup build environment -BUILD_DIR := build - -ARM_CPU = ARMCM55 -ETHOSU_PATH = /opt/arm/ethosu -CMSIS_PATH ?= ${ETHOSU_PATH}/cmsis -ETHOSU_PLATFORM_PATH ?= ${ETHOSU_PATH}/core_platform -STANDALONE_CRT_PATH := $(abspath $(BUILD_DIR))/runtime -CORSTONE_300_PATH = ${ETHOSU_PLATFORM_PATH}/targets/corstone-300 -PKG_COMPILE_OPTS = -g -Wall -O2 -Wno-incompatible-pointer-types -Wno-format -mcpu=cortex-m55 -mthumb -mfloat-abi=hard -std=gnu99 -CMAKE ?= cmake -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib -PKG_CFLAGS = ${PKG_COMPILE_OPTS} \ - -I${STANDALONE_CRT_PATH}/include \ - -I${STANDALONE_CRT_PATH}/src/runtime/crt/include \ - -I${PWD}/include \ - -I${CORSTONE_300_PATH} \ - -I${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Include/ \ - -I${CMSIS_PATH}/CMSIS/Core/Include \ - -I${CMSIS_PATH}/CMSIS/NN/Include \ - -I${CMSIS_PATH}/CMSIS/DSP/Include \ - -I$(abspath $(BUILD_DIR))/codegen/host/include -CMSIS_NN_CMAKE_FLAGS = -DCMAKE_TOOLCHAIN_FILE=$(abspath $(BUILD_DIR))/../arm-none-eabi-gcc.cmake \ - -DTARGET_CPU=cortex-m55 \ - -DBUILD_CMSIS_NN_FUNCTIONS=YES -PKG_LDFLAGS = -lm -specs=nosys.specs -static -T corstone300.ld - -$(ifeq VERBOSE,1) -QUIET ?= -$(else) -QUIET ?= @ -$(endif) - -DEMO_MAIN = src/demo_bare_metal.c -CODEGEN_SRCS = $(wildcard $(abspath $(BUILD_DIR))/codegen/host/src/*.c) -CODEGEN_OBJS = $(subst .c,.o,$(CODEGEN_SRCS)) -CMSIS_STARTUP_SRCS = $(wildcard ${CMSIS_PATH}/Device/ARM/${ARM_CPU}/Source/*.c) -UART_SRCS = $(wildcard ${CORSTONE_300_PATH}/*.c) - -demo: $(BUILD_DIR)/demo - -$(BUILD_DIR)/stack_allocator.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/memory/stack_allocator.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -$(BUILD_DIR)/crt_backend_api.o: $(STANDALONE_CRT_PATH)/src/runtime/crt/common/crt_backend_api.c - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) -c $(PKG_CFLAGS) -o $@ $^ - -# Build generated code -$(BUILD_DIR)/libcodegen.a: $(CODEGEN_SRCS) - $(QUIET)cd $(abspath $(BUILD_DIR)/codegen/host/src) && $(CC) -c $(PKG_CFLAGS) $(CODEGEN_SRCS) - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcodegen.a) $(CODEGEN_OBJS) - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcodegen.a) - -# Build CMSIS startup code -${BUILD_DIR}/libcmsis_startup.a: $(CMSIS_STARTUP_SRCS) - $(QUIET)mkdir -p $(abspath $(BUILD_DIR)/libcmsis_startup) - $(QUIET)cd $(abspath $(BUILD_DIR)/libcmsis_startup) && $(CC) -c $(PKG_CFLAGS) -D${ARM_CPU} $^ - $(QUIET)$(AR) -cr $(abspath $(BUILD_DIR)/libcmsis_startup.a) $(abspath $(BUILD_DIR))/libcmsis_startup/*.o - $(QUIET)$(RANLIB) $(abspath $(BUILD_DIR)/libcmsis_startup.a) - -CMSIS_SHA_FILE=${CMSIS_PATH}/977abe9849781a2e788b02282986480ff4e25ea6.sha -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -else -# Build CMSIS-NN -${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a: - $(QUIET)mkdir -p $(@D) - $(QUIET)cd $(CMSIS_PATH)/CMSIS/NN && $(CMAKE) -B $(abspath $(BUILD_DIR)/cmsis_nn) $(CMSIS_NN_CMAKE_FLAGS) - $(QUIET)cd $(abspath $(BUILD_DIR)/cmsis_nn) && $(MAKE) all -endif - -# Build demo application -ifneq ("$(wildcard $(CMSIS_SHA_FILE))","") -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a ${BUILD_DIR}/cmsis_nn/Source/libcmsis-nn.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -else -$(BUILD_DIR)/demo: $(DEMO_MAIN) $(UART_SRCS) $(BUILD_DIR)/stack_allocator.o $(BUILD_DIR)/crt_backend_api.o \ - ${BUILD_DIR}/libcodegen.a ${BUILD_DIR}/libcmsis_startup.a \ - ${BUILD_DIR}/cmsis_nn/Source/SoftmaxFunctions/libCMSISNNSoftmax.a \ - ${BUILD_DIR}/cmsis_nn/Source/FullyConnectedFunctions/libCMSISNNFullyConnected.a \ - ${BUILD_DIR}/cmsis_nn/Source/SVDFunctions/libCMSISNNSVDF.a \ - ${BUILD_DIR}/cmsis_nn/Source/ReshapeFunctions/libCMSISNNReshape.a \ - ${BUILD_DIR}/cmsis_nn/Source/ActivationFunctions/libCMSISNNActivation.a \ - ${BUILD_DIR}/cmsis_nn/Source/NNSupportFunctions/libCMSISNNSupport.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConcatenationFunctions/libCMSISNNConcatenation.a \ - ${BUILD_DIR}/cmsis_nn/Source/BasicMathFunctions/libCMSISNNBasicMaths.a \ - ${BUILD_DIR}/cmsis_nn/Source/ConvolutionFunctions/libCMSISNNConvolutions.a \ - ${BUILD_DIR}/cmsis_nn/Source/PoolingFunctions/libCMSISNNPooling.a - $(QUIET)mkdir -p $(@D) - $(QUIET)$(CC) $(PKG_CFLAGS) $(FREERTOS_FLAGS) -o $@ -Wl,--whole-archive $^ -Wl,--no-whole-archive $(PKG_LDFLAGS) -endif - -clean: - $(QUIET)rm -rf $(BUILD_DIR)/codegen - -cleanall: - $(QUIET)rm -rf $(BUILD_DIR) - -.SUFFIXES: - -.DEFAULT: demo diff --git a/Semantic-Segmentation-example/PP-LiteSeg/README.md b/Semantic-Segmentation-example/PP-LiteSeg/README.md deleted file mode 100644 index 94bc3dc..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/README.md +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - - - - - - - - - - - - -English | [简体中文](README_ch.md) - -Running PaddleSeg semantic segmentation model on bare metal Arm(R) Cortex(R)-M55 CPU using Arm Virtual Hardware -====================================================================== - -This folder contains an example of how to run a PaddleSeg model on bare metal [Cortex(R)-M55 CPU](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55) using [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware). - - -Running environment and prerequisites -------------- -Case 1: If the demo is run in Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by [AWS](https://aws.amazon.com/marketplace/pp/prodview-urbpq7yo5va7g?sr=0-1&ref_=beagle&applicationId=AWSMPContessa)/[AWS China](https://awsmarketplace.amazonaws.cn/marketplace/pp/prodview-2y7nefntbmybu), the following software will be installed through [configure_avh.sh](./configure_avh.sh) script. It will install automatically when you run the application through [run_demo.sh](./run_demo.sh) script. -You can refer to this [guide](https://arm-software.github.io/AVH/main/examples/html/MicroSpeech.html#amilaunch) to launch an Arm Virtual Hardware AMI instance. - -Case 2: If the demo is run in the [ci_cpu Docker container](https://github.com/apache/tvm/blob/main/docker/Dockerfile.ci_cpu) provided with [TVM](https://github.com/apache/tvm), then the following software will already be installed. - -Case 3: If the demo is not run in the ci_cpu Docker container, then you will need the following: -- Software required to build and run the demo (These can all be installed by running - tvm/docker/install/ubuntu_install_ethosu_driver_stack.sh.) - - [Fixed Virtual Platform (FVP) based on Arm(R) Corstone(TM)-300 software](https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps) - - [cmake 3.19.5](https://github.com/Kitware/CMake/releases/) - - [GCC toolchain from Arm(R)](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2) - - [Arm(R) Ethos(TM)-U NPU driver stack](https://review.mlplatform.org) - - [CMSIS](https://github.com/ARM-software/CMSIS_5) -- The python libraries listed in the requirements.txt of this directory - - These can be installed by running the following from the current directory: - ```bash - pip install -r ./requirements.txt - ``` - -In case2 and case3: - -You will need to update your PATH environment variable to include the path to cmake 3.19.5 and the FVP. -For example if you've installed these in ```/opt/arm``` , then you would do the following: -```bash -export PATH=/opt/arm/FVP_Corstone_SSE-300/models/Linux64_GCC-6.4:/opt/arm/cmake/bin:$PATH -``` - -You will also need TVM which can either be: - - Installed from TLCPack(see [TLCPack](https://tlcpack.ai/)) - - Built from source (see [Install from Source](https://tvm.apache.org/docs/install/from_source.html)) - - When building from source, the following need to be set in config.cmake: - - set(USE_CMSISNN ON) - - set(USE_MICRO ON) - - set(USE_LLVM ON) - - -Running the demo application ----------------------------- -Type the following command to run the bare metal text recognition application ([src/demo_bare_metal.c](./src/demo_bare_metal.c)): - -```bash -./run_demo.sh -``` - -If you are not able to use Arm Virtual Hardware Amazon Machine Image(AMI) instance hosted by AWS/AWS China, specify argument --enable_FVP to 1 to make the application run on local Fixed Virtual Platforms (FVPs) executables. - -```bash -./run_demo.sh --enable_FVP 1 -``` - -If the Ethos(TM)-U platform and/or CMSIS have not been installed in /opt/arm/ethosu then -the locations for these can be specified as arguments to run_demo.sh, for example: - -```bash -./run_demo.sh --cmsis_path /home/tvm-user/cmsis \ ---ethosu_platform_path /home/tvm-user/ethosu/core_platform -``` - -With [run_demo.sh](./run_demo.sh) to run the demo application, it will: -- Set up running environment by installing the required prerequisites automatically if running in Arm Virtual Hardware Amazon AMI instance(not specify --enable_FVP to 1) -- Download a PaddleSeg semantic segmentation model -- Use tvmc to compile the semantic segmentation model for Cortex(R)-M55 CPU and CMSIS-NN -- Create a C header file inputs.c containing the image data as a C array -- Create a C header file outputs.c containing a C array where the output of inference will be stored -- Build the demo application -- Run the demo application on a Arm Virtual Hardware based on Arm(R) Corstone(TM)-300 software -- Convert outputs to a jpg format image - -Using your own image --------------------- -The create_image.py script takes a single argument on the command line which is the path of the -image to be converted into an array of bytes for consumption by the model. - -The demo can be modified to use an image of your choice by changing the following line in run_demo.sh - -```bash -python3 ./convert_image.py path/to/image -``` - -Model description ------------------ -The example is built on [PP-LiteSeg](https://github.com/PaddlePaddle/PaddleSeg/blob/release/2.8/configs/pp_liteseg/README.md) Real-Time Semantic Segmentation model released by [PaddleSeg](https://github.com/PaddlePaddle/PaddleSeg). diff --git a/Semantic-Segmentation-example/PP-LiteSeg/arm-none-eabi-gcc.cmake b/Semantic-Segmentation-example/PP-LiteSeg/arm-none-eabi-gcc.cmake deleted file mode 100644 index 415b313..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/arm-none-eabi-gcc.cmake +++ /dev/null @@ -1,79 +0,0 @@ -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -if (__TOOLCHAIN_LOADED) - return() -endif() -set(__TOOLCHAIN_LOADED TRUE) - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -set(CMAKE_SYSTEM_PROCESSOR "cortex-m55" CACHE STRING "Select Arm(R) Cortex(R)-M architecture. (cortex-m0, cortex-m3, cortex-m33, cortex-m4, cortex-m55, cortex-m7, etc)") - -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_STANDARD 99) -set(CMAKE_CXX_STANDARD 14) - -# The system processor could for example be set to cortex-m33+nodsp+nofp. -set(__CPU_COMPILE_TARGET ${CMAKE_SYSTEM_PROCESSOR}) -string(REPLACE "+" ";" __CPU_FEATURES ${__CPU_COMPILE_TARGET}) -list(POP_FRONT __CPU_FEATURES CMAKE_SYSTEM_PROCESSOR) - -string(FIND ${__CPU_COMPILE_TARGET} "+" __OFFSET) -if(__OFFSET GREATER_EQUAL 0) - string(SUBSTRING ${__CPU_COMPILE_TARGET} ${__OFFSET} -1 CPU_FEATURES) -endif() - -# Add -mcpu to the compile options to override the -mcpu the CMake toolchain adds -add_compile_options(-mcpu=${__CPU_COMPILE_TARGET}) - -# Set floating point unit -if("${__CPU_COMPILE_TARGET}" MATCHES "\\+fp") - set(FLOAT hard) -elseif("${__CPU_COMPILE_TARGET}" MATCHES "\\+nofp") - set(FLOAT soft) -elseif("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m33" OR - "${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55") - set(FLOAT hard) -else() - set(FLOAT soft) -endif() - -add_compile_options(-mfloat-abi=${FLOAT}) -add_link_options(-mfloat-abi=${FLOAT}) - -# Link target -add_link_options(-mcpu=${__CPU_COMPILE_TARGET}) -add_link_options(-Xlinker -Map=output.map) - -# -# Compile options -# -set(cxx_flags "-fno-unwind-tables;-fno-rtti;-fno-exceptions") - -add_compile_options("-Wall;-Wextra;-Wsign-compare;-Wunused;-Wswitch-default;\ --Wdouble-promotion;-Wredundant-decls;-Wshadow;-Wnull-dereference;\ --Wno-format-extra-args;-Wno-unused-function;-Wno-unused-label;\ --Wno-missing-field-initializers;-Wno-return-type;-Wno-format;-Wno-int-conversion" - "$<$:${cxx_flags}>" -) diff --git a/Semantic-Segmentation-example/PP-LiteSeg/configure_avh.sh b/Semantic-Segmentation-example/PP-LiteSeg/configure_avh.sh deleted file mode 100644 index 8042fd8..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/configure_avh.sh +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/bash -# Copyright (c) 2022 Arm Limited and Contributors. All rights reserved. -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. - -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat < Flash Configuration - Flash Base Address <0x0-0xFFFFFFFF:8> - Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00080000; - -/*--------------------- DTCM RAM Configuration ---------------------------- - RAM Configuration - RAM Base Address <0x0-0xFFFFFFFF:8> - RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00080000; - -/*----------------------- Data SRAM Configuration ------------------------------ - Data SRAM Configuration - DATA_SRAM Base Address <0x0-0xFFFFFFFF:8> - DATA_SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DATA_SRAM_BASE = 0x01000000; -__DATA_SRAM_SIZE = 0x00200000; - -/*--------------------- Embedded SRAM Configuration ---------------------------- - SRAM Configuration - SRAM Base Address <0x0-0xFFFFFFFF:8> - SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__SRAM_BASE = 0x21000000; -__SRAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00008000; -__HEAP_SIZE = 0x00008000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - DDR Configuration - DDR Base Address <0x0-0xFFFFFFFF:8> - DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__DDR_BASE = 0x60000000; -__DDR_SIZE = 0x02000000; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - DATA_SRAM (rwx) : ORIGIN = __DATA_SRAM_BASE, LENGTH = __DATA_SRAM_SIZE - SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE - DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - /* .ddr is placed before .text so that .rodata.tvm is encountered before .rodata* */ - .ddr : - { - . = ALIGN (16); - *(.rodata.tvm) - . = ALIGN (16); - *(.data.tvm); - . = ALIGN(16); - } > DDR - - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > ITCM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - /* Add each additional data section here */ - __copy_table_end__ = .; - } > ITCM - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > ITCM - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .sram : - { - . = ALIGN(16); - } > SRAM AT > SRAM - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > DTCM - - .bss.noinit (NOLOAD): - { - . = ALIGN(16); - *(.bss.noinit.*) - . = ALIGN(16); - } > SRAM AT > SRAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DTCM AT > DTCM - - .data_sram : - { - . = ALIGN(16); - } > DATA_SRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - - /* Check if data + stack exceeds DTCM limit */ - ASSERT(__StackLimit >= __bss_end__, "region DTCM overflowed with stack") -} diff --git a/Semantic-Segmentation-example/PP-LiteSeg/image/README.md b/Semantic-Segmentation-example/PP-LiteSeg/image/README.md deleted file mode 100644 index 6f8bfe4..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/image/README.md +++ /dev/null @@ -1,3 +0,0 @@ -# About Dataset -* The test image [test.png](./test.png) for this example comes from [](https://www.cityscapes-dataset.com/) dataset `Test`. It is used for verifying the inference results of PP-LiteSeg model running on AVH Corstone 300 platform with Cortex-M55 CPU. -* The Cityscapes Dataset focuses on semantic understanding of urban street scenes. Please refer to [Cityscapes](https://www.cityscapes-dataset.com/dataset-overview/) for more features. You can use relevant dataset after accepting their [license terms](https://www.cityscapes-dataset.com/license/). It is licensed under custom [terms and conditions](https://www.cityscapes-dataset.com/license/). diff --git a/Semantic-Segmentation-example/PP-LiteSeg/image/test.png b/Semantic-Segmentation-example/PP-LiteSeg/image/test.png deleted file mode 100644 index b9c6229..0000000 Binary files a/Semantic-Segmentation-example/PP-LiteSeg/image/test.png and /dev/null differ diff --git a/Semantic-Segmentation-example/PP-LiteSeg/include/crt_config.h b/Semantic-Segmentation-example/PP-LiteSeg/include/crt_config.h deleted file mode 100644 index 4b9ccca..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/include/crt_config.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef TVM_RUNTIME_CRT_CONFIG_H_ -#define TVM_RUNTIME_CRT_CONFIG_H_ - -/*! Log level of the CRT runtime */ -#define TVM_CRT_LOG_LEVEL TVM_CRT_LOG_LEVEL_DEBUG - -#endif // TVM_RUNTIME_CRT_CONFIG_H_ diff --git a/Semantic-Segmentation-example/PP-LiteSeg/include/tvm_runtime.h b/Semantic-Segmentation-example/PP-LiteSeg/include/tvm_runtime.h deleted file mode 100644 index 2b59d93..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/include/tvm_runtime.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void __attribute__((noreturn)) TVMPlatformAbort(tvm_crt_error_t error_code) { - printf("TVMPlatformAbort: %d\n", error_code); - printf("EXITTHESIM\n"); - exit(-1); -} - -tvm_crt_error_t TVMPlatformMemoryAllocate(size_t num_bytes, DLDevice dev, void** out_ptr) { - return kTvmErrorFunctionCallNotImplemented; -} - -tvm_crt_error_t TVMPlatformMemoryFree(void* ptr, DLDevice dev) { - return kTvmErrorFunctionCallNotImplemented; -} - -void TVMLogf(const char* msg, ...) { - va_list args; - va_start(args, msg); - vfprintf(stdout, msg, args); - va_end(args); -} - -TVM_DLL int TVMFuncRegisterGlobal(const char* name, TVMFunctionHandle f, int override) { return 0; } - -#ifdef __cplusplus -} -#endif diff --git a/Semantic-Segmentation-example/PP-LiteSeg/requirements.txt b/Semantic-Segmentation-example/PP-LiteSeg/requirements.txt deleted file mode 100644 index a1a8626..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/requirements.txt +++ /dev/null @@ -1,4 +0,0 @@ -paddlepaddle -numpy -opencv-python -typing-extensions diff --git a/Semantic-Segmentation-example/PP-LiteSeg/run_demo.sh b/Semantic-Segmentation-example/PP-LiteSeg/run_demo.sh deleted file mode 100644 index 6812707..0000000 --- a/Semantic-Segmentation-example/PP-LiteSeg/run_demo.sh +++ /dev/null @@ -1,186 +0,0 @@ -#!/bin/bash -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations -# under the License. -set -e -set -u -set -o pipefail - -# Show usage -function show_usage() { - cat <&2 - show_usage >&2 - exit 1 - fi - ;; - - --ethosu_platform_path) - if [ $# -gt 1 ] - then - export ETHOSU_PLATFORM_PATH="$2" - shift 2 - else - echo 'ERROR: --ethosu_platform_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --fvp_path) - if [ $# -gt 1 ] - then - export PATH="$2/models/Linux64_GCC-6.4:$PATH" - shift 2 - else - echo 'ERROR: --fvp_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --cmake_path) - if [ $# -gt 1 ] - then - export CMAKE="$2" - shift 2 - else - echo 'ERROR: --cmake_path requires a non-empty argument' >&2 - show_usage >&2 - exit 1 - fi - ;; - - --enable_FVP) - if [ $# -gt 1 ] && [ "$2" == "1" -o "$2" == "0" ]; - then - FVP_enable="$2" - shift 2 - else - echo 'ERROR: --enable_FVP requires a right argument 1 or 0' >&2 - show_usage >&2 - exit 1 - fi - ;; - - -*|--*) - echo "Error: Unknown flag: $1" >&2 - show_usage >&2 - exit 1 - ;; - esac -done - -# Choose running environment: cloud(default) or local environment -Platform="VHT_Corstone_SSE-300_Ethos-U55" -if [ $FVP_enable == "1" ]; then - Platform="FVP_Corstone_SSE-300_Ethos-U55" - echo -e "\e[36mRun application on local Fixed Virtual Platforms (FVPs)\e[0m" -else - if [ ! -d "/opt/arm/" ]; then - sudo ./configure_avh.sh - fi -fi - -# Directories -script_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )" - -# Make build directory -make cleanall -mkdir -p build -cd build - -# Get PaddlePaddle inference model -wget https://paddleseg.bj.bcebos.com/dygraph/demo/pp_liteseg_infer_model.tar.gz -tar -zxvf pp_liteseg_infer_model.tar.gz - -# Compile model for Arm(R) Cortex(R)-M55 CPU and CMSIS-NN -# An alternative to using "python3 -m tvm.driver.tvmc" is to call -# "tvmc" directly once TVM has been pip installed. -python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ - --target-cmsis-nn-mcpu=cortex-m55 \ - --target-c-mcpu=cortex-m55 \ - --runtime=crt \ - --executor=aot \ - --executor-aot-interface-api=c \ - --executor-aot-unpacked-api=1 \ - --pass-config tir.usmp.enable=1 \ - --pass-config tir.usmp.algorithm=hill_climb \ - --pass-config tir.disable_storage_rewrite=1 \ - --pass-config tir.disable_vectorize=1 pp_liteseg_infer_model/model.pdmodel \ - --output-format=mlf \ - --model-format=paddle \ - --module-name=seg \ - --input-shapes x:[1,3,64,128] \ - --output=seg.tar -tar -xf seg.tar - -# Create C header files -cd .. -python3 ./convert_image.py image/test.png - -# Build demo executable -cd ${script_dir} -echo ${script_dir} -make - -# Run demo executable on the AVH -$Platform -C cpu0.CFGDTCMSZ=15 \ --C cpu0.CFGITCMSZ=15 -C mps3_board.uart0.out_file=\"./build/uart0.txt\" -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ --C mps3_board.visualisation.disable-visualisation=1 -C mps3_board.telnetterminal0.start_telnet=0 \ --C mps3_board.telnetterminal1.start_telnet=0 -C mps3_board.telnetterminal2.start_telnet=0 -C mps3_board.telnetterminal5.start_telnet=0 \ -./build/demo --stat - -# Convert outputs to image -python3 ./convert_outputs.py ./build/uart0.txt diff --git a/object_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h b/object_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 b/object_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/object_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 b/object_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/device_cfg.h b/object_classification/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 b/object_classification/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct b/object_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 b/object_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_classification/RTE/Device/SSE-300-MPS3/region_defs.h b/object_classification/RTE/Device/SSE-300-MPS3/region_defs.h new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/region_defs.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 b/object_classification/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/region_limits.h b/object_classification/RTE/Device/SSE-300-MPS3/region_limits.h new file mode 100644 index 0000000..20ccc08 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/region_limits.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x00000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 b/object_classification/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/object_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/object_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/object_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/object_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/object_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h b/object_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 b/object_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h b/object_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 b/object_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct b/object_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 b/object_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c b/object_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 b/object_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c b/object_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 b/object_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/object_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_classification/RTE/_MobileNetV3M55/RTE_Components.h b/object_classification/RTE/_MobileNetV3M55/RTE_Components.h new file mode 100644 index 0000000..f41ccc6 --- /dev/null +++ b/object_classification/RTE/_MobileNetV3M55/RTE_Components.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_classification+MobileNetV3M55' + * Target: 'MobileNetV3M55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/object_classification/RTE/_MobileNetV3M85/RTE_Components.h b/object_classification/RTE/_MobileNetV3M85/RTE_Components.h new file mode 100644 index 0000000..5a18a77 --- /dev/null +++ b/object_classification/RTE/_MobileNetV3M85/RTE_Components.h @@ -0,0 +1,32 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_classification+MobileNetV3M85' + * Target: 'MobileNetV3M85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/object_classification/RTE/_PPLCNetM55/RTE_Components.h b/object_classification/RTE/_PPLCNetM55/RTE_Components.h new file mode 100644 index 0000000..5ab2c71 --- /dev/null +++ b/object_classification/RTE/_PPLCNetM55/RTE_Components.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_classification+PPLCNetM55' + * Target: 'PPLCNetM55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/object_classification/RTE/_PPLCNetM85/RTE_Components.h b/object_classification/RTE/_PPLCNetM85/RTE_Components.h new file mode 100644 index 0000000..7c6c168 --- /dev/null +++ b/object_classification/RTE/_PPLCNetM85/RTE_Components.h @@ -0,0 +1,32 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_classification+PPLCNetM85' + * Target: 'PPLCNetM85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Object-Classification-example/PP-LCNet/convert_image.py b/object_classification/convert_image.py similarity index 95% rename from Object-Classification-example/PP-LCNet/convert_image.py rename to object_classification/convert_image.py index df061ce..e2037ca 100755 --- a/Object-Classification-example/PP-LCNet/convert_image.py +++ b/object_classification/convert_image.py @@ -78,7 +78,7 @@ def create_header_file(name, tensor_name, tensor_data, output_path): file_path = pathlib.Path(f"{output_path}/" + name).resolve() # Create header file with npy_data as a C array raw_path = file_path.with_suffix(".h").resolve() - with open(raw_path, "w") as header_file: + with open(raw_path, "w+") as header_file: header_file.write( "\n" + f"const size_t {tensor_name}_len = {tensor_data.size};\n" @@ -95,25 +95,18 @@ def create_headers(img_path): """ This function generates C header files for the input and output arrays required to run inferences """ - + # Create input header file # Resize image to 32x320 img = cv2.imread(img_path) img = resize_norm_img(img) img_data = img.astype("float32") - # Add the batch dimension, as we are expecting 4-dimensional input: NCHW. img_data = np.expand_dims(img_data, axis=0) - - # Create input header file create_header_file("inputs", "input", img_data, "include") + # Create output header file output_data = np.zeros([1000], np.float32) - create_header_file( - "outputs", - "output", - output_data, - "include", - ) + create_header_file("outputs", "output", output_data, "include") if __name__ == "__main__": diff --git a/Object-Classification-example/PP-LCNet/labels/convert_labels.py b/object_classification/convert_labels.py similarity index 96% rename from Object-Classification-example/PP-LCNet/labels/convert_labels.py rename to object_classification/convert_labels.py index 3b3516a..c8c0ba3 100644 --- a/Object-Classification-example/PP-LCNet/labels/convert_labels.py +++ b/object_classification/convert_labels.py @@ -27,7 +27,7 @@ def create_labels_header(labels_file, section, output_path): file_path = pathlib.Path(f"{output_path}/labels.h").resolve() with open(labels_path) as f: labels = f.readlines() - with open(file_path, "w") as header_file: + with open(file_path, "w+") as header_file: header_file.write(f'char* labels[] __attribute__((section("{section}"), aligned(16))) = {{') for _, label in enumerate(labels): diff --git a/Object-Classification-example/PP-LCNet/image/ILSVRC2012_val_00020010.jpg b/object_classification/image/ILSVRC2012_val_00020010.jpg similarity index 100% rename from Object-Classification-example/PP-LCNet/image/ILSVRC2012_val_00020010.jpg rename to object_classification/image/ILSVRC2012_val_00020010.jpg diff --git a/Object-Classification-example/PP-LCNet/image/README.md b/object_classification/image/README.md similarity index 71% rename from Object-Classification-example/PP-LCNet/image/README.md rename to object_classification/image/README.md index bfebe8a..528834c 100644 --- a/Object-Classification-example/PP-LCNet/image/README.md +++ b/object_classification/image/README.md @@ -1,3 +1,3 @@ # About Dataset -* The test image [ILSVRC2012_val_00020010.jpg](./ILSVRC2012_val_00020010.jpg) for this example comes from [ILSVRC2012](https://www.image-net.org/) dataset `Val images`. It is used for verifying the inference results of PP-LCNet model running on AVH Corstone 300 platform with Cortex-M55 CPU. +* The test image [ILSVRC2012_val_00020010.jpg](ILSVRC2012_val_00020010.jpg) for this example comes from [ILSVRC2012](https://www.image-net.org/) dataset `Val images`. It is used for verifying the inference results of PP-LCNet model running on AVH Corstone 300 platform with Cortex-M55 CPU. * ImagetNet is an image database organized according to the WordNet hierarchy (currently only the nouns), in which each node of the hierarchy is depicted by hundreds and thousands of images. The project has been instrumental in advancing computer vision and deep learning research. The data is available for free to researchers for non-commercial use. Please refer to [ImageNet](https://www.image-net.org/index.php) for more features. You can use relevant dataset after accepting their [Terms of access](https://image-net.org/download). You can also visit [kaggle](https://www.kaggle.com/competitions/imagenet-object-localization-challenge/data) page to obtain the images. It is licensed by [CC BY 4.0](https://www.image-net.org/). diff --git a/Object-Classification-example/PP-LCNet/include/crt_config.h b/object_classification/include/crt_config.h similarity index 76% rename from Object-Classification-example/PP-LCNet/include/crt_config.h rename to object_classification/include/crt_config.h index 4b9ccca..4013721 100644 --- a/Object-Classification-example/PP-LCNet/include/crt_config.h +++ b/object_classification/include/crt_config.h @@ -17,10 +17,12 @@ * under the License. */ -#ifndef TVM_RUNTIME_CRT_CONFIG_H_ -#define TVM_RUNTIME_CRT_CONFIG_H_ - +/*! + * \file tvm/runtime/crt_config.h.template + * \brief Template for CRT configuration, to be modified on each target. + */ +#ifndef TVM_RUNTIME_CRT_CRT_CONFIG_TEMPLATE_H_ +#define TVM_RUNTIME_CRT_CRT_CONFIG_TEMPLATE_H_ /*! Log level of the CRT runtime */ #define TVM_CRT_LOG_LEVEL TVM_CRT_LOG_LEVEL_DEBUG - -#endif // TVM_RUNTIME_CRT_CONFIG_H_ +#endif // TVM_RUNTIME_CRT_CRT_CONFIG_TEMPLATE_H_ diff --git a/Object-Classification-example/MobileNetV3_small_x0_35/include/tvm_runtime.h b/object_classification/include/tvm_runtime.h similarity index 91% rename from Object-Classification-example/MobileNetV3_small_x0_35/include/tvm_runtime.h rename to object_classification/include/tvm_runtime.h index 0978d7a..ba16b83 100644 --- a/Object-Classification-example/MobileNetV3_small_x0_35/include/tvm_runtime.h +++ b/object_classification/include/tvm_runtime.h @@ -16,7 +16,6 @@ * specific language governing permissions and limitations * under the License. */ - #include #include #include @@ -49,11 +48,7 @@ void TVMLogf(const char *msg, ...) { va_end(args); } -TVM_DLL int TVMFuncRegisterGlobal(const char *name, TVMFunctionHandle f, - int override) { - return 0; -} - +TVM_DLL int TVMFuncRegisterGlobal(const char* name, TVMFunctionHandle f, int override) { return 0; } #ifdef __cplusplus } -#endif +#endif \ No newline at end of file diff --git a/Object-Classification-example/PP-LCNet/labels/README.md b/object_classification/labels/README.md similarity index 100% rename from Object-Classification-example/PP-LCNet/labels/README.md rename to object_classification/labels/README.md diff --git a/Object-Classification-example/PP-LCNet/labels/labels.txt b/object_classification/labels/labels.txt similarity index 100% rename from Object-Classification-example/PP-LCNet/labels/labels.txt rename to object_classification/labels/labels.txt diff --git a/object_classification/main.c b/object_classification/main.c new file mode 100644 index 0000000..b3d6c50 --- /dev/null +++ b/object_classification/main.c @@ -0,0 +1,37 @@ +#include +#include +#include +#include +#include + +#include "labels.h" + +#include "inputs.h" +#include "outputs.h" +#include "stdout_USART.h" + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +__asm(" .global __ARM_use_no_argv\n"); +#endif + +int main(){ + stdout_init(); +#if USE_MOBILENETV3 || USE_PP_LCNET + struct tvmgen_cls_inputs cls_inputs = { + .x = input, + }; +#endif + struct tvmgen_cls_outputs cls_outputs = { + .output = output, + }; + + tvmgen_cls_run(&cls_inputs, &cls_outputs); + int index = 0; + for(int i = 0; i < output_len;i++){ + if(output[i] > output[index]){ + index = i; + } + } + printf("Index is %d; Confidence is %f; Label is %s\n", index, output[index], labels[index]); + printf("EXITTHESIM\r\n"); +} diff --git a/object_classification/object_classification+MobileNetV3M55.cbuild.yml b/object_classification/object_classification+MobileNetV3M55.cbuild.yml new file mode 100644 index 0000000..3d1b66f --- /dev/null +++ b/object_classification/object_classification+MobileNetV3M55.cbuild.yml @@ -0,0 +1,447 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_classification.csolution.yml + project: object_classification.cproject.yml + context: object_classification+MobileNetV3M55 + compiler: AC6 + device: SSE-300-MPS3 + device-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M55 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_MOBILENETV3 + - _RTE_ + add-path: + - cls/codegen/host/include + - cls/runtime/include + - include + - RTE/Device/SSE-300-MPS3 + - RTE/_MobileNetV3M55 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Include + output-dirs: + intdir: tmp/object_classification/MobileNetV3M55 + outdir: out/object_classification/MobileNetV3M55 + rtedir: RTE + output: + - type: elf + file: object_classification.axf + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + condition: SSE-300-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-300-MPS3/RTE_Device.h + category: header + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/cmsis_driver_config.h + category: header + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/device_cfg.h + category: header + attr: config + version: 1.1.3 + - component: ARM::Device:Native Driver:IO@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.0 + condition: SSE-300-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-300-MPS3/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct + category: linkerScript + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - component: ARM::Device:USART STDOUT@1.0.0 + condition: SSE-300-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:USART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-300.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: Cls + files: + - file: cls/codegen/host/src/cls_lib0.c + category: sourceC + - file: cls/codegen/host/src/cls_lib1.c + category: sourceC + - file: cls/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_MobileNetV3M55/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.1.0 + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + - component: ARM::Device:Native Driver:Timeout@1.0.0 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:USART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_classification/object_classification+MobileNetV3M55.cprj b/object_classification/object_classification+MobileNetV3M55.cprj new file mode 100644 index 0000000..f915c75 --- /dev/null +++ b/object_classification/object_classification+MobileNetV3M55.cprj @@ -0,0 +1,68 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_MOBILENETV3 + cls/codegen/host/include;cls/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_classification/object_classification+MobileNetV3M85.cbuild.yml b/object_classification/object_classification+MobileNetV3M85.cbuild.yml new file mode 100644 index 0000000..ab6f100 --- /dev/null +++ b/object_classification/object_classification+MobileNetV3M85.cbuild.yml @@ -0,0 +1,445 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_classification.csolution.yml + project: object_classification.cproject.yml + context: object_classification+MobileNetV3M85 + compiler: AC6 + device: SSE-310-MPS3_FVP + device-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M85 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_MOBILENETV3 + - CORSTONE310_FVP + - _RTE_ + add-path: + - cls/codegen/host/include + - cls/runtime/include + - include + - RTE/Device/SSE-310-MPS3_FVP + - RTE/_MobileNetV3M85 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Include + output-dirs: + intdir: tmp/object_classification/MobileNetV3M85 + outdir: out/object_classification/MobileNetV3M85 + rtedir: RTE + output: + - type: elf + file: object_classification.axf + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + condition: SSE-310-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/device_cfg.h + category: header + attr: config + version: 1.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.1 + condition: SSE-310-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-310-MPS3_FVP/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct + category: linkerScript + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - component: ARM::Device:UART STDOUT@1.0.0 + condition: SSE-310-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:UART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-310.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: Cls + files: + - file: cls/codegen/host/src/cls_lib0.c + category: sourceC + - file: cls/codegen/host/src/cls_lib1.c + category: sourceC + - file: cls/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_MobileNetV3M85/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + - component: ARM::Device:Native Driver:Timeout@1.0.1 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:UART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_classification/object_classification+MobileNetV3M85.cprj b/object_classification/object_classification+MobileNetV3M85.cprj new file mode 100644 index 0000000..ff3df8e --- /dev/null +++ b/object_classification/object_classification+MobileNetV3M85.cprj @@ -0,0 +1,67 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_MOBILENETV3 + cls/codegen/host/include;cls/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_classification/object_classification+PPLCNetM55.cbuild.yml b/object_classification/object_classification+PPLCNetM55.cbuild.yml new file mode 100644 index 0000000..dc0603a --- /dev/null +++ b/object_classification/object_classification+PPLCNetM55.cbuild.yml @@ -0,0 +1,447 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_classification.csolution.yml + project: object_classification.cproject.yml + context: object_classification+PPLCNetM55 + compiler: AC6 + device: SSE-300-MPS3 + device-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M55 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_PP_LCNET + - _RTE_ + add-path: + - cls/codegen/host/include + - cls/runtime/include + - include + - RTE/Device/SSE-300-MPS3 + - RTE/_PPLCNetM55 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Include + output-dirs: + intdir: tmp/object_classification/PPLCNetM55 + outdir: out/object_classification/PPLCNetM55 + rtedir: RTE + output: + - type: elf + file: object_classification.axf + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + condition: SSE-300-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-300-MPS3/RTE_Device.h + category: header + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/cmsis_driver_config.h + category: header + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/device_cfg.h + category: header + attr: config + version: 1.1.3 + - component: ARM::Device:Native Driver:IO@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.0 + condition: SSE-300-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-300-MPS3/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct + category: linkerScript + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - component: ARM::Device:USART STDOUT@1.0.0 + condition: SSE-300-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:USART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-300.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: Cls + files: + - file: cls/codegen/host/src/cls_lib0.c + category: sourceC + - file: cls/codegen/host/src/cls_lib1.c + category: sourceC + - file: cls/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_PPLCNetM55/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.1.0 + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + - component: ARM::Device:Native Driver:Timeout@1.0.0 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:USART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_classification/object_classification+PPLCNetM55.cprj b/object_classification/object_classification+PPLCNetM55.cprj new file mode 100644 index 0000000..e5551b0 --- /dev/null +++ b/object_classification/object_classification+PPLCNetM55.cprj @@ -0,0 +1,68 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_PP_LCNET + cls/codegen/host/include;cls/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_classification/object_classification+PPLCNetM85.cbuild.yml b/object_classification/object_classification+PPLCNetM85.cbuild.yml new file mode 100644 index 0000000..e735182 --- /dev/null +++ b/object_classification/object_classification+PPLCNetM85.cbuild.yml @@ -0,0 +1,445 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_classification.csolution.yml + project: object_classification.cproject.yml + context: object_classification+PPLCNetM85 + compiler: AC6 + device: SSE-310-MPS3_FVP + device-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M85 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_PP_LCNET + - CORSTONE310_FVP + - _RTE_ + add-path: + - cls/codegen/host/include + - cls/runtime/include + - include + - RTE/Device/SSE-310-MPS3_FVP + - RTE/_PPLCNetM85 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Include + output-dirs: + intdir: tmp/object_classification/PPLCNetM85 + outdir: out/object_classification/PPLCNetM85 + rtedir: RTE + output: + - type: elf + file: object_classification.axf + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + condition: SSE-310-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/device_cfg.h + category: header + attr: config + version: 1.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.1 + condition: SSE-310-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-310-MPS3_FVP/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct + category: linkerScript + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - component: ARM::Device:UART STDOUT@1.0.0 + condition: SSE-310-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:UART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-310.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: Cls + files: + - file: cls/codegen/host/src/cls_lib0.c + category: sourceC + - file: cls/codegen/host/src/cls_lib1.c + category: sourceC + - file: cls/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_PPLCNetM85/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + - component: ARM::Device:Native Driver:Timeout@1.0.1 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:UART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_classification/object_classification+PPLCNetM85.cprj b/object_classification/object_classification+PPLCNetM85.cprj new file mode 100644 index 0000000..9463e32 --- /dev/null +++ b/object_classification/object_classification+PPLCNetM85.cprj @@ -0,0 +1,67 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_PP_LCNET + cls/codegen/host/include;cls/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_classification/object_classification.cbuild-idx.yml b/object_classification/object_classification.cbuild-idx.yml new file mode 100644 index 0000000..7e607de --- /dev/null +++ b/object_classification/object_classification.cbuild-idx.yml @@ -0,0 +1,18 @@ +build-idx: + generated-by: csolution version 2.2.1 + csolution: object_classification.csolution.yml + cprojects: + - cproject: object_classification.cproject.yml + cbuilds: + - cbuild: object_classification+MobileNetV3M55.cbuild.yml + project: object_classification + configuration: +MobileNetV3M55 + - cbuild: object_classification+MobileNetV3M85.cbuild.yml + project: object_classification + configuration: +MobileNetV3M85 + - cbuild: object_classification+PPLCNetM55.cbuild.yml + project: object_classification + configuration: +PPLCNetM55 + - cbuild: object_classification+PPLCNetM85.cbuild.yml + project: object_classification + configuration: +PPLCNetM85 diff --git a/object_classification/object_classification.cbuild-pack.yml b/object_classification/object_classification.cbuild-pack.yml new file mode 100644 index 0000000..b595c18 --- /dev/null +++ b/object_classification/object_classification.cbuild-pack.yml @@ -0,0 +1,20 @@ +cbuild-pack: + resolved-packs: + - resolved-pack: ARM::CMSIS@5.9.0 + selected-by: + - ARM::CMSIS + - resolved-pack: ARM::CMSIS-DSP@1.15.0 + selected-by: + - ARM::CMSIS-DSP + - resolved-pack: ARM::CMSIS-NN@4.1.0 + selected-by: + - ARM::CMSIS-NN + - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: + - ARM::V2M_MPS3_SSE_300_BSP + - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: + - ARM::V2M_MPS3_SSE_310_BSP + - resolved-pack: Keil::ARM_Compiler@1.7.2 + selected-by: + - Keil::ARM_Compiler diff --git a/object_classification/object_classification.cproject.yml b/object_classification/object_classification.cproject.yml new file mode 100644 index 0000000..b8c51a6 --- /dev/null +++ b/object_classification/object_classification.cproject.yml @@ -0,0 +1,194 @@ +project: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - pack: ARM::V2M_MPS3_SSE_310_BSP + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - pack: ARM::CMSIS + - pack: ARM::CMSIS-DSP + - pack: ARM::CMSIS-NN + - pack: Keil::ARM_Compiler + setups: + - setup: Options for MobileNetV3M55, MobileNetV3M85 + for-context: + - +MobileNetV3M55 + - +MobileNetV3M85 + processor: + trustzone: "off" + add-path: + - cls/codegen/host/include + - cls/runtime/include + - include + debug: "on" + define: + - USE_MOBILENETV3 + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + - setup: Options for PPLCNetM55, PPLCNetM85 + for-context: + - +PPLCNetM55 + - +PPLCNetM85 + processor: + trustzone: "off" + add-path: + - cls/codegen/host/include + - cls/runtime/include + - include + debug: "on" + define: + - USE_PP_LCNET + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + linker: + - script: sct/VHT_Corstone_SSE-300.sct + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - script: sct/VHT_Corstone_SSE-310.sct + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + groups: + - group: Source + files: + - file: main.c + - group: Cls + files: + - file: cls/codegen/host/src/cls_lib0.c + - file: cls/codegen/host/src/cls_lib1.c + - file: cls/runtime/src/runtime/crt/common/crt_backend_api.c + components: + - component: ARM::CMSIS Driver:USART + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::CMSIS Driver:USART + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source + - component: ARM::CMSIS:NN Lib + - component: ARM::Device:Definition + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::Device:Definition + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:Native Driver:IO + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:Native Driver:IO + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::Device:Native Driver:SysCounter + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:Native Driver:SysCounter + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::Device:Native Driver:SysTimer + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:Native Driver:SysTimer + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::Device:Native Driver:Timeout + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::Device:Native Driver:Timeout + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:Native Driver:UART + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::Device:Native Driver:UART + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:Startup&C Startup + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: ARM::Device:Startup&C Startup + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:UART STDOUT + for-context: + - +MobileNetV3M85 + - +PPLCNetM85 + - component: ARM::Device:USART STDOUT + for-context: + - +MobileNetV3M55 + - +PPLCNetM55 + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User diff --git a/object_classification/object_classification.csolution.yml b/object_classification/object_classification.csolution.yml new file mode 100644 index 0000000..f31694e --- /dev/null +++ b/object_classification/object_classification.csolution.yml @@ -0,0 +1,19 @@ +solution: + created-by: uv2csolution@1.2.0 + created-for: CMSIS-Toolbox@2.0.0 + compiler: AC6 + target-types: + - type: MobileNetV3M55 + device: SSE-300-MPS3 + optimize: none + - type: MobileNetV3M85 + device: SSE-310-MPS3_FVP + optimize: none + - type: PPLCNetM55 + device: SSE-300-MPS3 + optimize: none + - type: PPLCNetM85 + device: SSE-310-MPS3_FVP + optimize: none + projects: + - project: object_classification.cproject.yml diff --git a/object_classification/object_classification.uvprojx b/object_classification/object_classification.uvprojx new file mode 100644 index 0000000..3041e2b --- /dev/null +++ b/object_classification/object_classification.uvprojx @@ -0,0 +1,2305 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + MobileNetV3_M55 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-300-MPS3 + ARM + ARM.V2M_MPS3_SSE_300_BSP.1.4.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00080000) XRAM2(0x01000000,0x00100000) XRAM3(0x20000000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h + + + + + + + + + + $$Device:SSE-300-MPS3$SVD\SSE300.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + object_classification + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x20000 + + + 0 + 0x20040000 + 0x20000 + + + 0 + 0x0 + 0x80000 + + + 0 + 0x1000000 + 0x200000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_MOBILENETV3 + + .\cls\codegen\host\include;.\cls\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-300.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + Cls + + + cls_lib0.c + 1 + .\cls\codegen\host\src\cls_lib0.c + + + cls_lib1.c + 1 + .\cls\codegen\host\src\cls_lib1.c + + + crt_backend_api.c + 1 + .\cls\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + + + MobileNetV3_M85 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-310-MPS3_FVP + ARM + ARM.V2M_MPS3_SSE_310_BSP.1.3.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00008000) XRAM2(0x01000000,0x00200000) XRAM3(0x20000000,0x00002000) CPUTYPE("Cortex-M85") FPU3(DFPU) DSP TZ MVE(FP) PACBTI CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-310-MPS3_FVP$Device\Include\SSE310MPS3.h + + + + + + + + + + $$Device:SSE-310-MPS3_FVP$SVD\SSE310.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + object_classification + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1000000 + 0x200000 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x30000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_MOBILENETV3 + + .\cls\codegen\host\include;.\cls\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-310.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + Cls + + + cls_lib0.c + 1 + .\cls\codegen\host\src\cls_lib0.c + + + cls_lib1.c + 1 + .\cls\codegen\host\src\cls_lib1.c + + + crt_backend_api.c + 1 + .\cls\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::CMSIS Driver + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Compiler + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + PP_LCNet_M55 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-300-MPS3 + ARM + ARM.V2M_MPS3_SSE_300_BSP.1.4.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00080000) XRAM2(0x01000000,0x00100000) XRAM3(0x20000000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h + + + + + + + + + + $$Device:SSE-300-MPS3$SVD\SSE300.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + object_classification + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x20000 + + + 0 + 0x20040000 + 0x20000 + + + 0 + 0x0 + 0x80000 + + + 0 + 0x1000000 + 0x200000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_PP_LCNET + + .\cls\codegen\host\include;.\cls\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-300.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + Cls + + + cls_lib0.c + 1 + .\cls\codegen\host\src\cls_lib0.c + + + cls_lib1.c + 1 + .\cls\codegen\host\src\cls_lib1.c + + + crt_backend_api.c + 1 + .\cls\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + + + PP_LCNet_M85 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-310-MPS3_FVP + ARM + ARM.V2M_MPS3_SSE_310_BSP.1.3.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00008000) XRAM2(0x01000000,0x00200000) XRAM3(0x20000000,0x00002000) CPUTYPE("Cortex-M85") FPU3(DFPU) DSP TZ MVE(FP) PACBTI CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-310-MPS3_FVP$Device\Include\SSE310MPS3.h + + + + + + + + + + $$Device:SSE-310-MPS3_FVP$SVD\SSE310.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + object_classification + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1000000 + 0x200000 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x30000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_PP_LCNET + + .\cls\codegen\host\include;.\cls\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-310.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + Cls + + + cls_lib0.c + 1 + .\cls\codegen\host\src\cls_lib0.c + + + cls_lib1.c + 1 + .\cls\codegen\host\src\cls_lib1.c + + + crt_backend_api.c + 1 + .\cls\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM85\ARMCM85_ac6.sct + + + + + + RTE\Device\ARMCM85\startup_ARMCM85.c + + + + + + RTE\Device\ARMCM85\system_ARMCM85.c + + + + + + RTE\Device\SSE-300-MPS3\RTE_Device.h + + + + + + + + + RTE\Device\SSE-300-MPS3\cmsis_driver_config.h + + + + + + + + + RTE\Device\SSE-300-MPS3\device_cfg.h + + + + + + + + + RTE\Device\SSE-300-MPS3\linker_SSE300MPS3_secure.sct + + + + + + + + + RTE\Device\SSE-300-MPS3\region_defs.h + + + + + + + + + RTE\Device\SSE-300-MPS3\region_limits.h + + + + + + + + + RTE\Device\SSE-300-MPS3\startup_SSE300MPS3.c + + + + + + + + + RTE\Device\SSE-300-MPS3\system_SSE300MPS3.c + + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\cmsis_driver_config.h + + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\device_cfg.h + + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\linker_SSE310MPS3_secure.sct + + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_defs.h + + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_limits.h + + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\startup_SSE310MPS3.c + + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\system_SSE310MPS3.c + + + + + + + + + + + + + + base_project + 1 + + + + + diff --git a/object_classification/run_demo.sh b/object_classification/run_demo.sh new file mode 100644 index 0000000..1962408 --- /dev/null +++ b/object_classification/run_demo.sh @@ -0,0 +1,154 @@ +#!/bin/bash + +# Show usage +function show_usage() { + cat <&2 + show_usage >&2 + exit 1 + fi + ;; + + --device) + if [ $# -gt 1 ] + then + export DEVICE="$2" + shift 2 + else + echo 'ERROR: --device requires a non-empty argument' >&2 + show_usage >&2 + exit 1 + fi + ;; + + -*|--*) + echo "Error: Unknown flag: $1" >&2 + show_usage >&2 + exit 1 + ;; + esac +done + +echo "Device name is $DEVICE" +if [ "$DEVICE" == "cortex-m55" ]; then + RUN_DEVICE_NAME="M55" + VHT_Platform="VHT_MPS3_Corstone_SSE-300" + TVM_TARGET="cortex-m55" +elif [ "$DEVICE" == "cortex-m85" ]; then + RUN_DEVICE_NAME="M85" + VHT_Platform="VHT_Corstone_SSE-310" + TVM_TARGET="cortex-m85" +else + echo 'ERROR: --device only support cortex-m55/cortex-m85' >&2 + exit 1 +fi + +# download paddle model +echo "Model name is $MODEL_NAME" +if [ "$MODEL_NAME" == "MobileNetV3" ]; then + wget "https://paddle-imagenet-models-name.bj.bcebos.com/dygraph/inference/MobileNetV3_small_x0_35_ssld_infer.tar" + tar -xf MobileNetV3_small_x0_35_ssld_infer.tar + rm MobileNetV3_small_x0_35_ssld_infer.tar + mv MobileNetV3_small_x0_35_ssld_infer/inference "${PWD}/model" + rm -rf MobileNetV3_small_x0_35_ssld_infer +elif [ "$MODEL_NAME" == "PP_LCNet" ]; then + wget "https://paddle-imagenet-models-name.bj.bcebos.com/dygraph/inference/PPLCNet_x0_75_infer.tar" + tar -xf PPLCNet_x0_75_infer.tar + rm PPLCNet_x0_75_infer.tar + mv PPLCNet_x0_75_infer "${PWD}/model" + MODEL_NAME="PPLCNet" +else + echo 'ERROR: --model_name only support MobileNetV3/PP_LCNet' >&2 + exit 1 +fi + +# convert paddle model to onnx model +paddle2onnx --model_dir "${PWD}/model" \ + --model_filename inference.pdmodel \ + --params_filename inference.pdiparams \ + --save_file inference.onnx +rm -rf "${PWD}/model" + +# convert onnx model to tvm model +python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ + --target-cmsis-nn-mcpu=$TVM_TARGET \ + --target-c-mcpu=$TVM_TARGET \ + --runtime=crt \ + --executor=aot \ + --executor-aot-interface-api=c \ + --executor-aot-unpacked-api=1 \ + --pass-config tir.usmp.enable=1 \ + --pass-config tir.usmp.algorithm=hill_climb \ + --pass-config tir.disable_storage_rewrite=1 \ + --pass-config tir.disable_vectorize=1 \ + inference.onnx \ + --output-format=mlf \ + --model-format=onnx \ + --input-shapes x:[1,3,224,224] \ + --module-name=cls \ + --output=cls.tar +rm inference.onnx + +# decompression cls.tar +mkdir -p "${PWD}/cls" +tar -xvf cls.tar -C "${PWD}/cls" +rm cls.tar + +# create input and output head file +python3 ./convert_labels.py ./labels/labels.txt +python3 ./convert_image.py ./image/ILSVRC2012_val_00020010.jpg + +# build +csolution list packs -s object_classification.csolution.yml -m > packs.txt +cpackget update-index +cpackget add -f packs.txt + +PROJECT_FILE_NAME="object_classification+$MODEL_NAME$RUN_DEVICE_NAME.cprj" +echo "Project file name is $PROJECT_FILE_NAME" +cbuild "$PROJECT_FILE_NAME" + +rm -rf "${PWD}/cls" +rm "${PWD}/include/inputs.h" +rm "${PWD}/include/outputs.h" +rm "${PWD}/include/labels.h" + +# run +$VHT_Platform -C cpu0.CFGDTCMSZ=15 \ + -C cpu0.CFGITCMSZ=15 \ + -C mps3_board.uart0.out_file=\"-\" \ + -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ + -C mps3_board.visualisation.disable-visualisation=1 \ + -C mps3_board.telnetterminal0.start_telnet=0 \ + -C mps3_board.telnetterminal1.start_telnet=0 \ + -C mps3_board.telnetterminal2.start_telnet=0 \ + -C mps3_board.telnetterminal5.start_telnet=0 \ + "out/object_classification/$MODEL_NAME$RUN_DEVICE_NAME/object_classification.axf" \ + --stat + +# clean +rm -rf out +rm -rf tmp +rm -rf packs.txt \ No newline at end of file diff --git a/object_classification/sct/VHT_Corstone_SSE-300.sct b/object_classification/sct/VHT_Corstone_SSE-300.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/object_classification/sct/VHT_Corstone_SSE-300.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_classification/sct/VHT_Corstone_SSE-310.sct b/object_classification/sct/VHT_Corstone_SSE-310.sct new file mode 100644 index 0000000..27ffc47 --- /dev/null +++ b/object_classification/sct/VHT_Corstone_SSE-310.sct @@ -0,0 +1,119 @@ +; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping +; information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; + +;--------------------------------------------------------- +; First load region (SRAM/BRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00200000 +{ + ;----------------------------------------------------- + ; 0.5 MiB of SRAM/BRAM region. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + bram.bin 0x11000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x11080000 ALIGN 8 0x00080000 + { + .ANY(+ZI +RW) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_classification/vcpkg-configuration.json b/object_classification/vcpkg-configuration.json new file mode 100644 index 0000000..4e959b0 --- /dev/null +++ b/object_classification/vcpkg-configuration.json @@ -0,0 +1,27 @@ +{ + "default-registry": { + "kind": "git", + "baseline": "032d9d0820db290ce9ff644dabfdf564343013ae", + "repository": "https://github.com/microsoft/vcpkg" + }, + "registries": [ + { + "kind": "artifact", + "location": "https://aka.ms/vcpkg-ce-default", + "name": "microsoft" + }, + { + "kind": "artifact", + "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", + "name": "arm" + } + ], + "requires": { + "microsoft:cmake": "^3.25.2", + "microsoft:ninja": "^1.10.2", + "arm:compilers/arm/armclang": "^6.20.0", + "arm:compilers/arm/armclang": "^6.21.0", + "arm:debuggers/arm/armdbg": "^6.0.0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.0.0-0" + } +} \ No newline at end of file diff --git a/object_detection/RTE/Device/SSE-300-MPS3/RTE_Device.h b/object_detection/RTE/Device/SSE-300-MPS3/RTE_Device.h new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/RTE_Device.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 b/object_detection/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/object_detection/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 b/object_detection/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/device_cfg.h b/object_detection/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 b/object_detection/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct b/object_detection/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_detection/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 b/object_detection/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_detection/RTE/Device/SSE-300-MPS3/region_defs.h b/object_detection/RTE/Device/SSE-300-MPS3/region_defs.h new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/region_defs.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 b/object_detection/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/region_limits.h b/object_detection/RTE/Device/SSE-300-MPS3/region_limits.h new file mode 100644 index 0000000..20ccc08 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/region_limits.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x00000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 b/object_detection/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_detection/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/object_detection/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_detection/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/object_detection/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_detection/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/object_detection/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_detection/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/object_detection/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/object_detection/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h b/object_detection/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 b/object_detection/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h b/object_detection/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 b/object_detection/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct b/object_detection/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 b/object_detection/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_defs.h b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_defs.h new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_defs.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_limits.h b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_limits.h new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_limits.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c b/object_detection/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 b/object_detection/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c b/object_detection/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_detection/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 b/object_detection/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/object_detection/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_detection/RTE/_PicodetM55/RTE_Components.h b/object_detection/RTE/_PicodetM55/RTE_Components.h new file mode 100644 index 0000000..f47f797 --- /dev/null +++ b/object_detection/RTE/_PicodetM55/RTE_Components.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_detection+PicodetM55' + * Target: 'PicodetM55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/object_detection/RTE/_PicodetM85/RTE_Components.h b/object_detection/RTE/_PicodetM85/RTE_Components.h new file mode 100644 index 0000000..18ecadb --- /dev/null +++ b/object_detection/RTE/_PicodetM85/RTE_Components.h @@ -0,0 +1,32 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_detection+PicodetM85' + * Target: 'PicodetM85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Object-Detection-example/convert_image.py b/object_detection/convert_image.py similarity index 90% rename from Object-Detection-example/convert_image.py rename to object_detection/convert_image.py index c2f43f0..e496691 100755 --- a/Object-Detection-example/convert_image.py +++ b/object_detection/convert_image.py @@ -78,18 +78,10 @@ def create_headers(image_name): # Create input header file create_header_file("inputs", "input", img_data, "./include") # Create output header file - output_data = np.zeros([8500], np.float) - create_header_file( - "outputs", - "output0", - output_data, - "./include", ) - output_data = np.zeros([170000], np.float) - create_header_file( - "outputs", - "output1", - output_data, - "./include", ) + output_data = np.zeros([8500], np.float32) + create_header_file("outputs", "output0", output_data, "./include", ) + output_data = np.zeros([170000], np.float32) + create_header_file("outputs", "output1", output_data, "./include", ) if __name__ == "__main__": diff --git a/Object-Detection-example/image/000000014439_640x640.jpg b/object_detection/image/000000014439_640x640.jpg similarity index 100% rename from Object-Detection-example/image/000000014439_640x640.jpg rename to object_detection/image/000000014439_640x640.jpg diff --git a/Object-Detection-example/image/README.md b/object_detection/image/README.md similarity index 100% rename from Object-Detection-example/image/README.md rename to object_detection/image/README.md diff --git a/Object-Classification-example/MobileNetV3_small_x0_35/include/crt_config.h b/object_detection/include/crt_config.h similarity index 76% rename from Object-Classification-example/MobileNetV3_small_x0_35/include/crt_config.h rename to object_detection/include/crt_config.h index 2fd0ead..4013721 100644 --- a/Object-Classification-example/MobileNetV3_small_x0_35/include/crt_config.h +++ b/object_detection/include/crt_config.h @@ -17,10 +17,12 @@ * under the License. */ -#ifndef TVM_RUNTIME_CRT_CONFIG_H_ -#define TVM_RUNTIME_CRT_CONFIG_H_ - +/*! + * \file tvm/runtime/crt_config.h.template + * \brief Template for CRT configuration, to be modified on each target. + */ +#ifndef TVM_RUNTIME_CRT_CRT_CONFIG_TEMPLATE_H_ +#define TVM_RUNTIME_CRT_CRT_CONFIG_TEMPLATE_H_ /*! Log level of the CRT runtime */ #define TVM_CRT_LOG_LEVEL TVM_CRT_LOG_LEVEL_DEBUG - -#endif // TVM_RUNTIME_CRT_CONFIG_H_ +#endif // TVM_RUNTIME_CRT_CRT_CONFIG_TEMPLATE_H_ diff --git a/Object-Detection-example/include/tvm_runtime.h b/object_detection/include/tvm_runtime.h similarity index 91% rename from Object-Detection-example/include/tvm_runtime.h rename to object_detection/include/tvm_runtime.h index 0978d7a..ba16b83 100644 --- a/Object-Detection-example/include/tvm_runtime.h +++ b/object_detection/include/tvm_runtime.h @@ -16,7 +16,6 @@ * specific language governing permissions and limitations * under the License. */ - #include #include #include @@ -49,11 +48,7 @@ void TVMLogf(const char *msg, ...) { va_end(args); } -TVM_DLL int TVMFuncRegisterGlobal(const char *name, TVMFunctionHandle f, - int override) { - return 0; -} - +TVM_DLL int TVMFuncRegisterGlobal(const char* name, TVMFunctionHandle f, int override) { return 0; } #ifdef __cplusplus } -#endif +#endif \ No newline at end of file diff --git a/Object-Detection-example/src/demo_bare_metal.c b/object_detection/main.c similarity index 84% rename from Object-Detection-example/src/demo_bare_metal.c rename to object_detection/main.c index 07ed5be..7927c5c 100644 --- a/Object-Detection-example/src/demo_bare_metal.c +++ b/object_detection/main.c @@ -17,27 +17,28 @@ * under the License. */ +#include #include #include -#include +#include -#include "uart.h" +#include "stdout_USART.h" // Header files generated by convert_image.py #include "inputs.h" #include "outputs.h" int main(int argc, char **argv) { - uart_init(); - printf("Starting PicoDet inference:\n"); - struct tvmgen_picodet_outputs rec_outputs = { + stdout_init(); + printf("Starting det inference:\n"); + struct tvmgen_det_outputs rec_outputs = { .output0 = output0, .output1 = output1, }; - struct tvmgen_picodet_inputs rec_inputs = { + struct tvmgen_det_inputs rec_inputs = { .image = input, }; - tvmgen_picodet_run(&rec_inputs, &rec_outputs); + tvmgen_det_run(&rec_inputs, &rec_outputs); // post process for (int i = 0; i < output0_len / 4; i++) { @@ -55,5 +56,6 @@ int main(int argc, char **argv) { output0[i * 4 + 3] * 2, class, score); } } + printf("EXITTHESIM\r\n"); return 0; } diff --git a/object_detection/object_detection+PicodetM55.cbuild.yml b/object_detection/object_detection+PicodetM55.cbuild.yml new file mode 100644 index 0000000..b04bc2c --- /dev/null +++ b/object_detection/object_detection+PicodetM55.cbuild.yml @@ -0,0 +1,447 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_detection.csolution.yml + project: object_detection.cproject.yml + context: object_detection+PicodetM55 + compiler: AC6 + device: SSE-300-MPS3 + device-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M55 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_PICODET + - _RTE_ + add-path: + - det/codegen/host/include + - det/runtime/include + - include + - RTE/Device/SSE-300-MPS3 + - RTE/_PicodetM55 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Include + output-dirs: + intdir: tmp/object_detection/PicodetM55 + outdir: out/object_detection/PicodetM55 + rtedir: RTE + output: + - type: elf + file: object_detection.axf + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + condition: SSE-300-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-300-MPS3/RTE_Device.h + category: header + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/cmsis_driver_config.h + category: header + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/device_cfg.h + category: header + attr: config + version: 1.1.3 + - component: ARM::Device:Native Driver:IO@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.0 + condition: SSE-300-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-300-MPS3/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct + category: linkerScript + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - component: ARM::Device:USART STDOUT@1.0.0 + condition: SSE-300-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:USART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-300.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: Det + files: + - file: det/codegen/host/src/det_lib0.c + category: sourceC + - file: det/codegen/host/src/det_lib1.c + category: sourceC + - file: det/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_PicodetM55/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.1.0 + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + - component: ARM::Device:Native Driver:Timeout@1.0.0 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:USART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_detection/object_detection+PicodetM55.cprj b/object_detection/object_detection+PicodetM55.cprj new file mode 100644 index 0000000..0c6b2e3 --- /dev/null +++ b/object_detection/object_detection+PicodetM55.cprj @@ -0,0 +1,68 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_PICODET + det/codegen/host/include;det/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_detection/object_detection+PicodetM85.cbuild.yml b/object_detection/object_detection+PicodetM85.cbuild.yml new file mode 100644 index 0000000..fdc6b49 --- /dev/null +++ b/object_detection/object_detection+PicodetM85.cbuild.yml @@ -0,0 +1,445 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_detection.csolution.yml + project: object_detection.cproject.yml + context: object_detection+PicodetM85 + compiler: AC6 + device: SSE-310-MPS3_FVP + device-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M85 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_PICODET + - CORSTONE310_FVP + - _RTE_ + add-path: + - det/codegen/host/include + - det/runtime/include + - include + - RTE/Device/SSE-310-MPS3_FVP + - RTE/_PicodetM85 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Include + output-dirs: + intdir: tmp/object_detection/PicodetM85 + outdir: out/object_detection/PicodetM85 + rtedir: RTE + output: + - type: elf + file: object_detection.axf + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + condition: SSE-310-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/device_cfg.h + category: header + attr: config + version: 1.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.1 + condition: SSE-310-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-310-MPS3_FVP/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct + category: linkerScript + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - component: ARM::Device:UART STDOUT@1.0.0 + condition: SSE-310-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:UART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-310.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: Det + files: + - file: det/codegen/host/src/det_lib0.c + category: sourceC + - file: det/codegen/host/src/det_lib1.c + category: sourceC + - file: det/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_PicodetM85/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + - component: ARM::Device:Native Driver:Timeout@1.0.1 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:UART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_detection/object_detection+PicodetM85.cprj b/object_detection/object_detection+PicodetM85.cprj new file mode 100644 index 0000000..42badf8 --- /dev/null +++ b/object_detection/object_detection+PicodetM85.cprj @@ -0,0 +1,67 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_PICODET + det/codegen/host/include;det/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_detection/object_detection.cbuild-idx.yml b/object_detection/object_detection.cbuild-idx.yml new file mode 100644 index 0000000..8e991c8 --- /dev/null +++ b/object_detection/object_detection.cbuild-idx.yml @@ -0,0 +1,12 @@ +build-idx: + generated-by: csolution version 2.2.1 + csolution: object_detection.csolution.yml + cprojects: + - cproject: object_detection.cproject.yml + cbuilds: + - cbuild: object_detection+PicodetM55.cbuild.yml + project: object_detection + configuration: +PicodetM55 + - cbuild: object_detection+PicodetM85.cbuild.yml + project: object_detection + configuration: +PicodetM85 diff --git a/object_detection/object_detection.cbuild-pack.yml b/object_detection/object_detection.cbuild-pack.yml new file mode 100644 index 0000000..b595c18 --- /dev/null +++ b/object_detection/object_detection.cbuild-pack.yml @@ -0,0 +1,20 @@ +cbuild-pack: + resolved-packs: + - resolved-pack: ARM::CMSIS@5.9.0 + selected-by: + - ARM::CMSIS + - resolved-pack: ARM::CMSIS-DSP@1.15.0 + selected-by: + - ARM::CMSIS-DSP + - resolved-pack: ARM::CMSIS-NN@4.1.0 + selected-by: + - ARM::CMSIS-NN + - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: + - ARM::V2M_MPS3_SSE_300_BSP + - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: + - ARM::V2M_MPS3_SSE_310_BSP + - resolved-pack: Keil::ARM_Compiler@1.7.2 + selected-by: + - Keil::ARM_Compiler diff --git a/object_detection/object_detection.cproject.yml b/object_detection/object_detection.cproject.yml new file mode 100644 index 0000000..cbd3a6a --- /dev/null +++ b/object_detection/object_detection.cproject.yml @@ -0,0 +1,105 @@ +project: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP + for-context: +PicodetM55 + - pack: ARM::V2M_MPS3_SSE_310_BSP + for-context: +PicodetM85 + - pack: ARM::CMSIS + - pack: ARM::CMSIS-DSP + - pack: ARM::CMSIS-NN + - pack: Keil::ARM_Compiler + setups: + - setup: Options for PicodetM55, PicodetM85 + processor: + trustzone: "off" + add-path: + - det/codegen/host/include + - det/runtime/include + - include + debug: "on" + define: + - USE_PICODET + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + linker: + - script: sct/VHT_Corstone_SSE-300.sct + for-context: +PicodetM55 + - script: sct/VHT_Corstone_SSE-310.sct + for-context: +PicodetM85 + groups: + - group: Source + files: + - file: main.c + - group: Det + files: + - file: det/codegen/host/src/det_lib0.c + - file: det/codegen/host/src/det_lib1.c + - file: det/runtime/src/runtime/crt/common/crt_backend_api.c + components: + - component: ARM::CMSIS Driver:USART + for-context: +PicodetM55 + - component: ARM::CMSIS Driver:USART + for-context: +PicodetM85 + - component: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source + - component: ARM::CMSIS:NN Lib + - component: ARM::Device:Definition + for-context: +PicodetM55 + - component: ARM::Device:Definition + for-context: +PicodetM85 + - component: ARM::Device:Native Driver:IO + for-context: +PicodetM85 + - component: ARM::Device:Native Driver:IO + for-context: +PicodetM55 + - component: ARM::Device:Native Driver:SysCounter + for-context: +PicodetM85 + - component: ARM::Device:Native Driver:SysCounter + for-context: +PicodetM55 + - component: ARM::Device:Native Driver:SysTimer + for-context: +PicodetM85 + - component: ARM::Device:Native Driver:SysTimer + for-context: +PicodetM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +PicodetM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +PicodetM85 + - component: ARM::Device:Native Driver:UART + for-context: +PicodetM55 + - component: ARM::Device:Native Driver:UART + for-context: +PicodetM85 + - component: ARM::Device:Startup&C Startup + for-context: +PicodetM55 + - component: ARM::Device:Startup&C Startup + for-context: +PicodetM85 + - component: ARM::Device:UART STDOUT + for-context: +PicodetM85 + - component: ARM::Device:USART STDOUT + for-context: +PicodetM55 + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User diff --git a/object_detection/object_detection.csolution.yml b/object_detection/object_detection.csolution.yml new file mode 100644 index 0000000..9f659b4 --- /dev/null +++ b/object_detection/object_detection.csolution.yml @@ -0,0 +1,13 @@ +solution: + created-by: uv2csolution@1.2.0 + created-for: CMSIS-Toolbox@2.0.0 + compiler: AC6 + target-types: + - type: PicodetM55 + device: SSE-300-MPS3 + optimize: none + - type: PicodetM85 + device: SSE-310-MPS3_FVP + optimize: none + projects: + - project: object_detection.cproject.yml diff --git a/object_detection/object_detection.uvprojx b/object_detection/object_detection.uvprojx new file mode 100644 index 0000000..3f109f9 --- /dev/null +++ b/object_detection/object_detection.uvprojx @@ -0,0 +1,1424 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Picodet_M55 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-300-MPS3 + ARM + ARM.V2M_MPS3_SSE_300_BSP.1.4.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00080000) XRAM2(0x01000000,0x00100000) XRAM3(0x20000000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h + + + + + + + + + + $$Device:SSE-300-MPS3$SVD\SSE300.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + object_detection + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x20000 + + + 0 + 0x20040000 + 0x20000 + + + 0 + 0x0 + 0x80000 + + + 0 + 0x1000000 + 0x200000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_PICODET + + .\det\codegen\host\include;.\det\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-300.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + Det + + + det_lib0.c + 1 + .\det\codegen\host\src\det_lib0.c + + + det_lib1.c + 1 + .\det\codegen\host\src\det_lib1.c + + + crt_backend_api.c + 1 + .\det\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + + + Picodet_M85 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-310-MPS3_FVP + ARM + ARM.V2M_MPS3_SSE_310_BSP.1.3.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00008000) XRAM2(0x01000000,0x00200000) XRAM3(0x20000000,0x00002000) CPUTYPE("Cortex-M85") FPU3(DFPU) DSP TZ MVE(FP) PACBTI CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-310-MPS3_FVP$Device\Include\SSE310MPS3.h + + + + + + + + + + $$Device:SSE-310-MPS3_FVP$SVD\SSE310.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + object_detection + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1000000 + 0x200000 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x30000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_PICODET + + .\det\codegen\host\include;.\det\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-310.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + Det + + + det_lib0.c + 1 + .\det\codegen\host\src\det_lib0.c + + + det_lib1.c + 1 + .\det\codegen\host\src\det_lib1.c + + + crt_backend_api.c + 1 + .\det\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::CMSIS Driver + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Compiler + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM85\ARMCM85_ac6.sct + + + + + + RTE\Device\ARMCM85\startup_ARMCM85.c + + + + + + RTE\Device\ARMCM85\system_ARMCM85.c + + + + + + RTE\Device\SSE-300-MPS3\RTE_Device.h + + + + + + + + RTE\Device\SSE-300-MPS3\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-300-MPS3\device_cfg.h + + + + + + + + RTE\Device\SSE-300-MPS3\linker_SSE300MPS3_secure.sct + + + + + + + + RTE\Device\SSE-300-MPS3\region_defs.h + + + + + + + + RTE\Device\SSE-300-MPS3\region_limits.h + + + + + + + + RTE\Device\SSE-300-MPS3\startup_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-300-MPS3\system_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\device_cfg.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\linker_SSE310MPS3_secure.sct + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_defs.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_limits.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\startup_SSE310MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\system_SSE310MPS3.c + + + + + + + + + + + + + base_project + 1 + + + + + diff --git a/object_detection/run_demo.sh b/object_detection/run_demo.sh new file mode 100644 index 0000000..ad5ff45 --- /dev/null +++ b/object_detection/run_demo.sh @@ -0,0 +1,144 @@ +#!/bin/bash + +# Show usage +function show_usage() { + cat <&2 + show_usage >&2 + exit 1 + fi + ;; + + --device) + if [ $# -gt 1 ] + then + export DEVICE="$2" + shift 2 + else + echo 'ERROR: --device requires a non-empty argument' >&2 + show_usage >&2 + exit 1 + fi + ;; + + -*|--*) + echo "Error: Unknown flag: $1" >&2 + show_usage >&2 + exit 1 + ;; + esac +done + +echo "Device name is $DEVICE" +if [ "$DEVICE" == "cortex-m55" ]; then + RUN_DEVICE_NAME="M55" + VHT_Platform="VHT_MPS3_Corstone_SSE-300" + TVM_TARGET="cortex-m55" +elif [ "$DEVICE" == "cortex-m85" ]; then + RUN_DEVICE_NAME="M85" + VHT_Platform="VHT_Corstone_SSE-310" + TVM_TARGET="cortex-m85" +else + echo 'ERROR: --device only support cortex-m55/cortex-m85' >&2 + exit 1 +fi + +# download paddle model +echo "Model name is $MODEL_NAME" +if [ "$MODEL_NAME" == "Picodet" ]; then + wget https://bj.bcebos.com/v1/paddledet/deploy/Inference/picodet_s_320_coco_lcnet_no_nms.tar + tar -xf picodet_s_320_coco_lcnet_no_nms.tar + rm -rf picodet_s_320_coco_lcnet_no_nms.tar + mv picodet_s_320_coco_lcnet_no_nms model +else + echo 'ERROR: --model_name only support Picodet' >&2 + exit 1 +fi + +# convert paddle model to onnx model +paddle2onnx --model_dir "${PWD}/model" \ + --model_filename model.pdmodel \ + --params_filename model.pdiparams \ + --save_file model.onnx +rm -rf "${PWD}/model" + +# convert onnx model to tvm model +python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ + --target-cmsis-nn-mcpu="${TVM_TARGET}" \ + --target-c-mcpu="${TVM_TARGET}" \ + --runtime=crt \ + --executor=aot \ + --executor-aot-interface-api=c \ + --executor-aot-unpacked-api=1 \ + --pass-config tir.usmp.enable=1 \ + --pass-config tir.usmp.algorithm=hill_climb \ + --pass-config tir.disable_storage_rewrite=1 \ + --pass-config tir.disable_vectorize=1 model.onnx \ + --output-format=mlf \ + --model-format=onnx \ + --module-name=det \ + --input-shapes image:[1,3,320,320] \ + --output=det.tar +rm model.onnx + +# decompression cls.tar +mkdir -p "${PWD}/det" +tar -xvf det.tar -C "${PWD}/det" +rm det.tar + +# create input and output head file + python3 ./convert_image.py ./image/000000014439_640x640.jpg + +# build + csolution list packs -s object_detection.csolution.yml -m > packs.txt + cpackget update-index + cpackget add -f packs.txt + + PROJECT_FILE_NAME="object_detection+$MODEL_NAME$RUN_DEVICE_NAME.cprj" + echo "Project file name is $PROJECT_FILE_NAME" + cbuild "$PROJECT_FILE_NAME" + + rm -rf "${PWD}/cls" + rm "${PWD}/include/inputs.h" + rm "${PWD}/include/outputs.h" + + # run + $VHT_Platform -C cpu0.CFGDTCMSZ=15 \ + -C cpu0.CFGITCMSZ=15 \ + -C mps3_board.uart0.out_file=\"-\" \ + -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ + -C mps3_board.visualisation.disable-visualisation=1 \ + -C mps3_board.telnetterminal0.start_telnet=0 \ + -C mps3_board.telnetterminal1.start_telnet=0 \ + -C mps3_board.telnetterminal2.start_telnet=0 \ + -C mps3_board.telnetterminal5.start_telnet=0 \ + "out/object_detection/$MODEL_NAME$RUN_DEVICE_NAME/object_detection.axf" \ + --stat + + # clean + rm -rf out + rm -rf tmp + rm -rf packs.txt \ No newline at end of file diff --git a/object_detection/sct/VHT_Corstone_SSE-300.sct b/object_detection/sct/VHT_Corstone_SSE-300.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/object_detection/sct/VHT_Corstone_SSE-300.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_detection/sct/VHT_Corstone_SSE-310.sct b/object_detection/sct/VHT_Corstone_SSE-310.sct new file mode 100644 index 0000000..27ffc47 --- /dev/null +++ b/object_detection/sct/VHT_Corstone_SSE-310.sct @@ -0,0 +1,119 @@ +; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping +; information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; + +;--------------------------------------------------------- +; First load region (SRAM/BRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00200000 +{ + ;----------------------------------------------------- + ; 0.5 MiB of SRAM/BRAM region. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + bram.bin 0x11000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x11080000 ALIGN 8 0x00080000 + { + .ANY(+ZI +RW) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_detection/vcpkg-configuration.json b/object_detection/vcpkg-configuration.json new file mode 100644 index 0000000..4e959b0 --- /dev/null +++ b/object_detection/vcpkg-configuration.json @@ -0,0 +1,27 @@ +{ + "default-registry": { + "kind": "git", + "baseline": "032d9d0820db290ce9ff644dabfdf564343013ae", + "repository": "https://github.com/microsoft/vcpkg" + }, + "registries": [ + { + "kind": "artifact", + "location": "https://aka.ms/vcpkg-ce-default", + "name": "microsoft" + }, + { + "kind": "artifact", + "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", + "name": "arm" + } + ], + "requires": { + "microsoft:cmake": "^3.25.2", + "microsoft:ninja": "^1.10.2", + "arm:compilers/arm/armclang": "^6.20.0", + "arm:compilers/arm/armclang": "^6.21.0", + "arm:debuggers/arm/armdbg": "^6.0.0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.0.0-0" + } +} \ No newline at end of file diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/RTE_Device.h b/object_segmentation/RTE/Device/SSE-300-MPS3/RTE_Device.h new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/RTE_Device.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 b/object_segmentation/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/object_segmentation/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 b/object_segmentation/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/device_cfg.h b/object_segmentation/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 b/object_segmentation/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct b/object_segmentation/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 b/object_segmentation/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/region_defs.h b/object_segmentation/RTE/Device/SSE-300-MPS3/region_defs.h new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/region_defs.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 b/object_segmentation/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/region_limits.h b/object_segmentation/RTE/Device/SSE-300-MPS3/region_limits.h new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/region_limits.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 b/object_segmentation/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/object_segmentation/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/object_segmentation/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/object_segmentation/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_segmentation/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/object_segmentation/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_defs.h b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_defs.h new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_defs.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_limits.h b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_limits.h new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_limits.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/object_segmentation/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/object_segmentation/RTE/_PPHumanSegM55/RTE_Components.h b/object_segmentation/RTE/_PPHumanSegM55/RTE_Components.h new file mode 100644 index 0000000..8afdb28 --- /dev/null +++ b/object_segmentation/RTE/_PPHumanSegM55/RTE_Components.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_segmentation+PPHumanSegM55' + * Target: 'PPHumanSegM55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/object_segmentation/RTE/_PPHumanSegM85/RTE_Components.h b/object_segmentation/RTE/_PPHumanSegM85/RTE_Components.h new file mode 100644 index 0000000..6d8f765 --- /dev/null +++ b/object_segmentation/RTE/_PPHumanSegM85/RTE_Components.h @@ -0,0 +1,32 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'object_segmentation+PPHumanSegM85' + * Target: 'PPHumanSegM85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/object_segmentation/RTE/_PP_HumanSeg_M55/RTE_Components.h b/object_segmentation/RTE/_PP_HumanSeg_M55/RTE_Components.h new file mode 100644 index 0000000..d6c44a5 --- /dev/null +++ b/object_segmentation/RTE/_PP_HumanSeg_M55/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'object_segmentation' + * Target: 'PP_HumanSeg_M55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/object_segmentation/RTE/_PP_HumanSeg_M85/RTE_Components.h b/object_segmentation/RTE/_PP_HumanSeg_M85/RTE_Components.h new file mode 100644 index 0000000..ba9bd61 --- /dev/null +++ b/object_segmentation/RTE/_PP_HumanSeg_M85/RTE_Components.h @@ -0,0 +1,33 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'object_segmentation' + * Target: 'PP_HumanSeg_M85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Semantic-Segmentation-example/PP-LiteSeg/convert_image.py b/object_segmentation/convert_image.py similarity index 77% rename from Semantic-Segmentation-example/PP-LiteSeg/convert_image.py rename to object_segmentation/convert_image.py index 170e04d..86e6f7b 100644 --- a/Semantic-Segmentation-example/PP-LiteSeg/convert_image.py +++ b/object_segmentation/convert_image.py @@ -27,19 +27,8 @@ def resize_norm_img(img, image_shape, padding=True): imgC, imgH, imgW = image_shape - h = img.shape[0] - w = img.shape[1] - if not padding: - resized_image = cv2.resize( - img, (imgW, imgH), interpolation=cv2.INTER_LINEAR) - resized_w = imgW - else: - ratio = w / float(h) - if math.ceil(imgH * ratio) > imgW: - resized_w = imgW - else: - resized_w = int(math.ceil(imgH * ratio)) - resized_image = cv2.resize(img, (resized_w, imgH)) + resized_image = cv2.resize(img, (imgW, imgH)) + cv2.imwrite("./temp.png", resized_image) resized_image = resized_image.astype('float32') if image_shape[0] == 1: resized_image = resized_image / 255 @@ -48,9 +37,7 @@ def resize_norm_img(img, image_shape, padding=True): resized_image = resized_image.transpose((2, 0, 1)) / 255 resized_image -= 0.5 resized_image /= 0.5 - padding_im = np.zeros((imgC, imgH, imgW), dtype=np.float32) - padding_im[:, :, 0:resized_w] = resized_image - return padding_im + return resized_image def create_header_file(name, dtype, tensor_name, tensor_data, output_path): @@ -80,7 +67,7 @@ def create_headers(image_name): # Resize image to 224x224 img = cv2.imread(img_path) - img = resize_norm_img(img, [3, 128, 64]) + img = resize_norm_img(img, [3,114,256]) img_data = img.astype("float32") # # Add the batch dimension, as we are expecting 4-dimensional input: NCHW. @@ -89,13 +76,8 @@ def create_headers(image_name): # Create input header file create_header_file("inputs", "float", "input", img_data, "./include") # Create output header file - output_data = np.zeros([128*64], np.int32) - create_header_file( - "outputs", - "int", - "output", - output_data, - "./include", ) + output_data = np.zeros([114*256], np.int32) + create_header_file("outputs", "int", "output", output_data, "./include") if __name__ == "__main__": diff --git a/Semantic-Segmentation-example/PP-LiteSeg/convert_outputs.py b/object_segmentation/convert_outputs.py similarity index 81% rename from Semantic-Segmentation-example/PP-LiteSeg/convert_outputs.py rename to object_segmentation/convert_outputs.py index 3f5c2c2..03117c0 100644 --- a/Semantic-Segmentation-example/PP-LiteSeg/convert_outputs.py +++ b/object_segmentation/convert_outputs.py @@ -25,14 +25,14 @@ def create_mask_jpg(output_file): """ This function generates a jpg format image of the inference result. """ - label_colors = np.array([[128, 64, 128], [244, 35, 232], [70, 70, 70], [102, 102, 156], [190, 153, 153], [153, 153, 153], [250, 170, 30], [220, 220, 0], [107, 142, 35], [152, 251, 152], [70, 130, 180], [220, 20, 60], [255, 0, 0], [0, 0, 142], [0, 0, 70], [0, 60, 100], [0, 80, 100], [0, 0, 230], [119, 11, 32]]) + label_colors = np.array([[0,0,0],[255,255,255]]) # read outputs file with open(output_file) as f: content = f.read() # process outputs - height, width = (64, 128) + height, width = (114, 256) mask = [] for line in content.splitlines(): @@ -48,7 +48,7 @@ def create_mask_jpg(output_file): mask_gray = cv2.cvtColor(mask_img_rgb, cv2.COLOR_RGB2GRAY) # save result image - if cv2.imwrite("build/result.jpg", mask_gray): + if cv2.imwrite("result.jpg", mask_gray): print("Save result.jpg successfully!\n") else: print("Failed to save result.jpg!\n") diff --git a/object_segmentation/images/README.md b/object_segmentation/images/README.md new file mode 100644 index 0000000..2265e97 --- /dev/null +++ b/object_segmentation/images/README.md @@ -0,0 +1,5 @@ +# About Dataset + +The test image [portrait_heng.jpg](./portrait_heng.jpg) for this example comes +from [PaddleSeg](https://github.com/PaddlePaddle/PaddleSeg)'s val images. It is used for verifying the inference +results of PPHumanseg model running on AVH Corstone 300 platform with Cortex-M55 CPU. diff --git a/object_segmentation/images/portrait_heng.jpg b/object_segmentation/images/portrait_heng.jpg new file mode 100644 index 0000000..7f87940 Binary files /dev/null and b/object_segmentation/images/portrait_heng.jpg differ diff --git a/OCR-example/Text-angle-classification-example/include/crt_config.h b/object_segmentation/include/crt_config.h similarity index 100% rename from OCR-example/Text-angle-classification-example/include/crt_config.h rename to object_segmentation/include/crt_config.h diff --git a/OCR-example/Text-angle-classification-example/include/tvm_runtime.h b/object_segmentation/include/tvm_runtime.h similarity index 100% rename from OCR-example/Text-angle-classification-example/include/tvm_runtime.h rename to object_segmentation/include/tvm_runtime.h diff --git a/Semantic-Segmentation-example/PP-LiteSeg/src/demo_bare_metal.c b/object_segmentation/main.c similarity index 77% rename from Semantic-Segmentation-example/PP-LiteSeg/src/demo_bare_metal.c rename to object_segmentation/main.c index cd61dce..e3e43a0 100644 --- a/Semantic-Segmentation-example/PP-LiteSeg/src/demo_bare_metal.c +++ b/object_segmentation/main.c @@ -17,32 +17,29 @@ * under the License. */ +#include #include +#include #include -#include - -#include "uart.h" - -// Header files generated by convert_image.py +#include #include "inputs.h" #include "outputs.h" +#include "stdout_USART.h" int main(int argc, char** argv) { - uart_init(); - - // Starting semantic segmentation inference - struct tvmgen_seg_outputs seg_outputs = { + stdout_init(); + struct tvmgen_object_segmentation_outputs seg_outputs = { .output = output, }; - struct tvmgen_seg_inputs seg_inputs = { + struct tvmgen_object_segmentation_inputs seg_inputs = { .x = input, }; - tvmgen_seg_run(&seg_inputs, &seg_outputs); + tvmgen_object_segmentation_run(&seg_inputs, &seg_outputs); // print output - int width = 64, height = 128; + int width = 256, height = 114; for (int i = 0; i < width * height; i++) { printf("%d ", output[i]); } @@ -50,7 +47,6 @@ int main(int argc, char** argv) { // The FVP will shut down when it receives "EXITTHESIM" on the UART printf("EXITTHESIM\n"); - while (1 == 1) - ; + while (1 == 1); return 0; -} +} \ No newline at end of file diff --git a/object_segmentation/object_segmentation+PPHumanSegM55.cbuild.yml b/object_segmentation/object_segmentation+PPHumanSegM55.cbuild.yml new file mode 100644 index 0000000..1775342 --- /dev/null +++ b/object_segmentation/object_segmentation+PPHumanSegM55.cbuild.yml @@ -0,0 +1,445 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_segmentation.csolution.yml + project: object_segmentation.cproject.yml + context: object_segmentation+PPHumanSegM55 + compiler: AC6 + device: SSE-300-MPS3 + device-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M55 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_PP_HUMANSEG + - _RTE_ + add-path: + - object_segmentation/codegen/host/include + - object_segmentation/runtime/include + - include + - RTE/Device/SSE-300-MPS3 + - RTE/_PPHumanSegM55 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Include + output-dirs: + intdir: tmp/object_segmentation/PPHumanSegM55 + outdir: out/object_segmentation/PPHumanSegM55 + rtedir: RTE + output: + - type: elf + file: object_segmentation.axf + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + condition: SSE-300-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-300-MPS3/RTE_Device.h + category: header + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/cmsis_driver_config.h + category: header + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/device_cfg.h + category: header + attr: config + version: 1.1.3 + - component: ARM::Device:Native Driver:IO@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.0 + condition: SSE-300-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-300-MPS3/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct + category: linkerScript + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - component: ARM::Device:USART STDOUT@1.0.0 + condition: SSE-300-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:USART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-300.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - file: object_segmentation/codegen/host/src/object_segmentation_lib0.c + category: sourceC + - file: object_segmentation/codegen/host/src/object_segmentation_lib1.c + category: sourceC + - file: object_segmentation/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_PPHumanSegM55/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.1.0 + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + - component: ARM::Device:Native Driver:Timeout@1.0.0 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:USART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_segmentation/object_segmentation+PPHumanSegM55.cprj b/object_segmentation/object_segmentation+PPHumanSegM55.cprj new file mode 100644 index 0000000..5d6dc26 --- /dev/null +++ b/object_segmentation/object_segmentation+PPHumanSegM55.cprj @@ -0,0 +1,66 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_PP_HUMANSEG + object_segmentation/codegen/host/include;object_segmentation/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_segmentation/object_segmentation+PPHumanSegM85.cbuild.yml b/object_segmentation/object_segmentation+PPHumanSegM85.cbuild.yml new file mode 100644 index 0000000..56fb63f --- /dev/null +++ b/object_segmentation/object_segmentation+PPHumanSegM85.cbuild.yml @@ -0,0 +1,443 @@ +build: + generated-by: csolution version 2.2.1 + solution: object_segmentation.csolution.yml + project: object_segmentation.cproject.yml + context: object_segmentation+PPHumanSegM85 + compiler: AC6 + device: SSE-310-MPS3_FVP + device-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M85 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_PP_HUMANSEG + - CORSTONE310_FVP + - _RTE_ + add-path: + - include + - object_segmentation/runtime/include + - object_segmentation/codegen/host/include + - RTE/Device/SSE-310-MPS3_FVP + - RTE/_PPHumanSegM85 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Include + output-dirs: + intdir: tmp/object_segmentation/PPHumanSegM85 + outdir: out/object_segmentation/PPHumanSegM85 + rtedir: RTE + output: + - type: elf + file: object_segmentation.axf + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + condition: SSE-310-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/device_cfg.h + category: header + attr: config + version: 1.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.1 + condition: SSE-310-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-310-MPS3_FVP/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct + category: linkerScript + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - component: ARM::Device:UART STDOUT@1.0.0 + condition: SSE-310-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:UART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-310.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - file: object_segmentation/codegen/host/src/object_segmentation_lib0.c + category: sourceC + - file: object_segmentation/codegen/host/src/object_segmentation_lib1.c + category: sourceC + - file: object_segmentation/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_PPHumanSegM85/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + - component: ARM::Device:Native Driver:Timeout@1.0.1 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:UART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/object_segmentation/object_segmentation+PPHumanSegM85.cprj b/object_segmentation/object_segmentation+PPHumanSegM85.cprj new file mode 100644 index 0000000..e08c3c2 --- /dev/null +++ b/object_segmentation/object_segmentation+PPHumanSegM85.cprj @@ -0,0 +1,65 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_PP_HUMANSEG + include;object_segmentation/runtime/include;object_segmentation/codegen/host/include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/object_segmentation/object_segmentation.cbuild-idx.yml b/object_segmentation/object_segmentation.cbuild-idx.yml new file mode 100644 index 0000000..ff771ba --- /dev/null +++ b/object_segmentation/object_segmentation.cbuild-idx.yml @@ -0,0 +1,12 @@ +build-idx: + generated-by: csolution version 2.2.1 + csolution: object_segmentation.csolution.yml + cprojects: + - cproject: object_segmentation.cproject.yml + cbuilds: + - cbuild: object_segmentation+PPHumanSegM55.cbuild.yml + project: object_segmentation + configuration: +PPHumanSegM55 + - cbuild: object_segmentation+PPHumanSegM85.cbuild.yml + project: object_segmentation + configuration: +PPHumanSegM85 diff --git a/object_segmentation/object_segmentation.cbuild-pack.yml b/object_segmentation/object_segmentation.cbuild-pack.yml new file mode 100644 index 0000000..b595c18 --- /dev/null +++ b/object_segmentation/object_segmentation.cbuild-pack.yml @@ -0,0 +1,20 @@ +cbuild-pack: + resolved-packs: + - resolved-pack: ARM::CMSIS@5.9.0 + selected-by: + - ARM::CMSIS + - resolved-pack: ARM::CMSIS-DSP@1.15.0 + selected-by: + - ARM::CMSIS-DSP + - resolved-pack: ARM::CMSIS-NN@4.1.0 + selected-by: + - ARM::CMSIS-NN + - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: + - ARM::V2M_MPS3_SSE_300_BSP + - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: + - ARM::V2M_MPS3_SSE_310_BSP + - resolved-pack: Keil::ARM_Compiler@1.7.2 + selected-by: + - Keil::ARM_Compiler diff --git a/object_segmentation/object_segmentation.cproject.yml b/object_segmentation/object_segmentation.cproject.yml new file mode 100644 index 0000000..135157c --- /dev/null +++ b/object_segmentation/object_segmentation.cproject.yml @@ -0,0 +1,144 @@ +project: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP + for-context: +PPHumanSegM55 + - pack: ARM::V2M_MPS3_SSE_310_BSP + for-context: +PPHumanSegM85 + - pack: ARM::CMSIS + - pack: ARM::CMSIS-DSP + - pack: ARM::CMSIS-NN + - pack: Keil::ARM_Compiler + setups: + - setup: Options for PPHumanSegM55 + for-context: +PPHumanSegM55 + processor: + trustzone: "off" + add-path: + - object_segmentation/codegen/host/include + - object_segmentation/runtime/include + - include + debug: "on" + define: + - USE_PP_HUMANSEG + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + - setup: Options for PPHumanSegM85 + for-context: +PPHumanSegM85 + processor: + trustzone: "off" + add-path: + - include + - object_segmentation/runtime/include + - object_segmentation/codegen/host/include + debug: "on" + define: + - USE_PP_HUMANSEG + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + linker: + - script: sct/VHT_Corstone_SSE-300.sct + for-context: +PPHumanSegM55 + - script: sct/VHT_Corstone_SSE-310.sct + for-context: +PPHumanSegM85 + groups: + - group: Source + files: + - file: main.c + - file: object_segmentation/codegen/host/src/object_segmentation_lib0.c + - file: object_segmentation/codegen/host/src/object_segmentation_lib1.c + - file: object_segmentation/runtime/src/runtime/crt/common/crt_backend_api.c + components: + - component: ARM::CMSIS Driver:USART + for-context: +PPHumanSegM55 + - component: ARM::CMSIS Driver:USART + for-context: +PPHumanSegM85 + - component: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source + - component: ARM::CMSIS:NN Lib + - component: ARM::Device:Definition + for-context: +PPHumanSegM55 + - component: ARM::Device:Definition + for-context: +PPHumanSegM85 + - component: ARM::Device:Native Driver:IO + for-context: +PPHumanSegM85 + - component: ARM::Device:Native Driver:IO + for-context: +PPHumanSegM55 + - component: ARM::Device:Native Driver:SysCounter + for-context: +PPHumanSegM85 + - component: ARM::Device:Native Driver:SysCounter + for-context: +PPHumanSegM55 + - component: ARM::Device:Native Driver:SysTimer + for-context: +PPHumanSegM85 + - component: ARM::Device:Native Driver:SysTimer + for-context: +PPHumanSegM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +PPHumanSegM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +PPHumanSegM85 + - component: ARM::Device:Native Driver:UART + for-context: +PPHumanSegM55 + - component: ARM::Device:Native Driver:UART + for-context: +PPHumanSegM85 + - component: ARM::Device:Startup&C Startup + for-context: +PPHumanSegM55 + - component: ARM::Device:Startup&C Startup + for-context: +PPHumanSegM85 + - component: ARM::Device:UART STDOUT + for-context: +PPHumanSegM85 + - component: ARM::Device:USART STDOUT + for-context: +PPHumanSegM55 + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User diff --git a/object_segmentation/object_segmentation.csolution.yml b/object_segmentation/object_segmentation.csolution.yml new file mode 100644 index 0000000..739ff0b --- /dev/null +++ b/object_segmentation/object_segmentation.csolution.yml @@ -0,0 +1,13 @@ +solution: + created-by: uv2csolution@1.2.0 + created-for: CMSIS-Toolbox@2.0.0 + compiler: AC6 + target-types: + - type: PPHumanSegM55 + device: SSE-300-MPS3 + optimize: none + - type: PPHumanSegM85 + device: SSE-310-MPS3_FVP + optimize: none + projects: + - project: object_segmentation.cproject.yml diff --git a/object_segmentation/object_segmentation.uvguix.zheng b/object_segmentation/object_segmentation.uvguix.zheng new file mode 100644 index 0000000..7d7044d --- /dev/null +++ b/object_segmentation/object_segmentation.uvguix.zheng @@ -0,0 +1,3628 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
+ + + + + + + + + + 38003 + Registers + 124 100 + + + 346 + Code Coverage + 877 603 + + + 204 + Performance Analyzer + 313 155 155 857 + + + + + + 35141 + Event Statistics + + 250 50 741 + + + 1506 + Symbols + + 71 71 71 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 300 + + + + + + + + 0 + 0 + 0 + 50 + 16 + + + + + + + 44 + 2 + 3 + + -32000 + -32000 + + + -1 + -1 + + + 130 + 130 + 1410 + 865 + + + + 0 + + 434 + 0100000004000000010000000100000001000000010000000000000002000000000000000100000001000000000000002800000028000000010000000200000000000000010000004F433A5C55736572735C7A68656E675C434C696F6E50726F6A656374735C506164646C652D6578616D706C65732D666F722D4156485C6F626A6563745F7365676D656E746174696F6E5C6D61696E2E6300000000066D61696E2E6300000000C5D4F200FFFFFFFF79433A5C55736572735C7A68656E675C434C696F6E50726F6A656374735C506164646C652D6578616D706C65732D666F722D4156485C6F626A6563745F7365676D656E746174696F6E5C5254455C4465766963655C5353452D3331302D4D5053335F4656505C737461727475705F5353453331304D5053332E630000000014737461727475705F5353453331304D5053332E6300000000FFDC7800FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000D900000066000000AB06000059030000 + + + + 0 + Build + + -1 + -1 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D90000004F000000F0040000DA000000 + + + 16 + D900000066000000F0040000F1000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000029030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 109 + 109 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000029030000 + + + 16 + F200000009010000EE01000036030000 + + + + 1465 + 1465 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 1935 + 1935 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 195 + 195 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000029030000 + + + 16 + F200000009010000EE01000036030000 + + + + 196 + 196 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000029030000 + + + 16 + F200000009010000EE01000036030000 + + + + 197 + 197 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000005A030000AB060000D1030000 + + + 16 + F2000000090100006A03000094010000 + + + + 198 + 198 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 0000000006020000F0040000A5020000 + + + 16 + F2000000090100006A03000094010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000005D030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 203 + 203 + 0 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 38003 + 38003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000029030000 + + + 16 + F200000009010000EE01000036030000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000005D030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000005D030000A8060000B8030000 + + + 16 + F200000009010000EE01000036030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F200000009010000C7010000D0010000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F200000009010000C7010000D0010000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000005D030000A8060000B8030000 + + + 16 + F200000009010000EE01000036030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000005D030000A8060000B8030000 + + + 16 + F200000009010000EE01000036030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000ED040000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000D1030000AB060000E4030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 1 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 0 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 00000000380000006F02000054000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000001D020000ED0400008C020000 + + + 16 + F200000009010000C7010000D0010000 + + + + 3312 + 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFD9000000DA000000F0040000DE000000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000D900000066000000F0040000F1000000D90000004F000000F0040000DA0000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF170400004F0000001B04000016020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C30000018000400000000000001B04000066000000F00400002D0200001B0400004F000000F00400001602000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFD50000004F000000D900000042030000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000D500000059030000000000004F000000D5000000420300000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF0000000002020000F00400000602000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800080000000000000000000001D020000F0040000BC0200000000000006020000F0040000A502000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFF78020000060200007C020000A502000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF0000000042030000AB06000046030000010000000100001004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000001000000000000005D030000AB060000E80300000000000046030000AB060000D10300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2663 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000000000000000000000000000000000000000000100000001000000960000000200205000000000077069636F64657496000000000000000800077069636F6465741554564D46756E635265676973746572476C6F62616C0745525F44415441045352414D0C535F444154415F53544152540E5352414D5F57415445524D41524B077374646F75745F07776169745F75730000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 1010 + 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000004002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050010000000F50505F48756D616E5365675F4D3835960000000000000002000F50505F48756D616E5365675F4D35350F50505F48756D616E5365675F4D383500000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2373 + 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1707 + 1067 + + + + 1 + Debug + + -1 + -1 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D90000004F000000AB060000DA000000 + + + 16 + D900000066000000AB060000F1000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000015030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 109 + 109 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000015030000 + + + 16 + F200000009010000EE01000036030000 + + + + 1465 + 1465 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000A8060000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 1935 + 1935 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 195 + 195 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000015030000 + + + 16 + F200000009010000EE01000036030000 + + + + 196 + 196 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000015030000 + + + 16 + F200000009010000EE01000036030000 + + + + 197 + 197 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 0300000031020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 198 + 198 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000003203000055030000D1030000 + + + 16 + F2000000090100006A03000094010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000031020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 203 + 203 + 1 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + D900000063000000AB060000DA000000 + + + 16 + F2000000090100006A03000094010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000A8060000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F2000000090100006A03000094010000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000A8060000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000A8060000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000A8060000C1000000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000A8060000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 38003 + 38003 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000D200000015030000 + + + 16 + F200000009010000EE01000036030000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000031020000ED0400008C020000 + + + 16 + F2000000090100006A03000094010000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000031020000ED0400008C020000 + + + 16 + F200000009010000EE01000036030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000031020000ED0400008C020000 + + + 16 + F200000009010000EE01000036030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000031020000ED0400008C020000 + + + 16 + F200000009010000EE01000036030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + DC00000066000000A8060000C1000000 + + + 16 + F2000000090100006A03000094010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 1E04000066000000ED040000FD010000 + + + 16 + F200000009010000C7010000D0010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000D1030000AB060000E4030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 0 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 1 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 000000001C0000006F02000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 5C03000049030000A8060000B8030000 + + + 16 + F200000009010000C7010000D0010000 + + + + 3311 + 000000000B000000000000000020000001000000FFFFFFFFFFFFFFFFD9000000DA000000AB060000DE000000010000000100001004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000001000000D900000066000000AB060000F1000000D90000004F000000AB060000DA0000000000000040280056080000000B446973617373656D626C7901000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF170400004F0000001B04000016020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C30000018000400000000000001B04000066000000F00400002D0200001B0400004F000000F00400001602000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFD50000004F000000D90000002E030000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000D500000045030000000000004F000000D50000002E0300000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73000000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7300000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657300000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273010000007394000001000000FFFFFFFFFFFFFFFF04000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000001000000FFFFFFFFFFFFFFFF000000002E030000AB0600003203000001000000010000100400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB090000018000800000010000005903000049030000AB060000E80300005903000032030000AB060000D103000000000000404100560F0000001343616C6C20537461636B202B204C6F63616C73010000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203101000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFF000000000000000001000000000000000100000001000000FFFFFFFF550300003203000059030000D103000001000000020000100400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000000000000FFFFFFFFFFFFFFFF0000000016020000F00400001A020000000000000100000004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF01000077940000018000800000000000000000000031020000F0040000BC020000000000001A020000F0040000A50200000000000040820046060000000C4275696C64204F757470757400000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0642726F777365000000007794000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2663 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE80300000000000000000000000000000000000000000000000100000001000000960000000200205000000000077069636F64657496000000000000000800077069636F6465741554564D46756E635265676973746572476C6F62616C0745525F44415441045352414D0C535F444154415F53544152540E5352414D5F57415445524D41524B077374646F75745F07776169745F75730000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000100150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 955 + 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2362 + 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1707 + 1067 + + + + + + 1 + 0 + + 100 + 0 + + .\main.c + 0 + 1 + 30 + 1 + + 0 + + + RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c + 0 + 441 + 481 + 1 + + 0 + + + + + diff --git a/object_segmentation/object_segmentation.uvoptx b/object_segmentation/object_segmentation.uvoptx new file mode 100644 index 0000000..159c368 --- /dev/null +++ b/object_segmentation/object_segmentation.uvoptx @@ -0,0 +1,447 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + PP_HumanSeg_M55 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + + BIN\DbgFMv8M.DLL + + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O200710 -C0 -MC".\VHT\VHT_Corstone_SSE-300.exe" -MF -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + PP_HumanSeg_M85 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + + BIN\DbgFMv8M.DLL + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)(6020=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O200710 -C0 -MC".\VHT\VHT_Corstone_SSE-310.exe" -MF -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Source + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\object_segmentation\codegen\host\src\object_segmentation_lib0.c + object_segmentation_lib0.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\object_segmentation\codegen\host\src\object_segmentation_lib1.c + object_segmentation_lib1.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\object_segmentation\runtime\src\runtime\crt\common\crt_backend_api.c + crt_backend_api.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS Driver + 0 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/object_segmentation/object_segmentation.uvprojx b/object_segmentation/object_segmentation.uvprojx new file mode 100644 index 0000000..6a2ab03 --- /dev/null +++ b/object_segmentation/object_segmentation.uvprojx @@ -0,0 +1,1414 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + PP_HumanSeg_M55 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-300-MPS3 + ARM + ARM.V2M_MPS3_SSE_300_BSP.1.4.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00080000) XRAM2(0x01000000,0x00100000) XRAM3(0x20000000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h + + + + + + + + + + $$Device:SSE-300-MPS3$SVD\SSE300.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + text_recognition + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x20000 + + + 0 + 0x20040000 + 0x20000 + + + 0 + 0x0 + 0x80000 + + + 0 + 0x1000000 + 0x200000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_PP_HUMANSEG + + .\object_segmentation\codegen\host\include;.\object_segmentation\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-300.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + object_segmentation_lib0.c + 1 + .\object_segmentation\codegen\host\src\object_segmentation_lib0.c + + + object_segmentation_lib1.c + 1 + .\object_segmentation\codegen\host\src\object_segmentation_lib1.c + + + crt_backend_api.c + 1 + .\object_segmentation\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + + + PP_HumanSeg_M85 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-310-MPS3_FVP + ARM + ARM.V2M_MPS3_SSE_310_BSP.1.3.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00008000) XRAM2(0x01000000,0x00200000) XRAM3(0x20000000,0x00002000) CPUTYPE("Cortex-M85") FPU3(DFPU) DSP TZ MVE(FP) PACBTI CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-310-MPS3_FVP$Device\Include\SSE310MPS3.h + + + + + + + + + + $$Device:SSE-310-MPS3_FVP$SVD\SSE310.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + text_recognition + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1000000 + 0x200000 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x30000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_PP_HUMANSEG + + .\include;.\object_segmentation\runtime\include;.\object_segmentation\codegen\host\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-310.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + object_segmentation_lib0.c + 1 + .\object_segmentation\codegen\host\src\object_segmentation_lib0.c + + + object_segmentation_lib1.c + 1 + .\object_segmentation\codegen\host\src\object_segmentation_lib1.c + + + crt_backend_api.c + 1 + .\object_segmentation\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::CMSIS Driver + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Compiler + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM85\ARMCM85_ac6.sct + + + + + + RTE\Device\ARMCM85\startup_ARMCM85.c + + + + + + RTE\Device\ARMCM85\system_ARMCM85.c + + + + + + RTE\Device\SSE-300-MPS3\RTE_Device.h + + + + + + + + RTE\Device\SSE-300-MPS3\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-300-MPS3\device_cfg.h + + + + + + + + RTE\Device\SSE-300-MPS3\linker_SSE300MPS3_secure.sct + + + + + + + + RTE\Device\SSE-300-MPS3\region_defs.h + + + + + + + + RTE\Device\SSE-300-MPS3\region_limits.h + + + + + + + + RTE\Device\SSE-300-MPS3\startup_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-300-MPS3\system_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\device_cfg.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\linker_SSE310MPS3_secure.sct + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_defs.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_limits.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\startup_SSE310MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\system_SSE310MPS3.c + + + + + + + + + + + + + base_project + 1 + + + + + diff --git a/object_segmentation/paddle_infer_shape.py b/object_segmentation/paddle_infer_shape.py new file mode 100644 index 0000000..5fa26e7 --- /dev/null +++ b/object_segmentation/paddle_infer_shape.py @@ -0,0 +1,101 @@ +# Copyright (c) 2020 PaddlePaddle Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License" +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import argparse + + +def process_old_ops_desc(program): + for i in range(len(program.blocks[0].ops)): + if program.blocks[0].ops[i].type == "matmul": + if not program.blocks[0].ops[i].has_attr("head_number"): + program.blocks[0].ops[i]._set_attr("head_number", 1) + + +def infer_shape(program, input_shape_dict): + import paddle + paddle.enable_static() + import paddle.fluid as fluid + + OP_WITHOUT_KERNEL_SET = { + 'feed', 'fetch', 'recurrent', 'go', 'rnn_memory_helper_grad', + 'conditional_block', 'while', 'send', 'recv', 'listen_and_serv', + 'fl_listen_and_serv', 'ncclInit', 'select', 'checkpoint_notify', + 'gen_bkcl_id', 'c_gen_bkcl_id', 'gen_nccl_id', 'c_gen_nccl_id', + 'c_comm_init', 'c_sync_calc_stream', 'c_sync_comm_stream', + 'queue_generator', 'dequeue', 'enqueue', 'heter_listen_and_serv', + 'c_wait_comm', 'c_wait_compute', 'c_gen_hccl_id', 'c_comm_init_hccl', + 'copy_cross_scope' + } + model_version = program.desc._version() + paddle_version = paddle.__version__ + major_ver = model_version // 1000000 + minor_ver = (model_version - major_ver * 1000000) // 1000 + patch_ver = model_version - major_ver * 1000000 - minor_ver * 1000 + model_version = "{}.{}.{}".format(major_ver, minor_ver, patch_ver) + if model_version != paddle_version: + print( + "[WARNING] The model is saved by paddlepaddle v{}, but now your paddlepaddle is version of {}, this difference may cause error, it is recommend you reinstall a same version of paddlepaddle for this model". + format(model_version, paddle_version)) + for k, v in input_shape_dict.items(): + program.blocks[0].var(k).desc.set_shape(v) + for i in range(len(program.blocks)): + for j in range(len(program.blocks[0].ops)): + if program.blocks[i].ops[j].type in OP_WITHOUT_KERNEL_SET: + continue + program.blocks[i].ops[j].desc.infer_shape(program.blocks[i].desc) + + +def parse_arguments(): + parser = argparse.ArgumentParser() + parser.add_argument( + '--model_dir', + required=True, + help='Path of directory saved the input model.') + parser.add_argument( + '--model_filename', required=True, help='The input model file name.') + parser.add_argument( + '--params_filename', required=True, help='The parameters file name.') + parser.add_argument( + '--save_dir', + required=True, + help='Path of directory to save the new exported model.') + parser.add_argument( + '--input_shape_dict', required=True, help="The new shape information.") + return parser.parse_args() + + +if __name__ == '__main__': + args = parse_arguments() + import paddle + paddle.enable_static() + import paddle.fluid as fluid + input_shape_dict_str = args.input_shape_dict + input_shape_dict = eval(input_shape_dict_str) + print("Start to load paddle model...") + exe = fluid.Executor(fluid.CPUPlace()) + [prog, ipts, outs] = fluid.io.load_inference_model( + args.model_dir, + exe, + model_filename=args.model_filename, + params_filename=args.params_filename) + process_old_ops_desc(prog) + infer_shape(prog, input_shape_dict) + fluid.io.save_inference_model( + args.save_dir, + ipts, + outs, + exe, + prog, + model_filename=args.model_filename, + params_filename=args.params_filename) diff --git a/object_segmentation/run_demo.sh b/object_segmentation/run_demo.sh new file mode 100644 index 0000000..aab68e5 --- /dev/null +++ b/object_segmentation/run_demo.sh @@ -0,0 +1,152 @@ +#!/bin/bash + +# Show usage +function show_usage() { + cat <&2 + show_usage >&2 + exit 1 + fi + ;; + + --device) + if [ $# -gt 1 ] + then + export DEVICE="$2" + shift 2 + else + echo 'ERROR: --device requires a non-empty argument' >&2 + show_usage >&2 + exit 1 + fi + ;; + + -*|--*) + echo "Error: Unknown flag: $1" >&2 + show_usage >&2 + exit 1 + ;; + esac +done + +echo "Device name is $DEVICE" +if [ "$DEVICE" == "cortex-m55" ]; then + RUN_DEVICE_NAME="M55" + VHT_Platform="VHT_MPS3_Corstone_SSE-300" + TVM_TARGET="cortex-m55" +elif [ "$DEVICE" == "cortex-m85" ]; then + RUN_DEVICE_NAME="M85" + VHT_Platform="VHT_Corstone_SSE-310" + TVM_TARGET="cortex-m85" +else + echo 'ERROR: --device only support cortex-m55/cortex-m85' >&2 + exit 1 +fi + +# download paddle model +echo "Model name is $MODEL_NAME" +if [ "$MODEL_NAME" == "PP_HumanSeg" ]; then + wget https://bj.bcebos.com/paddlehub/fastdeploy/Portrait_PP_HumanSegV2_Lite_256x144_with_argmax_infer.tgz + tar -xvf Portrait_PP_HumanSegV2_Lite_256x144_with_argmax_infer.tgz + rm Portrait_PP_HumanSegV2_Lite_256x144_with_argmax_infer.tgz + mv Portrait_PP_HumanSegV2_Lite_256x144_with_argmax_infer model + rm -rf __MACOSX + MODEL_NAME="PPHumanSeg" +else + echo 'ERROR: --model_name only support PP_HumanSeg' >&2 + exit 1 +fi + +# convert paddle model to onnx model +python paddle_infer_shape.py --model_dir model \ + --model_filename model.pdmodel \ + --params_filename model.pdiparams \ + --save_dir model \ + --input_shape_dict="{'x':[1,3,114,256]}" +paddle2onnx --model_dir "${PWD}/model" \ + --model_filename model.pdmodel \ + --params_filename model.pdiparams \ + --save_file model.onnx +rm -rf "${PWD}/model" + +# convert onnx model to tvm model +python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ + --target-cmsis-nn-mcpu="${TVM_TARGET}" \ + --target-c-mcpu="${TVM_TARGET}" \ + --runtime=crt \ + --executor=aot \ + --executor-aot-interface-api=c \ + --executor-aot-unpacked-api=1 \ + --pass-config tir.usmp.enable=1 \ + --pass-config tir.usmp.algorithm=hill_climb \ + --pass-config tir.disable_storage_rewrite=1 \ + --pass-config tir.disable_vectorize=1 model.onnx \ + --output-format=mlf \ + --model-format=onnx \ + --module-name=object_segmentation \ + --input-shapes "x:[1,3,114,256]" \ + --output=object_segmentation.tar +rm model.onnx + +# decompression cls.tar +mkdir -p "${PWD}/object_segmentation" +tar -xvf object_segmentation.tar -C "${PWD}/object_segmentation" +rm object_segmentation.tar + +# create input and output head file +python3 ./convert_image.py images/portrait_heng.jpg + +# build +csolution list packs -s object_segmentation.csolution.yml -m > packs.txt +cpackget update-index +cpackget add -f packs.txt +PROJECT_FILE_NAME="object_segmentation+$MODEL_NAME$RUN_DEVICE_NAME.cprj" +echo "Project file name is $PROJECT_FILE_NAME" +cbuild "$PROJECT_FILE_NAME" + +rm -rf "${PWD}/object_segmentation" +rm "${PWD}/include/inputs.h" +rm "${PWD}/include/outputs.h" + +# run +$VHT_Platform -C cpu0.CFGDTCMSZ=15 \ + -C cpu0.CFGITCMSZ=15 \ + -C mps3_board.uart0.out_file=\"uart0.txt\" \ + -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ + -C mps3_board.visualisation.disable-visualisation=1 \ + -C mps3_board.telnetterminal0.start_telnet=0 \ + -C mps3_board.telnetterminal1.start_telnet=0 \ + -C mps3_board.telnetterminal2.start_telnet=0 \ + -C mps3_board.telnetterminal5.start_telnet=0 \ + "out/object_segmentation/$MODEL_NAME$RUN_DEVICE_NAME/object_segmentation.axf" \ + --stat + +# Convert outputs to image +python3 ./convert_outputs.py uart0.txt + +# clean +rm -rf out +rm -rf tmp +rm -rf packs.txt \ No newline at end of file diff --git a/object_segmentation/sct/VHT_Corstone_SSE-300.sct b/object_segmentation/sct/VHT_Corstone_SSE-300.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/object_segmentation/sct/VHT_Corstone_SSE-300.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_segmentation/sct/VHT_Corstone_SSE-310.sct b/object_segmentation/sct/VHT_Corstone_SSE-310.sct new file mode 100644 index 0000000..27ffc47 --- /dev/null +++ b/object_segmentation/sct/VHT_Corstone_SSE-310.sct @@ -0,0 +1,119 @@ +; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping +; information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; + +;--------------------------------------------------------- +; First load region (SRAM/BRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00200000 +{ + ;----------------------------------------------------- + ; 0.5 MiB of SRAM/BRAM region. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + bram.bin 0x11000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x11080000 ALIGN 8 0x00080000 + { + .ANY(+ZI +RW) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/object_segmentation/vcpkg-configuration.json b/object_segmentation/vcpkg-configuration.json new file mode 100644 index 0000000..4e959b0 --- /dev/null +++ b/object_segmentation/vcpkg-configuration.json @@ -0,0 +1,27 @@ +{ + "default-registry": { + "kind": "git", + "baseline": "032d9d0820db290ce9ff644dabfdf564343013ae", + "repository": "https://github.com/microsoft/vcpkg" + }, + "registries": [ + { + "kind": "artifact", + "location": "https://aka.ms/vcpkg-ce-default", + "name": "microsoft" + }, + { + "kind": "artifact", + "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", + "name": "arm" + } + ], + "requires": { + "microsoft:cmake": "^3.25.2", + "microsoft:ninja": "^1.10.2", + "arm:compilers/arm/armclang": "^6.20.0", + "arm:compilers/arm/armclang": "^6.21.0", + "arm:debuggers/arm/armdbg": "^6.0.0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.0.0-0" + } +} \ No newline at end of file diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/device_cfg.h b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_defs.h b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_defs.h new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_defs.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_limits.h b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_limits.h new file mode 100644 index 0000000..20ccc08 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_limits.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x00000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/ocr/text_angle_classification/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_angle_classification/RTE/_CHPPOCRV2CLSM55/RTE_Components.h b/ocr/text_angle_classification/RTE/_CHPPOCRV2CLSM55/RTE_Components.h new file mode 100644 index 0000000..e3c85e2 --- /dev/null +++ b/ocr/text_angle_classification/RTE/_CHPPOCRV2CLSM55/RTE_Components.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'text_angle_classification+CHPPOCRV2CLSM55' + * Target: 'CHPPOCRV2CLSM55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ocr/text_angle_classification/RTE/_CHPPOCRV2CLSM85/RTE_Components.h b/ocr/text_angle_classification/RTE/_CHPPOCRV2CLSM85/RTE_Components.h new file mode 100644 index 0000000..6c78599 --- /dev/null +++ b/ocr/text_angle_classification/RTE/_CHPPOCRV2CLSM85/RTE_Components.h @@ -0,0 +1,32 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'text_angle_classification+CHPPOCRV2CLSM85' + * Target: 'CHPPOCRV2CLSM85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ocr/text_angle_classification/RTE/_CH_PPOCRV2_CLS_M55/RTE_Components.h b/ocr/text_angle_classification/RTE/_CH_PPOCRV2_CLS_M55/RTE_Components.h new file mode 100644 index 0000000..f84d2e8 --- /dev/null +++ b/ocr/text_angle_classification/RTE/_CH_PPOCRV2_CLS_M55/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'text_angle_classification' + * Target: 'CH_PPOCRV2_CLS_M55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ocr/text_angle_classification/RTE/_CH_PPOCRV2_CLS_M85/RTE_Components.h b/ocr/text_angle_classification/RTE/_CH_PPOCRV2_CLS_M85/RTE_Components.h new file mode 100644 index 0000000..aad266f --- /dev/null +++ b/ocr/text_angle_classification/RTE/_CH_PPOCRV2_CLS_M85/RTE_Components.h @@ -0,0 +1,33 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'text_angle_classification' + * Target: 'CH_PPOCRV2_CLS_M85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/OCR-example/Text-angle-classification-example/convert_image.py b/ocr/text_angle_classification/convert_image.py old mode 100755 new mode 100644 similarity index 96% rename from OCR-example/Text-angle-classification-example/convert_image.py rename to ocr/text_angle_classification/convert_image.py index 54459f2..04a3312 --- a/OCR-example/Text-angle-classification-example/convert_image.py +++ b/ocr/text_angle_classification/convert_image.py @@ -91,12 +91,7 @@ def create_headers(image_name): create_header_file("inputs", "text_angle_cls_input", img_data, "include") # Create output header file output_data = np.zeros([2], np.float32) - create_header_file( - "outputs", - "text_angle_cls_output", - output_data, - "include", - ) + create_header_file("outputs", "text_angle_cls_output", output_data, "include") if __name__ == "__main__": diff --git a/OCR-example/Text-angle-classification-example/imgs/README.md b/ocr/text_angle_classification/image/README.md similarity index 100% rename from OCR-example/Text-angle-classification-example/imgs/README.md rename to ocr/text_angle_classification/image/README.md diff --git a/OCR-example/Text-angle-classification-example/imgs/horizontal.png b/ocr/text_angle_classification/image/horizontal.png similarity index 100% rename from OCR-example/Text-angle-classification-example/imgs/horizontal.png rename to ocr/text_angle_classification/image/horizontal.png diff --git a/OCR-example/Text-recognition-example-m85/include/crt_config.h b/ocr/text_angle_classification/include/crt_config.h similarity index 100% rename from OCR-example/Text-recognition-example-m85/include/crt_config.h rename to ocr/text_angle_classification/include/crt_config.h diff --git a/OCR-example/Text-recognition-example-m85/include/tvm_runtime.h b/ocr/text_angle_classification/include/tvm_runtime.h similarity index 100% rename from OCR-example/Text-recognition-example-m85/include/tvm_runtime.h rename to ocr/text_angle_classification/include/tvm_runtime.h diff --git a/OCR-example/Text-angle-classification-example/src/demo_bare_metal.c b/ocr/text_angle_classification/main.c similarity index 95% rename from OCR-example/Text-angle-classification-example/src/demo_bare_metal.c rename to ocr/text_angle_classification/main.c index 197f5e3..ecff0ca 100644 --- a/OCR-example/Text-angle-classification-example/src/demo_bare_metal.c +++ b/ocr/text_angle_classification/main.c @@ -17,19 +17,18 @@ * under the License. */ +#include #include +#include #include #include - -#include "uart.h" - -// Header files generated by convert_image.py #include "inputs.h" #include "outputs.h" +#include "stdout_USART.h" int main(int argc, char** argv) { - uart_init(); + stdout_init(); printf("Starting text angle classification inference\n"); struct tvmgen_text_angle_cls_outputs text_angle_cls_outputs = { .output = text_angle_cls_output, diff --git a/ocr/text_angle_classification/run_demo.sh b/ocr/text_angle_classification/run_demo.sh new file mode 100644 index 0000000..6542e38 --- /dev/null +++ b/ocr/text_angle_classification/run_demo.sh @@ -0,0 +1,143 @@ +#!/bin/bash + +# Show usage +function show_usage() { + cat <&2 + show_usage >&2 + exit 1 + fi + ;; + + --device) + if [ $# -gt 1 ] + then + export DEVICE="$2" + shift 2 + else + echo 'ERROR: --device requires a non-empty argument' >&2 + show_usage >&2 + exit 1 + fi + ;; + + -*|--*) + echo "Error: Unknown flag: $1" >&2 + show_usage >&2 + exit 1 + ;; + esac +done + +echo "Device name is $DEVICE" +if [ "$DEVICE" == "cortex-m55" ]; then + RUN_DEVICE_NAME="M55" + VHT_Platform="VHT_MPS3_Corstone_SSE-300" + TVM_TARGET="cortex-m55" +elif [ "$DEVICE" == "cortex-m85" ]; then + RUN_DEVICE_NAME="M85" + VHT_Platform="VHT_Corstone_SSE-310" + TVM_TARGET="cortex-m85" +else + echo 'ERROR: --device only support cortex-m55/cortex-m85' >&2 + exit 1 +fi + +# download paddle model +echo "Model name is $MODEL_NAME" +if [ "$MODEL_NAME" == "CH_PPOCRV2_CLS" ]; then + wget https://paddleocr.bj.bcebos.com/dygraph_v2.0/ch/ch_ppocr_mobile_v2.0_cls_infer.tar + tar -xvf ch_ppocr_mobile_v2.0_cls_infer.tar + rm ch_ppocr_mobile_v2.0_cls_infer.tar + mv ch_ppocr_mobile_v2.0_cls_infer model + MODEL_NAME="CHPPOCRV2CLS" +else + echo 'ERROR: --model_name only support CH_PPOCRV2_CLS' >&2 + exit 1 +fi + +# convert paddle model to onnx model +paddle2onnx --model_dir "${PWD}/model" \ + --model_filename inference.pdmodel \ + --params_filename inference.pdiparams \ + --save_file model.onnx +rm -rf "${PWD}/model" + +# convert onnx model to tvm model +python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ + --target-cmsis-nn-mcpu="${TVM_TARGET}" \ + --target-c-mcpu="${TVM_TARGET}" \ + --runtime=crt \ + --executor=aot \ + --executor-aot-interface-api=c \ + --executor-aot-unpacked-api=1 \ + --pass-config tir.usmp.enable=1 \ + --pass-config tir.usmp.algorithm=hill_climb \ + --pass-config tir.disable_storage_rewrite=1 \ + --pass-config tir.disable_vectorize=1 model.onnx \ + --output-format=mlf \ + --model-format=onnx \ + --module-name=text_angle_cls \ + --input-shapes "x:[1,3,48,192]" \ + --output=text_angle_cls.tar +rm model.onnx + +# decompression cls.tar +mkdir -p "${PWD}/text_angle_cls" +tar -xvf text_angle_cls.tar -C "${PWD}/text_angle_cls" +rm text_angle_cls.tar + +# create input and output head file +python3 ./convert_image.py image/horizontal.png + +# build +csolution list packs -s text_angle_classification.csolution.yml -m > packs.txt +cpackget update-index +cpackget add -f packs.txt +PROJECT_FILE_NAME="text_angle_classification+$MODEL_NAME$RUN_DEVICE_NAME.cprj" +echo "Project file name is $PROJECT_FILE_NAME" +cbuild "$PROJECT_FILE_NAME" + +rm -rf "${PWD}/text_angle_cls" +rm "${PWD}/include/inputs.h" +rm "${PWD}/include/outputs.h" + +# run +$VHT_Platform -C cpu0.CFGDTCMSZ=15 \ + -C cpu0.CFGITCMSZ=15 \ + -C mps3_board.uart0.out_file=\"-\" \ + -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ + -C mps3_board.visualisation.disable-visualisation=1 \ + -C mps3_board.telnetterminal0.start_telnet=0 \ + -C mps3_board.telnetterminal1.start_telnet=0 \ + -C mps3_board.telnetterminal2.start_telnet=0 \ + -C mps3_board.telnetterminal5.start_telnet=0 \ + "out/text_angle_classification/$MODEL_NAME$RUN_DEVICE_NAME/text_angle_classification.axf" \ + --stat + +# clean +rm -rf out +rm -rf tmp +rm -rf packs.txt \ No newline at end of file diff --git a/ocr/text_angle_classification/sct/VHT_Corstone_SSE-300.sct b/ocr/text_angle_classification/sct/VHT_Corstone_SSE-300.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/ocr/text_angle_classification/sct/VHT_Corstone_SSE-300.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/ocr/text_angle_classification/sct/VHT_Corstone_SSE-310.sct b/ocr/text_angle_classification/sct/VHT_Corstone_SSE-310.sct new file mode 100644 index 0000000..27ffc47 --- /dev/null +++ b/ocr/text_angle_classification/sct/VHT_Corstone_SSE-310.sct @@ -0,0 +1,119 @@ +; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping +; information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; + +;--------------------------------------------------------- +; First load region (SRAM/BRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00200000 +{ + ;----------------------------------------------------- + ; 0.5 MiB of SRAM/BRAM region. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + bram.bin 0x11000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x11080000 ALIGN 8 0x00080000 + { + .ANY(+ZI +RW) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM55.cbuild.yml b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM55.cbuild.yml new file mode 100644 index 0000000..3a3c464 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM55.cbuild.yml @@ -0,0 +1,447 @@ +build: + generated-by: csolution version 2.2.1 + solution: text_angle_classification.csolution.yml + project: text_angle_classification.cproject.yml + context: text_angle_classification+CHPPOCRV2CLSM55 + compiler: AC6 + device: SSE-300-MPS3 + device-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M55 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_CH_PPOCRV2_CLS + - _RTE_ + add-path: + - text_angle_cls/codegen/host/include + - text_angle_cls/runtime/include + - include + - RTE/Device/SSE-300-MPS3 + - RTE/_CHPPOCRV2CLSM55 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Include + output-dirs: + intdir: tmp/text_angle_classification/CHPPOCRV2CLSM55 + outdir: out/text_angle_classification/CHPPOCRV2CLSM55 + rtedir: RTE + output: + - type: elf + file: text_angle_classification.axf + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + condition: SSE-300-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-300-MPS3/RTE_Device.h + category: header + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/cmsis_driver_config.h + category: header + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/device_cfg.h + category: header + attr: config + version: 1.1.3 + - component: ARM::Device:Native Driver:IO@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.0 + condition: SSE-300-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-300-MPS3/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct + category: linkerScript + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - component: ARM::Device:USART STDOUT@1.0.0 + condition: SSE-300-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:USART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-300.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: TextAngleClassification + files: + - file: text_angle_cls/codegen/host/src/text_angle_cls_lib0.c + category: sourceC + - file: text_angle_cls/codegen/host/src/text_angle_cls_lib1.c + category: sourceC + - file: text_angle_cls/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_CHPPOCRV2CLSM55/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.1.0 + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + - component: ARM::Device:Native Driver:Timeout@1.0.0 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:USART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM55.cprj b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM55.cprj new file mode 100644 index 0000000..200e533 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM55.cprj @@ -0,0 +1,68 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_CH_PPOCRV2_CLS + text_angle_cls/codegen/host/include;text_angle_cls/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM85.cbuild.yml b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM85.cbuild.yml new file mode 100644 index 0000000..c56923b --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM85.cbuild.yml @@ -0,0 +1,445 @@ +build: + generated-by: csolution version 2.2.1 + solution: text_angle_classification.csolution.yml + project: text_angle_classification.cproject.yml + context: text_angle_classification+CHPPOCRV2CLSM85 + compiler: AC6 + device: SSE-310-MPS3_FVP + device-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M85 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_CH_PPOCRV2_CLS + - CORSTONE310_FVP + - _RTE_ + add-path: + - include + - text_angle_cls/runtime/include + - text_angle_cls/codegen/host/include + - RTE/Device/SSE-310-MPS3_FVP + - RTE/_CHPPOCRV2CLSM85 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Include + output-dirs: + intdir: tmp/text_angle_classification/CHPPOCRV2CLSM85 + outdir: out/text_angle_classification/CHPPOCRV2CLSM85 + rtedir: RTE + output: + - type: elf + file: text_angle_classification.axf + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + condition: SSE-310-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/device_cfg.h + category: header + attr: config + version: 1.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.1 + condition: SSE-310-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-310-MPS3_FVP/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct + category: linkerScript + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - component: ARM::Device:UART STDOUT@1.0.0 + condition: SSE-310-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:UART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-310.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: TextAngleClassification + files: + - file: text_angle_cls/codegen/host/src/text_angle_cls_lib0.c + category: sourceC + - file: text_angle_cls/codegen/host/src/text_angle_cls_lib1.c + category: sourceC + - file: text_angle_cls/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + constructed-files: + - file: RTE/_CHPPOCRV2CLSM85/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + - component: ARM::Device:Native Driver:Timeout@1.0.1 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:UART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM85.cprj b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM85.cprj new file mode 100644 index 0000000..881d789 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification+CHPPOCRV2CLSM85.cprj @@ -0,0 +1,67 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_CH_PPOCRV2_CLS + include;text_angle_cls/runtime/include;text_angle_cls/codegen/host/include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ocr/text_angle_classification/text_angle_classification.cbuild-idx.yml b/ocr/text_angle_classification/text_angle_classification.cbuild-idx.yml new file mode 100644 index 0000000..a198684 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification.cbuild-idx.yml @@ -0,0 +1,12 @@ +build-idx: + generated-by: csolution version 2.2.1 + csolution: text_angle_classification.csolution.yml + cprojects: + - cproject: text_angle_classification.cproject.yml + cbuilds: + - cbuild: text_angle_classification+CHPPOCRV2CLSM55.cbuild.yml + project: text_angle_classification + configuration: +CHPPOCRV2CLSM55 + - cbuild: text_angle_classification+CHPPOCRV2CLSM85.cbuild.yml + project: text_angle_classification + configuration: +CHPPOCRV2CLSM85 diff --git a/ocr/text_angle_classification/text_angle_classification.cbuild-pack.yml b/ocr/text_angle_classification/text_angle_classification.cbuild-pack.yml new file mode 100644 index 0000000..b595c18 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification.cbuild-pack.yml @@ -0,0 +1,20 @@ +cbuild-pack: + resolved-packs: + - resolved-pack: ARM::CMSIS@5.9.0 + selected-by: + - ARM::CMSIS + - resolved-pack: ARM::CMSIS-DSP@1.15.0 + selected-by: + - ARM::CMSIS-DSP + - resolved-pack: ARM::CMSIS-NN@4.1.0 + selected-by: + - ARM::CMSIS-NN + - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: + - ARM::V2M_MPS3_SSE_300_BSP + - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: + - ARM::V2M_MPS3_SSE_310_BSP + - resolved-pack: Keil::ARM_Compiler@1.7.2 + selected-by: + - Keil::ARM_Compiler diff --git a/ocr/text_angle_classification/text_angle_classification.cproject.yml b/ocr/text_angle_classification/text_angle_classification.cproject.yml new file mode 100644 index 0000000..f41a024 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification.cproject.yml @@ -0,0 +1,146 @@ +project: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP + for-context: +CHPPOCRV2CLSM55 + - pack: ARM::V2M_MPS3_SSE_310_BSP + for-context: +CHPPOCRV2CLSM85 + - pack: ARM::CMSIS + - pack: ARM::CMSIS-DSP + - pack: ARM::CMSIS-NN + - pack: Keil::ARM_Compiler + setups: + - setup: Options for CHPPOCRV2CLSM55 + for-context: +CHPPOCRV2CLSM55 + processor: + trustzone: "off" + add-path: + - text_angle_cls/codegen/host/include + - text_angle_cls/runtime/include + - include + debug: "on" + define: + - USE_CH_PPOCRV2_CLS + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + - setup: Options for CHPPOCRV2CLSM85 + for-context: +CHPPOCRV2CLSM85 + processor: + trustzone: "off" + add-path: + - include + - text_angle_cls/runtime/include + - text_angle_cls/codegen/host/include + debug: "on" + define: + - USE_CH_PPOCRV2_CLS + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + linker: + - script: sct/VHT_Corstone_SSE-300.sct + for-context: +CHPPOCRV2CLSM55 + - script: sct/VHT_Corstone_SSE-310.sct + for-context: +CHPPOCRV2CLSM85 + groups: + - group: Source + files: + - file: main.c + - group: TextAngleClassification + files: + - file: text_angle_cls/codegen/host/src/text_angle_cls_lib0.c + - file: text_angle_cls/codegen/host/src/text_angle_cls_lib1.c + - file: text_angle_cls/runtime/src/runtime/crt/common/crt_backend_api.c + components: + - component: ARM::CMSIS Driver:USART + for-context: +CHPPOCRV2CLSM55 + - component: ARM::CMSIS Driver:USART + for-context: +CHPPOCRV2CLSM85 + - component: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source + - component: ARM::CMSIS:NN Lib + - component: ARM::Device:Definition + for-context: +CHPPOCRV2CLSM55 + - component: ARM::Device:Definition + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:Native Driver:IO + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:Native Driver:IO + for-context: +CHPPOCRV2CLSM55 + - component: ARM::Device:Native Driver:SysCounter + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:Native Driver:SysCounter + for-context: +CHPPOCRV2CLSM55 + - component: ARM::Device:Native Driver:SysTimer + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:Native Driver:SysTimer + for-context: +CHPPOCRV2CLSM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +CHPPOCRV2CLSM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:Native Driver:UART + for-context: +CHPPOCRV2CLSM55 + - component: ARM::Device:Native Driver:UART + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:Startup&C Startup + for-context: +CHPPOCRV2CLSM55 + - component: ARM::Device:Startup&C Startup + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:UART STDOUT + for-context: +CHPPOCRV2CLSM85 + - component: ARM::Device:USART STDOUT + for-context: +CHPPOCRV2CLSM55 + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User diff --git a/ocr/text_angle_classification/text_angle_classification.csolution.yml b/ocr/text_angle_classification/text_angle_classification.csolution.yml new file mode 100644 index 0000000..8571216 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification.csolution.yml @@ -0,0 +1,13 @@ +solution: + created-by: uv2csolution@1.2.0 + created-for: CMSIS-Toolbox@2.0.0 + compiler: AC6 + target-types: + - type: CHPPOCRV2CLSM55 + device: SSE-300-MPS3 + optimize: none + - type: CHPPOCRV2CLSM85 + device: SSE-310-MPS3_FVP + optimize: none + projects: + - project: text_angle_classification.cproject.yml diff --git a/ocr/text_angle_classification/text_angle_classification.uvoptx b/ocr/text_angle_classification/text_angle_classification.uvoptx new file mode 100644 index 0000000..9fc5f38 --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification.uvoptx @@ -0,0 +1,470 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + CH_PPOCRV2_CLS_M55 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + + BIN\DbgFMv8M.DLL + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)(6020=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O200710 -C0 -MC".\VHT\VHT_Corstone_SSE-300.exe" -MF -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + CH_PPOCRV2_CLS_M85 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + + BIN\DbgFMv8M.DLL + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)(6020=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O200710 -C0 -MC".\VHT\VHT_Corstone_SSE-310.exe" -MF -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Source + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + TextAngleClassification + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + .\text_angle_cls\codegen\host\src\text_angle_cls_lib0.c + text_angle_cls_lib0.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + .\text_angle_cls\codegen\host\src\text_angle_cls_lib1.c + text_angle_cls_lib1.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + .\text_angle_cls\runtime\src\runtime\crt\common\crt_backend_api.c + crt_backend_api.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS Driver + 0 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/ocr/text_angle_classification/text_angle_classification.uvprojx b/ocr/text_angle_classification/text_angle_classification.uvprojx new file mode 100644 index 0000000..928296e --- /dev/null +++ b/ocr/text_angle_classification/text_angle_classification.uvprojx @@ -0,0 +1,1424 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + CH_PPOCRV2_CLS_M55 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-300-MPS3 + ARM + ARM.V2M_MPS3_SSE_300_BSP.1.4.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00080000) XRAM2(0x01000000,0x00100000) XRAM3(0x20000000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h + + + + + + + + + + $$Device:SSE-300-MPS3$SVD\SSE300.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + text_angle_classification + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x20000 + + + 0 + 0x20040000 + 0x20000 + + + 0 + 0x0 + 0x80000 + + + 0 + 0x1000000 + 0x200000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_CH_PPOCRV2_CLS + + .\text_angle_cls\codegen\host\include;.\text_angle_cls\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-300.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + TextAngleClassification + + + text_angle_cls_lib0.c + 1 + .\text_angle_cls\codegen\host\src\text_angle_cls_lib0.c + + + text_angle_cls_lib1.c + 1 + .\text_angle_cls\codegen\host\src\text_angle_cls_lib1.c + + + crt_backend_api.c + 1 + .\text_angle_cls\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + + + CH_PPOCRV2_CLS_M85 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-310-MPS3_FVP + ARM + ARM.V2M_MPS3_SSE_310_BSP.1.3.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00008000) XRAM2(0x01000000,0x00200000) XRAM3(0x20000000,0x00002000) CPUTYPE("Cortex-M85") FPU3(DFPU) DSP TZ MVE(FP) PACBTI CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-310-MPS3_FVP$Device\Include\SSE310MPS3.h + + + + + + + + + + $$Device:SSE-310-MPS3_FVP$SVD\SSE310.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + text_angle_classification + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1000000 + 0x200000 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x30000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_CH_PPOCRV2_CLS + + .\include;.\text_angle_cls\runtime\include;.\text_angle_cls\codegen\host\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-310.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + TextAngleClassification + + + text_angle_cls_lib0.c + 1 + .\text_angle_cls\codegen\host\src\text_angle_cls_lib0.c + + + text_angle_cls_lib1.c + 1 + .\text_angle_cls\codegen\host\src\text_angle_cls_lib1.c + + + crt_backend_api.c + 1 + .\text_angle_cls\runtime\src\runtime\crt\common\crt_backend_api.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::CMSIS Driver + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Compiler + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM85\ARMCM85_ac6.sct + + + + + + RTE\Device\ARMCM85\startup_ARMCM85.c + + + + + + RTE\Device\ARMCM85\system_ARMCM85.c + + + + + + RTE\Device\SSE-300-MPS3\RTE_Device.h + + + + + + + + RTE\Device\SSE-300-MPS3\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-300-MPS3\device_cfg.h + + + + + + + + RTE\Device\SSE-300-MPS3\linker_SSE300MPS3_secure.sct + + + + + + + + RTE\Device\SSE-300-MPS3\region_defs.h + + + + + + + + RTE\Device\SSE-300-MPS3\region_limits.h + + + + + + + + RTE\Device\SSE-300-MPS3\startup_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-300-MPS3\system_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\device_cfg.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\linker_SSE310MPS3_secure.sct + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_defs.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_limits.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\startup_SSE310MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\system_SSE310MPS3.c + + + + + + + + + + + + + base_project + 1 + + + + + diff --git a/ocr/text_angle_classification/vcpkg-configuration.json b/ocr/text_angle_classification/vcpkg-configuration.json new file mode 100644 index 0000000..4e959b0 --- /dev/null +++ b/ocr/text_angle_classification/vcpkg-configuration.json @@ -0,0 +1,27 @@ +{ + "default-registry": { + "kind": "git", + "baseline": "032d9d0820db290ce9ff644dabfdf564343013ae", + "repository": "https://github.com/microsoft/vcpkg" + }, + "registries": [ + { + "kind": "artifact", + "location": "https://aka.ms/vcpkg-ce-default", + "name": "microsoft" + }, + { + "kind": "artifact", + "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", + "name": "arm" + } + ], + "requires": { + "microsoft:cmake": "^3.25.2", + "microsoft:ninja": "^1.10.2", + "arm:compilers/arm/armclang": "^6.20.0", + "arm:compilers/arm/armclang": "^6.21.0", + "arm:debuggers/arm/armdbg": "^6.0.0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.0.0-0" + } +} \ No newline at end of file diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/RTE_Device.h b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/RTE_Device.h new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/RTE_Device.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 new file mode 100644 index 0000000..3125547 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 1 + +// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] +// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC +#define RTE_ISRAM0_MPC 0 + +// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] +// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC +#define RTE_ISRAM1_MPC 0 + +// MPC (Memory Protection Controller) [Driver_SRAM_MPC] +// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC +#define RTE_SRAM_MPC 0 + +// MPC (Memory Protection Controller) [Driver_QSPI_MPC] +// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC +#define RTE_QSPI_MPC 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] +// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] +// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_MAIN_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] +// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] +// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP0 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP1 0 + +// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] +// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC +#define RTE_PPC_SSE300_PERIPH_EXP2 0 + +// Flash device emulated by SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +// I2C SBCon [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 new file mode 100644 index 0000000..bfc348f --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE300MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/device_cfg.h b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 new file mode 100644 index 0000000..2ff3eaa --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3 @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct.base@1.1.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_defs.h b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_defs.h new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_defs.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..32ac16b --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +#define S_DDR4_START ( S_DDR4_ALIAS ) +#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) +#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_limits.h b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_limits.h new file mode 100644 index 0000000..20ccc08 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_limits.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x00000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..e789786 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ + +/* Secure DDR4 */ +#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ +#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..72b39ca --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_recognition/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..4e67d53 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 new file mode 100644 index 0000000..35df89e --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h.base@1.0.0 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019-2022 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_DRIVER_CONFIG_H__ +#define __CMSIS_DRIVER_CONFIG_H__ + +#include "system_SSE310MPS3.h" +#include "device_cfg.h" +#include "device_definition.h" +#include "platform_base_address.h" + +#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 new file mode 100644 index 0000000..ce1adf2 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.0.0 @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2023 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 new file mode 100644 index 0000000..8b95c18 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct.base@1.0.0 @@ -0,0 +1,62 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +#include "region_defs.h" + +LR_CODE S_CODE_START { + ER_CODE S_CODE_START { + *.o (RESET +First) + .ANY (+RO) + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + CODE_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) + + ER_DATA S_DATA_START { + .ANY (+ZI +RW) + } + + #if HEAP_SIZE > 0 + ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap + } + #endif + + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { + } + + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) +} diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_defs.h b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_defs.h new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_defs.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 new file mode 100644 index 0000000..c8cd919 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_defs.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "region_limits.h" + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure regions */ +#define S_CODE_START ( S_ROM_ALIAS ) +#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) +#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) + +#define S_DATA_START ( S_RAM_ALIAS ) +#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) +#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) + +/* Non-Secure regions */ +#define NS_CODE_START ( NS_ROM_ALIAS ) +#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) +#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) + +#define NS_DATA_START ( NS_RAM_ALIAS ) +#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) +#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_limits.h b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_limits.h new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_limits.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 new file mode 100644 index 0000000..4ca8f99 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/region_limits.h.base@1.0.0 @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_LIMITS_H__ +#define __REGION_LIMITS_H__ + +/* ************************************************************** + * WARNING: this file is parsed both by the C/C++ compiler + * and the linker. As a result the syntax must be valid not only + * for C/C++ but for the linker scripts too. + * Beware of the following limitations: + * - LD (GCC linker) requires white space around operators. + * - UL postfix for macros is not suported by the linker script + ****************************************************************/ + +/* Secure Code */ +#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ +#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Secure Data */ +#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ +#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Non-Secure Code */ +#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ +#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ + +/* Non-Secure Data */ +#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ +#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ + +/* Heap and Stack sizes for secure and nonsecure applications */ +#define HEAP_SIZE (0x00000400) /* 1 KiB */ +#define STACK_SIZE (0x00000400) /* 1 KiB */ + +#endif /* __REGION_LIMITS_H__ */ diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..70cb828 --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __WEAK handler_name(void) __NO_RETURN; \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(VSI0_Handler) +DEFAULT_IRQ_HANDLER(VSI1_Handler) +DEFAULT_IRQ_HANDLER(VSI2_Handler) +DEFAULT_IRQ_HANDLER(VSI3_Handler) +DEFAULT_IRQ_HANDLER(VSI4_Handler) +DEFAULT_IRQ_HANDLER(VSI5_Handler) +DEFAULT_IRQ_HANDLER(VSI6_Handler) +DEFAULT_IRQ_HANDLER(VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + VSI0_Handler, /* 224: VSI 0 Handler */ + VSI1_Handler, /* 225: VSI 1 Handler */ + VSI2_Handler, /* 226: VSI 2 Handler */ + VSI3_Handler, /* 227: VSI 3 Handler */ + VSI4_Handler, /* 228: VSI 4 Handler */ + VSI5_Handler, /* 229: VSI 5 Handler */ + VSI6_Handler, /* 230: VSI 6 Handler */ + VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..1f05efb --- /dev/null +++ b/ocr/text_recognition/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/ocr/text_recognition/RTE/_ENPPOCRV3RECM55/RTE_Components.h b/ocr/text_recognition/RTE/_ENPPOCRV3RECM55/RTE_Components.h new file mode 100644 index 0000000..0ec168d --- /dev/null +++ b/ocr/text_recognition/RTE/_ENPPOCRV3RECM55/RTE_Components.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'text_recognition+ENPPOCRV3RECM55' + * Target: 'ENPPOCRV3RECM55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ocr/text_recognition/RTE/_ENPPOCRV3RECM85/RTE_Components.h b/ocr/text_recognition/RTE/_ENPPOCRV3RECM85/RTE_Components.h new file mode 100644 index 0000000..9f8644e --- /dev/null +++ b/ocr/text_recognition/RTE/_ENPPOCRV3RECM85/RTE_Components.h @@ -0,0 +1,32 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.2.1 + * + * Project: 'text_recognition+ENPPOCRV3RECM85' + * Target: 'ENPPOCRV3RECM85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ocr/text_recognition/RTE/_EN_PPOCRV3_REC_M55/RTE_Components.h b/ocr/text_recognition/RTE/_EN_PPOCRV3_REC_M55/RTE_Components.h new file mode 100644 index 0000000..a6ecbba --- /dev/null +++ b/ocr/text_recognition/RTE/_EN_PPOCRV3_REC_M55/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'text_angle_classification' + * Target: 'EN_PPOCRV3_REC_M55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ocr/text_recognition/RTE/_EN_PPOCRV3_REC_M85/RTE_Components.h b/ocr/text_recognition/RTE/_EN_PPOCRV3_REC_M85/RTE_Components.h new file mode 100644 index 0000000..9f70f56 --- /dev/null +++ b/ocr/text_recognition/RTE/_EN_PPOCRV3_REC_M85/RTE_Components.h @@ -0,0 +1,33 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'text_angle_classification' + * Target: 'EN_PPOCRV3_REC_M85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/OCR-example/Text-recognition-example/convert_image.py b/ocr/text_recognition/convert_image.py old mode 100755 new mode 100644 similarity index 95% rename from OCR-example/Text-recognition-example/convert_image.py rename to ocr/text_recognition/convert_image.py index e3e0619..01b58bc --- a/OCR-example/Text-recognition-example/convert_image.py +++ b/ocr/text_recognition/convert_image.py @@ -89,13 +89,8 @@ def create_headers(image_name): # Create input header file create_header_file("inputs", "input", img_data, "include") # Create output header file - output_data = np.zeros([7760], np.float) - create_header_file( - "outputs", - "output", - output_data, - "include", - ) + output_data = np.zeros([7760], np.float32) + create_header_file("outputs", "output", output_data, "include") if __name__ == "__main__": diff --git a/OCR-example/Text-recognition-example-m85/imgs_words_en/README.md b/ocr/text_recognition/imgs_words_en/README.md similarity index 100% rename from OCR-example/Text-recognition-example-m85/imgs_words_en/README.md rename to ocr/text_recognition/imgs_words_en/README.md diff --git a/OCR-example/Text-recognition-example-m85/imgs_words_en/word_10.png b/ocr/text_recognition/imgs_words_en/word_10.png similarity index 100% rename from OCR-example/Text-recognition-example-m85/imgs_words_en/word_10.png rename to ocr/text_recognition/imgs_words_en/word_10.png diff --git a/OCR-example/Text-recognition-example-m85/imgs_words_en/word_116.png b/ocr/text_recognition/imgs_words_en/word_116.png similarity index 100% rename from OCR-example/Text-recognition-example-m85/imgs_words_en/word_116.png rename to ocr/text_recognition/imgs_words_en/word_116.png diff --git a/OCR-example/Text-recognition-example/include/crt_config.h b/ocr/text_recognition/include/crt_config.h similarity index 100% rename from OCR-example/Text-recognition-example/include/crt_config.h rename to ocr/text_recognition/include/crt_config.h diff --git a/OCR-example/Text-recognition-example/include/tvm_runtime.h b/ocr/text_recognition/include/tvm_runtime.h similarity index 100% rename from OCR-example/Text-recognition-example/include/tvm_runtime.h rename to ocr/text_recognition/include/tvm_runtime.h diff --git a/OCR-example/Text-recognition-example/src/demo_bare_metal.c b/ocr/text_recognition/main.c similarity index 86% rename from OCR-example/Text-recognition-example/src/demo_bare_metal.c rename to ocr/text_recognition/main.c index 3f5f1bc..da82521 100644 --- a/OCR-example/Text-recognition-example/src/demo_bare_metal.c +++ b/ocr/text_recognition/main.c @@ -17,38 +17,37 @@ * under the License. */ +#include #include +#include #include -#include - -#include "uart.h" - -// Header files generated by convert_image.py +#include #include "inputs.h" #include "outputs.h" +#include "stdout_USART.h" int main(int argc, char** argv) { char dict[]={"#0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~!\"#$%&'()*+,-./ "}; int char_dict_nums = 97; - uart_init(); + stdout_init(); printf("Starting ocr rec inference\n"); - struct tvmgen_rec_outputs rec_outputs = { + struct tvmgen_text_recognition_outputs rec_outputs = { .output = output, }; - struct tvmgen_rec_inputs rec_inputs = { + struct tvmgen_text_recognition_inputs rec_inputs = { .x = input, }; - tvmgen_rec_run(&rec_inputs, &rec_outputs); + tvmgen_text_recognition_run(&rec_inputs, &rec_outputs); // post process int char_nums = output_len / char_dict_nums; - + int last_index = 0; float score = 0.f; int count = 0; - + printf("text: "); for (int i = 0; i < char_nums; i++) { int argmax_idx = 0; @@ -69,10 +68,9 @@ int main(int argc, char** argv) { } score /= count; printf(", score: %f\n", score); - + // The FVP will shut down when it receives "EXITTHESIM" on the UART printf("EXITTHESIM\n"); - while (1 == 1) - ; + while (1 == 1); return 0; -} +} \ No newline at end of file diff --git a/ocr/text_recognition/paddle_infer_shape.py b/ocr/text_recognition/paddle_infer_shape.py new file mode 100644 index 0000000..5fa26e7 --- /dev/null +++ b/ocr/text_recognition/paddle_infer_shape.py @@ -0,0 +1,101 @@ +# Copyright (c) 2020 PaddlePaddle Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License" +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import argparse + + +def process_old_ops_desc(program): + for i in range(len(program.blocks[0].ops)): + if program.blocks[0].ops[i].type == "matmul": + if not program.blocks[0].ops[i].has_attr("head_number"): + program.blocks[0].ops[i]._set_attr("head_number", 1) + + +def infer_shape(program, input_shape_dict): + import paddle + paddle.enable_static() + import paddle.fluid as fluid + + OP_WITHOUT_KERNEL_SET = { + 'feed', 'fetch', 'recurrent', 'go', 'rnn_memory_helper_grad', + 'conditional_block', 'while', 'send', 'recv', 'listen_and_serv', + 'fl_listen_and_serv', 'ncclInit', 'select', 'checkpoint_notify', + 'gen_bkcl_id', 'c_gen_bkcl_id', 'gen_nccl_id', 'c_gen_nccl_id', + 'c_comm_init', 'c_sync_calc_stream', 'c_sync_comm_stream', + 'queue_generator', 'dequeue', 'enqueue', 'heter_listen_and_serv', + 'c_wait_comm', 'c_wait_compute', 'c_gen_hccl_id', 'c_comm_init_hccl', + 'copy_cross_scope' + } + model_version = program.desc._version() + paddle_version = paddle.__version__ + major_ver = model_version // 1000000 + minor_ver = (model_version - major_ver * 1000000) // 1000 + patch_ver = model_version - major_ver * 1000000 - minor_ver * 1000 + model_version = "{}.{}.{}".format(major_ver, minor_ver, patch_ver) + if model_version != paddle_version: + print( + "[WARNING] The model is saved by paddlepaddle v{}, but now your paddlepaddle is version of {}, this difference may cause error, it is recommend you reinstall a same version of paddlepaddle for this model". + format(model_version, paddle_version)) + for k, v in input_shape_dict.items(): + program.blocks[0].var(k).desc.set_shape(v) + for i in range(len(program.blocks)): + for j in range(len(program.blocks[0].ops)): + if program.blocks[i].ops[j].type in OP_WITHOUT_KERNEL_SET: + continue + program.blocks[i].ops[j].desc.infer_shape(program.blocks[i].desc) + + +def parse_arguments(): + parser = argparse.ArgumentParser() + parser.add_argument( + '--model_dir', + required=True, + help='Path of directory saved the input model.') + parser.add_argument( + '--model_filename', required=True, help='The input model file name.') + parser.add_argument( + '--params_filename', required=True, help='The parameters file name.') + parser.add_argument( + '--save_dir', + required=True, + help='Path of directory to save the new exported model.') + parser.add_argument( + '--input_shape_dict', required=True, help="The new shape information.") + return parser.parse_args() + + +if __name__ == '__main__': + args = parse_arguments() + import paddle + paddle.enable_static() + import paddle.fluid as fluid + input_shape_dict_str = args.input_shape_dict + input_shape_dict = eval(input_shape_dict_str) + print("Start to load paddle model...") + exe = fluid.Executor(fluid.CPUPlace()) + [prog, ipts, outs] = fluid.io.load_inference_model( + args.model_dir, + exe, + model_filename=args.model_filename, + params_filename=args.params_filename) + process_old_ops_desc(prog) + infer_shape(prog, input_shape_dict) + fluid.io.save_inference_model( + args.save_dir, + ipts, + outs, + exe, + prog, + model_filename=args.model_filename, + params_filename=args.params_filename) diff --git a/ocr/text_recognition/run_demo.sh b/ocr/text_recognition/run_demo.sh new file mode 100644 index 0000000..e9dc883 --- /dev/null +++ b/ocr/text_recognition/run_demo.sh @@ -0,0 +1,149 @@ +#!/bin/bash + +# Show usage +function show_usage() { + cat <&2 + show_usage >&2 + exit 1 + fi + ;; + + --device) + if [ $# -gt 1 ] + then + export DEVICE="$2" + shift 2 + else + echo 'ERROR: --device requires a non-empty argument' >&2 + show_usage >&2 + exit 1 + fi + ;; + + -*|--*) + echo "Error: Unknown flag: $1" >&2 + show_usage >&2 + exit 1 + ;; + esac +done + +echo "Device name is $DEVICE" +if [ "$DEVICE" == "cortex-m55" ]; then + RUN_DEVICE_NAME="M55" + VHT_Platform="VHT_MPS3_Corstone_SSE-300" + TVM_TARGET="cortex-m55" +elif [ "$DEVICE" == "cortex-m85" ]; then + RUN_DEVICE_NAME="M85" + VHT_Platform="VHT_Corstone_SSE-310" + TVM_TARGET="cortex-m85" +else + echo 'ERROR: --device only support cortex-m55/cortex-m85' >&2 + exit 1 +fi + +# download paddle model +echo "Model name is $MODEL_NAME" +if [ "$MODEL_NAME" == "EN_PPOCRV3_REC" ]; then + echo -e "\e[36mDownload PaddlePaddle inference model\e[0m" + wget https://paddleocr.bj.bcebos.com/tvm/ocr_en.tar + tar -xf ocr_en.tar + mv ocr_en model + rm ocr_en.tar + MODEL_NAME="ENPPOCRV3REC" +else + echo 'ERROR: --model_name only support EN_PPOCRV3_REC' >&2 + exit 1 +fi + +# convert paddle model to onnx model +python paddle_infer_shape.py --model_dir model \ + --model_filename inference.pdmodel \ + --params_filename inference.pdiparams \ + --save_dir model \ + --input_shape_dict="{'x':[1,3,32,320]}" +paddle2onnx --model_dir "${PWD}/model" \ + --model_filename inference.pdmodel \ + --params_filename inference.pdiparams \ + --save_file model.onnx +rm -rf "${PWD}/model" + +# convert onnx model to tvm model +python3 -m tvm.driver.tvmc compile --target=cmsis-nn,c \ + --target-cmsis-nn-mcpu="${TVM_TARGET}" \ + --target-c-mcpu="${TVM_TARGET}" \ + --runtime=crt \ + --executor=aot \ + --executor-aot-interface-api=c \ + --executor-aot-unpacked-api=1 \ + --pass-config tir.usmp.enable=1 \ + --pass-config tir.usmp.algorithm=hill_climb \ + --pass-config tir.disable_storage_rewrite=1 \ + --pass-config tir.disable_vectorize=1 model.onnx \ + --output-format=mlf \ + --model-format=onnx \ + --module-name=text_recognition \ + --input-shapes "x:[1,3,32,320]" \ + --output=text_recognition.tar +rm model.onnx + +# decompression cls.tar +mkdir -p "${PWD}/text_recognition" +tar -xvf text_recognition.tar -C "${PWD}/text_recognition" +rm text_recognition.tar + +# create input and output head file +python3 ./convert_image.py imgs_words_en/word_116.png + +# build +csolution list packs -s text_recognition.csolution.yml -m > packs.txt +cpackget update-index +cpackget add -f packs.txt +PROJECT_FILE_NAME="text_recognition+$MODEL_NAME$RUN_DEVICE_NAME.cprj" +echo "Project file name is $PROJECT_FILE_NAME" +cbuild "$PROJECT_FILE_NAME" + +rm -rf "${PWD}/text_recognition" +rm "${PWD}/include/inputs.h" +rm "${PWD}/include/outputs.h" + +# run +$VHT_Platform -C cpu0.CFGDTCMSZ=15 \ + -C cpu0.CFGITCMSZ=15 \ + -C mps3_board.uart0.out_file=\"-\" \ + -C mps3_board.uart0.shutdown_tag=\"EXITTHESIM\" \ + -C mps3_board.visualisation.disable-visualisation=1 \ + -C mps3_board.telnetterminal0.start_telnet=0 \ + -C mps3_board.telnetterminal1.start_telnet=0 \ + -C mps3_board.telnetterminal2.start_telnet=0 \ + -C mps3_board.telnetterminal5.start_telnet=0 \ + "out/text_recognition/$MODEL_NAME$RUN_DEVICE_NAME/text_recognition.axf" \ + --stat + +# clean +rm -rf out +rm -rf tmp +rm -rf packs.txt \ No newline at end of file diff --git a/ocr/text_recognition/sct/VHT_Corstone_SSE-300.sct b/ocr/text_recognition/sct/VHT_Corstone_SSE-300.sct new file mode 100644 index 0000000..335fa77 --- /dev/null +++ b/ocr/text_recognition/sct/VHT_Corstone_SSE-300.sct @@ -0,0 +1,82 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc + +;/* +; * Copyright (c) 2018-2023 Arm Limited +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; */ + +LOAD_REGION_0 0x00000000 0x00080000 +{ + ; ITCM is used for code + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ; DTCM is used for any other RW or ZI data. + dtcm.bin 0x20000000 0x00060000 + { + .ANY(+ZI +RW) + } + + ; 32 kiB of stack space within the DTCM region. + ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 + {} + + ; This region should have 3 cycle read latency from both Cortex-M55 and Ethos-U NPU + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +; Second load region (DDR) +LOAD_REGION_1 0x60000000 0x02000000 +{ + ; 32 MiB of DDR space for neural network model input vectors and labels. + ddr.bin 0x60000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + ;.ANY (+RO-DATA) + } + + ; 768 KiB of remaining part of the 1MiB BRAM used as heap space. + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 + { + + } + + ; 32 MiB of model space for run-time load of model + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + { + + } + + ; 16 MiB of IFM space for run-time loading (FVP only) + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ; 16 MiB of OFM space for run-time loading (FVP only) + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/ocr/text_recognition/sct/VHT_Corstone_SSE-310.sct b/ocr/text_recognition/sct/VHT_Corstone_SSE-310.sct new file mode 100644 index 0000000..27ffc47 --- /dev/null +++ b/ocr/text_recognition/sct/VHT_Corstone_SSE-310.sct @@ -0,0 +1,119 @@ +; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping +; information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; + +;--------------------------------------------------------- +; First load region (SRAM/BRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00200000 +{ + ;----------------------------------------------------- + ; 0.5 MiB of SRAM/BRAM region. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + bram.bin 0x11000000 0x00080000 + { + *.o (RESET, +First) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x11080000 ALIGN 8 0x00080000 + { + .ANY(+ZI +RW) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + *.o (.bss.noinit.*) + *.o (.rodata.tvm) + *.o (.data.tvm) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} \ No newline at end of file diff --git a/ocr/text_recognition/text_recognition+ENPPOCRV3RECM55.cbuild.yml b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM55.cbuild.yml new file mode 100644 index 0000000..5e749df --- /dev/null +++ b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM55.cbuild.yml @@ -0,0 +1,447 @@ +build: + generated-by: csolution version 2.2.1 + solution: text_recognition.csolution.yml + project: text_recognition.cproject.yml + context: text_recognition+ENPPOCRV3RECM55 + compiler: AC6 + device: SSE-300-MPS3 + device-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M55 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_EN_PPOCRV3_REC + - _RTE_ + add-path: + - text_recognition/codegen/host/include + - text_recognition/runtime/include + - include + - RTE/Device/SSE-300-MPS3 + - RTE/_ENPPOCRV3RECM55 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Include + output-dirs: + intdir: tmp/text_recognition/ENPPOCRV3RECM55 + outdir: out/text_recognition/ENPPOCRV3RECM55 + rtedir: RTE + output: + - type: elf + file: text_recognition.axf + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + condition: SSE-300-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-300-MPS3/RTE_Device.h + category: header + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/cmsis_driver_config.h + category: header + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/device_cfg.h + category: header + attr: config + version: 1.1.3 + - component: ARM::Device:Native Driver:IO@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.0 + condition: SSE-300-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-300-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-300-MPS3/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct + category: linkerScript + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - file: RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c + category: source + attr: config + version: 1.1.1 + - component: ARM::Device:USART STDOUT@1.0.0 + condition: SSE-300-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: ARM::Device:USART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.4.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-300.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: TextAngleClassification + files: + - file: text_recognition/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + - file: text_recognition/codegen/host/src/text_recognition_lib0.c + category: sourceC + - file: text_recognition/codegen/host/src/text_recognition_lib1.c + category: sourceC + constructed-files: + - file: RTE/_ENPPOCRV3RECM55/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + components: + - component: ARM::CMSIS Driver:USART@1.0.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.1.0 + - component: ARM::Device:Native Driver:SysCounter@1.1.0 + - component: ARM::Device:Native Driver:SysTimer@1.1.0 + - component: ARM::Device:Native Driver:Timeout@1.0.0 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:USART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/ocr/text_recognition/text_recognition+ENPPOCRV3RECM55.cprj b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM55.cprj new file mode 100644 index 0000000..0135c88 --- /dev/null +++ b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM55.cprj @@ -0,0 +1,68 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_EN_PPOCRV3_REC + text_recognition/codegen/host/include;text_recognition/runtime/include;include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ocr/text_recognition/text_recognition+ENPPOCRV3RECM85.cbuild.yml b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM85.cbuild.yml new file mode 100644 index 0000000..1a53e8b --- /dev/null +++ b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM85.cbuild.yml @@ -0,0 +1,445 @@ +build: + generated-by: csolution version 2.2.1 + solution: text_recognition.csolution.yml + project: text_recognition.cproject.yml + context: text_recognition+ENPPOCRV3RECM85 + compiler: AC6 + device: SSE-310-MPS3_FVP + device-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + processor: + dsp: on + fpu: dp + trustzone: off + core: Cortex-M85 + packs: + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@5.9.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0 + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0 + - pack: Keil::ARM_Compiler@1.7.2 + path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2 + optimize: none + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=c99 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + define: + - USE_EN_PPOCRV3_REC + - CORSTONE310_FVP + - _RTE_ + add-path: + - include + - text_recognition/runtime/include + - text_recognition/codegen/host/include + - RTE/Device/SSE-310-MPS3_FVP + - RTE/_ENPPOCRV3RECM85 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Driver/Include + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Platform + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver + - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Include + output-dirs: + intdir: tmp/text_recognition/ENPPOCRV3RECM85 + outdir: out/text_recognition/ENPPOCRV3RECM85 + rtedir: RTE + output: + - type: elf + file: text_recognition.axf + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + condition: SSE-310-MPS3 USART + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::CMSIS Driver:USART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/CMSIS_Driver/Driver_USART.c + category: source + - component: ARM::CMSIS:CORE@5.6.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source@1.10.0 + condition: CMSIS DSP + from-pack: ARM::CMSIS@5.9.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_w.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_x.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_y.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConcatenationFunctions/arm_concatenation_s8_z.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/FullyConnectedFunctions/arm_fully_connected_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/LSTMFunctions/arm_lstm_unidirectional_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_calculate_gate_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_step_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_cell_state_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_lstm_update_output_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mul_result_acc_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_nntables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_get_buffer_sizes_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_avgpool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/PoolingFunctions/arm_max_pool_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ReshapeFunctions/arm_reshape_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SVDFunctions/arm_svdf_state_s16_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_s8_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/SoftmaxFunctions/arm_softmax_u8.c + category: source + - component: ARM::Device:Definition@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Definition + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Board/Device_Definition/device_definition.c + category: source + - file: RTE/Device/SSE-310-MPS3_FVP/cmsis_driver_config.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/device_cfg.h + category: header + attr: config + version: 1.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:IO + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/arm_mps3_io_drv.c + category: source + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysCounter + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_cntrl_drv.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/syscounter_armv8-m_read_drv.c + category: source + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:SysTimer + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_drv.c + category: source + - component: ARM::Device:Native Driver:Timeout@1.0.1 + condition: SSE-310-MPS3 Systimer Syscounter + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:Timeout + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/systimer_armv8-m_timeout.c + category: source + - component: ARM::Device:Native Driver:UART@1.1.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Native Driver:UART + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/uart_cmsdk_drv.c + category: source + - component: ARM::Device:Startup&C Startup@2.0.0 + condition: SSE-310-MPS3 Device + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:Startup&C Startup + files: + - file: RTE/Device/SSE-310-MPS3_FVP/region_defs.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/region_limits.h + category: header + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/linker_SSE310MPS3_secure.sct + category: linkerScript + attr: config + version: 1.0.0 + - file: RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - file: RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c + category: source + attr: config + version: 1.1.0 + - component: ARM::Device:UART STDOUT@1.0.0 + condition: SSE-310-MPS3 USART STDOUT + from-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: ARM::Device:UART STDOUT + files: + - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_310_BSP/1.3.0/Device/Source/stdout_USART.c + category: source + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 + condition: ARMCC Cortex-M + from-pack: Keil::ARM_Compiler@1.7.2 + selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&User + files: + - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c + category: source + linker: + script: sct/VHT_Corstone_SSE-310.sct + groups: + - group: Source + files: + - file: main.c + category: sourceC + - group: TextAngleClassification + files: + - file: text_recognition/runtime/src/runtime/crt/common/crt_backend_api.c + category: sourceC + - file: text_recognition/codegen/host/src/text_recognition_lib0.c + category: sourceC + - file: text_recognition/codegen/host/src/text_recognition_lib1.c + category: sourceC + constructed-files: + - file: RTE/_ENPPOCRV3RECM85/RTE_Components.h + category: header + licenses: + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + packs: + - pack: ARM::CMSIS@5.9.0 + components: + - component: ::CMSIS Driver:USART(API) + - component: ARM::CMSIS:CORE@5.6.0 + - component: ARM::CMSIS:DSP&Source@1.10.0 + - license: + packs: + - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + components: + - component: ARM::CMSIS Driver:USART@1.1.0 + - component: ARM::Device:Definition@2.0.0 + - component: ARM::Device:Native Driver:IO@1.0.1 + - component: ARM::Device:Native Driver:SysCounter@1.0.1 + - component: ARM::Device:Native Driver:SysTimer@1.0.0 + - component: ARM::Device:Native Driver:Timeout@1.0.1 + - component: ARM::Device:Native Driver:UART@1.1.0 + - component: ARM::Device:Startup&C Startup@2.0.0 + - component: ARM::Device:UART STDOUT@1.0.0 + - license: + packs: + - pack: Keil::ARM_Compiler@1.7.2 + components: + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User@1.2.0 diff --git a/ocr/text_recognition/text_recognition+ENPPOCRV3RECM85.cprj b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM85.cprj new file mode 100644 index 0000000..b061702 --- /dev/null +++ b/ocr/text_recognition/text_recognition+ENPPOCRV3RECM85.cprj @@ -0,0 +1,67 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + USE_EN_PPOCRV3_REC + include;text_recognition/runtime/include;text_recognition/codegen/host/include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ocr/text_recognition/text_recognition.cbuild-idx.yml b/ocr/text_recognition/text_recognition.cbuild-idx.yml new file mode 100644 index 0000000..db1f9b9 --- /dev/null +++ b/ocr/text_recognition/text_recognition.cbuild-idx.yml @@ -0,0 +1,12 @@ +build-idx: + generated-by: csolution version 2.2.1 + csolution: text_recognition.csolution.yml + cprojects: + - cproject: text_recognition.cproject.yml + cbuilds: + - cbuild: text_recognition+ENPPOCRV3RECM55.cbuild.yml + project: text_recognition + configuration: +ENPPOCRV3RECM55 + - cbuild: text_recognition+ENPPOCRV3RECM85.cbuild.yml + project: text_recognition + configuration: +ENPPOCRV3RECM85 diff --git a/ocr/text_recognition/text_recognition.cbuild-pack.yml b/ocr/text_recognition/text_recognition.cbuild-pack.yml new file mode 100644 index 0000000..b595c18 --- /dev/null +++ b/ocr/text_recognition/text_recognition.cbuild-pack.yml @@ -0,0 +1,20 @@ +cbuild-pack: + resolved-packs: + - resolved-pack: ARM::CMSIS@5.9.0 + selected-by: + - ARM::CMSIS + - resolved-pack: ARM::CMSIS-DSP@1.15.0 + selected-by: + - ARM::CMSIS-DSP + - resolved-pack: ARM::CMSIS-NN@4.1.0 + selected-by: + - ARM::CMSIS-NN + - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + selected-by: + - ARM::V2M_MPS3_SSE_300_BSP + - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0 + selected-by: + - ARM::V2M_MPS3_SSE_310_BSP + - resolved-pack: Keil::ARM_Compiler@1.7.2 + selected-by: + - Keil::ARM_Compiler diff --git a/ocr/text_recognition/text_recognition.cproject.yml b/ocr/text_recognition/text_recognition.cproject.yml new file mode 100644 index 0000000..51f26b8 --- /dev/null +++ b/ocr/text_recognition/text_recognition.cproject.yml @@ -0,0 +1,146 @@ +project: + packs: + - pack: ARM::V2M_MPS3_SSE_300_BSP + for-context: +ENPPOCRV3RECM55 + - pack: ARM::V2M_MPS3_SSE_310_BSP + for-context: +ENPPOCRV3RECM85 + - pack: ARM::CMSIS + - pack: ARM::CMSIS-DSP + - pack: ARM::CMSIS-NN + - pack: Keil::ARM_Compiler + setups: + - setup: Options for ENPPOCRV3RECM55 + for-context: +ENPPOCRV3RECM55 + processor: + trustzone: "off" + add-path: + - text_recognition/codegen/host/include + - text_recognition/runtime/include + - include + debug: "on" + define: + - USE_EN_PPOCRV3_REC + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + - setup: Options for ENPPOCRV3RECM85 + for-context: +ENPPOCRV3RECM85 + processor: + trustzone: "off" + add-path: + - include + - text_recognition/runtime/include + - text_recognition/codegen/host/include + debug: "on" + define: + - USE_EN_PPOCRV3_REC + misc: + - C: + - -std=c99 + C-CPP: + - -mthumb + - -fno-rtti + - -funsigned-char + - -fshort-enums + - -fshort-wchar + - -ffunction-sections + - -w + CPP: + - -xc++ + - -std=c++11 + ASM: + - -masm=auto + Link: + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --strict + - --summary_stderr + - --info summarysizes + linker: + - script: sct/VHT_Corstone_SSE-300.sct + for-context: +ENPPOCRV3RECM55 + - script: sct/VHT_Corstone_SSE-310.sct + for-context: +ENPPOCRV3RECM85 + groups: + - group: Source + files: + - file: main.c + - group: TextAngleClassification + files: + - file: text_recognition/runtime/src/runtime/crt/common/crt_backend_api.c + - file: text_recognition/codegen/host/src/text_recognition_lib0.c + - file: text_recognition/codegen/host/src/text_recognition_lib1.c + components: + - component: ARM::CMSIS Driver:USART + for-context: +ENPPOCRV3RECM55 + - component: ARM::CMSIS Driver:USART + for-context: +ENPPOCRV3RECM85 + - component: ARM::CMSIS:CORE + - component: ARM::CMSIS:DSP&Source + - component: ARM::CMSIS:NN Lib + - component: ARM::Device:Definition + for-context: +ENPPOCRV3RECM55 + - component: ARM::Device:Definition + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:Native Driver:IO + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:Native Driver:IO + for-context: +ENPPOCRV3RECM55 + - component: ARM::Device:Native Driver:SysCounter + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:Native Driver:SysCounter + for-context: +ENPPOCRV3RECM55 + - component: ARM::Device:Native Driver:SysTimer + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:Native Driver:SysTimer + for-context: +ENPPOCRV3RECM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +ENPPOCRV3RECM55 + - component: ARM::Device:Native Driver:Timeout + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:Native Driver:UART + for-context: +ENPPOCRV3RECM55 + - component: ARM::Device:Native Driver:UART + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:Startup&C Startup + for-context: +ENPPOCRV3RECM55 + - component: ARM::Device:Startup&C Startup + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:UART STDOUT + for-context: +ENPPOCRV3RECM85 + - component: ARM::Device:USART STDOUT + for-context: +ENPPOCRV3RECM55 + - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&User diff --git a/ocr/text_recognition/text_recognition.csolution.yml b/ocr/text_recognition/text_recognition.csolution.yml new file mode 100644 index 0000000..dd872ed --- /dev/null +++ b/ocr/text_recognition/text_recognition.csolution.yml @@ -0,0 +1,13 @@ +solution: + created-by: uv2csolution@1.2.0 + created-for: CMSIS-Toolbox@2.0.0 + compiler: AC6 + target-types: + - type: ENPPOCRV3RECM55 + device: SSE-300-MPS3 + optimize: none + - type: ENPPOCRV3RECM85 + device: SSE-310-MPS3_FVP + optimize: none + projects: + - project: text_recognition.cproject.yml diff --git a/ocr/text_recognition/text_recognition.uvoptx b/ocr/text_recognition/text_recognition.uvoptx new file mode 100644 index 0000000..5b694c2 --- /dev/null +++ b/ocr/text_recognition/text_recognition.uvoptx @@ -0,0 +1,470 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + EN_PPOCRV3_REC_M55 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + + BIN\DbgFMv8M.DLL + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)(6020=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O200710 -C0 -MC".\VHT\VHT_Corstone_SSE-300.exe" -MF -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + EN_PPOCRV3_REC_M85 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + + BIN\DbgFMv8M.DLL + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)(6020=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O200710 -C0 -MC".\VHT\VHT_Corstone_SSE-310.exe" -MF -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Source + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + TextAngleClassification + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + .\text_recognition\runtime\src\runtime\crt\common\crt_backend_api.c + crt_backend_api.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + .\text_recognition\codegen\host\src\text_recognition_lib0.c + text_recognition_lib0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + .\text_recognition\codegen\host\src\text_recognition_lib1.c + text_recognition_lib1.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS Driver + 0 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/ocr/text_recognition/text_recognition.uvprojx b/ocr/text_recognition/text_recognition.uvprojx new file mode 100644 index 0000000..2794061 --- /dev/null +++ b/ocr/text_recognition/text_recognition.uvprojx @@ -0,0 +1,1424 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + EN_PPOCRV3_REC_M55 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-300-MPS3 + ARM + ARM.V2M_MPS3_SSE_300_BSP.1.4.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00080000) XRAM2(0x01000000,0x00100000) XRAM3(0x20000000,0x00020000) CPUTYPE("Cortex-M55") FPU3(DFPU) DSP TZ MVE(FP) CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-300-MPS3$Device\Include\SSE300MPS3.h + + + + + + + + + + $$Device:SSE-300-MPS3$SVD\SSE300.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + text_recognition + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x20000 + + + 0 + 0x20040000 + 0x20000 + + + 0 + 0x0 + 0x80000 + + + 0 + 0x1000000 + 0x200000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_EN_PPOCRV3_REC + + .\text_recognition\codegen\host\include;.\text_recognition\runtime\include;.\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-300.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + TextAngleClassification + + + crt_backend_api.c + 1 + .\text_recognition\runtime\src\runtime\crt\common\crt_backend_api.c + + + text_recognition_lib0.c + 1 + .\text_recognition\codegen\host\src\text_recognition_lib0.c + + + text_recognition_lib1.c + 1 + .\text_recognition\codegen\host\src\text_recognition_lib1.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + + + EN_PPOCRV3_REC_M85 + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + SSE-310-MPS3_FVP + ARM + ARM.V2M_MPS3_SSE_310_BSP.1.3.0 + http://www.keil.com/pack/ + IRAM(0x30000000,0x00020000) IRAM2(0x20000000,0x00020000) IROM(0x10000000,0x00200000) IROM2(0x00000000,0x00200000) XRAM(0x00000000,0x00008000) XRAM2(0x01000000,0x00200000) XRAM3(0x20000000,0x00002000) CPUTYPE("Cortex-M85") FPU3(DFPU) DSP TZ MVE(FP) PACBTI CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD30000000 -FC1000) + 0 + $$Device:SSE-310-MPS3_FVP$Device\Include\SSE310MPS3.h + + + + + + + + + + $$Device:SSE-310-MPS3_FVP$SVD\SSE310.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + text_recognition + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 2 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x20000 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x200000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1000000 + 0x200000 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x30000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -mthumb + USE_EN_PPOCRV3_REC + + .\include;.\text_recognition\runtime\include;.\text_recognition\codegen\host\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x70000000 + + .\sct\VHT_Corstone_SSE-310.sct + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + + + TextAngleClassification + + + crt_backend_api.c + 1 + .\text_recognition\runtime\src\runtime\crt\common\crt_backend_api.c + + + text_recognition_lib0.c + 1 + .\text_recognition\codegen\host\src\text_recognition_lib0.c + + + text_recognition_lib1.c + 1 + .\text_recognition\codegen\host\src\text_recognition_lib1.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::CMSIS Driver + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Compiler + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM85\ARMCM85_ac6.sct + + + + + + RTE\Device\ARMCM85\startup_ARMCM85.c + + + + + + RTE\Device\ARMCM85\system_ARMCM85.c + + + + + + RTE\Device\SSE-300-MPS3\RTE_Device.h + + + + + + + + RTE\Device\SSE-300-MPS3\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-300-MPS3\device_cfg.h + + + + + + + + RTE\Device\SSE-300-MPS3\linker_SSE300MPS3_secure.sct + + + + + + + + RTE\Device\SSE-300-MPS3\region_defs.h + + + + + + + + RTE\Device\SSE-300-MPS3\region_limits.h + + + + + + + + RTE\Device\SSE-300-MPS3\startup_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-300-MPS3\system_SSE300MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\cmsis_driver_config.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\device_cfg.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\linker_SSE310MPS3_secure.sct + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_defs.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\region_limits.h + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\startup_SSE310MPS3.c + + + + + + + + RTE\Device\SSE-310-MPS3_FVP\system_SSE310MPS3.c + + + + + + + + + + + + + base_project + 1 + + + + + diff --git a/ocr/text_recognition/vcpkg-configuration.json b/ocr/text_recognition/vcpkg-configuration.json new file mode 100644 index 0000000..4e959b0 --- /dev/null +++ b/ocr/text_recognition/vcpkg-configuration.json @@ -0,0 +1,27 @@ +{ + "default-registry": { + "kind": "git", + "baseline": "032d9d0820db290ce9ff644dabfdf564343013ae", + "repository": "https://github.com/microsoft/vcpkg" + }, + "registries": [ + { + "kind": "artifact", + "location": "https://aka.ms/vcpkg-ce-default", + "name": "microsoft" + }, + { + "kind": "artifact", + "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", + "name": "arm" + } + ], + "requires": { + "microsoft:cmake": "^3.25.2", + "microsoft:ninja": "^1.10.2", + "arm:compilers/arm/armclang": "^6.20.0", + "arm:compilers/arm/armclang": "^6.21.0", + "arm:debuggers/arm/armdbg": "^6.0.0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.0.0-0" + } +} \ No newline at end of file diff --git a/scripts/config_cmsis_toolbox.sh b/scripts/config_cmsis_toolbox.sh new file mode 100644 index 0000000..eb68e47 --- /dev/null +++ b/scripts/config_cmsis_toolbox.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +# download cmsis-toolbox +cmsis_toolbox_name="cmsis-toolbox-linux-amd64" +cmsis_toolbox_version="2.2.1" +cmsis_toolbox_url="https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases/download/${cmsis_toolbox_version}/${cmsis_toolbox_name}.tar.gz" +wget ${cmsis_toolbox_url} +tar -vxf ${cmsis_toolbox_name}.tar.gz +rm ${cmsis_toolbox_name}.tar.gz + +# copy to opt +mv ${cmsis_toolbox_name} ctools +rm -rf /opt/ctools +mv ctools /opt \ No newline at end of file diff --git a/scripts/config_tvm.sh b/scripts/config_tvm.sh new file mode 100644 index 0000000..530da63 --- /dev/null +++ b/scripts/config_tvm.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +echo 'export PATH=/home/ubuntu/.local/bin:$PATH' >> ~/.bashrc +source ~/.bashrc +pip install --upgrade pip +pip install opencv-python +pip install apache-tvm +pip install paddle2onnx +pip install onnx +pip install paddlepaddle \ No newline at end of file