diff --git a/docs/changelog.md b/docs/changelog.md
index b610dc6e..00605d8b 100644
--- a/docs/changelog.md
+++ b/docs/changelog.md
@@ -9,6 +9,8 @@
 - AerBackend now reject circuits with too many qubits
 - Update pytket version requirement to 1.37.0.
 - Update qiskit version requirement to 1.3.1.
+- Fix conversion of circuits containing multiple operations conditioned on the
+  same scratch bit.
 
 ## 0.61.0 (December 2024)
 
diff --git a/pytket/extensions/qiskit/qiskit_convert.py b/pytket/extensions/qiskit/qiskit_convert.py
index 0a84eee1..31fad552 100644
--- a/pytket/extensions/qiskit/qiskit_convert.py
+++ b/pytket/extensions/qiskit/qiskit_convert.py
@@ -662,6 +662,8 @@ def append_tk_command_to_qiskit(
         bit = args[1]
         qb = qregmap[qubit.reg_name][qubit.index[0]]
         b = cregmap[bit.reg_name][bit.index[0]]
+        # If the bit is storing a range predicate it should be invalidated:
+        range_preds.pop(bit, None)
         return qcirc.measure(qb, b)
 
     if optype == OpType.Reset:
@@ -745,7 +747,6 @@ def append_tk_command_to_qiskit(
         if args[0] in range_preds:
             assert op.value == 1  # type: ignore
             condition_bits, value = range_preds[args[0]]  # type: ignore
-            del range_preds[args[0]]  # type: ignore
             args = condition_bits + args[1:]
             width = len(condition_bits)
         else:
diff --git a/tests/qiskit_convert_test.py b/tests/qiskit_convert_test.py
index b490525e..a90da2b4 100644
--- a/tests/qiskit_convert_test.py
+++ b/tests/qiskit_convert_test.py
@@ -77,6 +77,7 @@
     RebaseTket,
     SequencePass,
 )
+from pytket.unit_id import _TEMP_BIT_NAME
 from pytket.utils.results import (
     compare_statevectors,
     compare_unitaries,
@@ -1190,3 +1191,16 @@ def test_nonregister_bits() -> None:
     c.rename_units({Bit(0): Bit(1)})
     with pytest.raises(NotImplementedError):
         tk_to_qiskit(c)
+
+
+def test_range_preds_with_conditionals():
+    # https://github.com/CQCL/pytket-qiskit/issues/375
+    c = Circuit(1, 1)
+    treg = c.add_c_register(_TEMP_BIT_NAME, 1)
+    c.add_c_range_predicate(1, 1, [Bit(0)], treg[0])
+    c.add_gate(OpType.X, [Qubit(0)], condition_bits=[treg[0]], condition_value=1)
+    c.add_gate(OpType.Y, [Qubit(0)], condition_bits=[treg[0]], condition_value=1)
+    qkc = tk_to_qiskit(c)
+    assert len(qkc) == 2
+    assert len(qkc.qubits) == 1
+    assert len(qkc.clbits) == 1