diff --git a/examples/webserver-ch32v307-none-os/lib/HTTP/HTTPS.c b/examples/webserver-ch32v307-none-os/lib/HTTP/HTTPS.c index 7532485..e2f5e10 100644 --- a/examples/webserver-ch32v307-none-os/lib/HTTP/HTTPS.c +++ b/examples/webserver-ch32v307-none-os/lib/HTTP/HTTPS.c @@ -2339,6 +2339,28 @@ char * DataLocate(char *buf, char *name) return p; } +/********************************************************************* + * @fn atoh + * + * @brief Converting character to hexadecimal number + * + * @param src - character + * + * @return hexadecimal number + */ +uint8_t atoh(uint8_t *src) +{ + uint8_t desc=0; + + if((*src >= '0') && (*src <= '9')) + desc = *src - 0x30; + else if((*src >= 'a') && (*src <= 'f')) + desc = *src - 0x57; + else if((*src >= 'A') && (*src <= 'F')) + desc = *src - 0x37; + + return desc; +} /********************************************************************* * @fn Refresh_Basic * @@ -2368,10 +2390,10 @@ void Refresh_Basic(u8 *buf) if(q == NULL) return; memcpy(temp, p, (q - p)); p = strtok(temp, "."); - BasicCfg.mac[0] = atoi(p); + (strlen(p) == 1) ? (BasicCfg.mac[0] = atoh(p)) : (BasicCfg.mac[0] = atoh(p) << 4 | atoh(p + 1)); for (i = 1; i < 6; i++) { p = strtok(NULL, "."); - BasicCfg.mac[i] = atoi(p); + (strlen(p) == 1) ? (BasicCfg.mac[i] = atoh(p)) : (BasicCfg.mac[i] = atoh(p) << 4 | atoh(p + 1)); } } else return; @@ -2790,11 +2812,11 @@ void Init_Para_Tab(void) Para_Basic[0].para = "__AMAC"; memset(s, 0, 30); - snprintf(s, 30, "%d.%d.%d.%d.%d.%d", Basic_CfgBuf.mac[0], Basic_CfgBuf.mac[1], + snprintf(s, 30, "%x.%x.%x.%x.%x.%x", Basic_CfgBuf.mac[0], Basic_CfgBuf.mac[1], Basic_CfgBuf.mac[2], Basic_CfgBuf.mac[3], Basic_CfgBuf.mac[4], Basic_CfgBuf.mac[5]); strcpy(Para_Basic[0].value, s); - printf("__ASIP = %s\n", Para_Basic[0].value); + printf("__ASMAC = %s\n", Para_Basic[0].value); Para_Basic[1].para = "__ASIP"; memset(s, 0, 30); diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_10M.c b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_10M.c index e003291..930d362 100644 --- a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_10M.c +++ b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_10M.c @@ -417,6 +417,31 @@ void ETH_SetClock(void) while(RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY)); } +/********************************************************************* + * @fn ETH_LinkUpCfg + * + * @brief When the PHY is connected, configure the relevant functions. + * + * @param regval BMSR register value + * + * @return none. + */ +void ETH_LinkUpCfg(uint16_t regval) +{ + WCHNET_PhyStatus( regval ); + ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M); + phyStatus = PHY_Linked_Status; + + /* disable Filter function */ + ETH->MACFFR |= (ETH_ReceiveAll_Enable | ETH_PromiscuousMode_Enable); + + ETH->MMCCR |= ETH_MMCCR_CR; //Counters Reset + while(ETH->MMCCR & ETH_MMCCR_CR); //Wait for counters reset to complete + PhyPolarityDetect = 1; + LinkSuccTime = LocalTime; + ETH_Start( ); +} + /********************************************************************* * @fn ETH_PHYLink * @@ -428,52 +453,63 @@ void ETH_SetClock(void) */ void ETH_PHYLink( void ) { - u32 phy_stat; - u16 phy_anlpar; + u16 phy_bsr, phy_stat, phy_anlpar, phy_bcr; + phy_bsr = ETH_ReadPHYRegister( gPHYAddress, PHY_BSR); + phy_bcr = ETH_ReadPHYRegister( gPHYAddress, PHY_BCR); phy_anlpar = ETH_ReadPHYRegister( gPHYAddress, PHY_ANLPAR); - phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_BSR); - if((phy_stat&(PHY_Linked_Status))&&(phy_anlpar == 0)){ /* restart negotiation */ - EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN; - phyLinkReset = 1; - phyLinkTime = LocalTime; - return; - } - WCHNET_PhyStatus( phy_stat ); - - if( (phy_stat&PHY_Linked_Status) && (phy_stat&PHY_AutoNego_Complete) ) + if(phy_bsr & PHY_Linked_Status) //LinkUp { - phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_STATUS ); - if( phy_stat & (1<<2) ) + if(phy_bcr & PHY_AutoNegotiation) //determine whether auto-negotiation is enable { - ETH->MACCR |= ETH_Mode_FullDuplex; - } - else - { - if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) != PHY_ANLPAR_SELECTOR_VALUE ) + if(phy_anlpar == 0) { - ETH->MACCR |= ETH_Mode_FullDuplex; + if(phy_bsr & PHY_AutoNego_Complete) + { + ETH->MACCR &= ~ETH_Mode_FullDuplex; + ETH_LinkUpCfg(phy_bsr); + } + else{ + PHY_LINK_RESET(); + } } - else - { - ETH->MACCR &= ~ETH_Mode_FullDuplex; + else { + if(phy_bsr & PHY_AutoNego_Complete) + { + phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_STATUS ); + if( phy_stat & (1<<2) ) + { + ETH->MACCR |= ETH_Mode_FullDuplex; + } + else + { + if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) != PHY_ANLPAR_SELECTOR_VALUE ) + { + ETH->MACCR |= ETH_Mode_FullDuplex; + } + else + { + ETH->MACCR &= ~ETH_Mode_FullDuplex; + } + } + ETH_LinkUpCfg(phy_bsr); + } + else{ + WCHNET_PhyStatus( phy_bsr ); + EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN; + phyLinkReset = 1; + phyLinkTime = LocalTime; + } } } - ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M); - phyStatus = PHY_Linked_Status; - - /* disable Filter function */ - ETH->MACFFR |= (ETH_ReceiveAll_Enable | ETH_PromiscuousMode_Enable); - - ETH->MMCCR |= ETH_MMCCR_CR; //Counters Reset - while(ETH->MMCCR & ETH_MMCCR_CR); //Wait for counters reset to complete - PhyPolarityDetect = 1; - LinkSuccTime = LocalTime; - ETH_Start( ); + else { + ETH->MACCR &= ~ETH_Mode_FullDuplex; + ETH_LinkUpCfg(phy_bsr); + } } - else - { + else { //LinkDown + WCHNET_PhyStatus( phy_bsr ); EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN; phyLinkReset = 1; phyLinkTime = LocalTime; @@ -517,17 +553,17 @@ void ReInitMACReg(void) /*------------------------ MAC -----------------------------------*/ ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; ETH_InitStructure.ETH_Speed = ETH_Speed_10M; - #if HARDWARE_CHECKSUM_CONFIG +#if HARDWARE_CHECKSUM_CONFIG ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; - #endif +#endif ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; /* Filter function configuration */ ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable; - ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable; ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable; ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; /*------------------------ DMA -----------------------------------*/ @@ -535,11 +571,9 @@ void ReInitMACReg(void) the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; /* Configure Ethernet */ /*---------------------- Physical layer configuration -------------------*/ /* Set the SMI interface clock, set as the main frequency divided by 42 */ @@ -551,33 +585,24 @@ void ReInitMACReg(void) /*------------------------ MAC register configuration ----------------------- --------------------*/ tmpreg = ETH->MACCR; tmpreg &= MACCR_CLEAR_MASK; - tmpreg |= (uint32_t)(ETH_InitStructure.ETH_AutoNegotiation | - ETH_InitStructure.ETH_Watchdog | - ETH_InitStructure.ETH_Jabber | - ETH_InitStructure.ETH_InterFrameGap | - ETH_InitStructure.ETH_CarrierSense | - ETH_InitStructure.ETH_Speed | - ETH_InitStructure.ETH_ReceiveOwn | - ETH_InitStructure.ETH_LoopbackMode | - ETH_InitStructure.ETH_Mode | - ETH_InitStructure.ETH_ChecksumOffload | - ETH_InitStructure.ETH_RetryTransmission | - ETH_InitStructure.ETH_AutomaticPadCRCStrip | - ETH_InitStructure.ETH_BackOffLimit | - ETH_InitStructure.ETH_DeferralCheck); + tmpreg |= (uint32_t)(ETH_InitStructure.ETH_Watchdog | + ETH_InitStructure.ETH_Jabber | + ETH_InitStructure.ETH_InterFrameGap | + ETH_InitStructure.ETH_ChecksumOffload | + ETH_InitStructure.ETH_AutomaticPadCRCStrip | + ETH_InitStructure.ETH_DeferralCheck | + (1 << 20)); /* Write MAC Control Register */ ETH->MACCR = (uint32_t)tmpreg; - #if( PHY_MODE == USE_10M_BASE ) ETH->MACCR |= ETH_Internal_Pull_Up_Res_Enable; /*Turn on the internal pull-up resistor*/ - #endif ETH->MACFFR = (uint32_t)(ETH_InitStructure.ETH_ReceiveAll | - ETH_InitStructure.ETH_SourceAddrFilter | - ETH_InitStructure.ETH_PassControlFrames | - ETH_InitStructure.ETH_BroadcastFramesReception | - ETH_InitStructure.ETH_DestinationAddrFilter | - ETH_InitStructure.ETH_PromiscuousMode | - ETH_InitStructure.ETH_MulticastFramesFilter | - ETH_InitStructure.ETH_UnicastFramesFilter); + ETH_InitStructure.ETH_SourceAddrFilter | + ETH_InitStructure.ETH_PassControlFrames | + ETH_InitStructure.ETH_BroadcastFramesReception | + ETH_InitStructure.ETH_DestinationAddrFilter | + ETH_InitStructure.ETH_PromiscuousMode | + ETH_InitStructure.ETH_MulticastFramesFilter | + ETH_InitStructure.ETH_UnicastFramesFilter); /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ /* Write to ETHERNET MACHTHR */ ETH->MACHTHR = (uint32_t)ETH_InitStructure.ETH_HashTableHigh; @@ -589,29 +614,24 @@ void ReInitMACReg(void) /* Clear xx bits */ tmpreg &= MACFCR_CLEAR_MASK; tmpreg |= (uint32_t)((ETH_InitStructure.ETH_PauseTime << 16) | - ETH_InitStructure.ETH_ZeroQuantaPause | - ETH_InitStructure.ETH_PauseLowThreshold | - ETH_InitStructure.ETH_UnicastPauseFrameDetect | - ETH_InitStructure.ETH_ReceiveFlowControl | - ETH_InitStructure.ETH_TransmitFlowControl); + ETH_InitStructure.ETH_UnicastPauseFrameDetect | + ETH_InitStructure.ETH_ReceiveFlowControl | + ETH_InitStructure.ETH_TransmitFlowControl); ETH->MACFCR = (uint32_t)tmpreg; ETH->MACVLANTR = (uint32_t)(ETH_InitStructure.ETH_VLANTagComparison | - ETH_InitStructure.ETH_VLANTagIdentifier); + ETH_InitStructure.ETH_VLANTagIdentifier); tmpreg = ETH->DMAOMR; tmpreg &= DMAOMR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStructure.ETH_ReceiveStoreForward | - ETH_InitStructure.ETH_FlushReceivedFrame | - ETH_InitStructure.ETH_TransmitStoreForward | - ETH_InitStructure.ETH_TransmitThresholdControl | - ETH_InitStructure.ETH_ForwardErrorFrames | - ETH_InitStructure.ETH_ForwardUndersizedGoodFrames | - ETH_InitStructure.ETH_ReceiveThresholdControl | - ETH_InitStructure.ETH_SecondFrameOperate); + ETH_InitStructure.ETH_FlushReceivedFrame | + ETH_InitStructure.ETH_TransmitStoreForward | + ETH_InitStructure.ETH_ForwardErrorFrames | + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames); ETH->DMAOMR = (uint32_t)tmpreg; + /* Configure MAC address */ ETH->MACA0HR = (uint32_t)((MACAddr[5]<<8) | MACAddr[4]); ETH->MACA0LR = (uint32_t)(MACAddr[0] | (MACAddr[1]<<8) | (MACAddr[2]<<16) | (MACAddr[3]<<24)); @@ -680,20 +700,13 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /*------------------------ MAC register configuration ----------------------- --------------------*/ tmpreg = ETH->MACCR; tmpreg &= MACCR_CLEAR_MASK; - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_AutoNegotiation | - ETH_InitStruct->ETH_Watchdog | + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | ETH_InitStruct->ETH_Jabber | ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); + ETH_InitStruct->ETH_DeferralCheck | + (1 << 20)); /* Write MAC Control Register */ ETH->MACCR = (uint32_t)tmpreg; ETH->MACCR |= ETH_Internal_Pull_Up_Res_Enable; /*Turn on the internal pull-up resistor*/ @@ -716,8 +729,6 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /* Clear xx bits */ tmpreg &= MACFCR_CLEAR_MASK; tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | ETH_InitStruct->ETH_UnicastPauseFrameDetect | ETH_InitStruct->ETH_ReceiveFlowControl | ETH_InitStruct->ETH_TransmitFlowControl); @@ -729,14 +740,10 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) tmpreg = ETH->DMAOMR; tmpreg &= DMAOMR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | ETH_InitStruct->ETH_FlushReceivedFrame | ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames); ETH->DMAOMR = (uint32_t)tmpreg; /* Reset the physical layer */ @@ -805,11 +812,9 @@ void ETH_Configuration( uint8_t *macAddr ) the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; /* Configure Ethernet */ ETH_RegInit( Ð_InitStructure, gPHYAddress ); diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver.c.txt b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_CH32V317.c similarity index 51% rename from examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver.c.txt rename to examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_CH32V317.c index ca076e9..c322a73 100644 --- a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver.c.txt +++ b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_CH32V317.c @@ -11,14 +11,13 @@ *******************************************************************************/ #include "string.h" -#include "debug.h" #include "eth_driver.h" - __attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/ - __attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */ +__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/ +__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */ - __attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */ - __attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */ +__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */ +__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */ __attribute__((__aligned__(4))) SOCK_INF SocketInf[WCHNET_MAX_SOCKET_NUM]; /* Socket information table, 4-byte alignment */ const uint16_t MemNum[8] = {WCHNET_NUM_IPRAW, @@ -39,35 +38,21 @@ const uint16_t MemSize[8] = {WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB), WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF), WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF) }; - __attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE]; - __attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE]; - __attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE]; +__attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE]; +__attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE]; +__attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE]; uint16_t gPHYAddress; uint32_t volatile LocalTime; -uint8_t volatile ChipVerNum; ETH_DMADESCTypeDef *pDMARxSet; ETH_DMADESCTypeDef *pDMATxSet; - -#if( PHY_MODE == USE_10M_BASE ) -uint32_t phyLinkTime; -uint8_t phyLinkStatus = 0; -uint8_t phyStatus = 0; -uint8_t phyRetryCnt = 0; -uint8_t phyLinkCnt = 0; -uint8_t phySucCnt = 0; -uint8_t phyPN = PHY_PN_SWITCH_AUTO; -#endif - -#if( PHY_MODE == USE_MAC_MII ) u16 LastPhyStat = 0; u32 LastQueryPhyTime = 0; -#endif /********************************************************************* * @fn WCHNET_GetMacAddr * - * @brief Get MAC address + * @brief Get the MAC address * * @return none. */ @@ -103,7 +88,7 @@ void WCHNET_TimeIsr( uint16_t timperiod ) * * @return none. */ -#if( PHY_MODE == USE_MAC_MII ) + void WCHNET_QueryPhySta(void) { u16 phy_stat; @@ -115,299 +100,95 @@ void WCHNET_QueryPhySta(void) } } } -#endif -#if( PHY_MODE == USE_10M_BASE ) /********************************************************************* - * @fn WCHNET_LinkProcess + * @fn WCHNET_MainTask * - * @brief link process. + * @brief library main task function * * @param none. * * @return none. */ -void WCHNET_LinkProcess( void ) +void WCHNET_MainTask(void) { - uint16_t phy_anlpar, phy_bmsr, RegVal; - phy_anlpar = ETH_ReadPHYRegister(gPHYAddress, PHY_ANLPAR); - phy_bmsr = ETH_ReadPHYRegister( gPHYAddress, PHY_BMSR); - - if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) ) - { - if( !(phyLinkStatus&PHY_LINK_WAIT_SUC) ) - { - if( phyPN == PHY_PN_SWITCH_AUTO ) - { - PHY_PN_SWITCH(PHY_PN_SWITCH_P); - } - else if( phyPN == PHY_PN_SWITCH_P ) - { - phyLinkStatus = PHY_LINK_WAIT_SUC; - } - else - { - phyLinkStatus = PHY_LINK_WAIT_SUC; - } - } - else{ - if((phySucCnt++ == 5) && ((phy_bmsr&(1<<5)) == 0)) - { - phySucCnt = 0; - RegVal = ETH_ReadPHYRegister(gPHYAddress, PHY_BCR); - RegVal |= 1<<9; - ETH_WritePHYRegister( gPHYAddress, PHY_BCR, RegVal); - phyPN ^= PHY_PN_SWITCH_N; - ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, phyPN); - } - } - phyLinkCnt = 0; - phyRetryCnt = 0; - } - else - { - if( phyLinkStatus == PHY_LINK_WAIT_SUC ) - { - phyRetryCnt = 0; - if(phyLinkCnt++ == 15 ) - { - phyLinkCnt = 0; - phySucCnt = 0; - phyLinkStatus = PHY_LINK_INIT; - PHY_PN_SWITCH(PHY_PN_SWITCH_AUTO); - } - } - else - { - if( phyPN == PHY_PN_SWITCH_P ) - { - PHY_PN_SWITCH(PHY_PN_SWITCH_N); - } - else if( phyPN == PHY_PN_SWITCH_N ) - { - phyRetryCnt = 0; - if(phyLinkCnt++ == 15 ) - { - phyLinkCnt = 0; - phySucCnt = 0; - phyLinkStatus = PHY_LINK_INIT; - PHY_PN_SWITCH(PHY_PN_SWITCH_AUTO); - } - } - else{ - PHY_RESTART_NEGOTIATION( ); - } - } - } + WCHNET_NetInput( ); /* Ethernet data input */ + WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */ + WCHNET_QueryPhySta(); /* Query external PHY status */ } /********************************************************************* - * @fn WCHNET_HandlePhyNegotiation + * @fn ETH_SetClock * - * @brief Handle PHY Negotiation. + * @brief Set the Ethernet related clock * * @param none. * * @return none. */ -void WCHNET_HandlePhyNegotiation(void) +void ETH_SetClock(void) { - if( !phyStatus ) /* Handling PHY Negotiation Exceptions */ - { - if( LocalTime - phyLinkTime >= PHY_LINK_TASK_PERIOD ) /* 50ms cycle timing call */ - { - phyLinkTime = LocalTime; - WCHNET_LinkProcess( ); - } - } + /* Only support HSE_VALUE: 8MHz. + * If you select other HSE value,you should + * change the configuration below*/ + RCC_PLL3Cmd(DISABLE); + RCC_PREDIV2Config(RCC_PREDIV2_Div1); // HSE = 8M + RCC_PLL3Config(RCC_PLL3Mul_12_5); // 8M*12.5 = 100MHz + RCC_MCOConfig(RCC_MCO_PLL3CLK); + RCC_PLL3Cmd(ENABLE); + while(RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY)); } -#endif + /********************************************************************* - * @fn WCHNET_MainTask + * @fn ETH_RMIIPinInit * - * @brief library main task function + * @brief PHY RMII interface GPIO initialization. + * + * @param none. * * @return none. */ -void WCHNET_MainTask(void) +void ETH_RMIIPinInit(void) { - WCHNET_NetInput( ); /* Ethernet data input */ - WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */ - -#if( PHY_MODE == USE_10M_BASE ) - WCHNET_HandlePhyNegotiation(); -#endif + GPIO_InitTypeDef GPIO_InitStructure; -#if( PHY_MODE == USE_MAC_MII ) - WCHNET_QueryPhySta(); /* Query external PHY status*/ -#endif -} + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD|RCC_APB2Periph_GPIOE|RCC_APB2Periph_AFIO, ENABLE); + GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII); + GPIO_Output(GPIOD, GPIO_Pin_8); /* MDIO */ + GPIO_Output(GPIOE, GPIO_Pin_15); /* MDC */ -#if( PHY_MODE == USE_10M_BASE ) -/********************************************************************* - * @fn ETH_LedLinkSet - * - * @brief set eth link led,setbit 0 or 1,the link led turn on or turn off - * - * @return none - */ -void ETH_LedLinkSet( uint8_t mode ) -{ - if( mode == LED_OFF ) - { - GPIO_SetBits(GPIOC, GPIO_Pin_0); - } - else - { - GPIO_ResetBits(GPIOC, GPIO_Pin_0); - } -} - -/********************************************************************* - * @fn ETH_LedDataSet - * - * @brief set eth data led,setbit 0 or 1,the data led turn on or turn off - * - * @return none - */ -void ETH_LedDataSet( uint8_t mode ) -{ - if( mode == LED_OFF ) - { - GPIO_SetBits(GPIOC, GPIO_Pin_1); - } - else - { - GPIO_ResetBits(GPIOC, GPIO_Pin_1); - } -} + GPIO_Output(GPIOE, GPIO_Pin_8); /* TXEN */ + GPIO_Output(GPIOE, GPIO_Pin_11); /* TXD0 */ + GPIO_Output(GPIOE, GPIO_Pin_10); /* TXD1 */ -/********************************************************************* - * @fn ETH_LedConfiguration - * - * @brief set eth data and link led pin - * - * @return none - */ -void ETH_LedConfiguration(void) -{ - GPIO_InitTypeDef GPIO={0}; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC,ENABLE); - GPIO.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; - GPIO.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOC,&GPIO); - ETH_LedDataSet(LED_OFF); - ETH_LedLinkSet(LED_OFF); + GPIO_Output(GPIOE, GPIO_Pin_12); /* REFCLK */ + GPIO_Input(GPIOE, GPIO_Pin_9); /* CRSDV */ + GPIO_Input(GPIOE, GPIO_Pin_14); /* RXD0 */ + GPIO_Input(GPIOE, GPIO_Pin_13); /* RXD1 */ } /********************************************************************* - * @fn ETH_SetClock + * @fn ETH_PHYLink * - * @brief Set ETH Clock(60MHZ). - * - * @return none - */ -void ETH_SetClock(void) -{ - RCC_PLL3Cmd(DISABLE); - RCC_PREDIV2Config(RCC_PREDIV2_Div2); /* HSE = 8M */ - RCC_PLL3Config(RCC_PLL3Mul_15); /* 4M*15 = 60MHz */ - RCC_PLL3Cmd(ENABLE); - while(RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY)); -} -#elif( PHY_MODE == USE_MAC_MII ) -/********************************************************************* - * @fn ETH_MIIPinInit + * @brief Configure MAC parameters after the PHY Link is successful. * - * @brief PHY MII interface GPIO initialization. + * @param none. * - * @return none + * @return none. */ -void ETH_MIIPinInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC, ENABLE); - - define_O(GPIOA,GPIO_Pin_2); /* MDIO */ - define_O(GPIOC,GPIO_Pin_1); /* MDC */ - - define_I(GPIOC,GPIO_Pin_3); /* txclk */ - define_O(GPIOB,GPIO_Pin_11); /* txen */ - define_O(GPIOB,GPIO_Pin_12); /* txd0 */ - define_O(GPIOB,GPIO_Pin_13); /* txd1 */ - define_O(GPIOC,GPIO_Pin_2); /* txd2 */ - define_O(GPIOB,GPIO_Pin_8); /* txd3 */ - /* RX */ - define_I(GPIOA,GPIO_Pin_1); /* PA1 RXC */ - define_I(GPIOA,GPIO_Pin_7); /* PA7 RXDV */ - define_I(GPIOC,GPIO_Pin_4); /* RXD0 */ - define_I(GPIOC,GPIO_Pin_5); /* RXD1 */ - define_I(GPIOB,GPIO_Pin_0); /* RXD2 */ - define_I(GPIOB,GPIO_Pin_1); /* RXD3 */ - define_I(GPIOB,GPIO_Pin_10); /* RXER */ - - define_O(GPIOA,GPIO_Pin_0); /* PA0 */ - define_O(GPIOA,GPIO_Pin_3); /* PA3 */ -} -#endif - void ETH_PHYLink( void ) { u32 phy_stat; -#if( PHY_MODE == USE_10M_BASE ) - u16 phy_anlpar; - phy_anlpar = ETH_ReadPHYRegister( gPHYAddress, PHY_ANLPAR); - phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_BSR); - - if((phy_stat&(PHY_Linked_Status))&&(phy_anlpar == 0)){ /* restart negotiation */ - ETH_WritePHYRegister(gPHYAddress, PHY_BCR, PHY_Reset); - EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN; - Delay_Ms(500); - EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN; - PHY_NEGOTIATION_PARAM_INIT( ); - return; - } - WCHNET_PhyStatus( phy_stat ); - - if( (phy_stat&(PHY_Linked_Status)) && (phy_stat&PHY_AutoNego_Complete) ) - { - phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_STATUS ); - if( phy_stat & (1<<2) ) - { - ETH->MACCR |= ETH_Mode_FullDuplex; - } - else - { - if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) != PHY_ANLPAR_SELECTOR_VALUE ) - { - ETH->MACCR |= ETH_Mode_FullDuplex; - } - else - { - ETH->MACCR &= ~ETH_Mode_FullDuplex; - } - } - ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M); - phyStatus = PHY_Linked_Status; - ETH_Start( ); - } - else - { - PHY_NEGOTIATION_PARAM_INIT( ); - } -#else + ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x00 ); phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR ); LastPhyStat = phy_stat; WCHNET_PhyStatus( phy_stat ); - if( (phy_stat&PHY_Linked_Status) && (phy_stat&PHY_AutoNego_Complete) ) + if( (phy_stat & PHY_Linked_Status) && (phy_stat & PHY_AutoNego_Complete) ) { phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR ); /* PHY negotiation result */ - if(phy_stat&(1<<13)) /* 100M */ + if(phy_stat & (1<<13)) /* 100M */ { ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M); ETH->MACCR |= ETH_Speed_100M; @@ -416,7 +197,7 @@ void ETH_PHYLink( void ) { ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M); } - if(phy_stat&(1<<8)) /* full duplex */ + if(phy_stat & (1<<8)) /* full duplex */ { ETH->MACCR |= ETH_Mode_FullDuplex; } @@ -426,7 +207,7 @@ void ETH_PHYLink( void ) } ETH_Start( ); } -#endif + phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1E); /* Clear the Interrupt status */ } /********************************************************************* @@ -453,25 +234,15 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /*------------------------ MAC register configuration ----------------------- --------------------*/ tmpreg = ETH->MACCR; tmpreg &= MACCR_CLEAR_MASK; - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_AutoNegotiation | - ETH_InitStruct->ETH_Watchdog | + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | ETH_InitStruct->ETH_Jabber | ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); + ETH_InitStruct->ETH_DeferralCheck | + (1 << 20)); /* Write MAC Control Register */ ETH->MACCR = (uint32_t)tmpreg; -#if( PHY_MODE == USE_10M_BASE ) - ETH->MACCR |= ETH_Internal_Pull_Up_Res_Enable;/* */ -#endif ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | ETH_InitStruct->ETH_SourceAddrFilter | ETH_InitStruct->ETH_PassControlFrames | @@ -491,8 +262,6 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /* Clear xx bits */ tmpreg &= MACFCR_CLEAR_MASK; tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | ETH_InitStruct->ETH_UnicastPauseFrameDetect | ETH_InitStruct->ETH_ReceiveFlowControl | ETH_InitStruct->ETH_TransmitFlowControl); @@ -504,19 +273,14 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) tmpreg = ETH->DMAOMR; tmpreg &= DMAOMR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | ETH_InitStruct->ETH_FlushReceivedFrame | ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames); ETH->DMAOMR = (uint32_t)tmpreg; /* Reset the physical layer */ ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset); - ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, PHY_PN_SWITCH_AUTO); return ETH_SUCCESS; } @@ -531,19 +295,21 @@ void ETH_Configuration( uint8_t *macAddr ) { ETH_InitTypeDef ETH_InitStructure; uint16_t timeout = 10000; + uint16_t regval; /* Enable Ethernet MAC clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC|RCC_AHBPeriph_ETH_MAC_Tx|RCC_AHBPeriph_ETH_MAC_Rx,ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | \ + RCC_AHBPeriph_ETH_MAC_Tx | \ + RCC_AHBPeriph_ETH_MAC_Rx, ENABLE); gPHYAddress = PHY_ADDRESS; -#if( PHY_MODE == USE_10M_BASE ) - ETH_SetClock( ); - /* Enable internal 10BASE-T PHY*/ - EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN; /* Enable 10M Ethernet physical layer */ -#elif( PHY_MODE == USE_MAC_MII) - /* Enable MII GPIO */ - ETH_MIIPinInit( ); -#endif + + /* Enable RMII GPIO */ + ETH_RMIIPinInit(); + + /* Set the Ethernet related clock */ + ETH_SetClock(); + /* Reset ETHERNET on AHB Bus */ ETH_DeInit(); @@ -556,25 +322,24 @@ void ETH_Configuration( uint8_t *macAddr ) if( !--timeout ) break; }while(ETH->DMABMR & ETH_DMABMR_SR); - ChipVerNum = GET_CHIP_VER(); /* ETHERNET Configuration */ /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ ETH_StructInit(Ð_InitStructure); /* Fill ETH_InitStructure parameters */ /*------------------------ MAC -----------------------------------*/ ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; -#if( PHY_MODE == USE_10M_BASE ) - ETH_InitStructure.ETH_Speed = ETH_Speed_10M; -#else ETH_InitStructure.ETH_Speed = ETH_Speed_100M; +#if HARDWARE_CHECKSUM_CONFIG + ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; #endif - ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ; + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; - ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + /* Filter function configuration */ + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable; - ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Enable; ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; /*------------------------ DMA -----------------------------------*/ @@ -582,32 +347,54 @@ void ETH_Configuration( uint8_t *macAddr ) the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; /* Configure Ethernet */ ETH_RegInit( Ð_InitStructure, gPHYAddress ); -#if( PHY_MODE == USE_10M_BASE ) - /* Enable the Ethernet Rx Interrupt */ - ETH_DMAITConfig( ETH_DMA_IT_NIS |\ - ETH_DMA_IT_R |\ - ETH_DMA_IT_T |\ - ETH_DMA_IT_PHYLINK,\ - ENABLE ); -#else - /* Enable the Ethernet Rx Interrupt */ - ETH_DMAITConfig( ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE ); -#endif + + /* Configure MAC address */ + ETH->MACA0HR = (uint32_t)((macAddr[5]<<8) | macAddr[4]); + ETH->MACA0LR = (uint32_t)(macAddr[0] | (macAddr[1]<<8) | (macAddr[2]<<16) | (macAddr[3]<<24)); + + /* Mask the interrupt that Tx good frame count counter reaches half the maximum value */ + ETH->MMCTIMR = ETH_MMCTIMR_TGFM; + /* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */ + /* Mask the interrupt that Rx crc error counter reaches half the maximum value */ + ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM; + + ETH_DMAITConfig(ETH_DMA_IT_NIS |\ + ETH_DMA_IT_R |\ + ETH_DMA_IT_T |\ + ETH_DMA_IT_AIS |\ + ETH_DMA_IT_RBU,\ + ENABLE); + + ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x00 ); + /* Configure Repeater mode */ + regval = ETH_ReadPHYRegister(gPHYAddress, 28); + regval |= 1<<13; + ETH_WritePHYRegister(gPHYAddress, 28, regval ); + + /*rmii rx clock change */ + ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x07 ); + regval = ETH_ReadPHYRegister( gPHYAddress, 16); + regval &= ~(0x0f<<4); + regval |= 0x04<<4; + ETH_WritePHYRegister(gPHYAddress, 16, regval ); + + + /*Reads the default value of the PHY_BSR register*/ + LastPhyStat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR ); } /********************************************************************* * @fn ETH_TxPktChainMode * - * @brief process net send a Ethernet frame in chain mode. + * @brief Ethernet sends data frames in chain mode. * - * @param Send length + * @param len Send data length + * pBuff send buffer pointer * * @return Send status. */ @@ -622,21 +409,22 @@ uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff ) /* Setting the Frame Length: bits[12:0] */ DMATxDescToSet->ControlBufferSize = (len & ETH_DMATxDesc_TBS1); DMATxDescToSet->Buffer1Addr = (uint32_t)pBuff; - pDMATxSet = DMATxDescToSet; + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ +#if HARDWARE_CHECKSUM_CONFIG + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_CIC_TCPUDPICMP_Full; +#else DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; +#endif /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if ((ETH->DMASR & ETH_DMASR_TBUS) != (u32)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - ETH->DMATPDR = 0; - } + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + /* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */ /* Chained Mode */ /* Selects the next DMA Tx descriptor list for next buffer to send */ @@ -648,7 +436,7 @@ uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff ) /********************************************************************* * @fn WCHNET_ETHIsr * - * @brief Ethernet Interrupt Service program + * @brief Ethernet Interrupt Service Routine * * @return none */ @@ -657,49 +445,26 @@ void WCHNET_ETHIsr(void) uint32_t int_sta; int_sta = ETH->DMASR; + if (int_sta & ETH_DMA_IT_AIS) + { + if (int_sta & ETH_DMA_IT_RBU) + { + ETH_DMAClearITPendingBit(ETH_DMA_IT_RBU); + } + ETH_DMAClearITPendingBit(ETH_DMA_IT_AIS); + } + if( int_sta & ETH_DMA_IT_NIS ) { if( int_sta & ETH_DMA_IT_R ) { - if( ChipVerNum < CHIP_C_VER_NUM ) - { - if ((int_sta & ETH_DMA_IT_RBU) != (u32)RESET) - { - /* Clear RBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMA_IT_RBU; - - ((ETH_DMADESCTypeDef *)(((ETH_DMADESCTypeDef *)(ETH->DMACHRDR))->Buffer2NextDescAddr))->Status = ETH_DMARxDesc_OWN; - - /* Resume DMA reception */ - ETH->DMARPDR = 0; - } - } + /*If you don't use the Ethernet library, + * you can do some data processing operations here*/ ETH_DMAClearITPendingBit(ETH_DMA_IT_R); - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET) - { - /***/ - } - else - { - /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */ - /* Chained Mode */ - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } } if( int_sta & ETH_DMA_IT_T ) { ETH_DMAClearITPendingBit(ETH_DMA_IT_T); - if( (pDMATxSet->StatusÐ_DMATxDesc_ES) ) - { - /***/ - } - } - if( int_sta & ETH_DMA_IT_PHYLINK) - { - ETH_PHYLink( ); - ETH_DMAClearITPendingBit(ETH_DMA_IT_PHYLINK); } ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS); } @@ -714,16 +479,13 @@ void WCHNET_ETHIsr(void) */ void ETH_Init( uint8_t *macAddr ) { -#if( PHY_MODE == USE_10M_BASE ) - ETH_LedConfiguration( ); -#endif - Delay_Ms(100); ETH_Configuration( macAddr ); ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB); ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB); pDMARxSet = DMARxDscrTab; pDMATxSet = DMATxDscrTab; NVIC_EnableIRQ(ETH_IRQn); + NVIC_SetPriority(ETH_IRQn, 0); } /********************************************************************* @@ -745,10 +507,6 @@ uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr cfg.ARPTableNum = WCHNET_NUM_ARP_TABLE; cfg.MiscConfig0 = WCHNET_MISC_CONFIG0; cfg.MiscConfig1 = WCHNET_MISC_CONFIG1; -#if( PHY_MODE == USE_10M_BASE ) - cfg.led_link = ETH_LedLinkSet; - cfg.led_data = ETH_LedDataSet; -#endif cfg.net_send = ETH_TxPktChainMode; cfg.CheckValid = WCHNET_CFG_VALID; s = WCHNET_ConfigLIB(&cfg); diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_MII.c.txt b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_MII.c similarity index 94% rename from examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_MII.c.txt rename to examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_MII.c index 6143d47..097a6b7 100644 --- a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_MII.c.txt +++ b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_MII.c @@ -220,20 +220,13 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /*------------------------ MAC register configuration ----------------------- --------------------*/ tmpreg = ETH->MACCR; tmpreg &= MACCR_CLEAR_MASK; - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_AutoNegotiation | - ETH_InitStruct->ETH_Watchdog | + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | ETH_InitStruct->ETH_Jabber | ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); + ETH_InitStruct->ETH_DeferralCheck | + (1 << 20)); /* Write MAC Control Register */ ETH->MACCR = (uint32_t)tmpreg; ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | @@ -255,8 +248,6 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /* Clear xx bits */ tmpreg &= MACFCR_CLEAR_MASK; tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | ETH_InitStruct->ETH_UnicastPauseFrameDetect | ETH_InitStruct->ETH_ReceiveFlowControl | ETH_InitStruct->ETH_TransmitFlowControl); @@ -268,14 +259,10 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) tmpreg = ETH->DMAOMR; tmpreg &= DMAOMR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | ETH_InitStruct->ETH_FlushReceivedFrame | ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames); ETH->DMAOMR = (uint32_t)tmpreg; /* Reset the physical layer */ @@ -342,11 +329,9 @@ void ETH_Configuration( uint8_t *macAddr ) the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; /* Configure Ethernet */ ETH_RegInit( Ð_InitStructure, gPHYAddress ); diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RGMII.c.txt b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RGMII.c similarity index 95% rename from examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RGMII.c.txt rename to examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RGMII.c index 2f79598..b029034 100644 --- a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RGMII.c.txt +++ b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RGMII.c @@ -304,20 +304,13 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /*------------------------ MAC register configuration ----------------------- --------------------*/ tmpreg = ETH->MACCR; tmpreg &= MACCR_CLEAR_MASK; - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_AutoNegotiation | - ETH_InitStruct->ETH_Watchdog | + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | ETH_InitStruct->ETH_Jabber | ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); + ETH_InitStruct->ETH_DeferralCheck | + (1 << 20)); /* Write MAC Control Register */ ETH->MACCR = (uint32_t)tmpreg; ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | @@ -339,8 +332,6 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /* Clear xx bits */ tmpreg &= MACFCR_CLEAR_MASK; tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | ETH_InitStruct->ETH_UnicastPauseFrameDetect | ETH_InitStruct->ETH_ReceiveFlowControl | ETH_InitStruct->ETH_TransmitFlowControl); @@ -352,14 +343,10 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) tmpreg = ETH->DMAOMR; tmpreg &= DMAOMR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | ETH_InitStruct->ETH_FlushReceivedFrame | ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames); ETH->DMAOMR = (uint32_t)tmpreg; /* Reset the physical layer */ @@ -430,11 +417,9 @@ void ETH_Configuration( uint8_t *macAddr ) the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; /* Configure Ethernet */ ETH_RegInit( Ð_InitStructure, gPHYAddress ); diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RMII.c.txt b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RMII.c similarity index 95% rename from examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RMII.c.txt rename to examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RMII.c index 4030859..9f0817a 100644 --- a/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RMII.c.txt +++ b/examples/webserver-ch32v307-none-os/lib/NetLib/eth_driver_RMII.c @@ -324,20 +324,13 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /*------------------------ MAC register configuration ----------------------- --------------------*/ tmpreg = ETH->MACCR; tmpreg &= MACCR_CLEAR_MASK; - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_AutoNegotiation | - ETH_InitStruct->ETH_Watchdog | + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | ETH_InitStruct->ETH_Jabber | ETH_InitStruct->ETH_InterFrameGap | - ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | - ETH_InitStruct->ETH_ReceiveOwn | - ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | - ETH_InitStruct->ETH_DeferralCheck); + ETH_InitStruct->ETH_DeferralCheck | + (1 << 20)); /* Write MAC Control Register */ ETH->MACCR = (uint32_t)tmpreg; ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | @@ -359,8 +352,6 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) /* Clear xx bits */ tmpreg &= MACFCR_CLEAR_MASK; tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | - ETH_InitStruct->ETH_ZeroQuantaPause | - ETH_InitStruct->ETH_PauseLowThreshold | ETH_InitStruct->ETH_UnicastPauseFrameDetect | ETH_InitStruct->ETH_ReceiveFlowControl | ETH_InitStruct->ETH_TransmitFlowControl); @@ -372,14 +363,10 @@ uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) tmpreg = ETH->DMAOMR; tmpreg &= DMAOMR_CLEAR_MASK; tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | - ETH_InitStruct->ETH_ReceiveStoreForward | ETH_InitStruct->ETH_FlushReceivedFrame | ETH_InitStruct->ETH_TransmitStoreForward | - ETH_InitStruct->ETH_TransmitThresholdControl | ETH_InitStruct->ETH_ForwardErrorFrames | - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames); ETH->DMAOMR = (uint32_t)tmpreg; /* Reset the physical layer */ @@ -398,6 +385,7 @@ void ETH_Configuration( uint8_t *macAddr ) { ETH_InitTypeDef ETH_InitStructure; uint16_t timeout = 10000; + uint16_t regval; /* Enable Ethernet MAC clock */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | \ @@ -446,11 +434,9 @@ void ETH_Configuration( uint8_t *macAddr ) the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; /* Configure Ethernet */ ETH_RegInit( Ð_InitStructure, gPHYAddress ); @@ -471,6 +457,19 @@ void ETH_Configuration( uint8_t *macAddr ) ETH_DMA_IT_RBU,\ ENABLE); + ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x00 ); + /* Configure Repeater mode */ + regval = ETH_ReadPHYRegister(gPHYAddress, 28); + regval |= 1<<13; + ETH_WritePHYRegister(gPHYAddress, 28, regval ); + + /*rmii rx clock change */ + ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x07 ); + regval = ETH_ReadPHYRegister( gPHYAddress, 16); + regval &= ~(0x0f<<4); + regval |= 0x04<<4; + ETH_WritePHYRegister(gPHYAddress, 16, regval ); + #if LINK_STAT_ACQUISITION_METHOD /* Configure the PHY interrupt function, the supported chip is: CH182H RMII */ PHY_InterruptInit( ); diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/library.json b/examples/webserver-ch32v307-none-os/lib/NetLib/library.json index c58aab4..13ca0b7 100644 --- a/examples/webserver-ch32v307-none-os/lib/NetLib/library.json +++ b/examples/webserver-ch32v307-none-os/lib/NetLib/library.json @@ -1,10 +1,12 @@ { "name": "W.CH NetLib", - "version": "1.60.0", + "version": "1.90.0", "build": { "flags": [ "-L.", "-lwchnet" - ] + ], + "srcDir": ".", + "srcFilter": "-<*> +" } } \ No newline at end of file diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet.a b/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet.a index 151c5eb..9eee482 100644 Binary files a/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet.a and b/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet.a differ diff --git a/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet_float.a b/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet_float.a index f567125..028ae86 100644 Binary files a/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet_float.a and b/examples/webserver-ch32v307-none-os/lib/NetLib/libwchnet_float.a differ diff --git a/examples/webserver-ch32v307-none-os/platformio.ini b/examples/webserver-ch32v307-none-os/platformio.ini index ffd4e25..8991607 100644 --- a/examples/webserver-ch32v307-none-os/platformio.ini +++ b/examples/webserver-ch32v307-none-os/platformio.ini @@ -12,7 +12,7 @@ platform = ch32v framework = noneos-sdk monitor_speed = 115200 ; make net_config.h globally discoverable -build_flags = -I src/ +build_flags = -I src/ -Wno-pointer-sign ; uncomment this to use USB bootloader upload via WCHISP ;upload_protocol = isp diff --git a/examples/webserver-ch32v307-none-os/src/net_config.h b/examples/webserver-ch32v307-none-os/src/net_config.h index 1ce9412..38c658f 100644 --- a/examples/webserver-ch32v307-none-os/src/net_config.h +++ b/examples/webserver-ch32v307-none-os/src/net_config.h @@ -26,7 +26,7 @@ extern "C" { #define WCHNET_NUM_TCP 3 /* Number of TCP connections */ -#define WCHNET_NUM_TCP_LISTEN 3 /* Number of TCP listening */ +#define WCHNET_NUM_TCP_LISTEN 2 /* Number of TCP listening */ /* The number of sockets, the maximum is 31 */ #define WCHNET_MAX_SOCKET_NUM (WCHNET_NUM_IPRAW+WCHNET_NUM_UDP+WCHNET_NUM_TCP+WCHNET_NUM_TCP_LISTEN) @@ -59,9 +59,9 @@ extern "C" { #define TCP_RETRY_PERIOD 10 /* TCP retransmission period, the default value is 10, the unit is 50ms */ -#define SOCKET_SEND_RETRY 2 /* Send failed retry configuration, 1: enable, 0: disable */ +#define SOCKET_SEND_RETRY 0 /* Send failed retry configuration, 1: enable, 0: disable */ -#define HARDWARE_CHECKSUM_CONFIG 1 /* Hardware checksum checking and insertion configuration, 1: enable, 0: disable */ +#define HARDWARE_CHECKSUM_CONFIG 0 /* Hardware checksum checking and insertion configuration, 1: enable, 0: disable */ #define FINE_DHCP_PERIOD 8 /* Fine DHCP period, the default value is 8, the unit is 250ms */ @@ -73,7 +73,7 @@ extern "C" { #define CFG0_IP_REASS_PBUFS 0 /* Number of reassembled IP PBUFs */ -#define CFG0_TCP_DEALY_ACK_DISABLE 0 /* 1: disable TCP delay ACK 0: enable TCP delay ACK */ +#define CFG0_TCP_DEALY_ACK_DISABLE 1 /* 1: disable TCP delay ACK 0: enable TCP delay ACK */ /********************************************************************* * Memory related configuration