From 1f6b12e7908c44c14d674cdaf8b45a585b8158b8 Mon Sep 17 00:00:00 2001 From: shiptux Date: Fri, 19 May 2023 17:09:57 +0800 Subject: [PATCH 1/9] i#3544 riscv64: Implemented dr_setjmp This commit introduces the following changes: - Implemented dynamorio_condvar_wake_and_jmp Issue: #3544 --- core/arch/arch_exports.h | 5 ++++- core/arch/riscv64/riscv64.asm | 41 ++++++++++++++++++++++++++++++++--- 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/core/arch/arch_exports.h b/core/arch/arch_exports.h index 6a1b844a000..f4d1299adaa 100644 --- a/core/arch/arch_exports.h +++ b/core/arch/arch_exports.h @@ -1608,7 +1608,10 @@ typedef struct dr_jmp_buf_t { #elif defined(AARCH64) /* for aarch64.asm */ # define REGS_IN_JMP_BUF 22 /* See dr_setjmp and dr_longjmp. */ reg_t regs[REGS_IN_JMP_BUF]; -#endif /* X86/AARCH64/ARM */ +#elif defined(RISCV64) /* For riscv64.asm. */ +# define REGS_IN_JMP_BUF 25 /* See dr_setjmp and dr_longjmp. */ + reg_t regs[REGS_IN_JMP_BUF]; +#endif /* X86/AARCH64/ARM/RISCV64 */ #if defined(UNIX) && defined(DEBUG) /* i#226/PR 492568: we avoid the cost of storing this by using the * mask in the fault's signal frame, but we do record it in debug diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index dab1e6b84c1..9cd3f3cca82 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -208,16 +208,51 @@ ADDRTAKEN_LABEL(safe_read_asm_recover:) */ DECLARE_EXPORTED_FUNC(dr_try_start) GLOBAL_LABEL(dr_try_start:) - addi ARG1, ARG1, TRY_CXT_SETJMP_OFFS + addi ARG1, ARG1, TRY_CXT_SETJMP_OFFS j GLOBAL_REF(dr_setjmp) END_FUNC(dr_try_start) -/* +/* We save only callee-saved regites: SP, x8/fp, x9, x18-x27, f8-9, f18-27: + * a total of 25 reg_t (64-bit) slots. See definition of dr_jmp_buf_t. + * * int dr_setjmp(dr_jmp_buf_t *buf); */ DECLARE_FUNC(dr_setjmp) GLOBAL_LABEL(dr_setjmp:) -/* FIXME i#3544: Not implemented */ + sd x18, (ARG1) + sd x19, 8 (ARG1) + sd x20, 16 (ARG1) + sd x21, 24 (ARG1) + sd x22, 32 (ARG1) + sd x23, 40 (ARG1) + sd x24, 48 (ARG1) + sd x25, 56 (ARG1) + sd x26, 64 (ARG1) + sd x27, 72 (ARG1) + mv ARG7, sp + sd ARG7, 80 (ARG1) + sd x8, 88 (ARG1) + sd x9, 96 (ARG1) + fsd f8, 104 (ARG1) + fsd f9, 112 (ARG1) + fsd f18, 120 (ARG1) + fsd f19, 128 (ARG1) + fsd f20, 136 (ARG1) + fsd f21, 144 (ARG1) + fsd f22, 152 (ARG1) + fsd f23, 160 (ARG1) + fsd f24, 168 (ARG1) + fsd f25, 176 (ARG1) + fsd f26, 184 (ARG1) + fsd f27, 192 (ARG1) +# ifdef UNIX + addi sp, sp, -16 + sd ra, 0 (sp) + jal GLOBAL_REF(dr_setjmp_sigmask) + ld ra, 0 (sp) + add sp, sp, 16 +# endif + li a0, 0 ret END_FUNC(dr_setjmp) From 7a1ccc0f2bca7bd87938fb10ad43fd3783b9a6e5 Mon Sep 17 00:00:00 2001 From: shiptux Date: Fri, 19 May 2023 19:22:00 +0800 Subject: [PATCH 2/9] Implemented dr_setjmp --- core/arch/riscv64/riscv64.asm | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index 9cd3f3cca82..1b5a28e3fc4 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -219,7 +219,7 @@ GLOBAL_LABEL(dr_try_start:) */ DECLARE_FUNC(dr_setjmp) GLOBAL_LABEL(dr_setjmp:) - sd x18, (ARG1) + sd x18, 0 (ARG1) sd x19, 8 (ARG1) sd x20, 16 (ARG1) sd x21, 24 (ARG1) @@ -261,8 +261,36 @@ GLOBAL_LABEL(dr_setjmp:) */ DECLARE_FUNC(dr_longjmp) GLOBAL_LABEL(dr_longjmp:) -/* FIXME i#3544: Not implemented */ - ret + sd x18, 0 (ARG1) + sd x19, 8 (ARG1) + sd x20, 16 (ARG1) + sd x21, 24 (ARG1) + sd x22, 32 (ARG1) + sd x23, 40 (ARG1) + sd x24, 48 (ARG1) + sd x25, 56 (ARG1) + sd x26, 64 (ARG1) + sd x27, 72 (ARG1) + mv ARG7, sp + sd ARG7, 80 (ARG1) + sd x8, 88 (ARG1) + sd x9, 96 (ARG1) + fsd f8, 104 (ARG1) + fsd f9, 112 (ARG1) + fsd f18, 120 (ARG1) + fsd f19, 128 (ARG1) + fsd f20, 136 (ARG1) + fsd f21, 144 (ARG1) + fsd f22, 152 (ARG1) + fsd f23, 160 (ARG1) + fsd f24, 168 (ARG1) + fsd f25, 176 (ARG1) + fsd f26, 184 (ARG1) + fsd f27, 192 (ARG1) + li t0, 0 + snez t0, ARG1 + add ARG1, ARG, t0 + jalr ra END_FUNC(dr_longjmp) /* int atomic_swap(int *adr, int val) */ From 3859e2075255495463f4d09652e54771306f0a75 Mon Sep 17 00:00:00 2001 From: shiptux Date: Sat, 20 May 2023 12:34:09 +0800 Subject: [PATCH 3/9] Fix review --- core/arch/riscv64/riscv64.asm | 82 +++++++++++++++++------------------ 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index 1b5a28e3fc4..73cde138e33 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -212,27 +212,27 @@ GLOBAL_LABEL(dr_try_start:) j GLOBAL_REF(dr_setjmp) END_FUNC(dr_try_start) -/* We save only callee-saved regites: SP, x8/fp, x9, x18-x27, f8-9, f18-27: +/* We save only callee-saved registers: SP, x8/fp, x9, x18-x27, f8-9, f18-27: * a total of 25 reg_t (64-bit) slots. See definition of dr_jmp_buf_t. * * int dr_setjmp(dr_jmp_buf_t *buf); */ DECLARE_FUNC(dr_setjmp) GLOBAL_LABEL(dr_setjmp:) - sd x18, 0 (ARG1) - sd x19, 8 (ARG1) - sd x20, 16 (ARG1) - sd x21, 24 (ARG1) - sd x22, 32 (ARG1) - sd x23, 40 (ARG1) - sd x24, 48 (ARG1) - sd x25, 56 (ARG1) - sd x26, 64 (ARG1) - sd x27, 72 (ARG1) - mv ARG7, sp - sd ARG7, 80 (ARG1) - sd x8, 88 (ARG1) - sd x9, 96 (ARG1) + mv t0, sp + sd t0, 0 (ARG1) + sd x8, 8 (ARG1) + sd x9, 16 (ARG1) + sd x18, 24 (ARG1) + sd x19, 32 (ARG1) + sd x20, 40 (ARG1) + sd x21, 48 (ARG1) + sd x22, 56 (ARG1) + sd x23, 64 (ARG1) + sd x24, 72 (ARG1) + sd x25, 80 (ARG1) + sd x26, 88 (ARG1) + sd x27, 96 (ARG1) fsd f8, 104 (ARG1) fsd f9, 112 (ARG1) fsd f18, 120 (ARG1) @@ -261,32 +261,32 @@ GLOBAL_LABEL(dr_setjmp:) */ DECLARE_FUNC(dr_longjmp) GLOBAL_LABEL(dr_longjmp:) - sd x18, 0 (ARG1) - sd x19, 8 (ARG1) - sd x20, 16 (ARG1) - sd x21, 24 (ARG1) - sd x22, 32 (ARG1) - sd x23, 40 (ARG1) - sd x24, 48 (ARG1) - sd x25, 56 (ARG1) - sd x26, 64 (ARG1) - sd x27, 72 (ARG1) - mv ARG7, sp - sd ARG7, 80 (ARG1) - sd x8, 88 (ARG1) - sd x9, 96 (ARG1) - fsd f8, 104 (ARG1) - fsd f9, 112 (ARG1) - fsd f18, 120 (ARG1) - fsd f19, 128 (ARG1) - fsd f20, 136 (ARG1) - fsd f21, 144 (ARG1) - fsd f22, 152 (ARG1) - fsd f23, 160 (ARG1) - fsd f24, 168 (ARG1) - fsd f25, 176 (ARG1) - fsd f26, 184 (ARG1) - fsd f27, 192 (ARG1) + ld t0, 0 (ARG1) + mv sp, t0 + ld x8, 8 (ARG1) + ld x9, 16 (ARG1) + ld x18, 24 (ARG1) + ld x19, 32 (ARG1) + ld x20, 40 (ARG1) + ld x21, 48 (ARG1) + ld x22, 56 (ARG1) + ld x23, 64 (ARG1) + ld x24, 72 (ARG1) + ld x25, 80 (ARG1) + ld x26, 88 (ARG1) + ld x27, 96 (ARG1) + fld f8, 104 (ARG1) + fld f9, 112 (ARG1) + fld f18, 120 (ARG1) + fld f19, 128 (ARG1) + fld f20, 136 (ARG1) + fld f21, 144 (ARG1) + fld f22, 152 (ARG1) + fld f23, 160 (ARG1) + fld f24, 168 (ARG1) + fld f25, 176 (ARG1) + fld f26, 184 (ARG1) + fld f27, 192 (ARG1) li t0, 0 snez t0, ARG1 add ARG1, ARG, t0 From 702e762ca03ec7f068426e9a508d52f60001d683 Mon Sep 17 00:00:00 2001 From: shiptux Date: Sat, 20 May 2023 13:11:25 +0800 Subject: [PATCH 4/9] Fix review --- core/arch/riscv64/riscv64.asm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index 73cde138e33..88992b8b4c8 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -289,7 +289,7 @@ GLOBAL_LABEL(dr_longjmp:) fld f27, 192 (ARG1) li t0, 0 snez t0, ARG1 - add ARG1, ARG, t0 + add ARG1, ARG1, t0 jalr ra END_FUNC(dr_longjmp) From 55d5d5ee04ae070aa0ca1ece64d4514871a95d29 Mon Sep 17 00:00:00 2001 From: shiptux Date: Sat, 20 May 2023 13:34:52 +0800 Subject: [PATCH 5/9] fixed review2 --- core/arch/riscv64/riscv64.asm | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index 88992b8b4c8..c8b0b73fb67 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -287,10 +287,9 @@ GLOBAL_LABEL(dr_longjmp:) fld f25, 176 (ARG1) fld f26, 184 (ARG1) fld f27, 192 (ARG1) - li t0, 0 - snez t0, ARG1 - add ARG1, ARG1, t0 - jalr ra + beqz ARG1, 1b + addi ARG1, ARG1, 1 +1: jalr ra END_FUNC(dr_longjmp) /* int atomic_swap(int *adr, int val) */ From 7757a583f55e3cedff8a5488b259a042acbe0309 Mon Sep 17 00:00:00 2001 From: shiptux Date: Sat, 20 May 2023 13:51:03 +0800 Subject: [PATCH 6/9] fixed review3 --- core/arch/riscv64/riscv64.asm | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index c8b0b73fb67..15523ce5ab9 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -287,9 +287,10 @@ GLOBAL_LABEL(dr_longjmp:) fld f25, 176 (ARG1) fld f26, 184 (ARG1) fld f27, 192 (ARG1) - beqz ARG1, 1b + beqz ARG1, skip addi ARG1, ARG1, 1 -1: jalr ra +skip: + jalr ra END_FUNC(dr_longjmp) /* int atomic_swap(int *adr, int val) */ From 7afbe5bbd7a28dc0a6e224093ef7113c959a896a Mon Sep 17 00:00:00 2001 From: shiptux Date: Sun, 21 May 2023 12:44:57 +0800 Subject: [PATCH 7/9] fixed review --- core/arch/riscv64/riscv64.asm | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index 15523ce5ab9..e4cff529d4a 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -287,9 +287,8 @@ GLOBAL_LABEL(dr_longjmp:) fld f25, 176 (ARG1) fld f26, 184 (ARG1) fld f27, 192 (ARG1) - beqz ARG1, skip - addi ARG1, ARG1, 1 -skip: + seqz ARG1, ARG2 + add ARG1, ARG1, ARG2 jalr ra END_FUNC(dr_longjmp) From 6779b4195a5960141158905e3623fd9b9d7868fe Mon Sep 17 00:00:00 2001 From: shiptux Date: Sun, 21 May 2023 13:23:45 +0800 Subject: [PATCH 8/9] fixed review2 --- core/arch/arch_exports.h | 2 +- core/arch/riscv64/riscv64.asm | 110 +++++++++++++++++----------------- 2 files changed, 57 insertions(+), 55 deletions(-) diff --git a/core/arch/arch_exports.h b/core/arch/arch_exports.h index f4d1299adaa..6d11d87b3f0 100644 --- a/core/arch/arch_exports.h +++ b/core/arch/arch_exports.h @@ -1609,7 +1609,7 @@ typedef struct dr_jmp_buf_t { # define REGS_IN_JMP_BUF 22 /* See dr_setjmp and dr_longjmp. */ reg_t regs[REGS_IN_JMP_BUF]; #elif defined(RISCV64) /* For riscv64.asm. */ -# define REGS_IN_JMP_BUF 25 /* See dr_setjmp and dr_longjmp. */ +# define REGS_IN_JMP_BUF 26 /* See dr_setjmp and dr_longjmp. */ reg_t regs[REGS_IN_JMP_BUF]; #endif /* X86/AARCH64/ARM/RISCV64 */ #if defined(UNIX) && defined(DEBUG) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index e4cff529d4a..33e3dc44896 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -212,39 +212,40 @@ GLOBAL_LABEL(dr_try_start:) j GLOBAL_REF(dr_setjmp) END_FUNC(dr_try_start) -/* We save only callee-saved registers: SP, x8/fp, x9, x18-x27, f8-9, f18-27: - * a total of 25 reg_t (64-bit) slots. See definition of dr_jmp_buf_t. +/* We save only callee-saved registers and ra: ra, SP, x8/fp, x9, x18-x27, f8-9, f18-27: + * a total of 26 reg_t (64-bit) slots. See definition of dr_jmp_buf_t. * * int dr_setjmp(dr_jmp_buf_t *buf); */ DECLARE_FUNC(dr_setjmp) GLOBAL_LABEL(dr_setjmp:) + sd ra, 0 (ARG1) + sd t0, ARG_SZ (ARG1) mv t0, sp - sd t0, 0 (ARG1) - sd x8, 8 (ARG1) - sd x9, 16 (ARG1) - sd x18, 24 (ARG1) - sd x19, 32 (ARG1) - sd x20, 40 (ARG1) - sd x21, 48 (ARG1) - sd x22, 56 (ARG1) - sd x23, 64 (ARG1) - sd x24, 72 (ARG1) - sd x25, 80 (ARG1) - sd x26, 88 (ARG1) - sd x27, 96 (ARG1) - fsd f8, 104 (ARG1) - fsd f9, 112 (ARG1) - fsd f18, 120 (ARG1) - fsd f19, 128 (ARG1) - fsd f20, 136 (ARG1) - fsd f21, 144 (ARG1) - fsd f22, 152 (ARG1) - fsd f23, 160 (ARG1) - fsd f24, 168 (ARG1) - fsd f25, 176 (ARG1) - fsd f26, 184 (ARG1) - fsd f27, 192 (ARG1) + sd s0, 2*ARG_SZ (ARG1) + sd s1, 3*ARG_SZ (ARG1) + sd s2, 4*ARG_SZ (ARG1) + sd s3, 5*ARG_SZ (ARG1) + sd s4, 6*ARG_SZ (ARG1) + sd s5, 7*ARG_SZ (ARG1) + sd s6, 8*ARG_SZ (ARG1) + sd s7, 9*ARG_SZ (ARG1) + sd s8, 10*ARG_SZ (ARG1) + sd s9, 11*ARG_SZ (ARG1) + sd s10, 12*ARG_SZ (ARG1) + sd s11, 13*ARG_SZ (ARG1) + fsd fs0, 14*ARG_SZ (ARG1) + fsd fs1, 15*ARG_SZ (ARG1) + fsd fs2, 16*ARG_SZ (ARG1) + fsd fs3, 17*ARG_SZ (ARG1) + fsd fs4, 18*ARG_SZ (ARG1) + fsd fs5, 19*ARG_SZ (ARG1) + fsd fs6, 20*ARG_SZ (ARG1) + fsd fs7, 21*ARG_SZ (ARG1) + fsd fs8, 22*ARG_SZ (ARG1) + fsd fs9, 23*ARG_SZ (ARG1) + fsd fs10, 24*ARG_SZ (ARG1) + fsd fs11, 25*ARG_SZ (ARG1) # ifdef UNIX addi sp, sp, -16 sd ra, 0 (sp) @@ -261,35 +262,36 @@ GLOBAL_LABEL(dr_setjmp:) */ DECLARE_FUNC(dr_longjmp) GLOBAL_LABEL(dr_longjmp:) - ld t0, 0 (ARG1) + ld ra, 0 (ARG1) /* Restore return address from buf */ + ld t0, ARG_SZ (ARG1) mv sp, t0 - ld x8, 8 (ARG1) - ld x9, 16 (ARG1) - ld x18, 24 (ARG1) - ld x19, 32 (ARG1) - ld x20, 40 (ARG1) - ld x21, 48 (ARG1) - ld x22, 56 (ARG1) - ld x23, 64 (ARG1) - ld x24, 72 (ARG1) - ld x25, 80 (ARG1) - ld x26, 88 (ARG1) - ld x27, 96 (ARG1) - fld f8, 104 (ARG1) - fld f9, 112 (ARG1) - fld f18, 120 (ARG1) - fld f19, 128 (ARG1) - fld f20, 136 (ARG1) - fld f21, 144 (ARG1) - fld f22, 152 (ARG1) - fld f23, 160 (ARG1) - fld f24, 168 (ARG1) - fld f25, 176 (ARG1) - fld f26, 184 (ARG1) - fld f27, 192 (ARG1) + ld s0, 2*ARG_SZ (ARG1) + ld s1, 3*ARG_SZ (ARG1) + ld s2, 4*ARG_SZ (ARG1) + ld s3, 5*ARG_SZ (ARG1) + ld s4, 6*ARG_SZ (ARG1) + ld s5, 7*ARG_SZ (ARG1) + ld s6, 8*ARG_SZ (ARG1) + ld s7, 9*ARG_SZ (ARG1) + ld s8, 10*ARG_SZ (ARG1) + ld s9, 11*ARG_SZ (ARG1) + ld s10, 12*ARG_SZ (ARG1) + ld s11, 13*ARG_SZ (ARG1) + fld fs0, 14*ARG_SZ (ARG1) + fld fs1, 15*ARG_SZ (ARG1) + fld fs2, 16*ARG_SZ (ARG1) + fld fs3, 17*ARG_SZ (ARG1) + fld fs4, 18*ARG_SZ (ARG1) + fld fs5, 19*ARG_SZ (ARG1) + fld fs6, 20*ARG_SZ (ARG1) + fld fs7, 21*ARG_SZ (ARG1) + fld fs8, 22*ARG_SZ (ARG1) + fld fs9, 23*ARG_SZ (ARG1) + fld fs10, 24*ARG_SZ (ARG1) + fld fs11, 25*ARG_SZ (ARG1) seqz ARG1, ARG2 - add ARG1, ARG1, ARG2 - jalr ra + add ARG1, ARG1, ARG2 /* ARG1 = ( ARG2 == 0 ) ? 1 : ARG2 */ + ret END_FUNC(dr_longjmp) /* int atomic_swap(int *adr, int val) */ From 1451c1cbcbfbef45d68fa62cb0c32144f99f686c Mon Sep 17 00:00:00 2001 From: shiptux Date: Sun, 21 May 2023 15:19:57 +0800 Subject: [PATCH 9/9] Fix review4 --- core/arch/riscv64/riscv64.asm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/riscv64/riscv64.asm b/core/arch/riscv64/riscv64.asm index 33e3dc44896..1c4ffd11b2d 100644 --- a/core/arch/riscv64/riscv64.asm +++ b/core/arch/riscv64/riscv64.asm @@ -220,8 +220,8 @@ GLOBAL_LABEL(dr_try_start:) DECLARE_FUNC(dr_setjmp) GLOBAL_LABEL(dr_setjmp:) sd ra, 0 (ARG1) - sd t0, ARG_SZ (ARG1) mv t0, sp + sd t0, ARG_SZ (ARG1) sd s0, 2*ARG_SZ (ARG1) sd s1, 3*ARG_SZ (ARG1) sd s2, 4*ARG_SZ (ARG1)