diff --git a/README.md b/README.md index 1d96e78..6da5e12 100644 --- a/README.md +++ b/README.md @@ -32,9 +32,106 @@ For installing and using this colection in Icestudio follow these steps: ## Blocks * **Ledoscope** +* **Ledoscope-Cycles** + * **02-bits** + * Ledoscope-cycles-zero-sys + * **05-bits** + * Ledoscope-cycles-zero-sys +* **Ledoscope-Data** + * **02x02** + * Ledoscope-data-zero-sys + * **04x02** + * Ledoscope-data-zero-sys + * **08x02** + * Ledoscope-data-zero-sys + * **08x04** + * Ledoscope-data-zero-sys + * **08x08** + * Ledoscope-data-zero-sys + * **16x02** + * Ledoscope-data-zero-sys + * **16x04** + * Ledoscope-data-zero-sys + * **32x02** + * Ledoscope-data-zero-sys + * **01-bit** + * ledoscope-sys-1 + * ledoscope-sys-zero-1 + * **02-bits** + * ledoscope-sys-2 + * **04-bits** + * ledoscope-4 + * ledoscope-sys-4 + * ledoscope-sys-zero-4 * **08-bits** + * ledoscope-sys-8 * ledoscope-sys-zero-8 + * **16-bits** + * ledoscope-sys-zero-16 + * **32-bits** + * ledoscope-sys-zero-32 +## Examples +* 00-Index +* **Ledoscope** +* **Ledoscope-Data** + * **08x02-samples** + * **Sys-zero** + * **Alhambra-II** + * Manual-testing + * **08x04-samples** + * **Sys-zero** + * **Alhambra-II** + * Manual-testing + * **16x02-samples** + * **Sys-zero** + * **Alhambra-II** + * 01-Manual-testing + * **32x02-samples** + * **Sys-zero** + * **Alhambra-II** + * 01-Manual-testing +* **Ledoscope-cycles** + * **02-bits** + * **Alhambra-II** + * 01-Manual-testing + * **05-bits** + * **Alhambra-II** + * 01-Manual-testing + * **01-bit** + * **Ledoscope-sys** + * **Alhambra-II** + * Test-01 + * **Ledoscope-zero-sys** + * **Alhambra-II** + * Test-01 + * **02-bits** + * **Ledoscope-sys** + * **Alhambra-II** + * Test-01 + * **04-bits** + * **Ledoscope** + * **Ledoscope-sys** + * **Ledoscope-sys-zero** + * **Alhambra-II** + * Test-01 + * **Alhambra-II** + * Test-01 + * **Alhambra-II** + * Test-01 + * **08-bits** + * **Ledoscope-sys** + * **Ledoscope-sys-zero** + * **Alhambra-II** + * Test-01 + * **Alhambra-II** + * Test-01 + * **16-bits** + * **Ledoscopio-sys-zero** + * **Alhambra-II** + * Test-01 + * **32-bits** + * **Ledoscopio-sys-zero** ## Authors * [Juan Gonzalez-Gomez (Obijuan)](https://github.com/Obijuan) diff --git a/locale/translation.js b/locale/translation.js index 7ce9c02..91386cb 100644 --- a/locale/translation.js +++ b/locale/translation.js @@ -8,46 +8,411 @@ // 2. Press "Update" to update from sources gettext('Ledoscope'); +gettext('Ledoscope-Cycles'); +gettext('Ledoscope-Data'); +gettext('01-bit'); +gettext('02-bits'); +gettext('04-bits'); gettext('08-bits'); -gettext('ledoscope-sys-zero-8'); -gettext('Ledoscope. Capture the input signal during the first 8 cycles after circuit initialization'); +gettext('16-bits'); +gettext('32-bits'); +gettext('02-bits'); +gettext('05-bits'); +gettext('Ledoscope-cycles-zero-sys'); +gettext('2-bits cycles Ledoscope. Measure the cycles it takes for a tic to arrive from the cycle 0'); gettext('Constant bit 0'); -gettext('3-bits Syscounter'); -gettext('DFF-03: Three D flip-flops in paralell'); -gettext('D Flip-flop (verilog implementation)'); -gettext('Bus3-Split-all: Split the 3-bits bus into three wires'); -gettext('Bus3-Join-all: Joint three wires into a 3-bits Bus'); -gettext('Inc1-3bit: Increment a 3-bits number by one'); -gettext('AdderK-3bit: Adder of 3-bit operand and 3-bit constant'); -gettext('Generic: 3-bits generic constant (0-7)'); -gettext('Adder-3bits: Adder of two operands of 3 bits'); +gettext('02-Reg: 2 bits Register. Verilog implementation'); +gettext('2-bits Syscounter'); +gettext('Inc1-2bit: Increment a 2-bits number by one'); +gettext('AdderK-2bit: Adder of 2-bit operand and 2-bit constant'); +gettext('Generic: 2-bits generic constant (0,1,2,3)'); +gettext('Adder-2bits: Adder of two operands of 2 bits'); +gettext('Bus2-Split-all: Split the 2-bits bus into two wires'); gettext('Adder-1bit: Adder of two operands of 1 bit'); gettext('AdderC-1bit: Adder of two operands of 1 bit plus the carry in'); gettext('XOR gate: two bits input xor gate'); gettext('Two bits input And gate'); gettext('OR2: Two bits input OR gate'); -gettext('SReg-right-x8: 8 bits Shift register (to the right)'); -gettext('Bus8-Join-half: Join the two same halves into an 8-bits Bus'); -gettext('SReg-right-x4: 4 bits Shift register (to the right)'); -gettext('Reg: 1-Bit register'); -gettext('2-to-1 Multplexer (1-bit channels). Fippled version'); -gettext('2-to-1 Multplexer (1-bit channels)'); +gettext('Bus2-Join-all: Joint two wires into a 2-bits Bus'); +gettext('02-Sys-reg: 2 bits system register. Verilog implementation'); +gettext('1-tic-pass: Only one tic is allowed to pass. After that the component is blocked (until the reset is activated)'); gettext('NOT gate (Verilog implementation)'); +gettext('RS-FF-set-verilog. RS Flip-flop with priority set. Implementation in verilog'); +gettext('1-tic-pass'); +gettext('The tic on the input channel \ncan only pass one time though the component'); +gettext('Cycles counter'); +gettext('when the tic is received the \ncurrent counter value is \nstored and displayed on \nthe LEDs'); +gettext('2-bits register'); +gettext('0: Ready: Waiting for a tic to arrive \n1: Triggered \n(Meassure performed!)'); +gettext('State of the component: \n* 0: Ready\n* 1: Trigged: Tics are not allowed \nto pass'); +gettext('Tics can only pass if the \ncomponent is ready'); +gettext('Input'); +gettext('Output'); +gettext('Ledoscope-cycles-zero-sys'); +gettext('5-bits cycles Ledoscope. Measure the cycles it takes for a tic to arrive from the cycle 0'); +gettext('05-Reg: 5 bits Register. Verilog implementation'); +gettext('5-bits Syscounter'); +gettext('Inc1-5bit: Increment a 5-bits number by one'); +gettext('AdderK-5bit: Adder of 5-bit operand and 5-bit constant'); +gettext('Adder-5bits: Adder of two operands of 5 bits'); +gettext('Bus5-Split-1-4: Split the 5-bits bus into two buses of 1 and 4 bits'); +gettext('Adder-4bits: Adder of two operands of 4 bits'); +gettext('Bus4-Split-all: Split the 4-bits bus into its wires'); gettext('Bus4-Join-all: Join all the wires into a 4-bits Bus'); -gettext('RS-FF-set. RS Flip-flop with priority set'); -gettext('Constant bit 1'); -gettext('8-bits Shift register'); +gettext('Bus5-Join-1-4: Join the two buses of 1 and 4 bits into a 5-bits Bus'); +gettext('Generic: 5-bits generic constant (0-31)'); +gettext('05-Sys-reg: 5 bits system register. Verilog implementation'); +gettext('5-bits register'); +gettext('02x02'); +gettext('04x02'); +gettext('08x02'); +gettext('08x04'); +gettext('08x08'); +gettext('16x02'); +gettext('16x04'); +gettext('32x02'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 2 samples of 2bits data are taken initially, at the system clock rate'); +gettext('TFF-verilog. System TFF with toggle input: It toogles on every system cycle if the input is active. Verilog implementation'); +gettext('2-to-1 Multplexer (2-bit channels). Verilog implementation'); +gettext('Select which sample is shown \non the LEDs'); +gettext('Sample 0'); +gettext('The first two samples on the \nchannels are captured \n(Samples at cycles 0 to 1)'); +gettext('Enable the capture '); +gettext('This signal is 1 initially'); +gettext('RS-flip-flop'); +gettext('Cycle number: 0-1'); +gettext('The Flip-flips is reset \nat the end of cycle 3'); +gettext('4-cycles with pulse'); +gettext('Sample 1'); +gettext('Sample number currently \ndisplayed'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 2 samples of 4bits data are taken initially, at the system clock rate'); +gettext('Sys-TFF: System TFF: It toogles its output on every system cycle. Verilog implementation'); +gettext('04-Reg: 4 bits Register. Verilog implementation'); +gettext('2-to-1 Multplexer (4-bit channels). Verilog implementation'); +gettext('The first two samples on the \nchannels are captured \n(Samples at cycles 0 and 1)'); +gettext('T flip-flop'); +gettext('Cycle number: 0 and 1'); +gettext('The Flip-flips is reset \nat the end of cycle 1'); +gettext('2-cycles with pulse'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 2 samples of 8bits data are taken initially, at the system clock rate'); +gettext('08-Reg: 8 bits Register. Verilog implementation'); +gettext('2-to-1 Multplexer (8-bit channels). Verilog implementation'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 4 samples of 8bits data are taken initially, at the system clock rate'); +gettext('OR-BUS2: OR gate with 2-bits bus input'); +gettext('4-to-1 Multplexer (8-bit channels). Verilog implementation'); +gettext('Counter-x02: 2-bits counter'); +gettext('The first four samples on the \nchannels are captured \n(Samples at cycles 0 to 3)'); +gettext('Cycle number: 0-3'); +gettext('Sample 2'); +gettext('Sample 3'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 8 samples of 8bits data are taken initially, at the system clock rate'); +gettext('8-to-1 Multplexer (8-bit channels) (Verilog implementation)'); +gettext('OR-BUS3-verilog: OR gate with 3-bits bus input. Verilog implementation'); +gettext('3-bits Syscounter'); +gettext('Inc1-3bit: Increment a 3-bits number by one'); +gettext('AdderK-3bit: Adder of 3-bit operand and 3-bit constant'); +gettext('Generic: 3-bits generic constant (0-7)'); +gettext('Adder-3bits: Adder of two operands of 3 bits'); +gettext('Bus3-Split-all: Split the 3-bits bus into three wires'); +gettext('Bus3-Join-all: Joint three wires into a 3-bits Bus'); +gettext('03-Sys-reg: 3 bits system register. Verilog implementation'); +gettext('Counter-x03: 3-bits counter'); +gettext('03-Reg: 3 bits Register. Verilog implementation'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 2 samples of 16bits data are taken initially, at the system clock rate'); +gettext('2-to-1 Multplexer (16-bit channels). Verilog implementation'); +gettext('16-Reg: 16 bits Register. Verilog implementation'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 4 samples of 16bits data are taken initially, at the system clock rate'); +gettext('OR-BUS2-verilog: OR gate with 2-bits bus input. Verilog implementation'); +gettext('4-to-1 Multplexer (16-bit channels). Verilog implementation'); +gettext('The first four samples on the \nchannels are captured \n(Samples at cycles 0-3)'); +gettext('Ledoscope-data-zero-sys'); +gettext('Data Ledoscope. 2 samples of 32bits data are taken initially, at the system clock rate'); +gettext('2-to-1 Multplexer (32-bit channels). Verilog implementation'); +gettext('32-Reg: 32 bits Register. Verilog implementation'); +gettext('It is 1 if the sample 0 is \nthe current sample'); +gettext('ledoscope-sys-1'); +gettext('Ledoscope. Capture the input signal'); +gettext('DFF. D Flip-flop. Verilog implementation'); +gettext('One sample is captured \n'); +gettext('ledoscope-sys-zero-1'); +gettext('Ledoscope. Capture the input signal during the cycle 0'); +gettext('start: Start signal: It goes from 1 to 0 when the system clock starts. 1 cycle pulse witch. Block implementation'); +gettext('System - D Flip-flop. Capture data every system clock cycle. Verilog implementation'); +gettext('One sample is captured \n(at cycle 0)'); +gettext('The load signal is activated \nonly in the cycle 0'); +gettext('System clock'); +gettext('Initial value: 1'); +gettext('Initial value: 0'); +gettext('Falling edge'); +gettext('Parameter: Initial value'); +gettext('Input data'); +gettext('# D Flip-Flop (system)\n\nIt stores the input data that arrives at cycle n \nIts output is shown in the cycle n+1'); +gettext('Not connected'); +gettext('ledoscope-sys-2'); +gettext('Ledoscope. Capture the input signal for 2 cycles'); +gettext('02-SR: 2 bits shift right register. Verilog implementation'); +gettext('Sample number: \n* 0: First sample \n* 1: second sample'); +gettext('the start signal only enters \nwhen the Ledoscope is off. It is \nnot allowed to enter when it is on'); +gettext('LEDoscope state: \n* 0: Not capturing\n* 1: Capturing data'); +gettext('2-bits shift register'); +gettext('Buffer for capturing the \ntwo samples'); +gettext('ledoscope-4'); +gettext('Ledoscope. Capture 4 samples of the input signal'); +gettext('04-SR: 4 bits shift right register. Verilog implementation'); +gettext('Sample number: \n* 0: First sample \n* 1: second sample\n* ...'); +gettext('4-bits shift register'); +gettext('Buffer for capturing the \nfour samples'); +gettext('After 4 cycles the Flip-Flop is \nreset and it stops capturing \nbits'); +gettext('As the 2-bits system counter is counting \nall the time, the done signal is only \ngenerated when the counter reaches the maximum \nvalue and the Ledoscope is on (busy)'); gettext('The input channel is captured \non the register. One bit per \nsystem clock'); -gettext('RS FlipFlop initialized to 1'); +gettext('The next signal is only read if the \nLEDoscope has been previously started'); +gettext('ledoscope-sys-4'); +gettext('Ledoscope. Capture the input signal for 4 cycles'); gettext('while 1, the shift register \nis capturing'); +gettext('ledoscope-sys-zero-4'); +gettext('Ledoscope. Capture the input signal during the first 4 cycles after circuit initialization'); +gettext('SR-04-verilog: 4-bits Shift register to the right. Verilog implementation'); +gettext('4-bits Shift register'); +gettext('RS FlipFlop initialized to 1'); +gettext('2-bits counter'); +gettext('ledoscope-sys-8'); +gettext('Ledoscope-sys. Capture the input signal during the 8 cycles after the start signal is active'); +gettext('08-SR: 8 bits shift right register. Verilog implementation'); +gettext('ledoscope-sys-zero-8'); +gettext('Ledoscope. Capture the input signal during the first 8 cycles after circuit initialization'); +gettext('SR-08-verilog: 8-bits Shift register to the right. Verilog implementation'); +gettext('8-bits Shift register'); gettext('3-bits counter'); gettext('After 8 cycles the Flip-Flop is \nreset and it stops capturing \nbits'); -gettext('Parameter: Initial value'); -gettext('System clock'); -gettext('Input data'); -gettext('Output'); -gettext('# D Flip-Flop \n\nIt stores the input data that arrives at cycle n \nIts output is shown in the cycle n+1'); -gettext('Mux 2-1'); -gettext('D Flip-flip\n(System)'); -gettext('Input'); -gettext('Priority for the set'); +gettext('ledoscope-sys-zero-16'); +gettext('Ledoscope. Capture the input signal during the first 16 cycles after circuit initialization'); +gettext('Bus16-Join-half: Join the two same halves into an 16-bits Bus'); +gettext('4-bits Syscounter'); +gettext('Inc1-4bit: Increment a 4-bits number by one'); +gettext('AdderK-4bit: Adder of 4-bit operand and 4-bit constant'); +gettext('Generic: 4-bits generic constant (0-15)'); +gettext('04-Sys-reg: 4 bits system register. Verilog implementation'); +gettext('4-bits counter'); +gettext('ledoscope-sys-zero-32'); +gettext('Ledoscope. Capture the input signal during the first 32 cycles after circuit initialization'); +gettext('Bus32-Join-quarter: Join the four buses into an 32-bits Bus'); +gettext('5-bits counter'); +gettext('After 16 cycles the Flip-Flop is \nreset and it stops capturing \nbits'); +gettext('Ledoscope'); +gettext('Ledoscope-Data'); +gettext('Ledoscope-cycles'); +gettext('00-Index'); +gettext('# INDEX: IceLEDOscope Collection'); +gettext('## LEDOscope'); +gettext('## LEDOscope-DATA'); +gettext('## LEDOscope-Cycles'); +gettext('### 1-bit'); +gettext('Ledoscope-sys-zero'); +gettext('Ledoscope-sys'); +gettext('### 2-bits'); +gettext('### 4-bits'); +gettext('### 8-bits'); +gettext('01-bit'); +gettext('02-bits'); +gettext('04-bits'); +gettext('08-bits'); +gettext('16-bits'); +gettext('32-bits'); +gettext('08x02-samples'); +gettext('08x04-samples'); +gettext('16x02-samples'); +gettext('32x02-samples'); +gettext('Sys-zero'); +gettext('Alhambra-II'); +gettext('Manual-testing'); +gettext('8bits constant value: 0'); +gettext('Generic: 8-bits generic constant (0-255)'); +gettext('08-Sys-reg: 8 bits system register. Verilog implementation'); +gettext('Button-tic: Configurable button that emits a tic when it is pressed'); +gettext('Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input. Block implementation'); +gettext('Configurable button (pull-up on/off. Not on/off)'); +gettext('FPGA internal pull-up configuration on the input port'); +gettext('Select positive or negative logic for the input (0=positive, 1=negative)'); +gettext('Valor genérico constante, de 1 bits. Su valor se introduce como parámetro. Por defecto vale 0'); +gettext('Remove the rebound on a mechanical switch'); +gettext('Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input. Block implementation'); +gettext('16-bits Syscounter with reset'); +gettext('Inc1-16bit: Increment a 16-bits number by one'); +gettext('AdderK-16bit: Adder of 16-bit operand and 16-bit constant'); +gettext('Generic: 16-bits generic constant'); +gettext('Adder-16bits: Adder of two operands of 16 bits'); +gettext('Bus16-Split-half: Split the 16-bits bus into two buses of the same size'); +gettext('Adder-8bits: Adder of two operands of 8 bits'); +gettext('Bus8-Split-half: Split the 8-bits bus into two buses of the same size'); +gettext('Bus8-Join-half: Join the two same halves into an 8-bits Bus'); +gettext('AdderC-4bits: Adder of two operands of 4 bits and Carry in'); +gettext('AdderC-8bits: Adder of two operands of 8 bits and Carry in'); +gettext('16-Sys-reg-rst: 16 bits system register with reset. Verilog implementation'); +gettext('Sync-x01: 1-bit input with the system clock domain (Verilog implementation)'); +gettext('# Testing the LEDoscope-Data-zero-sys 8x2-samples\n\n'); +gettext('Values generated at cycles 0 and 1'); +gettext('Select which data is \nshown on the LEDs'); +gettext('Capture the data \nat channel 1'); +gettext('Button state signal'); +gettext('Tic: button pressed'); +gettext('Rising edge detector'); +gettext('Pull up on/off'); +gettext('Not on/off'); +gettext('## Rising edge detector\n\nIt generates a 1-period pulse (tic) when a rising edge is detected on the \ninput signal'); +gettext('Input signal'); +gettext('Current signal \nstate'); +gettext('Signal state in the previous \nclock cycle'); +gettext('If the current signal is 1 and its value in \nthe previous clock cycle was 0, it means \nthat a rising edge has been detected! \nThe output es 1\n\nIn any other case the output is 0'); +gettext('**Delay**: 0 clock cycles \n\nThere is no delay between the arrival of a rising edge \nand its detection'); +gettext('Internal pull-up \n* 0: OFF\n* 1: ON'); +gettext('Synchronization stage'); +gettext('Normalization stage\n\n* 0: Wire\n* 1: signal inverted'); +gettext('Debouncing stage'); +gettext('### Pull-up parameter:\n\n0: No pull-up \n1: Pull-up activated'); +gettext('Only an FPGA pin can \nbe connected here!!!'); +gettext('The pull-up is connected \nby default'); +gettext('When k=0, it works like a wire \n(The output is equal to the input) \nWhen k=1, it act as a not gate\n(The output is the inverse of the input)'); +gettext('### Truth table for XOR\n\n| k | input | output | function |\n|---|-------|--------|----------|\n| 0 | 0 | 0 | wire |\n| 0 | 1 | 1 | wire |\n| 1 | 0 | 1 | Not |\n| 1 | 1 | 0 | Not |'); +gettext('Edge detector'); +gettext('Whenever there is a change in \nthe input, the counter is started'); +gettext('If the counter reaches it maximum \nvalue, the input is considered stable \nand it is captured'); +gettext('### Time calculation\n\nFor CLK=12MHZ, a 16-bit counter reaches its \nmaximum every 2 ** 16 * 1/F = 5.5ms aprox \nIF more time is needed for debouncing, \nuse a counter with more bits (17, 18...)'); +gettext('## Debouncer \n\nA value is considered stable when \nthere is no changes during 5.5ms \naprox. When a value is stable it is \ncaptured on the output flip-flop'); +gettext('Stable output'); +gettext('Counter'); +gettext('## Edges detector\n\nIt generates a 1-period pulse (tic) when an edge (Rising or falling) is detected on the \ninput signal'); +gettext('The output is 1 if the current value is 1 and the \nprevious 0, or if the current value is 0 and the \nprevious 1\n'); +gettext('In any other case the output is 0'); +gettext('Manual-testing'); +gettext('Sys-zero'); +gettext('Alhambra-II'); +gettext('Manual-testing'); +gettext('# Testing the LEDoscope-Data-zero-sys 8x4-samples\n\n'); +gettext('Values generated at cycles 0-3'); +gettext('Manual-testing'); +gettext('Sys-zero'); +gettext('Alhambra-II'); +gettext('01-Manual-testing'); +gettext('16bits constant value: 0'); +gettext('16-Sys-reg: 16 bits system register. Verilog implementation'); +gettext('Display16-8: Display a 16-bits value on an 8-LEDs. The sel input selects the byte to display '); +gettext('2-to-1 Multplexer (8-bit channels)'); +gettext('2-to-1 Multplexer (4-bit channels)'); +gettext('2-to-1 Multplexer (1-bit channels)'); +gettext('# Testing the LEDoscope-Data-zero-sys 16x2-samples\n\n'); +gettext('* OFF: Cycle 0\n* ON: cycle 1'); +gettext('CFG LED:'); +gettext('Display-16-8'); +gettext('Display the data on the LEDs'); +gettext('Select the byte to show \non the LEDs'); +gettext('Byte 0 \n(least significant) '); +gettext('Channel B'); +gettext('Channel A'); +gettext('01-Manual-testing'); +gettext('Sys-zero'); +gettext('Alhambra-II'); +gettext('01-Manual-testing'); +gettext('32bits constant value: 0'); +gettext('Generic: 32-bits generic constant'); +gettext('Display32-8: Display a 32-bits value on an 8-LEDs. The sel input selects the byte to display '); +gettext('Bus32-Split-quarter: Split the 32-bits bus into four buses of 8 wires'); +gettext('4-to-1 Multplexer (8-bit channels)'); +gettext('32-Sys-reg: 32 bits system register. Verilog implementation'); +gettext('# Testing the LEDoscope-Data-zero-sys 32x02-samples\n\n'); +gettext('Display-32-8'); +gettext('01-Manual-testing'); +gettext('02-bits'); +gettext('05-bits'); +gettext('Alhambra-II'); +gettext('01-Manual-testing'); +gettext('Constant bit 1'); +gettext('# Testing the 2-bits LEDoscope-cycles-zero-sys\n\n'); +gettext('Circuit to meassure. It takes 2 cycles for the 1-bit to \nreach the channel input'); +gettext('01-Manual-testing'); +gettext('Alhambra-II'); +gettext('01-Manual-testing'); +gettext('Sys-Delay-xN-K: The input tic is delayed N cycles'); +gettext('Sys-Delay-xN-3bits: The input tic is delayed N cycles'); +gettext('Counter-M-x03: 3-bits M module counter with reset'); +gettext('Comp2-3bit: Comparator of two 3-bit numbers'); +gettext('Comp2-1bit: Comparator of two 1-bit numbers'); +gettext('Three bits input And gate'); +gettext('03-Reg-rst: 3 bits Register with reset. Verilog implementation'); +gettext('# Testing the 5-bits LEDoscope-cycles-zero-sys\n\n'); +gettext('Circuit to meassure. It takes 8 cycles for the 1-bit to \nreach the channel input'); +gettext('Current working cycle: 0-1'); +gettext('Cycles to delay'); +gettext('Delay finished!'); +gettext('Machine state: ON/OFF'); +gettext('Sys-Delay-xN'); +gettext('Current working cycle: 1-3'); +gettext('RS Flip-Flop'); +gettext('Circuit state: \n* ON: working (1)\n* OFF: Not working (0)'); +gettext('The counter has reached \nthe number of cycles \nto delay'); +gettext('Initial value'); +gettext('2-bits Comparator'); +gettext('Maximum count \nreached'); +gettext('If the max count is reached \nand the cnt tic is received, \nthe register is reset to 0'); +gettext('External reset'); +gettext('A'); +gettext('B'); +gettext('01-Manual-testing'); +gettext('Ledoscope-sys'); +gettext('Ledoscope-zero-sys'); +gettext('Alhambra-II'); +gettext('Test-01'); +gettext('# Testing the LEDoscope-sys 1-bit\n'); +gettext('Test-01'); +gettext('Alhambra-II'); +gettext('Test-01'); +gettext('# Testing the LEDoscope-zero-sys 1-bit\n'); +gettext('Test-01'); +gettext('Ledoscope-sys'); +gettext('Alhambra-II'); +gettext('Test-01'); +gettext('# Testing the LEDoscope-sys 2-bit\n'); +gettext('Two width pulse'); +gettext('Test-01'); +gettext('Ledoscope'); +gettext('Ledoscope-sys'); +gettext('Ledoscope-sys-zero'); +gettext('Alhambra-II'); +gettext('Alhambra-II'); +gettext('Alhambra-II'); +gettext('Test-01'); +gettext('# Testing the LEDoscope-zero-sys-4 bits\n\nThe less significant signal of a 2-bits counter is captured and shown \non the LED'); +gettext('Test-01'); +gettext('Test-01'); +gettext('Sys-TFF-rst: System TFF with reset: It toogles its output on every system cycle. Verilog implementation'); +gettext('# Testing the LEDoscope-sys 4-bit\n'); +gettext('Test-01'); +gettext('Test-01'); +gettext('# Testing the LEDoscope 4-bit\n'); +gettext('Test-01'); +gettext('Ledoscope-sys'); +gettext('Ledoscope-sys-zero'); +gettext('Alhambra-II'); +gettext('Alhambra-II'); +gettext('Test-01'); +gettext('# Testing the LEDoscope-zero-sys-8 bits\n\nThe less significant signal of a 2-bits counter is captured and shown \non the LED'); +gettext('Test-01'); +gettext('Test-01'); +gettext('# Testing the LEDoscope-sys-8 bits\n'); +gettext('Test-01'); +gettext('Ledoscopio-sys-zero'); +gettext('Alhambra-II'); +gettext('Test-01'); +gettext('Delay-tic-x1: The input tic is delayed 1 cycle'); +gettext('# Testing the LEDoscope-zero-sys-16 bits\n'); +gettext('Delay 1 cycle'); +gettext('Sys-DFF'); +gettext('Test-01'); +gettext('Ledoscopio-sys-zero'); +gettext('00-Index');