testbench.vl

//Testbench
//Travis Layne tll8197
//Andrew Colvin awc1517

module Top();
	reg GO, maxCarsNS, maxCarsEW, sNS, sEW, rst, clk, picture1, picture2, i, halfclk;
  reg [2:0]currState, nextState, crrState;

  FSM Test1(GO, maxCarsNS, maxCarsEW, sNS, sEW, rst, clk, currState, picture1, picture2, nextState, halfclk);

	//Reset and clock section
	initial begin
		clk = 0; 
		rst = 0;
		halfclk = 0;
		#100 rst = 1; //restart machine after 1000 clock cycles
		#1 rst = 0;
      	#1000 GO = 0;
	end

  always #6 clk = ~clk; //(rate at which you switch states)changing clock frequency ---- 10 MHz clock(50 % 1 ns *2) with 50% duty-cycle
  always #3 halfclk = ~halfclk; 

	//specift the input waveforms for maxCars
	initial 
      begin
        GO = 1;
        #1;
		//intially no traffic
		maxCarsNS = 0;
		maxCarsEW = 0;
		sNS = 0;
		sEW =0;

		#1; //Delay to keep inputs from, changing on clock edge


		//example for maxCars  #600 maxcars = 1;  // at time 601 maxCars =1
		//                     #400 maxCars = 0; at 400 mroe cycles maxCars is 0
        
        for(i = 0; i < 2; i=i+1)
          begin 
            //every 10 clock cycles there is a 50% chance of traffc on both sides of the road
            //also 50% chance that each sensore goes off, which implies that someone violated the traffic law and a picture was taken
            #6
			maxCarsNS = $random; 
			maxCarsEW = $random;
			sNS = $random;
			sEW = $random;
          end
        
		$finish; // end simulation
	end

	initial
		begin
          $monitor("\nStart=%b, \nTrafficDetectorNS=%b, TrafficDetectorEW=%b, \nSenorNS=%b, SensorEW=%b, \nreset=%b, clock=%b, halfclock=%b \ncurrentState=%3b, nextState=%3b, \npictureNS=%b,  pictureEW=%b,  \ntime = %t", GO, maxCarsNS, maxCarsEW, sNS, sEW, rst, clk, halfclk, currState, nextState, picture1, picture2, $time);
		end
endmodule;