diff --git a/Lab2_VHDL/Lab2_VHDL/simulation/modelsim.ini b/Lab1_VHDL/simulation/modelsim.ini.sav similarity index 70% rename from Lab2_VHDL/Lab2_VHDL/simulation/modelsim.ini rename to Lab1_VHDL/simulation/modelsim.ini.sav index 320458a..7be6750 100644 --- a/Lab2_VHDL/Lab2_VHDL/simulation/modelsim.ini +++ b/Lab1_VHDL/simulation/modelsim.ini.sav @@ -3,6 +3,8 @@ others = $MODEL_TECH/../modelsim.ini smartfusion2 = C:/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2 syncad_vhdl_lib = C:\Microsemi\Libero_SoC_v11.7\Designer/lib/actel/syncad_vhdl_lib +postsynth = postsynth +IGLOO2 = C:/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2 [vcom] VHDL93 = 1 diff --git a/Lab1_VHDL/synthesis/LedBlinkingDSpeed_syn.bak b/Lab1_VHDL/synthesis/LedBlinkingDSpeed_syn.bak new file mode 100644 index 0000000..6e8db68 --- /dev/null +++ b/Lab1_VHDL/synthesis/LedBlinkingDSpeed_syn.bak @@ -0,0 +1,70 @@ +#-- Synopsys, Inc. +#-- Version J-2015.03M-SP1-2 +#-- Project file C:\Users\ashj\Documents\LEARNING\Microsemi\Lab1_VHDL_VHDL\synthesis\LedBlinkingDSpeed_syn.prj + +#project files +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/ClkGen.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/ClkGenNoSwitch.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/Display.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/Reset_out.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/hdl/LedBlinkingDSpeed.vhd" +add_file -fpga_constraint "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab1_VHDL_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc" + + + +#implementation: "synthesis" +impl -add synthesis -type fpga + +#device options +set_option -technology IGLOO2 +set_option -part M2GL025 +set_option -package VF256 +set_option -speed_grade STD +set_option -part_companion "" + +#compilation/mapping options +set_option -use_fsm_explorer 0 +set_option -top_module "work.LedBlinkingDSpeed" + +# mapper_options +set_option -frequency 100.000 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# actel_options +set_option -rw_check_on_ram 0 + +# Microsemi G4 +set_option -run_prop_extract 1 +set_option -maxfan 10000 +set_option -clock_globalthreshold 2 +set_option -async_globalthreshold 12 +set_option -globalthreshold 5000 +set_option -low_power_ram_decomp 0 +set_option -disable_io_insertion 0 +set_option -opcond COMTC +set_option -retiming 0 +set_option -report_path 4000 +set_option -update_models_cp 0 +set_option -preserve_registers 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +# Compiler Options +set_option -vhdl2008 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./LedBlinkingDSpeed.edn" +impl -active "synthesis" diff --git a/Lab2_VHDL/Lab2_VHDL/Lab2_VHDL.prjx b/Lab2_VHDL/Lab2_VHDL.prjx similarity index 67% rename from Lab2_VHDL/Lab2_VHDL/Lab2_VHDL.prjx rename to Lab2_VHDL/Lab2_VHDL.prjx index 3a0fa59..ff510eb 100644 --- a/Lab2_VHDL/Lab2_VHDL/Lab2_VHDL.prjx +++ b/Lab2_VHDL/Lab2_VHDL.prjx @@ -1,6 +1,7 @@ KEY LIBERO "11.7" KEY CAPTURE "11.7.1.14" -KEY DEFAULT_IMPORT_LOC "" +KEY DEFAULT_IMPORT_LOC "C:\Actelprj\A3P_Verilog_labs\lab2" +KEY DEFAULT_OPEN_LOC "" KEY ProjectID "0" KEY HDLTechnology "VHDL" KEY VERILOGMODE "VERILOG2001" @@ -14,7 +15,9 @@ KEY VendorTechnology_DieVoltage "1.2" KEY VendorTechnology_PART_RANGE "COM" KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS" KEY VendorTechnology_IO_DEFT_STD "LVCMOS33" +KEY VendorTechnology_OPCONR "" KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_33" +KEY VendorTechnology_RAD_EXPOSURE "" KEY VendorTechnology_RESERVEMIGRATIONPINS "1" KEY VendorTechnology_RESTRICTPROBEPINS "0" KEY VendorTechnology_RESTRICTSPIPINS "0" @@ -28,7 +31,7 @@ KEY VendorTechnology_VCCI_1.8_VOLTR "COM" KEY VendorTechnology_VCCI_2.5_VOLTR "COM" KEY VendorTechnology_VCCI_3.3_VOLTR "COM" KEY VendorTechnology_VOLTR "COM" -KEY ProjectLocation "C:\Users\ashj\Documents\LEARNING\Microsemi\Lab2_VHDL\Lab2_VHDL" +KEY ProjectLocation "C:\Users\ashj\Documents\LEARNING\Microsemi\Lab2_VHDL" KEY ProjectDescription "" KEY Pa4PeripheralNewSeq "GOOD" KEY SimulationType "VHDL" @@ -41,45 +44,113 @@ ENDLIST LIST FileManager VALUE "\constraint\io\LedBlinkingDSpeed.io.pdc,io_pdc" STATE="utd" -TIME="1489082277" +TIME="1477216352" SIZE="1197" ENDFILE VALUE "\constraint\LedBlinkingDSpeed_sdc.sdc,sdc" STATE="utd" -TIME="1489082277" +TIME="1477216352" SIZE="152" ENDFILE +VALUE "\designer\impl1\LedBlinkingDSpeed.ide_des,ide_des" +STATE="utd" +TIME="1477216382" +SIZE="438" +ENDFILE VALUE "\hdl\ClkGen.vhd,hdl" STATE="utd" -TIME="1489082275" +TIME="1477216352" SIZE="4624" ENDFILE VALUE "\hdl\ClkGenNoSwitch.vhd,hdl" STATE="utd" -TIME="1489082275" +TIME="1477216352" SIZE="4722" ENDFILE VALUE "\hdl\Display.vhd,hdl" STATE="utd" -TIME="1489082275" +TIME="1477216352" SIZE="4734" ENDFILE VALUE "\hdl\LedBlinkingDSpeed.vhd,hdl" STATE="utd" -TIME="1489082275" -SIZE="8892" +TIME="1477216740" +SIZE="8890" ENDFILE VALUE "\hdl\Reset_out.vhd,hdl" STATE="utd" -TIME="1489082275" +TIME="1477216352" SIZE="3699" ENDFILE +VALUE "\simulation\run.do,do" +STATE="utd" +TIME="1477216662" +SIZE="727" +ENDFILE +VALUE "\stimulus\LedBlinkingDSpeed_tb.vhd,tb_hdl" +STATE="utd" +TIME="1477216430" +SIZE="6181" +ENDFILE +VALUE "\synthesis\LedBlinkingDSpeed.edn,syn_edn" +STATE="utd" +TIME="1477216774" +SIZE="182614" +ENDFILE +VALUE "\synthesis\LedBlinkingDSpeed.so,so" +STATE="utd" +TIME="1477216774" +SIZE="259" +ENDFILE +VALUE "\synthesis\LedBlinkingDSpeed.vhd,syn_hdl" +STATE="utd" +TIME="1477216778" +SIZE="88479" +ENDFILE +VALUE "\synthesis\LedBlinkingDSpeed_sdc.sdc,syn_sdc" +STATE="utd" +TIME="1477216774" +SIZE="901" +ENDFILE +VALUE "\synthesis\LedBlinkingDSpeed_syn.prj,prj" +STATE="utd" +TIME="1477216776" +SIZE="2218" +ENDFILE ENDLIST LIST UsedFile ENDLIST LIST NewModulesInfo +LIST "LedBlinkingDSpeed::work" +FILE "\hdl\LedBlinkingDSpeed.vhd,hdl" +LIST AssociatedStimulus +VALUE "\stimulus\LedBlinkingDSpeed_tb.vhd,tb_hdl" +ENDLIST +LIST SynthesisConstraints +VALUE "\constraint\LedBlinkingDSpeed_sdc.sdc,sdc" +ENDLIST +LIST TimingConstraints +VALUE "\constraint\LedBlinkingDSpeed_sdc.sdc,sdc" +ENDLIST +LIST ProjectState5.1 +LIST Impl1 +LiberoState=Post_Synthesis +ideSTIMULUS=StateSuccess +ideSYNTHESIS(\synthesis\LedBlinkingDSpeed.edn,syn_edn)=StateSuccess +LIST FlowOptions +UsePhySynth=FALSE +UseSynth=TRUE +ENDLIST +Used_File_List +ENDUsed_File_List +ENDLIST +ENDLIST +ENDLIST ENDLIST LIST AssociatedStimulus +LIST LedBlinkingDSpeed +VALUE "\stimulus\LedBlinkingDSpeed_tb.vhd,tb_hdl" +ENDLIST ENDLIST LIST Other_Association ENDLIST @@ -87,16 +158,16 @@ LIST SimulationOptions UseAutomaticDoFile=true IncludeWaveDo=false Type=max -RunTime=1000ns +RunTime=650us Resolution=1fs VsimOpt= -EntityName=testbench +EntityName=LedBlinkingDSpeed_tb TopInstanceName=_0 DoFileName= DoFileName2=wave.do DoFileParams= DisplayDUTWave=false -LogAllSignals=false +LogAllSignals=true DisablePulseFiltering=false DumpVCD=false VCDFileName=power.vcd @@ -182,6 +253,19 @@ IS32BIT="1" EndProfile ENDLIST LIST ProjectState5.1 +LIST "LedBlinkingDSpeed::work" +LIST Impl1 +LiberoState=Post_Synthesis +ideSTIMULUS=StateSuccess +ideSYNTHESIS(\synthesis\LedBlinkingDSpeed.edn,syn_edn)=StateSuccess +LIST FlowOptions +UsePhySynth=FALSE +UseSynth=TRUE +ENDLIST +Used_File_List +ENDUsed_File_List +ENDLIST +ENDLIST ENDLIST LIST ExcludePackageForSimulation ENDLIST @@ -195,10 +279,8 @@ LIST UserCustomizedFileList ENDLIST LIST OpenedFileList ORIENTATION;HORIZONTAL -Reports;Reports;0 -ReportsCurrentItem;Project Summary:Lab2_VHDL.log StartPage;StartPage;0 -ACTIVEVIEW;Reports +ACTIVEVIEW;StartPage ENDLIST LIST ModuleSubBlockList LIST "ClkGen::work","hdl\ClkGen.vhd","FALSE","FALSE" @@ -215,6 +297,9 @@ SUBBLOCK "Reset_out::work","hdl\Reset_out.vhd","FALSE","FALSE" ENDLIST LIST "Reset_out::work","hdl\Reset_out.vhd","FALSE","FALSE" ENDLIST +LIST "LedBlinkingDSpeed_tb::work","stimulus\LedBlinkingDSpeed_tb.vhd","FALSE","TRUE" +SUBBLOCK "LedBlinkingDSpeed::work","hdl\LedBlinkingDSpeed.vhd","FALSE","FALSE" +ENDLIST ENDLIST LIST ActiveTestBenchList ENDLIST diff --git a/Lab2_VHDL/Lab2_VHDL/smartgen/smartgen.aws b/Lab2_VHDL/Lab2_VHDL/smartgen/smartgen.aws deleted file mode 100644 index e4d6713..0000000 --- a/Lab2_VHDL/Lab2_VHDL/smartgen/smartgen.aws +++ /dev/null @@ -1 +0,0 @@ -smartgenVHDLVHDL \ No newline at end of file diff --git a/Lab2_VHDL/Lab2_VHDL/tooldata/LedBlinkingDSpeed_tools.xml b/Lab2_VHDL/Lab2_VHDL/tooldata/LedBlinkingDSpeed_tools.xml deleted file mode 100644 index a6943b2..0000000 --- a/Lab2_VHDL/Lab2_VHDL/tooldata/LedBlinkingDSpeed_tools.xml +++ /dev/null @@ -1 +0,0 @@ -falseERRORLOCK1250002falsefalsefalsefalsefalsefalsefalsefalsefalsefalseflashlockfalsedefaultfullfalsepasskeypasskeyfalsefalseflashlockfalsefalsefalsetruefalsetruetrue100falsefalseselected_featuresfalsefree_running_clkOFF400000ONfree_running_clkOFF400000ONfree_running_clkOFF400000ONOFFOFF400000ONONOFFOFFON400000ON2.5ONONfalsetruefalseVHDLPDC_PLACEPDC_PLACEfalseERRORLOCKverilogUserBlockBlocktruetruetrueCompany1.0RCOSC_1MHZSUSPENDMAXfalsefalseVIOLATIONSfalse5false0trueWORST_SLACK1falsetruefalsefalseselected_featuresfalse""falseVHDLtruetruetrueXMLfalsetruefalsetruetruefalsetruefalse \ No newline at end of file diff --git a/Lab2_VHDL/Lab2_VHDL/constraint/LedBlinkingDSpeed_sdc.sdc b/Lab2_VHDL/constraint/LedBlinkingDSpeed_sdc.sdc similarity index 100% rename from Lab2_VHDL/Lab2_VHDL/constraint/LedBlinkingDSpeed_sdc.sdc rename to Lab2_VHDL/constraint/LedBlinkingDSpeed_sdc.sdc diff --git a/Lab2_VHDL/Lab2_VHDL/constraint/io/LedBlinkingDSpeed.io.pdc b/Lab2_VHDL/constraint/io/LedBlinkingDSpeed.io.pdc similarity index 100% rename from Lab2_VHDL/Lab2_VHDL/constraint/io/LedBlinkingDSpeed.io.pdc rename to Lab2_VHDL/constraint/io/LedBlinkingDSpeed.io.pdc diff --git a/Lab2_VHDL/constraint/io/pre/LedBlinkingDSpeed.io.pdc b/Lab2_VHDL/constraint/io/pre/LedBlinkingDSpeed.io.pdc new file mode 100644 index 0000000..f5682be --- /dev/null +++ b/Lab2_VHDL/constraint/io/pre/LedBlinkingDSpeed.io.pdc @@ -0,0 +1,81 @@ +# Microsemi I/O Physical Design Constraints file + +# User I/O Constraints file + +# Version: v11.7 SP1 11.7.1.11 + +# Family: IGLOO2 , Die: M2GL025 , Package: 256 VF + +# Date generated: Sun Oct 23 02:59:56 2016 + + +# +# User Locked I/O Bank Settings +# + + +# +# Unlocked I/O Bank Settings +# The I/O Bank Settings can be locked by directly editing this file +# or by making changes in the I/O Attribute Editor +# + + +# +# User Locked I/O settings +# + +set_io SW1 \ + -pinname H12 \ + -fixed yes \ + -DIRECTION INPUT + + +set_io SW2 \ + -pinname H13 \ + -fixed yes \ + -DIRECTION INPUT + + +set_io clk \ + -pinname H16 \ + -fixed yes \ + -DIRECTION INPUT + + +set_io green_led1 \ + -pinname J16 \ + -fixed yes \ + -DIRECTION OUTPUT + + +set_io green_led2 \ + -pinname M16 \ + -fixed yes \ + -DIRECTION OUTPUT + + +set_io red_led1 \ + -pinname K16 \ + -fixed yes \ + -DIRECTION OUTPUT + + +set_io red_led2 \ + -pinname N16 \ + -fixed yes \ + -DIRECTION OUTPUT + + + +# +# Dedicated Peripheral I/O Settings +# + + +# +# Unlocked I/O settings +# The I/Os in this section are unplaced or placed but are not locked +# the other listed attributes have been applied +# + diff --git a/Lab2_VHDL/constraint/io/run_ioed.def b/Lab2_VHDL/constraint/io/run_ioed.def new file mode 100644 index 0000000..7836bfe --- /dev/null +++ b/Lab2_VHDL/constraint/io/run_ioed.def @@ -0,0 +1,35 @@ +data DESIGN LedBlinkingDSpeed +data HPATH 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed' +data CPATH 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/constraint/io' +data CDIR 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/constraint' +data REGION_DEFCOLOR_EMPTY 2143322112 +data REGION_DEFCOLOR_INCLUSIVE 2147442270 +data REGION_DEFCOLOR_EXCLUSIVE 2143338688 +data REGION_DEFCOLOR_CLOCK 16735838 +data ETYPE IO +data FAM IGLOO2 +data DIE PA4MGL2500_N +data PACKAGE vf256 +data HYDRA_EXPORT_DATA 1 +data HYDRA_PRESERVE_DATA_FILES 1 +data VCCI_1.2_VOLTR COM +data VCCI_1.5_VOLTR COM +data VCCI_1.8_VOLTR COM +data VCCI_2.5_VOLTR COM +data VCCI_3.3_VOLTR COM +data FLOW_TYPE NEW +data AFL 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.afl' +data ADL 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.adl' +data LOC 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.loc' +data SEG 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.seg' + +data IO_PDC_0 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/constraint/io/LedBlinkingDSpeed.io.pdc' +data TARGET_IOPDC 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/constraint/io/user.pdc' +data TARGET_FPPDC 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/constraint/fp/user.pdc' +data TARGET_DEVICES_FOR_MIGRATION 'PA4MGL2500_N ' +data RESTRICTPROBEPINS 0 +data RESTRICTSPIPINS 0 +data GDEV_SKIP_UNASSIGN_CMP_CHECK 1 +data HIDE_MIGRATION_PINS_MENU 1 +data IO_DEFT_STD LVCMOS33 + diff --git a/Lab2_VHDL/constraint/placer_sdc_errors.log b/Lab2_VHDL/constraint/placer_sdc_errors.log new file mode 100644 index 0000000..a685e21 --- /dev/null +++ b/Lab2_VHDL/constraint/placer_sdc_errors.log @@ -0,0 +1 @@ +No errors or warnings found. diff --git a/Lab2_VHDL/constraint/run_stce_adl.tcl b/Lab2_VHDL/constraint/run_stce_adl.tcl new file mode 100644 index 0000000..29c0aca --- /dev/null +++ b/Lab2_VHDL/constraint/run_stce_adl.tcl @@ -0,0 +1,6 @@ +set_family {IGLOO2} +set_editor_type {PLACEANDROUTE} +read_adl {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed.adl} +map_netlist +read_sdc {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\LedBlinkingDSpeed_sdc.sdc} +set_output_sdc {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\user.sdc} diff --git a/Lab2_VHDL/constraint/synthesis_sdc_errors.log b/Lab2_VHDL/constraint/synthesis_sdc_errors.log new file mode 100644 index 0000000..a685e21 --- /dev/null +++ b/Lab2_VHDL/constraint/synthesis_sdc_errors.log @@ -0,0 +1 @@ +No errors or warnings found. diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.afl b/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.afl new file mode 100644 index 0000000..2148921 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.afl differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.loc b/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.loc new file mode 100644 index 0000000..896b069 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.loc differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.seg b/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.seg new file mode 100644 index 0000000..4958fd5 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/COMPILE/LedBlinkingDSpeed.seg differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.adl b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.adl new file mode 100644 index 0000000..3ded8c1 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.adl differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.afl b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.afl new file mode 100644 index 0000000..d6ace69 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.afl differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.cfrt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.cfrt new file mode 100644 index 0000000..b853885 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.cfrt differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.dca b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.dca new file mode 100644 index 0000000..6c851e0 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.dca @@ -0,0 +1 @@ +Sunday October 23 03:01:38 2016LedBlinkingDSpeedIGLOO2M2GL025256 VF003ffffffff \ No newline at end of file diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.hdr b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.hdr new file mode 100644 index 0000000..7eed570 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.hdr @@ -0,0 +1 @@ +
1.9100LiberoLedBlinkingDSpeedPA4MGL2500_NPA4MGLPA4vf256M2GL025IGLOO20000STDCOM0047000000000Undef0000000000000000000000000000000000000000000000000000000024924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001truefalsetruefalsetruefalsefalsefalsefalseLedBlinkingDSpeedfalseFLASHPRO_3_4_5SINGLEfalsefalsefalsefalsefalsefalsefalsefalsefalsefalsefalsefalsefalse12.50100PROGRAM
\ No newline at end of file diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.ipd b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.ipd new file mode 100644 index 0000000..aad1738 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.ipd differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.loc b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.loc new file mode 100644 index 0000000..184001b Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.loc differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.map b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.map new file mode 100644 index 0000000..c5c7125 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.map differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.mvn.pdc b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.mvn.pdc new file mode 100644 index 0000000..c02d594 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.mvn.pdc @@ -0,0 +1,37 @@ +# Microsemi Physical design constraints file + +# Version: v11.7 SP1 11.7.1.11 + +# Design Name: + +# Input Netlist Format: EDIF + +# Family: IGLOO2 , Die: M2GL025 , Package: 256 VF , Speed grade: STD + +# Date generated: Sun Oct 23 02:59:39 2016 + + +# +# IO banks setting +# + + +# +# Local clock constraints +# + + +# +# Region constraints +# + + +# +# I/O constraints +# + + +# +# Core cell constraints +# + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.nmatinit.pdc b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.nmatinit.pdc new file mode 100644 index 0000000..2a39b15 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.nmatinit.pdc @@ -0,0 +1,225 @@ +# Microsemi Physical design constraints file + +# Version: v11.7 SP1 11.7.1.11 + +# Design Name: LedBlinkingDSpeed + +# Input Netlist Format: EDIF + +# Family: IGLOO2 , Die: M2GL025 , Package: 256 VF , Speed grade: STD + +# Date generated: Sun Oct 23 03:00:36 2016 + + +# +# I/O constraints +# + +set_io SW1 -DIRECTION INPUT -pinname H12 -fixed no +set_io SW2 -DIRECTION INPUT -pinname H13 -fixed no +set_io clk -DIRECTION INPUT -pinname H16 -fixed no +set_io green_led1 -DIRECTION OUTPUT -pinname J16 -fixed no +set_io green_led2 -DIRECTION OUTPUT -pinname M16 -fixed no +set_io red_led1 -DIRECTION OUTPUT -pinname K16 -fixed no +set_io red_led2 -DIRECTION OUTPUT -pinname N16 -fixed no + +# +# Core cell constraints +# + +set_location Initial_blinking_SW1/cnt\[25\] -fixed no 38 70 +set_location Fast_clk_SW2/un14_cntlto31_0_a2 -fixed no 131 24 +set_location Fast_clk_SW1/cnt\[4\] -fixed no 113 28 +set_location Fast_clk_SW1/cnt\[21\] -fixed no 130 28 +set_location Initial_blinking_SW2/tmp_clk_RNO_0 -fixed no 136 117 +set_location Fast_clk_SW2/cnt\[1\] -fixed no 98 25 +set_location Fast_clk_SW2/cnt\[12\] -fixed no 109 25 +set_location Initial_blinking_SW2/cnt\[26\] -fixed no 162 115 +set_location Initial_blinking_SW1/cnt\[19\] -fixed no 32 70 +set_location Initial_blinking_SW2/cnt_RNI4JC9\[21\] -fixed no 122 114 +set_location Initial_blinking_SW1/un7_cntlto31_0_a3 -fixed no 33 66 +set_location Initial_blinking_SW2/cnt\[19\] -fixed no 143 115 +set_location Fast_clk_SW2/cnt\[23\] -fixed no 120 25 +set_location Fast_clk_SW2/cnt\[19\] -fixed no 116 25 +set_location Initial_blinking_SW1/cnt\[13\] -fixed no 26 70 +set_location Initial_blinking_SW1/cnt\[15\] -fixed no 28 70 +set_location Fast_clk_SW2/cnt\[18\] -fixed no 115 25 +set_location Initial_blinking_SW1/cnt\[22\] -fixed no 35 70 +set_location Fast_clk_SW1/cnt\[14\] -fixed no 123 28 +set_location Initial_blinking_SW2/cnt\[13\] -fixed no 137 115 +set_location Initial_blinking_SW2/tmp_clk -fixed no 117 115 +set_location Initial_blinking_SW2/cnt\[15\] -fixed no 139 115 +set_location Display_out/green_led1 -fixed no 140 28 +set_location Clear_outputs/reset_RNO -fixed no 137 27 +set_location Initial_blinking_SW1/cnt\[24\] -fixed no 37 70 +set_location Fast_clk_SW2/cnt\[25\] -fixed no 122 25 +set_location Initial_blinking_SW1/un14_cntlto31_0_o3_0 -fixed no 29 66 +set_location Fast_clk_SW1/cnt\[23\] -fixed no 132 28 +set_location Fast_clk_SW2/un7_cntlto31_0_a2_0 -fixed no 132 24 +set_location Fast_clk_SW2/un14_cntlto31_0_o3 -fixed no 130 24 +set_location Initial_blinking_SW1/cnt\[0\] -fixed no 13 70 +set_location Initial_blinking_SW2/cnt_RNI4GAR1\[17\] -fixed no 115 114 +set_location Initial_blinking_SW1/cnt\[12\] -fixed no 25 70 +set_location Fast_clk_SW1/un14_cntlto31_0_o2_0 -fixed no 121 30 +set_location Initial_blinking_SW1/cnt\[20\] -fixed no 33 70 +set_location Clear_outputs/reset_RNIREK/U0_RGB1 -fixed no 146 114 +set_location Initial_blinking_SW2/cnt\[12\] -fixed no 136 115 +set_location Initial_blinking_SW1/un7_cntlto31_0_a2_0 -fixed no 26 66 +set_location Fast_clk_SW2/cnt\[20\] -fixed no 117 25 +set_location Fast_clk_SW2/cnt\[11\] -fixed no 108 25 +set_location Initial_blinking_SW2/cnt\[7\] -fixed no 131 115 +set_location Initial_blinking_SW1/cnt\[14\] -fixed no 27 70 +set_location Fast_clk_SW1/cnt\[25\] -fixed no 134 28 +set_location Initial_blinking_SW1/un14_cntlto31_0_a2_1_3 -fixed no 30 66 +set_location Fast_clk_SW2/un7_cntlto31_0_a2_1 -fixed no 143 24 +set_location clk_ibuf_RNIVTI2 -fixed no 293 72 +set_location Initial_blinking_SW2/cnt\[14\] -fixed no 138 115 +set_location Fast_clk_SW2/cnt\[17\] -fixed no 114 25 +set_location Initial_blinking_SW2/tmp_clk_RNO_4 -fixed no 111 114 +set_location Fast_clk_SW1/un14_cntlto31_0_a2_1_3 -fixed no 111 30 +set_location Fast_clk_SW1/un7_cntlto31_0_a2_1 -fixed no 128 30 +set_location Fast_clk_SW1/cnt\[16\] -fixed no 125 28 +set_location Fast_clk_SW2/un7_cntlto31_0_a3 -fixed no 124 24 +set_location Initial_blinking_SW1/un14_cntlto31_0_o3_0_RNI6DVC1 -fixed no 28 66 +set_location Fast_clk_SW1/cnt\[5\] -fixed no 114 28 +set_location Initial_blinking_SW2/cnt\[3\] -fixed no 127 115 +set_location Initial_blinking_SW2/cnt_RNI8JG21\[10\] -fixed no 112 114 +set_location Initial_blinking_SW1/cnt\[10\] -fixed no 23 70 +set_location Fast_clk_SW1/cnt\[20\] -fixed no 129 28 +set_location Clear_outputs/reset -fixed no 137 28 +set_location Fast_clk_SW2/un14_cntlto31_0_o3_0 -fixed no 133 24 +set_location Initial_blinking_SW2/cnt\[10\] -fixed no 134 115 +set_location Fast_clk_SW1/cnt\[0\] -fixed no 109 28 +set_location Fast_clk_SW1/cnt\[2\] -fixed no 111 28 +set_location Fast_clk_SW2/un14_cntlto31_0_o3_0_RNIA4EM1 -fixed no 135 24 +set_location Initial_blinking_SW2/cnt\[21\] -fixed no 157 115 +set_location Initial_blinking_SW1/cnt\[2\] -fixed no 15 70 +set_location Initial_blinking_SW1/cnt\[5\] -fixed no 18 70 +set_location Initial_blinking_SW1/cnt\[6\] -fixed no 19 70 +set_location Fast_clk_SW2/cnt\[13\] -fixed no 110 25 +set_location Fast_clk_SW1/cnt\[12\] -fixed no 121 28 +set_location Fast_clk_SW1/cnt\[6\] -fixed no 115 28 +set_location Initial_blinking_SW2/cnt\[2\] -fixed no 126 115 +set_location Fast_clk_SW2/cnt\[24\] -fixed no 121 25 +set_location Fast_clk_SW1/cnt\[1\] -fixed no 110 28 +set_location Initial_blinking_SW2/cnt\[8\] -fixed no 132 115 +set_location Fast_clk_SW1/cnt\[19\] -fixed no 128 28 +set_location Fast_clk_SW2/cnt\[6\] -fixed no 103 25 +set_location Fast_clk_SW2/cnt\[15\] -fixed no 112 25 +set_location Fast_clk_SW2/un7_cntlto31_0_0 -fixed no 126 24 +set_location Fast_clk_SW1/cnt\[18\] -fixed no 127 28 +set_location Initial_blinking_SW2/cnt\[23\] -fixed no 159 115 +set_location Initial_blinking_SW1/cnt\[3\] -fixed no 16 70 +set_location Initial_blinking_SW2/cnt\[25\] -fixed no 161 115 +set_location Fast_clk_SW1/un7_cntlto31_0_a2_0 -fixed no 129 30 +set_location Fast_clk_SW1/un14_cntlto31_0_o2_3 -fixed no 126 30 +set_location Initial_blinking_SW1/un14_cntlto31_0_o3 -fixed no 31 66 +set_location Fast_clk_SW1/cnt\[24\] -fixed no 133 28 +set_location Fast_clk_SW2/cnt\[10\] -fixed no 107 25 +set_location Initial_blinking_SW2/cnt\[1\] -fixed no 125 115 +set_location ip_interface_inst -fixed no 203 0 +set_location Fast_clk_SW2/un7_cntlto31_0_a2 -fixed no 127 24 +set_location Initial_blinking_SW2/tmp_clk_RNO_1 -fixed no 134 117 +set_location Initial_blinking_SW1/tmp_clk -fixed no 34 67 +set_location Fast_clk_SW2/cnt\[9\] -fixed no 106 25 +set_location Initial_blinking_SW2/cnt\[5\] -fixed no 129 115 +set_location Initial_blinking_SW1/cnt\[26\] -fixed no 39 70 +set_location Initial_blinking_SW2/cnt\[22\] -fixed no 158 115 +set_location Initial_blinking_SW1/cnt\[17\] -fixed no 30 70 +set_location Fast_clk_SW2/cnt\[5\] -fixed no 102 25 +set_location Fast_clk_SW1/cnt\[11\] -fixed no 120 28 +set_location Fast_clk_SW2/cnt\[26\] -fixed no 123 25 +set_location Initial_blinking_SW2/cnt\[17\] -fixed no 141 115 +set_location Initial_blinking_SW1/cnt\[8\] -fixed no 21 70 +set_location Fast_clk_SW1/un7_cntlto31_0_a2 -fixed no 120 30 +set_location Initial_blinking_SW2/cnt\[24\] -fixed no 160 115 +set_location Fast_clk_SW1/cnt\[17\] -fixed no 126 28 +set_location Initial_blinking_SW1/cnt\[4\] -fixed no 17 70 +set_location Display_out/green_led1_4 -fixed no 136 27 +set_location Fast_clk_SW1/cnt\[9\] -fixed no 118 28 +set_location Fast_clk_SW2/un14_cntlto31_0_o2_0 -fixed no 125 24 +set_location Fast_clk_SW1/un14_cntlto31_0_o3_0_RNI3K631 -fixed no 127 30 +set_location Initial_blinking_SW1/cnt\[16\] -fixed no 29 70 +set_location Initial_blinking_SW2/cnt\[20\] -fixed no 156 115 +set_location Initial_blinking_SW2/cnt\[16\] -fixed no 140 115 +set_location Initial_blinking_SW1/un7_cntlto31_0 -fixed no 34 66 +set_location Fast_clk_SW2/cnt\[7\] -fixed no 104 25 +set_location Initial_blinking_SW1/cnt\[7\] -fixed no 20 70 +set_location Fast_clk_SW2/cnt\[22\] -fixed no 119 25 +set_location Display_out/red_led2 -fixed no 135 28 +set_location Fast_clk_SW2/cnt\[14\] -fixed no 111 25 +set_location Fast_clk_SW1/cnt\[13\] -fixed no 122 28 +set_location Initial_blinking_SW2/tmp_clk_RNO_2 -fixed no 132 117 +set_location Fast_clk_SW2/cnt\[0\] -fixed no 97 25 +set_location clk_ibuf_RNIVTI2/U0_RGB1 -fixed no 147 114 +set_location Initial_blinking_SW2/cnt_RNIIH0I1\[12\] -fixed no 114 114 +set_location Fast_clk_SW1/un7_cntlto31_0_a3 -fixed no 123 30 +set_location Initial_blinking_SW1/un14_cntlto31_0_o2_0 -fixed no 24 66 +set_location Fast_clk_SW2/cnt\[8\] -fixed no 105 25 +set_location Initial_blinking_SW2/cnt_RNI9EVA2\[20\] -fixed no 113 114 +set_location Fast_clk_SW1/cnt\[22\] -fixed no 131 28 +set_location Fast_clk_SW1/un7_cntlto31_0_0 -fixed no 122 30 +set_location Initial_blinking_SW1/un14_cntlto31_0_o2_3 -fixed no 27 66 +set_location Fast_clk_SW1/cnt\[15\] -fixed no 124 28 +set_location Display_out/red_led2_3 -fixed no 135 27 +set_location Initial_blinking_SW1/cnt\[1\] -fixed no 14 70 +set_location Initial_blinking_SW2/cnt\[9\] -fixed no 133 115 +set_location Fast_clk_SW1/cnt\[7\] -fixed no 116 28 +set_location Fast_clk_SW1/un14_cntlto31_0_o3 -fixed no 130 30 +set_location flash_freeze_inst/INST_FLASH_FREEZE_IP -fixed no 624 8 +set_location Fast_clk_SW1/un14_cntlto31_0_o3_0 -fixed no 125 30 +set_location Initial_blinking_SW2/tmp_clk_RNO_3 -fixed no 135 117 +set_location Initial_blinking_SW1/cnt\[21\] -fixed no 34 70 +set_location Initial_blinking_SW2/tmp_clk_RNO -fixed no 117 114 +set_location Fast_clk_SW1/cnt\[10\] -fixed no 119 28 +set_location Fast_clk_SW1/un14_cntlto31_0_a2 -fixed no 124 30 +set_location Initial_blinking_SW2/cnt_RNIAQCC\[13\] -fixed no 109 114 +set_location Fast_clk_SW1/cnt\[8\] -fixed no 117 28 +set_location Initial_blinking_SW1/cnt\[18\] -fixed no 31 70 +set_location Fast_clk_SW2/cnt\[16\] -fixed no 113 25 +set_location Fast_clk_SW2/un14_cntlto31_0_a2_1_3 -fixed no 134 24 +set_location Fast_clk_SW2/cnt\[3\] -fixed no 100 25 +set_location Initial_blinking_SW2/cnt\[4\] -fixed no 128 115 +set_location Initial_blinking_SW1/un14_cntlto31_0_a2 -fixed no 25 66 +set_location Initial_blinking_SW2/cnt\[6\] -fixed no 130 115 +set_location Initial_blinking_SW2/cnt\[0\] -fixed no 124 115 +set_location Fast_clk_SW2/cnt\[21\] -fixed no 118 25 +set_location Initial_blinking_SW2/cnt\[18\] -fixed no 142 115 +set_location Initial_blinking_SW1/un7_cntlto31_0_a2 -fixed no 32 66 +set_location Fast_clk_SW2/un14_cntlto31_0_o2_3 -fixed no 128 24 +set_location Fast_clk_SW1/cnt\[3\] -fixed no 112 28 +set_location Initial_blinking_SW1/cnt\[9\] -fixed no 22 70 +set_location Fast_clk_SW2/tmp_clk -fixed no 126 25 +set_location Fast_clk_SW2/cnt\[2\] -fixed no 99 25 +set_location Initial_blinking_SW1/cnt\[11\] -fixed no 24 70 +set_location Initial_blinking_SW2/cnt\[27\] -fixed no 163 115 +set_location Initial_blinking_SW2/cnt\[11\] -fixed no 135 115 +set_location Fast_clk_SW2/cnt\[4\] -fixed no 101 25 +set_location Fast_clk_SW1/tmp_clk -fixed no 136 28 +set_location Clear_outputs/reset_RNIREK -fixed no 297 72 +set_location Initial_blinking_SW1/un7_cntlto31_0_a2_1 -fixed no 35 66 +set_location Initial_blinking_SW1/cnt\[23\] -fixed no 36 70 +set_location Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1 -fixed no 12 69 +set_location Initial_blinking_SW2/cnt_RNIOCCK2\[27\] -fixed no 123 114 +set_location Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2 -fixed no 96 24 +set_location Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32 -fixed no 108 27 +set_location Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1_CC_2 -fixed no 36 71 +set_location Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1_CC_0 -fixed no 12 71 +set_location Initial_blinking_SW2/cnt_RNIOCCK2\[27\]_CC_2 -fixed no 156 116 +set_location Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2_CC_0 -fixed no 96 26 +set_location Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32_CC_0 -fixed no 108 29 +set_location Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1_CC_1 -fixed no 24 71 +set_location Initial_blinking_SW2/cnt_RNIOCCK2\[27\]_CC_1 -fixed no 132 116 +set_location Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2_CC_1 -fixed no 108 26 +set_location Initial_blinking_SW2/cnt_RNIOCCK2\[27\]_CC_0 -fixed no 123 116 +set_location Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32_CC_2 -fixed no 132 29 +set_location Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32_CC_1 -fixed no 120 29 +set_location Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2_CC_2 -fixed no 120 26 +set_location Clear_outputs/reset_RNIREK/U0_RGB1_RGB0 -fixed no 146 69 +set_location Clear_outputs/reset_RNIREK/U0_RGB1_RGB1 -fixed no 146 66 +set_location Clear_outputs/reset_RNIREK/U0_RGB1_RGB2 -fixed no 146 27 +set_location Clear_outputs/reset_RNIREK/U0_RGB1_RGB3 -fixed no 146 24 +set_location clk_ibuf_RNIVTI2/U0_RGB1_RGB0 -fixed no 147 69 +set_location clk_ibuf_RNIVTI2/U0_RGB1_RGB1 -fixed no 147 66 +set_location clk_ibuf_RNIVTI2/U0_RGB1_RGB2 -fixed no 147 27 +set_location clk_ibuf_RNIVTI2/U0_RGB1_RGB3 -fixed no 147 24 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.seg b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.seg new file mode 100644 index 0000000..fd071b8 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.seg differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.smat.seg b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.smat.seg new file mode 100644 index 0000000..fd071b8 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.smat.seg differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.tcml b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.tcml new file mode 100644 index 0000000..d71ca34 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.tcml @@ -0,0 +1 @@ +LedBlinkingDSpeed|clk200 10CLOCK_SRCSDC_USER[get_ports { clk }]PORTclkC:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/place_route.sdc8 \ No newline at end of file diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_bankrpt.rpt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_bankrpt.rpt new file mode 100644 index 0000000..67eaad4 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_bankrpt.rpt @@ -0,0 +1,53 @@ +******************************************************************** +I/O Bank Report - Date: Sun Oct 23 03:01:00 2016 +Product: Designer +Release: v11.7 SP1 +Version: 11.7.1.11 +Design Name: LedBlinkingDSpeed +Family: IGLOO2 +Die: M2GL025 +Package: 256 VF +******************************************************************** + + +I/O Function: + + Type | w/o register | w/ register | w/ DDR register + --------------------------------------|---------------|--------------|---------------- + Input I/O | 3 | 0 | 0 + Output I/O | 4 | 0 | 0 + Bidirectional I/O | 0 | 0 | 0 + Differential Input I/O Pairs | 0 | 0 | 0 + Differential Output I/O Pairs | 0 | 0 | 0 + +I/O Technology: + + | Voltages | I/Os + --------------------------------|-------|-------|-------|--------|-------------- + I/O Standard(s) | Vddi | Vref | Input | Output | Bidirectional + --------------------------------|-------|-------|-------|--------|-------------- + LVCMOS33 | 3.30v | N/A | 3 | 4 | 0 + +I/O Bank Resource Usage: + + | Voltages | Single I/Os | Diff I/O Pairs | Vref I/Os | Type + |-------|-------|------|-------|-------|--------|------|-------|----------|--------- + | Vddi | Vref | Used | Total | Used | Total | Used | Total | Vref Pins| + ------|-------|-------|------|-------|-------|--------|------|-------|----------|--------- + Bank0 | N/A | N/A | 0 | 64 | 0 | 32 | N/A | N/A | N/A | DDRIO + Bank1 | 3.30v | N/A | 2 | 4 | 0 | 0 | N/A | N/A | N/A | MSIO + Bank2 | 3.30v | N/A | 5 | 24 | 0 | 12 | N/A | N/A | N/A | MSIO + Bank3 | N/A | N/A | 0 | 0 | 0 | 0 | N/A | N/A | N/A | JTAG + Bank4 | N/A | N/A | 0 | 28 | 0 | 14 | N/A | N/A | N/A | MSIO + Bank5 | N/A | N/A | 0 | 4 | 0 | 2 | N/A | N/A | N/A | MSIOD + Bank6 | N/A | N/A | 0 | 4 | 0 | 0 | N/A | N/A | N/A | MSIOD + Bank7 | N/A | N/A | 0 | 10 | 0 | 5 | N/A | N/A | N/A | MSIO + +I/O Voltage Usage: + + Voltages | I/Os + -------|-------|------|------- + Vddi | Vref | Used | Total + -------|-------|------|------- + 3.30v | N/A | 7 | 28 + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist.log new file mode 100644 index 0000000..6bfbfc5 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist.log @@ -0,0 +1,22 @@ + +===============================================================================. + +Info: Global design data: + Total globals: 2 + Globals that cannot be demoted: 0 + Globals considered for demotion: 2 + + +Info: List of globals considered for demotion: + CLK ASYN DATA Instance Name + --- ---- ---- ------------- + 115 0 0 'clk_ibuf_RNIVTI2' + 0 114 0 'Clear_outputs/reset_RNIREK' + +Info: Demotion information: +Info: CMPG4-302: Added 0 row global instances. +Info: CMPG4-303: Deleted 0 global instances. + +===============================================================================. + +INFO: No User PDC file(s) was specified. diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_hier_resources.csv b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_hier_resources.csv new file mode 100644 index 0000000..7439b07 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_hier_resources.csv @@ -0,0 +1,9 @@ +Detailed Resource Usage +Module Name,Fabric 4LUT,Fabric DFF,Single-Ended I/O,Chip Globals +Clear_outputs/Primitives,1,1,0,1 +Display_out/Primitives,2,2,0,0 +Fast_clk_SW1/Primitives,39,27,0,0 +Fast_clk_SW2/Primitives,40,28,0,0 +Initial_blinking_SW1/Primitives,40,28,0,0 +Initial_blinking_SW2/Primitives,41,29,0,0 +Primitives/Primitives,0,0,7,1 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_resources.rpt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_resources.rpt new file mode 100644 index 0000000..f68de0b --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_resources.rpt @@ -0,0 +1,173 @@ +Resource Report +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 02:59:39 2016 + +Device Selection ++--------------------------------+----------------+ +| Family | IGLOO2 | +| Device | M2GL025 | +| Package | 256 VF | +| Speed Grade | STD | +| Temp | 0:25:85 | +| Voltage | 1.26:1.20:1.14 | +| Core Voltage | 1.2V | +| Ramp Rate | 100ms Minimum | +| System Controller Suspend Mode | No | +| PLL Supply Voltage | 3.3V | +| Default I/O technology | LVCMOS 3.3V | +| Restrict Probe Pins | No | +| Restrict SPI Pins | No | ++--------------------------------+----------------+ + +Source Files ++---------+-----------------------------------------------------------------------------------------+ +| Topcell | LedBlinkingDSpeed | +| Format | EDIF | +| Source | C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn | ++---------+-----------------------------------------------------------------------------------------+ + +Options ++----------------------------------------------------+-------+ +| Enable Single Event Transient mitigation | false | +| Enable Design Separation Methodology | false | +| Limit the number of high fanout nets to display to | 10 | ++----------------------------------------------------+-------+ + +Resource Usage ++---------------------------+------+-------+------------+ +| Type | Used | Total | Percentage | ++---------------------------+------+-------+------------+ +| 4LUT | 163 | 27696 | 0.59 | +| DFF | 115 | 27696 | 0.42 | +| I/O Register | 0 | 414 | 0.00 | +| User I/O | 7 | 138 | 5.07 | +| -- Single-ended I/O | 7 | 138 | 5.07 | +| -- Differential I/O Pairs | 0 | 65 | 0.00 | +| RAM64x18 | 0 | 34 | 0.00 | +| RAM1K18 | 0 | 31 | 0.00 | +| MACC | 0 | 34 | 0.00 | +| Chip Globals | 2 | 16 | 12.50 | +| CCC | 0 | 6 | 0.00 | +| RCOSC_25_50MHZ | 0 | 1 | 0.00 | +| RCOSC_1MHZ | 0 | 1 | 0.00 | +| XTLOSC | 0 | 1 | 0.00 | +| HPMS | 0 | 1 | 0.00 | ++---------------------------+------+-------+------------+ + +Detailed Logic Resource Usage ++--------------------------+------+-----+ +| Type | 4LUT | DFF | ++--------------------------+------+-----+ +| Fabric Logic | 163 | 115 | +| RAM64x18 Interface Logic | 0 | 0 | +| RAM1K18 Interface Logic | 0 | 0 | +| MACC Interface Logic | 0 | 0 | +| Total Used | 163 | 115 | ++--------------------------+------+-----+ + +Detailed Carry Chains Resource Usage ++--------+------+ +| Length | Used | +| 27 | 1 | +| 28 | 2 | +| 29 | 1 | +| Total | 4 | ++--------+------+ + +I/O Function ++-------------------------------+--------------+-------------+-----------------+ +| Type | w/o register | w/ register | w/ DDR register | ++-------------------------------+--------------+-------------+-----------------+ +| Input I/O | 3 | 0 | 0 | +| Output I/O | 4 | 0 | 0 | +| Bidirectional I/O | 0 | 0 | 0 | +| Differential Input I/O Pairs | 0 | 0 | 0 | +| Differential Output I/O Pairs | 0 | 0 | 0 | ++-------------------------------+--------------+-------------+-----------------+ + +I/O Technology ++--------------+--------+------+-------+--------+---------------+ +| I/O Standard | Vddi | Vref | Input | Output | Bidirectional | ++--------------+--------+------+-------+--------+---------------+ +| LVCMOS33 | 3.30v | N/A | 3 | 4 | 0 | ++--------------+--------+------+-------+--------+---------------+ + +I/O Placement ++----------+-------+------------+ +| Type | Count | Percentage | ++----------+-------+------------+ +| Locked | 0 | 0.00% | +| Placed | 0 | 0.00% | +| UnPlaced | 7 | 100.00% | ++----------+-------+------------+ + +Nets assigned to chip global resources ++--------+---------+--------------------------------------------+ +| Fanout | Type | Name | ++--------+---------+--------------------------------------------+ +| 115 | INT_NET | Net : clk_c | +| | | Driver: clk_ibuf_RNIVTI2/U0_RGB1 | +| | | Source: NETLIST | +| 114 | INT_NET | Net : reset | +| | | Driver: Clear_outputs/reset_RNIREK/U0_RGB1 | +| | | Source: NETLIST | ++--------+---------+--------------------------------------------+ + +Nets assigned to row global resources ++--------+------+------+ +| Fanout | Type | Name | ++--------+------+------+ ++--------+------+------+ + +High fanout nets ++--------+---------+------------------------------------------------------------+ +| Fanout | Type | Name | ++--------+---------+------------------------------------------------------------+ +| 31 | INT_NET | Net : SW2_c | +| | | Driver: SW2_ibuf | +| 30 | INT_NET | Net : SW1_c | +| | | Driver: SW1_ibuf | +| 27 | INT_NET | Net : Initial_blinking_SW2/cnt_RNIOCCK2_Y[27] | +| | | Driver: Initial_blinking_SW2/cnt_RNIOCCK2[27] | +| 26 | INT_NET | Net : Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2_Y | +| | | Driver: Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2 | +| 26 | INT_NET | Net : Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1_Y | +| | | Driver: Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1 | +| 25 | INT_NET | Net : Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32_Y | +| | | Driver: Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32 | +| 4 | INT_NET | Net : Fast_clk_SW2/cnt[23] | +| | | Driver: Fast_clk_SW2/cnt[23] | +| 4 | INT_NET | Net : Fast_clk_SW2/cnt[24] | +| | | Driver: Fast_clk_SW2/cnt[24] | +| 4 | INT_NET | Net : Fast_clk_SW2/cnt[25] | +| | | Driver: Fast_clk_SW2/cnt[25] | +| 4 | INT_NET | Net : Initial_blinking_SW1/cnt[23] | +| | | Driver: Initial_blinking_SW1/cnt[23] | ++--------+---------+------------------------------------------------------------+ + +High fanout nets (through buffer trees) ++--------+---------+------------------------------------------------------------+ +| Fanout | Type | Name | ++--------+---------+------------------------------------------------------------+ +| 31 | INT_NET | Net : SW2_c | +| | | Driver: SW2_ibuf | +| 30 | INT_NET | Net : SW1_c | +| | | Driver: SW1_ibuf | +| 27 | INT_NET | Net : Initial_blinking_SW2/cnt_RNIOCCK2_Y[27] | +| | | Driver: Initial_blinking_SW2/cnt_RNIOCCK2[27] | +| 26 | INT_NET | Net : Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2_Y | +| | | Driver: Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2 | +| 26 | INT_NET | Net : Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1_Y | +| | | Driver: Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1 | +| 25 | INT_NET | Net : Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32_Y | +| | | Driver: Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32 | +| 4 | INT_NET | Net : Fast_clk_SW2/cnt[23] | +| | | Driver: Fast_clk_SW2/cnt[23] | +| 4 | INT_NET | Net : Fast_clk_SW2/cnt[24] | +| | | Driver: Fast_clk_SW2/cnt[24] | +| 4 | INT_NET | Net : Fast_clk_SW2/cnt[25] | +| | | Driver: Fast_clk_SW2/cnt[25] | +| 4 | INT_NET | Net : Initial_blinking_SW1/cnt[23] | +| | | Driver: Initial_blinking_SW1/cnt[23] | ++--------+---------+------------------------------------------------------------+ + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_resources.xml b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_resources.xml new file mode 100644 index 0000000..c4f2e23 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_compile_netlist_resources.xml @@ -0,0 +1,599 @@ + + + +Resource Report +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 02:59:39 2016 + +
Device Selection
+ +
+
+ + Family + IGLOO2 + + + Device + M2GL025 + + + Package + 256 VF + + + Speed Grade + STD + + + Temp + 0:25:85 + + + Voltage + 1.26:1.20:1.14 + + + Core Voltage + 1.2V + + + Ramp Rate + 100ms Minimum + + + System Controller Suspend Mode + No + + + PLL Supply Voltage + 3.3V + + + Default I/O technology + LVCMOS 3.3V + + + Restrict Probe Pins + No + + + Restrict SPI Pins + No + +
+
Source Files
+ +
+
+ + Topcell + LedBlinkingDSpeed + + + Format + EDIF + + + Source + C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn + +
+
Options
+ +
+
+ + Enable Single Event Transient mitigation + false + + + Enable Design Separation Methodology + false + + + Limit the number of high fanout nets to display to + 10 + +
+
Resource Usage
+ +
+ Type + Used + Total + Percentage +
+ + 4LUT + 163 + 27696 + 0.59 + + + DFF + 115 + 27696 + 0.42 + + + I/O Register + 0 + 414 + 0.00 + + + User I/O + 7 + 138 + 5.07 + + + -- Single-ended I/O + 7 + 138 + 5.07 + + + -- Differential I/O Pairs + 0 + 65 + 0.00 + + + RAM64x18 + 0 + 34 + 0.00 + + + RAM1K18 + 0 + 31 + 0.00 + + + MACC + 0 + 34 + 0.00 + + + Chip Globals + 2 + 16 + 12.50 + + + CCC + 0 + 6 + 0.00 + + + RCOSC_25_50MHZ + 0 + 1 + 0.00 + + + RCOSC_1MHZ + 0 + 1 + 0.00 + + + XTLOSC + 0 + 1 + 0.00 + + + HPMS + 0 + 1 + 0.00 + +
+
Detailed Logic Resource Usage
+ +
+ Type + 4LUT + DFF +
+ + Fabric Logic + 163 + 115 + + + RAM64x18 Interface Logic + 0 + 0 + + + RAM1K18 Interface Logic + 0 + 0 + + + MACC Interface Logic + 0 + 0 + + + Total Used + 163 + 115 + +
+
Detailed Carry Chains Resource Usage
+ +
+
+ + Length + Used + + + 27 + 1 + + + 28 + 2 + + + 29 + 1 + + + Total + 4 + +
+
I/O Function
+ +
+ Type + w/o register + w/ register + w/ DDR register +
+ + Input I/O + 3 + 0 + 0 + + + Output I/O + 4 + 0 + 0 + + + Bidirectional I/O + 0 + 0 + 0 + + + Differential Input I/O Pairs + 0 + 0 + 0 + + + Differential Output I/O Pairs + 0 + 0 + 0 + +
+
I/O Technology
+ +
+ I/O Standard + Vddi + Vref + Input + Output + Bidirectional +
+ + LVCMOS33 + 3.30v + N/A + 3 + 4 + 0 + +
+
I/O Placement
+ +
+ Type + Count + Percentage +
+ + Locked + 0 + 0.00% + + + Placed + 0 + 0.00% + + + UnPlaced + 7 + 100.00% + +
+
Nets assigned to chip global resources
+ +
+ Fanout + Type + Name +
+ + 115 + INT_NET + Net : clk_c + + + + + Driver: clk_ibuf_RNIVTI2/U0_RGB1 + + + + + Source: NETLIST + + + 114 + INT_NET + Net : reset + + + + + Driver: Clear_outputs/reset_RNIREK/U0_RGB1 + + + + + Source: NETLIST + +
+
Nets assigned to row global resources
+ +
+ Fanout + Type + Name +
+
+
High fanout nets
+ +
+ Fanout + Type + Name +
+ + 31 + INT_NET + Net : SW2_c + + + + + Driver: SW2_ibuf + + + 30 + INT_NET + Net : SW1_c + + + + + Driver: SW1_ibuf + + + 27 + INT_NET + Net : Initial_blinking_SW2/cnt_RNIOCCK2_Y[27] + + + + + Driver: Initial_blinking_SW2/cnt_RNIOCCK2[27] + + + 26 + INT_NET + Net : Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2_Y + + + + + Driver: Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2 + + + 26 + INT_NET + Net : Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1_Y + + + + + Driver: Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1 + + + 25 + INT_NET + Net : Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32_Y + + + + + Driver: Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32 + + + 4 + INT_NET + Net : Fast_clk_SW2/cnt[23] + + + + + Driver: Fast_clk_SW2/cnt[23] + + + 4 + INT_NET + Net : Fast_clk_SW2/cnt[24] + + + + + Driver: Fast_clk_SW2/cnt[24] + + + 4 + INT_NET + Net : Fast_clk_SW2/cnt[25] + + + + + Driver: Fast_clk_SW2/cnt[25] + + + 4 + INT_NET + Net : Initial_blinking_SW1/cnt[23] + + + + + Driver: Initial_blinking_SW1/cnt[23] + +
+
High fanout nets (through buffer trees)
+ +
+ Fanout + Type + Name +
+ + 31 + INT_NET + Net : SW2_c + + + + + Driver: SW2_ibuf + + + 30 + INT_NET + Net : SW1_c + + + + + Driver: SW1_ibuf + + + 27 + INT_NET + Net : Initial_blinking_SW2/cnt_RNIOCCK2_Y[27] + + + + + Driver: Initial_blinking_SW2/cnt_RNIOCCK2[27] + + + 26 + INT_NET + Net : Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2_Y + + + + + Driver: Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2 + + + 26 + INT_NET + Net : Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1_Y + + + + + Driver: Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1 + + + 25 + INT_NET + Net : Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32_Y + + + + + Driver: Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32 + + + 4 + INT_NET + Net : Fast_clk_SW2/cnt[23] + + + + + Driver: Fast_clk_SW2/cnt[23] + + + 4 + INT_NET + Net : Fast_clk_SW2/cnt[24] + + + + + Driver: Fast_clk_SW2/cnt[24] + + + 4 + INT_NET + Net : Fast_clk_SW2/cnt[25] + + + + + Driver: Fast_clk_SW2/cnt[25] + + + 4 + INT_NET + Net : Initial_blinking_SW1/cnt[23] + + + + + Driver: Initial_blinking_SW1/cnt[23] + +
+ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_coverage_pr.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_coverage_pr.log new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp.tcl new file mode 100644 index 0000000..ef44278 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp.tcl @@ -0,0 +1,13 @@ +new_project \ + -name {LedBlinkingDSpeed} \ + -location {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_fp} \ + -mode {chain} \ + -connect_programmers {FALSE} +add_actel_device \ + -device {M2GL025} \ + -name {M2GL025} +enable_device \ + -name {M2GL025} \ + -enable {TRUE} +save_project +close_project diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed.pro b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed.pro new file mode 100644 index 0000000..78479eb --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed.pro @@ -0,0 +1,100 @@ + + + C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_fp + + + ChainView + + + M2GL025 + + + C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_fp\LedBlinkingDSpeed.log + + + Skip + + + + E200WJY28 + + + E200WJY28 + + + + + + + 4000000 + + + + + +2500 + + + + 4000000 + + + + + + + 4000000 + + + + FreeRunningClk + + + + + 4000000 + + + + FreeRunningClk + + + + + 4000000 + + + + FreeRunningClk + + + JTAGMode + + + + + + M2GL025 + + + M2GL025 + + + + 8 + + + 10000000 + + + + + + 0 + + + 0 + + + + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed.tcl new file mode 100644 index 0000000..cc9bfc1 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed.tcl @@ -0,0 +1,8 @@ +open_project -project {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_fp\LedBlinkingDSpeed.pro} +set_programming_file -name {M2GL025} -file {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed.ipd} +enable_device -name {M2GL025} -enable 1 +set_programming_action -action {PROGRAM} -name {M2GL025} +run_selected_actions +set_programming_file -name {M2GL025} -no_file +save_project +close_project diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed_PROGRAM.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed_PROGRAM.log new file mode 100644 index 0000000..378291b --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed_PROGRAM.log @@ -0,0 +1,42 @@ +Software Version: 11.7.1.11 +Embedded FlashPro5 programmer detected. +programmer 'E200WJY28' : FlashPro5 +Opened 'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_fp\LedBlinkingDSpeed.pro' +The 'open_project' command succeeded. +IPD file 'C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed.ipd' has been loaded successfully. +DESIGN : LedBlinkingDSpeed; CHECKSUM : 8F38; PDB_VERSION : 1.9 +The 'set_programming_file' command succeeded. +Warning: Programming is already enabled for device 'M2GL025'. +The 'enable_device' command succeeded. +The 'set_programming_action' command succeeded. +programmer 'E200WJY28' : Scan Chain... +Warning: programmer 'E200WJY28' : Vpump has been selected on programmer AND an externally provided Vpump has also been detected. Using externally provided Vpump voltage source. +programmer 'E200WJY28' : Check Chain... +programmer 'E200WJY28' : Scan and Check Chain PASSED. +programmer 'E200WJY28' : device 'M2GL025' : Executing action PROGRAM +programmer 'E200WJY28' : device 'M2GL025' : Family: Igloo2 +programmer 'E200WJY28' : device 'M2GL025' : Product: M2GL025 +programmer 'E200WJY28' : device 'M2GL025' : EXPORT ISC_ENABLE_RESULT[32] = 00786744 +programmer 'E200WJY28' : device 'M2GL025' : EXPORT CRCERR: [1] = 0 +programmer 'E200WJY28' : device 'M2GL025' : EXPORT EDCERR: [1] = 0 +programmer 'E200WJY28' : device 'M2GL025' : TEMPGRADE: ROOM +programmer 'E200WJY28' : device 'M2GL025' : EXPORT VPPRANGE: [3] = 2 +programmer 'E200WJY28' : device 'M2GL025' : VPPRANGE: HIGH +programmer 'E200WJY28' : device 'M2GL025' : EXPORT TEMP: [8] = 67 +programmer 'E200WJY28' : device 'M2GL025' : EXPORT VPP: [8] = 78 +programmer 'E200WJY28' : device 'M2GL025' : Programming FPGA Array... +programmer 'E200WJY28' : device 'M2GL025' : =================================================================================== +programmer 'E200WJY28' : device 'M2GL025' : EXPORT DSN[128] = 647854d7146932d9ca6798f35286b3f4 +programmer 'E200WJY28' : device 'M2GL025' : =================================================================================== +programmer 'E200WJY28' : device 'M2GL025' : Finished: Sun Oct 23 03:03:03 2016 (Elapsed time 00:00:38) +programmer 'E200WJY28' : device 'M2GL025' : Executing action PROGRAM PASSED. +programmer 'E200WJY28' : Chain programming PASSED. +Chain Programming Finished: Sun Oct 23 03:03:03 2016 (Elapsed time 00:00:38) + + o - o - o - o - o - o + +The 'run_selected_actions' command succeeded. +The 'set_programming_file' command succeeded. +Project saved. +The 'save_project' command succeeded. +Project closed. diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed_generateBitstream.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed_generateBitstream.log new file mode 100644 index 0000000..f5cb853 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_fp/LedBlinkingDSpeed_generateBitstream.log @@ -0,0 +1,10 @@ +Software Version: 11.7.1.11 +Opened 'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_fp\LedBlinkingDSpeed.pro' +The 'open_project' command succeeded. +PDB file 'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\e3c708ff-89b9-4f77-89b9-ff7789b9ff77.pdb' has been loaded successfully. +DESIGN : LedBlinkingDSpeed; CHECKSUM : 8F38; PDB_VERSION : 1.9 +The 'load_programming_data' command succeeded. +The 'set_programming_file' command succeeded. +Project saved. +The 'save_project' command succeeded. +Project closed. diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_glb_net_report.xml b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_glb_net_report.xml new file mode 100644 index 0000000..bbcfa9d --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_glb_net_report.xml @@ -0,0 +1,217 @@ + + + +Global Net Report +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 03:00:36 2016 + +
+Global Nets Information + +
+ + From + GB Location + Net Name + Fanout +
+ + 1 + GB[3] + (293, 72) + clk_ibuf_RNIVTI2/U0_YWn + 115 + + + 2 + GB[7] + (297, 72) + Clear_outputs/reset_RNIREK/U0_YWn + 114 + +
+ +
+
+I/O to GB Connections + +
+ + Port Name + Pin Number + I/O Function + From + From Location + To + Net Name + Net Type + Fanout +
+ + 1 + clk + H16 + MSIO11NB2/CCC_NE1_CLKI0 + clk_ibuf/U0/U_IOIN:Y + East IO #1 (627, 28) + GB[3] + clk_ibuf + ROUTED + 1 + +
+ +
+
+Fabric to GB Connections + +
+ + From + From Location + To + Net Name + Net Type + Fanout +
+ + 1 + Clear_outputs/reset:Q + (137, 28) + GB[7] + Clear_outputs/reset_0 + ROUTED + 1 + +
+ +
+
+CCC to GB Connections +(none) +
+
+CCC Input Connections +(none) +
+
+Local Clock Nets to RGB Connections +(none) +
+
+Global Clock Nets to RGB Connections + +
+ + From + From Location + Net Name + Fanout + + RGB Location + Local Fanout +
+ + 1 + GB[3] + (293, 72) + clk_ibuf_RNIVTI2/U0_YWn + 115 + 1 + (147, 24) + 28 + + + + + + + + 2 + (147, 27) + 30 + + + + + + + + 3 + (147, 66) + 1 + + + + + + + + 4 + (147, 69) + 27 + + + + + + + + 5 + (147, 114) + 29 + + + 2 + GB[7] + (297, 72) + Clear_outputs/reset_RNIREK/U0_YWn + 114 + 1 + (146, 24) + 28 + + + + + + + + 2 + (146, 27) + 29 + + + + + + + + 3 + (146, 66) + 1 + + + + + + + + 4 + (146, 69) + 27 + + + + + + + + 5 + (146, 114) + 29 + +
+ +
+ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_has_io_constraints b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_has_io_constraints new file mode 100644 index 0000000..da5cfd5 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_has_io_constraints @@ -0,0 +1 @@ +IO_CONSTRAINT_PRESENT \ No newline at end of file diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config.txt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config.txt new file mode 100644 index 0000000..8ddb33e --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config.txt @@ -0,0 +1,4 @@ +Configuration Report for MSS, SERDES(s), Fabric DDR and Fabric CCC(s) +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 03:01:16 2016 + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config.xml b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config.xml new file mode 100644 index 0000000..a61a8a6 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config.xml @@ -0,0 +1,8 @@ + + + +Configuration Report for MSS, SERDES(s), Fabric DDR and Fabric CCC(s) +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 03:01:16 2016 + + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config_lock_bits.txt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config_lock_bits.txt new file mode 100644 index 0000000..b740423 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_init_config_lock_bits.txt @@ -0,0 +1,4 @@ +# Register Lock Bits Configuration File for MSS, SERDES(s) and Fabric DDR +# Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +# Date: Sun Oct 23 03:01:16 2016 + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_inst.db b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_inst.db new file mode 100644 index 0000000..802db2c Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_inst.db differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_ioff.rpt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_ioff.rpt new file mode 100644 index 0000000..e3a725d --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_ioff.rpt @@ -0,0 +1,12 @@ +I/O Register Combining Report +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 03:01:00 2016 + +I/O Register Combining Summary ++ ++ + +I/O DDR Register Combining Summary ++ ++ + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_ioff.xml b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_ioff.xml new file mode 100644 index 0000000..11842ff --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_ioff.xml @@ -0,0 +1,18 @@ + + + +I/O Register Combining Report +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 03:01:00 2016 + +
I/O Register Combining Summary
+ +
+
+
+
I/O DDR Register Combining Summary
+ +
+
+
+ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_layout_combinational_loops.xml b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_layout_combinational_loops.xml new file mode 100644 index 0000000..cfda5b4 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_layout_combinational_loops.xml @@ -0,0 +1,61 @@ + + + +Combinational Loop Report +SmartTime Version 11.7.1.11 +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 03:00:15 2016 + + +
+
+ + Design + LedBlinkingDSpeed + + + Family + IGLOO2 + + + Die + M2GL025 + + + Package + 256 VF + + + Temperature Range + 0 - 85 C + + + Voltage Range + 1.14 - 1.26 V + + + Speed Grade + STD + + + Design State + Pre-Layout + + + Analysis Min Case + BEST - 1.26 V - 0 C + + + Analysis Max Case + WORST - 1.14 V - 85 C + + + Scenario for Timing Analysis + place_and_route + +
+ + + +No combinational loops were detected in the design. + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_layout_log.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_layout_log.log new file mode 100644 index 0000000..62760c9 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_layout_log.log @@ -0,0 +1,61 @@ +No errors or warnings found. +***** Place and Route Configurations ***** +Timing-driven : ON +Power-driven : OFF +High-effort : OFF +Repair min-delay : ON +Incremental : OFF +Inter-clock optimization : ON +TDPR scenario : place_and_route + +INFO: Reading User PDC file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\io\LedBlinkingDSpeed.io.pdc. 0 error(s) and 0 warning(s) + +Running the I/O Bank and Globals Assigner. +Info: I/O Bank and Globals Assigner identified 7 fixed I/O macros, 0 unfixed I/O macros + +I/O Bank and Globals Assigner completed successfully. +Total time spent in I/O Bank and Globals Assigner: 0 seconds + +Placer V4.0 - 11.7.1 +Design: LedBlinkingDSpeed Started: Sun Oct 23 03:00:17 2016 + +Initializing Timing-Driven Placement ... +Placing design... +End of placement. +Pre-Placement Runtime : 1 seconds +Placement Runtime : 2 seconds + +Placer completed successfully. + +Design: LedBlinkingDSpeed +Finished: Sun Oct 23 03:00:36 2016 +Total CPU Time: 00:00:17 Total Elapsed Time: 00:00:19 +Total Memory Usage: 351.1 Mbytes + o - o - o - o - o - o + + +Router +Design: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeedStarted: Sun Oct 23 03:00:38 2016 + + +Router completed successfully. + +Design: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed +Finished: Sun Oct 23 03:00:50 2016 +Total CPU Time: 00:00:11 Total Elapsed Time: 00:00:12 +Total Memory Usage: 1022.8 Mbytes + o - o - o - o - o - o + +Info: Iteration 1: + Number of violating paths: 0 + Worst minimum delay slack: +Resource Usage ++---------------+------+-------+------------+ +| Type | Used | Total | Percentage | ++---------------+------+-------+------------+ +| 4LUT | 163 | 27696 | 0.59 | +| DFF | 115 | 27696 | 0.42 | +| I/O Register | 0 | 414 | 0.00 | +| Logic Element | 164 | 27696 | 0.59 | ++---------------+------+-------+------------+ + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_mindelay_repair_report.rpt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_mindelay_repair_report.rpt new file mode 100644 index 0000000..34dbd79 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_mindelay_repair_report.rpt @@ -0,0 +1,29 @@ +------------------------------------- + External Hold Repair Report +------------------------------------- + Iteration 1 + Total I/O input ports improved: 0 +------------------------------------- + + + +------------------------- + Min-delay Repair Report +------------------------- + Iteration 1 + Total paths found: 0 + Total paths improved: 0 +------------------------- + + +Note: + [1]: A net cannot be modified for repair if: + - it is hardwired, preserved, or global; + - the sink pin is a clock pin; + - the sink pin has negative max-delay slack allowance; + - the sink and driving pins are placed in the same cluster. + + [2]: A location is not feasible for inserting a delay buffer if the estimated minimum delay to be inserted might exceed the max-delay slack allowance of the sink pin. + + + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_partition.dat b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_partition.dat new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_datasheet.rpt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_datasheet.rpt new file mode 100644 index 0000000..5741e38 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_datasheet.rpt @@ -0,0 +1,20 @@ +***************************************************************** +Pin Report - Date: Sun Oct 23 03:01:00 2016 Pinchecksum: NOT-AVAILABLE +Product: Designer +Release: v11.7 SP1 +Version: 11.7.1.11 +Design Name: LedBlinkingDSpeed +Family: IGLOO2 +Die: M2GL025 +Package: 256 VF +***************************************************************** + +Port |Pin |Fixed |Function |Bank |I/O Std |Direction |I/O state in Flash*Freeze mode |Resistor Pull |I/O available in Flash*Freeze mode |Schmitt Trigger |Odt_Static |Odt Imp (Ohm) |Low Power Exit |Input Delay |Slew |Pre-Emphasis |Output Drive (mA) |Output Load (pF) | +-----------|----|------|-------------------------|---------|----------|-------------------------------|-------------------------------|-----------------------------------|-----------------------------------|----------------|--------------|---------------|---------------|------------|-------------|------------------|------------------|-----------------| +clk H16 Yes MSIO11NB2/CCC_NE1_CLKI0 Bank2 LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- +green_led1 J16 Yes MSIO11PB2//CCC_NE0_CLKI0 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +green_led2 M16 Yes MSIO1NB2 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +red_led1 K16 Yes MSIO4PB2 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +red_led2 N16 Yes MSIO1PB2 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +SW1 H12 Yes MSI27NB1 Bank1 LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- +SW2 H13 Yes MSIO28NB1 Bank1 LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_name.rpt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_name.rpt new file mode 100644 index 0000000..5741e38 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_name.rpt @@ -0,0 +1,20 @@ +***************************************************************** +Pin Report - Date: Sun Oct 23 03:01:00 2016 Pinchecksum: NOT-AVAILABLE +Product: Designer +Release: v11.7 SP1 +Version: 11.7.1.11 +Design Name: LedBlinkingDSpeed +Family: IGLOO2 +Die: M2GL025 +Package: 256 VF +***************************************************************** + +Port |Pin |Fixed |Function |Bank |I/O Std |Direction |I/O state in Flash*Freeze mode |Resistor Pull |I/O available in Flash*Freeze mode |Schmitt Trigger |Odt_Static |Odt Imp (Ohm) |Low Power Exit |Input Delay |Slew |Pre-Emphasis |Output Drive (mA) |Output Load (pF) | +-----------|----|------|-------------------------|---------|----------|-------------------------------|-------------------------------|-----------------------------------|-----------------------------------|----------------|--------------|---------------|---------------|------------|-------------|------------------|------------------|-----------------| +clk H16 Yes MSIO11NB2/CCC_NE1_CLKI0 Bank2 LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- +green_led1 J16 Yes MSIO11PB2//CCC_NE0_CLKI0 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +green_led2 M16 Yes MSIO1NB2 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +red_led1 K16 Yes MSIO4PB2 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +red_led2 N16 Yes MSIO1PB2 Bank2 LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +SW1 H12 Yes MSI27NB1 Bank1 LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- +SW2 H13 Yes MSIO28NB1 Bank1 LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_number.rpt b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_number.rpt new file mode 100644 index 0000000..350b151 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pinrpt_number.rpt @@ -0,0 +1,269 @@ +***************************************************************** +Pin Report - Date: Sun Oct 23 03:01:00 2016 Pinchecksum: NOT-AVAILABLE +Product: Designer +Release: v11.7 SP1 +Version: 11.7.1.11 +Design Name: LedBlinkingDSpeed +Family: IGLOO2 +Die: M2GL025 +Package: 256 VF +***************************************************************** + +Number |Port |Function |State |I/O Std |Direction |I/O state in Flash*Freeze mode |Resistor Pull |I/O available in Flash*Freeze mode |Schmitt Trigger |Odt_Static |Odt Imp (Ohm) |Low Power Exit |Input Delay |Slew |Pre-Emphasis |Output Drive (mA) |Output Load (pF) | +-------|-----------|----------------------------------------|-----------|---------|----------|-------------------------------|--------------|-----------------------------------|----------------|-----------|--------------|---------------|------------|-----|-------------|------------------|-----------------| +A1 VDDI0 Reserved +A2 DDRIO60NB0/MDDR_DQ1 Unassigned +A3 DDRIO57PB0/MDDR_DM_RDQS0 Unassigned +A4 DDRIO58NB0/MDDR_DQS0_N Unassigned +A5 DDRIO58PB0/MDDR_DQS0 Unassigned +A6 VSS Reserved +A7 DDRIO55PB0/MDDR_DQ7 Unassigned +A8 DDRIO55NB0/MDDR_TMATCH_0_OUT Unassigned +A9 DDRIO52PB0/MDDR_DQS1/GB8/CCC_NE0_CLKI3 Special +A10 DDRIO52NB0/MDDR_DQS1_N Unassigned +A11 VDDI0 Reserved +A12 DDRIO46NB0/MDDR_CAS_N Unassigned +A13 DDRIO46PB0/MDDR_RESET_N Unassigned +A14 DDRIO45PB0/MDDR_CLK Unassigned +A15 DDRIO45NB0/MDDR_CLK_N Unassigned +A16 VSS Reserved +B1 DDRIO64NB0/MDDR_DQS_ECC_N Unassigned +B2 DDRIO60PB0/MDDR_DQ0 Unassigned +B3 DDRIO57NB0/MDDR_DQ4 Unassigned +B4 VDDI0 Reserved +B5 DDRIO59NB0/MDDR_DQ3 Unassigned +B6 DDRIO59PB0/MDDR_DQ2 Unassigned +B7 DDRIO56PB0/MDDR_DQ5 Unassigned +B8 DDRIO51PB0/MDDR_TMATCH_0_IN Unassigned +B9 VSS Reserved +B10 DDRIO50NB0/MDDR_DQ13 Unassigned +B11 DDRIO50PB0/MDDR_DQ12/GB12/CCC_NE1_CLKI2 Special +B12 DDRIO48PB0/MDDR_RAS_N Unassigned +B13 DDRIO43PB0/MDDR_BA2 Unassigned +B14 VDDI0 Reserved +B15 DDRIO35NB0/MDDR_ADDR15 Unassigned +B16 DDRIO41PB0/MDDR_ADDR3 Unassigned +C1 DDRIO64PB0/MDDR_DQS_ECC Unassigned +C2 VSS Reserved +C3 DDRIO63NB0/MDDR_DM_RDQS_ECC Unassigned +C4 DDRIO63PB0/MDDR_TMATCH_ECC_IN Unassigned +C5 DDRIO62PB0/MDDR_DQ_ECC3 Unassigned +C6 DDRIO56NB0/MDDR_DQ6 Unassigned +C7 VDDI0 Reserved +C8 DDRIO54PB0/MDDR_DQ8 Unassigned +C9 DDRIO54NB0/MDDR_DQ9 Unassigned +C10 DDRIO51NB0/MDDR_DM_RDQS1 Unassigned +C11 DDRIO48NB0/MDDR_WE_N Unassigned +C12 DDRIO44PB0/MDDR_BA0 Unassigned +C13 VSS Reserved +C14 DDRIO43NB0/MDDR_ADDR0 Unassigned +C15 DDRIO35PB0/MDDR_ADDR14 Unassigned +C16 DDRIO41NB0/MDDR_ADDR4 Unassigned +D1 DDRIO61PB0/CCC_NW1_CLKI3 Special +D2 DDRIO61NB0 Unassigned +D3 DDRIO66PB0/MDDR_TMATCH_ECC_OUT Unassigned +D4 DDRIO65PB0/GB0/CCC_NW0_CLKI3 Special +D5 VSS Reserved +D6 DDRIO62NB0/MDDR_DQ_ECC2 Unassigned +D7 DDRIO53PB0/MDDR_DQ10/CCC_NE0_CLKI2 Special +D8 DDRIO53NB0/MDDR_DQ11 Unassigned +D9 DDRIO49PB0/MDDR_DQ14/CCC_NE1_CLKI3 Special +D10 VDDI0 Reserved +D11 DDRIO47NB0/MDDR_CS_N Unassigned +D12 DDRIO44NB0/MDDR_BA1 Unassigned +D13 DDRIO36NB0/MDDR_ADDR13 Unassigned +D14 DDRIO36PB0/MDDR_ADDR12 Unassigned +D15 VSS Reserved +D16 DDRIO40PB0/MDDR_ADDR5 Unassigned +E1 MDDR_IMP_CALIB Reserved +E2 DDRIO66NB0/CCC_NW0_CLKI2 Special +E3 VDDI0 Reserved +E4 DDRIO65NB0/GB4/CCC_NW1_CLKI2 Special +E5 CCC_NW0_NW1_PLL_VSSA Reserved +E6 CCC_NW0_NW1_PLL_VDDA Reserved +E7 VREF0 Reserved +E8 DDRIO49NB0/MDDR_DQ15 Unassigned +E9 VREF0 Reserved +E10 DDRIO47PB0/MDDR_CKE Unassigned +E11 DDRIO42PB0/MDDR_ADDR1 Unassigned +E12 DDRIO42NB0/MDDR_ADDR2 Unassigned +E13 VDDI0 Reserved +E14 DDRIO37PB0/MDDR_ADDR10 Unassigned +E15 DDRIO38NB0/MDDR_ADDR9 Unassigned +E16 DDRIO40NB0/MDDR_ADDR6 Unassigned +F1 VSS Reserved +F2 MSIO97NB7 Unassigned +F3 MSIO96NB7 Unassigned +F4 MSIO96PB7/GB6/CCC_NW1_CLKI1 Special +F5 MSIO95NB7 Unassigned +F6 VDDI7 Reserved +F7 VSS Reserved +F8 VDDI0 Reserved +F9 VSS Reserved +F10 VDDI0 Reserved +F11 CCC_NE0_NE1_HPMS_MDDR_PLL_VDDA Reserved +F12 CCC_NE0_NE1_HPMS_MDDR_PLL_VSSA Reserved +F13 DDRIO37NB0/MDDR_ADDR11 Unassigned +F14 DDRIO38PB0/MDDR_ADDR8 Unassigned +F15 DDRIO39NB0/MDDR_ADDR7 Unassigned +F16 DDRIO39PB0/MDDR_ODT Unassigned +G1 MSIO97PB7/GB2/CCC_NW0_CLKI1 Special +G2 MSIO98NB7 Unassigned +G3 MSIO98PB7/CCC_NW1_CLKI0 Special +G4 VSS Reserved +G5 MSIO95PB7 Unassigned +G6 VSS Reserved +G7 VDD Reserved +G8 VSS Reserved +G9 VDD Reserved +G10 VSS Reserved +G11 VDDI1 Reserved +G12 MSIO32NB1 Unassigned +G13 MSIO33PB1 Unassigned +G14 MSIO15NB2 Unassigned +G15 VSS Reserved +G16 MSIO14NB2 Unassigned +H1 MSIOD103PB6/CCC_SW0_CLKI0 Special +H2 VDDI7 Reserved +H3 MSIO99PB7/CCC_NW0_CLKI0 Special +H4 MSIO99NB7 Unassigned +H5 MSIOD100PB6/GB5/CCC_SW1_CLKI1 Special +H6 VDDI6 Reserved +H7 VSS Reserved +H8 VDD Reserved +H9 VSS Reserved +H10 VPP Reserved +H11 FLASH_GOLDEN_N Reserved +H12 SW1 MSI27NB1 Fixed LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- +H13 SW2 MSIO28NB1 Fixed LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- +H14 MSIO15PB2 Unassigned +H15 MSIO14PB2 Unassigned +H16 clk MSIO11NB2/CCC_NE1_CLKI0 Special LVCMOS33 Input TRISTATE None No Off --- --- Off Off --- --- --- --- +J1 MSIOD118PB5 Unassigned +J2 MSIOD118NB5 Unassigned +J3 MSIOD102PB6/CCC_SW1_CLKI0 Special +J4 VSS Reserved +J5 MSIOD101PB6/GB1/CCC_SW0_CLKI1 Special +J6 VSS Reserved +J7 VDD Reserved +J8 VSS Reserved +J9 VDD Reserved +J10 VSS Reserved +J11 VDDI2 Reserved +J12 MSIO13NB2/SPI_0_SS0 Unassigned +J13 MSIO12NB2/SPI_0_SDI Unassigned +J14 MSIO12PB2/SPI_0_CLK Unassigned +J15 VDDI2 Reserved +J16 green_led1 MSIO11PB2//CCC_NE0_CLKI0 Special LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +K1 MSIOD119NB5 Unassigned +K2 VDDI5 Reserved +K3 DNC Reserved +K4 VSS Reserved +K5 VPP Reserved +K6 CCC_SW0_SW1_PLL_VSSA Reserved +K7 VSS Reserved +K8 VDD Reserved +K9 VSS Reserved +K10 VDD Reserved +K11 VPPNVM Reserved +K12 MSIO13PB2/SPI_0_SDO Unassigned +K13 VSS Reserved +K14 MSIO6PB2 Unassigned +K15 MSIO6NB2 Unassigned +K16 red_led1 MSIO4PB2 Fixed LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +L1 MSIOD119PB5 Unassigned +L2 DNC Reserved +L3 VDD Reserved +L4 VSS Reserved +L5 CCC_SW0_SW1_PLL_VDDA Reserved +L6 VSS Reserved +L7 VDD Reserved +L8 VSS Reserved +L9 VPP Reserved +L10 VSSNVM Reserved +L11 MSIO3PB2 Unassigned +L12 MSIO3NB2 Unassigned +L13 MSIO5NB2 Unassigned +L14 MSIO5PB2 Unassigned +L15 MSIO4NB2 Unassigned +L16 VSS Reserved +M1 VSS Reserved +M2 VSS Reserved +M3 VSS Reserved +M4 VDD Reserved +M5 VDD Reserved +M6 VDD Reserved +M7 MSIO125PB4/GB3/CCC_SW0_CLKI3 Special +M8 MSIO129NB4 Unassigned +M9 MSIO132PB4 Unassigned +M10 MSIO132NB4 Unassigned +M11 DEVRST_N Reserved +M12 JTAGSEL Reserved +M13 MSIO2NB2 Unassigned +M14 VDDI2 Reserved +M15 MSIO0PB2 Unassigned +M16 green_led2 MSIO1NB2 Fixed LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +N1 VSS Reserved +N2 VSS Reserved +N3 VSS Reserved +N4 VSS Reserved +N5 VDD Reserved +N6 VSS Reserved +N7 MSIO125NB4/GB7/CCC_SW1_CLKI2 Special +N8 MSIO129PB4/CCC_SW1_CLKI3 Special +N9 VSS Reserved +N10 MSIO133NB4 Unassigned +N11 JTAG_TMS Reserved +N12 VDDI3 Reserved +N13 JTAG_TRSTB Reserved +N14 MSIO2PB2 Unassigned +N15 MSIO0NB2 Unassigned +N16 red_led2 MSIO1PB2 Fixed LVCMOS33 Output TRISTATE None No --- --- --- --- --- --- --- 4 5 +P1 VSS Reserved +P2 VSS Reserved +P3 VSS Reserved +P4 VSS Reserved +P5 VSS Reserved +P6 MSIO121PB4/PROBE_A Unassigned +P7 MSIO121NB4/PROBE_B Unassigned +P8 MSIO126NB4 Unassigned +P9 MSIO131PB4/GB11/VCCC_SE0_CLKI Special +P10 MSIO133PB4/GB15/VCCC_SE1_CLKI Special +P11 VDDI4 Reserved +P12 MSIO143PB4 Unassigned +P13 MSIO143NB4 Unassigned +P14 JTAG_TDO Reserved +P15 VSS Reserved +P16 JTAG_TDI Reserved +R1 VSS Reserved +R2 DNC Reserved +R3 VSS Reserved +R4 DNC Reserved +R5 VSS Reserved +R6 MSIO120PB4 Unassigned +R7 VDDI4 Reserved +R8 MSIO126PB4 Unassigned +R9 MSIO130NB4 Unassigned +R10 MSIO131NB4 Unassigned +R11 MSIO134NB4 Unassigned +R12 MSIO138NB4 Unassigned +R13 MSIO145NB4 Unassigned +R14 JTAG_TCK Reserved +R15 XTLOSC_MAIN_EXTAL Reserved +R16 XTLOSC_MAIN_XTAL Reserved +T1 VSS Reserved +T2 DNC Reserved +T3 VSS Reserved +T4 DNC Reserved +T5 VSS Reserved +T6 MSIO120NB4/CCC_SW0_CLKI2 Special +T7 MSIO122PB4 Unassigned +T8 MSIO122NB4 Unassigned +T9 MSIO130PB4/VCCC_SE0_CLKI Special +T10 VSS Reserved +T11 MSIO134PB4/VCCC_SE1_CLKI Special +T12 MSIO138PB4 Unassigned +T13 MSIO145PB4 Unassigned +T14 VSS Reserved +T15 VPP Reserved +T16 VPP Reserved diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pkg_pin.db b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pkg_pin.db new file mode 100644 index 0000000..4eaf318 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_pkg_pin.db differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_place_and_route_constraint_coverage.xml b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_place_and_route_constraint_coverage.xml new file mode 100644 index 0000000..754dbd5 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_place_and_route_constraint_coverage.xml @@ -0,0 +1,344 @@ + + + +SmartTime Version 11.7.1.11 +Microsemi Corporation - Microsemi Libero Software Release v11.7 SP1 (Version 11.7.1.11) +Date: Sun Oct 23 03:01:07 2016 + +
+
+ + Design + LedBlinkingDSpeed + + + Family + IGLOO2 + + + Die + M2GL025 + + + Package + 256 VF + + + Temperature Range + 0 - 85 C + + + Voltage Range + 1.14 - 1.26 V + + + Speed Grade + STD + +
+ + +
+Coverage Summary + + +
+ Type of check + Constrained + UnConstrained + Total +
+ + Setup + 114 + 56 + 170 + + + Recovery + 114 + 0 + 114 + + + Output Setup + 0 + 2 + 2 + + + Total Setup + 228 + 58 + 286 + + + + Hold + 114 + 56 + 170 + + + Removal + 114 + 0 + 114 + + + Output Hold + 0 + 2 + 2 + + + Total Hold + 228 + 58 + 286 + +
+
+Clock domain: +LedBlinkingDSpeed|clk + + +
+ Type of check + Constrained + UnConstrained + Total +
+ + Setup + 114 + 56 + 170 + + + Recovery + 114 + 0 + 114 + + + Output Setup + 0 + 2 + 2 + + + Total Setup + 228 + 58 + 286 + + + + Hold + 114 + 56 + 170 + + + Removal + 114 + 0 + 114 + + + Output Hold + 0 + 2 + 2 + + + Total Hold + 228 + 58 + 286 + +
+
+Enhancement Suggestions + + - Max input delay constraint missing on ports: + + + SW1 + SW2 + + + - Min input delay constraint missing on ports: + + + SW1 + SW2 + + + + - Max output delay constraint missing on ports: + + + green_led1 + red_led2 + + + - Min output delay constraint missing on ports: + + + green_led1 + red_led2 + + + + - Setup uncconstrained for the following pins: + + + Clear_outputs/reset:D + Fast_clk_SW1/cnt[0]:EN + Fast_clk_SW1/cnt[10]:EN + Fast_clk_SW1/cnt[11]:EN + Fast_clk_SW1/cnt[12]:EN + Fast_clk_SW1/cnt[13]:EN + Fast_clk_SW1/cnt[14]:EN + Fast_clk_SW1/cnt[15]:EN + Fast_clk_SW1/cnt[16]:EN + Fast_clk_SW1/cnt[17]:EN + Fast_clk_SW1/cnt[18]:EN + Fast_clk_SW1/cnt[19]:EN + Fast_clk_SW1/cnt[1]:EN + Fast_clk_SW1/cnt[20]:EN + Fast_clk_SW1/cnt[21]:EN + Fast_clk_SW1/cnt[22]:EN + Fast_clk_SW1/cnt[23]:EN + Fast_clk_SW1/cnt[24]:EN + Fast_clk_SW1/cnt[25]:EN + Fast_clk_SW1/cnt[2]:EN + Fast_clk_SW1/cnt[3]:EN + Fast_clk_SW1/cnt[4]:EN + Fast_clk_SW1/cnt[5]:EN + Fast_clk_SW1/cnt[6]:EN + Fast_clk_SW1/cnt[7]:EN + Fast_clk_SW1/cnt[8]:EN + Fast_clk_SW1/cnt[9]:EN + Fast_clk_SW1/tmp_clk:EN + Fast_clk_SW2/cnt[0]:EN + Fast_clk_SW2/cnt[10]:EN + Fast_clk_SW2/cnt[11]:EN + Fast_clk_SW2/cnt[12]:EN + Fast_clk_SW2/cnt[13]:EN + Fast_clk_SW2/cnt[14]:EN + Fast_clk_SW2/cnt[15]:EN + Fast_clk_SW2/cnt[16]:EN + Fast_clk_SW2/cnt[17]:EN + Fast_clk_SW2/cnt[18]:EN + Fast_clk_SW2/cnt[19]:EN + Fast_clk_SW2/cnt[1]:EN + Fast_clk_SW2/cnt[20]:EN + Fast_clk_SW2/cnt[21]:EN + Fast_clk_SW2/cnt[22]:EN + Fast_clk_SW2/cnt[23]:EN + Fast_clk_SW2/cnt[24]:EN + Fast_clk_SW2/cnt[25]:EN + Fast_clk_SW2/cnt[26]:EN + Fast_clk_SW2/cnt[2]:EN + Fast_clk_SW2/cnt[3]:EN + Fast_clk_SW2/cnt[4]:EN + Fast_clk_SW2/cnt[5]:EN + Fast_clk_SW2/cnt[6]:EN + Fast_clk_SW2/cnt[7]:EN + Fast_clk_SW2/cnt[8]:EN + Fast_clk_SW2/cnt[9]:EN + Fast_clk_SW2/tmp_clk:EN + + + - Hold uncconstrained for the following pins: + + + Clear_outputs/reset:D + Fast_clk_SW1/cnt[0]:EN + Fast_clk_SW1/cnt[10]:EN + Fast_clk_SW1/cnt[11]:EN + Fast_clk_SW1/cnt[12]:EN + Fast_clk_SW1/cnt[13]:EN + Fast_clk_SW1/cnt[14]:EN + Fast_clk_SW1/cnt[15]:EN + Fast_clk_SW1/cnt[16]:EN + Fast_clk_SW1/cnt[17]:EN + Fast_clk_SW1/cnt[18]:EN + Fast_clk_SW1/cnt[19]:EN + Fast_clk_SW1/cnt[1]:EN + Fast_clk_SW1/cnt[20]:EN + Fast_clk_SW1/cnt[21]:EN + Fast_clk_SW1/cnt[22]:EN + Fast_clk_SW1/cnt[23]:EN + Fast_clk_SW1/cnt[24]:EN + Fast_clk_SW1/cnt[25]:EN + Fast_clk_SW1/cnt[2]:EN + Fast_clk_SW1/cnt[3]:EN + Fast_clk_SW1/cnt[4]:EN + Fast_clk_SW1/cnt[5]:EN + Fast_clk_SW1/cnt[6]:EN + Fast_clk_SW1/cnt[7]:EN + Fast_clk_SW1/cnt[8]:EN + Fast_clk_SW1/cnt[9]:EN + Fast_clk_SW1/tmp_clk:EN + Fast_clk_SW2/cnt[0]:EN + Fast_clk_SW2/cnt[10]:EN + Fast_clk_SW2/cnt[11]:EN + Fast_clk_SW2/cnt[12]:EN + Fast_clk_SW2/cnt[13]:EN + Fast_clk_SW2/cnt[14]:EN + Fast_clk_SW2/cnt[15]:EN + Fast_clk_SW2/cnt[16]:EN + Fast_clk_SW2/cnt[17]:EN + Fast_clk_SW2/cnt[18]:EN + Fast_clk_SW2/cnt[19]:EN + Fast_clk_SW2/cnt[1]:EN + Fast_clk_SW2/cnt[20]:EN + Fast_clk_SW2/cnt[21]:EN + Fast_clk_SW2/cnt[22]:EN + Fast_clk_SW2/cnt[23]:EN + Fast_clk_SW2/cnt[24]:EN + Fast_clk_SW2/cnt[25]:EN + Fast_clk_SW2/cnt[26]:EN + Fast_clk_SW2/cnt[2]:EN + Fast_clk_SW2/cnt[3]:EN + Fast_clk_SW2/cnt[4]:EN + Fast_clk_SW2/cnt[5]:EN + Fast_clk_SW2/cnt[6]:EN + Fast_clk_SW2/cnt[7]:EN + Fast_clk_SW2/cnt[8]:EN + Fast_clk_SW2/cnt[9]:EN + Fast_clk_SW2/tmp_clk:EN + + +
+
+
+Input to Output + +
+ Type of check + Constrained + UnConstrained + Total +
+ + Output Setup + 0 + 0 + 0 + + + + Output Hold + 0 + 0 + 0 + +
+
+
+ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_probe.db b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_probe.db new file mode 100644 index 0000000..aaf02e3 Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_probe.db differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_rwnetlist.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_rwnetlist.log new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_sdc.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_sdc.log new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_sii_block.db b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_sii_block.db new file mode 100644 index 0000000..c06fbcf Binary files /dev/null and b/Lab2_VHDL/designer/LedBlinkingDSpeed/LedBlinkingDSpeed_sii_block.db differ diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/clocklist.txt b/Lab2_VHDL/designer/LedBlinkingDSpeed/clocklist.txt new file mode 100644 index 0000000..ad3b31f --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/clocklist.txt @@ -0,0 +1 @@ +"clk",,"clk","clk" diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/coverage_placeandroute b/Lab2_VHDL/designer/LedBlinkingDSpeed/coverage_placeandroute new file mode 100644 index 0000000..663cbb6 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/coverage_placeandroute @@ -0,0 +1 @@ +79.72% diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/options.txt b/Lab2_VHDL/designer/LedBlinkingDSpeed/options.txt new file mode 100644 index 0000000..133fbf0 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/options.txt @@ -0,0 +1,48 @@ +ANALYSIS_BOTTLENECK_COST_TYPE,Path Count +ANALYSIS_BREAK_AT_ASYNC,1 +ANALYSIS_CLOCKLIST_SORT_CRITERIA,NAME +ANALYSIS_ENABLE_INTERDOMAINS,1 +ANALYSIS_ENHANCED_MIN_TIMING,0 +ANALYSIS_EXPAND_CLOCK_NETWORK,1 +ANALYSIS_INCLUDE_ASYNC_SETS,1 +ANALYSIS_LIMIT_PATHS,1 +ANALYSIS_MAX_BOTTLENECK_INSTANCES,10 +ANALYSIS_MAX_OPCOND,WORST +ANALYSIS_MAX_PARALLEL_PATHS,1 +ANALYSIS_MAX_PATHS,100 +ANALYSIS_MAX_SLACK,0 +ANALYSIS_MIN_OPCOND,BEST +ANALYSIS_MIN_SLACK,0 +ANALYSIS_SCENARIO,Primary +ANALYSIS_USE_LOOPBACK,0 +ANALYSIS_USE_MAX_SLACK,0 +ANALYSIS_USE_MIN_SLACK,0 +ANALYSIS_USE_SLACK_THRESHOLD,0 +BOTTLENECK_REPORT_ANALYSIS_TYPE,1 +BOTTLENECK_REPORT_MAX_PARALLEL_PATHS,1 +BOTTLENECK_REPORT_MAX_PATHS,100 +BOTTLENECK_REPORT_SLACK_THRESHOLD,0 +REPORT_ANALYSIS_TYPE,1 +REPORT_CLOCK_DOMAINS,clk +REPORT_FORMAT,TEXT +REPORT_MAX_EXPANDED_PATHS,1 +REPORT_MAX_PARALLEL_PATHS,1 +REPORT_MAX_PATHS,5 +REPORT_SHOW_CLOCK_DOMAINS,1 +REPORT_SHOW_INOUT_SETS,1 +REPORT_SHOW_PATHS,1 +REPORT_SHOW_SUMMARY,1 +REPORT_SHOW_USER_SETS,0 +REPORT_SLACK_THRESHOLD,0 +REPORT_USE_CLOCK_DOMAINS,0 +REPORT_USE_SLACK_THRESHOLD,0 +STATS_REPORT_NUMBER_DETAILS,20 +STATS_REPORT_SLACKS,0 +TDPR_SCENARIO,place_and_route +VIOLATION_REPORT_ANALYSIS_TYPE,1 +VIOLATION_REPORT_LIMIT_PATHS,1 +VIOLATION_REPORT_MAX_EXPANDED_PATHS,0 +VIOLATION_REPORT_MAX_PARALLEL_PATHS,1 +VIOLATION_REPORT_MAX_PATHS,100 +VIOLATION_REPORT_SLACK_THRESHOLD,0 +VIOLATION_REPORT_USE_SLACK_THRESHOLD,1 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/pinslacks.txt b/Lab2_VHDL/designer/LedBlinkingDSpeed/pinslacks.txt new file mode 100644 index 0000000..3bfeba8 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/pinslacks.txt @@ -0,0 +1,2101 @@ +pin,slack +Initial_blinking_SW1/cnt[25]:ADn, +Initial_blinking_SW1/cnt[25]:ALn,16174 +Initial_blinking_SW1/cnt[25]:CLK,14455 +Initial_blinking_SW1/cnt[25]:D,12116 +Initial_blinking_SW1/cnt[25]:EN, +Initial_blinking_SW1/cnt[25]:LAT, +Initial_blinking_SW1/cnt[25]:Q,14455 +Initial_blinking_SW1/cnt[25]:SD, +Initial_blinking_SW1/cnt[25]:SLn, +Fast_clk_SW2/un14_cntlto31_0_a2:A,14244 +Fast_clk_SW2/un14_cntlto31_0_a2:B,12873 +Fast_clk_SW2/un14_cntlto31_0_a2:C,14105 +Fast_clk_SW2/un14_cntlto31_0_a2:Y,12873 +Fast_clk_SW1/cnt[4]:ADn, +Fast_clk_SW1/cnt[4]:ALn,16174 +Fast_clk_SW1/cnt[4]:CLK,16977 +Fast_clk_SW1/cnt[4]:D,12433 +Fast_clk_SW1/cnt[4]:EN, +Fast_clk_SW1/cnt[4]:LAT, +Fast_clk_SW1/cnt[4]:Q,16977 +Fast_clk_SW1/cnt[4]:SD, +Fast_clk_SW1/cnt[4]:SLn, +Fast_clk_SW1/cnt_RNIT8KKR1[23]:A, +Fast_clk_SW1/cnt_RNIT8KKR1[23]:B,12472 +Fast_clk_SW1/cnt_RNIT8KKR1[23]:C,17256 +Fast_clk_SW1/cnt_RNIT8KKR1[23]:D, +Fast_clk_SW1/cnt_RNIT8KKR1[23]:FCI,12053 +Fast_clk_SW1/cnt_RNIT8KKR1[23]:FCO,12053 +Fast_clk_SW1/cnt_RNIT8KKR1[23]:S,12072 +Fast_clk_SW1/cnt[21]:ADn, +Fast_clk_SW1/cnt[21]:ALn,16174 +Fast_clk_SW1/cnt[21]:CLK,13165 +Fast_clk_SW1/cnt[21]:D,12110 +Fast_clk_SW1/cnt[21]:EN, +Fast_clk_SW1/cnt[21]:LAT, +Fast_clk_SW1/cnt[21]:Q,13165 +Fast_clk_SW1/cnt[21]:SD, +Fast_clk_SW1/cnt[21]:SLn, +Fast_clk_SW2/cnt_RNIBIIQL2[25]:A, +Fast_clk_SW2/cnt_RNIBIIQL2[25]:B,12464 +Fast_clk_SW2/cnt_RNIBIIQL2[25]:C,17256 +Fast_clk_SW2/cnt_RNIBIIQL2[25]:D, +Fast_clk_SW2/cnt_RNIBIIQL2[25]:FCI,12026 +Fast_clk_SW2/cnt_RNIBIIQL2[25]:FCO,12079 +Fast_clk_SW2/cnt_RNIBIIQL2[25]:S,12026 +Initial_blinking_SW2/tmp_clk_RNO_0:A,16456 +Initial_blinking_SW2/tmp_clk_RNO_0:B,16400 +Initial_blinking_SW2/tmp_clk_RNO_0:C,12788 +Initial_blinking_SW2/tmp_clk_RNO_0:D,14972 +Initial_blinking_SW2/tmp_clk_RNO_0:Y,12788 +Fast_clk_SW2/cnt_RNI2HMJ61[11]:A, +Fast_clk_SW2/cnt_RNI2HMJ61[11]:B,12235 +Fast_clk_SW2/cnt_RNI2HMJ61[11]:C,17075 +Fast_clk_SW2/cnt_RNI2HMJ61[11]:D, +Fast_clk_SW2/cnt_RNI2HMJ61[11]:FCI,12026 +Fast_clk_SW2/cnt_RNI2HMJ61[11]:FCO,12026 +Fast_clk_SW2/cnt_RNI2HMJ61[11]:S,12292 +Fast_clk_SW2/cnt[1]:ADn, +Fast_clk_SW2/cnt[1]:ALn,16174 +Fast_clk_SW2/cnt[1]:CLK,16901 +Fast_clk_SW2/cnt[1]:D,12464 +Fast_clk_SW2/cnt[1]:EN, +Fast_clk_SW2/cnt[1]:LAT, +Fast_clk_SW2/cnt[1]:Q,16901 +Fast_clk_SW2/cnt[1]:SD, +Fast_clk_SW2/cnt[1]:SLn, +Fast_clk_SW2/cnt[12]:ADn, +Fast_clk_SW2/cnt[12]:ALn,16174 +Fast_clk_SW2/cnt[12]:CLK,12236 +Fast_clk_SW2/cnt[12]:D,12273 +Fast_clk_SW2/cnt[12]:EN, +Fast_clk_SW2/cnt[12]:LAT, +Fast_clk_SW2/cnt[12]:Q,12236 +Fast_clk_SW2/cnt[12]:SD, +Fast_clk_SW2/cnt[12]:SLn, +Initial_blinking_SW1/cnt_RNI17TIH[6]:A, +Initial_blinking_SW1/cnt_RNI17TIH[6]:B,12230 +Initial_blinking_SW1/cnt_RNI17TIH[6]:C,16988 +Initial_blinking_SW1/cnt_RNI17TIH[6]:D, +Initial_blinking_SW1/cnt_RNI17TIH[6]:FCI,12116 +Initial_blinking_SW1/cnt_RNI17TIH[6]:FCO,12116 +Initial_blinking_SW1/cnt_RNI17TIH[6]:S,12477 +Fast_clk_SW2/cnt_RNIP91P5[0]:A, +Fast_clk_SW2/cnt_RNIP91P5[0]:B,12026 +Fast_clk_SW2/cnt_RNIP91P5[0]:C,16882 +Fast_clk_SW2/cnt_RNIP91P5[0]:D, +Fast_clk_SW2/cnt_RNIP91P5[0]:FCI,13309 +Fast_clk_SW2/cnt_RNIP91P5[0]:FCO,12026 +Fast_clk_SW2/cnt_RNIP91P5[0]:S,12464 +clk_ibuf/U0/U_IOINFF:A, +clk_ibuf/U0/U_IOINFF:Y, +Initial_blinking_SW2/cnt[26]:ADn, +Initial_blinking_SW2/cnt[26]:ALn,16174 +Initial_blinking_SW2/cnt[26]:CLK,15540 +Initial_blinking_SW2/cnt[26]:D,10915 +Initial_blinking_SW2/cnt[26]:EN, +Initial_blinking_SW2/cnt[26]:LAT, +Initial_blinking_SW2/cnt[26]:Q,15540 +Initial_blinking_SW2/cnt[26]:SD, +Initial_blinking_SW2/cnt[26]:SLn, +Initial_blinking_SW1/cnt[19]:ADn, +Initial_blinking_SW1/cnt[19]:ALn,16174 +Initial_blinking_SW1/cnt[19]:CLK,13178 +Initial_blinking_SW1/cnt[19]:D,12230 +Initial_blinking_SW1/cnt[19]:EN, +Initial_blinking_SW1/cnt[19]:LAT, +Initial_blinking_SW1/cnt[19]:Q,13178 +Initial_blinking_SW1/cnt[19]:SD, +Initial_blinking_SW1/cnt[19]:SLn, +Initial_blinking_SW2/cnt_RNI4JC9[21]:A,13364 +Initial_blinking_SW2/cnt_RNI4JC9[21]:B,13273 +Initial_blinking_SW2/cnt_RNI4JC9[21]:C,13220 +Initial_blinking_SW2/cnt_RNI4JC9[21]:Y,13220 +Initial_blinking_SW1/un7_cntlto31_0_a3:A,16238 +Initial_blinking_SW1/un7_cntlto31_0_a3:B,16190 +Initial_blinking_SW1/un7_cntlto31_0_a3:C,11541 +Initial_blinking_SW1/un7_cntlto31_0_a3:D,15984 +Initial_blinking_SW1/un7_cntlto31_0_a3:Y,11541 +Initial_blinking_SW2/cnt[19]:ADn, +Initial_blinking_SW2/cnt[19]:ALn,16174 +Initial_blinking_SW2/cnt[19]:CLK,13278 +Initial_blinking_SW2/cnt[19]:D,11040 +Initial_blinking_SW2/cnt[19]:EN, +Initial_blinking_SW2/cnt[19]:LAT, +Initial_blinking_SW2/cnt[19]:Q,13278 +Initial_blinking_SW2/cnt[19]:SD, +Initial_blinking_SW2/cnt[19]:SLn, +Fast_clk_SW2/cnt_RNI0BA3K1[15]:A, +Fast_clk_SW2/cnt_RNI0BA3K1[15]:B,12311 +Fast_clk_SW2/cnt_RNI0BA3K1[15]:C,17151 +Fast_clk_SW2/cnt_RNI0BA3K1[15]:D, +Fast_clk_SW2/cnt_RNI0BA3K1[15]:FCI,12026 +Fast_clk_SW2/cnt_RNI0BA3K1[15]:FCO,12026 +Fast_clk_SW2/cnt_RNI0BA3K1[15]:S,12216 +Initial_blinking_SW2/cnt_RNILBPBC1[13]:A, +Initial_blinking_SW2/cnt_RNILBPBC1[13]:B,11125 +Initial_blinking_SW2/cnt_RNILBPBC1[13]:C,17094 +Initial_blinking_SW2/cnt_RNILBPBC1[13]:D, +Initial_blinking_SW2/cnt_RNILBPBC1[13]:FCI,10904 +Initial_blinking_SW2/cnt_RNILBPBC1[13]:FCO,10904 +Initial_blinking_SW2/cnt_RNILBPBC1[13]:S,11142 +Fast_clk_SW2/cnt[23]:ADn, +Fast_clk_SW2/cnt[23]:ALn,16174 +Fast_clk_SW2/cnt[23]:CLK,14549 +Fast_clk_SW2/cnt[23]:D,12064 +Fast_clk_SW2/cnt[23]:EN, +Fast_clk_SW2/cnt[23]:LAT, +Fast_clk_SW2/cnt[23]:Q,14549 +Fast_clk_SW2/cnt[23]:SD, +Fast_clk_SW2/cnt[23]:SLn, +Fast_clk_SW2/cnt[19]:ADn, +Fast_clk_SW2/cnt[19]:ALn,16174 +Fast_clk_SW2/cnt[19]:CLK,12873 +Fast_clk_SW2/cnt[19]:D,12140 +Fast_clk_SW2/cnt[19]:EN, +Fast_clk_SW2/cnt[19]:LAT, +Fast_clk_SW2/cnt[19]:Q,12873 +Fast_clk_SW2/cnt[19]:SD, +Fast_clk_SW2/cnt[19]:SLn, +Initial_blinking_SW1/cnt_RNI3INT71[16]:A, +Initial_blinking_SW1/cnt_RNI3INT71[16]:B,12420 +Initial_blinking_SW1/cnt_RNI3INT71[16]:C,17170 +Initial_blinking_SW1/cnt_RNI3INT71[16]:D, +Initial_blinking_SW1/cnt_RNI3INT71[16]:FCI,12116 +Initial_blinking_SW1/cnt_RNI3INT71[16]:FCO,12116 +Initial_blinking_SW1/cnt_RNI3INT71[16]:S,12287 +Initial_blinking_SW1/cnt[13]:ADn, +Initial_blinking_SW1/cnt[13]:ALn,16174 +Initial_blinking_SW1/cnt[13]:CLK,12213 +Initial_blinking_SW1/cnt[13]:D,12344 +Initial_blinking_SW1/cnt[13]:EN, +Initial_blinking_SW1/cnt[13]:LAT, +Initial_blinking_SW1/cnt[13]:Q,12213 +Initial_blinking_SW1/cnt[13]:SD, +Initial_blinking_SW1/cnt[13]:SLn, +Initial_blinking_SW1/cnt[15]:ADn, +Initial_blinking_SW1/cnt[15]:ALn,16174 +Initial_blinking_SW1/cnt[15]:CLK,13492 +Initial_blinking_SW1/cnt[15]:D,12306 +Initial_blinking_SW1/cnt[15]:EN, +Initial_blinking_SW1/cnt[15]:LAT, +Initial_blinking_SW1/cnt[15]:Q,13492 +Initial_blinking_SW1/cnt[15]:SD, +Initial_blinking_SW1/cnt[15]:SLn, +Fast_clk_SW2/cnt[18]:ADn, +Fast_clk_SW2/cnt[18]:ALn,16174 +Fast_clk_SW2/cnt[18]:CLK,14105 +Fast_clk_SW2/cnt[18]:D,12159 +Fast_clk_SW2/cnt[18]:EN, +Fast_clk_SW2/cnt[18]:LAT, +Fast_clk_SW2/cnt[18]:Q,14105 +Fast_clk_SW2/cnt[18]:SD, +Fast_clk_SW2/cnt[18]:SLn, +Initial_blinking_SW1/cnt[22]:ADn, +Initial_blinking_SW1/cnt[22]:ALn,16174 +Initial_blinking_SW1/cnt[22]:CLK,13443 +Initial_blinking_SW1/cnt[22]:D,12173 +Initial_blinking_SW1/cnt[22]:EN, +Initial_blinking_SW1/cnt[22]:LAT, +Initial_blinking_SW1/cnt[22]:Q,13443 +Initial_blinking_SW1/cnt[22]:SD, +Initial_blinking_SW1/cnt[22]:SLn, +Fast_clk_SW1/cnt[14]:ADn, +Fast_clk_SW1/cnt[14]:ALn,16174 +Fast_clk_SW1/cnt[14]:CLK,13569 +Fast_clk_SW1/cnt[14]:D,12243 +Fast_clk_SW1/cnt[14]:EN, +Fast_clk_SW1/cnt[14]:LAT, +Fast_clk_SW1/cnt[14]:Q,13569 +Fast_clk_SW1/cnt[14]:SD, +Fast_clk_SW1/cnt[14]:SLn, +Initial_blinking_SW2/cnt[13]:ADn, +Initial_blinking_SW2/cnt[13]:ALn,16174 +Initial_blinking_SW2/cnt[13]:CLK,11009 +Initial_blinking_SW2/cnt[13]:D,11142 +Initial_blinking_SW2/cnt[13]:EN, +Initial_blinking_SW2/cnt[13]:LAT, +Initial_blinking_SW2/cnt[13]:Q,11009 +Initial_blinking_SW2/cnt[13]:SD, +Initial_blinking_SW2/cnt[13]:SLn, +Initial_blinking_SW2/tmp_clk:ADn, +Initial_blinking_SW2/tmp_clk:ALn,16174 +Initial_blinking_SW2/tmp_clk:CLK,17476 +Initial_blinking_SW2/tmp_clk:D,12788 +Initial_blinking_SW2/tmp_clk:EN, +Initial_blinking_SW2/tmp_clk:LAT, +Initial_blinking_SW2/tmp_clk:Q,17476 +Initial_blinking_SW2/tmp_clk:SD, +Initial_blinking_SW2/tmp_clk:SLn, +Initial_blinking_SW2/cnt[15]:ADn, +Initial_blinking_SW2/cnt[15]:ALn,16174 +Initial_blinking_SW2/cnt[15]:CLK,11154 +Initial_blinking_SW2/cnt[15]:D,11108 +Initial_blinking_SW2/cnt[15]:EN, +Initial_blinking_SW2/cnt[15]:LAT, +Initial_blinking_SW2/cnt[15]:Q,11154 +Initial_blinking_SW2/cnt[15]:SD, +Initial_blinking_SW2/cnt[15]:SLn, +Display_out/green_led1:ADn, +Display_out/green_led1:ALn,16174 +Display_out/green_led1:CLK, +Display_out/green_led1:D,17329 +Display_out/green_led1:EN, +Display_out/green_led1:LAT, +Display_out/green_led1:Q, +Display_out/green_led1:SD, +Display_out/green_led1:SLn, +Fast_clk_SW2/cnt_RNIIRHIB[2]:A, +Fast_clk_SW2/cnt_RNIIRHIB[2]:B,12064 +Fast_clk_SW2/cnt_RNIIRHIB[2]:C,16920 +Fast_clk_SW2/cnt_RNIIRHIB[2]:D, +Fast_clk_SW2/cnt_RNIIRHIB[2]:FCI,12026 +Fast_clk_SW2/cnt_RNIIRHIB[2]:FCO,12026 +Fast_clk_SW2/cnt_RNIIRHIB[2]:S,12463 +Clear_outputs/reset_RNO:A, +Clear_outputs/reset_RNO:B, +Clear_outputs/reset_RNO:Y, +Initial_blinking_SW1/cnt_RNIUC45A1[17]:A, +Initial_blinking_SW1/cnt_RNIUC45A1[17]:B,12439 +Initial_blinking_SW1/cnt_RNIUC45A1[17]:C,17189 +Initial_blinking_SW1/cnt_RNIUC45A1[17]:D, +Initial_blinking_SW1/cnt_RNIUC45A1[17]:FCI,12116 +Initial_blinking_SW1/cnt_RNIUC45A1[17]:FCO,12116 +Initial_blinking_SW1/cnt_RNIUC45A1[17]:S,12268 +Initial_blinking_SW1/cnt[24]:ADn, +Initial_blinking_SW1/cnt[24]:ALn,16174 +Initial_blinking_SW1/cnt[24]:CLK,14325 +Initial_blinking_SW1/cnt[24]:D,12135 +Initial_blinking_SW1/cnt[24]:EN, +Initial_blinking_SW1/cnt[24]:LAT, +Initial_blinking_SW1/cnt[24]:Q,14325 +Initial_blinking_SW1/cnt[24]:SD, +Initial_blinking_SW1/cnt[24]:SLn, +Initial_blinking_SW1/cnt_RNI3G6K8[2]:A, +Initial_blinking_SW1/cnt_RNI3G6K8[2]:B,12154 +Initial_blinking_SW1/cnt_RNI3G6K8[2]:C,16920 +Initial_blinking_SW1/cnt_RNI3G6K8[2]:D, +Initial_blinking_SW1/cnt_RNI3G6K8[2]:FCI,12116 +Initial_blinking_SW1/cnt_RNI3G6K8[2]:FCO,12116 +Initial_blinking_SW1/cnt_RNI3G6K8[2]:S,12553 +green_led2_obuf/U0/U_IOOUTFF:A, +green_led2_obuf/U0/U_IOOUTFF:Y, +Initial_blinking_SW1/cnt_RNIUSGC6[1]:A, +Initial_blinking_SW1/cnt_RNIUSGC6[1]:B,12135 +Initial_blinking_SW1/cnt_RNIUSGC6[1]:C,16901 +Initial_blinking_SW1/cnt_RNIUSGC6[1]:D, +Initial_blinking_SW1/cnt_RNIUSGC6[1]:FCI,12116 +Initial_blinking_SW1/cnt_RNIUSGC6[1]:FCO,12116 +Initial_blinking_SW1/cnt_RNIUSGC6[1]:S,12554 +green_led2_obuf/U0/U_IOPAD:D, +green_led2_obuf/U0/U_IOPAD:E, +green_led2_obuf/U0/U_IOPAD:PAD, +Fast_clk_SW2/cnt[25]:ADn, +Fast_clk_SW2/cnt[25]:ALn,16174 +Fast_clk_SW2/cnt[25]:CLK,14402 +Fast_clk_SW2/cnt[25]:D,12026 +Fast_clk_SW2/cnt[25]:EN, +Fast_clk_SW2/cnt[25]:LAT, +Fast_clk_SW2/cnt[25]:Q,14402 +Fast_clk_SW2/cnt[25]:SD, +Fast_clk_SW2/cnt[25]:SLn, +Initial_blinking_SW1/un14_cntlto31_0_o3_0:A,13542 +Initial_blinking_SW1/un14_cntlto31_0_o3_0:B,13492 +Initial_blinking_SW1/un14_cntlto31_0_o3_0:C,12118 +Initial_blinking_SW1/un14_cntlto31_0_o3_0:D,12116 +Initial_blinking_SW1/un14_cntlto31_0_o3_0:Y,12116 +Fast_clk_SW1/cnt_RNICOU4H[5]:A, +Fast_clk_SW1/cnt_RNICOU4H[5]:B,12148 +Fast_clk_SW1/cnt_RNICOU4H[5]:C,16988 +Fast_clk_SW1/cnt_RNICOU4H[5]:D, +Fast_clk_SW1/cnt_RNICOU4H[5]:FCI,12053 +Fast_clk_SW1/cnt_RNICOU4H[5]:FCO,12053 +Fast_clk_SW1/cnt_RNICOU4H[5]:S,12414 +Fast_clk_SW1/cnt_RNI8IMKE[4]:A, +Fast_clk_SW1/cnt_RNI8IMKE[4]:B,12129 +Fast_clk_SW1/cnt_RNI8IMKE[4]:C,16977 +Fast_clk_SW1/cnt_RNI8IMKE[4]:D, +Fast_clk_SW1/cnt_RNI8IMKE[4]:FCI,12053 +Fast_clk_SW1/cnt_RNI8IMKE[4]:FCO,12053 +Fast_clk_SW1/cnt_RNI8IMKE[4]:S,12433 +Fast_clk_SW2/cnt_RNIBISU42[20]:A, +Fast_clk_SW2/cnt_RNIBISU42[20]:B,12406 +Fast_clk_SW2/cnt_RNIBISU42[20]:C,17254 +Fast_clk_SW2/cnt_RNIBISU42[20]:D, +Fast_clk_SW2/cnt_RNIBISU42[20]:FCI,12026 +Fast_clk_SW2/cnt_RNIBISU42[20]:FCO,12026 +Fast_clk_SW2/cnt_RNIBISU42[20]:S,12121 +Fast_clk_SW1/cnt_RNIPOG421[12]:A, +Fast_clk_SW1/cnt_RNIPOG421[12]:B,12281 +Fast_clk_SW1/cnt_RNIPOG421[12]:C,17121 +Fast_clk_SW1/cnt_RNIPOG421[12]:D, +Fast_clk_SW1/cnt_RNIPOG421[12]:FCI,12053 +Fast_clk_SW1/cnt_RNIPOG421[12]:FCO,12053 +Fast_clk_SW1/cnt_RNIPOG421[12]:S,12281 +Fast_clk_SW1/cnt[23]:ADn, +Fast_clk_SW1/cnt[23]:ALn,16174 +Fast_clk_SW1/cnt[23]:CLK,14299 +Fast_clk_SW1/cnt[23]:D,12072 +Fast_clk_SW1/cnt[23]:EN, +Fast_clk_SW1/cnt[23]:LAT, +Fast_clk_SW1/cnt[23]:Q,14299 +Fast_clk_SW1/cnt[23]:SD, +Fast_clk_SW1/cnt[23]:SLn, +Fast_clk_SW2/un7_cntlto31_0_a2_0:A,13997 +Fast_clk_SW2/un7_cntlto31_0_a2_0:B,13941 +Fast_clk_SW2/un7_cntlto31_0_a2_0:C,12703 +Fast_clk_SW2/un7_cntlto31_0_a2_0:D,11512 +Fast_clk_SW2/un7_cntlto31_0_a2_0:Y,11512 +Initial_blinking_SW2/cnt_RNI819V42[22]:A, +Initial_blinking_SW2/cnt_RNI819V42[22]:B,11278 +Initial_blinking_SW2/cnt_RNI819V42[22]:C,17264 +Initial_blinking_SW2/cnt_RNI819V42[22]:D, +Initial_blinking_SW2/cnt_RNI819V42[22]:FCI,10904 +Initial_blinking_SW2/cnt_RNI819V42[22]:FCO,10904 +Initial_blinking_SW2/cnt_RNI819V42[22]:S,10989 +Initial_blinking_SW2/cnt_RNIAIOQH1[15]:A, +Initial_blinking_SW2/cnt_RNIAIOQH1[15]:B,11159 +Initial_blinking_SW2/cnt_RNIAIOQH1[15]:C,17132 +Initial_blinking_SW2/cnt_RNIAIOQH1[15]:D, +Initial_blinking_SW2/cnt_RNIAIOQH1[15]:FCI,10904 +Initial_blinking_SW2/cnt_RNIAIOQH1[15]:FCO,10904 +Initial_blinking_SW2/cnt_RNIAIOQH1[15]:S,11108 +Fast_clk_SW2/un14_cntlto31_0_o3:A,14549 +Fast_clk_SW2/un14_cntlto31_0_o3:B,13186 +Fast_clk_SW2/un14_cntlto31_0_o3:C,14402 +Fast_clk_SW2/un14_cntlto31_0_o3:D,14272 +Fast_clk_SW2/un14_cntlto31_0_o3:Y,13186 +Initial_blinking_SW1/cnt[0]:ADn, +Initial_blinking_SW1/cnt[0]:ALn,16174 +Initial_blinking_SW1/cnt[0]:CLK,16882 +Initial_blinking_SW1/cnt[0]:D,12554 +Initial_blinking_SW1/cnt[0]:EN, +Initial_blinking_SW1/cnt[0]:LAT, +Initial_blinking_SW1/cnt[0]:Q,16882 +Initial_blinking_SW1/cnt[0]:SD, +Initial_blinking_SW1/cnt[0]:SLn, +Initial_blinking_SW2/cnt_RNI4GAR1[17]:A,13422 +Initial_blinking_SW2/cnt_RNI4GAR1[17]:B,10904 +Initial_blinking_SW2/cnt_RNI4GAR1[17]:C,13278 +Initial_blinking_SW2/cnt_RNI4GAR1[17]:D,13158 +Initial_blinking_SW2/cnt_RNI4GAR1[17]:Y,10904 +Initial_blinking_SW1/cnt[12]:ADn, +Initial_blinking_SW1/cnt[12]:ALn,16174 +Initial_blinking_SW1/cnt[12]:CLK,12116 +Initial_blinking_SW1/cnt[12]:D,12363 +Initial_blinking_SW1/cnt[12]:EN, +Initial_blinking_SW1/cnt[12]:LAT, +Initial_blinking_SW1/cnt[12]:Q,12116 +Initial_blinking_SW1/cnt[12]:SD, +Initial_blinking_SW1/cnt[12]:SLn, +Fast_clk_SW1/un14_cntlto31_0_o2_0:A,12410 +Fast_clk_SW1/un14_cntlto31_0_o2_0:B,12360 +Fast_clk_SW1/un14_cntlto31_0_o2_0:C,12263 +Fast_clk_SW1/un14_cntlto31_0_o2_0:Y,12263 +Fast_clk_SW1/cnt_RNILV1391[15]:A, +Fast_clk_SW1/cnt_RNILV1391[15]:B,12338 +Fast_clk_SW1/cnt_RNILV1391[15]:C,17170 +Fast_clk_SW1/cnt_RNILV1391[15]:D, +Fast_clk_SW1/cnt_RNILV1391[15]:FCI,12053 +Fast_clk_SW1/cnt_RNILV1391[15]:FCO,12053 +Fast_clk_SW1/cnt_RNILV1391[15]:S,12224 +Initial_blinking_SW1/cnt[20]:ADn, +Initial_blinking_SW1/cnt[20]:ALn,16174 +Initial_blinking_SW1/cnt[20]:CLK,13296 +Initial_blinking_SW1/cnt[20]:D,12211 +Initial_blinking_SW1/cnt[20]:EN, +Initial_blinking_SW1/cnt[20]:LAT, +Initial_blinking_SW1/cnt[20]:Q,13296 +Initial_blinking_SW1/cnt[20]:SD, +Initial_blinking_SW1/cnt[20]:SLn, +Clear_outputs/reset_RNIREK/U0_RGB1:An, +Clear_outputs/reset_RNIREK/U0_RGB1:ENn, +Clear_outputs/reset_RNIREK/U0_RGB1:YL,16174 +Initial_blinking_SW2/cnt[12]:ADn, +Initial_blinking_SW2/cnt[12]:ALn,16174 +Initial_blinking_SW2/cnt[12]:CLK,12351 +Initial_blinking_SW2/cnt[12]:D,11159 +Initial_blinking_SW2/cnt[12]:EN, +Initial_blinking_SW2/cnt[12]:LAT, +Initial_blinking_SW2/cnt[12]:Q,12351 +Initial_blinking_SW2/cnt[12]:SD, +Initial_blinking_SW2/cnt[12]:SLn, +Initial_blinking_SW1/un7_cntlto31_0_a2_0:A,13946 +Initial_blinking_SW1/un7_cntlto31_0_a2_0:B,13890 +Initial_blinking_SW1/un7_cntlto31_0_a2_0:C,11541 +Initial_blinking_SW1/un7_cntlto31_0_a2_0:D,12572 +Initial_blinking_SW1/un7_cntlto31_0_a2_0:Y,11541 +Fast_clk_SW2/cnt[20]:ADn, +Fast_clk_SW2/cnt[20]:ALn,16174 +Fast_clk_SW2/cnt[20]:CLK,12991 +Fast_clk_SW2/cnt[20]:D,12121 +Fast_clk_SW2/cnt[20]:EN, +Fast_clk_SW2/cnt[20]:LAT, +Fast_clk_SW2/cnt[20]:Q,12991 +Fast_clk_SW2/cnt[20]:SD, +Fast_clk_SW2/cnt[20]:SLn, +Fast_clk_SW2/cnt[11]:ADn, +Fast_clk_SW2/cnt[11]:ALn,16174 +Fast_clk_SW2/cnt[11]:CLK,13492 +Fast_clk_SW2/cnt[11]:D,12292 +Fast_clk_SW2/cnt[11]:EN, +Fast_clk_SW2/cnt[11]:LAT, +Fast_clk_SW2/cnt[11]:Q,13492 +Fast_clk_SW2/cnt[11]:SD, +Fast_clk_SW2/cnt[11]:SLn, +Initial_blinking_SW2/cnt[7]:ADn, +Initial_blinking_SW2/cnt[7]:ALn,16174 +Initial_blinking_SW2/cnt[7]:CLK,14243 +Initial_blinking_SW2/cnt[7]:D,11244 +Initial_blinking_SW2/cnt[7]:EN, +Initial_blinking_SW2/cnt[7]:LAT, +Initial_blinking_SW2/cnt[7]:Q,14243 +Initial_blinking_SW2/cnt[7]:SD, +Initial_blinking_SW2/cnt[7]:SLn, +Initial_blinking_SW1/cnt[14]:ADn, +Initial_blinking_SW1/cnt[14]:ALn,16174 +Initial_blinking_SW1/cnt[14]:CLK,12263 +Initial_blinking_SW1/cnt[14]:D,12325 +Initial_blinking_SW1/cnt[14]:EN, +Initial_blinking_SW1/cnt[14]:LAT, +Initial_blinking_SW1/cnt[14]:Q,12263 +Initial_blinking_SW1/cnt[14]:SD, +Initial_blinking_SW1/cnt[14]:SLn, +Fast_clk_SW1/cnt[25]:ADn, +Fast_clk_SW1/cnt[25]:ALn,16174 +Fast_clk_SW1/cnt[25]:CLK,14271 +Fast_clk_SW1/cnt[25]:D,12104 +Fast_clk_SW1/cnt[25]:EN, +Fast_clk_SW1/cnt[25]:LAT, +Fast_clk_SW1/cnt[25]:Q,14271 +Fast_clk_SW1/cnt[25]:SD, +Fast_clk_SW1/cnt[25]:SLn, +Initial_blinking_SW1/un14_cntlto31_0_a2_1_3:A,11795 +Initial_blinking_SW1/un14_cntlto31_0_a2_1_3:B,11739 +Initial_blinking_SW1/un14_cntlto31_0_a2_1_3:C,11651 +Initial_blinking_SW1/un14_cntlto31_0_a2_1_3:D,11541 +Initial_blinking_SW1/un14_cntlto31_0_a2_1_3:Y,11541 +Initial_blinking_SW1/cnt_RNI1H40V[12]:A, +Initial_blinking_SW1/cnt_RNI1H40V[12]:B,12344 +Initial_blinking_SW1/cnt_RNI1H40V[12]:C,17102 +Initial_blinking_SW1/cnt_RNI1H40V[12]:D, +Initial_blinking_SW1/cnt_RNI1H40V[12]:FCI,12116 +Initial_blinking_SW1/cnt_RNI1H40V[12]:FCO,12116 +Initial_blinking_SW1/cnt_RNI1H40V[12]:S,12363 +Fast_clk_SW2/un7_cntlto31_0_a2_1:A,11512 +Fast_clk_SW2/un7_cntlto31_0_a2_1:B,12719 +Fast_clk_SW2/un7_cntlto31_0_a2_1:Y,11512 +Fast_clk_SW2/cnt_RNIFH2CH[4]:A, +Fast_clk_SW2/cnt_RNIFH2CH[4]:B,12102 +Fast_clk_SW2/cnt_RNIFH2CH[4]:C,16958 +Fast_clk_SW2/cnt_RNIFH2CH[4]:D, +Fast_clk_SW2/cnt_RNIFH2CH[4]:FCI,12026 +Fast_clk_SW2/cnt_RNIFH2CH[4]:FCO,12026 +Fast_clk_SW2/cnt_RNIFH2CH[4]:S,12425 +clk_ibuf_RNIVTI2/U0:An, +clk_ibuf_RNIVTI2/U0:ENn, +clk_ibuf_RNIVTI2/U0:YWn, +Initial_blinking_SW2/cnt[14]:ADn, +Initial_blinking_SW2/cnt[14]:ALn,16174 +Initial_blinking_SW2/cnt[14]:CLK,11101 +Initial_blinking_SW2/cnt[14]:D,11125 +Initial_blinking_SW2/cnt[14]:EN, +Initial_blinking_SW2/cnt[14]:LAT, +Initial_blinking_SW2/cnt[14]:Q,11101 +Initial_blinking_SW2/cnt[14]:SD, +Initial_blinking_SW2/cnt[14]:SLn, +Fast_clk_SW2/cnt_RNIVBGBD1[13]:A, +Fast_clk_SW2/cnt_RNIVBGBD1[13]:B,12273 +Fast_clk_SW2/cnt_RNIVBGBD1[13]:C,17121 +Fast_clk_SW2/cnt_RNIVBGBD1[13]:D, +Fast_clk_SW2/cnt_RNIVBGBD1[13]:FCI,12026 +Fast_clk_SW2/cnt_RNIVBGBD1[13]:FCO,12026 +Fast_clk_SW2/cnt_RNIVBGBD1[13]:S,12254 +Fast_clk_SW2/cnt[17]:ADn, +Fast_clk_SW2/cnt[17]:ALn,16174 +Fast_clk_SW2/cnt[17]:CLK,14651 +Fast_clk_SW2/cnt[17]:D,12178 +Fast_clk_SW2/cnt[17]:EN, +Fast_clk_SW2/cnt[17]:LAT, +Fast_clk_SW2/cnt[17]:Q,14651 +Fast_clk_SW2/cnt[17]:SD, +Fast_clk_SW2/cnt[17]:SLn, +Initial_blinking_SW2/tmp_clk_RNO_4:A,13129 +Initial_blinking_SW2/tmp_clk_RNO_4:B,13038 +Initial_blinking_SW2/tmp_clk_RNO_4:C,12985 +Initial_blinking_SW2/tmp_clk_RNO_4:D,12893 +Initial_blinking_SW2/tmp_clk_RNO_4:Y,12893 +Fast_clk_SW1/cnt_RNI24MJ4[0]:A, +Fast_clk_SW1/cnt_RNI24MJ4[0]:B,12053 +Fast_clk_SW1/cnt_RNI24MJ4[0]:C,16901 +Fast_clk_SW1/cnt_RNI24MJ4[0]:D, +Fast_clk_SW1/cnt_RNI24MJ4[0]:FCI,13328 +Fast_clk_SW1/cnt_RNI24MJ4[0]:FCO,12053 +Fast_clk_SW1/cnt_RNI24MJ4[0]:S,12472 +Fast_clk_SW1/un14_cntlto31_0_a2_1_3:A,11766 +Fast_clk_SW1/un14_cntlto31_0_a2_1_3:B,11710 +Fast_clk_SW1/un14_cntlto31_0_a2_1_3:C,11622 +Fast_clk_SW1/un14_cntlto31_0_a2_1_3:D,11512 +Fast_clk_SW1/un14_cntlto31_0_a2_1_3:Y,11512 +Initial_blinking_SW1/cnt_RNIH2LHN1[23]:A, +Initial_blinking_SW1/cnt_RNIH2LHN1[23]:B,12550 +Initial_blinking_SW1/cnt_RNIH2LHN1[23]:C,17256 +Initial_blinking_SW1/cnt_RNIH2LHN1[23]:D, +Initial_blinking_SW1/cnt_RNIH2LHN1[23]:FCI,12116 +Initial_blinking_SW1/cnt_RNIH2LHN1[23]:FCO,12116 +Initial_blinking_SW1/cnt_RNIH2LHN1[23]:S,12154 +Fast_clk_SW1/un7_cntlto31_0_a2_1:A,11512 +Fast_clk_SW1/un7_cntlto31_0_a2_1:B,12719 +Fast_clk_SW1/un7_cntlto31_0_a2_1:Y,11512 +Fast_clk_SW1/cnt_RNIUGNLO[8]:A, +Fast_clk_SW1/cnt_RNIUGNLO[8]:B,12205 +Fast_clk_SW1/cnt_RNIUGNLO[8]:C,17045 +Fast_clk_SW1/cnt_RNIUGNLO[8]:D, +Fast_clk_SW1/cnt_RNIUGNLO[8]:FCI,12053 +Fast_clk_SW1/cnt_RNIUGNLO[8]:FCO,12053 +Fast_clk_SW1/cnt_RNIUGNLO[8]:S,12357 +Fast_clk_SW1/cnt[16]:ADn, +Fast_clk_SW1/cnt[16]:ALn,16174 +Fast_clk_SW1/cnt[16]:CLK,14678 +Fast_clk_SW1/cnt[16]:D,12205 +Fast_clk_SW1/cnt[16]:EN, +Fast_clk_SW1/cnt[16]:LAT, +Fast_clk_SW1/cnt[16]:Q,14678 +Fast_clk_SW1/cnt[16]:SD, +Fast_clk_SW1/cnt[16]:SLn, +Initial_blinking_SW1/cnt_RNIMO82M[8]:A, +Initial_blinking_SW1/cnt_RNIMO82M[8]:B,12268 +Initial_blinking_SW1/cnt_RNIMO82M[8]:C,17026 +Initial_blinking_SW1/cnt_RNIMO82M[8]:D, +Initial_blinking_SW1/cnt_RNIMO82M[8]:FCI,12116 +Initial_blinking_SW1/cnt_RNIMO82M[8]:FCO,12116 +Initial_blinking_SW1/cnt_RNIMO82M[8]:S,12439 +Fast_clk_SW2/un7_cntlto31_0_a3:A,16238 +Fast_clk_SW2/un7_cntlto31_0_a3:B,11512 +Fast_clk_SW2/un7_cntlto31_0_a3:C,16102 +Fast_clk_SW2/un7_cntlto31_0_a3:D,15974 +Fast_clk_SW2/un7_cntlto31_0_a3:Y,11512 +Initial_blinking_SW1/un14_cntlto31_0_o3_0_RNI6DVC1:A,14701 +Initial_blinking_SW1/un14_cntlto31_0_o3_0_RNI6DVC1:B,14651 +Initial_blinking_SW1/un14_cntlto31_0_o3_0_RNI6DVC1:C,12116 +Initial_blinking_SW1/un14_cntlto31_0_o3_0_RNI6DVC1:D,14395 +Initial_blinking_SW1/un14_cntlto31_0_o3_0_RNI6DVC1:Y,12116 +Fast_clk_SW1/cnt[5]:ADn, +Fast_clk_SW1/cnt[5]:ALn,16174 +Fast_clk_SW1/cnt[5]:CLK,12719 +Fast_clk_SW1/cnt[5]:D,12414 +Fast_clk_SW1/cnt[5]:EN, +Fast_clk_SW1/cnt[5]:LAT, +Fast_clk_SW1/cnt[5]:Q,12719 +Fast_clk_SW1/cnt[5]:SD, +Fast_clk_SW1/cnt[5]:SLn, +Initial_blinking_SW2/cnt[3]:ADn, +Initial_blinking_SW2/cnt[3]:ALn,16174 +Initial_blinking_SW2/cnt[3]:CLK,16920 +Initial_blinking_SW2/cnt[3]:D,11312 +Initial_blinking_SW2/cnt[3]:EN, +Initial_blinking_SW2/cnt[3]:LAT, +Initial_blinking_SW2/cnt[3]:Q,16920 +Initial_blinking_SW2/cnt[3]:SD, +Initial_blinking_SW2/cnt[3]:SLn, +Initial_blinking_SW2/cnt_RNI8JG21[10]:A,11158 +Initial_blinking_SW2/cnt_RNI8JG21[10]:B,11102 +Initial_blinking_SW2/cnt_RNI8JG21[10]:C,11014 +Initial_blinking_SW2/cnt_RNI8JG21[10]:D,10904 +Initial_blinking_SW2/cnt_RNI8JG21[10]:Y,10904 +Initial_blinking_SW2/cnt_RNI1K71Q1[18]:A, +Initial_blinking_SW2/cnt_RNI1K71Q1[18]:B,11210 +Initial_blinking_SW2/cnt_RNI1K71Q1[18]:C,17189 +Initial_blinking_SW2/cnt_RNI1K71Q1[18]:D, +Initial_blinking_SW2/cnt_RNI1K71Q1[18]:FCI,10904 +Initial_blinking_SW2/cnt_RNI1K71Q1[18]:FCO,10904 +Initial_blinking_SW2/cnt_RNI1K71Q1[18]:S,11057 +Initial_blinking_SW1/cnt[10]:ADn, +Initial_blinking_SW1/cnt[10]:ALn,16174 +Initial_blinking_SW1/cnt[10]:CLK,11795 +Initial_blinking_SW1/cnt[10]:D,12401 +Initial_blinking_SW1/cnt[10]:EN, +Initial_blinking_SW1/cnt[10]:LAT, +Initial_blinking_SW1/cnt[10]:Q,11795 +Initial_blinking_SW1/cnt[10]:SD, +Initial_blinking_SW1/cnt[10]:SLn, +Initial_blinking_SW1/cnt_RNIQAR44[0]:A, +Initial_blinking_SW1/cnt_RNIQAR44[0]:B,12116 +Initial_blinking_SW1/cnt_RNIQAR44[0]:C,16882 +Initial_blinking_SW1/cnt_RNIQAR44[0]:D, +Initial_blinking_SW1/cnt_RNIQAR44[0]:FCI,13399 +Initial_blinking_SW1/cnt_RNIQAR44[0]:FCO,12116 +Initial_blinking_SW1/cnt_RNIQAR44[0]:S,12554 +Fast_clk_SW1/cnt_RNI396K9[2]:A, +Fast_clk_SW1/cnt_RNI396K9[2]:B,12091 +Fast_clk_SW1/cnt_RNI396K9[2]:C,16939 +Fast_clk_SW1/cnt_RNI396K9[2]:D, +Fast_clk_SW1/cnt_RNI396K9[2]:FCI,12053 +Fast_clk_SW1/cnt_RNI396K9[2]:FCO,12053 +Fast_clk_SW1/cnt_RNI396K9[2]:S,12471 +Fast_clk_SW1/cnt[20]:ADn, +Fast_clk_SW1/cnt[20]:ALn,16174 +Fast_clk_SW1/cnt[20]:CLK,13115 +Fast_clk_SW1/cnt[20]:D,12129 +Fast_clk_SW1/cnt[20]:EN, +Fast_clk_SW1/cnt[20]:LAT, +Fast_clk_SW1/cnt[20]:Q,13115 +Fast_clk_SW1/cnt[20]:SD, +Fast_clk_SW1/cnt[20]:SLn, +Clear_outputs/reset:ADn, +Clear_outputs/reset:ALn, +Clear_outputs/reset:CLK, +Clear_outputs/reset:D, +Clear_outputs/reset:EN, +Clear_outputs/reset:LAT, +Clear_outputs/reset:Q, +Clear_outputs/reset:SD, +Clear_outputs/reset:SLn, +Fast_clk_SW2/un14_cntlto31_0_o3_0:A,13542 +Fast_clk_SW2/un14_cntlto31_0_o3_0:B,13492 +Fast_clk_SW2/un14_cntlto31_0_o3_0:C,12236 +Fast_clk_SW2/un14_cntlto31_0_o3_0:D,12026 +Fast_clk_SW2/un14_cntlto31_0_o3_0:Y,12026 +red_led1_obuf/U0/U_IOOUTFF:A, +red_led1_obuf/U0/U_IOOUTFF:Y, +Initial_blinking_SW2/cnt[10]:ADn, +Initial_blinking_SW2/cnt[10]:ALn,16174 +Initial_blinking_SW2/cnt[10]:CLK,11102 +Initial_blinking_SW2/cnt[10]:D,11193 +Initial_blinking_SW2/cnt[10]:EN, +Initial_blinking_SW2/cnt[10]:LAT, +Initial_blinking_SW2/cnt[10]:Q,11102 +Initial_blinking_SW2/cnt[10]:SD, +Initial_blinking_SW2/cnt[10]:SLn, +Initial_blinking_SW2/cnt_RNIRE31I[4]:A, +Initial_blinking_SW2/cnt_RNIRE31I[4]:B,10972 +Initial_blinking_SW2/cnt_RNIRE31I[4]:C,16939 +Initial_blinking_SW2/cnt_RNIRE31I[4]:D, +Initial_blinking_SW2/cnt_RNIRE31I[4]:FCI,10904 +Initial_blinking_SW2/cnt_RNIRE31I[4]:FCO,10904 +Initial_blinking_SW2/cnt_RNIRE31I[4]:S,11295 +Initial_blinking_SW1/cnt_RNIM6BHQ[10]:A, +Initial_blinking_SW1/cnt_RNIM6BHQ[10]:B,12306 +Initial_blinking_SW1/cnt_RNIM6BHQ[10]:C,17064 +Initial_blinking_SW1/cnt_RNIM6BHQ[10]:D, +Initial_blinking_SW1/cnt_RNIM6BHQ[10]:FCI,12116 +Initial_blinking_SW1/cnt_RNIM6BHQ[10]:FCO,12116 +Initial_blinking_SW1/cnt_RNIM6BHQ[10]:S,12401 +Fast_clk_SW1/cnt[0]:ADn, +Fast_clk_SW1/cnt[0]:ALn,16174 +Fast_clk_SW1/cnt[0]:CLK,16901 +Fast_clk_SW1/cnt[0]:D,12472 +Fast_clk_SW1/cnt[0]:EN, +Fast_clk_SW1/cnt[0]:LAT, +Fast_clk_SW1/cnt[0]:Q,16901 +Fast_clk_SW1/cnt[0]:SD, +Fast_clk_SW1/cnt[0]:SLn, +Fast_clk_SW2/cnt_RNI5IPL8[1]:A, +Fast_clk_SW2/cnt_RNI5IPL8[1]:B,12045 +Fast_clk_SW2/cnt_RNI5IPL8[1]:C,16901 +Fast_clk_SW2/cnt_RNI5IPL8[1]:D, +Fast_clk_SW2/cnt_RNI5IPL8[1]:FCI,12026 +Fast_clk_SW2/cnt_RNI5IPL8[1]:FCO,12026 +Fast_clk_SW2/cnt_RNI5IPL8[1]:S,12464 +Fast_clk_SW1/cnt[2]:ADn, +Fast_clk_SW1/cnt[2]:ALn,16174 +Fast_clk_SW1/cnt[2]:CLK,16939 +Fast_clk_SW1/cnt[2]:D,12471 +Fast_clk_SW1/cnt[2]:EN, +Fast_clk_SW1/cnt[2]:LAT, +Fast_clk_SW1/cnt[2]:Q,16939 +Fast_clk_SW1/cnt[2]:SD, +Fast_clk_SW1/cnt[2]:SLn, +Fast_clk_SW2/cnt_RNIGBJ5N[6]:A, +Fast_clk_SW2/cnt_RNIGBJ5N[6]:B,12140 +Fast_clk_SW2/cnt_RNIGBJ5N[6]:C,16988 +Fast_clk_SW2/cnt_RNIGBJ5N[6]:D, +Fast_clk_SW2/cnt_RNIGBJ5N[6]:FCI,12026 +Fast_clk_SW2/cnt_RNIGBJ5N[6]:FCO,12026 +Fast_clk_SW2/cnt_RNIGBJ5N[6]:S,12387 +green_led1_obuf/U0/U_IOENFF:A, +green_led1_obuf/U0/U_IOENFF:Y, +Fast_clk_SW2/un14_cntlto31_0_o3_0_RNIA4EM1:A,14701 +Fast_clk_SW2/un14_cntlto31_0_o3_0_RNIA4EM1:B,14651 +Fast_clk_SW2/un14_cntlto31_0_o3_0_RNIA4EM1:C,12026 +Fast_clk_SW2/un14_cntlto31_0_o3_0_RNIA4EM1:D,14395 +Fast_clk_SW2/un14_cntlto31_0_o3_0_RNIA4EM1:Y,12026 +Initial_blinking_SW2/cnt[21]:ADn, +Initial_blinking_SW2/cnt[21]:ALn,16174 +Initial_blinking_SW2/cnt[21]:CLK,13220 +Initial_blinking_SW2/cnt[21]:D,11006 +Initial_blinking_SW2/cnt[21]:EN, +Initial_blinking_SW2/cnt[21]:LAT, +Initial_blinking_SW2/cnt[21]:Q,13220 +Initial_blinking_SW2/cnt[21]:SD, +Initial_blinking_SW2/cnt[21]:SLn, +Initial_blinking_SW2/cnt_RNIGG66O[6]:A, +Initial_blinking_SW2/cnt_RNIGG66O[6]:B,11006 +Initial_blinking_SW2/cnt_RNIGG66O[6]:C,16977 +Initial_blinking_SW2/cnt_RNIGG66O[6]:D, +Initial_blinking_SW2/cnt_RNIGG66O[6]:FCI,10904 +Initial_blinking_SW2/cnt_RNIGG66O[6]:FCO,10904 +Initial_blinking_SW2/cnt_RNIGG66O[6]:S,11261 +Initial_blinking_SW2/cnt_RNI5VK3L[5]:A, +Initial_blinking_SW2/cnt_RNI5VK3L[5]:B,10989 +Initial_blinking_SW2/cnt_RNI5VK3L[5]:C,16958 +Initial_blinking_SW2/cnt_RNI5VK3L[5]:D, +Initial_blinking_SW2/cnt_RNI5VK3L[5]:FCI,10904 +Initial_blinking_SW2/cnt_RNI5VK3L[5]:FCO,10904 +Initial_blinking_SW2/cnt_RNI5VK3L[5]:S,11278 +Initial_blinking_SW1/cnt[2]:ADn, +Initial_blinking_SW1/cnt[2]:ALn,16174 +Initial_blinking_SW1/cnt[2]:CLK,16920 +Initial_blinking_SW1/cnt[2]:D,12553 +Initial_blinking_SW1/cnt[2]:EN, +Initial_blinking_SW1/cnt[2]:LAT, +Initial_blinking_SW1/cnt[2]:Q,16920 +Initial_blinking_SW1/cnt[2]:SD, +Initial_blinking_SW1/cnt[2]:SLn, +Initial_blinking_SW2/cnt_RNIIVHUE[3]:A, +Initial_blinking_SW2/cnt_RNIIVHUE[3]:B,10955 +Initial_blinking_SW2/cnt_RNIIVHUE[3]:C,16920 +Initial_blinking_SW2/cnt_RNIIVHUE[3]:D, +Initial_blinking_SW2/cnt_RNIIVHUE[3]:FCI,10904 +Initial_blinking_SW2/cnt_RNIIVHUE[3]:FCO,10904 +Initial_blinking_SW2/cnt_RNIIVHUE[3]:S,11312 +Initial_blinking_SW2/cnt_RNINS7GV1[20]:A, +Initial_blinking_SW2/cnt_RNINS7GV1[20]:B,11244 +Initial_blinking_SW2/cnt_RNINS7GV1[20]:C,17227 +Initial_blinking_SW2/cnt_RNINS7GV1[20]:D, +Initial_blinking_SW2/cnt_RNINS7GV1[20]:FCI,10904 +Initial_blinking_SW2/cnt_RNINS7GV1[20]:FCO,10904 +Initial_blinking_SW2/cnt_RNINS7GV1[20]:S,11023 +Initial_blinking_SW1/cnt[5]:ADn, +Initial_blinking_SW1/cnt[5]:ALn,16174 +Initial_blinking_SW1/cnt[5]:CLK,16977 +Initial_blinking_SW1/cnt[5]:D,12496 +Initial_blinking_SW1/cnt[5]:EN, +Initial_blinking_SW1/cnt[5]:LAT, +Initial_blinking_SW1/cnt[5]:Q,16977 +Initial_blinking_SW1/cnt[5]:SD, +Initial_blinking_SW1/cnt[5]:SLn, +Fast_clk_SW1/cnt_RNI2KDND1[17]:A, +Fast_clk_SW1/cnt_RNI2KDND1[17]:B,12376 +Fast_clk_SW1/cnt_RNI2KDND1[17]:C,17216 +Fast_clk_SW1/cnt_RNI2KDND1[17]:D, +Fast_clk_SW1/cnt_RNI2KDND1[17]:FCI,12053 +Fast_clk_SW1/cnt_RNI2KDND1[17]:FCO,12053 +Fast_clk_SW1/cnt_RNI2KDND1[17]:S,12186 +Fast_clk_SW1/cnt_RNIME5GT[10]:A, +Fast_clk_SW1/cnt_RNIME5GT[10]:B,12243 +Fast_clk_SW1/cnt_RNIME5GT[10]:C,17075 +Fast_clk_SW1/cnt_RNIME5GT[10]:D, +Fast_clk_SW1/cnt_RNIME5GT[10]:FCI,12053 +Fast_clk_SW1/cnt_RNIME5GT[10]:FCO,12053 +Fast_clk_SW1/cnt_RNIME5GT[10]:S,12319 +Initial_blinking_SW1/cnt[6]:ADn, +Initial_blinking_SW1/cnt[6]:ALn,16174 +Initial_blinking_SW1/cnt[6]:CLK,12748 +Initial_blinking_SW1/cnt[6]:D,12477 +Initial_blinking_SW1/cnt[6]:EN, +Initial_blinking_SW1/cnt[6]:LAT, +Initial_blinking_SW1/cnt[6]:Q,12748 +Initial_blinking_SW1/cnt[6]:SD, +Initial_blinking_SW1/cnt[6]:SLn, +Fast_clk_SW2/cnt[13]:ADn, +Fast_clk_SW2/cnt[13]:ALn,16174 +Fast_clk_SW2/cnt[13]:CLK,12333 +Fast_clk_SW2/cnt[13]:D,12254 +Fast_clk_SW2/cnt[13]:EN, +Fast_clk_SW2/cnt[13]:LAT, +Fast_clk_SW2/cnt[13]:Q,12333 +Fast_clk_SW2/cnt[13]:SD, +Fast_clk_SW2/cnt[13]:SLn, +Initial_blinking_SW2/cnt_RNIDPA541[10]:A, +Initial_blinking_SW2/cnt_RNIDPA541[10]:B,11074 +Initial_blinking_SW2/cnt_RNIDPA541[10]:C,17045 +Initial_blinking_SW2/cnt_RNIDPA541[10]:D, +Initial_blinking_SW2/cnt_RNIDPA541[10]:FCI,10904 +Initial_blinking_SW2/cnt_RNIDPA541[10]:FCO,10904 +Initial_blinking_SW2/cnt_RNIDPA541[10]:S,11193 +green_led1_obuf/U0/U_IOOUTFF:A, +green_led1_obuf/U0/U_IOOUTFF:Y, +Fast_clk_SW1/cnt[12]:ADn, +Fast_clk_SW1/cnt[12]:ALn,16174 +Fast_clk_SW1/cnt[12]:CLK,12360 +Fast_clk_SW1/cnt[12]:D,12281 +Fast_clk_SW1/cnt[12]:EN, +Fast_clk_SW1/cnt[12]:LAT, +Fast_clk_SW1/cnt[12]:Q,12360 +Fast_clk_SW1/cnt[12]:SD, +Fast_clk_SW1/cnt[12]:SLn, +clk_ibuf/U0/U_IOPAD:PAD, +clk_ibuf/U0/U_IOPAD:Y, +red_led2_obuf/U0/U_IOOUTFF:A, +red_led2_obuf/U0/U_IOOUTFF:Y, +Fast_clk_SW2/cnt_RNI5E4RQ1[17]:A, +Fast_clk_SW2/cnt_RNI5E4RQ1[17]:B,12349 +Fast_clk_SW2/cnt_RNI5E4RQ1[17]:C,17189 +Fast_clk_SW2/cnt_RNI5E4RQ1[17]:D, +Fast_clk_SW2/cnt_RNI5E4RQ1[17]:FCI,12026 +Fast_clk_SW2/cnt_RNI5E4RQ1[17]:FCO,12026 +Fast_clk_SW2/cnt_RNI5E4RQ1[17]:S,12178 +Fast_clk_SW1/cnt_RNI9GDAP1[22]:A, +Fast_clk_SW1/cnt_RNI9GDAP1[22]:B,12471 +Fast_clk_SW1/cnt_RNI9GDAP1[22]:C,17256 +Fast_clk_SW1/cnt_RNI9GDAP1[22]:D, +Fast_clk_SW1/cnt_RNI9GDAP1[22]:FCI,12053 +Fast_clk_SW1/cnt_RNI9GDAP1[22]:FCO,12053 +Fast_clk_SW1/cnt_RNI9GDAP1[22]:S,12091 +Fast_clk_SW1/cnt[6]:ADn, +Fast_clk_SW1/cnt[6]:ALn,16174 +Fast_clk_SW1/cnt[6]:CLK,11512 +Fast_clk_SW1/cnt[6]:D,12395 +Fast_clk_SW1/cnt[6]:EN, +Fast_clk_SW1/cnt[6]:LAT, +Fast_clk_SW1/cnt[6]:Q,11512 +Fast_clk_SW1/cnt[6]:SD, +Fast_clk_SW1/cnt[6]:SLn, +Fast_clk_SW2/cnt_RNIVTQ8K[5]:A, +Fast_clk_SW2/cnt_RNIVTQ8K[5]:B,12121 +Fast_clk_SW2/cnt_RNIVTQ8K[5]:C,16977 +Fast_clk_SW2/cnt_RNIVTQ8K[5]:D, +Fast_clk_SW2/cnt_RNIVTQ8K[5]:FCI,12026 +Fast_clk_SW2/cnt_RNIVTQ8K[5]:FCO,12026 +Fast_clk_SW2/cnt_RNIVTQ8K[5]:S,12406 +Initial_blinking_SW2/cnt[2]:ADn, +Initial_blinking_SW2/cnt[2]:ALn,16174 +Initial_blinking_SW2/cnt[2]:CLK,16901 +Initial_blinking_SW2/cnt[2]:D,11322 +Initial_blinking_SW2/cnt[2]:EN, +Initial_blinking_SW2/cnt[2]:LAT, +Initial_blinking_SW2/cnt[2]:Q,16901 +Initial_blinking_SW2/cnt[2]:SD, +Initial_blinking_SW2/cnt[2]:SLn, +Fast_clk_SW2/cnt_RNI9GKEI2[24]:A, +Fast_clk_SW2/cnt_RNI9GKEI2[24]:B,12464 +Fast_clk_SW2/cnt_RNI9GKEI2[24]:C,17256 +Fast_clk_SW2/cnt_RNI9GKEI2[24]:D, +Fast_clk_SW2/cnt_RNI9GKEI2[24]:FCI,12026 +Fast_clk_SW2/cnt_RNI9GKEI2[24]:FCO,12026 +Fast_clk_SW2/cnt_RNI9GKEI2[24]:S,12045 +Initial_blinking_SW1/cnt_RNI94SRA[3]:A, +Initial_blinking_SW1/cnt_RNI94SRA[3]:B,12173 +Initial_blinking_SW1/cnt_RNI94SRA[3]:C,16939 +Initial_blinking_SW1/cnt_RNI94SRA[3]:D, +Initial_blinking_SW1/cnt_RNI94SRA[3]:FCI,12116 +Initial_blinking_SW1/cnt_RNI94SRA[3]:FCO,12116 +Initial_blinking_SW1/cnt_RNI94SRA[3]:S,12534 +Fast_clk_SW2/cnt[24]:ADn, +Fast_clk_SW2/cnt[24]:ALn,16174 +Fast_clk_SW2/cnt[24]:CLK,14272 +Fast_clk_SW2/cnt[24]:D,12045 +Fast_clk_SW2/cnt[24]:EN, +Fast_clk_SW2/cnt[24]:LAT, +Fast_clk_SW2/cnt[24]:Q,14272 +Fast_clk_SW2/cnt[24]:SD, +Fast_clk_SW2/cnt[24]:SLn, +Fast_clk_SW1/cnt[1]:ADn, +Fast_clk_SW1/cnt[1]:ALn,16174 +Fast_clk_SW1/cnt[1]:CLK,16920 +Fast_clk_SW1/cnt[1]:D,12472 +Fast_clk_SW1/cnt[1]:EN, +Fast_clk_SW1/cnt[1]:LAT, +Fast_clk_SW1/cnt[1]:Q,16920 +Fast_clk_SW1/cnt[1]:SD, +Fast_clk_SW1/cnt[1]:SLn, +Initial_blinking_SW2/cnt[8]:ADn, +Initial_blinking_SW2/cnt[8]:ALn,16174 +Initial_blinking_SW2/cnt[8]:CLK,10904 +Initial_blinking_SW2/cnt[8]:D,11227 +Initial_blinking_SW2/cnt[8]:EN, +Initial_blinking_SW2/cnt[8]:LAT, +Initial_blinking_SW2/cnt[8]:Q,10904 +Initial_blinking_SW2/cnt[8]:SD, +Initial_blinking_SW2/cnt[8]:SLn, +Fast_clk_SW2/cnt_RNI0EJV91[12]:A, +Fast_clk_SW2/cnt_RNI0EJV91[12]:B,12254 +Fast_clk_SW2/cnt_RNI0EJV91[12]:C,17102 +Fast_clk_SW2/cnt_RNI0EJV91[12]:D, +Fast_clk_SW2/cnt_RNI0EJV91[12]:FCI,12026 +Fast_clk_SW2/cnt_RNI0EJV91[12]:FCO,12026 +Fast_clk_SW2/cnt_RNI0EJV91[12]:S,12273 +Fast_clk_SW1/cnt[19]:ADn, +Fast_clk_SW1/cnt[19]:ALn,16174 +Fast_clk_SW1/cnt[19]:CLK,13018 +Fast_clk_SW1/cnt[19]:D,12148 +Fast_clk_SW1/cnt[19]:EN, +Fast_clk_SW1/cnt[19]:LAT, +Fast_clk_SW1/cnt[19]:Q,13018 +Fast_clk_SW1/cnt[19]:SD, +Fast_clk_SW1/cnt[19]:SLn, +SW1_ibuf/U0/U_IOPAD:PAD, +SW1_ibuf/U0/U_IOPAD:Y, +Fast_clk_SW2/cnt[6]:ADn, +Fast_clk_SW2/cnt[6]:ALn,16174 +Fast_clk_SW2/cnt[6]:CLK,12719 +Fast_clk_SW2/cnt[6]:D,12387 +Fast_clk_SW2/cnt[6]:EN, +Fast_clk_SW2/cnt[6]:LAT, +Fast_clk_SW2/cnt[6]:Q,12719 +Fast_clk_SW2/cnt[6]:SD, +Fast_clk_SW2/cnt[6]:SLn, +Fast_clk_SW1/cnt_RNI26U37[1]:A, +Fast_clk_SW1/cnt_RNI26U37[1]:B,12072 +Fast_clk_SW1/cnt_RNI26U37[1]:C,16920 +Fast_clk_SW1/cnt_RNI26U37[1]:D, +Fast_clk_SW1/cnt_RNI26U37[1]:FCI,12053 +Fast_clk_SW1/cnt_RNI26U37[1]:FCO,12053 +Fast_clk_SW1/cnt_RNI26U37[1]:S,12472 +Initial_blinking_SW2/cnt_RNI34FP8[1]:A, +Initial_blinking_SW2/cnt_RNI34FP8[1]:B,10921 +Initial_blinking_SW2/cnt_RNI34FP8[1]:C,16882 +Initial_blinking_SW2/cnt_RNI34FP8[1]:D, +Initial_blinking_SW2/cnt_RNI34FP8[1]:FCI,10904 +Initial_blinking_SW2/cnt_RNI34FP8[1]:FCO,10904 +Initial_blinking_SW2/cnt_RNI34FP8[1]:S,11322 +Fast_clk_SW2/cnt[15]:ADn, +Fast_clk_SW2/cnt[15]:ALn,16174 +Fast_clk_SW2/cnt[15]:CLK,13542 +Fast_clk_SW2/cnt[15]:D,12216 +Fast_clk_SW2/cnt[15]:EN, +Fast_clk_SW2/cnt[15]:LAT, +Fast_clk_SW2/cnt[15]:Q,13542 +Fast_clk_SW2/cnt[15]:SD, +Fast_clk_SW2/cnt[15]:SLn, +Fast_clk_SW2/un7_cntlto31_0_0:A,17547 +Fast_clk_SW2/un7_cntlto31_0_0:B,17491 +Fast_clk_SW2/un7_cntlto31_0_0:C,15044 +Fast_clk_SW2/un7_cntlto31_0_0:D,11512 +Fast_clk_SW2/un7_cntlto31_0_0:Y,11512 +Fast_clk_SW1/cnt[18]:ADn, +Fast_clk_SW1/cnt[18]:ALn,16174 +Fast_clk_SW1/cnt[18]:CLK,12900 +Fast_clk_SW1/cnt[18]:D,12167 +Fast_clk_SW1/cnt[18]:EN, +Fast_clk_SW1/cnt[18]:LAT, +Fast_clk_SW1/cnt[18]:Q,12900 +Fast_clk_SW1/cnt[18]:SD, +Fast_clk_SW1/cnt[18]:SLn, +Initial_blinking_SW2/cnt_RNIFU83F1[14]:A, +Initial_blinking_SW2/cnt_RNIFU83F1[14]:B,11142 +Initial_blinking_SW2/cnt_RNIFU83F1[14]:C,17113 +Initial_blinking_SW2/cnt_RNIFU83F1[14]:D, +Initial_blinking_SW2/cnt_RNIFU83F1[14]:FCI,10904 +Initial_blinking_SW2/cnt_RNIFU83F1[14]:FCO,10904 +Initial_blinking_SW2/cnt_RNIFU83F1[14]:S,11125 +Initial_blinking_SW2/cnt[23]:ADn, +Initial_blinking_SW2/cnt[23]:ALn,16174 +Initial_blinking_SW2/cnt[23]:CLK,14524 +Initial_blinking_SW2/cnt[23]:D,10972 +Initial_blinking_SW2/cnt[23]:EN, +Initial_blinking_SW2/cnt[23]:LAT, +Initial_blinking_SW2/cnt[23]:Q,14524 +Initial_blinking_SW2/cnt[23]:SD, +Initial_blinking_SW2/cnt[23]:SLn, +Initial_blinking_SW1/cnt[3]:ADn, +Initial_blinking_SW1/cnt[3]:ALn,16174 +Initial_blinking_SW1/cnt[3]:CLK,16939 +Initial_blinking_SW1/cnt[3]:D,12534 +Initial_blinking_SW1/cnt[3]:EN, +Initial_blinking_SW1/cnt[3]:LAT, +Initial_blinking_SW1/cnt[3]:Q,16939 +Initial_blinking_SW1/cnt[3]:SD, +Initial_blinking_SW1/cnt[3]:SLn, +Initial_blinking_SW2/cnt[25]:ADn, +Initial_blinking_SW2/cnt[25]:ALn,16174 +Initial_blinking_SW2/cnt[25]:CLK,15253 +Initial_blinking_SW2/cnt[25]:D,10934 +Initial_blinking_SW2/cnt[25]:EN, +Initial_blinking_SW2/cnt[25]:LAT, +Initial_blinking_SW2/cnt[25]:Q,15253 +Initial_blinking_SW2/cnt[25]:SD, +Initial_blinking_SW2/cnt[25]:SLn, +Fast_clk_SW2/cnt_RNI9GQA82[21]:A, +Fast_clk_SW2/cnt_RNI9GQA82[21]:B,12425 +Fast_clk_SW2/cnt_RNI9GQA82[21]:C,17272 +Fast_clk_SW2/cnt_RNI9GQA82[21]:D, +Fast_clk_SW2/cnt_RNI9GQA82[21]:FCI,12026 +Fast_clk_SW2/cnt_RNI9GQA82[21]:FCO,12026 +Fast_clk_SW2/cnt_RNI9GQA82[21]:S,12102 +Fast_clk_SW1/un7_cntlto31_0_a2_0:A,13997 +Fast_clk_SW1/un7_cntlto31_0_a2_0:B,13941 +Fast_clk_SW1/un7_cntlto31_0_a2_0:C,12703 +Fast_clk_SW1/un7_cntlto31_0_a2_0:D,11512 +Fast_clk_SW1/un7_cntlto31_0_a2_0:Y,11512 +Initial_blinking_SW2/cnt_RNIPVQ5D2[25]:A, +Initial_blinking_SW2/cnt_RNIPVQ5D2[25]:B,11322 +Initial_blinking_SW2/cnt_RNIPVQ5D2[25]:C,17264 +Initial_blinking_SW2/cnt_RNIPVQ5D2[25]:D, +Initial_blinking_SW2/cnt_RNIPVQ5D2[25]:FCI,10904 +Initial_blinking_SW2/cnt_RNIPVQ5D2[25]:FCO,10904 +Initial_blinking_SW2/cnt_RNIPVQ5D2[25]:S,10934 +Fast_clk_SW1/un14_cntlto31_0_o2_3:A,13165 +Fast_clk_SW1/un14_cntlto31_0_o2_3:B,13115 +Fast_clk_SW1/un14_cntlto31_0_o2_3:C,13018 +Fast_clk_SW1/un14_cntlto31_0_o2_3:D,12900 +Fast_clk_SW1/un14_cntlto31_0_o2_3:Y,12900 +Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1:A,12116 +Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1:B,13239 +Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1:C,13178 +Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1:D,15279 +Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1:FCI, +Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1:FCO,13399 +Initial_blinking_SW1/un14_cntlto31_0_o3_RNINP5T1:Y,12116 +Initial_blinking_SW2/cnt_RNI2LPM72[23]:A, +Initial_blinking_SW2/cnt_RNI2LPM72[23]:B,11295 +Initial_blinking_SW2/cnt_RNI2LPM72[23]:C,17264 +Initial_blinking_SW2/cnt_RNI2LPM72[23]:D, +Initial_blinking_SW2/cnt_RNI2LPM72[23]:FCI,10904 +Initial_blinking_SW2/cnt_RNI2LPM72[23]:FCO,10904 +Initial_blinking_SW2/cnt_RNI2LPM72[23]:S,10972 +Initial_blinking_SW1/un14_cntlto31_0_o3:A,14602 +Initial_blinking_SW1/un14_cntlto31_0_o3:B,13239 +Initial_blinking_SW1/un14_cntlto31_0_o3:C,14455 +Initial_blinking_SW1/un14_cntlto31_0_o3:D,14325 +Initial_blinking_SW1/un14_cntlto31_0_o3:Y,13239 +green_led2_obuf/U0/U_IOENFF:A, +green_led2_obuf/U0/U_IOENFF:Y, +Initial_blinking_SW2/cnt_RNI3TN9N1[17]:A, +Initial_blinking_SW2/cnt_RNI3TN9N1[17]:B,11193 +Initial_blinking_SW2/cnt_RNI3TN9N1[17]:C,17170 +Initial_blinking_SW2/cnt_RNI3TN9N1[17]:D, +Initial_blinking_SW2/cnt_RNI3TN9N1[17]:FCI,10904 +Initial_blinking_SW2/cnt_RNI3TN9N1[17]:FCO,10904 +Initial_blinking_SW2/cnt_RNI3TN9N1[17]:S,11074 +Initial_blinking_SW2/cnt_RNIS2O8R[7]:A, +Initial_blinking_SW2/cnt_RNIS2O8R[7]:B,11023 +Initial_blinking_SW2/cnt_RNIS2O8R[7]:C,16988 +Initial_blinking_SW2/cnt_RNIS2O8R[7]:D, +Initial_blinking_SW2/cnt_RNIS2O8R[7]:FCI,10904 +Initial_blinking_SW2/cnt_RNIS2O8R[7]:FCO,10904 +Initial_blinking_SW2/cnt_RNIS2O8R[7]:S,11244 +Fast_clk_SW2/cnt_RNI9H17U1[18]:A, +Fast_clk_SW2/cnt_RNI9H17U1[18]:B,12368 +Fast_clk_SW2/cnt_RNI9H17U1[18]:C,17216 +Fast_clk_SW2/cnt_RNI9H17U1[18]:D, +Fast_clk_SW2/cnt_RNI9H17U1[18]:FCI,12026 +Fast_clk_SW2/cnt_RNI9H17U1[18]:FCO,12026 +Fast_clk_SW2/cnt_RNI9H17U1[18]:S,12159 +Fast_clk_SW1/cnt_RNI73BQV[11]:A, +Fast_clk_SW1/cnt_RNI73BQV[11]:B,12262 +Fast_clk_SW1/cnt_RNI73BQV[11]:C,17102 +Fast_clk_SW1/cnt_RNI73BQV[11]:D, +Fast_clk_SW1/cnt_RNI73BQV[11]:FCI,12053 +Fast_clk_SW1/cnt_RNI73BQV[11]:FCO,12053 +Fast_clk_SW1/cnt_RNI73BQV[11]:S,12300 +Fast_clk_SW1/cnt[24]:ADn, +Fast_clk_SW1/cnt[24]:ALn,16174 +Fast_clk_SW1/cnt[24]:CLK,14429 +Fast_clk_SW1/cnt[24]:D,12053 +Fast_clk_SW1/cnt[24]:EN, +Fast_clk_SW1/cnt[24]:LAT, +Fast_clk_SW1/cnt[24]:Q,14429 +Fast_clk_SW1/cnt[24]:SD, +Fast_clk_SW1/cnt[24]:SLn, +Initial_blinking_SW2/cnt_RNI678IK1[16]:A, +Initial_blinking_SW2/cnt_RNI678IK1[16]:B,11176 +Initial_blinking_SW2/cnt_RNI678IK1[16]:C,17151 +Initial_blinking_SW2/cnt_RNI678IK1[16]:D, +Initial_blinking_SW2/cnt_RNI678IK1[16]:FCI,10904 +Initial_blinking_SW2/cnt_RNI678IK1[16]:FCO,10904 +Initial_blinking_SW2/cnt_RNI678IK1[16]:S,11091 +Initial_blinking_SW2/cnt_RNIOCCK2[27]:A,15697 +Initial_blinking_SW2/cnt_RNIOCCK2[27]:B,10904 +Initial_blinking_SW2/cnt_RNIOCCK2[27]:C,15540 +Initial_blinking_SW2/cnt_RNIOCCK2[27]:D,15253 +Initial_blinking_SW2/cnt_RNIOCCK2[27]:FCI, +Initial_blinking_SW2/cnt_RNIOCCK2[27]:FCO,12193 +Initial_blinking_SW2/cnt_RNIOCCK2[27]:Y,10904 +Initial_blinking_SW1/cnt_RNIGVTE31[14]:A, +Initial_blinking_SW1/cnt_RNIGVTE31[14]:B,12382 +Initial_blinking_SW1/cnt_RNIGVTE31[14]:C,17140 +Initial_blinking_SW1/cnt_RNIGVTE31[14]:D, +Initial_blinking_SW1/cnt_RNIGVTE31[14]:FCI,12116 +Initial_blinking_SW1/cnt_RNIGVTE31[14]:FCO,12116 +Initial_blinking_SW1/cnt_RNIGVTE31[14]:S,12325 +Fast_clk_SW2/cnt_RNIL94VS[8]:A, +Fast_clk_SW2/cnt_RNIL94VS[8]:B,12178 +Fast_clk_SW2/cnt_RNIL94VS[8]:C,17026 +Fast_clk_SW2/cnt_RNIL94VS[8]:D, +Fast_clk_SW2/cnt_RNIL94VS[8]:FCI,12026 +Fast_clk_SW2/cnt_RNIL94VS[8]:FCO,12026 +Fast_clk_SW2/cnt_RNIL94VS[8]:S,12349 +Fast_clk_SW2/cnt[10]:ADn, +Fast_clk_SW2/cnt[10]:ALn,16174 +Fast_clk_SW2/cnt[10]:CLK,11766 +Fast_clk_SW2/cnt[10]:D,12311 +Fast_clk_SW2/cnt[10]:EN, +Fast_clk_SW2/cnt[10]:LAT, +Fast_clk_SW2/cnt[10]:Q,11766 +Fast_clk_SW2/cnt[10]:SD, +Fast_clk_SW2/cnt[10]:SLn, +Initial_blinking_SW2/cnt[1]:ADn, +Initial_blinking_SW2/cnt[1]:ALn,16174 +Initial_blinking_SW2/cnt[1]:CLK,16882 +Initial_blinking_SW2/cnt[1]:D,11322 +Initial_blinking_SW2/cnt[1]:EN, +Initial_blinking_SW2/cnt[1]:LAT, +Initial_blinking_SW2/cnt[1]:Q,16882 +Initial_blinking_SW2/cnt[1]:SD, +Initial_blinking_SW2/cnt[1]:SLn, +SW1_ibuf/U0/U_IOINFF:A, +SW1_ibuf/U0/U_IOINFF:Y, +ip_interface_inst:A, +ip_interface_inst:B, +ip_interface_inst:C, +Fast_clk_SW2/un7_cntlto31_0_a2:A,15147 +Fast_clk_SW2/un7_cntlto31_0_a2:B,15091 +Fast_clk_SW2/un7_cntlto31_0_a2:C,11512 +Fast_clk_SW2/un7_cntlto31_0_a2:D,14875 +Fast_clk_SW2/un7_cntlto31_0_a2:Y,11512 +Initial_blinking_SW2/tmp_clk_RNO_1:A,15306 +Initial_blinking_SW2/tmp_clk_RNO_1:B,12788 +Initial_blinking_SW2/tmp_clk_RNO_1:C,15162 +Initial_blinking_SW2/tmp_clk_RNO_1:D,15042 +Initial_blinking_SW2/tmp_clk_RNO_1:Y,12788 +Initial_blinking_SW1/tmp_clk:ADn, +Initial_blinking_SW1/tmp_clk:ALn,16174 +Initial_blinking_SW1/tmp_clk:CLK,17329 +Initial_blinking_SW1/tmp_clk:D,11541 +Initial_blinking_SW1/tmp_clk:EN, +Initial_blinking_SW1/tmp_clk:LAT, +Initial_blinking_SW1/tmp_clk:Q,17329 +Initial_blinking_SW1/tmp_clk:SD, +Initial_blinking_SW1/tmp_clk:SLn, +Fast_clk_SW2/cnt_RNI8FOMB2[22]:A, +Fast_clk_SW2/cnt_RNI8FOMB2[22]:B,12444 +Fast_clk_SW2/cnt_RNI8FOMB2[22]:C,17272 +Fast_clk_SW2/cnt_RNI8FOMB2[22]:D, +Fast_clk_SW2/cnt_RNI8FOMB2[22]:FCI,12026 +Fast_clk_SW2/cnt_RNI8FOMB2[22]:FCO,12026 +Fast_clk_SW2/cnt_RNI8FOMB2[22]:S,12083 +Fast_clk_SW2/cnt[9]:ADn, +Fast_clk_SW2/cnt[9]:ALn,16174 +Fast_clk_SW2/cnt[9]:CLK,11710 +Fast_clk_SW2/cnt[9]:D,12330 +Fast_clk_SW2/cnt[9]:EN, +Fast_clk_SW2/cnt[9]:LAT, +Fast_clk_SW2/cnt[9]:Q,11710 +Fast_clk_SW2/cnt[9]:SD, +Fast_clk_SW2/cnt[9]:SLn, +Initial_blinking_SW2/cnt[5]:ADn, +Initial_blinking_SW2/cnt[5]:ALn,16174 +Initial_blinking_SW2/cnt[5]:CLK,16958 +Initial_blinking_SW2/cnt[5]:D,11278 +Initial_blinking_SW2/cnt[5]:EN, +Initial_blinking_SW2/cnt[5]:LAT, +Initial_blinking_SW2/cnt[5]:Q,16958 +Initial_blinking_SW2/cnt[5]:SD, +Initial_blinking_SW2/cnt[5]:SLn, +Initial_blinking_SW1/cnt[26]:ADn, +Initial_blinking_SW1/cnt[26]:ALn,16174 +Initial_blinking_SW1/cnt[26]:CLK,14549 +Initial_blinking_SW1/cnt[26]:D,12159 +Initial_blinking_SW1/cnt[26]:EN, +Initial_blinking_SW1/cnt[26]:LAT, +Initial_blinking_SW1/cnt[26]:Q,14549 +Initial_blinking_SW1/cnt[26]:SD, +Initial_blinking_SW1/cnt[26]:SLn, +Initial_blinking_SW2/cnt[22]:ADn, +Initial_blinking_SW2/cnt[22]:ALn,16174 +Initial_blinking_SW2/cnt[22]:CLK,13273 +Initial_blinking_SW2/cnt[22]:D,10989 +Initial_blinking_SW2/cnt[22]:EN, +Initial_blinking_SW2/cnt[22]:LAT, +Initial_blinking_SW2/cnt[22]:Q,13273 +Initial_blinking_SW2/cnt[22]:SD, +Initial_blinking_SW2/cnt[22]:SLn, +Initial_blinking_SW1/cnt[17]:ADn, +Initial_blinking_SW1/cnt[17]:ALn,16174 +Initial_blinking_SW1/cnt[17]:CLK,14651 +Initial_blinking_SW1/cnt[17]:D,12268 +Initial_blinking_SW1/cnt[17]:EN, +Initial_blinking_SW1/cnt[17]:LAT, +Initial_blinking_SW1/cnt[17]:Q,14651 +Initial_blinking_SW1/cnt[17]:SD, +Initial_blinking_SW1/cnt[17]:SLn, +Fast_clk_SW2/cnt[5]:ADn, +Fast_clk_SW2/cnt[5]:ALn,16174 +Fast_clk_SW2/cnt[5]:CLK,16977 +Fast_clk_SW2/cnt[5]:D,12406 +Fast_clk_SW2/cnt[5]:EN, +Fast_clk_SW2/cnt[5]:LAT, +Fast_clk_SW2/cnt[5]:Q,16977 +Fast_clk_SW2/cnt[5]:SD, +Fast_clk_SW2/cnt[5]:SLn, +Fast_clk_SW1/cnt[11]:ADn, +Fast_clk_SW1/cnt[11]:ALn,16174 +Fast_clk_SW1/cnt[11]:CLK,12263 +Fast_clk_SW1/cnt[11]:D,12300 +Fast_clk_SW1/cnt[11]:EN, +Fast_clk_SW1/cnt[11]:LAT, +Fast_clk_SW1/cnt[11]:Q,12263 +Fast_clk_SW1/cnt[11]:SD, +Fast_clk_SW1/cnt[11]:SLn, +Initial_blinking_SW1/cnt_RNIBRNOS[11]:A, +Initial_blinking_SW1/cnt_RNIBRNOS[11]:B,12325 +Initial_blinking_SW1/cnt_RNIBRNOS[11]:C,17075 +Initial_blinking_SW1/cnt_RNIBRNOS[11]:D, +Initial_blinking_SW1/cnt_RNIBRNOS[11]:FCI,12116 +Initial_blinking_SW1/cnt_RNIBRNOS[11]:FCO,12116 +Initial_blinking_SW1/cnt_RNIBRNOS[11]:S,12382 +Initial_blinking_SW1/cnt_RNI2IP2J1[21]:A, +Initial_blinking_SW1/cnt_RNI2IP2J1[21]:B,12515 +Initial_blinking_SW1/cnt_RNI2IP2J1[21]:C,17272 +Initial_blinking_SW1/cnt_RNI2IP2J1[21]:D, +Initial_blinking_SW1/cnt_RNI2IP2J1[21]:FCI,12116 +Initial_blinking_SW1/cnt_RNI2IP2J1[21]:FCO,12116 +Initial_blinking_SW1/cnt_RNI2IP2J1[21]:S,12192 +Fast_clk_SW2/cnt[26]:ADn, +Fast_clk_SW2/cnt[26]:ALn,16174 +Fast_clk_SW2/cnt[26]:CLK,14244 +Fast_clk_SW2/cnt[26]:D,12079 +Fast_clk_SW2/cnt[26]:EN, +Fast_clk_SW2/cnt[26]:LAT, +Fast_clk_SW2/cnt[26]:Q,14244 +Fast_clk_SW2/cnt[26]:SD, +Fast_clk_SW2/cnt[26]:SLn, +Fast_clk_SW1/cnt_RNIHV6LJ[6]:A, +Fast_clk_SW1/cnt_RNIHV6LJ[6]:B,12167 +Fast_clk_SW1/cnt_RNIHV6LJ[6]:C,17007 +Fast_clk_SW1/cnt_RNIHV6LJ[6]:D, +Fast_clk_SW1/cnt_RNIHV6LJ[6]:FCI,12053 +Fast_clk_SW1/cnt_RNIHV6LJ[6]:FCO,12053 +Fast_clk_SW1/cnt_RNIHV6LJ[6]:S,12395 +Initial_blinking_SW2/cnt_RNITNTM5[0]:A, +Initial_blinking_SW2/cnt_RNITNTM5[0]:B,10904 +Initial_blinking_SW2/cnt_RNITNTM5[0]:C,16863 +Initial_blinking_SW2/cnt_RNITNTM5[0]:D, +Initial_blinking_SW2/cnt_RNITNTM5[0]:FCI,12193 +Initial_blinking_SW2/cnt_RNITNTM5[0]:FCO,10904 +Initial_blinking_SW2/cnt_RNITNTM5[0]:S,11322 +Initial_blinking_SW2/cnt[17]:ADn, +Initial_blinking_SW2/cnt[17]:ALn,16174 +Initial_blinking_SW2/cnt[17]:CLK,13422 +Initial_blinking_SW2/cnt[17]:D,11074 +Initial_blinking_SW2/cnt[17]:EN, +Initial_blinking_SW2/cnt[17]:LAT, +Initial_blinking_SW2/cnt[17]:Q,13422 +Initial_blinking_SW2/cnt[17]:SD, +Initial_blinking_SW2/cnt[17]:SLn, +Initial_blinking_SW1/cnt[8]:ADn, +Initial_blinking_SW1/cnt[8]:ALn,16174 +Initial_blinking_SW1/cnt[8]:CLK,11651 +Initial_blinking_SW1/cnt[8]:D,12439 +Initial_blinking_SW1/cnt[8]:EN, +Initial_blinking_SW1/cnt[8]:LAT, +Initial_blinking_SW1/cnt[8]:Q,11651 +Initial_blinking_SW1/cnt[8]:SD, +Initial_blinking_SW1/cnt[8]:SLn, +Fast_clk_SW1/un7_cntlto31_0_a2:A,15147 +Fast_clk_SW1/un7_cntlto31_0_a2:B,15091 +Fast_clk_SW1/un7_cntlto31_0_a2:C,11512 +Fast_clk_SW1/un7_cntlto31_0_a2:D,14875 +Fast_clk_SW1/un7_cntlto31_0_a2:Y,11512 +Initial_blinking_SW2/cnt[24]:ADn, +Initial_blinking_SW2/cnt[24]:ALn,16174 +Initial_blinking_SW2/cnt[24]:CLK,13364 +Initial_blinking_SW2/cnt[24]:D,10953 +Initial_blinking_SW2/cnt[24]:EN, +Initial_blinking_SW2/cnt[24]:LAT, +Initial_blinking_SW2/cnt[24]:Q,13364 +Initial_blinking_SW2/cnt[24]:SD, +Initial_blinking_SW2/cnt[24]:SLn, +Initial_blinking_SW2/cnt_RNIFEO722[21]:A, +Initial_blinking_SW2/cnt_RNIFEO722[21]:B,11261 +Initial_blinking_SW2/cnt_RNIFEO722[21]:C,17246 +Initial_blinking_SW2/cnt_RNIFEO722[21]:D, +Initial_blinking_SW2/cnt_RNIFEO722[21]:FCI,10904 +Initial_blinking_SW2/cnt_RNIFEO722[21]:FCO,10904 +Initial_blinking_SW2/cnt_RNIFEO722[21]:S,11006 +Fast_clk_SW1/cnt[17]:ADn, +Fast_clk_SW1/cnt[17]:ALn,16174 +Fast_clk_SW1/cnt[17]:CLK,14132 +Fast_clk_SW1/cnt[17]:D,12186 +Fast_clk_SW1/cnt[17]:EN, +Fast_clk_SW1/cnt[17]:LAT, +Fast_clk_SW1/cnt[17]:Q,14132 +Fast_clk_SW1/cnt[17]:SD, +Fast_clk_SW1/cnt[17]:SLn, +Initial_blinking_SW1/cnt[4]:ADn, +Initial_blinking_SW1/cnt[4]:ALn,16174 +Initial_blinking_SW1/cnt[4]:CLK,16958 +Initial_blinking_SW1/cnt[4]:D,12515 +Initial_blinking_SW1/cnt[4]:EN, +Initial_blinking_SW1/cnt[4]:LAT, +Initial_blinking_SW1/cnt[4]:Q,16958 +Initial_blinking_SW1/cnt[4]:SD, +Initial_blinking_SW1/cnt[4]:SLn, +Fast_clk_SW1/cnt_RNII2RUT1[24]_FCINST1:CO,12104 +Fast_clk_SW1/cnt_RNII2RUT1[24]_FCINST1:FCI,12104 +Display_out/green_led1_4:A, +Display_out/green_led1_4:B, +Display_out/green_led1_4:C,17476 +Display_out/green_led1_4:D,17329 +Display_out/green_led1_4:Y,17329 +Fast_clk_SW1/cnt_RNIN7F5M[7]:A, +Fast_clk_SW1/cnt_RNIN7F5M[7]:B,12186 +Fast_clk_SW1/cnt_RNIN7F5M[7]:C,17026 +Fast_clk_SW1/cnt_RNIN7F5M[7]:D, +Fast_clk_SW1/cnt_RNIN7F5M[7]:FCI,12053 +Fast_clk_SW1/cnt_RNIN7F5M[7]:FCO,12053 +Fast_clk_SW1/cnt_RNIN7F5M[7]:S,12376 +SW2_ibuf/U0/U_IOPAD:PAD, +SW2_ibuf/U0/U_IOPAD:Y, +Initial_blinking_SW1/cnt_RNIAS2PP1[24]:A, +Initial_blinking_SW1/cnt_RNIAS2PP1[24]:B,12554 +Initial_blinking_SW1/cnt_RNIAS2PP1[24]:C,17256 +Initial_blinking_SW1/cnt_RNIAS2PP1[24]:D, +Initial_blinking_SW1/cnt_RNIAS2PP1[24]:FCI,12116 +Initial_blinking_SW1/cnt_RNIAS2PP1[24]:FCO,12116 +Initial_blinking_SW1/cnt_RNIAS2PP1[24]:S,12135 +Fast_clk_SW2/cnt_RNIELUI12[19]:A, +Fast_clk_SW2/cnt_RNIELUI12[19]:B,12387 +Fast_clk_SW2/cnt_RNIELUI12[19]:C,17235 +Fast_clk_SW2/cnt_RNIELUI12[19]:D, +Fast_clk_SW2/cnt_RNIELUI12[19]:FCI,12026 +Fast_clk_SW2/cnt_RNIELUI12[19]:FCO,12026 +Fast_clk_SW2/cnt_RNIELUI12[19]:S,12140 +Fast_clk_SW1/cnt_RNI420MK1[20]:A, +Fast_clk_SW1/cnt_RNI420MK1[20]:B,12433 +Fast_clk_SW1/cnt_RNI420MK1[20]:C,17272 +Fast_clk_SW1/cnt_RNI420MK1[20]:D, +Fast_clk_SW1/cnt_RNI420MK1[20]:FCI,12053 +Fast_clk_SW1/cnt_RNI420MK1[20]:FCO,12053 +Fast_clk_SW1/cnt_RNI420MK1[20]:S,12129 +Initial_blinking_SW1/cnt_RNIO7H711[13]:A, +Initial_blinking_SW1/cnt_RNIO7H711[13]:B,12363 +Initial_blinking_SW1/cnt_RNIO7H711[13]:C,17121 +Initial_blinking_SW1/cnt_RNIO7H711[13]:D, +Initial_blinking_SW1/cnt_RNIO7H711[13]:FCI,12116 +Initial_blinking_SW1/cnt_RNIO7H711[13]:FCO,12116 +Initial_blinking_SW1/cnt_RNIO7H711[13]:S,12344 +Fast_clk_SW1/cnt[9]:ADn, +Fast_clk_SW1/cnt[9]:ALn,16174 +Fast_clk_SW1/cnt[9]:CLK,11766 +Fast_clk_SW1/cnt[9]:D,12338 +Fast_clk_SW1/cnt[9]:EN, +Fast_clk_SW1/cnt[9]:LAT, +Fast_clk_SW1/cnt[9]:Q,11766 +Fast_clk_SW1/cnt[9]:SD, +Fast_clk_SW1/cnt[9]:SLn, +Fast_clk_SW2/un14_cntlto31_0_o2_0:A,12383 +Fast_clk_SW2/un14_cntlto31_0_o2_0:B,12333 +Fast_clk_SW2/un14_cntlto31_0_o2_0:C,12236 +Fast_clk_SW2/un14_cntlto31_0_o2_0:Y,12236 +Fast_clk_SW1/cnt_RNIQFJ1G1[18]:A, +Fast_clk_SW1/cnt_RNIQFJ1G1[18]:B,12395 +Fast_clk_SW1/cnt_RNIQFJ1G1[18]:C,17235 +Fast_clk_SW1/cnt_RNIQFJ1G1[18]:D, +Fast_clk_SW1/cnt_RNIQFJ1G1[18]:FCI,12053 +Fast_clk_SW1/cnt_RNIQFJ1G1[18]:FCO,12053 +Fast_clk_SW1/cnt_RNIQFJ1G1[18]:S,12167 +Fast_clk_SW1/un14_cntlto31_0_o3_0_RNI3K631:A,14728 +Fast_clk_SW1/un14_cntlto31_0_o3_0_RNI3K631:B,14678 +Fast_clk_SW1/un14_cntlto31_0_o3_0_RNI3K631:C,12053 +Fast_clk_SW1/un14_cntlto31_0_o3_0_RNI3K631:D,14422 +Fast_clk_SW1/un14_cntlto31_0_o3_0_RNI3K631:Y,12053 +red_led2_obuf/U0/U_IOPAD:D, +red_led2_obuf/U0/U_IOPAD:E, +red_led2_obuf/U0/U_IOPAD:PAD, +Initial_blinking_SW1/cnt[16]:ADn, +Initial_blinking_SW1/cnt[16]:ALn,16174 +Initial_blinking_SW1/cnt[16]:CLK,14701 +Initial_blinking_SW1/cnt[16]:D,12287 +Initial_blinking_SW1/cnt[16]:EN, +Initial_blinking_SW1/cnt[16]:LAT, +Initial_blinking_SW1/cnt[16]:Q,14701 +Initial_blinking_SW1/cnt[16]:SD, +Initial_blinking_SW1/cnt[16]:SLn, +red_led1_obuf/U0/U_IOPAD:D, +red_led1_obuf/U0/U_IOPAD:E, +red_led1_obuf/U0/U_IOPAD:PAD, +Initial_blinking_SW1/cnt_RNIN5UJE1[19]:A, +Initial_blinking_SW1/cnt_RNIN5UJE1[19]:B,12477 +Initial_blinking_SW1/cnt_RNIN5UJE1[19]:C,17235 +Initial_blinking_SW1/cnt_RNIN5UJE1[19]:D, +Initial_blinking_SW1/cnt_RNIN5UJE1[19]:FCI,12116 +Initial_blinking_SW1/cnt_RNIN5UJE1[19]:FCO,12116 +Initial_blinking_SW1/cnt_RNIN5UJE1[19]:S,12230 +Fast_clk_SW1/cnt_RNI5DE4C[3]:A, +Fast_clk_SW1/cnt_RNI5DE4C[3]:B,12110 +Fast_clk_SW1/cnt_RNI5DE4C[3]:C,16958 +Fast_clk_SW1/cnt_RNI5DE4C[3]:D, +Fast_clk_SW1/cnt_RNI5DE4C[3]:FCI,12053 +Fast_clk_SW1/cnt_RNI5DE4C[3]:FCO,12053 +Fast_clk_SW1/cnt_RNI5DE4C[3]:S,12452 +Initial_blinking_SW2/cnt[20]:ADn, +Initial_blinking_SW2/cnt[20]:ALn,16174 +Initial_blinking_SW2/cnt[20]:CLK,14615 +Initial_blinking_SW2/cnt[20]:D,11023 +Initial_blinking_SW2/cnt[20]:EN, +Initial_blinking_SW2/cnt[20]:LAT, +Initial_blinking_SW2/cnt[20]:Q,14615 +Initial_blinking_SW2/cnt[20]:SD, +Initial_blinking_SW2/cnt[20]:SLn, +Fast_clk_SW1/cnt_RNIJCPBI1[19]:A, +Fast_clk_SW1/cnt_RNIJCPBI1[19]:B,12414 +Fast_clk_SW1/cnt_RNIJCPBI1[19]:C,17254 +Fast_clk_SW1/cnt_RNIJCPBI1[19]:D, +Fast_clk_SW1/cnt_RNIJCPBI1[19]:FCI,12053 +Fast_clk_SW1/cnt_RNIJCPBI1[19]:FCO,12053 +Fast_clk_SW1/cnt_RNIJCPBI1[19]:S,12148 +Initial_blinking_SW2/cnt_RNISP9K91[12]:A, +Initial_blinking_SW2/cnt_RNISP9K91[12]:B,11108 +Initial_blinking_SW2/cnt_RNISP9K91[12]:C,17075 +Initial_blinking_SW2/cnt_RNISP9K91[12]:D, +Initial_blinking_SW2/cnt_RNISP9K91[12]:FCI,10904 +Initial_blinking_SW2/cnt_RNISP9K91[12]:FCO,10904 +Initial_blinking_SW2/cnt_RNISP9K91[12]:S,11159 +Initial_blinking_SW2/cnt[16]:ADn, +Initial_blinking_SW2/cnt[16]:ALn,16174 +Initial_blinking_SW2/cnt[16]:CLK,11245 +Initial_blinking_SW2/cnt[16]:D,11091 +Initial_blinking_SW2/cnt[16]:EN, +Initial_blinking_SW2/cnt[16]:LAT, +Initial_blinking_SW2/cnt[16]:Q,11245 +Initial_blinking_SW2/cnt[16]:SD, +Initial_blinking_SW2/cnt[16]:SLn, +Initial_blinking_SW2/cnt_RNI0CNOS1[19]:A, +Initial_blinking_SW2/cnt_RNI0CNOS1[19]:B,11227 +Initial_blinking_SW2/cnt_RNI0CNOS1[19]:C,17208 +Initial_blinking_SW2/cnt_RNI0CNOS1[19]:D, +Initial_blinking_SW2/cnt_RNI0CNOS1[19]:FCI,10904 +Initial_blinking_SW2/cnt_RNI0CNOS1[19]:FCO,10904 +Initial_blinking_SW2/cnt_RNI0CNOS1[19]:S,11040 +Initial_blinking_SW1/un7_cntlto31_0:A,17547 +Initial_blinking_SW1/un7_cntlto31_0:B,17491 +Initial_blinking_SW1/un7_cntlto31_0:C,15044 +Initial_blinking_SW1/un7_cntlto31_0:D,11541 +Initial_blinking_SW1/un7_cntlto31_0:Y,11541 +Fast_clk_SW2/cnt[7]:ADn, +Fast_clk_SW2/cnt[7]:ALn,16174 +Fast_clk_SW2/cnt[7]:CLK,11512 +Fast_clk_SW2/cnt[7]:D,12368 +Fast_clk_SW2/cnt[7]:EN, +Fast_clk_SW2/cnt[7]:LAT, +Fast_clk_SW2/cnt[7]:Q,11512 +Fast_clk_SW2/cnt[7]:SD, +Fast_clk_SW2/cnt[7]:SLn, +Initial_blinking_SW1/cnt_RNIBVIQJ[7]:A, +Initial_blinking_SW1/cnt_RNIBVIQJ[7]:B,12249 +Initial_blinking_SW1/cnt_RNIBVIQJ[7]:C,17007 +Initial_blinking_SW1/cnt_RNIBVIQJ[7]:D, +Initial_blinking_SW1/cnt_RNIBVIQJ[7]:FCI,12116 +Initial_blinking_SW1/cnt_RNIBVIQJ[7]:FCO,12116 +Initial_blinking_SW1/cnt_RNIBVIQJ[7]:S,12458 +Initial_blinking_SW1/cnt[7]:ADn, +Initial_blinking_SW1/cnt[7]:ALn,16174 +Initial_blinking_SW1/cnt[7]:CLK,11541 +Initial_blinking_SW1/cnt[7]:D,12458 +Initial_blinking_SW1/cnt[7]:EN, +Initial_blinking_SW1/cnt[7]:LAT, +Initial_blinking_SW1/cnt[7]:Q,11541 +Initial_blinking_SW1/cnt[7]:SD, +Initial_blinking_SW1/cnt[7]:SLn, +green_led1_obuf/U0/U_IOPAD:D, +green_led1_obuf/U0/U_IOPAD:E, +green_led1_obuf/U0/U_IOPAD:PAD, +Fast_clk_SW2/cnt[22]:ADn, +Fast_clk_SW2/cnt[22]:ALn,16174 +Fast_clk_SW2/cnt[22]:CLK,13138 +Fast_clk_SW2/cnt[22]:D,12083 +Fast_clk_SW2/cnt[22]:EN, +Fast_clk_SW2/cnt[22]:LAT, +Fast_clk_SW2/cnt[22]:Q,13138 +Fast_clk_SW2/cnt[22]:SD, +Fast_clk_SW2/cnt[22]:SLn, +Fast_clk_SW1/cnt_RNII2RUT1[24]:A, +Fast_clk_SW1/cnt_RNII2RUT1[24]:B,12472 +Fast_clk_SW1/cnt_RNII2RUT1[24]:C,17256 +Fast_clk_SW1/cnt_RNII2RUT1[24]:D, +Fast_clk_SW1/cnt_RNII2RUT1[24]:FCI,12053 +Fast_clk_SW1/cnt_RNII2RUT1[24]:FCO,12104 +Fast_clk_SW1/cnt_RNII2RUT1[24]:S,12053 +Initial_blinking_SW1/cnt_RNIOF7BF[5]:A, +Initial_blinking_SW1/cnt_RNIOF7BF[5]:B,12211 +Initial_blinking_SW1/cnt_RNIOF7BF[5]:C,16977 +Initial_blinking_SW1/cnt_RNIOF7BF[5]:D, +Initial_blinking_SW1/cnt_RNIOF7BF[5]:FCI,12116 +Initial_blinking_SW1/cnt_RNIOF7BF[5]:FCO,12116 +Initial_blinking_SW1/cnt_RNIOF7BF[5]:S,12496 +Initial_blinking_SW1/cnt_RNI9OAM51[15]:A, +Initial_blinking_SW1/cnt_RNI9OAM51[15]:B,12401 +Initial_blinking_SW1/cnt_RNI9OAM51[15]:C,17151 +Initial_blinking_SW1/cnt_RNI9OAM51[15]:D, +Initial_blinking_SW1/cnt_RNI9OAM51[15]:FCI,12116 +Initial_blinking_SW1/cnt_RNI9OAM51[15]:FCO,12116 +Initial_blinking_SW1/cnt_RNI9OAM51[15]:S,12306 +Display_out/red_led2:ADn, +Display_out/red_led2:ALn,16174 +Display_out/red_led2:CLK, +Display_out/red_led2:D,17381 +Display_out/red_led2:EN, +Display_out/red_led2:LAT, +Display_out/red_led2:Q, +Display_out/red_led2:SD, +Display_out/red_led2:SLn, +Initial_blinking_SW1/cnt_RNI4NG0S1[25]_FCINST1:CO,12159 +Initial_blinking_SW1/cnt_RNI4NG0S1[25]_FCINST1:FCI,12159 +Fast_clk_SW2/cnt[14]:ADn, +Fast_clk_SW2/cnt[14]:ALn,16174 +Fast_clk_SW2/cnt[14]:CLK,12383 +Fast_clk_SW2/cnt[14]:D,12235 +Fast_clk_SW2/cnt[14]:EN, +Fast_clk_SW2/cnt[14]:LAT, +Fast_clk_SW2/cnt[14]:Q,12383 +Fast_clk_SW2/cnt[14]:SD, +Fast_clk_SW2/cnt[14]:SLn, +Fast_clk_SW2/cnt_RNIBIIQL2[25]_FCINST1:CO,12079 +Fast_clk_SW2/cnt_RNIBIIQL2[25]_FCINST1:FCI,12079 +Fast_clk_SW1/cnt[13]:ADn, +Fast_clk_SW1/cnt[13]:ALn,16174 +Fast_clk_SW1/cnt[13]:CLK,12410 +Fast_clk_SW1/cnt[13]:D,12262 +Fast_clk_SW1/cnt[13]:EN, +Fast_clk_SW1/cnt[13]:LAT, +Fast_clk_SW1/cnt[13]:Q,12410 +Fast_clk_SW1/cnt[13]:SD, +Fast_clk_SW1/cnt[13]:SLn, +Initial_blinking_SW2/tmp_clk_RNO_2:A,15226 +Initial_blinking_SW2/tmp_clk_RNO_2:B,15170 +Initial_blinking_SW2/tmp_clk_RNO_2:C,15082 +Initial_blinking_SW2/tmp_clk_RNO_2:D,14972 +Initial_blinking_SW2/tmp_clk_RNO_2:Y,14972 +Fast_clk_SW2/cnt[0]:ADn, +Fast_clk_SW2/cnt[0]:ALn,16174 +Fast_clk_SW2/cnt[0]:CLK,16882 +Fast_clk_SW2/cnt[0]:D,12464 +Fast_clk_SW2/cnt[0]:EN, +Fast_clk_SW2/cnt[0]:LAT, +Fast_clk_SW2/cnt[0]:Q,16882 +Fast_clk_SW2/cnt[0]:SD, +Fast_clk_SW2/cnt[0]:SLn, +Initial_blinking_SW2/cnt_RNI9M9BU[8]:A, +Initial_blinking_SW2/cnt_RNI9M9BU[8]:B,11040 +Initial_blinking_SW2/cnt_RNI9M9BU[8]:C,17007 +Initial_blinking_SW2/cnt_RNI9M9BU[8]:D, +Initial_blinking_SW2/cnt_RNI9M9BU[8]:FCI,10904 +Initial_blinking_SW2/cnt_RNI9M9BU[8]:FCO,10904 +Initial_blinking_SW2/cnt_RNI9M9BU[8]:S,11227 +Initial_blinking_SW1/cnt_RNI4NG0S1[25]:A, +Initial_blinking_SW1/cnt_RNI4NG0S1[25]:B,12554 +Initial_blinking_SW1/cnt_RNI4NG0S1[25]:C,17256 +Initial_blinking_SW1/cnt_RNI4NG0S1[25]:D, +Initial_blinking_SW1/cnt_RNI4NG0S1[25]:FCI,12116 +Initial_blinking_SW1/cnt_RNI4NG0S1[25]:FCO,12159 +Initial_blinking_SW1/cnt_RNI4NG0S1[25]:S,12116 +clk_ibuf_RNIVTI2/U0_RGB1:An, +clk_ibuf_RNIVTI2/U0_RGB1:ENn, +clk_ibuf_RNIVTI2/U0_RGB1:YL, +red_led2_obuf/U0/U_IOENFF:A, +red_led2_obuf/U0/U_IOENFF:Y, +Initial_blinking_SW2/cnt_RNIIH0I1[12]:A,12351 +Initial_blinking_SW2/cnt_RNIIH0I1[12]:B,11009 +Initial_blinking_SW2/cnt_RNIIH0I1[12]:C,10904 +Initial_blinking_SW2/cnt_RNIIH0I1[12]:Y,10904 +Fast_clk_SW1/un7_cntlto31_0_a3:A,16238 +Fast_clk_SW1/un7_cntlto31_0_a3:B,11512 +Fast_clk_SW1/un7_cntlto31_0_a3:C,16102 +Fast_clk_SW1/un7_cntlto31_0_a3:D,15974 +Fast_clk_SW1/un7_cntlto31_0_a3:Y,11512 +Initial_blinking_SW1/un14_cntlto31_0_o2_0:A,12263 +Initial_blinking_SW1/un14_cntlto31_0_o2_0:B,12213 +Initial_blinking_SW1/un14_cntlto31_0_o2_0:C,12116 +Initial_blinking_SW1/un14_cntlto31_0_o2_0:Y,12116 +Fast_clk_SW2/cnt[8]:ADn, +Fast_clk_SW2/cnt[8]:ALn,16174 +Fast_clk_SW2/cnt[8]:CLK,11622 +Fast_clk_SW2/cnt[8]:D,12349 +Fast_clk_SW2/cnt[8]:EN, +Fast_clk_SW2/cnt[8]:LAT, +Fast_clk_SW2/cnt[8]:Q,11622 +Fast_clk_SW2/cnt[8]:SD, +Fast_clk_SW2/cnt[8]:SLn, +Fast_clk_SW2/cnt_RNI2QB2Q[7]:A, +Fast_clk_SW2/cnt_RNI2QB2Q[7]:B,12159 +Fast_clk_SW2/cnt_RNI2QB2Q[7]:C,17007 +Fast_clk_SW2/cnt_RNI2QB2Q[7]:D, +Fast_clk_SW2/cnt_RNI2QB2Q[7]:FCI,12026 +Fast_clk_SW2/cnt_RNI2QB2Q[7]:FCO,12026 +Fast_clk_SW2/cnt_RNI2QB2Q[7]:S,12368 +Fast_clk_SW1/cnt_RNI07SO61[14]:A, +Fast_clk_SW1/cnt_RNI07SO61[14]:B,12319 +Fast_clk_SW1/cnt_RNI07SO61[14]:C,17151 +Fast_clk_SW1/cnt_RNI07SO61[14]:D, +Fast_clk_SW1/cnt_RNI07SO61[14]:FCI,12053 +Fast_clk_SW1/cnt_RNI07SO61[14]:FCO,12053 +Fast_clk_SW1/cnt_RNI07SO61[14]:S,12243 +Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2:A,12026 +Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2:B,15654 +Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2:C,13186 +Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2:D,12873 +Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2:FCI, +Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2:FCO,13309 +Fast_clk_SW2/un14_cntlto31_0_o3_RNIE29S2:Y,12026 +Initial_blinking_SW2/cnt_RNIMMBTF2[26]_FCINST1:CO,10904 +Initial_blinking_SW2/cnt_RNIMMBTF2[26]_FCINST1:FCI,10904 +Initial_blinking_SW2/cnt_RNI9EVA2[20]:A,14615 +Initial_blinking_SW2/cnt_RNI9EVA2[20]:B,14524 +Initial_blinking_SW2/cnt_RNI9EVA2[20]:C,10904 +Initial_blinking_SW2/cnt_RNI9EVA2[20]:D,13220 +Initial_blinking_SW2/cnt_RNI9EVA2[20]:Y,10904 +Fast_clk_SW1/cnt[22]:ADn, +Fast_clk_SW1/cnt[22]:ALn,16174 +Fast_clk_SW1/cnt[22]:CLK,14575 +Fast_clk_SW1/cnt[22]:D,12091 +Fast_clk_SW1/cnt[22]:EN, +Fast_clk_SW1/cnt[22]:LAT, +Fast_clk_SW1/cnt[22]:Q,14575 +Fast_clk_SW1/cnt[22]:SD, +Fast_clk_SW1/cnt[22]:SLn, +Fast_clk_SW1/un7_cntlto31_0_0:A,17547 +Fast_clk_SW1/un7_cntlto31_0_0:B,17491 +Fast_clk_SW1/un7_cntlto31_0_0:C,15044 +Fast_clk_SW1/un7_cntlto31_0_0:D,11512 +Fast_clk_SW1/un7_cntlto31_0_0:Y,11512 +Initial_blinking_SW1/un14_cntlto31_0_o2_3:A,13443 +Initial_blinking_SW1/un14_cntlto31_0_o2_3:B,13393 +Initial_blinking_SW1/un14_cntlto31_0_o2_3:C,13296 +Initial_blinking_SW1/un14_cntlto31_0_o2_3:D,13178 +Initial_blinking_SW1/un14_cntlto31_0_o2_3:Y,13178 +Fast_clk_SW1/cnt[15]:ADn, +Fast_clk_SW1/cnt[15]:ALn,16174 +Fast_clk_SW1/cnt[15]:CLK,14728 +Fast_clk_SW1/cnt[15]:D,12224 +Fast_clk_SW1/cnt[15]:EN, +Fast_clk_SW1/cnt[15]:LAT, +Fast_clk_SW1/cnt[15]:Q,14728 +Fast_clk_SW1/cnt[15]:SD, +Fast_clk_SW1/cnt[15]:SLn, +Display_out/red_led2_3:A, +Display_out/red_led2_3:B, +Display_out/red_led2_3:C,17476 +Display_out/red_led2_3:D,17381 +Display_out/red_led2_3:Y,17381 +Initial_blinking_SW2/cnt_RNI49QS61[11]:A, +Initial_blinking_SW2/cnt_RNI49QS61[11]:B,11091 +Initial_blinking_SW2/cnt_RNI49QS61[11]:C,17064 +Initial_blinking_SW2/cnt_RNI49QS61[11]:D, +Initial_blinking_SW2/cnt_RNI49QS61[11]:FCI,10904 +Initial_blinking_SW2/cnt_RNI49QS61[11]:FCO,10904 +Initial_blinking_SW2/cnt_RNI49QS61[11]:S,11176 +Initial_blinking_SW1/cnt[1]:ADn, +Initial_blinking_SW1/cnt[1]:ALn,16174 +Initial_blinking_SW1/cnt[1]:CLK,16901 +Initial_blinking_SW1/cnt[1]:D,12554 +Initial_blinking_SW1/cnt[1]:EN, +Initial_blinking_SW1/cnt[1]:LAT, +Initial_blinking_SW1/cnt[1]:Q,16901 +Initial_blinking_SW1/cnt[1]:SD, +Initial_blinking_SW1/cnt[1]:SLn, +Initial_blinking_SW2/cnt[9]:ADn, +Initial_blinking_SW2/cnt[9]:ALn,16174 +Initial_blinking_SW2/cnt[9]:CLK,11014 +Initial_blinking_SW2/cnt[9]:D,11210 +Initial_blinking_SW2/cnt[9]:EN, +Initial_blinking_SW2/cnt[9]:LAT, +Initial_blinking_SW2/cnt[9]:Q,11014 +Initial_blinking_SW2/cnt[9]:SD, +Initial_blinking_SW2/cnt[9]:SLn, +Initial_blinking_SW1/cnt_RNI2JU9O[9]:A, +Initial_blinking_SW1/cnt_RNI2JU9O[9]:B,12287 +Initial_blinking_SW1/cnt_RNI2JU9O[9]:C,17045 +Initial_blinking_SW1/cnt_RNI2JU9O[9]:D, +Initial_blinking_SW1/cnt_RNI2JU9O[9]:FCI,12116 +Initial_blinking_SW1/cnt_RNI2JU9O[9]:FCO,12116 +Initial_blinking_SW1/cnt_RNI2JU9O[9]:S,12420 +Initial_blinking_SW2/cnt_RNIT9AEA2[24]:A, +Initial_blinking_SW2/cnt_RNIT9AEA2[24]:B,11312 +Initial_blinking_SW2/cnt_RNIT9AEA2[24]:C,17264 +Initial_blinking_SW2/cnt_RNIT9AEA2[24]:D, +Initial_blinking_SW2/cnt_RNIT9AEA2[24]:FCI,10904 +Initial_blinking_SW2/cnt_RNIT9AEA2[24]:FCO,10904 +Initial_blinking_SW2/cnt_RNIT9AEA2[24]:S,10953 +Fast_clk_SW1/cnt[7]:ADn, +Fast_clk_SW1/cnt[7]:ALn,16174 +Fast_clk_SW1/cnt[7]:CLK,11622 +Fast_clk_SW1/cnt[7]:D,12376 +Fast_clk_SW1/cnt[7]:EN, +Fast_clk_SW1/cnt[7]:LAT, +Fast_clk_SW1/cnt[7]:Q,11622 +Fast_clk_SW1/cnt[7]:SD, +Fast_clk_SW1/cnt[7]:SLn, +Fast_clk_SW1/un14_cntlto31_0_o3:A,14575 +Fast_clk_SW1/un14_cntlto31_0_o3:B,13213 +Fast_clk_SW1/un14_cntlto31_0_o3:C,14429 +Fast_clk_SW1/un14_cntlto31_0_o3:D,14299 +Fast_clk_SW1/un14_cntlto31_0_o3:Y,13213 +flash_freeze_inst/INST_FLASH_FREEZE_IP:FF_TO_START, +Fast_clk_SW1/un14_cntlto31_0_o3_0:A,13569 +Fast_clk_SW1/un14_cntlto31_0_o3_0:B,13519 +Fast_clk_SW1/un14_cntlto31_0_o3_0:C,12263 +Fast_clk_SW1/un14_cntlto31_0_o3_0:D,12053 +Fast_clk_SW1/un14_cntlto31_0_o3_0:Y,12053 +Initial_blinking_SW2/tmp_clk_RNO_3:A,14243 +Initial_blinking_SW2/tmp_clk_RNO_3:B,12893 +Initial_blinking_SW2/tmp_clk_RNO_3:C,12788 +Initial_blinking_SW2/tmp_clk_RNO_3:Y,12788 +Initial_blinking_SW2/cnt_RNIAH0SB[2]:A, +Initial_blinking_SW2/cnt_RNIAH0SB[2]:B,10938 +Initial_blinking_SW2/cnt_RNIAH0SB[2]:C,16901 +Initial_blinking_SW2/cnt_RNIAH0SB[2]:D, +Initial_blinking_SW2/cnt_RNIAH0SB[2]:FCI,10904 +Initial_blinking_SW2/cnt_RNIAH0SB[2]:FCO,10904 +Initial_blinking_SW2/cnt_RNIAH0SB[2]:S,11322 +Initial_blinking_SW1/cnt[21]:ADn, +Initial_blinking_SW1/cnt[21]:ALn,16174 +Initial_blinking_SW1/cnt[21]:CLK,13393 +Initial_blinking_SW1/cnt[21]:D,12192 +Initial_blinking_SW1/cnt[21]:EN, +Initial_blinking_SW1/cnt[21]:LAT, +Initial_blinking_SW1/cnt[21]:Q,13393 +Initial_blinking_SW1/cnt[21]:SD, +Initial_blinking_SW1/cnt[21]:SLn, +Fast_clk_SW2/cnt_RNI06AFE[3]:A, +Fast_clk_SW2/cnt_RNI06AFE[3]:B,12083 +Fast_clk_SW2/cnt_RNI06AFE[3]:C,16939 +Fast_clk_SW2/cnt_RNI06AFE[3]:D, +Fast_clk_SW2/cnt_RNI06AFE[3]:FCI,12026 +Fast_clk_SW2/cnt_RNI06AFE[3]:FCO,12026 +Fast_clk_SW2/cnt_RNI06AFE[3]:S,12444 +Initial_blinking_SW2/tmp_clk_RNO:A,17555 +Initial_blinking_SW2/tmp_clk_RNO:B,12788 +Initial_blinking_SW2/tmp_clk_RNO:C,17419 +Initial_blinking_SW2/tmp_clk_RNO:D,17291 +Initial_blinking_SW2/tmp_clk_RNO:Y,12788 +Fast_clk_SW1/cnt[10]:ADn, +Fast_clk_SW1/cnt[10]:ALn,16174 +Fast_clk_SW1/cnt[10]:CLK,13519 +Fast_clk_SW1/cnt[10]:D,12319 +Fast_clk_SW1/cnt[10]:EN, +Fast_clk_SW1/cnt[10]:LAT, +Fast_clk_SW1/cnt[10]:Q,13519 +Fast_clk_SW1/cnt[10]:SD, +Fast_clk_SW1/cnt[10]:SLn, +Fast_clk_SW1/un14_cntlto31_0_a2:A,14271 +Fast_clk_SW1/un14_cntlto31_0_a2:B,12900 +Fast_clk_SW1/un14_cntlto31_0_a2:C,14132 +Fast_clk_SW1/un14_cntlto31_0_a2:Y,12900 +Initial_blinking_SW2/cnt_RNIAQCC[13]:A,11245 +Initial_blinking_SW2/cnt_RNIAQCC[13]:B,11154 +Initial_blinking_SW2/cnt_RNIAQCC[13]:C,11101 +Initial_blinking_SW2/cnt_RNIAQCC[13]:D,11009 +Initial_blinking_SW2/cnt_RNIAQCC[13]:Y,11009 +Initial_blinking_SW1/cnt_RNIP97AL1[22]:A, +Initial_blinking_SW1/cnt_RNIP97AL1[22]:B,12533 +Initial_blinking_SW1/cnt_RNIP97AL1[22]:C,17272 +Initial_blinking_SW1/cnt_RNIP97AL1[22]:D, +Initial_blinking_SW1/cnt_RNIP97AL1[22]:FCI,12116 +Initial_blinking_SW1/cnt_RNIP97AL1[22]:FCO,12116 +Initial_blinking_SW1/cnt_RNIP97AL1[22]:S,12173 +Fast_clk_SW1/cnt[8]:ADn, +Fast_clk_SW1/cnt[8]:ALn,16174 +Fast_clk_SW1/cnt[8]:CLK,11710 +Fast_clk_SW1/cnt[8]:D,12357 +Fast_clk_SW1/cnt[8]:EN, +Fast_clk_SW1/cnt[8]:LAT, +Fast_clk_SW1/cnt[8]:Q,11710 +Fast_clk_SW1/cnt[8]:SD, +Fast_clk_SW1/cnt[8]:SLn, +Initial_blinking_SW1/cnt[18]:ADn, +Initial_blinking_SW1/cnt[18]:ALn,16174 +Initial_blinking_SW1/cnt[18]:CLK,14410 +Initial_blinking_SW1/cnt[18]:D,12249 +Initial_blinking_SW1/cnt[18]:EN, +Initial_blinking_SW1/cnt[18]:LAT, +Initial_blinking_SW1/cnt[18]:Q,14410 +Initial_blinking_SW1/cnt[18]:SD, +Initial_blinking_SW1/cnt[18]:SLn, +SW2_ibuf/U0/U_IOINFF:A, +SW2_ibuf/U0/U_IOINFF:Y, +Fast_clk_SW2/cnt[16]:ADn, +Fast_clk_SW2/cnt[16]:ALn,16174 +Fast_clk_SW2/cnt[16]:CLK,14701 +Fast_clk_SW2/cnt[16]:D,12197 +Fast_clk_SW2/cnt[16]:EN, +Fast_clk_SW2/cnt[16]:LAT, +Fast_clk_SW2/cnt[16]:Q,14701 +Fast_clk_SW2/cnt[16]:SD, +Fast_clk_SW2/cnt[16]:SLn, +Fast_clk_SW2/un14_cntlto31_0_a2_1_3:A,11766 +Fast_clk_SW2/un14_cntlto31_0_a2_1_3:B,11710 +Fast_clk_SW2/un14_cntlto31_0_a2_1_3:C,11622 +Fast_clk_SW2/un14_cntlto31_0_a2_1_3:D,11512 +Fast_clk_SW2/un14_cntlto31_0_a2_1_3:Y,11512 +Fast_clk_SW2/cnt_RNI8FM2F2[23]:A, +Fast_clk_SW2/cnt_RNI8FM2F2[23]:B,12463 +Fast_clk_SW2/cnt_RNI8FM2F2[23]:C,17256 +Fast_clk_SW2/cnt_RNI8FM2F2[23]:D, +Fast_clk_SW2/cnt_RNI8FM2F2[23]:FCI,12026 +Fast_clk_SW2/cnt_RNI8FM2F2[23]:FCO,12026 +Fast_clk_SW2/cnt_RNI8FM2F2[23]:S,12064 +Fast_clk_SW2/cnt_RNI5LP731[10]:A, +Fast_clk_SW2/cnt_RNI5LP731[10]:B,12216 +Fast_clk_SW2/cnt_RNI5LP731[10]:C,17064 +Fast_clk_SW2/cnt_RNI5LP731[10]:D, +Fast_clk_SW2/cnt_RNI5LP731[10]:FCI,12026 +Fast_clk_SW2/cnt_RNI5LP731[10]:FCO,12026 +Fast_clk_SW2/cnt_RNI5LP731[10]:S,12311 +Initial_blinking_SW2/cnt_RNINARD11[9]:A, +Initial_blinking_SW2/cnt_RNINARD11[9]:B,11057 +Initial_blinking_SW2/cnt_RNINARD11[9]:C,17026 +Initial_blinking_SW2/cnt_RNINARD11[9]:D, +Initial_blinking_SW2/cnt_RNINARD11[9]:FCI,10904 +Initial_blinking_SW2/cnt_RNINARD11[9]:FCO,10904 +Initial_blinking_SW2/cnt_RNINARD11[9]:S,11210 +Initial_blinking_SW1/cnt_RNIGPH3D[4]:A, +Initial_blinking_SW1/cnt_RNIGPH3D[4]:B,12192 +Initial_blinking_SW1/cnt_RNIGPH3D[4]:C,16958 +Initial_blinking_SW1/cnt_RNIGPH3D[4]:D, +Initial_blinking_SW1/cnt_RNIGPH3D[4]:FCI,12116 +Initial_blinking_SW1/cnt_RNIGPH3D[4]:FCO,12116 +Initial_blinking_SW1/cnt_RNIGPH3D[4]:S,12515 +Fast_clk_SW2/cnt[3]:ADn, +Fast_clk_SW2/cnt[3]:ALn,16174 +Fast_clk_SW2/cnt[3]:CLK,16939 +Fast_clk_SW2/cnt[3]:D,12444 +Fast_clk_SW2/cnt[3]:EN, +Fast_clk_SW2/cnt[3]:LAT, +Fast_clk_SW2/cnt[3]:Q,16939 +Fast_clk_SW2/cnt[3]:SD, +Fast_clk_SW2/cnt[3]:SLn, +Initial_blinking_SW2/cnt[4]:ADn, +Initial_blinking_SW2/cnt[4]:ALn,16174 +Initial_blinking_SW2/cnt[4]:CLK,16939 +Initial_blinking_SW2/cnt[4]:D,11295 +Initial_blinking_SW2/cnt[4]:EN, +Initial_blinking_SW2/cnt[4]:LAT, +Initial_blinking_SW2/cnt[4]:Q,16939 +Initial_blinking_SW2/cnt[4]:SD, +Initial_blinking_SW2/cnt[4]:SLn, +Initial_blinking_SW1/un14_cntlto31_0_a2:A,14549 +Initial_blinking_SW1/un14_cntlto31_0_a2:B,13178 +Initial_blinking_SW1/un14_cntlto31_0_a2:C,14410 +Initial_blinking_SW1/un14_cntlto31_0_a2:Y,13178 +Initial_blinking_SW2/cnt[6]:ADn, +Initial_blinking_SW2/cnt[6]:ALn,16174 +Initial_blinking_SW2/cnt[6]:CLK,16977 +Initial_blinking_SW2/cnt[6]:D,11261 +Initial_blinking_SW2/cnt[6]:EN, +Initial_blinking_SW2/cnt[6]:LAT, +Initial_blinking_SW2/cnt[6]:Q,16977 +Initial_blinking_SW2/cnt[6]:SD, +Initial_blinking_SW2/cnt[6]:SLn, +Fast_clk_SW2/cnt_RNIVADNG1[14]:A, +Fast_clk_SW2/cnt_RNIVADNG1[14]:B,12292 +Fast_clk_SW2/cnt_RNIVADNG1[14]:C,17140 +Fast_clk_SW2/cnt_RNIVADNG1[14]:D, +Fast_clk_SW2/cnt_RNIVADNG1[14]:FCI,12026 +Fast_clk_SW2/cnt_RNIVADNG1[14]:FCO,12026 +Fast_clk_SW2/cnt_RNIVADNG1[14]:S,12235 +Initial_blinking_SW2/cnt[0]:ADn, +Initial_blinking_SW2/cnt[0]:ALn,16174 +Initial_blinking_SW2/cnt[0]:CLK,16863 +Initial_blinking_SW2/cnt[0]:D,11322 +Initial_blinking_SW2/cnt[0]:EN, +Initial_blinking_SW2/cnt[0]:LAT, +Initial_blinking_SW2/cnt[0]:Q,16863 +Initial_blinking_SW2/cnt[0]:SD, +Initial_blinking_SW2/cnt[0]:SLn, +Fast_clk_SW2/cnt[21]:ADn, +Fast_clk_SW2/cnt[21]:ALn,16174 +Fast_clk_SW2/cnt[21]:CLK,13088 +Fast_clk_SW2/cnt[21]:D,12102 +Fast_clk_SW2/cnt[21]:EN, +Fast_clk_SW2/cnt[21]:LAT, +Fast_clk_SW2/cnt[21]:Q,13088 +Fast_clk_SW2/cnt[21]:SD, +Fast_clk_SW2/cnt[21]:SLn, +Initial_blinking_SW2/cnt[18]:ADn, +Initial_blinking_SW2/cnt[18]:ALn,16174 +Initial_blinking_SW2/cnt[18]:CLK,13158 +Initial_blinking_SW2/cnt[18]:D,11057 +Initial_blinking_SW2/cnt[18]:EN, +Initial_blinking_SW2/cnt[18]:LAT, +Initial_blinking_SW2/cnt[18]:Q,13158 +Initial_blinking_SW2/cnt[18]:SD, +Initial_blinking_SW2/cnt[18]:SLn, +Fast_clk_SW1/cnt_RNIBP7DB1[16]:A, +Fast_clk_SW1/cnt_RNIBP7DB1[16]:B,12357 +Fast_clk_SW1/cnt_RNIBP7DB1[16]:C,17189 +Fast_clk_SW1/cnt_RNIBP7DB1[16]:D, +Fast_clk_SW1/cnt_RNIBP7DB1[16]:FCI,12053 +Fast_clk_SW1/cnt_RNIBP7DB1[16]:FCO,12053 +Fast_clk_SW1/cnt_RNIBP7DB1[16]:S,12205 +Initial_blinking_SW1/un7_cntlto31_0_a2:A,15096 +Initial_blinking_SW1/un7_cntlto31_0_a2:B,15040 +Initial_blinking_SW1/un7_cntlto31_0_a2:C,11541 +Initial_blinking_SW1/un7_cntlto31_0_a2:D,14824 +Initial_blinking_SW1/un7_cntlto31_0_a2:Y,11541 +Fast_clk_SW2/un14_cntlto31_0_o2_3:A,13138 +Fast_clk_SW2/un14_cntlto31_0_o2_3:B,13088 +Fast_clk_SW2/un14_cntlto31_0_o2_3:C,12991 +Fast_clk_SW2/un14_cntlto31_0_o2_3:D,12873 +Fast_clk_SW2/un14_cntlto31_0_o2_3:Y,12873 +Fast_clk_SW1/cnt[3]:ADn, +Fast_clk_SW1/cnt[3]:ALn,16174 +Fast_clk_SW1/cnt[3]:CLK,16958 +Fast_clk_SW1/cnt[3]:D,12452 +Fast_clk_SW1/cnt[3]:EN, +Fast_clk_SW1/cnt[3]:LAT, +Fast_clk_SW1/cnt[3]:Q,16958 +Fast_clk_SW1/cnt[3]:SD, +Fast_clk_SW1/cnt[3]:SLn, +Initial_blinking_SW1/cnt[9]:ADn, +Initial_blinking_SW1/cnt[9]:ALn,16174 +Initial_blinking_SW1/cnt[9]:CLK,11739 +Initial_blinking_SW1/cnt[9]:D,12420 +Initial_blinking_SW1/cnt[9]:EN, +Initial_blinking_SW1/cnt[9]:LAT, +Initial_blinking_SW1/cnt[9]:Q,11739 +Initial_blinking_SW1/cnt[9]:SD, +Initial_blinking_SW1/cnt[9]:SLn, +Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32:A,12053 +Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32:B,15679 +Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32:C,13213 +Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32:D,12900 +Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32:FCI, +Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32:FCO,13328 +Fast_clk_SW1/un14_cntlto31_0_o3_RNI33E32:Y,12053 +Fast_clk_SW2/tmp_clk:ADn, +Fast_clk_SW2/tmp_clk:ALn,16174 +Fast_clk_SW2/tmp_clk:CLK,17381 +Fast_clk_SW2/tmp_clk:D,11512 +Fast_clk_SW2/tmp_clk:EN, +Fast_clk_SW2/tmp_clk:LAT, +Fast_clk_SW2/tmp_clk:Q,17381 +Fast_clk_SW2/tmp_clk:SD, +Fast_clk_SW2/tmp_clk:SLn, +Fast_clk_SW2/cnt[2]:ADn, +Fast_clk_SW2/cnt[2]:ALn,16174 +Fast_clk_SW2/cnt[2]:CLK,16920 +Fast_clk_SW2/cnt[2]:D,12463 +Fast_clk_SW2/cnt[2]:EN, +Fast_clk_SW2/cnt[2]:LAT, +Fast_clk_SW2/cnt[2]:Q,16920 +Fast_clk_SW2/cnt[2]:SD, +Fast_clk_SW2/cnt[2]:SLn, +Initial_blinking_SW2/cnt_RNIMMBTF2[26]:A, +Initial_blinking_SW2/cnt_RNIMMBTF2[26]:B,11322 +Initial_blinking_SW2/cnt_RNIMMBTF2[26]:C,17264 +Initial_blinking_SW2/cnt_RNIMMBTF2[26]:D, +Initial_blinking_SW2/cnt_RNIMMBTF2[26]:FCI,10904 +Initial_blinking_SW2/cnt_RNIMMBTF2[26]:FCO,10904 +Initial_blinking_SW2/cnt_RNIMMBTF2[26]:S,10915 +Initial_blinking_SW1/cnt[11]:ADn, +Initial_blinking_SW1/cnt[11]:ALn,16174 +Initial_blinking_SW1/cnt[11]:CLK,13542 +Initial_blinking_SW1/cnt[11]:D,12382 +Initial_blinking_SW1/cnt[11]:EN, +Initial_blinking_SW1/cnt[11]:LAT, +Initial_blinking_SW1/cnt[11]:Q,13542 +Initial_blinking_SW1/cnt[11]:SD, +Initial_blinking_SW1/cnt[11]:SLn, +Fast_clk_SW1/cnt_RNI6RV5R[9]:A, +Fast_clk_SW1/cnt_RNI6RV5R[9]:B,12224 +Fast_clk_SW1/cnt_RNI6RV5R[9]:C,17064 +Fast_clk_SW1/cnt_RNI6RV5R[9]:D, +Fast_clk_SW1/cnt_RNI6RV5R[9]:FCI,12053 +Fast_clk_SW1/cnt_RNI6RV5R[9]:FCO,12053 +Fast_clk_SW1/cnt_RNI6RV5R[9]:S,12338 +red_led1_obuf/U0/U_IOENFF:A, +red_led1_obuf/U0/U_IOENFF:Y, +Initial_blinking_SW2/cnt[27]:ADn, +Initial_blinking_SW2/cnt[27]:ALn,16174 +Initial_blinking_SW2/cnt[27]:CLK,15697 +Initial_blinking_SW2/cnt[27]:D,10904 +Initial_blinking_SW2/cnt[27]:EN, +Initial_blinking_SW2/cnt[27]:LAT, +Initial_blinking_SW2/cnt[27]:Q,15697 +Initial_blinking_SW2/cnt[27]:SD, +Initial_blinking_SW2/cnt[27]:SLn, +Initial_blinking_SW2/cnt[11]:ADn, +Initial_blinking_SW2/cnt[11]:ALn,16174 +Initial_blinking_SW2/cnt[11]:CLK,11158 +Initial_blinking_SW2/cnt[11]:D,11176 +Initial_blinking_SW2/cnt[11]:EN, +Initial_blinking_SW2/cnt[11]:LAT, +Initial_blinking_SW2/cnt[11]:Q,11158 +Initial_blinking_SW2/cnt[11]:SD, +Initial_blinking_SW2/cnt[11]:SLn, +Fast_clk_SW2/cnt_RNI2C7FN1[16]:A, +Fast_clk_SW2/cnt_RNI2C7FN1[16]:B,12330 +Fast_clk_SW2/cnt_RNI2C7FN1[16]:C,17170 +Fast_clk_SW2/cnt_RNI2C7FN1[16]:D, +Fast_clk_SW2/cnt_RNI2C7FN1[16]:FCI,12026 +Fast_clk_SW2/cnt_RNI2C7FN1[16]:FCO,12026 +Fast_clk_SW2/cnt_RNI2C7FN1[16]:S,12197 +Fast_clk_SW2/cnt[4]:ADn, +Fast_clk_SW2/cnt[4]:ALn,16174 +Fast_clk_SW2/cnt[4]:CLK,16958 +Fast_clk_SW2/cnt[4]:D,12425 +Fast_clk_SW2/cnt[4]:EN, +Fast_clk_SW2/cnt[4]:LAT, +Fast_clk_SW2/cnt[4]:Q,16958 +Fast_clk_SW2/cnt[4]:SD, +Fast_clk_SW2/cnt[4]:SLn, +Initial_blinking_SW1/cnt_RNICRBRG1[20]:A, +Initial_blinking_SW1/cnt_RNICRBRG1[20]:B,12496 +Initial_blinking_SW1/cnt_RNICRBRG1[20]:C,17254 +Initial_blinking_SW1/cnt_RNICRBRG1[20]:D, +Initial_blinking_SW1/cnt_RNICRBRG1[20]:FCI,12116 +Initial_blinking_SW1/cnt_RNICRBRG1[20]:FCO,12116 +Initial_blinking_SW1/cnt_RNICRBRG1[20]:S,12211 +Initial_blinking_SW1/cnt_RNIQ8HCC1[18]:A, +Initial_blinking_SW1/cnt_RNIQ8HCC1[18]:B,12458 +Initial_blinking_SW1/cnt_RNIQ8HCC1[18]:C,17216 +Initial_blinking_SW1/cnt_RNIQ8HCC1[18]:D, +Initial_blinking_SW1/cnt_RNIQ8HCC1[18]:FCI,12116 +Initial_blinking_SW1/cnt_RNIQ8HCC1[18]:FCO,12116 +Initial_blinking_SW1/cnt_RNIQ8HCC1[18]:S,12249 +Fast_clk_SW1/cnt_RNIMO60N1[21]:A, +Fast_clk_SW1/cnt_RNIMO60N1[21]:B,12452 +Fast_clk_SW1/cnt_RNIMO60N1[21]:C,17272 +Fast_clk_SW1/cnt_RNIMO60N1[21]:D, +Fast_clk_SW1/cnt_RNIMO60N1[21]:FCI,12053 +Fast_clk_SW1/cnt_RNIMO60N1[21]:FCO,12053 +Fast_clk_SW1/cnt_RNIMO60N1[21]:S,12110 +Fast_clk_SW2/cnt_RNI9QSRV[9]:A, +Fast_clk_SW2/cnt_RNI9QSRV[9]:B,12197 +Fast_clk_SW2/cnt_RNI9QSRV[9]:C,17045 +Fast_clk_SW2/cnt_RNI9QSRV[9]:D, +Fast_clk_SW2/cnt_RNI9QSRV[9]:FCI,12026 +Fast_clk_SW2/cnt_RNI9QSRV[9]:FCO,12026 +Fast_clk_SW2/cnt_RNI9QSRV[9]:S,12330 +Fast_clk_SW1/tmp_clk:ADn, +Fast_clk_SW1/tmp_clk:ALn,16174 +Fast_clk_SW1/tmp_clk:CLK,17476 +Fast_clk_SW1/tmp_clk:D,11512 +Fast_clk_SW1/tmp_clk:EN, +Fast_clk_SW1/tmp_clk:LAT, +Fast_clk_SW1/tmp_clk:Q,17476 +Fast_clk_SW1/tmp_clk:SD, +Fast_clk_SW1/tmp_clk:SLn, +Clear_outputs/reset_RNIREK/U0:An, +Clear_outputs/reset_RNIREK/U0:ENn, +Clear_outputs/reset_RNIREK/U0:YWn, +Initial_blinking_SW1/un7_cntlto31_0_a2_1:A,11541 +Initial_blinking_SW1/un7_cntlto31_0_a2_1:B,12748 +Initial_blinking_SW1/un7_cntlto31_0_a2_1:Y,11541 +Initial_blinking_SW1/cnt[23]:ADn, +Initial_blinking_SW1/cnt[23]:ALn,16174 +Initial_blinking_SW1/cnt[23]:CLK,14602 +Initial_blinking_SW1/cnt[23]:D,12154 +Initial_blinking_SW1/cnt[23]:EN, +Initial_blinking_SW1/cnt[23]:LAT, +Initial_blinking_SW1/cnt[23]:Q,14602 +Initial_blinking_SW1/cnt[23]:SD, +Initial_blinking_SW1/cnt[23]:SLn, +Fast_clk_SW1/cnt_RNICFME41[13]:A, +Fast_clk_SW1/cnt_RNICFME41[13]:B,12300 +Fast_clk_SW1/cnt_RNICFME41[13]:C,17140 +Fast_clk_SW1/cnt_RNICFME41[13]:D, +Fast_clk_SW1/cnt_RNICFME41[13]:FCI,12053 +Fast_clk_SW1/cnt_RNICFME41[13]:FCO,12053 +Fast_clk_SW1/cnt_RNICFME41[13]:S,12262 +clk, +SW1, +SW2, +green_led1, +red_led1, +green_led2, +red_led2, diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/place_route.sdc b/Lab2_VHDL/designer/LedBlinkingDSpeed/place_route.sdc new file mode 100644 index 0000000..21ba2a8 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/place_route.sdc @@ -0,0 +1,8 @@ +# Microsemi Corp. +# Date: 2016-Oct-23 03:01:01 +# This file was generated based on the following SDC source files: +# C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/constraint/LedBlinkingDSpeed_sdc.sdc +# + +# Clocks +create_clock -name {LedBlinkingDSpeed|clk} -period 20 -waveform {0 10 } [ get_ports { clk } ] diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/placer_coverage.log b/Lab2_VHDL/designer/LedBlinkingDSpeed/placer_coverage.log new file mode 100644 index 0000000..a685e21 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/placer_coverage.log @@ -0,0 +1 @@ +No errors or warnings found. diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/rptstyle.xsl b/Lab2_VHDL/designer/LedBlinkingDSpeed/rptstyle.xsl new file mode 100644 index 0000000..c0bf831 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/rptstyle.xsl @@ -0,0 +1,96 @@ + + + + + + + + + + + + + + + +

+ + + +

+ + + +

+ + + + +

+ + + + +

+ + + +
+ + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_compile.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_compile.tcl new file mode 100644 index 0000000..3127a52 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_compile.tcl @@ -0,0 +1,103 @@ +set_defvar -name {SPEED} -value {STD} +set_defvar -name {VOLTAGE} -value {1.2} +set_defvar -name {TEMPR} -value {COM} +set_defvar -name {PART_RANGE} -value {COM} +set_defvar -name {IO_DEFT_STD} -value {LVCMOS33} +set_defvar -name {PACOMP_PARPT_MAX_NET} -value {10} +set_defvar -name {PA4_GB_MAX_RCLKINT_INSERTION} -value {16} +set_defvar -name {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT} -value {300} +set_defvar -name {PA4_GB_MAX_FANOUT_DATA_MOVE} -value {5000} +set_defvar -name {PA4_GB_HIGH_FANOUT_THRESHOLD} -value {5000} +set_defvar -name {PA4_GB_COUNT} -value {16} +set_defvar -name {RESTRICTPROBEPINS} -value {0} +set_defvar -name {RESTRICTSPIPINS} -value {0} +set_defvar -name {PDC_IMPORT_HARDERROR} -value {1} +set_defvar -name {PA4_IDDQ_FF_FIX} -value {1} +set_defvar -name {BLOCK_PLACEMENT_CONFLICTS} -value {ERROR} +set_defvar -name {BLOCK_ROUTING_CONFLICTS} -value {LOCK} +set_defvar -name {RTG4_MITIGATION_ON} -value {0} +set_defvar -name {USE_CONSTRAINT_FLOW} -value True + +set_compile_info \ + -category {"Device Selection"} \ + -name {"Family"} \ + -value {"IGLOO2"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Device"} \ + -value {"M2GL025"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Package"} \ + -value {"256 VF"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Speed Grade"} \ + -value {"STD"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Temp"} \ + -value {"0:25:85"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Voltage"} \ + -value {"1.26:1.20:1.14"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Core Voltage"} \ + -value {"1.2V"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Ramp Rate"} \ + -value {"100ms Minimum"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"System Controller Suspend Mode"} \ + -value {"No"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"PLL Supply Voltage"} \ + -value {"3.3V"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Default I/O technology"} \ + -value {"LVCMOS 3.3V"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Restrict Probe Pins"} \ + -value {"No"} +set_compile_info \ + -category {"Device Selection"} \ + -name {"Restrict SPI Pins"} \ + -value {"No"} +set_compile_info \ + -category {"Source Files"} \ + -name {"Topcell"} \ + -value {"LedBlinkingDSpeed"} +set_compile_info \ + -category {"Source Files"} \ + -name {"Format"} \ + -value {"EDIF"} +set_compile_info \ + -category {"Source Files"} \ + -name {"Source"} \ + -value {"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn"} +set_compile_info \ + -category {"Options"} \ + -name {"Enable Single Event Transient mitigation"} \ + -value {"false"} +set_compile_info \ + -category {"Options"} \ + -name {"Enable Design Separation Methodology"} \ + -value {"false"} +set_compile_info \ + -category {"Options"} \ + -name {"Limit the number of high fanout nets to display to"} \ + -value {"10"} +compile \ + -desdir {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed} \ + -design LedBlinkingDSpeed \ + -fam IGLOO2 \ + -die PA4MGL2500_N \ + -pkg vf256 \ + -merge_pdc 0 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_create_clocklist.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_create_clocklist.tcl new file mode 100644 index 0000000..c4c4bfe --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_create_clocklist.tcl @@ -0,0 +1,4 @@ +set_family {IGLOO2} +read_sdc {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\LedBlinkingDSpeed_sdc.sdc} +write_clock_list {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\clocklist.txt} + diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_export_netlist.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_export_netlist.tcl new file mode 100644 index 0000000..d6993ed --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_export_netlist.tcl @@ -0,0 +1,4 @@ +set_device -fam IGLOO2 +read_edif \ + -file {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn} +write_vhdl -file {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.vhd} diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_mapper.def b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_mapper.def new file mode 100644 index 0000000..cb9dcd9 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_mapper.def @@ -0,0 +1,28 @@ +DESIGN=LedBlinkingDSpeed +DESDIR=C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed +FAM=IGLOO2 +DIE=PA4MGL2500_N +PACKAGE=vf256 +SPEED=STD +VOLTAGE=1.2 +TEMPR=COM +VOLTR=COM +VCCI_1.2_VOLTR=COM +VCCI_1.5_VOLTR=COM +VCCI_1.8_VOLTR=COM +VCCI_2.5_VOLTR=COM +VCCI_3.3_VOLTR=COM +RESTRICTPROBEPINS=0 +RESTRICTSPIPINS=0 +DSW_VCCA_VOLTAGE_RAMP_RATE=100_MS +PLL_SUPPLY=PLL_SUPPLY_33 +SYSTEM_CONTROLLER_SUSPEND_MODE=0 +PA4_URAM_FF_CONFIG=SUSPEND +PA4_SRAM_FF_CONFIG=SUSPEND +PA4_MSS_FF_CLOCK=RCOSC_1MHZ +INIT_LOCK_FILE= +MSVT_EXPORT_DATA=0 +NETLIST_TYPE=EDIF +TARGET_DEVICES_FOR_MIGRATION='PA4MGL2500_N ' +RESTRICTPROBEPINS=0 +RESTRICTSPIPINS=0 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_pinrpt.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_pinrpt.tcl new file mode 100644 index 0000000..1c42503 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_pinrpt.tcl @@ -0,0 +1,10 @@ +DESIGN=LedBlinkingDSpeed +DESDIR=C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed +TARGET_DIR=C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed +FAM=IGLOO2 +DIE=PA4MGL2500_N +PACKAGE=vf256 +PINRPT_BY_NAME=1 +PINRPT_BY_NUMBER=1 +BANK_REPORT=1 +IOREG_REPORT=1 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer.def b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer.def new file mode 100644 index 0000000..59cf04d --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer.def @@ -0,0 +1,30 @@ +DESIGN=LedBlinkingDSpeed +DESDIR=C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed +FAM=IGLOO2 +DIE=PA4MGL2500_N +PACKAGE=vf256 +SPEED=STD +VOLTAGE=1.2 +TEMPR=COM +VOLTR=COM +VCCI_1.2_VOLTR=COM +VCCI_1.5_VOLTR=COM +VCCI_1.8_VOLTR=COM +VCCI_2.5_VOLTR=COM +VCCI_3.3_VOLTR=COM +PDC_IMPORT_HARDERROR=1 +LAYOUT_MODE=TIMING_DRIVEN +INCREMENTAL_MODE=OFF +PA4_LAYOUT_HIGH_EFFORT_MODE=0 +PDPR=0 +PA4_PHYS_OPT_MODE=0 +PA4_LAYOUT_SEQ_OPT_MODE=0 +MINDELAYG4_REPAIR=1 +RANDOM_SEED=0 +NETLIST_TYPE=EDIF +LAYOUT_STATE=NOT_VALID +PDC_FILE=C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\io\LedBlinkingDSpeed.io.pdc,, +USE_CONSTRAINT_FLOW=1 +TARGET_DEVICES_FOR_MIGRATION='PA4MGL2500_N ' +RESTRICTPROBEPINS=0 +RESTRICTSPIPINS=0 diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage.tcl new file mode 100644 index 0000000..d3bb124 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage.tcl @@ -0,0 +1,6 @@ +set_family {IGLOO2} +read_adl {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed.adl} +map_netlist +read_sdc {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\LedBlinkingDSpeed_sdc.sdc} +check_constraints {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\placer_coverage.log} +write_sdc -strict {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\place_route.sdc} diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage_st_shell_cmd.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage_st_shell_cmd.tcl new file mode 100644 index 0000000..572d3c1 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage_st_shell_cmd.tcl @@ -0,0 +1,13 @@ +read_sdc -scenario "place_and_route" -netlist "user" -pin_separator "/" -ignore_errors {C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/place_route.sdc} +set_options -tdpr_scenario "place_and_route" +save +set_options -analysis_scenario "place_and_route" +set coverage [report \ + -type constraints_coverage \ + -format xml \ + -slacks no \ + {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_place_and_route_constraint_coverage.xml}] +set reportfile {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\coverage_placeandroute} +set fp [open $reportfile w] +puts $fp $coverage +close $fp diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage_st_shell_des.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage_st_shell_des.tcl new file mode 100644 index 0000000..5ba1b53 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_coverage_st_shell_des.tcl @@ -0,0 +1,20 @@ +set_device \ + -family IGLOO2 \ + -die PA4MGL2500_N \ + -package vf256 \ + -speed STD \ + -tempr {COM} \ + -voltr {COM} +set_def {VOLTAGE} {1.2} +set_def {VCCI_1.2_VOLTR} {COM} +set_def {VCCI_1.5_VOLTR} {COM} +set_def {VCCI_1.8_VOLTR} {COM} +set_def {VCCI_2.5_VOLTR} {COM} +set_def {VCCI_3.3_VOLTR} {COM} +set_def {RTG4_MITIGATION_ON} {0} +set_def USE_CONSTRAINTS_FLOW 1 +set_def NETLIST_TYPE EDIF +set_name LedBlinkingDSpeed +set_workdir {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed} +set_log {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_coverage_pr.log} +set_design_state pre_layout diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_st_shell_cmd.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_st_shell_cmd.tcl new file mode 100644 index 0000000..94c447e --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_st_shell_cmd.tcl @@ -0,0 +1,6 @@ +read_sdc -scenario "place_and_route" -netlist "user" -pin_separator "/" -ignore_errors {C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/place_route.sdc} +set_options -tdpr_scenario "place_and_route" +save +set_options -analysis_scenario "place_and_route" +report -type combinational_loops -format xml {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_layout_combinational_loops.xml} +report -type slack {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\pinslacks.txt} diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_st_shell_des.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_st_shell_des.tcl new file mode 100644 index 0000000..3a9dafa --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_placer_st_shell_des.tcl @@ -0,0 +1,20 @@ +set_device \ + -family IGLOO2 \ + -die PA4MGL2500_N \ + -package vf256 \ + -speed STD \ + -tempr {COM} \ + -voltr {COM} +set_def {VOLTAGE} {1.2} +set_def {VCCI_1.2_VOLTR} {COM} +set_def {VCCI_1.5_VOLTR} {COM} +set_def {VCCI_1.8_VOLTR} {COM} +set_def {VCCI_2.5_VOLTR} {COM} +set_def {VCCI_3.3_VOLTR} {COM} +set_def {RTG4_MITIGATION_ON} {0} +set_def USE_CONSTRAINTS_FLOW 1 +set_def NETLIST_TYPE EDIF +set_name LedBlinkingDSpeed +set_workdir {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed} +set_log {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed_sdc.log} +set_design_state pre_layout diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_prober.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_prober.tcl new file mode 100644 index 0000000..277c248 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_prober.tcl @@ -0,0 +1,8 @@ +probe \ + -desdir {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed} \ + -design LedBlinkingDSpeed \ + -fam IGLOO2 \ + -die PA4MGL2500_N \ + -pkg vf256 \ + -use_mvn_pdc 0 \ + -use_last_placement 0 \ No newline at end of file diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_router.def b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_router.def new file mode 100644 index 0000000..cbd5294 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_router.def @@ -0,0 +1,20 @@ +DESIGN=LedBlinkingDSpeed +DESDIR=C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed +FAM=IGLOO2 +DIE=PA4MGL2500_N +PACKAGE=vf256 +SPEED=STD +VOLTAGE=1.2 +TEMPR=COM +VOLTR=COM +VCCI_1.2_VOLTR=COM +VCCI_1.5_VOLTR=COM +VCCI_1.8_VOLTR=COM +VCCI_2.5_VOLTR=COM +VCCI_3.3_VOLTR=COM +LAYOUT_MODE=TIMING_DRIVEN +INCREMENTAL_MODE=OFF +PA4_LAYOUT_HIGH_EFFORT_MODE=0 +MINDELAYG4_REPAIR=1 +NETLIST_TYPE=EDIF +LAYOUT_STATE=NOT_VALID diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_rwnetlist.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_rwnetlist.tcl new file mode 100644 index 0000000..2ce0bab --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_rwnetlist.tcl @@ -0,0 +1,4 @@ +set_device -fam IGLOO2 +read_edif \ + -file {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn} +write_adl -file {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed.adl} diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_tao.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_tao.tcl new file mode 100644 index 0000000..7d9fb63 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_tao.tcl @@ -0,0 +1,11 @@ +set_family {IGLOO2} +read_vhdl -mode vhdl_2008 {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd} +read_vhdl -mode vhdl_2008 {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd} +read_vhdl -mode vhdl_2008 {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd} +read_vhdl -mode vhdl_2008 {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd} +read_vhdl -mode vhdl_2008 {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd} +set_top_level {LedBlinkingDSpeed} +map_netlist +read_sdc {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\LedBlinkingDSpeed_sdc.sdc} +check_constraints {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\synthesis_sdc_errors.log} +write_fdc {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc} diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/run_tao_adl.tcl b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_tao_adl.tcl new file mode 100644 index 0000000..4322d41 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/run_tao_adl.tcl @@ -0,0 +1,6 @@ +set_family {IGLOO2} +read_adl {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\LedBlinkingDSpeed.adl} +map_netlist +read_sdc {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\LedBlinkingDSpeed_sdc.sdc} +check_constraints {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\placer_sdc_errors.log} +write_sdc -strict {C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\place_route.sdc} diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc b/Lab2_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc new file mode 100644 index 0000000..5675795 --- /dev/null +++ b/Lab2_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc @@ -0,0 +1,7 @@ +# Microsemi Corp. +# Date: 2016-Oct-23 02:59:29 +# This file was generated based on the following SDC source files: +# C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/constraint/LedBlinkingDSpeed_sdc.sdc +# + +create_clock -name {LedBlinkingDSpeed|clk} -period 20 -waveform {0 10 } [ get_ports { clk } ] diff --git a/Lab2_VHDL/designer/LedBlinkingDSpeed/user_sets.txt b/Lab2_VHDL/designer/LedBlinkingDSpeed/user_sets.txt new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/designer/impl1/LedBlinkingDSpeed.ide_des b/Lab2_VHDL/designer/impl1/LedBlinkingDSpeed.ide_des new file mode 100644 index 0000000..3214dc9 --- /dev/null +++ b/Lab2_VHDL/designer/impl1/LedBlinkingDSpeed.ide_des @@ -0,0 +1,10 @@ +KEY IDE_DES_TOOL "Ide" +KEY IDE_DES_ADB_PATH "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\impl1\LedBlinkingDSpeed.adb" +LIST SOURCE_FILES +VALUE "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\io\LedBlinkingDSpeed.io.pdc;pdc" +VALUE "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\constraint\LedBlinkingDSpeed_sdc.sdc;sdc" +ENDLIST +LIST OPTIONAL_FILES +ENDLIST +LIST VCD_FILES +ENDLIST diff --git a/Lab2_VHDL/Lab2_VHDL/hdl/ClkGen.vhd b/Lab2_VHDL/hdl/ClkGen.vhd similarity index 100% rename from Lab2_VHDL/Lab2_VHDL/hdl/ClkGen.vhd rename to Lab2_VHDL/hdl/ClkGen.vhd diff --git a/Lab2_VHDL/Lab2_VHDL/hdl/ClkGenNoSwitch.vhd b/Lab2_VHDL/hdl/ClkGenNoSwitch.vhd similarity index 100% rename from Lab2_VHDL/Lab2_VHDL/hdl/ClkGenNoSwitch.vhd rename to Lab2_VHDL/hdl/ClkGenNoSwitch.vhd diff --git a/Lab2_VHDL/Lab2_VHDL/hdl/Display.vhd b/Lab2_VHDL/hdl/Display.vhd similarity index 100% rename from Lab2_VHDL/Lab2_VHDL/hdl/Display.vhd rename to Lab2_VHDL/hdl/Display.vhd diff --git a/Lab2_VHDL/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd b/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd similarity index 95% rename from Lab2_VHDL/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd rename to Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd index 5067b95..8c2ba2a 100644 --- a/Lab2_VHDL/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd +++ b/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd @@ -83,17 +83,16 @@ architecture architecture_LedBlinkingDSpeed of LedBlinkingDSpeed is -- Scale Factor used to simulate for Lab1 -- They are shorter times to make the simulation go quicker -- Comment these if you want to make real hardware - signal Scale_Factor0 : std_logic_vector(31 downto 0) := "00000000000000000000001111101000"; --every 20 us - signal Scale_Factor1 : std_logic_vector(31 downto 0) := "00000000000000000000000011111010"; --every 5 us - signal Scale_Factor3 : std_logic_vector(31 downto 0) := "00000000000000000000000111110100"; --every 10 us + --signal Scale_Factor0 : std_logic_vector(31 downto 0) := "00000000000000000000001111101000"; --every 20 us + --signal Scale_Factor1 : std_logic_vector(31 downto 0) := "00000000000000000000000011111010"; --every 5 us + --signal Scale_Factor3 : std_logic_vector(31 downto 0) := "00000000000000000000000111110100"; --every 10 us --------------------------------------------------------------------------------------------------------------- -- Scale Factor used to program the board for Lab1 -- They provide longer delays so you can see the lEDs blink -- Comment these factors if you want to simulate - --signal Scale_Factor0 : std_logic_vector(31 downto 0) := "00000101111101011110000100000000"; --every 2 sec - --signal Scale_Factor1 : std_logic_vector(31 downto 0) := "00000001011111010111100001000000"; --every 0.5 sec - --signal Scale_Factor3 : std_logic_vector(31 downto 0) := "00000010111110101111000010000000"; --every 1 sec - --------------------------------------------------------------------------------------------------------------- + signal Scale_Factor0 : std_logic_vector(31 downto 0) := "00000101111101011110000100000000"; --every 2 sec + signal Scale_Factor1 : std_logic_vector(31 downto 0) := "00000001011111010111100001000000"; --every 0.5 sec + signal Scale_Factor3 : std_logic_vector(31 downto 0) := "00000010111110101111000010000000"; --every 1 sec --------------------------------------------------------------------------------------------------------------- -- Scale Factor used to program the board for Lab 2 -- These change the Blink rates from Lab1 for Lab2 -- Comment these factors if you want to simulate diff --git a/Lab2_VHDL/Lab2_VHDL/hdl/Reset_out.vhd b/Lab2_VHDL/hdl/Reset_out.vhd similarity index 100% rename from Lab2_VHDL/Lab2_VHDL/hdl/Reset_out.vhd rename to Lab2_VHDL/hdl/Reset_out.vhd diff --git a/Lab2_VHDL/simulation/ENVM_init.mem b/Lab2_VHDL/simulation/ENVM_init.mem new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/simulation/modelsim.ini b/Lab2_VHDL/simulation/modelsim.ini new file mode 100644 index 0000000..e3b9791 --- /dev/null +++ b/Lab2_VHDL/simulation/modelsim.ini @@ -0,0 +1,12 @@ +[Library] +others = $MODEL_TECH/../modelsim.ini +smartfusion2 = C:/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2 +postsynth = postsynth +IGLOO2 = C:/tools/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2 +syncad_vhdl_lib = C:\Microsemi\Libero_SoC_v11.7\Designer/lib/actel/syncad_vhdl_lib + +[vcom] +VHDL93 = 1 + +[vsim] +IterationLimit = 5000 diff --git a/Lab2_VHDL/simulation/modelsim.ini.sav b/Lab2_VHDL/simulation/modelsim.ini.sav new file mode 100644 index 0000000..f17c176 --- /dev/null +++ b/Lab2_VHDL/simulation/modelsim.ini.sav @@ -0,0 +1,12 @@ +[Library] +others = $MODEL_TECH/../modelsim.ini +smartfusion2 = C:/tools/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2 +syncad_vhdl_lib = C:\tools\Microsemi\Libero_SoC_v11.7\Designer/lib/actel/syncad_vhdl_lib + +postsynth = postsynth +IGLOO2 = C:/tools/Microsemi/Libero_SoC_v11.7///Designer//lib//modelsim//precompiled/vhdl/smartfusion2 +[vcom] +VHDL93 = 1 + +[vsim] +IterationLimit = 5000 diff --git a/Lab2_VHDL/simulation/postsynth/_info b/Lab2_VHDL/simulation/postsynth/_info new file mode 100644 index 0000000..1dd45b4 --- /dev/null +++ b/Lab2_VHDL/simulation/postsynth/_info @@ -0,0 +1,314 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dC:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/simulation +Eclkgen +Z1 w1477216578 +Z2 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 +Z3 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 +R0 +Z4 8C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/synthesis/LedBlinkingDSpeed.vhd +Z5 FC:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/synthesis/LedBlinkingDSpeed.vhd +l0 +L985 +V<9Slo3P>A=4zFCbWB_5TQ1 +!s100 >j`i@kQe[2ZoobSCm@>dE1 +Z6 OW;C;10.4c;61 +33 +Z7 !s110 1477216663 +!i10b 1 +Z8 !s108 1477216663.000000 +Z9 !s90 -reportprogress|300|-2008|-explicit|-work|postsynth|C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/synthesis/LedBlinkingDSpeed.vhd| +Z10 !s107 C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/synthesis/LedBlinkingDSpeed.vhd| +!i113 1 +Z11 o-2008 -explicit -work postsynth -O0 +Adef_arch +R2 +R3 +Z12 DEx4 work 6 clkgen 0 22 <9Slo3P>A=4zFCbWB_5TQ1 +l1066 +L995 +VG[bmDn]CiI3oDz_Xc@T_]SknZSHhPoNeKl0 +R6 +33 +R7 +!i10b 1 +R8 +R9 +R10 +!i113 1 +R11 +Adef_arch +R2 +R3 +Z14 DEx4 work 14 clkgennoswitch 0 22 fEV^[5^oS7E;A_UPcniKL2 +l715 +L634 +VU>2648<=4THZaVfPO]6?A2 +!s100 6C4RigKMa9^iRQ@0SE7bK0 +R6 +33 +R7 +!i10b 1 +R8 +R9 +R10 +!i113 1 +R11 +Eclkgennoswitch_1 +R1 +R2 +R3 +R0 +R4 +R5 +l0 +L8 +VFLKYocgZicC>VGi[lR>aI0 +!s100 IkAL:j?ICY0VMUBX4c?DI3 +R6 +33 +R7 +!i10b 1 +R8 +R9 +R10 +!i113 1 +R11 +Adef_arch +R2 +R3 +Z15 DEx4 work 16 clkgennoswitch_1 0 22 FLKYocgZicC>VGi[lR>aI0 +l90 +L17 +VGg1AG5^DH:R2IXL>TMb<[0 +!s100 P?_nbFUHnEJikz:V1lEM@1 +R6 +33 +R7 +!i10b 1 +R8 +R9 +R10 +!i113 1 +R11 +Edisplay +R1 +R2 +R3 +R0 +R4 +R5 +l0 +L891 +VbkSWlm2zJiPZ8Z3fjZH3E0 +!s100 QRzWdMaIWBV_Fg=1=z3[B3 +R6 +33 +R7 +!i10b 1 +R8 +R9 +R10 +!i113 1 +R11 +Adef_arch +R2 +R3 +Z16 DEx4 work 7 display 0 22 bkSWlm2zJiPZ8Z3fjZH3E0 +l946 +L907 +VzacilQSnDFTBBkb?dIHJc2 +R6 +33 +R7 +!i10b 1 +R8 +R9 +R10 +!i113 1 +R11 +Eledblinkingdspeed +R1 +R2 +R3 +R0 +R4 +R5 +l0 +L1231 +VkR1l>7[_cX9WPaM>0Ti[h1 +!s100 ;BUnTb2nU[U9ie`WGT4o?0 +R6 +33 +R7 +!i10b 1 +R8 +R9 +R10 +!i113 1 +R11 +Adef_arch +R12 +R16 +R14 +Z17 DEx4 work 9 reset_out 0 22 oilXSHPUi`dJ=;iA?UDiM2 +R13 +R15 +R2 +R3 +DEx4 work 17 ledblinkingdspeed 0 22 kR1l>7[_cX9WPaM>0Ti[h1 +l1346 +L1244 +V`e5LgbYSdU=TnGTfTL@o4ZT]I3 +Z26 !s100 ;c70DGf`[[W4Lo3A:UAZP1 +R6 +33 +R7 +!i10b 1 +R8 +R22 +R23 +!i113 1 +R11 +Ereset_out +R1 +R2 +R3 +R0 +R4 +R5 +l0 +L542 +VoilXSHPUi`dJ=;iA?UDiM2 +!s100 BV^bOfFY4mWe0U8smartgenVHDLVHDL \ No newline at end of file diff --git a/Lab2_VHDL/stimulus/LedBlinkingDSpeed_tb.vhd b/Lab2_VHDL/stimulus/LedBlinkingDSpeed_tb.vhd new file mode 100644 index 0000000..be8a0ea --- /dev/null +++ b/Lab2_VHDL/stimulus/LedBlinkingDSpeed_tb.vhd @@ -0,0 +1,154 @@ +-------------------------------------------------------------------------------------------------------- +-- Company: Future Electronics Inc. +-- +-- File: LedBlinkingDSpeed_tb.vhd +-- File history: +-- Rev. 1: 8/23/2016 +-- Rev. 2: 10/07/2016 - added STOP command - Stefany Eck +-- Description: +-- +-- Testbench +-- +-- Targeted device: +-- Author: Giovanna Franco +-- +-------------------------------------------------------------------------------------------------------- +-- Copyright (c) 2016 Future Electronics +-- All rights reserved. +-------------------------------------------------------------------------------------------------------- +-- Disclaimer of Warranty +-- ALL MATERIALS, INFORMATION AND SERVICES ARE PROVIDED ?AS-IS? AND ?AS-AVAILABLE? FOR YOUR USE. +-- FUTURE ELECTRONICS DISCLAIMS ALL WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING +-- BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE, TITLE, OR NON-INFRINGEMENT. +-- YOU ACKNOWLEDGE AND AGREE THAT THE REFERENCE DESIGNS AND OTHER SUCH DESIGN MATERIALS INCLUDED +-- HEREIN ARE PROVIDED AS AN EXAMPLE ONLY AND THAT YOU WILL EXERCISE YOUR OWN INDEPENDENT ANALYSIS +-- AND JUDGEMENT IN YOUR USE OF THESE MATERIALS. FUTURE ELECTRONICS ASSUMES NO LIABILITY FOR YOUR +-- USE OF THESE MATERIALS FOR YOUR PRODUCT DESIGNS. +-- +-- Indemnification +-- You agree to indemnify, defend and hold Future Electronics and all of its agents, directors, +-- employees, information providers, licensors and licensees, and affiliated companies +-- (collectively, ?Indemnified Parties?), harmless from and against any and all liability +-- and costs (including, without limitation, attorneys? fees and costs), incurred by the +-- Indemnified Parties in connection with any claim arising out of any breach by You of these +-- Terms and Conditions of Use or any representations or warranties made by You herein. +-- You will cooperate as fully as reasonably required in Future Electronics? defense of any claim. +-- Future Electronics reserves the right, at its own expense, to assume the exclusive defense and +-- control of any matter otherwise subject to indemnification by You and You shall not in any event +-- settle any matter without the written consent of Future Electronics. +-- +-- Limitation of Liability +-- UNDER NO CIRCUMSTANCES SHALL FUTURE ELECTRONICS, NOR ITS AGENTS, DIRECTORS, EMPLOYEES, +-- INFORMATION PROVIDERS, LICENSORS AND LICENSEE, AND AFFILIATED COMPANIES BE LIABLE FOR ANY DAMAGES, +-- INCLUDING WITHOUT LIMITATION, DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, CONSEQUENTIAL, OR +-- OTHER DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS, LOST REVENUES, OR SIMILAR ECONOMIC LOSS), +-- WHETHER IN CONTRACT, TORT, OR OTHERWISE, ARISING OUT OF THE USE OR INABILITY TO USE THE MATERIALS +-- PROVIDED AS A REFERENCE DESIGN, EVEN IF WE ARE ADVISED OF THE POSSIBILITY THEREOF, NOR FOR ANY CLAIM +-- BY A THIRD PARTY. +-------------------------------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +library std; +use std.env.all; + +entity LedBlinkingDSpeed_tb is +end LedBlinkingDSpeed_tb; + +architecture behavioral of LedBlinkingDSpeed_tb is + + constant SYSCLK_PERIOD : time := 20 ns; + + signal SYSCLK : std_logic := '0'; + --signal NSYSRESET : std_logic := '0'; + signal SWITCH1 : std_logic := '0'; + signal SWITCH2 : std_logic := '0'; + signal GREEN1 : std_logic := '0'; + signal RED1 : std_logic := '0'; + signal GREEN2 : std_logic := '0'; + signal RED2 : std_logic := '0'; + + component LedBlinkingDSpeed + -- ports + port( + -- Inputs + clk : in std_logic; + SW1 : in std_logic; + SW2 : in std_logic; + --reset : in std_logic; + + -- Outputs + green_led1 : out std_logic; + red_led1 : out std_logic; + green_led2 : out std_logic; + red_led2 : out std_logic + ); + end component; + +begin + + process + variable vhdl_initial : BOOLEAN := TRUE; + + begin + if ( vhdl_initial ) then + -- Reset the Outputs to zero + SWITCH1 <= '1'; + SWITCH2 <= '1'; + wait for (SYSCLK_PERIOD * 10); --10 SYSCLK periods (10*20 ns = 200 ns) + + -- Test Case 1 + -- Set SWITCH1 to '0' and SWITCH2 to '0' for 10000 clock period + -- GREEN1 blinks every 10 us and RED1 is turned off + -- RED2 blinks every 20 us and GREEN2 is turned off + SWITCH1 <= '0'; + SWITCH2 <= '0'; + wait for (SYSCLK_PERIOD * 10000); --10000 SYSCLK periods (10000*20 ns = 200,000 ns) + + -- Test Case 2 + -- Set SWITCH1 to '0' for 10000 clock period + -- GREEN1 blinks every 10 us and RED1 is turned off + SWITCH1 <= '0'; + -- Set SWITCH2 to '1' for 10000 clock period + -- RED2 blinks every 10 us and GREEN2 is turned off + SWITCH2 <= '1'; + wait for (SYSCLK_PERIOD * 10000); + + -- Test Case 3 + -- Set SWITCH1 to '1' for 10000 clock period + -- GREEN1 blinks every 5 us and RED1 is turned off + SWITCH1 <= '1'; + -- Set SWITCH2 to '0' for 10000 clock period + -- RED2 blinks every 20 us and GREEN2 is turned off + SWITCH2 <= '0'; + wait for (SYSCLK_PERIOD * 10000); + stop(0); + end if; + end process; + + -- Clock Driver + SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 ); + + -- Instantiate Unit Under Test: LedBlinkingDSpeed + LedBlinkingDSpeed_0 : LedBlinkingDSpeed + -- port map + port map( + -- Inputs + clk => SYSCLK, + SW1 => SWITCH1, + SW2 => SWITCH2, + --reset => NSYSRESET, + + -- Outputs + green_led1 => GREEN1, + red_led1 => RED1, + green_led2 => GREEN2, + red_led2 => RED2 + + -- Inouts + + ); + +end behavioral; \ No newline at end of file diff --git a/Lab2_VHDL/synthesis/.recordref b/Lab2_VHDL/synthesis/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.edn b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.edn new file mode 100644 index 0000000..e1e83ed --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.edn @@ -0,0 +1,3976 @@ +(edif LedBlinkingDSpeed + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2016 10 23 2 59 33) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "J-2015.03M-SP1-2, mapper mapact, Build 1659R")) + ) + ) + (library ACG4 + (edifLevel 0) + (technology (numberDefinition )) + (cell CFG3 (cellType GENERIC) + (property dont_use (string "false")) + (property dont_touch (string "false")) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port Y (direction OUTPUT)) + ) + ) + ) + (cell GND (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Y (direction OUTPUT)) + ) + (property is_pwr (integer 1)) + ) + ) + (cell VCC (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Y (direction OUTPUT)) + ) + (property is_pwr (integer 1)) + ) + ) + (cell CLKINT (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Y (direction OUTPUT)) + (port A (direction INPUT)) + ) + ) + ) + (cell OUTBUF (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port PAD (direction OUTPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell INBUF (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Y (direction OUTPUT)) + (port PAD (direction INPUT)) + ) + ) + ) + (cell SLE (cellType GENERIC) + (property is_sequential (integer 1)) + (property dont_use (string "false")) + (property dont_touch (string "false")) + (view PRIM (viewType NETLIST) + (interface + (port Q (direction OUTPUT)) + (port ADn (direction INPUT)) + (port ALn (direction INPUT)) + (port CLK (direction INPUT)) + (port D (direction INPUT)) + (port EN (direction INPUT)) + (port LAT (direction INPUT)) + (port SD (direction INPUT)) + (port SLn (direction INPUT)) + ) + ) + ) + (cell ARI1 (cellType GENERIC) + (property dont_use (string "false")) + (property dont_touch (string "false")) + (view PRIM (viewType NETLIST) + (interface + (port FCO (direction OUTPUT)) + (port S (direction OUTPUT)) + (port Y (direction OUTPUT)) + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port FCI (direction INPUT)) + ) + ) + ) + (cell CFG4 (cellType GENERIC) + (property dont_use (string "false")) + (property dont_touch (string "false")) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port Y (direction OUTPUT)) + ) + ) + ) + (cell CFG2 (cellType GENERIC) + (property dont_use (string "false")) + (property dont_touch (string "false")) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port Y (direction OUTPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell Display (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port green_led1_c (direction OUTPUT)) + (port reset (direction INPUT)) + (port clk_c (direction INPUT)) + (port red_led2_c (direction OUTPUT)) + (port SW2_c (direction INPUT)) + (port SW1_c (direction INPUT)) + (port led1 (direction INPUT)) + (port led2 (direction INPUT)) + (port led (direction INPUT)) + (port led0 (direction INPUT)) + ) + (contents + (instance green_led1 (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance red_led2 (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance red_led2_3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "F2D0")) + ) + (instance green_led1_4 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "FB40")) + ) + (instance GND (viewRef PRIM (cellRef GND (libraryRef ACG4))) ) + (instance VCC (viewRef PRIM (cellRef VCC (libraryRef ACG4))) ) + (net green_led1_c (joined + (portRef Q (instanceRef green_led1)) + (portRef green_led1_c) + )) + (net (rename VCCZ0 "VCC") (joined + (portRef Y (instanceRef VCC)) + (portRef SLn (instanceRef red_led2)) + (portRef EN (instanceRef red_led2)) + (portRef ADn (instanceRef red_led2)) + (portRef SLn (instanceRef green_led1)) + (portRef EN (instanceRef green_led1)) + (portRef ADn (instanceRef green_led1)) + )) + (net reset (joined + (portRef reset) + (portRef ALn (instanceRef red_led2)) + (portRef ALn (instanceRef green_led1)) + )) + (net clk_c (joined + (portRef clk_c) + (portRef CLK (instanceRef red_led2)) + (portRef CLK (instanceRef green_led1)) + )) + (net (rename green_led1Z0Z_4 "green_led1_4") (joined + (portRef Y (instanceRef green_led1_4)) + (portRef D (instanceRef green_led1)) + )) + (net (rename GNDZ0 "GND") (joined + (portRef Y (instanceRef GND)) + (portRef SD (instanceRef red_led2)) + (portRef LAT (instanceRef red_led2)) + (portRef SD (instanceRef green_led1)) + (portRef LAT (instanceRef green_led1)) + )) + (net red_led2_c (joined + (portRef Q (instanceRef red_led2)) + (portRef red_led2_c) + )) + (net (rename red_led2Z0Z_3 "red_led2_3") (joined + (portRef Y (instanceRef red_led2_3)) + (portRef D (instanceRef red_led2)) + )) + (net (rename sw2_c "SW2_c") (joined + (portRef SW2_c) + (portRef A (instanceRef green_led1_4)) + (portRef A (instanceRef red_led2_3)) + )) + (net (rename sw1_c "SW1_c") (joined + (portRef SW1_c) + (portRef B (instanceRef green_led1_4)) + (portRef B (instanceRef red_led2_3)) + )) + (net led1 (joined + (portRef led1) + (portRef C (instanceRef red_led2_3)) + )) + (net led2 (joined + (portRef led2) + (portRef D (instanceRef red_led2_3)) + )) + (net led (joined + (portRef led) + (portRef C (instanceRef green_led1_4)) + )) + (net led0 (joined + (portRef led0) + (portRef D (instanceRef green_led1_4)) + )) + ) + (property orig_inst_of (string "Display")) + ) + ) + (cell ClkGen_1 (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port led2 (direction OUTPUT)) + (port reset (direction INPUT)) + (port clk_c (direction INPUT)) + (port SW2_c (direction INPUT)) + ) + (contents + (instance tmp_clk (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_0 "cnt[0]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_1 "cnt[1]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_2 "cnt[2]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_3 "cnt[3]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_4 "cnt[4]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_5 "cnt[5]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_6 "cnt[6]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_7 "cnt[7]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_8 "cnt[8]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_9 "cnt[9]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_10 "cnt[10]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_11 "cnt[11]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_12 "cnt[12]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_13 "cnt[13]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_14 "cnt[14]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_15 "cnt[15]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_16 "cnt[16]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_17 "cnt[17]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_18 "cnt[18]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_19 "cnt[19]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_20 "cnt[20]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_21 "cnt[21]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_22 "cnt[22]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_23 "cnt[23]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_24 "cnt[24]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_25 "cnt[25]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_26 "cnt[26]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance un14_cntlto31_0_o3_RNIE29S2 (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "4F444")) + ) + (instance (rename cnt_RNIP91P5_0 "cnt_RNIP91P5[0]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI5IPL8_1 "cnt_RNI5IPL8[1]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIIRHIB_2 "cnt_RNIIRHIB[2]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI06AFE_3 "cnt_RNI06AFE[3]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIFH2CH_4 "cnt_RNIFH2CH[4]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIVTQ8K_5 "cnt_RNIVTQ8K[5]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIGBJ5N_6 "cnt_RNIGBJ5N[6]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI2QB2Q_7 "cnt_RNI2QB2Q[7]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIL94VS_8 "cnt_RNIL94VS[8]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI9QSRV_9 "cnt_RNI9QSRV[9]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI5LP731_10 "cnt_RNI5LP731[10]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI2HMJ61_11 "cnt_RNI2HMJ61[11]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI0EJV91_12 "cnt_RNI0EJV91[12]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIVBGBD1_13 "cnt_RNIVBGBD1[13]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIVADNG1_14 "cnt_RNIVADNG1[14]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI0BA3K1_15 "cnt_RNI0BA3K1[15]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI2C7FN1_16 "cnt_RNI2C7FN1[16]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI5E4RQ1_17 "cnt_RNI5E4RQ1[17]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI9H17U1_18 "cnt_RNI9H17U1[18]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIELUI12_19 "cnt_RNIELUI12[19]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIBISU42_20 "cnt_RNIBISU42[20]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI9GQA82_21 "cnt_RNI9GQA82[21]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI8FOMB2_22 "cnt_RNI8FOMB2[22]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI8FM2F2_23 "cnt_RNI8FM2F2[23]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI9GKEI2_24 "cnt_RNI9GKEI2[24]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIBIIQL2_25 "cnt_RNIBIIQL2[25]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance un14_cntlto31_0_a2 (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "45")) + ) + (instance un14_cntlto31_0_o2_0 (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "7F")) + ) + (instance un14_cntlto31_0_o2_3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "7FFF")) + ) + (instance un14_cntlto31_0_a2_1_3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0001")) + ) + (instance un7_cntlto31_0_a2_1 (viewRef PRIM (cellRef CFG2 (libraryRef ACG4))) + (property INIT (string "2")) + ) + (instance un14_cntlto31_0_o3_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "F7F5")) + ) + (instance un14_cntlto31_0_o3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0FDF")) + ) + (instance un7_cntlto31_0_a2_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "5551")) + ) + (instance un14_cntlto31_0_o3_0_RNIA4EM1 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0073")) + ) + (instance un7_cntlto31_0_a2 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0031")) + ) + (instance un7_cntlto31_0_a3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "000D")) + ) + (instance un7_cntlto31_0_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "FF10")) + ) + (instance GND (viewRef PRIM (cellRef GND (libraryRef ACG4))) ) + (instance VCC (viewRef PRIM (cellRef VCC (libraryRef ACG4))) ) + (net led2 (joined + (portRef Q (instanceRef tmp_clk)) + (portRef led2) + )) + (net (rename VCCZ0 "VCC") (joined + (portRef Y (instanceRef VCC)) + (portRef A (instanceRef cnt_RNIBIIQL2_25)) + (portRef A (instanceRef cnt_RNI9GKEI2_24)) + (portRef A (instanceRef cnt_RNI8FM2F2_23)) + (portRef A (instanceRef cnt_RNI8FOMB2_22)) + (portRef A (instanceRef cnt_RNI9GQA82_21)) + (portRef A (instanceRef cnt_RNIBISU42_20)) + (portRef A (instanceRef cnt_RNIELUI12_19)) + (portRef A (instanceRef cnt_RNI9H17U1_18)) + (portRef A (instanceRef cnt_RNI5E4RQ1_17)) + (portRef A (instanceRef cnt_RNI2C7FN1_16)) + (portRef A (instanceRef cnt_RNI0BA3K1_15)) + (portRef A (instanceRef cnt_RNIVADNG1_14)) + (portRef A (instanceRef cnt_RNIVBGBD1_13)) + (portRef A (instanceRef cnt_RNI0EJV91_12)) + (portRef A (instanceRef cnt_RNI2HMJ61_11)) + (portRef A (instanceRef cnt_RNI5LP731_10)) + (portRef A (instanceRef cnt_RNI9QSRV_9)) + (portRef A (instanceRef cnt_RNIL94VS_8)) + (portRef A (instanceRef cnt_RNI2QB2Q_7)) + (portRef A (instanceRef cnt_RNIGBJ5N_6)) + (portRef A (instanceRef cnt_RNIVTQ8K_5)) + (portRef A (instanceRef cnt_RNIFH2CH_4)) + (portRef A (instanceRef cnt_RNI06AFE_3)) + (portRef A (instanceRef cnt_RNIIRHIB_2)) + (portRef A (instanceRef cnt_RNI5IPL8_1)) + (portRef A (instanceRef cnt_RNIP91P5_0)) + (portRef FCI (instanceRef un14_cntlto31_0_o3_RNIE29S2)) + (portRef SLn (instanceRef cnt_26)) + (portRef ADn (instanceRef cnt_26)) + (portRef SLn (instanceRef cnt_25)) + (portRef ADn (instanceRef cnt_25)) + (portRef SLn (instanceRef cnt_24)) + (portRef ADn (instanceRef cnt_24)) + (portRef SLn (instanceRef cnt_23)) + (portRef ADn (instanceRef cnt_23)) + (portRef SLn (instanceRef cnt_22)) + (portRef ADn (instanceRef cnt_22)) + (portRef SLn (instanceRef cnt_21)) + (portRef ADn (instanceRef cnt_21)) + (portRef SLn (instanceRef cnt_20)) + (portRef ADn (instanceRef cnt_20)) + (portRef SLn (instanceRef cnt_19)) + (portRef ADn (instanceRef cnt_19)) + (portRef SLn (instanceRef cnt_18)) + (portRef ADn (instanceRef cnt_18)) + (portRef SLn (instanceRef cnt_17)) + (portRef ADn (instanceRef cnt_17)) + (portRef SLn (instanceRef cnt_16)) + (portRef ADn (instanceRef cnt_16)) + (portRef SLn (instanceRef cnt_15)) + (portRef ADn (instanceRef cnt_15)) + (portRef SLn (instanceRef cnt_14)) + (portRef ADn (instanceRef cnt_14)) + (portRef SLn (instanceRef cnt_13)) + (portRef ADn (instanceRef cnt_13)) + (portRef SLn (instanceRef cnt_12)) + (portRef ADn (instanceRef cnt_12)) + (portRef SLn (instanceRef cnt_11)) + (portRef ADn (instanceRef cnt_11)) + (portRef SLn (instanceRef cnt_10)) + (portRef ADn (instanceRef cnt_10)) + (portRef SLn (instanceRef cnt_9)) + (portRef ADn (instanceRef cnt_9)) + (portRef SLn (instanceRef cnt_8)) + (portRef ADn (instanceRef cnt_8)) + (portRef SLn (instanceRef cnt_7)) + (portRef ADn (instanceRef cnt_7)) + (portRef SLn (instanceRef cnt_6)) + (portRef ADn (instanceRef cnt_6)) + (portRef SLn (instanceRef cnt_5)) + (portRef ADn (instanceRef cnt_5)) + (portRef SLn (instanceRef cnt_4)) + (portRef ADn (instanceRef cnt_4)) + (portRef SLn (instanceRef cnt_3)) + (portRef ADn (instanceRef cnt_3)) + (portRef SLn (instanceRef cnt_2)) + (portRef ADn (instanceRef cnt_2)) + (portRef SLn (instanceRef cnt_1)) + (portRef ADn (instanceRef cnt_1)) + (portRef SLn (instanceRef cnt_0)) + (portRef ADn (instanceRef cnt_0)) + (portRef SLn (instanceRef tmp_clk)) + (portRef ADn (instanceRef tmp_clk)) + )) + (net reset (joined + (portRef reset) + (portRef ALn (instanceRef cnt_26)) + (portRef ALn (instanceRef cnt_25)) + (portRef ALn (instanceRef cnt_24)) + (portRef ALn (instanceRef cnt_23)) + (portRef ALn (instanceRef cnt_22)) + (portRef ALn (instanceRef cnt_21)) + (portRef ALn (instanceRef cnt_20)) + (portRef ALn (instanceRef cnt_19)) + (portRef ALn (instanceRef cnt_18)) + (portRef ALn (instanceRef cnt_17)) + (portRef ALn (instanceRef cnt_16)) + (portRef ALn (instanceRef cnt_15)) + (portRef ALn (instanceRef cnt_14)) + (portRef ALn (instanceRef cnt_13)) + (portRef ALn (instanceRef cnt_12)) + (portRef ALn (instanceRef cnt_11)) + (portRef ALn (instanceRef cnt_10)) + (portRef ALn (instanceRef cnt_9)) + (portRef ALn (instanceRef cnt_8)) + (portRef ALn (instanceRef cnt_7)) + (portRef ALn (instanceRef cnt_6)) + (portRef ALn (instanceRef cnt_5)) + (portRef ALn (instanceRef cnt_4)) + (portRef ALn (instanceRef cnt_3)) + (portRef ALn (instanceRef cnt_2)) + (portRef ALn (instanceRef cnt_1)) + (portRef ALn (instanceRef cnt_0)) + (portRef ALn (instanceRef tmp_clk)) + )) + (net clk_c (joined + (portRef clk_c) + (portRef CLK (instanceRef cnt_26)) + (portRef CLK (instanceRef cnt_25)) + (portRef CLK (instanceRef cnt_24)) + (portRef CLK (instanceRef cnt_23)) + (portRef CLK (instanceRef cnt_22)) + (portRef CLK (instanceRef cnt_21)) + (portRef CLK (instanceRef cnt_20)) + (portRef CLK (instanceRef cnt_19)) + (portRef CLK (instanceRef cnt_18)) + (portRef CLK (instanceRef cnt_17)) + (portRef CLK (instanceRef cnt_16)) + (portRef CLK (instanceRef cnt_15)) + (portRef CLK (instanceRef cnt_14)) + (portRef CLK (instanceRef cnt_13)) + (portRef CLK (instanceRef cnt_12)) + (portRef CLK (instanceRef cnt_11)) + (portRef CLK (instanceRef cnt_10)) + (portRef CLK (instanceRef cnt_9)) + (portRef CLK (instanceRef cnt_8)) + (portRef CLK (instanceRef cnt_7)) + (portRef CLK (instanceRef cnt_6)) + (portRef CLK (instanceRef cnt_5)) + (portRef CLK (instanceRef cnt_4)) + (portRef CLK (instanceRef cnt_3)) + (portRef CLK (instanceRef cnt_2)) + (portRef CLK (instanceRef cnt_1)) + (portRef CLK (instanceRef cnt_0)) + (portRef CLK (instanceRef tmp_clk)) + )) + (net un7_cntlto31_0_0_0 (joined + (portRef Y (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef tmp_clk)) + )) + (net (rename sw2_c "SW2_c") (joined + (portRef SW2_c) + (portRef EN (instanceRef cnt_26)) + (portRef EN (instanceRef cnt_25)) + (portRef EN (instanceRef cnt_24)) + (portRef EN (instanceRef cnt_23)) + (portRef EN (instanceRef cnt_22)) + (portRef EN (instanceRef cnt_21)) + (portRef EN (instanceRef cnt_20)) + (portRef EN (instanceRef cnt_19)) + (portRef EN (instanceRef cnt_18)) + (portRef EN (instanceRef cnt_17)) + (portRef EN (instanceRef cnt_16)) + (portRef EN (instanceRef cnt_15)) + (portRef EN (instanceRef cnt_14)) + (portRef EN (instanceRef cnt_13)) + (portRef EN (instanceRef cnt_12)) + (portRef EN (instanceRef cnt_11)) + (portRef EN (instanceRef cnt_10)) + (portRef EN (instanceRef cnt_9)) + (portRef EN (instanceRef cnt_8)) + (portRef EN (instanceRef cnt_7)) + (portRef EN (instanceRef cnt_6)) + (portRef EN (instanceRef cnt_5)) + (portRef EN (instanceRef cnt_4)) + (portRef EN (instanceRef cnt_3)) + (portRef EN (instanceRef cnt_2)) + (portRef EN (instanceRef cnt_1)) + (portRef EN (instanceRef cnt_0)) + (portRef EN (instanceRef tmp_clk)) + )) + (net (rename GNDZ0 "GND") (joined + (portRef Y (instanceRef GND)) + (portRef D (instanceRef cnt_RNIBIIQL2_25)) + (portRef D (instanceRef cnt_RNI9GKEI2_24)) + (portRef D (instanceRef cnt_RNI8FM2F2_23)) + (portRef D (instanceRef cnt_RNI8FOMB2_22)) + (portRef D (instanceRef cnt_RNI9GQA82_21)) + (portRef D (instanceRef cnt_RNIBISU42_20)) + (portRef D (instanceRef cnt_RNIELUI12_19)) + (portRef D (instanceRef cnt_RNI9H17U1_18)) + (portRef D (instanceRef cnt_RNI5E4RQ1_17)) + (portRef D (instanceRef cnt_RNI2C7FN1_16)) + (portRef D (instanceRef cnt_RNI0BA3K1_15)) + (portRef D (instanceRef cnt_RNIVADNG1_14)) + (portRef D (instanceRef cnt_RNIVBGBD1_13)) + (portRef D (instanceRef cnt_RNI0EJV91_12)) + (portRef D (instanceRef cnt_RNI2HMJ61_11)) + (portRef D (instanceRef cnt_RNI5LP731_10)) + (portRef D (instanceRef cnt_RNI9QSRV_9)) + (portRef D (instanceRef cnt_RNIL94VS_8)) + (portRef D (instanceRef cnt_RNI2QB2Q_7)) + (portRef D (instanceRef cnt_RNIGBJ5N_6)) + (portRef D (instanceRef cnt_RNIVTQ8K_5)) + (portRef D (instanceRef cnt_RNIFH2CH_4)) + (portRef D (instanceRef cnt_RNI06AFE_3)) + (portRef D (instanceRef cnt_RNIIRHIB_2)) + (portRef D (instanceRef cnt_RNI5IPL8_1)) + (portRef D (instanceRef cnt_RNIP91P5_0)) + (portRef SD (instanceRef cnt_26)) + (portRef LAT (instanceRef cnt_26)) + (portRef SD (instanceRef cnt_25)) + (portRef LAT (instanceRef cnt_25)) + (portRef SD (instanceRef cnt_24)) + (portRef LAT (instanceRef cnt_24)) + (portRef SD (instanceRef cnt_23)) + (portRef LAT (instanceRef cnt_23)) + (portRef SD (instanceRef cnt_22)) + (portRef LAT (instanceRef cnt_22)) + (portRef SD (instanceRef cnt_21)) + (portRef LAT (instanceRef cnt_21)) + (portRef SD (instanceRef cnt_20)) + (portRef LAT (instanceRef cnt_20)) + (portRef SD (instanceRef cnt_19)) + (portRef LAT (instanceRef cnt_19)) + (portRef SD (instanceRef cnt_18)) + (portRef LAT (instanceRef cnt_18)) + (portRef SD (instanceRef cnt_17)) + (portRef LAT (instanceRef cnt_17)) + (portRef SD (instanceRef cnt_16)) + (portRef LAT (instanceRef cnt_16)) + (portRef SD (instanceRef cnt_15)) + (portRef LAT (instanceRef cnt_15)) + (portRef SD (instanceRef cnt_14)) + (portRef LAT (instanceRef cnt_14)) + (portRef SD (instanceRef cnt_13)) + (portRef LAT (instanceRef cnt_13)) + (portRef SD (instanceRef cnt_12)) + (portRef LAT (instanceRef cnt_12)) + (portRef SD (instanceRef cnt_11)) + (portRef LAT (instanceRef cnt_11)) + (portRef SD (instanceRef cnt_10)) + (portRef LAT (instanceRef cnt_10)) + (portRef SD (instanceRef cnt_9)) + (portRef LAT (instanceRef cnt_9)) + (portRef SD (instanceRef cnt_8)) + (portRef LAT (instanceRef cnt_8)) + (portRef SD (instanceRef cnt_7)) + (portRef LAT (instanceRef cnt_7)) + (portRef SD (instanceRef cnt_6)) + (portRef LAT (instanceRef cnt_6)) + (portRef SD (instanceRef cnt_5)) + (portRef LAT (instanceRef cnt_5)) + (portRef SD (instanceRef cnt_4)) + (portRef LAT (instanceRef cnt_4)) + (portRef SD (instanceRef cnt_3)) + (portRef LAT (instanceRef cnt_3)) + (portRef SD (instanceRef cnt_2)) + (portRef LAT (instanceRef cnt_2)) + (portRef SD (instanceRef cnt_1)) + (portRef LAT (instanceRef cnt_1)) + (portRef SD (instanceRef cnt_0)) + (portRef LAT (instanceRef cnt_0)) + (portRef SD (instanceRef tmp_clk)) + (portRef LAT (instanceRef tmp_clk)) + )) + (net (rename cntZ0Z_0 "cnt[0]") (joined + (portRef Q (instanceRef cnt_0)) + (portRef C (instanceRef cnt_RNIP91P5_0)) + )) + (net (rename cnt_s_0 "cnt_s[0]") (joined + (portRef S (instanceRef cnt_RNIP91P5_0)) + (portRef D (instanceRef cnt_0)) + )) + (net (rename cntZ0Z_1 "cnt[1]") (joined + (portRef Q (instanceRef cnt_1)) + (portRef C (instanceRef cnt_RNI5IPL8_1)) + )) + (net (rename cnt_s_1 "cnt_s[1]") (joined + (portRef S (instanceRef cnt_RNI5IPL8_1)) + (portRef D (instanceRef cnt_1)) + )) + (net (rename cntZ0Z_2 "cnt[2]") (joined + (portRef Q (instanceRef cnt_2)) + (portRef C (instanceRef cnt_RNIIRHIB_2)) + )) + (net (rename cnt_s_2 "cnt_s[2]") (joined + (portRef S (instanceRef cnt_RNIIRHIB_2)) + (portRef D (instanceRef cnt_2)) + )) + (net (rename cntZ0Z_3 "cnt[3]") (joined + (portRef Q (instanceRef cnt_3)) + (portRef C (instanceRef cnt_RNI06AFE_3)) + )) + (net (rename cnt_s_3 "cnt_s[3]") (joined + (portRef S (instanceRef cnt_RNI06AFE_3)) + (portRef D (instanceRef cnt_3)) + )) + (net (rename cntZ0Z_4 "cnt[4]") (joined + (portRef Q (instanceRef cnt_4)) + (portRef C (instanceRef cnt_RNIFH2CH_4)) + )) + (net (rename cnt_s_4 "cnt_s[4]") (joined + (portRef S (instanceRef cnt_RNIFH2CH_4)) + (portRef D (instanceRef cnt_4)) + )) + (net (rename cntZ0Z_5 "cnt[5]") (joined + (portRef Q (instanceRef cnt_5)) + (portRef C (instanceRef cnt_RNIVTQ8K_5)) + )) + (net (rename cnt_s_5 "cnt_s[5]") (joined + (portRef S (instanceRef cnt_RNIVTQ8K_5)) + (portRef D (instanceRef cnt_5)) + )) + (net (rename cntZ0Z_6 "cnt[6]") (joined + (portRef Q (instanceRef cnt_6)) + (portRef B (instanceRef un7_cntlto31_0_a2_1)) + (portRef C (instanceRef cnt_RNIGBJ5N_6)) + )) + (net (rename cnt_s_6 "cnt_s[6]") (joined + (portRef S (instanceRef cnt_RNIGBJ5N_6)) + (portRef D (instanceRef cnt_6)) + )) + (net (rename cntZ0Z_7 "cnt[7]") (joined + (portRef Q (instanceRef cnt_7)) + (portRef D (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNI2QB2Q_7)) + )) + (net (rename cnt_s_7 "cnt_s[7]") (joined + (portRef S (instanceRef cnt_RNI2QB2Q_7)) + (portRef D (instanceRef cnt_7)) + )) + (net (rename cntZ0Z_8 "cnt[8]") (joined + (portRef Q (instanceRef cnt_8)) + (portRef C (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNIL94VS_8)) + )) + (net (rename cnt_s_8 "cnt_s[8]") (joined + (portRef S (instanceRef cnt_RNIL94VS_8)) + (portRef D (instanceRef cnt_8)) + )) + (net (rename cntZ0Z_9 "cnt[9]") (joined + (portRef Q (instanceRef cnt_9)) + (portRef B (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNI9QSRV_9)) + )) + (net (rename cnt_s_9 "cnt_s[9]") (joined + (portRef S (instanceRef cnt_RNI9QSRV_9)) + (portRef D (instanceRef cnt_9)) + )) + (net (rename cntZ0Z_10 "cnt[10]") (joined + (portRef Q (instanceRef cnt_10)) + (portRef A (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNI5LP731_10)) + )) + (net (rename cnt_s_10 "cnt_s[10]") (joined + (portRef S (instanceRef cnt_RNI5LP731_10)) + (portRef D (instanceRef cnt_10)) + )) + (net (rename cntZ0Z_11 "cnt[11]") (joined + (portRef Q (instanceRef cnt_11)) + (portRef B (instanceRef un7_cntlto31_0_a2_0)) + (portRef B (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef cnt_RNI2HMJ61_11)) + )) + (net (rename cnt_s_11 "cnt_s[11]") (joined + (portRef S (instanceRef cnt_RNI2HMJ61_11)) + (portRef D (instanceRef cnt_11)) + )) + (net (rename cntZ0Z_12 "cnt[12]") (joined + (portRef Q (instanceRef cnt_12)) + (portRef C (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNI0EJV91_12)) + )) + (net (rename cnt_s_12 "cnt_s[12]") (joined + (portRef S (instanceRef cnt_RNI0EJV91_12)) + (portRef D (instanceRef cnt_12)) + )) + (net (rename cntZ0Z_13 "cnt[13]") (joined + (portRef Q (instanceRef cnt_13)) + (portRef B (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNIVBGBD1_13)) + )) + (net (rename cnt_s_13 "cnt_s[13]") (joined + (portRef S (instanceRef cnt_RNIVBGBD1_13)) + (portRef D (instanceRef cnt_13)) + )) + (net (rename cntZ0Z_14 "cnt[14]") (joined + (portRef Q (instanceRef cnt_14)) + (portRef A (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNIVADNG1_14)) + )) + (net (rename cnt_s_14 "cnt_s[14]") (joined + (portRef S (instanceRef cnt_RNIVADNG1_14)) + (portRef D (instanceRef cnt_14)) + )) + (net (rename cntZ0Z_15 "cnt[15]") (joined + (portRef Q (instanceRef cnt_15)) + (portRef A (instanceRef un7_cntlto31_0_a2_0)) + (portRef A (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef cnt_RNI0BA3K1_15)) + )) + (net (rename cnt_s_15 "cnt_s[15]") (joined + (portRef S (instanceRef cnt_RNI0BA3K1_15)) + (portRef D (instanceRef cnt_15)) + )) + (net (rename cntZ0Z_16 "cnt[16]") (joined + (portRef Q (instanceRef cnt_16)) + (portRef A (instanceRef un7_cntlto31_0_a2)) + (portRef A (instanceRef un14_cntlto31_0_o3_0_RNIA4EM1)) + (portRef C (instanceRef cnt_RNI2C7FN1_16)) + )) + (net (rename cnt_s_16 "cnt_s[16]") (joined + (portRef S (instanceRef cnt_RNI2C7FN1_16)) + (portRef D (instanceRef cnt_16)) + )) + (net (rename cntZ0Z_17 "cnt[17]") (joined + (portRef Q (instanceRef cnt_17)) + (portRef B (instanceRef un7_cntlto31_0_a2)) + (portRef B (instanceRef un14_cntlto31_0_o3_0_RNIA4EM1)) + (portRef C (instanceRef cnt_RNI5E4RQ1_17)) + )) + (net (rename cnt_s_17 "cnt_s[17]") (joined + (portRef S (instanceRef cnt_RNI5E4RQ1_17)) + (portRef D (instanceRef cnt_17)) + )) + (net (rename cntZ0Z_18 "cnt[18]") (joined + (portRef Q (instanceRef cnt_18)) + (portRef C (instanceRef un14_cntlto31_0_a2)) + (portRef C (instanceRef cnt_RNI9H17U1_18)) + )) + (net (rename cnt_s_18 "cnt_s[18]") (joined + (portRef S (instanceRef cnt_RNI9H17U1_18)) + (portRef D (instanceRef cnt_18)) + )) + (net (rename cntZ0Z_19 "cnt[19]") (joined + (portRef Q (instanceRef cnt_19)) + (portRef D (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNIELUI12_19)) + )) + (net (rename cnt_s_19 "cnt_s[19]") (joined + (portRef S (instanceRef cnt_RNIELUI12_19)) + (portRef D (instanceRef cnt_19)) + )) + (net (rename cntZ0Z_20 "cnt[20]") (joined + (portRef Q (instanceRef cnt_20)) + (portRef C (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNIBISU42_20)) + )) + (net (rename cnt_s_20 "cnt_s[20]") (joined + (portRef S (instanceRef cnt_RNIBISU42_20)) + (portRef D (instanceRef cnt_20)) + )) + (net (rename cntZ0Z_21 "cnt[21]") (joined + (portRef Q (instanceRef cnt_21)) + (portRef B (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNI9GQA82_21)) + )) + (net (rename cnt_s_21 "cnt_s[21]") (joined + (portRef S (instanceRef cnt_RNI9GQA82_21)) + (portRef D (instanceRef cnt_21)) + )) + (net (rename cntZ0Z_22 "cnt[22]") (joined + (portRef Q (instanceRef cnt_22)) + (portRef A (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNI8FOMB2_22)) + )) + (net (rename cnt_s_22 "cnt_s[22]") (joined + (portRef S (instanceRef cnt_RNI8FOMB2_22)) + (portRef D (instanceRef cnt_22)) + )) + (net (rename cntZ0Z_23 "cnt[23]") (joined + (portRef Q (instanceRef cnt_23)) + (portRef B (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef un7_cntlto31_0_a2)) + (portRef A (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNI8FM2F2_23)) + )) + (net (rename cnt_s_23 "cnt_s[23]") (joined + (portRef S (instanceRef cnt_RNI8FM2F2_23)) + (portRef D (instanceRef cnt_23)) + )) + (net (rename cntZ0Z_24 "cnt[24]") (joined + (portRef Q (instanceRef cnt_24)) + (portRef A (instanceRef un7_cntlto31_0_a3)) + (portRef D (instanceRef un14_cntlto31_0_o3_0_RNIA4EM1)) + (portRef D (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNI9GKEI2_24)) + )) + (net (rename cnt_s_24 "cnt_s[24]") (joined + (portRef S (instanceRef cnt_RNI9GKEI2_24)) + (portRef D (instanceRef cnt_24)) + )) + (net (rename cntZ0Z_25 "cnt[25]") (joined + (portRef Q (instanceRef cnt_25)) + (portRef A (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef un7_cntlto31_0_a3)) + (portRef C (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNIBIIQL2_25)) + )) + (net (rename cnt_s_25 "cnt_s[25]") (joined + (portRef S (instanceRef cnt_RNIBIIQL2_25)) + (portRef D (instanceRef cnt_25)) + )) + (net (rename cntZ0Z_26 "cnt[26]") (joined + (portRef Q (instanceRef cnt_26)) + (portRef C (instanceRef un7_cntlto31_0_a3)) + (portRef A (instanceRef un14_cntlto31_0_a2)) + (portRef B (instanceRef un14_cntlto31_0_o3_RNIE29S2)) + )) + (net (rename cnt_s_26 "cnt_s[26]") (joined + (portRef FCO (instanceRef cnt_RNIBIIQL2_25)) + (portRef D (instanceRef cnt_26)) + )) + (net cnt_cry_cy (joined + (portRef FCO (instanceRef un14_cntlto31_0_o3_RNIE29S2)) + (portRef FCI (instanceRef cnt_RNIP91P5_0)) + )) + (net un14_cntlto31_0_o3_RNIE29S2_Y (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_RNIE29S2)) + (portRef B (instanceRef cnt_RNIBIIQL2_25)) + (portRef B (instanceRef cnt_RNI9GKEI2_24)) + (portRef B (instanceRef cnt_RNI8FM2F2_23)) + (portRef B (instanceRef cnt_RNI8FOMB2_22)) + (portRef B (instanceRef cnt_RNI9GQA82_21)) + (portRef B (instanceRef cnt_RNIBISU42_20)) + (portRef B (instanceRef cnt_RNIELUI12_19)) + (portRef B (instanceRef cnt_RNI9H17U1_18)) + (portRef B (instanceRef cnt_RNI5E4RQ1_17)) + (portRef B (instanceRef cnt_RNI2C7FN1_16)) + (portRef B (instanceRef cnt_RNI0BA3K1_15)) + (portRef B (instanceRef cnt_RNIVADNG1_14)) + (portRef B (instanceRef cnt_RNIVBGBD1_13)) + (portRef B (instanceRef cnt_RNI0EJV91_12)) + (portRef B (instanceRef cnt_RNI2HMJ61_11)) + (portRef B (instanceRef cnt_RNI5LP731_10)) + (portRef B (instanceRef cnt_RNI9QSRV_9)) + (portRef B (instanceRef cnt_RNIL94VS_8)) + (portRef B (instanceRef cnt_RNI2QB2Q_7)) + (portRef B (instanceRef cnt_RNIGBJ5N_6)) + (portRef B (instanceRef cnt_RNIVTQ8K_5)) + (portRef B (instanceRef cnt_RNIFH2CH_4)) + (portRef B (instanceRef cnt_RNI06AFE_3)) + (portRef B (instanceRef cnt_RNIIRHIB_2)) + (portRef B (instanceRef cnt_RNI5IPL8_1)) + (portRef B (instanceRef cnt_RNIP91P5_0)) + )) + (net N_314_tz (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_0_RNIA4EM1)) + (portRef A (instanceRef un14_cntlto31_0_o3_RNIE29S2)) + )) + (net (rename un14_cntlto31_0_oZ0Z3 "un14_cntlto31_0_o3") (joined + (portRef Y (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef un14_cntlto31_0_o3_RNIE29S2)) + )) + (net (rename un14_cntlto31_0_aZ0Z2 "un14_cntlto31_0_a2") (joined + (portRef Y (instanceRef un14_cntlto31_0_a2)) + (portRef C (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef un14_cntlto31_0_o3_RNIE29S2)) + )) + (net (rename cnt_cry_0 "cnt_cry[0]") (joined + (portRef FCO (instanceRef cnt_RNIP91P5_0)) + (portRef FCI (instanceRef cnt_RNI5IPL8_1)) + )) + (net (rename cnt_cry_1 "cnt_cry[1]") (joined + (portRef FCO (instanceRef cnt_RNI5IPL8_1)) + (portRef FCI (instanceRef cnt_RNIIRHIB_2)) + )) + (net (rename cnt_cry_2 "cnt_cry[2]") (joined + (portRef FCO (instanceRef cnt_RNIIRHIB_2)) + (portRef FCI (instanceRef cnt_RNI06AFE_3)) + )) + (net (rename cnt_cry_3 "cnt_cry[3]") (joined + (portRef FCO (instanceRef cnt_RNI06AFE_3)) + (portRef FCI (instanceRef cnt_RNIFH2CH_4)) + )) + (net (rename cnt_cry_4 "cnt_cry[4]") (joined + (portRef FCO (instanceRef cnt_RNIFH2CH_4)) + (portRef FCI (instanceRef cnt_RNIVTQ8K_5)) + )) + (net (rename cnt_cry_5 "cnt_cry[5]") (joined + (portRef FCO (instanceRef cnt_RNIVTQ8K_5)) + (portRef FCI (instanceRef cnt_RNIGBJ5N_6)) + )) + (net (rename cnt_cry_6 "cnt_cry[6]") (joined + (portRef FCO (instanceRef cnt_RNIGBJ5N_6)) + (portRef FCI (instanceRef cnt_RNI2QB2Q_7)) + )) + (net (rename cnt_cry_7 "cnt_cry[7]") (joined + (portRef FCO (instanceRef cnt_RNI2QB2Q_7)) + (portRef FCI (instanceRef cnt_RNIL94VS_8)) + )) + (net (rename cnt_cry_8 "cnt_cry[8]") (joined + (portRef FCO (instanceRef cnt_RNIL94VS_8)) + (portRef FCI (instanceRef cnt_RNI9QSRV_9)) + )) + (net (rename cnt_cry_9 "cnt_cry[9]") (joined + (portRef FCO (instanceRef cnt_RNI9QSRV_9)) + (portRef FCI (instanceRef cnt_RNI5LP731_10)) + )) + (net (rename cnt_cry_10 "cnt_cry[10]") (joined + (portRef FCO (instanceRef cnt_RNI5LP731_10)) + (portRef FCI (instanceRef cnt_RNI2HMJ61_11)) + )) + (net (rename cnt_cry_11 "cnt_cry[11]") (joined + (portRef FCO (instanceRef cnt_RNI2HMJ61_11)) + (portRef FCI (instanceRef cnt_RNI0EJV91_12)) + )) + (net (rename cnt_cry_12 "cnt_cry[12]") (joined + (portRef FCO (instanceRef cnt_RNI0EJV91_12)) + (portRef FCI (instanceRef cnt_RNIVBGBD1_13)) + )) + (net (rename cnt_cry_13 "cnt_cry[13]") (joined + (portRef FCO (instanceRef cnt_RNIVBGBD1_13)) + (portRef FCI (instanceRef cnt_RNIVADNG1_14)) + )) + (net (rename cnt_cry_14 "cnt_cry[14]") (joined + (portRef FCO (instanceRef cnt_RNIVADNG1_14)) + (portRef FCI (instanceRef cnt_RNI0BA3K1_15)) + )) + (net (rename cnt_cry_15 "cnt_cry[15]") (joined + (portRef FCO (instanceRef cnt_RNI0BA3K1_15)) + (portRef FCI (instanceRef cnt_RNI2C7FN1_16)) + )) + (net (rename cnt_cry_16 "cnt_cry[16]") (joined + (portRef FCO (instanceRef cnt_RNI2C7FN1_16)) + (portRef FCI (instanceRef cnt_RNI5E4RQ1_17)) + )) + (net (rename cnt_cry_17 "cnt_cry[17]") (joined + (portRef FCO (instanceRef cnt_RNI5E4RQ1_17)) + (portRef FCI (instanceRef cnt_RNI9H17U1_18)) + )) + (net (rename cnt_cry_18 "cnt_cry[18]") (joined + (portRef FCO (instanceRef cnt_RNI9H17U1_18)) + (portRef FCI (instanceRef cnt_RNIELUI12_19)) + )) + (net (rename cnt_cry_19 "cnt_cry[19]") (joined + (portRef FCO (instanceRef cnt_RNIELUI12_19)) + (portRef FCI (instanceRef cnt_RNIBISU42_20)) + )) + (net (rename cnt_cry_20 "cnt_cry[20]") (joined + (portRef FCO (instanceRef cnt_RNIBISU42_20)) + (portRef FCI (instanceRef cnt_RNI9GQA82_21)) + )) + (net (rename cnt_cry_21 "cnt_cry[21]") (joined + (portRef FCO (instanceRef cnt_RNI9GQA82_21)) + (portRef FCI (instanceRef cnt_RNI8FOMB2_22)) + )) + (net (rename cnt_cry_22 "cnt_cry[22]") (joined + (portRef FCO (instanceRef cnt_RNI8FOMB2_22)) + (portRef FCI (instanceRef cnt_RNI8FM2F2_23)) + )) + (net (rename cnt_cry_23 "cnt_cry[23]") (joined + (portRef FCO (instanceRef cnt_RNI8FM2F2_23)) + (portRef FCI (instanceRef cnt_RNI9GKEI2_24)) + )) + (net (rename cnt_cry_24 "cnt_cry[24]") (joined + (portRef FCO (instanceRef cnt_RNI9GKEI2_24)) + (portRef FCI (instanceRef cnt_RNIBIIQL2_25)) + )) + (net (rename un14_cntlto31_0_o2Z0Z_3 "un14_cntlto31_0_o2_3") (joined + (portRef Y (instanceRef un14_cntlto31_0_o2_3)) + (portRef B (instanceRef un14_cntlto31_0_o3)) + (portRef B (instanceRef un14_cntlto31_0_a2)) + )) + (net (rename un14_cntlto31_0_o2Z0Z_0 "un14_cntlto31_0_o2_0") (joined + (portRef Y (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef un7_cntlto31_0_a2_0)) + (portRef C (instanceRef un14_cntlto31_0_o3_0)) + )) + (net N_125_3 (joined + (portRef Y (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef D (instanceRef un14_cntlto31_0_o3_0)) + (portRef A (instanceRef un7_cntlto31_0_a2_1)) + )) + (net (rename un7_cntlto31_0_a2Z0Z_1 "un7_cntlto31_0_a2_1") (joined + (portRef Y (instanceRef un7_cntlto31_0_a2_1)) + (portRef D (instanceRef un7_cntlto31_0_a2_0)) + )) + (net (rename un14_cntlto31_0_o3Z0Z_0 "un14_cntlto31_0_o3_0") (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef un14_cntlto31_0_o3_0_RNIA4EM1)) + )) + (net (rename un7_cntlto31_0_a2Z0Z_0 "un7_cntlto31_0_a2_0") (joined + (portRef Y (instanceRef un7_cntlto31_0_a2_0)) + (portRef C (instanceRef un7_cntlto31_0_a2)) + )) + (net (rename un7_cntlto31_0_aZ0Z2 "un7_cntlto31_0_a2") (joined + (portRef Y (instanceRef un7_cntlto31_0_a2)) + (portRef B (instanceRef un7_cntlto31_0_a3)) + )) + (net (rename un7_cntlto31_0_aZ0Z3 "un7_cntlto31_0_a3") (joined + (portRef Y (instanceRef un7_cntlto31_0_a3)) + (portRef D (instanceRef un7_cntlto31_0_0)) + )) + ) + (property orig_inst_of (string "ClkGen")) + ) + ) + (cell ClkGenNoSwitch_1 (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port led1 (direction OUTPUT)) + (port reset (direction INPUT)) + (port clk_c (direction INPUT)) + ) + (contents + (instance tmp_clk (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_0 "cnt[0]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_1 "cnt[1]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_2 "cnt[2]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_3 "cnt[3]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_4 "cnt[4]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_5 "cnt[5]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_6 "cnt[6]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_7 "cnt[7]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_8 "cnt[8]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_9 "cnt[9]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_10 "cnt[10]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_11 "cnt[11]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_12 "cnt[12]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_13 "cnt[13]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_14 "cnt[14]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_15 "cnt[15]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_16 "cnt[16]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_17 "cnt[17]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_18 "cnt[18]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_19 "cnt[19]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_20 "cnt[20]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_21 "cnt[21]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_22 "cnt[22]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_23 "cnt[23]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_24 "cnt[24]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_25 "cnt[25]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_26 "cnt[26]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_27 "cnt[27]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_RNIOCCK2_27 "cnt_RNIOCCK2[27]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "40037")) + ) + (instance (rename cnt_RNITNTM5_0 "cnt_RNITNTM5[0]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI34FP8_1 "cnt_RNI34FP8[1]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIAH0SB_2 "cnt_RNIAH0SB[2]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIIVHUE_3 "cnt_RNIIVHUE[3]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIRE31I_4 "cnt_RNIRE31I[4]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI5VK3L_5 "cnt_RNI5VK3L[5]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIGG66O_6 "cnt_RNIGG66O[6]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIS2O8R_7 "cnt_RNIS2O8R[7]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI9M9BU_8 "cnt_RNI9M9BU[8]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNINARD11_9 "cnt_RNINARD11[9]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIDPA541_10 "cnt_RNIDPA541[10]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI49QS61_11 "cnt_RNI49QS61[11]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNISP9K91_12 "cnt_RNISP9K91[12]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNILBPBC1_13 "cnt_RNILBPBC1[13]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIFU83F1_14 "cnt_RNIFU83F1[14]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIAIOQH1_15 "cnt_RNIAIOQH1[15]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI678IK1_16 "cnt_RNI678IK1[16]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI3TN9N1_17 "cnt_RNI3TN9N1[17]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI1K71Q1_18 "cnt_RNI1K71Q1[18]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI0CNOS1_19 "cnt_RNI0CNOS1[19]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNINS7GV1_20 "cnt_RNINS7GV1[20]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIFEO722_21 "cnt_RNIFEO722[21]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI819V42_22 "cnt_RNI819V42[22]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI2LPM72_23 "cnt_RNI2LPM72[23]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIT9AEA2_24 "cnt_RNIT9AEA2[24]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIPVQ5D2_25 "cnt_RNIPVQ5D2[25]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIMMBTF2_26 "cnt_RNIMMBTF2[26]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance tmp_clk_RNO_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "3331")) + ) + (instance tmp_clk_RNO_2 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "7FFF")) + ) + (instance (rename cnt_RNI4JC9_21 "cnt_RNI4JC9[21]") (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "80")) + ) + (instance tmp_clk_RNO_4 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "8000")) + ) + (instance (rename cnt_RNIAQCC_13 "cnt_RNIAQCC[13]") (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "8000")) + ) + (instance (rename cnt_RNI8JG21_10 "cnt_RNI8JG21[10]") (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0001")) + ) + (instance tmp_clk_RNO_3 (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "8C")) + ) + (instance (rename cnt_RNIIH0I1_12 "cnt_RNIIH0I1[12]") (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "8C")) + ) + (instance (rename cnt_RNI4GAR1_17 "cnt_RNI4GAR1[17]") (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "010F")) + ) + (instance tmp_clk_RNO_1 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "010F")) + ) + (instance (rename cnt_RNI9EVA2_20 "cnt_RNI9EVA2[20]") (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0800")) + ) + (instance tmp_clk_RNO (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "000D")) + ) + (instance GND (viewRef PRIM (cellRef GND (libraryRef ACG4))) ) + (instance VCC (viewRef PRIM (cellRef VCC (libraryRef ACG4))) ) + (net led1 (joined + (portRef Q (instanceRef tmp_clk)) + (portRef led1) + )) + (net (rename VCCZ0 "VCC") (joined + (portRef Y (instanceRef VCC)) + (portRef A (instanceRef cnt_RNIMMBTF2_26)) + (portRef A (instanceRef cnt_RNIPVQ5D2_25)) + (portRef A (instanceRef cnt_RNIT9AEA2_24)) + (portRef A (instanceRef cnt_RNI2LPM72_23)) + (portRef A (instanceRef cnt_RNI819V42_22)) + (portRef A (instanceRef cnt_RNIFEO722_21)) + (portRef A (instanceRef cnt_RNINS7GV1_20)) + (portRef A (instanceRef cnt_RNI0CNOS1_19)) + (portRef A (instanceRef cnt_RNI1K71Q1_18)) + (portRef A (instanceRef cnt_RNI3TN9N1_17)) + (portRef A (instanceRef cnt_RNI678IK1_16)) + (portRef A (instanceRef cnt_RNIAIOQH1_15)) + (portRef A (instanceRef cnt_RNIFU83F1_14)) + (portRef A (instanceRef cnt_RNILBPBC1_13)) + (portRef A (instanceRef cnt_RNISP9K91_12)) + (portRef A (instanceRef cnt_RNI49QS61_11)) + (portRef A (instanceRef cnt_RNIDPA541_10)) + (portRef A (instanceRef cnt_RNINARD11_9)) + (portRef A (instanceRef cnt_RNI9M9BU_8)) + (portRef A (instanceRef cnt_RNIS2O8R_7)) + (portRef A (instanceRef cnt_RNIGG66O_6)) + (portRef A (instanceRef cnt_RNI5VK3L_5)) + (portRef A (instanceRef cnt_RNIRE31I_4)) + (portRef A (instanceRef cnt_RNIIVHUE_3)) + (portRef A (instanceRef cnt_RNIAH0SB_2)) + (portRef A (instanceRef cnt_RNI34FP8_1)) + (portRef A (instanceRef cnt_RNITNTM5_0)) + (portRef FCI (instanceRef cnt_RNIOCCK2_27)) + (portRef SLn (instanceRef cnt_27)) + (portRef EN (instanceRef cnt_27)) + (portRef ADn (instanceRef cnt_27)) + (portRef SLn (instanceRef cnt_26)) + (portRef EN (instanceRef cnt_26)) + (portRef ADn (instanceRef cnt_26)) + (portRef SLn (instanceRef cnt_25)) + (portRef EN (instanceRef cnt_25)) + (portRef ADn (instanceRef cnt_25)) + (portRef SLn (instanceRef cnt_24)) + (portRef EN (instanceRef cnt_24)) + (portRef ADn (instanceRef cnt_24)) + (portRef SLn (instanceRef cnt_23)) + (portRef EN (instanceRef cnt_23)) + (portRef ADn (instanceRef cnt_23)) + (portRef SLn (instanceRef cnt_22)) + (portRef EN (instanceRef cnt_22)) + (portRef ADn (instanceRef cnt_22)) + (portRef SLn (instanceRef cnt_21)) + (portRef EN (instanceRef cnt_21)) + (portRef ADn (instanceRef cnt_21)) + (portRef SLn (instanceRef cnt_20)) + (portRef EN (instanceRef cnt_20)) + (portRef ADn (instanceRef cnt_20)) + (portRef SLn (instanceRef cnt_19)) + (portRef EN (instanceRef cnt_19)) + (portRef ADn (instanceRef cnt_19)) + (portRef SLn (instanceRef cnt_18)) + (portRef EN (instanceRef cnt_18)) + (portRef ADn (instanceRef cnt_18)) + (portRef SLn (instanceRef cnt_17)) + (portRef EN (instanceRef cnt_17)) + (portRef ADn (instanceRef cnt_17)) + (portRef SLn (instanceRef cnt_16)) + (portRef EN (instanceRef cnt_16)) + (portRef ADn (instanceRef cnt_16)) + (portRef SLn (instanceRef cnt_15)) + (portRef EN (instanceRef cnt_15)) + (portRef ADn (instanceRef cnt_15)) + (portRef SLn (instanceRef cnt_14)) + (portRef EN (instanceRef cnt_14)) + (portRef ADn (instanceRef cnt_14)) + (portRef SLn (instanceRef cnt_13)) + (portRef EN (instanceRef cnt_13)) + (portRef ADn (instanceRef cnt_13)) + (portRef SLn (instanceRef cnt_12)) + (portRef EN (instanceRef cnt_12)) + (portRef ADn (instanceRef cnt_12)) + (portRef SLn (instanceRef cnt_11)) + (portRef EN (instanceRef cnt_11)) + (portRef ADn (instanceRef cnt_11)) + (portRef SLn (instanceRef cnt_10)) + (portRef EN (instanceRef cnt_10)) + (portRef ADn (instanceRef cnt_10)) + (portRef SLn (instanceRef cnt_9)) + (portRef EN (instanceRef cnt_9)) + (portRef ADn (instanceRef cnt_9)) + (portRef SLn (instanceRef cnt_8)) + (portRef EN (instanceRef cnt_8)) + (portRef ADn (instanceRef cnt_8)) + (portRef SLn (instanceRef cnt_7)) + (portRef EN (instanceRef cnt_7)) + (portRef ADn (instanceRef cnt_7)) + (portRef SLn (instanceRef cnt_6)) + (portRef EN (instanceRef cnt_6)) + (portRef ADn (instanceRef cnt_6)) + (portRef SLn (instanceRef cnt_5)) + (portRef EN (instanceRef cnt_5)) + (portRef ADn (instanceRef cnt_5)) + (portRef SLn (instanceRef cnt_4)) + (portRef EN (instanceRef cnt_4)) + (portRef ADn (instanceRef cnt_4)) + (portRef SLn (instanceRef cnt_3)) + (portRef EN (instanceRef cnt_3)) + (portRef ADn (instanceRef cnt_3)) + (portRef SLn (instanceRef cnt_2)) + (portRef EN (instanceRef cnt_2)) + (portRef ADn (instanceRef cnt_2)) + (portRef SLn (instanceRef cnt_1)) + (portRef EN (instanceRef cnt_1)) + (portRef ADn (instanceRef cnt_1)) + (portRef SLn (instanceRef cnt_0)) + (portRef EN (instanceRef cnt_0)) + (portRef ADn (instanceRef cnt_0)) + (portRef SLn (instanceRef tmp_clk)) + (portRef EN (instanceRef tmp_clk)) + (portRef ADn (instanceRef tmp_clk)) + )) + (net reset (joined + (portRef reset) + (portRef ALn (instanceRef cnt_27)) + (portRef ALn (instanceRef cnt_26)) + (portRef ALn (instanceRef cnt_25)) + (portRef ALn (instanceRef cnt_24)) + (portRef ALn (instanceRef cnt_23)) + (portRef ALn (instanceRef cnt_22)) + (portRef ALn (instanceRef cnt_21)) + (portRef ALn (instanceRef cnt_20)) + (portRef ALn (instanceRef cnt_19)) + (portRef ALn (instanceRef cnt_18)) + (portRef ALn (instanceRef cnt_17)) + (portRef ALn (instanceRef cnt_16)) + (portRef ALn (instanceRef cnt_15)) + (portRef ALn (instanceRef cnt_14)) + (portRef ALn (instanceRef cnt_13)) + (portRef ALn (instanceRef cnt_12)) + (portRef ALn (instanceRef cnt_11)) + (portRef ALn (instanceRef cnt_10)) + (portRef ALn (instanceRef cnt_9)) + (portRef ALn (instanceRef cnt_8)) + (portRef ALn (instanceRef cnt_7)) + (portRef ALn (instanceRef cnt_6)) + (portRef ALn (instanceRef cnt_5)) + (portRef ALn (instanceRef cnt_4)) + (portRef ALn (instanceRef cnt_3)) + (portRef ALn (instanceRef cnt_2)) + (portRef ALn (instanceRef cnt_1)) + (portRef ALn (instanceRef cnt_0)) + (portRef ALn (instanceRef tmp_clk)) + )) + (net clk_c (joined + (portRef clk_c) + (portRef CLK (instanceRef cnt_27)) + (portRef CLK (instanceRef cnt_26)) + (portRef CLK (instanceRef cnt_25)) + (portRef CLK (instanceRef cnt_24)) + (portRef CLK (instanceRef cnt_23)) + (portRef CLK (instanceRef cnt_22)) + (portRef CLK (instanceRef cnt_21)) + (portRef CLK (instanceRef cnt_20)) + (portRef CLK (instanceRef cnt_19)) + (portRef CLK (instanceRef cnt_18)) + (portRef CLK (instanceRef cnt_17)) + (portRef CLK (instanceRef cnt_16)) + (portRef CLK (instanceRef cnt_15)) + (portRef CLK (instanceRef cnt_14)) + (portRef CLK (instanceRef cnt_13)) + (portRef CLK (instanceRef cnt_12)) + (portRef CLK (instanceRef cnt_11)) + (portRef CLK (instanceRef cnt_10)) + (portRef CLK (instanceRef cnt_9)) + (portRef CLK (instanceRef cnt_8)) + (portRef CLK (instanceRef cnt_7)) + (portRef CLK (instanceRef cnt_6)) + (portRef CLK (instanceRef cnt_5)) + (portRef CLK (instanceRef cnt_4)) + (portRef CLK (instanceRef cnt_3)) + (portRef CLK (instanceRef cnt_2)) + (portRef CLK (instanceRef cnt_1)) + (portRef CLK (instanceRef cnt_0)) + (portRef CLK (instanceRef tmp_clk)) + )) + (net (rename tmp_clk_RNOZ0 "tmp_clk_RNO") (joined + (portRef Y (instanceRef tmp_clk_RNO)) + (portRef D (instanceRef tmp_clk)) + )) + (net (rename GNDZ0 "GND") (joined + (portRef Y (instanceRef GND)) + (portRef D (instanceRef cnt_RNIMMBTF2_26)) + (portRef D (instanceRef cnt_RNIPVQ5D2_25)) + (portRef D (instanceRef cnt_RNIT9AEA2_24)) + (portRef D (instanceRef cnt_RNI2LPM72_23)) + (portRef D (instanceRef cnt_RNI819V42_22)) + (portRef D (instanceRef cnt_RNIFEO722_21)) + (portRef D (instanceRef cnt_RNINS7GV1_20)) + (portRef D (instanceRef cnt_RNI0CNOS1_19)) + (portRef D (instanceRef cnt_RNI1K71Q1_18)) + (portRef D (instanceRef cnt_RNI3TN9N1_17)) + (portRef D (instanceRef cnt_RNI678IK1_16)) + (portRef D (instanceRef cnt_RNIAIOQH1_15)) + (portRef D (instanceRef cnt_RNIFU83F1_14)) + (portRef D (instanceRef cnt_RNILBPBC1_13)) + (portRef D (instanceRef cnt_RNISP9K91_12)) + (portRef D (instanceRef cnt_RNI49QS61_11)) + (portRef D (instanceRef cnt_RNIDPA541_10)) + (portRef D (instanceRef cnt_RNINARD11_9)) + (portRef D (instanceRef cnt_RNI9M9BU_8)) + (portRef D (instanceRef cnt_RNIS2O8R_7)) + (portRef D (instanceRef cnt_RNIGG66O_6)) + (portRef D (instanceRef cnt_RNI5VK3L_5)) + (portRef D (instanceRef cnt_RNIRE31I_4)) + (portRef D (instanceRef cnt_RNIIVHUE_3)) + (portRef D (instanceRef cnt_RNIAH0SB_2)) + (portRef D (instanceRef cnt_RNI34FP8_1)) + (portRef D (instanceRef cnt_RNITNTM5_0)) + (portRef SD (instanceRef cnt_27)) + (portRef LAT (instanceRef cnt_27)) + (portRef SD (instanceRef cnt_26)) + (portRef LAT (instanceRef cnt_26)) + (portRef SD (instanceRef cnt_25)) + (portRef LAT (instanceRef cnt_25)) + (portRef SD (instanceRef cnt_24)) + (portRef LAT (instanceRef cnt_24)) + (portRef SD (instanceRef cnt_23)) + (portRef LAT (instanceRef cnt_23)) + (portRef SD (instanceRef cnt_22)) + (portRef LAT (instanceRef cnt_22)) + (portRef SD (instanceRef cnt_21)) + (portRef LAT (instanceRef cnt_21)) + (portRef SD (instanceRef cnt_20)) + (portRef LAT (instanceRef cnt_20)) + (portRef SD (instanceRef cnt_19)) + (portRef LAT (instanceRef cnt_19)) + (portRef SD (instanceRef cnt_18)) + (portRef LAT (instanceRef cnt_18)) + (portRef SD (instanceRef cnt_17)) + (portRef LAT (instanceRef cnt_17)) + (portRef SD (instanceRef cnt_16)) + (portRef LAT (instanceRef cnt_16)) + (portRef SD (instanceRef cnt_15)) + (portRef LAT (instanceRef cnt_15)) + (portRef SD (instanceRef cnt_14)) + (portRef LAT (instanceRef cnt_14)) + (portRef SD (instanceRef cnt_13)) + (portRef LAT (instanceRef cnt_13)) + (portRef SD (instanceRef cnt_12)) + (portRef LAT (instanceRef cnt_12)) + (portRef SD (instanceRef cnt_11)) + (portRef LAT (instanceRef cnt_11)) + (portRef SD (instanceRef cnt_10)) + (portRef LAT (instanceRef cnt_10)) + (portRef SD (instanceRef cnt_9)) + (portRef LAT (instanceRef cnt_9)) + (portRef SD (instanceRef cnt_8)) + (portRef LAT (instanceRef cnt_8)) + (portRef SD (instanceRef cnt_7)) + (portRef LAT (instanceRef cnt_7)) + (portRef SD (instanceRef cnt_6)) + (portRef LAT (instanceRef cnt_6)) + (portRef SD (instanceRef cnt_5)) + (portRef LAT (instanceRef cnt_5)) + (portRef SD (instanceRef cnt_4)) + (portRef LAT (instanceRef cnt_4)) + (portRef SD (instanceRef cnt_3)) + (portRef LAT (instanceRef cnt_3)) + (portRef SD (instanceRef cnt_2)) + (portRef LAT (instanceRef cnt_2)) + (portRef SD (instanceRef cnt_1)) + (portRef LAT (instanceRef cnt_1)) + (portRef SD (instanceRef cnt_0)) + (portRef LAT (instanceRef cnt_0)) + (portRef SD (instanceRef tmp_clk)) + (portRef LAT (instanceRef tmp_clk)) + )) + (net (rename cntZ0Z_0 "cnt[0]") (joined + (portRef Q (instanceRef cnt_0)) + (portRef C (instanceRef cnt_RNITNTM5_0)) + )) + (net (rename cnt_s_0 "cnt_s[0]") (joined + (portRef S (instanceRef cnt_RNITNTM5_0)) + (portRef D (instanceRef cnt_0)) + )) + (net (rename cntZ0Z_1 "cnt[1]") (joined + (portRef Q (instanceRef cnt_1)) + (portRef C (instanceRef cnt_RNI34FP8_1)) + )) + (net (rename cnt_s_1 "cnt_s[1]") (joined + (portRef S (instanceRef cnt_RNI34FP8_1)) + (portRef D (instanceRef cnt_1)) + )) + (net (rename cntZ0Z_2 "cnt[2]") (joined + (portRef Q (instanceRef cnt_2)) + (portRef C (instanceRef cnt_RNIAH0SB_2)) + )) + (net (rename cnt_s_2 "cnt_s[2]") (joined + (portRef S (instanceRef cnt_RNIAH0SB_2)) + (portRef D (instanceRef cnt_2)) + )) + (net (rename cntZ0Z_3 "cnt[3]") (joined + (portRef Q (instanceRef cnt_3)) + (portRef C (instanceRef cnt_RNIIVHUE_3)) + )) + (net (rename cnt_s_3 "cnt_s[3]") (joined + (portRef S (instanceRef cnt_RNIIVHUE_3)) + (portRef D (instanceRef cnt_3)) + )) + (net (rename cntZ0Z_4 "cnt[4]") (joined + (portRef Q (instanceRef cnt_4)) + (portRef C (instanceRef cnt_RNIRE31I_4)) + )) + (net (rename cnt_s_4 "cnt_s[4]") (joined + (portRef S (instanceRef cnt_RNIRE31I_4)) + (portRef D (instanceRef cnt_4)) + )) + (net (rename cntZ0Z_5 "cnt[5]") (joined + (portRef Q (instanceRef cnt_5)) + (portRef C (instanceRef cnt_RNI5VK3L_5)) + )) + (net (rename cnt_s_5 "cnt_s[5]") (joined + (portRef S (instanceRef cnt_RNI5VK3L_5)) + (portRef D (instanceRef cnt_5)) + )) + (net (rename cntZ0Z_6 "cnt[6]") (joined + (portRef Q (instanceRef cnt_6)) + (portRef C (instanceRef cnt_RNIGG66O_6)) + )) + (net (rename cnt_s_6 "cnt_s[6]") (joined + (portRef S (instanceRef cnt_RNIGG66O_6)) + (portRef D (instanceRef cnt_6)) + )) + (net (rename cntZ0Z_7 "cnt[7]") (joined + (portRef Q (instanceRef cnt_7)) + (portRef A (instanceRef tmp_clk_RNO_3)) + (portRef C (instanceRef cnt_RNIS2O8R_7)) + )) + (net (rename cnt_s_7 "cnt_s[7]") (joined + (portRef S (instanceRef cnt_RNIS2O8R_7)) + (portRef D (instanceRef cnt_7)) + )) + (net (rename cntZ0Z_8 "cnt[8]") (joined + (portRef Q (instanceRef cnt_8)) + (portRef D (instanceRef cnt_RNI8JG21_10)) + (portRef C (instanceRef cnt_RNI9M9BU_8)) + )) + (net (rename cnt_s_8 "cnt_s[8]") (joined + (portRef S (instanceRef cnt_RNI9M9BU_8)) + (portRef D (instanceRef cnt_8)) + )) + (net (rename cntZ0Z_9 "cnt[9]") (joined + (portRef Q (instanceRef cnt_9)) + (portRef C (instanceRef cnt_RNI8JG21_10)) + (portRef C (instanceRef cnt_RNINARD11_9)) + )) + (net (rename cnt_s_9 "cnt_s[9]") (joined + (portRef S (instanceRef cnt_RNINARD11_9)) + (portRef D (instanceRef cnt_9)) + )) + (net (rename cntZ0Z_10 "cnt[10]") (joined + (portRef Q (instanceRef cnt_10)) + (portRef B (instanceRef cnt_RNI8JG21_10)) + (portRef C (instanceRef cnt_RNIDPA541_10)) + )) + (net (rename cnt_s_10 "cnt_s[10]") (joined + (portRef S (instanceRef cnt_RNIDPA541_10)) + (portRef D (instanceRef cnt_10)) + )) + (net (rename cntZ0Z_11 "cnt[11]") (joined + (portRef Q (instanceRef cnt_11)) + (portRef A (instanceRef cnt_RNI8JG21_10)) + (portRef C (instanceRef cnt_RNI49QS61_11)) + )) + (net (rename cnt_s_11 "cnt_s[11]") (joined + (portRef S (instanceRef cnt_RNI49QS61_11)) + (portRef D (instanceRef cnt_11)) + )) + (net (rename cntZ0Z_12 "cnt[12]") (joined + (portRef Q (instanceRef cnt_12)) + (portRef A (instanceRef cnt_RNIIH0I1_12)) + (portRef D (instanceRef tmp_clk_RNO_4)) + (portRef C (instanceRef cnt_RNISP9K91_12)) + )) + (net (rename cnt_s_12 "cnt_s[12]") (joined + (portRef S (instanceRef cnt_RNISP9K91_12)) + (portRef D (instanceRef cnt_12)) + )) + (net (rename cntZ0Z_13 "cnt[13]") (joined + (portRef Q (instanceRef cnt_13)) + (portRef D (instanceRef cnt_RNIAQCC_13)) + (portRef C (instanceRef tmp_clk_RNO_4)) + (portRef C (instanceRef cnt_RNILBPBC1_13)) + )) + (net (rename cnt_s_13 "cnt_s[13]") (joined + (portRef S (instanceRef cnt_RNILBPBC1_13)) + (portRef D (instanceRef cnt_13)) + )) + (net (rename cntZ0Z_14 "cnt[14]") (joined + (portRef Q (instanceRef cnt_14)) + (portRef C (instanceRef cnt_RNIAQCC_13)) + (portRef B (instanceRef tmp_clk_RNO_4)) + (portRef C (instanceRef cnt_RNIFU83F1_14)) + )) + (net (rename cnt_s_14 "cnt_s[14]") (joined + (portRef S (instanceRef cnt_RNIFU83F1_14)) + (portRef D (instanceRef cnt_14)) + )) + (net (rename cntZ0Z_15 "cnt[15]") (joined + (portRef Q (instanceRef cnt_15)) + (portRef B (instanceRef cnt_RNIAQCC_13)) + (portRef A (instanceRef tmp_clk_RNO_4)) + (portRef C (instanceRef cnt_RNIAIOQH1_15)) + )) + (net (rename cnt_s_15 "cnt_s[15]") (joined + (portRef S (instanceRef cnt_RNIAIOQH1_15)) + (portRef D (instanceRef cnt_15)) + )) + (net (rename cntZ0Z_16 "cnt[16]") (joined + (portRef Q (instanceRef cnt_16)) + (portRef A (instanceRef tmp_clk_RNO_1)) + (portRef A (instanceRef cnt_RNIAQCC_13)) + (portRef C (instanceRef cnt_RNI678IK1_16)) + )) + (net (rename cnt_s_16 "cnt_s[16]") (joined + (portRef S (instanceRef cnt_RNI678IK1_16)) + (portRef D (instanceRef cnt_16)) + )) + (net (rename cntZ0Z_17 "cnt[17]") (joined + (portRef Q (instanceRef cnt_17)) + (portRef D (instanceRef tmp_clk_RNO_1)) + (portRef A (instanceRef cnt_RNI4GAR1_17)) + (portRef C (instanceRef cnt_RNI3TN9N1_17)) + )) + (net (rename cnt_s_17 "cnt_s[17]") (joined + (portRef S (instanceRef cnt_RNI3TN9N1_17)) + (portRef D (instanceRef cnt_17)) + )) + (net (rename cntZ0Z_18 "cnt[18]") (joined + (portRef Q (instanceRef cnt_18)) + (portRef C (instanceRef tmp_clk_RNO_1)) + (portRef D (instanceRef cnt_RNI4GAR1_17)) + (portRef C (instanceRef cnt_RNI1K71Q1_18)) + )) + (net (rename cnt_s_18 "cnt_s[18]") (joined + (portRef S (instanceRef cnt_RNI1K71Q1_18)) + (portRef D (instanceRef cnt_18)) + )) + (net (rename cntZ0Z_19 "cnt[19]") (joined + (portRef Q (instanceRef cnt_19)) + (portRef C (instanceRef cnt_RNI4GAR1_17)) + (portRef D (instanceRef tmp_clk_RNO_2)) + (portRef C (instanceRef cnt_RNI0CNOS1_19)) + )) + (net (rename cnt_s_19 "cnt_s[19]") (joined + (portRef S (instanceRef cnt_RNI0CNOS1_19)) + (portRef D (instanceRef cnt_19)) + )) + (net (rename cntZ0Z_20 "cnt[20]") (joined + (portRef Q (instanceRef cnt_20)) + (portRef A (instanceRef cnt_RNI9EVA2_20)) + (portRef C (instanceRef tmp_clk_RNO_2)) + (portRef C (instanceRef cnt_RNINS7GV1_20)) + )) + (net (rename cnt_s_20 "cnt_s[20]") (joined + (portRef S (instanceRef cnt_RNINS7GV1_20)) + (portRef D (instanceRef cnt_20)) + )) + (net (rename cntZ0Z_21 "cnt[21]") (joined + (portRef Q (instanceRef cnt_21)) + (portRef C (instanceRef cnt_RNI4JC9_21)) + (portRef B (instanceRef tmp_clk_RNO_2)) + (portRef C (instanceRef cnt_RNIFEO722_21)) + )) + (net (rename cnt_s_21 "cnt_s[21]") (joined + (portRef S (instanceRef cnt_RNIFEO722_21)) + (portRef D (instanceRef cnt_21)) + )) + (net (rename cntZ0Z_22 "cnt[22]") (joined + (portRef Q (instanceRef cnt_22)) + (portRef B (instanceRef cnt_RNI4JC9_21)) + (portRef A (instanceRef tmp_clk_RNO_2)) + (portRef C (instanceRef cnt_RNI819V42_22)) + )) + (net (rename cnt_s_22 "cnt_s[22]") (joined + (portRef S (instanceRef cnt_RNI819V42_22)) + (portRef D (instanceRef cnt_22)) + )) + (net (rename cntZ0Z_23 "cnt[23]") (joined + (portRef Q (instanceRef cnt_23)) + (portRef B (instanceRef cnt_RNI9EVA2_20)) + (portRef A (instanceRef tmp_clk_RNO_0)) + (portRef C (instanceRef cnt_RNI2LPM72_23)) + )) + (net (rename cnt_s_23 "cnt_s[23]") (joined + (portRef S (instanceRef cnt_RNI2LPM72_23)) + (portRef D (instanceRef cnt_23)) + )) + (net (rename cntZ0Z_24 "cnt[24]") (joined + (portRef Q (instanceRef cnt_24)) + (portRef A (instanceRef cnt_RNI4JC9_21)) + (portRef B (instanceRef tmp_clk_RNO_0)) + (portRef C (instanceRef cnt_RNIT9AEA2_24)) + )) + (net (rename cnt_s_24 "cnt_s[24]") (joined + (portRef S (instanceRef cnt_RNIT9AEA2_24)) + (portRef D (instanceRef cnt_24)) + )) + (net (rename cntZ0Z_25 "cnt[25]") (joined + (portRef Q (instanceRef cnt_25)) + (portRef A (instanceRef tmp_clk_RNO)) + (portRef C (instanceRef cnt_RNIPVQ5D2_25)) + (portRef D (instanceRef cnt_RNIOCCK2_27)) + )) + (net (rename cnt_s_25 "cnt_s[25]") (joined + (portRef S (instanceRef cnt_RNIPVQ5D2_25)) + (portRef D (instanceRef cnt_25)) + )) + (net (rename cntZ0Z_26 "cnt[26]") (joined + (portRef Q (instanceRef cnt_26)) + (portRef D (instanceRef tmp_clk_RNO)) + (portRef C (instanceRef cnt_RNIMMBTF2_26)) + (portRef C (instanceRef cnt_RNIOCCK2_27)) + )) + (net (rename cnt_s_26 "cnt_s[26]") (joined + (portRef S (instanceRef cnt_RNIMMBTF2_26)) + (portRef D (instanceRef cnt_26)) + )) + (net (rename cntZ0Z_27 "cnt[27]") (joined + (portRef Q (instanceRef cnt_27)) + (portRef C (instanceRef tmp_clk_RNO)) + (portRef A (instanceRef cnt_RNIOCCK2_27)) + )) + (net (rename cnt_s_27 "cnt_s[27]") (joined + (portRef FCO (instanceRef cnt_RNIMMBTF2_26)) + (portRef D (instanceRef cnt_27)) + )) + (net cnt_cry_cy (joined + (portRef FCO (instanceRef cnt_RNIOCCK2_27)) + (portRef FCI (instanceRef cnt_RNITNTM5_0)) + )) + (net (rename cnt_RNIOCCK2_Y_27 "cnt_RNIOCCK2_Y[27]") (joined + (portRef Y (instanceRef cnt_RNIOCCK2_27)) + (portRef B (instanceRef cnt_RNIMMBTF2_26)) + (portRef B (instanceRef cnt_RNIPVQ5D2_25)) + (portRef B (instanceRef cnt_RNIT9AEA2_24)) + (portRef B (instanceRef cnt_RNI2LPM72_23)) + (portRef B (instanceRef cnt_RNI819V42_22)) + (portRef B (instanceRef cnt_RNIFEO722_21)) + (portRef B (instanceRef cnt_RNINS7GV1_20)) + (portRef B (instanceRef cnt_RNI0CNOS1_19)) + (portRef B (instanceRef cnt_RNI1K71Q1_18)) + (portRef B (instanceRef cnt_RNI3TN9N1_17)) + (portRef B (instanceRef cnt_RNI678IK1_16)) + (portRef B (instanceRef cnt_RNIAIOQH1_15)) + (portRef B (instanceRef cnt_RNIFU83F1_14)) + (portRef B (instanceRef cnt_RNILBPBC1_13)) + (portRef B (instanceRef cnt_RNISP9K91_12)) + (portRef B (instanceRef cnt_RNI49QS61_11)) + (portRef B (instanceRef cnt_RNIDPA541_10)) + (portRef B (instanceRef cnt_RNINARD11_9)) + (portRef B (instanceRef cnt_RNI9M9BU_8)) + (portRef B (instanceRef cnt_RNIS2O8R_7)) + (portRef B (instanceRef cnt_RNIGG66O_6)) + (portRef B (instanceRef cnt_RNI5VK3L_5)) + (portRef B (instanceRef cnt_RNIRE31I_4)) + (portRef B (instanceRef cnt_RNIIVHUE_3)) + (portRef B (instanceRef cnt_RNIAH0SB_2)) + (portRef B (instanceRef cnt_RNI34FP8_1)) + (portRef B (instanceRef cnt_RNITNTM5_0)) + )) + (net N_103 (joined + (portRef Y (instanceRef cnt_RNI9EVA2_20)) + (portRef B (instanceRef cnt_RNIOCCK2_27)) + )) + (net (rename cnt_cry_0 "cnt_cry[0]") (joined + (portRef FCO (instanceRef cnt_RNITNTM5_0)) + (portRef FCI (instanceRef cnt_RNI34FP8_1)) + )) + (net (rename cnt_cry_1 "cnt_cry[1]") (joined + (portRef FCO (instanceRef cnt_RNI34FP8_1)) + (portRef FCI (instanceRef cnt_RNIAH0SB_2)) + )) + (net (rename cnt_cry_2 "cnt_cry[2]") (joined + (portRef FCO (instanceRef cnt_RNIAH0SB_2)) + (portRef FCI (instanceRef cnt_RNIIVHUE_3)) + )) + (net (rename cnt_cry_3 "cnt_cry[3]") (joined + (portRef FCO (instanceRef cnt_RNIIVHUE_3)) + (portRef FCI (instanceRef cnt_RNIRE31I_4)) + )) + (net (rename cnt_cry_4 "cnt_cry[4]") (joined + (portRef FCO (instanceRef cnt_RNIRE31I_4)) + (portRef FCI (instanceRef cnt_RNI5VK3L_5)) + )) + (net (rename cnt_cry_5 "cnt_cry[5]") (joined + (portRef FCO (instanceRef cnt_RNI5VK3L_5)) + (portRef FCI (instanceRef cnt_RNIGG66O_6)) + )) + (net (rename cnt_cry_6 "cnt_cry[6]") (joined + (portRef FCO (instanceRef cnt_RNIGG66O_6)) + (portRef FCI (instanceRef cnt_RNIS2O8R_7)) + )) + (net (rename cnt_cry_7 "cnt_cry[7]") (joined + (portRef FCO (instanceRef cnt_RNIS2O8R_7)) + (portRef FCI (instanceRef cnt_RNI9M9BU_8)) + )) + (net (rename cnt_cry_8 "cnt_cry[8]") (joined + (portRef FCO (instanceRef cnt_RNI9M9BU_8)) + (portRef FCI (instanceRef cnt_RNINARD11_9)) + )) + (net (rename cnt_cry_9 "cnt_cry[9]") (joined + (portRef FCO (instanceRef cnt_RNINARD11_9)) + (portRef FCI (instanceRef cnt_RNIDPA541_10)) + )) + (net (rename cnt_cry_10 "cnt_cry[10]") (joined + (portRef FCO (instanceRef cnt_RNIDPA541_10)) + (portRef FCI (instanceRef cnt_RNI49QS61_11)) + )) + (net (rename cnt_cry_11 "cnt_cry[11]") (joined + (portRef FCO (instanceRef cnt_RNI49QS61_11)) + (portRef FCI (instanceRef cnt_RNISP9K91_12)) + )) + (net (rename cnt_cry_12 "cnt_cry[12]") (joined + (portRef FCO (instanceRef cnt_RNISP9K91_12)) + (portRef FCI (instanceRef cnt_RNILBPBC1_13)) + )) + (net (rename cnt_cry_13 "cnt_cry[13]") (joined + (portRef FCO (instanceRef cnt_RNILBPBC1_13)) + (portRef FCI (instanceRef cnt_RNIFU83F1_14)) + )) + (net (rename cnt_cry_14 "cnt_cry[14]") (joined + (portRef FCO (instanceRef cnt_RNIFU83F1_14)) + (portRef FCI (instanceRef cnt_RNIAIOQH1_15)) + )) + (net (rename cnt_cry_15 "cnt_cry[15]") (joined + (portRef FCO (instanceRef cnt_RNIAIOQH1_15)) + (portRef FCI (instanceRef cnt_RNI678IK1_16)) + )) + (net (rename cnt_cry_16 "cnt_cry[16]") (joined + (portRef FCO (instanceRef cnt_RNI678IK1_16)) + (portRef FCI (instanceRef cnt_RNI3TN9N1_17)) + )) + (net (rename cnt_cry_17 "cnt_cry[17]") (joined + (portRef FCO (instanceRef cnt_RNI3TN9N1_17)) + (portRef FCI (instanceRef cnt_RNI1K71Q1_18)) + )) + (net (rename cnt_cry_18 "cnt_cry[18]") (joined + (portRef FCO (instanceRef cnt_RNI1K71Q1_18)) + (portRef FCI (instanceRef cnt_RNI0CNOS1_19)) + )) + (net (rename cnt_cry_19 "cnt_cry[19]") (joined + (portRef FCO (instanceRef cnt_RNI0CNOS1_19)) + (portRef FCI (instanceRef cnt_RNINS7GV1_20)) + )) + (net (rename cnt_cry_20 "cnt_cry[20]") (joined + (portRef FCO (instanceRef cnt_RNINS7GV1_20)) + (portRef FCI (instanceRef cnt_RNIFEO722_21)) + )) + (net (rename cnt_cry_21 "cnt_cry[21]") (joined + (portRef FCO (instanceRef cnt_RNIFEO722_21)) + (portRef FCI (instanceRef cnt_RNI819V42_22)) + )) + (net (rename cnt_cry_22 "cnt_cry[22]") (joined + (portRef FCO (instanceRef cnt_RNI819V42_22)) + (portRef FCI (instanceRef cnt_RNI2LPM72_23)) + )) + (net (rename cnt_cry_23 "cnt_cry[23]") (joined + (portRef FCO (instanceRef cnt_RNI2LPM72_23)) + (portRef FCI (instanceRef cnt_RNIT9AEA2_24)) + )) + (net (rename cnt_cry_24 "cnt_cry[24]") (joined + (portRef FCO (instanceRef cnt_RNIT9AEA2_24)) + (portRef FCI (instanceRef cnt_RNIPVQ5D2_25)) + )) + (net (rename cnt_cry_25 "cnt_cry[25]") (joined + (portRef FCO (instanceRef cnt_RNIPVQ5D2_25)) + (portRef FCI (instanceRef cnt_RNIMMBTF2_26)) + )) + (net N_94 (joined + (portRef Y (instanceRef tmp_clk_RNO_1)) + (portRef C (instanceRef tmp_clk_RNO_0)) + )) + (net m39_e_1 (joined + (portRef Y (instanceRef tmp_clk_RNO_2)) + (portRef D (instanceRef tmp_clk_RNO_0)) + )) + (net N_105 (joined + (portRef Y (instanceRef tmp_clk_RNO_0)) + (portRef B (instanceRef tmp_clk_RNO)) + )) + (net m21_e_2 (joined + (portRef Y (instanceRef cnt_RNI4JC9_21)) + (portRef D (instanceRef cnt_RNI9EVA2_20)) + )) + (net m30_e_1 (joined + (portRef Y (instanceRef tmp_clk_RNO_4)) + (portRef B (instanceRef tmp_clk_RNO_3)) + )) + (net m13_e_1 (joined + (portRef Y (instanceRef cnt_RNIAQCC_13)) + (portRef B (instanceRef cnt_RNIIH0I1_12)) + )) + (net N_176 (joined + (portRef Y (instanceRef cnt_RNI8JG21_10)) + (portRef C (instanceRef cnt_RNIIH0I1_12)) + (portRef C (instanceRef tmp_clk_RNO_3)) + )) + (net N_88 (joined + (portRef Y (instanceRef tmp_clk_RNO_3)) + (portRef B (instanceRef tmp_clk_RNO_1)) + )) + (net N_87 (joined + (portRef Y (instanceRef cnt_RNIIH0I1_12)) + (portRef B (instanceRef cnt_RNI4GAR1_17)) + )) + (net N_93 (joined + (portRef Y (instanceRef cnt_RNI4GAR1_17)) + (portRef C (instanceRef cnt_RNI9EVA2_20)) + )) + ) + (property orig_inst_of (string "ClkGenNoSwitch")) + ) + ) + (cell ClkGen (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port led (direction OUTPUT)) + (port reset (direction INPUT)) + (port clk_c (direction INPUT)) + (port SW1_c (direction INPUT)) + ) + (contents + (instance tmp_clk (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_0 "cnt[0]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_1 "cnt[1]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_2 "cnt[2]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_3 "cnt[3]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_4 "cnt[4]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_5 "cnt[5]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_6 "cnt[6]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_7 "cnt[7]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_8 "cnt[8]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_9 "cnt[9]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_10 "cnt[10]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_11 "cnt[11]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_12 "cnt[12]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_13 "cnt[13]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_14 "cnt[14]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_15 "cnt[15]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_16 "cnt[16]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_17 "cnt[17]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_18 "cnt[18]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_19 "cnt[19]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_20 "cnt[20]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_21 "cnt[21]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_22 "cnt[22]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_23 "cnt[23]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_24 "cnt[24]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_25 "cnt[25]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance un14_cntlto31_0_o3_RNI33E32 (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "4F444")) + ) + (instance (rename cnt_RNI24MJ4_0 "cnt_RNI24MJ4[0]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI26U37_1 "cnt_RNI26U37[1]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI396K9_2 "cnt_RNI396K9[2]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI5DE4C_3 "cnt_RNI5DE4C[3]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI8IMKE_4 "cnt_RNI8IMKE[4]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNICOU4H_5 "cnt_RNICOU4H[5]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIHV6LJ_6 "cnt_RNIHV6LJ[6]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIN7F5M_7 "cnt_RNIN7F5M[7]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIUGNLO_8 "cnt_RNIUGNLO[8]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI6RV5R_9 "cnt_RNI6RV5R[9]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIME5GT_10 "cnt_RNIME5GT[10]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI73BQV_11 "cnt_RNI73BQV[11]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIPOG421_12 "cnt_RNIPOG421[12]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNICFME41_13 "cnt_RNICFME41[13]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI07SO61_14 "cnt_RNI07SO61[14]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNILV1391_15 "cnt_RNILV1391[15]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIBP7DB1_16 "cnt_RNIBP7DB1[16]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI2KDND1_17 "cnt_RNI2KDND1[17]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIQFJ1G1_18 "cnt_RNIQFJ1G1[18]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIJCPBI1_19 "cnt_RNIJCPBI1[19]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI420MK1_20 "cnt_RNI420MK1[20]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIMO60N1_21 "cnt_RNIMO60N1[21]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI9GDAP1_22 "cnt_RNI9GDAP1[22]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIT8KKR1_23 "cnt_RNIT8KKR1[23]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNII2RUT1_24 "cnt_RNII2RUT1[24]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance un14_cntlto31_0_a2 (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "45")) + ) + (instance un14_cntlto31_0_o2_3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "7FFF")) + ) + (instance un14_cntlto31_0_o2_0 (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "7F")) + ) + (instance un14_cntlto31_0_a2_1_3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0001")) + ) + (instance un7_cntlto31_0_a2_1 (viewRef PRIM (cellRef CFG2 (libraryRef ACG4))) + (property INIT (string "2")) + ) + (instance un14_cntlto31_0_o3_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "F7F5")) + ) + (instance un14_cntlto31_0_o3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0FDF")) + ) + (instance un7_cntlto31_0_a2_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "5551")) + ) + (instance un14_cntlto31_0_o3_0_RNI3K631 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0073")) + ) + (instance un7_cntlto31_0_a2 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0031")) + ) + (instance un7_cntlto31_0_a3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "000D")) + ) + (instance un7_cntlto31_0_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "FF10")) + ) + (instance GND (viewRef PRIM (cellRef GND (libraryRef ACG4))) ) + (instance VCC (viewRef PRIM (cellRef VCC (libraryRef ACG4))) ) + (net led (joined + (portRef Q (instanceRef tmp_clk)) + (portRef led) + )) + (net (rename VCCZ0 "VCC") (joined + (portRef Y (instanceRef VCC)) + (portRef A (instanceRef cnt_RNII2RUT1_24)) + (portRef A (instanceRef cnt_RNIT8KKR1_23)) + (portRef A (instanceRef cnt_RNI9GDAP1_22)) + (portRef A (instanceRef cnt_RNIMO60N1_21)) + (portRef A (instanceRef cnt_RNI420MK1_20)) + (portRef A (instanceRef cnt_RNIJCPBI1_19)) + (portRef A (instanceRef cnt_RNIQFJ1G1_18)) + (portRef A (instanceRef cnt_RNI2KDND1_17)) + (portRef A (instanceRef cnt_RNIBP7DB1_16)) + (portRef A (instanceRef cnt_RNILV1391_15)) + (portRef A (instanceRef cnt_RNI07SO61_14)) + (portRef A (instanceRef cnt_RNICFME41_13)) + (portRef A (instanceRef cnt_RNIPOG421_12)) + (portRef A (instanceRef cnt_RNI73BQV_11)) + (portRef A (instanceRef cnt_RNIME5GT_10)) + (portRef A (instanceRef cnt_RNI6RV5R_9)) + (portRef A (instanceRef cnt_RNIUGNLO_8)) + (portRef A (instanceRef cnt_RNIN7F5M_7)) + (portRef A (instanceRef cnt_RNIHV6LJ_6)) + (portRef A (instanceRef cnt_RNICOU4H_5)) + (portRef A (instanceRef cnt_RNI8IMKE_4)) + (portRef A (instanceRef cnt_RNI5DE4C_3)) + (portRef A (instanceRef cnt_RNI396K9_2)) + (portRef A (instanceRef cnt_RNI26U37_1)) + (portRef A (instanceRef cnt_RNI24MJ4_0)) + (portRef FCI (instanceRef un14_cntlto31_0_o3_RNI33E32)) + (portRef SLn (instanceRef cnt_25)) + (portRef ADn (instanceRef cnt_25)) + (portRef SLn (instanceRef cnt_24)) + (portRef ADn (instanceRef cnt_24)) + (portRef SLn (instanceRef cnt_23)) + (portRef ADn (instanceRef cnt_23)) + (portRef SLn (instanceRef cnt_22)) + (portRef ADn (instanceRef cnt_22)) + (portRef SLn (instanceRef cnt_21)) + (portRef ADn (instanceRef cnt_21)) + (portRef SLn (instanceRef cnt_20)) + (portRef ADn (instanceRef cnt_20)) + (portRef SLn (instanceRef cnt_19)) + (portRef ADn (instanceRef cnt_19)) + (portRef SLn (instanceRef cnt_18)) + (portRef ADn (instanceRef cnt_18)) + (portRef SLn (instanceRef cnt_17)) + (portRef ADn (instanceRef cnt_17)) + (portRef SLn (instanceRef cnt_16)) + (portRef ADn (instanceRef cnt_16)) + (portRef SLn (instanceRef cnt_15)) + (portRef ADn (instanceRef cnt_15)) + (portRef SLn (instanceRef cnt_14)) + (portRef ADn (instanceRef cnt_14)) + (portRef SLn (instanceRef cnt_13)) + (portRef ADn (instanceRef cnt_13)) + (portRef SLn (instanceRef cnt_12)) + (portRef ADn (instanceRef cnt_12)) + (portRef SLn (instanceRef cnt_11)) + (portRef ADn (instanceRef cnt_11)) + (portRef SLn (instanceRef cnt_10)) + (portRef ADn (instanceRef cnt_10)) + (portRef SLn (instanceRef cnt_9)) + (portRef ADn (instanceRef cnt_9)) + (portRef SLn (instanceRef cnt_8)) + (portRef ADn (instanceRef cnt_8)) + (portRef SLn (instanceRef cnt_7)) + (portRef ADn (instanceRef cnt_7)) + (portRef SLn (instanceRef cnt_6)) + (portRef ADn (instanceRef cnt_6)) + (portRef SLn (instanceRef cnt_5)) + (portRef ADn (instanceRef cnt_5)) + (portRef SLn (instanceRef cnt_4)) + (portRef ADn (instanceRef cnt_4)) + (portRef SLn (instanceRef cnt_3)) + (portRef ADn (instanceRef cnt_3)) + (portRef SLn (instanceRef cnt_2)) + (portRef ADn (instanceRef cnt_2)) + (portRef SLn (instanceRef cnt_1)) + (portRef ADn (instanceRef cnt_1)) + (portRef SLn (instanceRef cnt_0)) + (portRef ADn (instanceRef cnt_0)) + (portRef SLn (instanceRef tmp_clk)) + (portRef ADn (instanceRef tmp_clk)) + )) + (net reset (joined + (portRef reset) + (portRef ALn (instanceRef cnt_25)) + (portRef ALn (instanceRef cnt_24)) + (portRef ALn (instanceRef cnt_23)) + (portRef ALn (instanceRef cnt_22)) + (portRef ALn (instanceRef cnt_21)) + (portRef ALn (instanceRef cnt_20)) + (portRef ALn (instanceRef cnt_19)) + (portRef ALn (instanceRef cnt_18)) + (portRef ALn (instanceRef cnt_17)) + (portRef ALn (instanceRef cnt_16)) + (portRef ALn (instanceRef cnt_15)) + (portRef ALn (instanceRef cnt_14)) + (portRef ALn (instanceRef cnt_13)) + (portRef ALn (instanceRef cnt_12)) + (portRef ALn (instanceRef cnt_11)) + (portRef ALn (instanceRef cnt_10)) + (portRef ALn (instanceRef cnt_9)) + (portRef ALn (instanceRef cnt_8)) + (portRef ALn (instanceRef cnt_7)) + (portRef ALn (instanceRef cnt_6)) + (portRef ALn (instanceRef cnt_5)) + (portRef ALn (instanceRef cnt_4)) + (portRef ALn (instanceRef cnt_3)) + (portRef ALn (instanceRef cnt_2)) + (portRef ALn (instanceRef cnt_1)) + (portRef ALn (instanceRef cnt_0)) + (portRef ALn (instanceRef tmp_clk)) + )) + (net clk_c (joined + (portRef clk_c) + (portRef CLK (instanceRef cnt_25)) + (portRef CLK (instanceRef cnt_24)) + (portRef CLK (instanceRef cnt_23)) + (portRef CLK (instanceRef cnt_22)) + (portRef CLK (instanceRef cnt_21)) + (portRef CLK (instanceRef cnt_20)) + (portRef CLK (instanceRef cnt_19)) + (portRef CLK (instanceRef cnt_18)) + (portRef CLK (instanceRef cnt_17)) + (portRef CLK (instanceRef cnt_16)) + (portRef CLK (instanceRef cnt_15)) + (portRef CLK (instanceRef cnt_14)) + (portRef CLK (instanceRef cnt_13)) + (portRef CLK (instanceRef cnt_12)) + (portRef CLK (instanceRef cnt_11)) + (portRef CLK (instanceRef cnt_10)) + (portRef CLK (instanceRef cnt_9)) + (portRef CLK (instanceRef cnt_8)) + (portRef CLK (instanceRef cnt_7)) + (portRef CLK (instanceRef cnt_6)) + (portRef CLK (instanceRef cnt_5)) + (portRef CLK (instanceRef cnt_4)) + (portRef CLK (instanceRef cnt_3)) + (portRef CLK (instanceRef cnt_2)) + (portRef CLK (instanceRef cnt_1)) + (portRef CLK (instanceRef cnt_0)) + (portRef CLK (instanceRef tmp_clk)) + )) + (net (rename un7_cntlto31_0Z0Z_0 "un7_cntlto31_0_0") (joined + (portRef Y (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef tmp_clk)) + )) + (net (rename sw1_c "SW1_c") (joined + (portRef SW1_c) + (portRef EN (instanceRef cnt_25)) + (portRef EN (instanceRef cnt_24)) + (portRef EN (instanceRef cnt_23)) + (portRef EN (instanceRef cnt_22)) + (portRef EN (instanceRef cnt_21)) + (portRef EN (instanceRef cnt_20)) + (portRef EN (instanceRef cnt_19)) + (portRef EN (instanceRef cnt_18)) + (portRef EN (instanceRef cnt_17)) + (portRef EN (instanceRef cnt_16)) + (portRef EN (instanceRef cnt_15)) + (portRef EN (instanceRef cnt_14)) + (portRef EN (instanceRef cnt_13)) + (portRef EN (instanceRef cnt_12)) + (portRef EN (instanceRef cnt_11)) + (portRef EN (instanceRef cnt_10)) + (portRef EN (instanceRef cnt_9)) + (portRef EN (instanceRef cnt_8)) + (portRef EN (instanceRef cnt_7)) + (portRef EN (instanceRef cnt_6)) + (portRef EN (instanceRef cnt_5)) + (portRef EN (instanceRef cnt_4)) + (portRef EN (instanceRef cnt_3)) + (portRef EN (instanceRef cnt_2)) + (portRef EN (instanceRef cnt_1)) + (portRef EN (instanceRef cnt_0)) + (portRef EN (instanceRef tmp_clk)) + )) + (net (rename GNDZ0 "GND") (joined + (portRef Y (instanceRef GND)) + (portRef D (instanceRef cnt_RNII2RUT1_24)) + (portRef D (instanceRef cnt_RNIT8KKR1_23)) + (portRef D (instanceRef cnt_RNI9GDAP1_22)) + (portRef D (instanceRef cnt_RNIMO60N1_21)) + (portRef D (instanceRef cnt_RNI420MK1_20)) + (portRef D (instanceRef cnt_RNIJCPBI1_19)) + (portRef D (instanceRef cnt_RNIQFJ1G1_18)) + (portRef D (instanceRef cnt_RNI2KDND1_17)) + (portRef D (instanceRef cnt_RNIBP7DB1_16)) + (portRef D (instanceRef cnt_RNILV1391_15)) + (portRef D (instanceRef cnt_RNI07SO61_14)) + (portRef D (instanceRef cnt_RNICFME41_13)) + (portRef D (instanceRef cnt_RNIPOG421_12)) + (portRef D (instanceRef cnt_RNI73BQV_11)) + (portRef D (instanceRef cnt_RNIME5GT_10)) + (portRef D (instanceRef cnt_RNI6RV5R_9)) + (portRef D (instanceRef cnt_RNIUGNLO_8)) + (portRef D (instanceRef cnt_RNIN7F5M_7)) + (portRef D (instanceRef cnt_RNIHV6LJ_6)) + (portRef D (instanceRef cnt_RNICOU4H_5)) + (portRef D (instanceRef cnt_RNI8IMKE_4)) + (portRef D (instanceRef cnt_RNI5DE4C_3)) + (portRef D (instanceRef cnt_RNI396K9_2)) + (portRef D (instanceRef cnt_RNI26U37_1)) + (portRef D (instanceRef cnt_RNI24MJ4_0)) + (portRef SD (instanceRef cnt_25)) + (portRef LAT (instanceRef cnt_25)) + (portRef SD (instanceRef cnt_24)) + (portRef LAT (instanceRef cnt_24)) + (portRef SD (instanceRef cnt_23)) + (portRef LAT (instanceRef cnt_23)) + (portRef SD (instanceRef cnt_22)) + (portRef LAT (instanceRef cnt_22)) + (portRef SD (instanceRef cnt_21)) + (portRef LAT (instanceRef cnt_21)) + (portRef SD (instanceRef cnt_20)) + (portRef LAT (instanceRef cnt_20)) + (portRef SD (instanceRef cnt_19)) + (portRef LAT (instanceRef cnt_19)) + (portRef SD (instanceRef cnt_18)) + (portRef LAT (instanceRef cnt_18)) + (portRef SD (instanceRef cnt_17)) + (portRef LAT (instanceRef cnt_17)) + (portRef SD (instanceRef cnt_16)) + (portRef LAT (instanceRef cnt_16)) + (portRef SD (instanceRef cnt_15)) + (portRef LAT (instanceRef cnt_15)) + (portRef SD (instanceRef cnt_14)) + (portRef LAT (instanceRef cnt_14)) + (portRef SD (instanceRef cnt_13)) + (portRef LAT (instanceRef cnt_13)) + (portRef SD (instanceRef cnt_12)) + (portRef LAT (instanceRef cnt_12)) + (portRef SD (instanceRef cnt_11)) + (portRef LAT (instanceRef cnt_11)) + (portRef SD (instanceRef cnt_10)) + (portRef LAT (instanceRef cnt_10)) + (portRef SD (instanceRef cnt_9)) + (portRef LAT (instanceRef cnt_9)) + (portRef SD (instanceRef cnt_8)) + (portRef LAT (instanceRef cnt_8)) + (portRef SD (instanceRef cnt_7)) + (portRef LAT (instanceRef cnt_7)) + (portRef SD (instanceRef cnt_6)) + (portRef LAT (instanceRef cnt_6)) + (portRef SD (instanceRef cnt_5)) + (portRef LAT (instanceRef cnt_5)) + (portRef SD (instanceRef cnt_4)) + (portRef LAT (instanceRef cnt_4)) + (portRef SD (instanceRef cnt_3)) + (portRef LAT (instanceRef cnt_3)) + (portRef SD (instanceRef cnt_2)) + (portRef LAT (instanceRef cnt_2)) + (portRef SD (instanceRef cnt_1)) + (portRef LAT (instanceRef cnt_1)) + (portRef SD (instanceRef cnt_0)) + (portRef LAT (instanceRef cnt_0)) + (portRef SD (instanceRef tmp_clk)) + (portRef LAT (instanceRef tmp_clk)) + )) + (net (rename cntZ0Z_0 "cnt[0]") (joined + (portRef Q (instanceRef cnt_0)) + (portRef C (instanceRef cnt_RNI24MJ4_0)) + )) + (net (rename cnt_s_0 "cnt_s[0]") (joined + (portRef S (instanceRef cnt_RNI24MJ4_0)) + (portRef D (instanceRef cnt_0)) + )) + (net (rename cntZ0Z_1 "cnt[1]") (joined + (portRef Q (instanceRef cnt_1)) + (portRef C (instanceRef cnt_RNI26U37_1)) + )) + (net (rename cnt_s_1 "cnt_s[1]") (joined + (portRef S (instanceRef cnt_RNI26U37_1)) + (portRef D (instanceRef cnt_1)) + )) + (net (rename cntZ0Z_2 "cnt[2]") (joined + (portRef Q (instanceRef cnt_2)) + (portRef C (instanceRef cnt_RNI396K9_2)) + )) + (net (rename cnt_s_2 "cnt_s[2]") (joined + (portRef S (instanceRef cnt_RNI396K9_2)) + (portRef D (instanceRef cnt_2)) + )) + (net (rename cntZ0Z_3 "cnt[3]") (joined + (portRef Q (instanceRef cnt_3)) + (portRef C (instanceRef cnt_RNI5DE4C_3)) + )) + (net (rename cnt_s_3 "cnt_s[3]") (joined + (portRef S (instanceRef cnt_RNI5DE4C_3)) + (portRef D (instanceRef cnt_3)) + )) + (net (rename cntZ0Z_4 "cnt[4]") (joined + (portRef Q (instanceRef cnt_4)) + (portRef C (instanceRef cnt_RNI8IMKE_4)) + )) + (net (rename cnt_s_4 "cnt_s[4]") (joined + (portRef S (instanceRef cnt_RNI8IMKE_4)) + (portRef D (instanceRef cnt_4)) + )) + (net (rename cntZ0Z_5 "cnt[5]") (joined + (portRef Q (instanceRef cnt_5)) + (portRef B (instanceRef un7_cntlto31_0_a2_1)) + (portRef C (instanceRef cnt_RNICOU4H_5)) + )) + (net (rename cnt_s_5 "cnt_s[5]") (joined + (portRef S (instanceRef cnt_RNICOU4H_5)) + (portRef D (instanceRef cnt_5)) + )) + (net (rename cntZ0Z_6 "cnt[6]") (joined + (portRef Q (instanceRef cnt_6)) + (portRef D (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNIHV6LJ_6)) + )) + (net (rename cnt_s_6 "cnt_s[6]") (joined + (portRef S (instanceRef cnt_RNIHV6LJ_6)) + (portRef D (instanceRef cnt_6)) + )) + (net (rename cntZ0Z_7 "cnt[7]") (joined + (portRef Q (instanceRef cnt_7)) + (portRef C (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNIN7F5M_7)) + )) + (net (rename cnt_s_7 "cnt_s[7]") (joined + (portRef S (instanceRef cnt_RNIN7F5M_7)) + (portRef D (instanceRef cnt_7)) + )) + (net (rename cntZ0Z_8 "cnt[8]") (joined + (portRef Q (instanceRef cnt_8)) + (portRef B (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNIUGNLO_8)) + )) + (net (rename cnt_s_8 "cnt_s[8]") (joined + (portRef S (instanceRef cnt_RNIUGNLO_8)) + (portRef D (instanceRef cnt_8)) + )) + (net (rename cntZ0Z_9 "cnt[9]") (joined + (portRef Q (instanceRef cnt_9)) + (portRef A (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNI6RV5R_9)) + )) + (net (rename cnt_s_9 "cnt_s[9]") (joined + (portRef S (instanceRef cnt_RNI6RV5R_9)) + (portRef D (instanceRef cnt_9)) + )) + (net (rename cntZ0Z_10 "cnt[10]") (joined + (portRef Q (instanceRef cnt_10)) + (portRef B (instanceRef un7_cntlto31_0_a2_0)) + (portRef B (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef cnt_RNIME5GT_10)) + )) + (net (rename cnt_s_10 "cnt_s[10]") (joined + (portRef S (instanceRef cnt_RNIME5GT_10)) + (portRef D (instanceRef cnt_10)) + )) + (net (rename cntZ0Z_11 "cnt[11]") (joined + (portRef Q (instanceRef cnt_11)) + (portRef C (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNI73BQV_11)) + )) + (net (rename cnt_s_11 "cnt_s[11]") (joined + (portRef S (instanceRef cnt_RNI73BQV_11)) + (portRef D (instanceRef cnt_11)) + )) + (net (rename cntZ0Z_12 "cnt[12]") (joined + (portRef Q (instanceRef cnt_12)) + (portRef B (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNIPOG421_12)) + )) + (net (rename cnt_s_12 "cnt_s[12]") (joined + (portRef S (instanceRef cnt_RNIPOG421_12)) + (portRef D (instanceRef cnt_12)) + )) + (net (rename cntZ0Z_13 "cnt[13]") (joined + (portRef Q (instanceRef cnt_13)) + (portRef A (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNICFME41_13)) + )) + (net (rename cnt_s_13 "cnt_s[13]") (joined + (portRef S (instanceRef cnt_RNICFME41_13)) + (portRef D (instanceRef cnt_13)) + )) + (net (rename cntZ0Z_14 "cnt[14]") (joined + (portRef Q (instanceRef cnt_14)) + (portRef A (instanceRef un7_cntlto31_0_a2_0)) + (portRef A (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef cnt_RNI07SO61_14)) + )) + (net (rename cnt_s_14 "cnt_s[14]") (joined + (portRef S (instanceRef cnt_RNI07SO61_14)) + (portRef D (instanceRef cnt_14)) + )) + (net (rename cntZ0Z_15 "cnt[15]") (joined + (portRef Q (instanceRef cnt_15)) + (portRef A (instanceRef un7_cntlto31_0_a2)) + (portRef A (instanceRef un14_cntlto31_0_o3_0_RNI3K631)) + (portRef C (instanceRef cnt_RNILV1391_15)) + )) + (net (rename cnt_s_15 "cnt_s[15]") (joined + (portRef S (instanceRef cnt_RNILV1391_15)) + (portRef D (instanceRef cnt_15)) + )) + (net (rename cntZ0Z_16 "cnt[16]") (joined + (portRef Q (instanceRef cnt_16)) + (portRef B (instanceRef un7_cntlto31_0_a2)) + (portRef B (instanceRef un14_cntlto31_0_o3_0_RNI3K631)) + (portRef C (instanceRef cnt_RNIBP7DB1_16)) + )) + (net (rename cnt_s_16 "cnt_s[16]") (joined + (portRef S (instanceRef cnt_RNIBP7DB1_16)) + (portRef D (instanceRef cnt_16)) + )) + (net (rename cntZ0Z_17 "cnt[17]") (joined + (portRef Q (instanceRef cnt_17)) + (portRef C (instanceRef un14_cntlto31_0_a2)) + (portRef C (instanceRef cnt_RNI2KDND1_17)) + )) + (net (rename cnt_s_17 "cnt_s[17]") (joined + (portRef S (instanceRef cnt_RNI2KDND1_17)) + (portRef D (instanceRef cnt_17)) + )) + (net (rename cntZ0Z_18 "cnt[18]") (joined + (portRef Q (instanceRef cnt_18)) + (portRef D (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNIQFJ1G1_18)) + )) + (net (rename cnt_s_18 "cnt_s[18]") (joined + (portRef S (instanceRef cnt_RNIQFJ1G1_18)) + (portRef D (instanceRef cnt_18)) + )) + (net (rename cntZ0Z_19 "cnt[19]") (joined + (portRef Q (instanceRef cnt_19)) + (portRef C (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNIJCPBI1_19)) + )) + (net (rename cnt_s_19 "cnt_s[19]") (joined + (portRef S (instanceRef cnt_RNIJCPBI1_19)) + (portRef D (instanceRef cnt_19)) + )) + (net (rename cntZ0Z_20 "cnt[20]") (joined + (portRef Q (instanceRef cnt_20)) + (portRef B (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNI420MK1_20)) + )) + (net (rename cnt_s_20 "cnt_s[20]") (joined + (portRef S (instanceRef cnt_RNI420MK1_20)) + (portRef D (instanceRef cnt_20)) + )) + (net (rename cntZ0Z_21 "cnt[21]") (joined + (portRef Q (instanceRef cnt_21)) + (portRef A (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNIMO60N1_21)) + )) + (net (rename cnt_s_21 "cnt_s[21]") (joined + (portRef S (instanceRef cnt_RNIMO60N1_21)) + (portRef D (instanceRef cnt_21)) + )) + (net (rename cntZ0Z_22 "cnt[22]") (joined + (portRef Q (instanceRef cnt_22)) + (portRef B (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef un7_cntlto31_0_a2)) + (portRef A (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNI9GDAP1_22)) + )) + (net (rename cnt_s_22 "cnt_s[22]") (joined + (portRef S (instanceRef cnt_RNI9GDAP1_22)) + (portRef D (instanceRef cnt_22)) + )) + (net (rename cntZ0Z_23 "cnt[23]") (joined + (portRef Q (instanceRef cnt_23)) + (portRef A (instanceRef un7_cntlto31_0_a3)) + (portRef D (instanceRef un14_cntlto31_0_o3_0_RNI3K631)) + (portRef D (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNIT8KKR1_23)) + )) + (net (rename cnt_s_23 "cnt_s[23]") (joined + (portRef S (instanceRef cnt_RNIT8KKR1_23)) + (portRef D (instanceRef cnt_23)) + )) + (net (rename cntZ0Z_24 "cnt[24]") (joined + (portRef Q (instanceRef cnt_24)) + (portRef A (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef un7_cntlto31_0_a3)) + (portRef C (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNII2RUT1_24)) + )) + (net (rename cnt_s_24 "cnt_s[24]") (joined + (portRef S (instanceRef cnt_RNII2RUT1_24)) + (portRef D (instanceRef cnt_24)) + )) + (net (rename cntZ0Z_25 "cnt[25]") (joined + (portRef Q (instanceRef cnt_25)) + (portRef C (instanceRef un7_cntlto31_0_a3)) + (portRef A (instanceRef un14_cntlto31_0_a2)) + (portRef B (instanceRef un14_cntlto31_0_o3_RNI33E32)) + )) + (net (rename cnt_s_25 "cnt_s[25]") (joined + (portRef FCO (instanceRef cnt_RNII2RUT1_24)) + (portRef D (instanceRef cnt_25)) + )) + (net cnt_cry_cy (joined + (portRef FCO (instanceRef un14_cntlto31_0_o3_RNI33E32)) + (portRef FCI (instanceRef cnt_RNI24MJ4_0)) + )) + (net un14_cntlto31_0_o3_RNI33E32_Y (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_RNI33E32)) + (portRef B (instanceRef cnt_RNII2RUT1_24)) + (portRef B (instanceRef cnt_RNIT8KKR1_23)) + (portRef B (instanceRef cnt_RNI9GDAP1_22)) + (portRef B (instanceRef cnt_RNIMO60N1_21)) + (portRef B (instanceRef cnt_RNI420MK1_20)) + (portRef B (instanceRef cnt_RNIJCPBI1_19)) + (portRef B (instanceRef cnt_RNIQFJ1G1_18)) + (portRef B (instanceRef cnt_RNI2KDND1_17)) + (portRef B (instanceRef cnt_RNIBP7DB1_16)) + (portRef B (instanceRef cnt_RNILV1391_15)) + (portRef B (instanceRef cnt_RNI07SO61_14)) + (portRef B (instanceRef cnt_RNICFME41_13)) + (portRef B (instanceRef cnt_RNIPOG421_12)) + (portRef B (instanceRef cnt_RNI73BQV_11)) + (portRef B (instanceRef cnt_RNIME5GT_10)) + (portRef B (instanceRef cnt_RNI6RV5R_9)) + (portRef B (instanceRef cnt_RNIUGNLO_8)) + (portRef B (instanceRef cnt_RNIN7F5M_7)) + (portRef B (instanceRef cnt_RNIHV6LJ_6)) + (portRef B (instanceRef cnt_RNICOU4H_5)) + (portRef B (instanceRef cnt_RNI8IMKE_4)) + (portRef B (instanceRef cnt_RNI5DE4C_3)) + (portRef B (instanceRef cnt_RNI396K9_2)) + (portRef B (instanceRef cnt_RNI26U37_1)) + (portRef B (instanceRef cnt_RNI24MJ4_0)) + )) + (net N_313_tz (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_0_RNI3K631)) + (portRef A (instanceRef un14_cntlto31_0_o3_RNI33E32)) + )) + (net un14_cntlto31_0_o3_1 (joined + (portRef Y (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef un14_cntlto31_0_o3_RNI33E32)) + )) + (net un14_cntlto31_0_a2_0 (joined + (portRef Y (instanceRef un14_cntlto31_0_a2)) + (portRef C (instanceRef un7_cntlto31_0_0)) + (portRef D (instanceRef un14_cntlto31_0_o3_RNI33E32)) + )) + (net (rename cnt_cry_0 "cnt_cry[0]") (joined + (portRef FCO (instanceRef cnt_RNI24MJ4_0)) + (portRef FCI (instanceRef cnt_RNI26U37_1)) + )) + (net (rename cnt_cry_1 "cnt_cry[1]") (joined + (portRef FCO (instanceRef cnt_RNI26U37_1)) + (portRef FCI (instanceRef cnt_RNI396K9_2)) + )) + (net (rename cnt_cry_2 "cnt_cry[2]") (joined + (portRef FCO (instanceRef cnt_RNI396K9_2)) + (portRef FCI (instanceRef cnt_RNI5DE4C_3)) + )) + (net (rename cnt_cry_3 "cnt_cry[3]") (joined + (portRef FCO (instanceRef cnt_RNI5DE4C_3)) + (portRef FCI (instanceRef cnt_RNI8IMKE_4)) + )) + (net (rename cnt_cry_4 "cnt_cry[4]") (joined + (portRef FCO (instanceRef cnt_RNI8IMKE_4)) + (portRef FCI (instanceRef cnt_RNICOU4H_5)) + )) + (net (rename cnt_cry_5 "cnt_cry[5]") (joined + (portRef FCO (instanceRef cnt_RNICOU4H_5)) + (portRef FCI (instanceRef cnt_RNIHV6LJ_6)) + )) + (net (rename cnt_cry_6 "cnt_cry[6]") (joined + (portRef FCO (instanceRef cnt_RNIHV6LJ_6)) + (portRef FCI (instanceRef cnt_RNIN7F5M_7)) + )) + (net (rename cnt_cry_7 "cnt_cry[7]") (joined + (portRef FCO (instanceRef cnt_RNIN7F5M_7)) + (portRef FCI (instanceRef cnt_RNIUGNLO_8)) + )) + (net (rename cnt_cry_8 "cnt_cry[8]") (joined + (portRef FCO (instanceRef cnt_RNIUGNLO_8)) + (portRef FCI (instanceRef cnt_RNI6RV5R_9)) + )) + (net (rename cnt_cry_9 "cnt_cry[9]") (joined + (portRef FCO (instanceRef cnt_RNI6RV5R_9)) + (portRef FCI (instanceRef cnt_RNIME5GT_10)) + )) + (net (rename cnt_cry_10 "cnt_cry[10]") (joined + (portRef FCO (instanceRef cnt_RNIME5GT_10)) + (portRef FCI (instanceRef cnt_RNI73BQV_11)) + )) + (net (rename cnt_cry_11 "cnt_cry[11]") (joined + (portRef FCO (instanceRef cnt_RNI73BQV_11)) + (portRef FCI (instanceRef cnt_RNIPOG421_12)) + )) + (net (rename cnt_cry_12 "cnt_cry[12]") (joined + (portRef FCO (instanceRef cnt_RNIPOG421_12)) + (portRef FCI (instanceRef cnt_RNICFME41_13)) + )) + (net (rename cnt_cry_13 "cnt_cry[13]") (joined + (portRef FCO (instanceRef cnt_RNICFME41_13)) + (portRef FCI (instanceRef cnt_RNI07SO61_14)) + )) + (net (rename cnt_cry_14 "cnt_cry[14]") (joined + (portRef FCO (instanceRef cnt_RNI07SO61_14)) + (portRef FCI (instanceRef cnt_RNILV1391_15)) + )) + (net (rename cnt_cry_15 "cnt_cry[15]") (joined + (portRef FCO (instanceRef cnt_RNILV1391_15)) + (portRef FCI (instanceRef cnt_RNIBP7DB1_16)) + )) + (net (rename cnt_cry_16 "cnt_cry[16]") (joined + (portRef FCO (instanceRef cnt_RNIBP7DB1_16)) + (portRef FCI (instanceRef cnt_RNI2KDND1_17)) + )) + (net (rename cnt_cry_17 "cnt_cry[17]") (joined + (portRef FCO (instanceRef cnt_RNI2KDND1_17)) + (portRef FCI (instanceRef cnt_RNIQFJ1G1_18)) + )) + (net (rename cnt_cry_18 "cnt_cry[18]") (joined + (portRef FCO (instanceRef cnt_RNIQFJ1G1_18)) + (portRef FCI (instanceRef cnt_RNIJCPBI1_19)) + )) + (net (rename cnt_cry_19 "cnt_cry[19]") (joined + (portRef FCO (instanceRef cnt_RNIJCPBI1_19)) + (portRef FCI (instanceRef cnt_RNI420MK1_20)) + )) + (net (rename cnt_cry_20 "cnt_cry[20]") (joined + (portRef FCO (instanceRef cnt_RNI420MK1_20)) + (portRef FCI (instanceRef cnt_RNIMO60N1_21)) + )) + (net (rename cnt_cry_21 "cnt_cry[21]") (joined + (portRef FCO (instanceRef cnt_RNIMO60N1_21)) + (portRef FCI (instanceRef cnt_RNI9GDAP1_22)) + )) + (net (rename cnt_cry_22 "cnt_cry[22]") (joined + (portRef FCO (instanceRef cnt_RNI9GDAP1_22)) + (portRef FCI (instanceRef cnt_RNIT8KKR1_23)) + )) + (net (rename cnt_cry_23 "cnt_cry[23]") (joined + (portRef FCO (instanceRef cnt_RNIT8KKR1_23)) + (portRef FCI (instanceRef cnt_RNII2RUT1_24)) + )) + (net un14_cntlto31_0_o2_3_0 (joined + (portRef Y (instanceRef un14_cntlto31_0_o2_3)) + (portRef B (instanceRef un14_cntlto31_0_o3)) + (portRef B (instanceRef un14_cntlto31_0_a2)) + )) + (net un14_cntlto31_0_o2_0_0 (joined + (portRef Y (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef un7_cntlto31_0_a2_0)) + (portRef C (instanceRef un14_cntlto31_0_o3_0)) + )) + (net N_59_3 (joined + (portRef Y (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef D (instanceRef un14_cntlto31_0_o3_0)) + (portRef A (instanceRef un7_cntlto31_0_a2_1)) + )) + (net un7_cntlto31_0_a2_1_0 (joined + (portRef Y (instanceRef un7_cntlto31_0_a2_1)) + (portRef D (instanceRef un7_cntlto31_0_a2_0)) + )) + (net un14_cntlto31_0_o3_0_0 (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef un14_cntlto31_0_o3_0_RNI3K631)) + )) + (net un7_cntlto31_0_a2_0_0 (joined + (portRef Y (instanceRef un7_cntlto31_0_a2_0)) + (portRef C (instanceRef un7_cntlto31_0_a2)) + )) + (net un7_cntlto31_0_a2_2 (joined + (portRef Y (instanceRef un7_cntlto31_0_a2)) + (portRef B (instanceRef un7_cntlto31_0_a3)) + )) + (net un7_cntlto31_0_a3_0 (joined + (portRef Y (instanceRef un7_cntlto31_0_a3)) + (portRef D (instanceRef un7_cntlto31_0_0)) + )) + ) + (property orig_inst_of (string "ClkGen")) + ) + ) + (cell ClkGenNoSwitch (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port led0 (direction OUTPUT)) + (port reset (direction INPUT)) + (port clk_c (direction INPUT)) + ) + (contents + (instance tmp_clk (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_0 "cnt[0]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_1 "cnt[1]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_2 "cnt[2]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_3 "cnt[3]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_4 "cnt[4]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_5 "cnt[5]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_6 "cnt[6]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_7 "cnt[7]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_8 "cnt[8]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_9 "cnt[9]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_10 "cnt[10]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_11 "cnt[11]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_12 "cnt[12]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_13 "cnt[13]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_14 "cnt[14]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_15 "cnt[15]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_16 "cnt[16]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_17 "cnt[17]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_18 "cnt[18]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_19 "cnt[19]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_20 "cnt[20]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_21 "cnt[21]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_22 "cnt[22]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_23 "cnt[23]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_24 "cnt[24]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_25 "cnt[25]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance (rename cnt_26 "cnt[26]") (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance un14_cntlto31_0_o3_RNINP5T1 (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "4CE0A")) + ) + (instance (rename cnt_RNIQAR44_0 "cnt_RNIQAR44[0]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIUSGC6_1 "cnt_RNIUSGC6[1]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI3G6K8_2 "cnt_RNI3G6K8[2]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI94SRA_3 "cnt_RNI94SRA[3]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIGPH3D_4 "cnt_RNIGPH3D[4]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIOF7BF_5 "cnt_RNIOF7BF[5]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI17TIH_6 "cnt_RNI17TIH[6]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIBVIQJ_7 "cnt_RNIBVIQJ[7]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIMO82M_8 "cnt_RNIMO82M[8]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI2JU9O_9 "cnt_RNI2JU9O[9]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIM6BHQ_10 "cnt_RNIM6BHQ[10]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIBRNOS_11 "cnt_RNIBRNOS[11]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI1H40V_12 "cnt_RNI1H40V[12]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIO7H711_13 "cnt_RNIO7H711[13]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIGVTE31_14 "cnt_RNIGVTE31[14]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI9OAM51_15 "cnt_RNI9OAM51[15]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI3INT71_16 "cnt_RNI3INT71[16]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIUC45A1_17 "cnt_RNIUC45A1[17]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIQ8HCC1_18 "cnt_RNIQ8HCC1[18]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIN5UJE1_19 "cnt_RNIN5UJE1[19]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNICRBRG1_20 "cnt_RNICRBRG1[20]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI2IP2J1_21 "cnt_RNI2IP2J1[21]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIP97AL1_22 "cnt_RNIP97AL1[22]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIH2LHN1_23 "cnt_RNIH2LHN1[23]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNIAS2PP1_24 "cnt_RNIAS2PP1[24]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance (rename cnt_RNI4NG0S1_25 "cnt_RNI4NG0S1[25]") (viewRef PRIM (cellRef ARI1 (libraryRef ACG4))) + (property INIT (string "48800")) + ) + (instance un14_cntlto31_0_a2 (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "45")) + ) + (instance un14_cntlto31_0_o2_0 (viewRef PRIM (cellRef CFG3 (libraryRef ACG4))) + (property INIT (string "7F")) + ) + (instance un14_cntlto31_0_o2_3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "7FFF")) + ) + (instance un14_cntlto31_0_a2_1_3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0001")) + ) + (instance un7_cntlto31_0_a2_1 (viewRef PRIM (cellRef CFG2 (libraryRef ACG4))) + (property INIT (string "2")) + ) + (instance un14_cntlto31_0_o3_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "FF73")) + ) + (instance un14_cntlto31_0_o3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0FDF")) + ) + (instance un7_cntlto31_0_a2_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "3331")) + ) + (instance un14_cntlto31_0_o3_0_RNI6DVC1 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0073")) + ) + (instance un7_cntlto31_0_a2 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "0031")) + ) + (instance un7_cntlto31_0_a3 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "1011")) + ) + (instance un7_cntlto31_0 (viewRef PRIM (cellRef CFG4 (libraryRef ACG4))) + (property INIT (string "FF10")) + ) + (instance GND (viewRef PRIM (cellRef GND (libraryRef ACG4))) ) + (instance VCC (viewRef PRIM (cellRef VCC (libraryRef ACG4))) ) + (net led0 (joined + (portRef Q (instanceRef tmp_clk)) + (portRef led0) + )) + (net (rename VCCZ0 "VCC") (joined + (portRef Y (instanceRef VCC)) + (portRef A (instanceRef cnt_RNI4NG0S1_25)) + (portRef A (instanceRef cnt_RNIAS2PP1_24)) + (portRef A (instanceRef cnt_RNIH2LHN1_23)) + (portRef A (instanceRef cnt_RNIP97AL1_22)) + (portRef A (instanceRef cnt_RNI2IP2J1_21)) + (portRef A (instanceRef cnt_RNICRBRG1_20)) + (portRef A (instanceRef cnt_RNIN5UJE1_19)) + (portRef A (instanceRef cnt_RNIQ8HCC1_18)) + (portRef A (instanceRef cnt_RNIUC45A1_17)) + (portRef A (instanceRef cnt_RNI3INT71_16)) + (portRef A (instanceRef cnt_RNI9OAM51_15)) + (portRef A (instanceRef cnt_RNIGVTE31_14)) + (portRef A (instanceRef cnt_RNIO7H711_13)) + (portRef A (instanceRef cnt_RNI1H40V_12)) + (portRef A (instanceRef cnt_RNIBRNOS_11)) + (portRef A (instanceRef cnt_RNIM6BHQ_10)) + (portRef A (instanceRef cnt_RNI2JU9O_9)) + (portRef A (instanceRef cnt_RNIMO82M_8)) + (portRef A (instanceRef cnt_RNIBVIQJ_7)) + (portRef A (instanceRef cnt_RNI17TIH_6)) + (portRef A (instanceRef cnt_RNIOF7BF_5)) + (portRef A (instanceRef cnt_RNIGPH3D_4)) + (portRef A (instanceRef cnt_RNI94SRA_3)) + (portRef A (instanceRef cnt_RNI3G6K8_2)) + (portRef A (instanceRef cnt_RNIUSGC6_1)) + (portRef A (instanceRef cnt_RNIQAR44_0)) + (portRef FCI (instanceRef un14_cntlto31_0_o3_RNINP5T1)) + (portRef SLn (instanceRef cnt_26)) + (portRef EN (instanceRef cnt_26)) + (portRef ADn (instanceRef cnt_26)) + (portRef SLn (instanceRef cnt_25)) + (portRef EN (instanceRef cnt_25)) + (portRef ADn (instanceRef cnt_25)) + (portRef SLn (instanceRef cnt_24)) + (portRef EN (instanceRef cnt_24)) + (portRef ADn (instanceRef cnt_24)) + (portRef SLn (instanceRef cnt_23)) + (portRef EN (instanceRef cnt_23)) + (portRef ADn (instanceRef cnt_23)) + (portRef SLn (instanceRef cnt_22)) + (portRef EN (instanceRef cnt_22)) + (portRef ADn (instanceRef cnt_22)) + (portRef SLn (instanceRef cnt_21)) + (portRef EN (instanceRef cnt_21)) + (portRef ADn (instanceRef cnt_21)) + (portRef SLn (instanceRef cnt_20)) + (portRef EN (instanceRef cnt_20)) + (portRef ADn (instanceRef cnt_20)) + (portRef SLn (instanceRef cnt_19)) + (portRef EN (instanceRef cnt_19)) + (portRef ADn (instanceRef cnt_19)) + (portRef SLn (instanceRef cnt_18)) + (portRef EN (instanceRef cnt_18)) + (portRef ADn (instanceRef cnt_18)) + (portRef SLn (instanceRef cnt_17)) + (portRef EN (instanceRef cnt_17)) + (portRef ADn (instanceRef cnt_17)) + (portRef SLn (instanceRef cnt_16)) + (portRef EN (instanceRef cnt_16)) + (portRef ADn (instanceRef cnt_16)) + (portRef SLn (instanceRef cnt_15)) + (portRef EN (instanceRef cnt_15)) + (portRef ADn (instanceRef cnt_15)) + (portRef SLn (instanceRef cnt_14)) + (portRef EN (instanceRef cnt_14)) + (portRef ADn (instanceRef cnt_14)) + (portRef SLn (instanceRef cnt_13)) + (portRef EN (instanceRef cnt_13)) + (portRef ADn (instanceRef cnt_13)) + (portRef SLn (instanceRef cnt_12)) + (portRef EN (instanceRef cnt_12)) + (portRef ADn (instanceRef cnt_12)) + (portRef SLn (instanceRef cnt_11)) + (portRef EN (instanceRef cnt_11)) + (portRef ADn (instanceRef cnt_11)) + (portRef SLn (instanceRef cnt_10)) + (portRef EN (instanceRef cnt_10)) + (portRef ADn (instanceRef cnt_10)) + (portRef SLn (instanceRef cnt_9)) + (portRef EN (instanceRef cnt_9)) + (portRef ADn (instanceRef cnt_9)) + (portRef SLn (instanceRef cnt_8)) + (portRef EN (instanceRef cnt_8)) + (portRef ADn (instanceRef cnt_8)) + (portRef SLn (instanceRef cnt_7)) + (portRef EN (instanceRef cnt_7)) + (portRef ADn (instanceRef cnt_7)) + (portRef SLn (instanceRef cnt_6)) + (portRef EN (instanceRef cnt_6)) + (portRef ADn (instanceRef cnt_6)) + (portRef SLn (instanceRef cnt_5)) + (portRef EN (instanceRef cnt_5)) + (portRef ADn (instanceRef cnt_5)) + (portRef SLn (instanceRef cnt_4)) + (portRef EN (instanceRef cnt_4)) + (portRef ADn (instanceRef cnt_4)) + (portRef SLn (instanceRef cnt_3)) + (portRef EN (instanceRef cnt_3)) + (portRef ADn (instanceRef cnt_3)) + (portRef SLn (instanceRef cnt_2)) + (portRef EN (instanceRef cnt_2)) + (portRef ADn (instanceRef cnt_2)) + (portRef SLn (instanceRef cnt_1)) + (portRef EN (instanceRef cnt_1)) + (portRef ADn (instanceRef cnt_1)) + (portRef SLn (instanceRef cnt_0)) + (portRef EN (instanceRef cnt_0)) + (portRef ADn (instanceRef cnt_0)) + (portRef SLn (instanceRef tmp_clk)) + (portRef EN (instanceRef tmp_clk)) + (portRef ADn (instanceRef tmp_clk)) + )) + (net reset (joined + (portRef reset) + (portRef ALn (instanceRef cnt_26)) + (portRef ALn (instanceRef cnt_25)) + (portRef ALn (instanceRef cnt_24)) + (portRef ALn (instanceRef cnt_23)) + (portRef ALn (instanceRef cnt_22)) + (portRef ALn (instanceRef cnt_21)) + (portRef ALn (instanceRef cnt_20)) + (portRef ALn (instanceRef cnt_19)) + (portRef ALn (instanceRef cnt_18)) + (portRef ALn (instanceRef cnt_17)) + (portRef ALn (instanceRef cnt_16)) + (portRef ALn (instanceRef cnt_15)) + (portRef ALn (instanceRef cnt_14)) + (portRef ALn (instanceRef cnt_13)) + (portRef ALn (instanceRef cnt_12)) + (portRef ALn (instanceRef cnt_11)) + (portRef ALn (instanceRef cnt_10)) + (portRef ALn (instanceRef cnt_9)) + (portRef ALn (instanceRef cnt_8)) + (portRef ALn (instanceRef cnt_7)) + (portRef ALn (instanceRef cnt_6)) + (portRef ALn (instanceRef cnt_5)) + (portRef ALn (instanceRef cnt_4)) + (portRef ALn (instanceRef cnt_3)) + (portRef ALn (instanceRef cnt_2)) + (portRef ALn (instanceRef cnt_1)) + (portRef ALn (instanceRef cnt_0)) + (portRef ALn (instanceRef tmp_clk)) + )) + (net clk_c (joined + (portRef clk_c) + (portRef CLK (instanceRef cnt_26)) + (portRef CLK (instanceRef cnt_25)) + (portRef CLK (instanceRef cnt_24)) + (portRef CLK (instanceRef cnt_23)) + (portRef CLK (instanceRef cnt_22)) + (portRef CLK (instanceRef cnt_21)) + (portRef CLK (instanceRef cnt_20)) + (portRef CLK (instanceRef cnt_19)) + (portRef CLK (instanceRef cnt_18)) + (portRef CLK (instanceRef cnt_17)) + (portRef CLK (instanceRef cnt_16)) + (portRef CLK (instanceRef cnt_15)) + (portRef CLK (instanceRef cnt_14)) + (portRef CLK (instanceRef cnt_13)) + (portRef CLK (instanceRef cnt_12)) + (portRef CLK (instanceRef cnt_11)) + (portRef CLK (instanceRef cnt_10)) + (portRef CLK (instanceRef cnt_9)) + (portRef CLK (instanceRef cnt_8)) + (portRef CLK (instanceRef cnt_7)) + (portRef CLK (instanceRef cnt_6)) + (portRef CLK (instanceRef cnt_5)) + (portRef CLK (instanceRef cnt_4)) + (portRef CLK (instanceRef cnt_3)) + (portRef CLK (instanceRef cnt_2)) + (portRef CLK (instanceRef cnt_1)) + (portRef CLK (instanceRef cnt_0)) + (portRef CLK (instanceRef tmp_clk)) + )) + (net (rename un7_cntlto31Z0Z_0 "un7_cntlto31_0") (joined + (portRef Y (instanceRef un7_cntlto31_0)) + (portRef D (instanceRef tmp_clk)) + )) + (net (rename GNDZ0 "GND") (joined + (portRef Y (instanceRef GND)) + (portRef D (instanceRef cnt_RNI4NG0S1_25)) + (portRef D (instanceRef cnt_RNIAS2PP1_24)) + (portRef D (instanceRef cnt_RNIH2LHN1_23)) + (portRef D (instanceRef cnt_RNIP97AL1_22)) + (portRef D (instanceRef cnt_RNI2IP2J1_21)) + (portRef D (instanceRef cnt_RNICRBRG1_20)) + (portRef D (instanceRef cnt_RNIN5UJE1_19)) + (portRef D (instanceRef cnt_RNIQ8HCC1_18)) + (portRef D (instanceRef cnt_RNIUC45A1_17)) + (portRef D (instanceRef cnt_RNI3INT71_16)) + (portRef D (instanceRef cnt_RNI9OAM51_15)) + (portRef D (instanceRef cnt_RNIGVTE31_14)) + (portRef D (instanceRef cnt_RNIO7H711_13)) + (portRef D (instanceRef cnt_RNI1H40V_12)) + (portRef D (instanceRef cnt_RNIBRNOS_11)) + (portRef D (instanceRef cnt_RNIM6BHQ_10)) + (portRef D (instanceRef cnt_RNI2JU9O_9)) + (portRef D (instanceRef cnt_RNIMO82M_8)) + (portRef D (instanceRef cnt_RNIBVIQJ_7)) + (portRef D (instanceRef cnt_RNI17TIH_6)) + (portRef D (instanceRef cnt_RNIOF7BF_5)) + (portRef D (instanceRef cnt_RNIGPH3D_4)) + (portRef D (instanceRef cnt_RNI94SRA_3)) + (portRef D (instanceRef cnt_RNI3G6K8_2)) + (portRef D (instanceRef cnt_RNIUSGC6_1)) + (portRef D (instanceRef cnt_RNIQAR44_0)) + (portRef SD (instanceRef cnt_26)) + (portRef LAT (instanceRef cnt_26)) + (portRef SD (instanceRef cnt_25)) + (portRef LAT (instanceRef cnt_25)) + (portRef SD (instanceRef cnt_24)) + (portRef LAT (instanceRef cnt_24)) + (portRef SD (instanceRef cnt_23)) + (portRef LAT (instanceRef cnt_23)) + (portRef SD (instanceRef cnt_22)) + (portRef LAT (instanceRef cnt_22)) + (portRef SD (instanceRef cnt_21)) + (portRef LAT (instanceRef cnt_21)) + (portRef SD (instanceRef cnt_20)) + (portRef LAT (instanceRef cnt_20)) + (portRef SD (instanceRef cnt_19)) + (portRef LAT (instanceRef cnt_19)) + (portRef SD (instanceRef cnt_18)) + (portRef LAT (instanceRef cnt_18)) + (portRef SD (instanceRef cnt_17)) + (portRef LAT (instanceRef cnt_17)) + (portRef SD (instanceRef cnt_16)) + (portRef LAT (instanceRef cnt_16)) + (portRef SD (instanceRef cnt_15)) + (portRef LAT (instanceRef cnt_15)) + (portRef SD (instanceRef cnt_14)) + (portRef LAT (instanceRef cnt_14)) + (portRef SD (instanceRef cnt_13)) + (portRef LAT (instanceRef cnt_13)) + (portRef SD (instanceRef cnt_12)) + (portRef LAT (instanceRef cnt_12)) + (portRef SD (instanceRef cnt_11)) + (portRef LAT (instanceRef cnt_11)) + (portRef SD (instanceRef cnt_10)) + (portRef LAT (instanceRef cnt_10)) + (portRef SD (instanceRef cnt_9)) + (portRef LAT (instanceRef cnt_9)) + (portRef SD (instanceRef cnt_8)) + (portRef LAT (instanceRef cnt_8)) + (portRef SD (instanceRef cnt_7)) + (portRef LAT (instanceRef cnt_7)) + (portRef SD (instanceRef cnt_6)) + (portRef LAT (instanceRef cnt_6)) + (portRef SD (instanceRef cnt_5)) + (portRef LAT (instanceRef cnt_5)) + (portRef SD (instanceRef cnt_4)) + (portRef LAT (instanceRef cnt_4)) + (portRef SD (instanceRef cnt_3)) + (portRef LAT (instanceRef cnt_3)) + (portRef SD (instanceRef cnt_2)) + (portRef LAT (instanceRef cnt_2)) + (portRef SD (instanceRef cnt_1)) + (portRef LAT (instanceRef cnt_1)) + (portRef SD (instanceRef cnt_0)) + (portRef LAT (instanceRef cnt_0)) + (portRef SD (instanceRef tmp_clk)) + (portRef LAT (instanceRef tmp_clk)) + )) + (net (rename cntZ0Z_0 "cnt[0]") (joined + (portRef Q (instanceRef cnt_0)) + (portRef C (instanceRef cnt_RNIQAR44_0)) + )) + (net (rename cnt_s_0 "cnt_s[0]") (joined + (portRef S (instanceRef cnt_RNIQAR44_0)) + (portRef D (instanceRef cnt_0)) + )) + (net (rename cntZ0Z_1 "cnt[1]") (joined + (portRef Q (instanceRef cnt_1)) + (portRef C (instanceRef cnt_RNIUSGC6_1)) + )) + (net (rename cnt_s_1 "cnt_s[1]") (joined + (portRef S (instanceRef cnt_RNIUSGC6_1)) + (portRef D (instanceRef cnt_1)) + )) + (net (rename cntZ0Z_2 "cnt[2]") (joined + (portRef Q (instanceRef cnt_2)) + (portRef C (instanceRef cnt_RNI3G6K8_2)) + )) + (net (rename cnt_s_2 "cnt_s[2]") (joined + (portRef S (instanceRef cnt_RNI3G6K8_2)) + (portRef D (instanceRef cnt_2)) + )) + (net (rename cntZ0Z_3 "cnt[3]") (joined + (portRef Q (instanceRef cnt_3)) + (portRef C (instanceRef cnt_RNI94SRA_3)) + )) + (net (rename cnt_s_3 "cnt_s[3]") (joined + (portRef S (instanceRef cnt_RNI94SRA_3)) + (portRef D (instanceRef cnt_3)) + )) + (net (rename cntZ0Z_4 "cnt[4]") (joined + (portRef Q (instanceRef cnt_4)) + (portRef C (instanceRef cnt_RNIGPH3D_4)) + )) + (net (rename cnt_s_4 "cnt_s[4]") (joined + (portRef S (instanceRef cnt_RNIGPH3D_4)) + (portRef D (instanceRef cnt_4)) + )) + (net (rename cntZ0Z_5 "cnt[5]") (joined + (portRef Q (instanceRef cnt_5)) + (portRef C (instanceRef cnt_RNIOF7BF_5)) + )) + (net (rename cnt_s_5 "cnt_s[5]") (joined + (portRef S (instanceRef cnt_RNIOF7BF_5)) + (portRef D (instanceRef cnt_5)) + )) + (net (rename cntZ0Z_6 "cnt[6]") (joined + (portRef Q (instanceRef cnt_6)) + (portRef B (instanceRef un7_cntlto31_0_a2_1)) + (portRef C (instanceRef cnt_RNI17TIH_6)) + )) + (net (rename cnt_s_6 "cnt_s[6]") (joined + (portRef S (instanceRef cnt_RNI17TIH_6)) + (portRef D (instanceRef cnt_6)) + )) + (net (rename cntZ0Z_7 "cnt[7]") (joined + (portRef Q (instanceRef cnt_7)) + (portRef D (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNIBVIQJ_7)) + )) + (net (rename cnt_s_7 "cnt_s[7]") (joined + (portRef S (instanceRef cnt_RNIBVIQJ_7)) + (portRef D (instanceRef cnt_7)) + )) + (net (rename cntZ0Z_8 "cnt[8]") (joined + (portRef Q (instanceRef cnt_8)) + (portRef C (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNIMO82M_8)) + )) + (net (rename cnt_s_8 "cnt_s[8]") (joined + (portRef S (instanceRef cnt_RNIMO82M_8)) + (portRef D (instanceRef cnt_8)) + )) + (net (rename cntZ0Z_9 "cnt[9]") (joined + (portRef Q (instanceRef cnt_9)) + (portRef B (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNI2JU9O_9)) + )) + (net (rename cnt_s_9 "cnt_s[9]") (joined + (portRef S (instanceRef cnt_RNI2JU9O_9)) + (portRef D (instanceRef cnt_9)) + )) + (net (rename cntZ0Z_10 "cnt[10]") (joined + (portRef Q (instanceRef cnt_10)) + (portRef A (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef cnt_RNIM6BHQ_10)) + )) + (net (rename cnt_s_10 "cnt_s[10]") (joined + (portRef S (instanceRef cnt_RNIM6BHQ_10)) + (portRef D (instanceRef cnt_10)) + )) + (net (rename cntZ0Z_11 "cnt[11]") (joined + (portRef Q (instanceRef cnt_11)) + (portRef A (instanceRef un7_cntlto31_0_a2_0)) + (portRef A (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef cnt_RNIBRNOS_11)) + )) + (net (rename cnt_s_11 "cnt_s[11]") (joined + (portRef S (instanceRef cnt_RNIBRNOS_11)) + (portRef D (instanceRef cnt_11)) + )) + (net (rename cntZ0Z_12 "cnt[12]") (joined + (portRef Q (instanceRef cnt_12)) + (portRef C (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNI1H40V_12)) + )) + (net (rename cnt_s_12 "cnt_s[12]") (joined + (portRef S (instanceRef cnt_RNI1H40V_12)) + (portRef D (instanceRef cnt_12)) + )) + (net (rename cntZ0Z_13 "cnt[13]") (joined + (portRef Q (instanceRef cnt_13)) + (portRef B (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNIO7H711_13)) + )) + (net (rename cnt_s_13 "cnt_s[13]") (joined + (portRef S (instanceRef cnt_RNIO7H711_13)) + (portRef D (instanceRef cnt_13)) + )) + (net (rename cntZ0Z_14 "cnt[14]") (joined + (portRef Q (instanceRef cnt_14)) + (portRef A (instanceRef un14_cntlto31_0_o2_0)) + (portRef C (instanceRef cnt_RNIGVTE31_14)) + )) + (net (rename cnt_s_14 "cnt_s[14]") (joined + (portRef S (instanceRef cnt_RNIGVTE31_14)) + (portRef D (instanceRef cnt_14)) + )) + (net (rename cntZ0Z_15 "cnt[15]") (joined + (portRef Q (instanceRef cnt_15)) + (portRef B (instanceRef un7_cntlto31_0_a2_0)) + (portRef B (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef cnt_RNI9OAM51_15)) + )) + (net (rename cnt_s_15 "cnt_s[15]") (joined + (portRef S (instanceRef cnt_RNI9OAM51_15)) + (portRef D (instanceRef cnt_15)) + )) + (net (rename cntZ0Z_16 "cnt[16]") (joined + (portRef Q (instanceRef cnt_16)) + (portRef A (instanceRef un7_cntlto31_0_a2)) + (portRef A (instanceRef un14_cntlto31_0_o3_0_RNI6DVC1)) + (portRef C (instanceRef cnt_RNI3INT71_16)) + )) + (net (rename cnt_s_16 "cnt_s[16]") (joined + (portRef S (instanceRef cnt_RNI3INT71_16)) + (portRef D (instanceRef cnt_16)) + )) + (net (rename cntZ0Z_17 "cnt[17]") (joined + (portRef Q (instanceRef cnt_17)) + (portRef B (instanceRef un7_cntlto31_0_a2)) + (portRef B (instanceRef un14_cntlto31_0_o3_0_RNI6DVC1)) + (portRef C (instanceRef cnt_RNIUC45A1_17)) + )) + (net (rename cnt_s_17 "cnt_s[17]") (joined + (portRef S (instanceRef cnt_RNIUC45A1_17)) + (portRef D (instanceRef cnt_17)) + )) + (net (rename cntZ0Z_18 "cnt[18]") (joined + (portRef Q (instanceRef cnt_18)) + (portRef C (instanceRef un14_cntlto31_0_a2)) + (portRef C (instanceRef cnt_RNIQ8HCC1_18)) + )) + (net (rename cnt_s_18 "cnt_s[18]") (joined + (portRef S (instanceRef cnt_RNIQ8HCC1_18)) + (portRef D (instanceRef cnt_18)) + )) + (net (rename cntZ0Z_19 "cnt[19]") (joined + (portRef Q (instanceRef cnt_19)) + (portRef D (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNIN5UJE1_19)) + )) + (net (rename cnt_s_19 "cnt_s[19]") (joined + (portRef S (instanceRef cnt_RNIN5UJE1_19)) + (portRef D (instanceRef cnt_19)) + )) + (net (rename cntZ0Z_20 "cnt[20]") (joined + (portRef Q (instanceRef cnt_20)) + (portRef C (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNICRBRG1_20)) + )) + (net (rename cnt_s_20 "cnt_s[20]") (joined + (portRef S (instanceRef cnt_RNICRBRG1_20)) + (portRef D (instanceRef cnt_20)) + )) + (net (rename cntZ0Z_21 "cnt[21]") (joined + (portRef Q (instanceRef cnt_21)) + (portRef B (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNI2IP2J1_21)) + )) + (net (rename cnt_s_21 "cnt_s[21]") (joined + (portRef S (instanceRef cnt_RNI2IP2J1_21)) + (portRef D (instanceRef cnt_21)) + )) + (net (rename cntZ0Z_22 "cnt[22]") (joined + (portRef Q (instanceRef cnt_22)) + (portRef A (instanceRef un14_cntlto31_0_o2_3)) + (portRef C (instanceRef cnt_RNIP97AL1_22)) + )) + (net (rename cnt_s_22 "cnt_s[22]") (joined + (portRef S (instanceRef cnt_RNIP97AL1_22)) + (portRef D (instanceRef cnt_22)) + )) + (net (rename cntZ0Z_23 "cnt[23]") (joined + (portRef Q (instanceRef cnt_23)) + (portRef B (instanceRef un7_cntlto31_0)) + (portRef D (instanceRef un7_cntlto31_0_a2)) + (portRef A (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNIH2LHN1_23)) + )) + (net (rename cnt_s_23 "cnt_s[23]") (joined + (portRef S (instanceRef cnt_RNIH2LHN1_23)) + (portRef D (instanceRef cnt_23)) + )) + (net (rename cntZ0Z_24 "cnt[24]") (joined + (portRef Q (instanceRef cnt_24)) + (portRef D (instanceRef un7_cntlto31_0_a3)) + (portRef D (instanceRef un14_cntlto31_0_o3_0_RNI6DVC1)) + (portRef D (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNIAS2PP1_24)) + )) + (net (rename cnt_s_24 "cnt_s[24]") (joined + (portRef S (instanceRef cnt_RNIAS2PP1_24)) + (portRef D (instanceRef cnt_24)) + )) + (net (rename cntZ0Z_25 "cnt[25]") (joined + (portRef Q (instanceRef cnt_25)) + (portRef A (instanceRef un7_cntlto31_0)) + (portRef A (instanceRef un7_cntlto31_0_a3)) + (portRef C (instanceRef un14_cntlto31_0_o3)) + (portRef C (instanceRef cnt_RNI4NG0S1_25)) + )) + (net (rename cnt_s_25 "cnt_s[25]") (joined + (portRef S (instanceRef cnt_RNI4NG0S1_25)) + (portRef D (instanceRef cnt_25)) + )) + (net N_39 (joined + (portRef Q (instanceRef cnt_26)) + (portRef B (instanceRef un7_cntlto31_0_a3)) + (portRef A (instanceRef un14_cntlto31_0_a2)) + (portRef D (instanceRef un14_cntlto31_0_o3_RNINP5T1)) + )) + (net (rename cnt_s_26 "cnt_s[26]") (joined + (portRef FCO (instanceRef cnt_RNI4NG0S1_25)) + (portRef D (instanceRef cnt_26)) + )) + (net cnt_cry_cy (joined + (portRef FCO (instanceRef un14_cntlto31_0_o3_RNINP5T1)) + (portRef FCI (instanceRef cnt_RNIQAR44_0)) + )) + (net un14_cntlto31_0_o3_RNINP5T1_Y (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_RNINP5T1)) + (portRef B (instanceRef cnt_RNI4NG0S1_25)) + (portRef B (instanceRef cnt_RNIAS2PP1_24)) + (portRef B (instanceRef cnt_RNIH2LHN1_23)) + (portRef B (instanceRef cnt_RNIP97AL1_22)) + (portRef B (instanceRef cnt_RNI2IP2J1_21)) + (portRef B (instanceRef cnt_RNICRBRG1_20)) + (portRef B (instanceRef cnt_RNIN5UJE1_19)) + (portRef B (instanceRef cnt_RNIQ8HCC1_18)) + (portRef B (instanceRef cnt_RNIUC45A1_17)) + (portRef B (instanceRef cnt_RNI3INT71_16)) + (portRef B (instanceRef cnt_RNI9OAM51_15)) + (portRef B (instanceRef cnt_RNIGVTE31_14)) + (portRef B (instanceRef cnt_RNIO7H711_13)) + (portRef B (instanceRef cnt_RNI1H40V_12)) + (portRef B (instanceRef cnt_RNIBRNOS_11)) + (portRef B (instanceRef cnt_RNIM6BHQ_10)) + (portRef B (instanceRef cnt_RNI2JU9O_9)) + (portRef B (instanceRef cnt_RNIMO82M_8)) + (portRef B (instanceRef cnt_RNIBVIQJ_7)) + (portRef B (instanceRef cnt_RNI17TIH_6)) + (portRef B (instanceRef cnt_RNIOF7BF_5)) + (portRef B (instanceRef cnt_RNIGPH3D_4)) + (portRef B (instanceRef cnt_RNI94SRA_3)) + (portRef B (instanceRef cnt_RNI3G6K8_2)) + (portRef B (instanceRef cnt_RNIUSGC6_1)) + (portRef B (instanceRef cnt_RNIQAR44_0)) + )) + (net N_312_tz (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_0_RNI6DVC1)) + (portRef A (instanceRef un14_cntlto31_0_o3_RNINP5T1)) + )) + (net N_16 (joined + (portRef Y (instanceRef un14_cntlto31_0_o3)) + (portRef B (instanceRef un14_cntlto31_0_o3_RNINP5T1)) + )) + (net N_29 (joined + (portRef Y (instanceRef un14_cntlto31_0_a2)) + (portRef C (instanceRef un7_cntlto31_0)) + (portRef C (instanceRef un14_cntlto31_0_o3_RNINP5T1)) + )) + (net (rename cnt_cry_0 "cnt_cry[0]") (joined + (portRef FCO (instanceRef cnt_RNIQAR44_0)) + (portRef FCI (instanceRef cnt_RNIUSGC6_1)) + )) + (net (rename cnt_cry_1 "cnt_cry[1]") (joined + (portRef FCO (instanceRef cnt_RNIUSGC6_1)) + (portRef FCI (instanceRef cnt_RNI3G6K8_2)) + )) + (net (rename cnt_cry_2 "cnt_cry[2]") (joined + (portRef FCO (instanceRef cnt_RNI3G6K8_2)) + (portRef FCI (instanceRef cnt_RNI94SRA_3)) + )) + (net (rename cnt_cry_3 "cnt_cry[3]") (joined + (portRef FCO (instanceRef cnt_RNI94SRA_3)) + (portRef FCI (instanceRef cnt_RNIGPH3D_4)) + )) + (net (rename cnt_cry_4 "cnt_cry[4]") (joined + (portRef FCO (instanceRef cnt_RNIGPH3D_4)) + (portRef FCI (instanceRef cnt_RNIOF7BF_5)) + )) + (net (rename cnt_cry_5 "cnt_cry[5]") (joined + (portRef FCO (instanceRef cnt_RNIOF7BF_5)) + (portRef FCI (instanceRef cnt_RNI17TIH_6)) + )) + (net (rename cnt_cry_6 "cnt_cry[6]") (joined + (portRef FCO (instanceRef cnt_RNI17TIH_6)) + (portRef FCI (instanceRef cnt_RNIBVIQJ_7)) + )) + (net (rename cnt_cry_7 "cnt_cry[7]") (joined + (portRef FCO (instanceRef cnt_RNIBVIQJ_7)) + (portRef FCI (instanceRef cnt_RNIMO82M_8)) + )) + (net (rename cnt_cry_8 "cnt_cry[8]") (joined + (portRef FCO (instanceRef cnt_RNIMO82M_8)) + (portRef FCI (instanceRef cnt_RNI2JU9O_9)) + )) + (net (rename cnt_cry_9 "cnt_cry[9]") (joined + (portRef FCO (instanceRef cnt_RNI2JU9O_9)) + (portRef FCI (instanceRef cnt_RNIM6BHQ_10)) + )) + (net (rename cnt_cry_10 "cnt_cry[10]") (joined + (portRef FCO (instanceRef cnt_RNIM6BHQ_10)) + (portRef FCI (instanceRef cnt_RNIBRNOS_11)) + )) + (net (rename cnt_cry_11 "cnt_cry[11]") (joined + (portRef FCO (instanceRef cnt_RNIBRNOS_11)) + (portRef FCI (instanceRef cnt_RNI1H40V_12)) + )) + (net (rename cnt_cry_12 "cnt_cry[12]") (joined + (portRef FCO (instanceRef cnt_RNI1H40V_12)) + (portRef FCI (instanceRef cnt_RNIO7H711_13)) + )) + (net (rename cnt_cry_13 "cnt_cry[13]") (joined + (portRef FCO (instanceRef cnt_RNIO7H711_13)) + (portRef FCI (instanceRef cnt_RNIGVTE31_14)) + )) + (net (rename cnt_cry_14 "cnt_cry[14]") (joined + (portRef FCO (instanceRef cnt_RNIGVTE31_14)) + (portRef FCI (instanceRef cnt_RNI9OAM51_15)) + )) + (net (rename cnt_cry_15 "cnt_cry[15]") (joined + (portRef FCO (instanceRef cnt_RNI9OAM51_15)) + (portRef FCI (instanceRef cnt_RNI3INT71_16)) + )) + (net (rename cnt_cry_16 "cnt_cry[16]") (joined + (portRef FCO (instanceRef cnt_RNI3INT71_16)) + (portRef FCI (instanceRef cnt_RNIUC45A1_17)) + )) + (net (rename cnt_cry_17 "cnt_cry[17]") (joined + (portRef FCO (instanceRef cnt_RNIUC45A1_17)) + (portRef FCI (instanceRef cnt_RNIQ8HCC1_18)) + )) + (net (rename cnt_cry_18 "cnt_cry[18]") (joined + (portRef FCO (instanceRef cnt_RNIQ8HCC1_18)) + (portRef FCI (instanceRef cnt_RNIN5UJE1_19)) + )) + (net (rename cnt_cry_19 "cnt_cry[19]") (joined + (portRef FCO (instanceRef cnt_RNIN5UJE1_19)) + (portRef FCI (instanceRef cnt_RNICRBRG1_20)) + )) + (net (rename cnt_cry_20 "cnt_cry[20]") (joined + (portRef FCO (instanceRef cnt_RNICRBRG1_20)) + (portRef FCI (instanceRef cnt_RNI2IP2J1_21)) + )) + (net (rename cnt_cry_21 "cnt_cry[21]") (joined + (portRef FCO (instanceRef cnt_RNI2IP2J1_21)) + (portRef FCI (instanceRef cnt_RNIP97AL1_22)) + )) + (net (rename cnt_cry_22 "cnt_cry[22]") (joined + (portRef FCO (instanceRef cnt_RNIP97AL1_22)) + (portRef FCI (instanceRef cnt_RNIH2LHN1_23)) + )) + (net (rename cnt_cry_23 "cnt_cry[23]") (joined + (portRef FCO (instanceRef cnt_RNIH2LHN1_23)) + (portRef FCI (instanceRef cnt_RNIAS2PP1_24)) + )) + (net (rename cnt_cry_24 "cnt_cry[24]") (joined + (portRef FCO (instanceRef cnt_RNIAS2PP1_24)) + (portRef FCI (instanceRef cnt_RNI4NG0S1_25)) + )) + (net N_9 (joined + (portRef Y (instanceRef un14_cntlto31_0_o2_3)) + (portRef B (instanceRef un14_cntlto31_0_o3)) + (portRef B (instanceRef un14_cntlto31_0_a2)) + )) + (net N_6 (joined + (portRef Y (instanceRef un14_cntlto31_0_o2_0)) + (portRef D (instanceRef un7_cntlto31_0_a2_0)) + (portRef D (instanceRef un14_cntlto31_0_o3_0)) + )) + (net N_30_3 (joined + (portRef Y (instanceRef un14_cntlto31_0_a2_1_3)) + (portRef C (instanceRef un14_cntlto31_0_o3_0)) + (portRef A (instanceRef un7_cntlto31_0_a2_1)) + )) + (net N_30 (joined + (portRef Y (instanceRef un7_cntlto31_0_a2_1)) + (portRef C (instanceRef un7_cntlto31_0_a2_0)) + )) + (net N_18 (joined + (portRef Y (instanceRef un14_cntlto31_0_o3_0)) + (portRef C (instanceRef un14_cntlto31_0_o3_0_RNI6DVC1)) + )) + (net N_31 (joined + (portRef Y (instanceRef un7_cntlto31_0_a2_0)) + (portRef C (instanceRef un7_cntlto31_0_a2)) + )) + (net N_32 (joined + (portRef Y (instanceRef un7_cntlto31_0_a2)) + (portRef C (instanceRef un7_cntlto31_0_a3)) + )) + (net N_27 (joined + (portRef Y (instanceRef un7_cntlto31_0_a3)) + (portRef D (instanceRef un7_cntlto31_0)) + )) + ) + (property orig_inst_of (string "ClkGenNoSwitch")) + ) + ) + (cell Reset_out (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port reset (direction OUTPUT)) + (port clk_c (direction INPUT)) + (port SW1_c (direction INPUT)) + (port SW2_c (direction INPUT)) + ) + (contents + (instance reset_RNIREK (viewRef PRIM (cellRef CLKINT (libraryRef ACG4))) ) + (instance reset (viewRef PRIM (cellRef SLE (libraryRef ACG4))) + ) + (instance reset_RNO (viewRef PRIM (cellRef CFG2 (libraryRef ACG4))) + (property INIT (string "7")) + ) + (instance GND (viewRef PRIM (cellRef GND (libraryRef ACG4))) ) + (instance VCC (viewRef PRIM (cellRef VCC (libraryRef ACG4))) ) + (net (rename resetZ0 "reset") (joined + (portRef Y (instanceRef reset_RNIREK)) + (portRef reset) + )) + (net reset_0 (joined + (portRef Q (instanceRef reset)) + (portRef A (instanceRef reset_RNIREK)) + )) + (net (rename VCCZ0 "VCC") (joined + (portRef Y (instanceRef VCC)) + (portRef SLn (instanceRef reset)) + (portRef EN (instanceRef reset)) + (portRef ALn (instanceRef reset)) + (portRef ADn (instanceRef reset)) + )) + (net clk_c (joined + (portRef clk_c) + (portRef CLK (instanceRef reset)) + )) + (net un2_sw1_i_0 (joined + (portRef Y (instanceRef reset_RNO)) + (portRef D (instanceRef reset)) + )) + (net (rename GNDZ0 "GND") (joined + (portRef Y (instanceRef GND)) + (portRef SD (instanceRef reset)) + (portRef LAT (instanceRef reset)) + )) + (net (rename sw1_c "SW1_c") (joined + (portRef SW1_c) + (portRef A (instanceRef reset_RNO)) + )) + (net (rename sw2_c "SW2_c") (joined + (portRef SW2_c) + (portRef B (instanceRef reset_RNO)) + )) + ) + (property orig_inst_of (string "Reset_out")) + ) + ) + (cell LedBlinkingDSpeed (cellType GENERIC) + (view architecture_ledblinkingdspeed (viewType NETLIST) + (interface + (port clk (direction INPUT)) + (port SW1 (direction INPUT)) + (port SW2 (direction INPUT)) + (port green_led1 (direction OUTPUT)) + (port red_led1 (direction OUTPUT)) + (port green_led2 (direction OUTPUT)) + (port red_led2 (direction OUTPUT)) + ) + (contents + (instance clk_ibuf_RNIVTI2 (viewRef PRIM (cellRef CLKINT (libraryRef ACG4))) + ) + (instance clk_ibuf (viewRef PRIM (cellRef INBUF (libraryRef ACG4))) + ) + (instance SW1_ibuf (viewRef PRIM (cellRef INBUF (libraryRef ACG4))) + ) + (instance SW2_ibuf (viewRef PRIM (cellRef INBUF (libraryRef ACG4))) + ) + (instance green_led1_obuf (viewRef PRIM (cellRef OUTBUF (libraryRef ACG4))) + ) + (instance red_led1_obuf (viewRef PRIM (cellRef OUTBUF (libraryRef ACG4))) + ) + (instance green_led2_obuf (viewRef PRIM (cellRef OUTBUF (libraryRef ACG4))) + ) + (instance red_led2_obuf (viewRef PRIM (cellRef OUTBUF (libraryRef ACG4))) + ) + (instance Clear_outputs (viewRef netlist (cellRef Reset_out)) + ) + (instance Initial_blinking_SW1 (viewRef netlist (cellRef ClkGenNoSwitch)) + ) + (instance Fast_clk_SW1 (viewRef netlist (cellRef ClkGen)) + ) + (instance Initial_blinking_SW2 (viewRef netlist (cellRef ClkGenNoSwitch_1)) + ) + (instance Fast_clk_SW2 (viewRef netlist (cellRef ClkGen_1)) + ) + (instance Display_out (viewRef netlist (cellRef Display)) + ) + (instance GND (viewRef PRIM (cellRef GND (libraryRef ACG4))) ) + (instance VCC (viewRef PRIM (cellRef VCC (libraryRef ACG4))) ) + (net reset (joined + (portRef reset (instanceRef Clear_outputs)) + (portRef reset (instanceRef Display_out)) + (portRef reset (instanceRef Fast_clk_SW2)) + (portRef reset (instanceRef Initial_blinking_SW2)) + (portRef reset (instanceRef Fast_clk_SW1)) + (portRef reset (instanceRef Initial_blinking_SW1)) + )) + (net (rename GNDZ0 "GND") (joined + (portRef Y (instanceRef GND)) + (portRef D (instanceRef green_led2_obuf)) + (portRef D (instanceRef red_led1_obuf)) + )) + (net (rename VCCZ0 "VCC") (joined + (portRef Y (instanceRef VCC)) + )) + (net led0 (joined + (portRef led0 (instanceRef Initial_blinking_SW1)) + (portRef led0 (instanceRef Display_out)) + )) + (net led (joined + (portRef led (instanceRef Fast_clk_SW1)) + (portRef led (instanceRef Display_out)) + )) + (net led1 (joined + (portRef led1 (instanceRef Initial_blinking_SW2)) + (portRef led1 (instanceRef Display_out)) + )) + (net led2 (joined + (portRef led2 (instanceRef Fast_clk_SW2)) + (portRef led2 (instanceRef Display_out)) + )) + (net clk_c (joined + (portRef Y (instanceRef clk_ibuf_RNIVTI2)) + (portRef clk_c (instanceRef Display_out)) + (portRef clk_c (instanceRef Fast_clk_SW2)) + (portRef clk_c (instanceRef Initial_blinking_SW2)) + (portRef clk_c (instanceRef Fast_clk_SW1)) + (portRef clk_c (instanceRef Initial_blinking_SW1)) + (portRef clk_c (instanceRef Clear_outputs)) + )) + (net clk (joined + (portRef clk) + (portRef PAD (instanceRef clk_ibuf)) + )) + (net SW1_c (joined + (portRef Y (instanceRef SW1_ibuf)) + (portRef SW1_c (instanceRef Display_out)) + (portRef SW1_c (instanceRef Fast_clk_SW1)) + (portRef SW1_c (instanceRef Clear_outputs)) + )) + (net (rename sw1 "SW1") (joined + (portRef SW1) + (portRef PAD (instanceRef SW1_ibuf)) + )) + (net SW2_c (joined + (portRef Y (instanceRef SW2_ibuf)) + (portRef SW2_c (instanceRef Display_out)) + (portRef SW2_c (instanceRef Fast_clk_SW2)) + (portRef SW2_c (instanceRef Clear_outputs)) + )) + (net (rename sw2 "SW2") (joined + (portRef SW2) + (portRef PAD (instanceRef SW2_ibuf)) + )) + (net green_led1_c (joined + (portRef green_led1_c (instanceRef Display_out)) + (portRef D (instanceRef green_led1_obuf)) + )) + (net green_led1 (joined + (portRef PAD (instanceRef green_led1_obuf)) + (portRef green_led1) + )) + (net red_led1 (joined + (portRef PAD (instanceRef red_led1_obuf)) + (portRef red_led1) + )) + (net green_led2 (joined + (portRef PAD (instanceRef green_led2_obuf)) + (portRef green_led2) + )) + (net red_led2_c (joined + (portRef red_led2_c (instanceRef Display_out)) + (portRef D (instanceRef red_led2_obuf)) + )) + (net red_led2 (joined + (portRef PAD (instanceRef red_led2_obuf)) + (portRef red_led2) + )) + (net (rename clk_ibufZ0 "clk_ibuf") (joined + (portRef Y (instanceRef clk_ibuf)) + (portRef A (instanceRef clk_ibuf_RNIVTI2)) + )) + ) + (property orig_inst_of (string "LedBlinkingDSpeed")) + ) + ) + ) + (design LedBlinkingDSpeed (cellRef LedBlinkingDSpeed (libraryRef work)) + (property PART (string "m2gl025vf256std") (owner "Microsemi"))) +) diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.fse b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.fse new file mode 100644 index 0000000..e69de29 diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.htm b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.htm new file mode 100644 index 0000000..15132de --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.htm @@ -0,0 +1,9 @@ + + + syntmp/LedBlinkingDSpeed_srr.htm log file + + + + + + diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.map b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.map new file mode 100644 index 0000000..2b02f94 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.map @@ -0,0 +1 @@ +%%% protect protected_file diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.sap b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.sap new file mode 100644 index 0000000..133b8e4 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.sap @@ -0,0 +1,199 @@ +%%% protect protected_file +@ER +8BNDCsk_F00bk# +; +osHRC0#C;H +NR$3#MD_OF_O CsG0NHO0FpMR;8 + +R#7Hb$DN_0Fk;o + +HCRs8C_D8 +.;N3HR#_$MOODF G_C0OsN0MHFR +p; +IMRFRs pAC8D HMH7Mo1CbC8sRNO0EHCkO0sDC_CD8LHHM M#o8b8CC;o + +HDRBC_NsFbk0k;0# +RNH3M#$_FODOC _GN0sOF0HM;Rv +H +oRHQM0DHN_HLDMM HoW_14N; +H#R3$OM_D FO_0CGs0NOHRFMv +; +owHRN_#0O_D 1;W4 +RNH3M#$_FODOC _GN0sOF0HM;Rv +H +oRHQM0DHN_HLDMM HoW_1.N; +H#R3$OM_D FO_0CGs0NOHRFMv +; +owHRN_#0O_D 1;W. +RNH3M#$_FODOC _GN0sOF0HM;Rv +H +oR#7Hb$DN_0Fk;H +NR$3#MD_OF_O CsG0NHO0FvMR;8 + +R#wN0D_O W_1. +; +oOHRMd0r49:j;H +NR$3#MD_OF_O CsG0NHO0FpMR;8 + +R#wN0D_O W_14 +; +oOHRMd0r49:j;H +NR$3#MD_OF_O CsG0NHO0FpMR;8 + +RHQM0DHN_HLDMM HoW_1. +; +oOHRMd0r49:j;H +NR$3#MD_OF_O CsG0NHO0FpMR;8 + +RHQM0DHN_HLDMM HoW_14 +; +oOHRMd0r49:j;H +NR$3#MD_OF_O CsG0NHO0FpMR; + + + +R +8BNDCsk_F00bk# +; +osHRC0#C;H +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNH3FODOC _8RoC"#sHC +";oBbR;b +NR#3H_FODO4 R;b +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNb3FODOC _8RoC"#sHC +";oOMRD + ;N3MRHO#_D FOR +4;N3MROODF pR"CD8AHHM M1o7b8CC| OD"N; +MOR3D FO_oC8CsR"H"#C;8 + +R#7Hb$DN_0Fk;o + +HsRoC_CMD4C8;H +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNH3FODOC _8RoC"#sHC +";N3HRNM#$OC_s#RC0"sM:C0#C"o; +b;RB +RNb3_H#OODF ;R4 +RNb3FODO" RpAC8D HMH7Mo1CbC8D|O +";N3bROODF 8_Co"CRsCH#" +; +osHRCD8_C;8. +RNH3FODO" RpAC8D HMH7Mo1CbC8D|O +";N3HROODF 8_Co"CRsCH#"N; +HNR3#O$M_#sCC"0RMC:s#"C0;b +oR +B;N3bRHO#_D FOR +4;N3bROODF pR"CD8AHHM M1o7b8CC| OD"N; +bOR3D FO_oC8CsR"H"#C;M +oR OD;M +NR#3H_FODO4 R;M +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNM3FODOC _8RoC"#sHC +"; +IMRFRs pAC8D HMH7Mo1CbC8sRNO0EHCkO0sDC_CD8LHHM M#o8b8CC;M +oR OD;M +NR#3H_FODO4 R;M +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNM3FODOC _8RoC"#sHC +";N3PR#_$MObFlH_DCbMFH0;R4 +R +8w0N#_ OD_.1W;o + +HlR0bD_O N; +HOR3D FORC"p8HADMM Hob71C|C8O"D ;H +NRD3OF_O CC8oRH"s#;C" +RNH3FODOC _MDNLCMR":.1W"N; +HNR3#O$M_#sCC"0RMC:s#"C0;b +oR +B;N3bRHO#_D FOR +4;N3bROODF pR"CD8AHHM M1o7b8CC| OD"N; +bOR3D FO_oC8CsR"H"#C;o + +HMRO04rd:;j9 +RNH3FODO" RpAC8D HMH7Mo1CbC8D|O +";N3HROODF 8_Co"CRsCH#"N; +HOR3D FO_NCMLRDC"1M:W;." +RNH3$N#MsO_C0#CR:"MsCC#0 +";oBbR;b +NR#3H_FODO4 R;b +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNb3FODOC _8RoC"#sHC +";oOMRDM Q;M +NR#3H_FODO4 R;M +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNM3FODOC _8RoC"#sHC +"; +w8RN_#0O_D 1;W4 +H +oRb0l_ OD;H +NRD3OFRO "8pCAMDH oHM7C1bCO8|D; " +RNH3FODOC _8RoC"#sHC +";N3HROODF M_CNCLDR:"M1"W4;H +NR#3N$_MOsCC#0MR":#sCC;0" +RobBN; +bHR3#D_OFRO 4N; +bOR3D FORC"p8HADMM Hob71C|C8O"D ;b +NRD3OF_O CC8oRH"s#;C" +H +oR0OMr:d4j +9;N3HROODF pR"CD8AHHM M1o7b8CC| OD"N; +HOR3D FO_oC8CsR"H"#C;H +NRD3OF_O CLMND"CRMW:14 +";N3HRNM#$OC_s#RC0"sM:C0#C"o; +b;RB +RNb3_H#OODF ;R4 +RNb3FODO" RpAC8D HMH7Mo1CbC8D|O +";N3bROODF 8_Co"CRsCH#"o; +MDRO ;QM +RNM3_H#OODF ;R4 +RNM3FODO" RpAC8D HMH7Mo1CbC8D|O +";N3MROODF 8_Co"CRsCH#" +; +8MRQHN0HDD_LHHM M1o_W +.; +RoH0_lbO;D +RNH3FODO" RpAC8D HMH7Mo1CbC8D|O +";N3HROODF 8_Co"CRsCH#"N; +HNR3#O$M_#sCC"0RMC:s#"C0;b +oR +B;N3bRHO#_D FOR +4;N3bROODF pR"CD8AHHM M1o7b8CC| OD"N; +bOR3D FO_oC8CsR"H"#C;o + +HMRO04rd:;j9 +RNH3FODO" RpAC8D HMH7Mo1CbC8D|O +";N3HROODF 8_Co"CRsCH#"N; +HNR3#O$M_#sCC"0RMC:s#"C0;b +oR +B;N3bRHO#_D FOR +4;N3bROODF pR"CD8AHHM M1o7b8CC| OD"N; +bOR3D FO_oC8CsR"H"#C;M +oR ODQ +M;N3MRHO#_D FOR +4;N3MROODF pR"CD8AHHM M1o7b8CC| OD"N; +MOR3D FO_oC8CsR"H"#C;8 + +RHQM0DHN_HLDMM HoW_14 +; +o0HRlOb_D + ;N3HROODF pR"CD8AHHM M1o7b8CC| OD"N; +HOR3D FO_oC8CsR"H"#C;H +NR#3N$_MOsCC#0MR":#sCC;0" +RobBN; +bHR3#D_OFRO 4N; +bOR3D FORC"p8HADMM Hob71C|C8O"D ;b +NRD3OF_O CC8oRH"s#;C" +H +oR0OMr:d4j +9;N3HROODF pR"CD8AHHM M1o7b8CC| OD"N; +HOR3D FO_oC8CsR"H"#C;H +NR#3N$_MOsCC#0MR":#sCC;0" +RobBN; +bHR3#D_OFRO 4N; +bOR3D FORC"p8HADMM Hob71C|C8O"D ;b +NRD3OF_O CC8oRH"s#;C" +RoMOQD MN; +MHR3#D_OFRO 4N; +MOR3D FORC"p8HADMM Hob71C|C8O"D ;M +NRD3OF_O CC8oRH"s#;C" diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.so b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.so new file mode 100644 index 0000000..46e665a --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.so @@ -0,0 +1,6 @@ + + + Success + LedBlinkingDSpeed + C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn + diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srd b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srd new file mode 100644 index 0000000..c038067 Binary files /dev/null and b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srd differ diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srm b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srm new file mode 100644 index 0000000..75e3af4 Binary files /dev/null and b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srm differ diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srr b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srr new file mode 100644 index 0000000..75ccddd --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srr @@ -0,0 +1,550 @@ +#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 +#install: C:\tools\Microsemi\Libero_SoC_v11.7\Synplify +#OS: Windows 7 6.1 +#Hostname: LOSANGLAP73674 + +#Implementation: synthesis + +Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode +Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode +Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns +@N:"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Top entity is set to LedBlinkingDSpeed. +File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd changed - recompiling +VHDL syntax check successful! +File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd changed - recompiling +@N: CD231 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus ('U'="1000000000") +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Synthesizing work.ledblinkingdspeed.architecture_ledblinkingdspeed +@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":93:11:93:23|Signal scale_factor0 is undriven +@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":94:11:94:23|Signal scale_factor1 is undriven +@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":95:11:95:23|Signal scale_factor3 is undriven +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":54:7:54:13|Synthesizing work.display.architecture_display +@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:18:82:20|Referenced variable sw2 is not in sensitivity list +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:24:82:26|Referenced variable sw1 is not in sensitivity list +Post processing for work.display.architecture_display +@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to red_led1 assign '0'; register removed by optimization +@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to green_led2 assign '0'; register removed by optimization +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":56:7:56:12|Synthesizing work.clkgen.architecture_clkgen +@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":76:4:76:10|Incomplete sensitivity list - assuming completeness +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":79:21:79:25|Referenced variable scale is not in sensitivity list +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":83:33:83:34|Referenced variable sw is not in sensitivity list +Post processing for work.clkgen.architecture_clkgen +@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal cnt[31:0]. +@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal tmp_clk. +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":56:7:56:20|Synthesizing work.clkgennoswitch.architecture_clkgennoswitch +@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":80:21:80:25|Referenced variable scale is not in sensitivity list +Post processing for work.clkgennoswitch.architecture_clkgennoswitch +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd":55:7:55:15|Synthesizing work.reset_out.architecture_reset_out +Post processing for work.reset_out.architecture_reset_out +Post processing for work.ledblinkingdspeed.architecture_ledblinkingdspeed + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:59:30 2016 + +###########################################################] +Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode +File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\layer0.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:59:30 2016 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:59:30 2016 + +###########################################################] +Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode +File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:59:31 2016 + +###########################################################] +Pre-mapping Report + +Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 +Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2015.03M-SP1-2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +Reading constraint file: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc +@L: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_scck.rpt +Printing clock summary report in "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF667 |Clock conversion disabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + +syn_allowed_resources : blockrams=31 set on top level netlist LedBlinkingDSpeed + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) + + + +@S |Clock Summary +***************** + +Start Requested Requested Clock Clock +Clock Frequency Period Type Group +----------------------------------------------------------------------------------- +LedBlinkingDSpeed|clk 50.0 MHz 20.000 declared default_clkgroup +=================================================================================== + +Finished Pre Mapping Phase. +@N: BN225 |Writing default property annotation file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap. +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:59:32 2016 + +###########################################################] +Map & Optimize Report + +Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 +Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2015.03M-SP1-2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF667 |Clock conversion disabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB) + +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Found counter in view:work.ClkGenNoSwitch(architecture_clkgennoswitch) inst cnt[31:0] +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Found counter in view:work.ClkGen(architecture_clkgen) inst cnt[31:0] +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Found counter in view:work.ClkGenNoSwitch_0(architecture_clkgennoswitch) inst cnt[31:0] +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Found counter in view:work.ClkGen_0(architecture_clkgen) inst cnt[31:0] + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:00s 10.53ns 165 / 115 +@N: FP130 |Promoting Net reset on CLKINT I_103 +@N: FP130 |Promoting Net clk_c on CLKINT I_104 + +Added 0 Buffers +Added 0 Cells via replication + Added 0 Sequential Cells via replication + Added 0 Combinational Cells via replication + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +Clock optimization not enabled +1 non-gated/non-generated clock tree(s) driving 115 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +================================= Non-Gated/Non-Generated Clocks ================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------- +@K:CKID0001 clk clock definition on port 115 Display_out.red_led2 +================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 134MB) + +Writing Analyst data base C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) + +Writing EDIF Netlist and constraint files +@N: BW103 |Synopsys Constraint File time units using default value of 1ns +@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF +J-2015.03M-SP1-2 + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) + +Found clock LedBlinkingDSpeed|clk with period 20.00ns + + +@S |##### START OF TIMING REPORT #####[ +# Timing Report written on Sun Oct 23 02:59:33 2016 +# + + +Top view: LedBlinkingDSpeed +Requested Frequency: 50.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc + +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: 12.640 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +-------------------------------------------------------------------------------------------------------------------------- +LedBlinkingDSpeed|clk 50.0 MHz 135.9 MHz 20.000 7.360 12.640 declared default_clkgroup +========================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------- +LedBlinkingDSpeed|clk LedBlinkingDSpeed|clk | 20.000 12.640 | No paths - | No paths - | No paths - +===================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: LedBlinkingDSpeed|clk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------------- +Initial_blinking_SW2.cnt[8] LedBlinkingDSpeed|clk SLE Q cnt[8] 0.108 12.640 +Initial_blinking_SW2.cnt[9] LedBlinkingDSpeed|clk SLE Q cnt[9] 0.108 12.734 +Initial_blinking_SW2.cnt[13] LedBlinkingDSpeed|clk SLE Q cnt[13] 0.108 12.747 +Initial_blinking_SW2.cnt[10] LedBlinkingDSpeed|clk SLE Q cnt[10] 0.108 12.809 +Initial_blinking_SW2.cnt[14] LedBlinkingDSpeed|clk SLE Q cnt[14] 0.108 12.825 +Initial_blinking_SW2.cnt[11] LedBlinkingDSpeed|clk SLE Q cnt[11] 0.108 12.857 +Initial_blinking_SW2.cnt[15] LedBlinkingDSpeed|clk SLE Q cnt[15] 0.108 12.871 +Initial_blinking_SW2.cnt[16] LedBlinkingDSpeed|clk SLE Q cnt[16] 0.108 12.948 +Fast_clk_SW2.cnt[7] LedBlinkingDSpeed|clk SLE Q cnt[7] 0.087 13.391 +Fast_clk_SW1.cnt[6] LedBlinkingDSpeed|clk SLE Q cnt[6] 0.087 13.407 +========================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------------------------- +Initial_blinking_SW2.cnt[26] LedBlinkingDSpeed|clk SLE D cnt_s[26] 19.745 12.640 +Initial_blinking_SW2.cnt[25] LedBlinkingDSpeed|clk SLE D cnt_s[25] 19.745 12.656 +Initial_blinking_SW2.cnt[24] LedBlinkingDSpeed|clk SLE D cnt_s[24] 19.745 12.673 +Initial_blinking_SW2.cnt[23] LedBlinkingDSpeed|clk SLE D cnt_s[23] 19.745 12.689 +Initial_blinking_SW2.cnt[22] LedBlinkingDSpeed|clk SLE D cnt_s[22] 19.745 12.705 +Initial_blinking_SW2.cnt[21] LedBlinkingDSpeed|clk SLE D cnt_s[21] 19.745 12.722 +Initial_blinking_SW2.cnt[20] LedBlinkingDSpeed|clk SLE D cnt_s[20] 19.745 12.738 +Initial_blinking_SW2.cnt[19] LedBlinkingDSpeed|clk SLE D cnt_s[19] 19.745 12.754 +Initial_blinking_SW2.cnt[18] LedBlinkingDSpeed|clk SLE D cnt_s[18] 19.745 12.770 +Initial_blinking_SW2.cnt[17] LedBlinkingDSpeed|clk SLE D cnt_s[17] 19.745 12.787 +============================================================================================================= + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 20.000 + - Setup time: 0.255 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 19.745 + + - Propagation time: 7.105 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 12.640 + + Number of logic level(s): 32 + Starting point: Initial_blinking_SW2.cnt[8] / Q + Ending point: Initial_blinking_SW2.cnt[26] / D + The start point is clocked by LedBlinkingDSpeed|clk [rising] on pin CLK + The end point is clocked by LedBlinkingDSpeed|clk [rising] on pin CLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------------------- +Initial_blinking_SW2.cnt[8] SLE Q Out 0.108 0.108 - +cnt[8] Net - - 0.674 - 2 +Initial_blinking_SW2.cnt_RNI8JG21[10] CFG4 D In - 0.783 - +Initial_blinking_SW2.cnt_RNI8JG21[10] CFG4 Y Out 0.317 1.100 - +N_176 Net - - 0.630 - 2 +Initial_blinking_SW2.cnt_RNIIH0I1[12] CFG3 C In - 1.730 - +Initial_blinking_SW2.cnt_RNIIH0I1[12] CFG3 Y Out 0.226 1.956 - +N_87 Net - - 0.556 - 1 +Initial_blinking_SW2.cnt_RNI4GAR1[17] CFG4 B In - 2.511 - +Initial_blinking_SW2.cnt_RNI4GAR1[17] CFG4 Y Out 0.148 2.660 - +N_93 Net - - 0.556 - 1 +Initial_blinking_SW2.cnt_RNI9EVA2[20] CFG4 C In - 3.216 - +Initial_blinking_SW2.cnt_RNI9EVA2[20] CFG4 Y Out 0.226 3.441 - +N_103 Net - - 0.556 - 1 +Initial_blinking_SW2.cnt_RNIOCCK2[27] ARI1 B In - 3.997 - +Initial_blinking_SW2.cnt_RNIOCCK2[27] ARI1 Y Out 0.165 4.161 - +cnt_RNIOCCK2_Y[27] Net - - 1.145 - 27 +Initial_blinking_SW2.cnt_RNITNTM5[0] ARI1 B In - 5.306 - +Initial_blinking_SW2.cnt_RNITNTM5[0] ARI1 FCO Out 0.201 5.507 - +cnt_cry[0] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI34FP8[1] ARI1 FCI In - 5.507 - +Initial_blinking_SW2.cnt_RNI34FP8[1] ARI1 FCO Out 0.016 5.523 - +cnt_cry[1] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIAH0SB[2] ARI1 FCI In - 5.523 - +Initial_blinking_SW2.cnt_RNIAH0SB[2] ARI1 FCO Out 0.016 5.540 - +cnt_cry[2] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIIVHUE[3] ARI1 FCI In - 5.540 - +Initial_blinking_SW2.cnt_RNIIVHUE[3] ARI1 FCO Out 0.016 5.556 - +cnt_cry[3] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIRE31I[4] ARI1 FCI In - 5.556 - +Initial_blinking_SW2.cnt_RNIRE31I[4] ARI1 FCO Out 0.016 5.572 - +cnt_cry[4] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI5VK3L[5] ARI1 FCI In - 5.572 - +Initial_blinking_SW2.cnt_RNI5VK3L[5] ARI1 FCO Out 0.016 5.589 - +cnt_cry[5] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIGG66O[6] ARI1 FCI In - 5.589 - +Initial_blinking_SW2.cnt_RNIGG66O[6] ARI1 FCO Out 0.016 5.605 - +cnt_cry[6] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIS2O8R[7] ARI1 FCI In - 5.605 - +Initial_blinking_SW2.cnt_RNIS2O8R[7] ARI1 FCO Out 0.016 5.621 - +cnt_cry[7] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI9M9BU[8] ARI1 FCI In - 5.621 - +Initial_blinking_SW2.cnt_RNI9M9BU[8] ARI1 FCO Out 0.016 5.638 - +cnt_cry[8] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNINARD11[9] ARI1 FCI In - 5.638 - +Initial_blinking_SW2.cnt_RNINARD11[9] ARI1 FCO Out 0.016 5.654 - +cnt_cry[9] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIDPA541[10] ARI1 FCI In - 5.654 - +Initial_blinking_SW2.cnt_RNIDPA541[10] ARI1 FCO Out 0.016 5.670 - +cnt_cry[10] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI49QS61[11] ARI1 FCI In - 5.670 - +Initial_blinking_SW2.cnt_RNI49QS61[11] ARI1 FCO Out 0.016 5.686 - +cnt_cry[11] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNISP9K91[12] ARI1 FCI In - 5.686 - +Initial_blinking_SW2.cnt_RNISP9K91[12] ARI1 FCO Out 0.016 5.703 - +cnt_cry[12] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNILBPBC1[13] ARI1 FCI In - 5.703 - +Initial_blinking_SW2.cnt_RNILBPBC1[13] ARI1 FCO Out 0.016 5.719 - +cnt_cry[13] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIFU83F1[14] ARI1 FCI In - 5.719 - +Initial_blinking_SW2.cnt_RNIFU83F1[14] ARI1 FCO Out 0.016 5.735 - +cnt_cry[14] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIAIOQH1[15] ARI1 FCI In - 5.735 - +Initial_blinking_SW2.cnt_RNIAIOQH1[15] ARI1 FCO Out 0.016 5.752 - +cnt_cry[15] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI678IK1[16] ARI1 FCI In - 5.752 - +Initial_blinking_SW2.cnt_RNI678IK1[16] ARI1 FCO Out 0.016 5.768 - +cnt_cry[16] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI3TN9N1[17] ARI1 FCI In - 5.768 - +Initial_blinking_SW2.cnt_RNI3TN9N1[17] ARI1 FCO Out 0.016 5.784 - +cnt_cry[17] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI1K71Q1[18] ARI1 FCI In - 5.784 - +Initial_blinking_SW2.cnt_RNI1K71Q1[18] ARI1 FCO Out 0.016 5.801 - +cnt_cry[18] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI0CNOS1[19] ARI1 FCI In - 5.801 - +Initial_blinking_SW2.cnt_RNI0CNOS1[19] ARI1 FCO Out 0.016 5.817 - +cnt_cry[19] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNINS7GV1[20] ARI1 FCI In - 5.817 - +Initial_blinking_SW2.cnt_RNINS7GV1[20] ARI1 FCO Out 0.016 5.833 - +cnt_cry[20] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIFEO722[21] ARI1 FCI In - 5.833 - +Initial_blinking_SW2.cnt_RNIFEO722[21] ARI1 FCO Out 0.016 5.849 - +cnt_cry[21] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI819V42[22] ARI1 FCI In - 5.849 - +Initial_blinking_SW2.cnt_RNI819V42[22] ARI1 FCO Out 0.016 5.866 - +cnt_cry[22] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNI2LPM72[23] ARI1 FCI In - 5.866 - +Initial_blinking_SW2.cnt_RNI2LPM72[23] ARI1 FCO Out 0.016 5.882 - +cnt_cry[23] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIT9AEA2[24] ARI1 FCI In - 5.882 - +Initial_blinking_SW2.cnt_RNIT9AEA2[24] ARI1 FCO Out 0.016 5.898 - +cnt_cry[24] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIPVQ5D2[25] ARI1 FCI In - 5.898 - +Initial_blinking_SW2.cnt_RNIPVQ5D2[25] ARI1 FCO Out 0.016 5.915 - +cnt_cry[25] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIMMBTF2[26] ARI1 FCI In - 5.915 - +Initial_blinking_SW2.cnt_RNIMMBTF2[26] ARI1 S Out 0.073 5.988 - +cnt_s[26] Net - - 1.117 - 1 +Initial_blinking_SW2.cnt[26] SLE D In - 7.105 - +===================================================================================================== +Total path delay (propagation time + setup) of 7.360 is 2.126(28.9%) logic and 5.234(71.1%) route. +Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value + + + +##### END OF TIMING REPORT #####] + + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) + +--------------------------------------- +Resource Usage Report for LedBlinkingDSpeed + +Mapping to part: m2gl025vf256std +Cell usage: +CLKINT 2 uses +CFG2 4 uses +CFG3 9 uses +CFG4 38 uses + +Carry primitives used for arithmetic functions: +ARI1 108 uses + + +Sequential Cells: +SLE 115 uses + +DSP Blocks: 0 + +I/O ports: 7 +I/O primitives: 7 +INBUF 3 uses +OUTBUF 4 uses + + +Global Clock Buffers: 2 + + +Total LUTs: 159 + +Extra resources required for RAM and MACC interface logic during P&R: + +RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; +RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; +MACC Interface Logic : SLEs = 0; LUTs = 0; + +Total number of SLEs after P&R: 115 + 0 + 0 + 0 = 115; +Total number of LUTs after P&R: 159 + 0 + 0 + 0 = 159; + +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 135MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:59:34 2016 + +###########################################################] diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srs b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srs new file mode 100644 index 0000000..75ff6c9 Binary files /dev/null and b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.srs differ diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed.vhd b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.vhd new file mode 100644 index 0000000..cd6681b --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed.vhd @@ -0,0 +1,2514 @@ +-- Version: v11.7 SP1 11.7.1.11 + +library ieee; +use ieee.std_logic_1164.all; +library smartfusion2; +use smartfusion2.all; + +entity ClkGenNoSwitch_1 is + + port( led1 : out std_logic; + reset : in std_logic; + clk_c : in std_logic + ); + +end ClkGenNoSwitch_1; + +architecture DEF_ARCH of ClkGenNoSwitch_1 is + + component CFG4 + generic (INIT:std_logic_vector(15 downto 0) := x"0000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component SLE + port( D : in std_logic := 'U'; + CLK : in std_logic := 'U'; + EN : in std_logic := 'U'; + ALn : in std_logic := 'U'; + ADn : in std_logic := 'U'; + SLn : in std_logic := 'U'; + SD : in std_logic := 'U'; + LAT : in std_logic := 'U'; + Q : out std_logic + ); + end component; + + component ARI1 + generic (INIT:std_logic_vector(19 downto 0) := x"00000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + FCI : in std_logic := 'U'; + S : out std_logic; + Y : out std_logic; + FCO : out std_logic + ); + end component; + + component VCC + port( Y : out std_logic + ); + end component; + + component GND + port( Y : out std_logic + ); + end component; + + component CFG3 + generic (INIT:std_logic_vector(7 downto 0) := x"00"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + signal VCC_net_1, \tmp_clk_RNO\, GND_net_1, \cnt[0]_net_1\, + \cnt_s[0]\, \cnt[1]_net_1\, \cnt_s[1]\, \cnt[2]_net_1\, + \cnt_s[2]\, \cnt[3]_net_1\, \cnt_s[3]\, \cnt[4]_net_1\, + \cnt_s[4]\, \cnt[5]_net_1\, \cnt_s[5]\, \cnt[6]_net_1\, + \cnt_s[6]\, \cnt[7]_net_1\, \cnt_s[7]\, \cnt[8]_net_1\, + \cnt_s[8]\, \cnt[9]_net_1\, \cnt_s[9]\, \cnt[10]_net_1\, + \cnt_s[10]\, \cnt[11]_net_1\, \cnt_s[11]\, + \cnt[12]_net_1\, \cnt_s[12]\, \cnt[13]_net_1\, + \cnt_s[13]\, \cnt[14]_net_1\, \cnt_s[14]\, + \cnt[15]_net_1\, \cnt_s[15]\, \cnt[16]_net_1\, + \cnt_s[16]\, \cnt[17]_net_1\, \cnt_s[17]\, + \cnt[18]_net_1\, \cnt_s[18]\, \cnt[19]_net_1\, + \cnt_s[19]\, \cnt[20]_net_1\, \cnt_s[20]\, + \cnt[21]_net_1\, \cnt_s[21]\, \cnt[22]_net_1\, + \cnt_s[22]\, \cnt[23]_net_1\, \cnt_s[23]\, + \cnt[24]_net_1\, \cnt_s[24]\, \cnt[25]_net_1\, + \cnt_s[25]\, \cnt[26]_net_1\, \cnt_s[26]\, + \cnt[27]_net_1\, \cnt_s[27]\, cnt_cry_cy, + \cnt_RNIOCCK2_Y[27]\, N_103, \cnt_cry[0]\, \cnt_cry[1]\, + \cnt_cry[2]\, \cnt_cry[3]\, \cnt_cry[4]\, \cnt_cry[5]\, + \cnt_cry[6]\, \cnt_cry[7]\, \cnt_cry[8]\, \cnt_cry[9]\, + \cnt_cry[10]\, \cnt_cry[11]\, \cnt_cry[12]\, + \cnt_cry[13]\, \cnt_cry[14]\, \cnt_cry[15]\, + \cnt_cry[16]\, \cnt_cry[17]\, \cnt_cry[18]\, + \cnt_cry[19]\, \cnt_cry[20]\, \cnt_cry[21]\, + \cnt_cry[22]\, \cnt_cry[23]\, \cnt_cry[24]\, + \cnt_cry[25]\, N_94, m39_e_1, N_105, m21_e_2, m30_e_1, + m13_e_1, N_176, N_88, N_87, N_93 : std_logic; + +begin + + + \cnt_RNI4GAR1[17]\ : CFG4 + generic map(INIT => x"010F") + + port map(A => \cnt[17]_net_1\, B => N_87, C => + \cnt[19]_net_1\, D => \cnt[18]_net_1\, Y => N_93); + + \cnt[19]\ : SLE + port map(D => \cnt_s[19]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[19]_net_1\); + + \cnt_RNI819V42[22]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[22]_net_1\, D => GND_net_1, FCI => \cnt_cry[21]\, S + => \cnt_s[22]\, Y => OPEN, FCO => \cnt_cry[22]\); + + tmp_clk_RNO_0 : CFG4 + generic map(INIT => x"3331") + + port map(A => \cnt[23]_net_1\, B => \cnt[24]_net_1\, C => + N_94, D => m39_e_1, Y => N_105); + + \cnt_RNIAH0SB[2]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[2]_net_1\, D => GND_net_1, FCI => \cnt_cry[1]\, S + => \cnt_s[2]\, Y => OPEN, FCO => \cnt_cry[2]\); + + \cnt[27]\ : SLE + port map(D => \cnt_s[27]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[27]_net_1\); + + tmp_clk : SLE + port map(D => \tmp_clk_RNO\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => led1); + + \cnt[2]\ : SLE + port map(D => \cnt_s[2]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[2]_net_1\); + + \cnt[8]\ : SLE + port map(D => \cnt_s[8]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[8]_net_1\); + + \cnt[26]\ : SLE + port map(D => \cnt_s[26]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[26]_net_1\); + + \cnt[1]\ : SLE + port map(D => \cnt_s[1]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[1]_net_1\); + + \cnt_RNIAIOQH1[15]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[15]_net_1\, D => GND_net_1, FCI => \cnt_cry[14]\, S + => \cnt_s[15]\, Y => OPEN, FCO => \cnt_cry[15]\); + + \cnt[11]\ : SLE + port map(D => \cnt_s[11]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[11]_net_1\); + + \cnt_RNIRE31I[4]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[4]_net_1\, D => GND_net_1, FCI => \cnt_cry[3]\, S + => \cnt_s[4]\, Y => OPEN, FCO => \cnt_cry[4]\); + + \cnt_RNI5VK3L[5]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[5]_net_1\, D => GND_net_1, FCI => \cnt_cry[4]\, S + => \cnt_s[5]\, Y => OPEN, FCO => \cnt_cry[5]\); + + \cnt_RNISP9K91[12]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[12]_net_1\, D => GND_net_1, FCI => \cnt_cry[11]\, S + => \cnt_s[12]\, Y => OPEN, FCO => \cnt_cry[12]\); + + \cnt[17]\ : SLE + port map(D => \cnt_s[17]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[17]_net_1\); + + tmp_clk_RNO : CFG4 + generic map(INIT => x"000D") + + port map(A => \cnt[25]_net_1\, B => N_105, C => + \cnt[27]_net_1\, D => \cnt[26]_net_1\, Y => \tmp_clk_RNO\); + + \cnt[16]\ : SLE + port map(D => \cnt_s[16]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[16]_net_1\); + + \cnt_RNIOCCK2[27]\ : ARI1 + generic map(INIT => x"40037") + + port map(A => \cnt[27]_net_1\, B => N_103, C => + \cnt[26]_net_1\, D => \cnt[25]_net_1\, FCI => VCC_net_1, + S => OPEN, Y => \cnt_RNIOCCK2_Y[27]\, FCO => cnt_cry_cy); + + \cnt_RNILBPBC1[13]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[13]_net_1\, D => GND_net_1, FCI => \cnt_cry[12]\, S + => \cnt_s[13]\, Y => OPEN, FCO => \cnt_cry[13]\); + + \cnt_RNI8JG21[10]\ : CFG4 + generic map(INIT => x"0001") + + port map(A => \cnt[11]_net_1\, B => \cnt[10]_net_1\, C => + \cnt[9]_net_1\, D => \cnt[8]_net_1\, Y => N_176); + + \cnt_RNI9EVA2[20]\ : CFG4 + generic map(INIT => x"0800") + + port map(A => \cnt[20]_net_1\, B => \cnt[23]_net_1\, C => + N_93, D => m21_e_2, Y => N_103); + + \VCC\ : VCC + port map(Y => VCC_net_1); + + \cnt_RNIMMBTF2[26]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[26]_net_1\, D => GND_net_1, FCI => \cnt_cry[25]\, S + => \cnt_s[26]\, Y => OPEN, FCO => \cnt_s[27]\); + + \cnt_RNI1K71Q1[18]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[18]_net_1\, D => GND_net_1, FCI => \cnt_cry[17]\, S + => \cnt_s[18]\, Y => OPEN, FCO => \cnt_cry[18]\); + + \cnt_RNI0CNOS1[19]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[19]_net_1\, D => GND_net_1, FCI => \cnt_cry[18]\, S + => \cnt_s[19]\, Y => OPEN, FCO => \cnt_cry[19]\); + + \cnt[6]\ : SLE + port map(D => \cnt_s[6]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[6]_net_1\); + + tmp_clk_RNO_4 : CFG4 + generic map(INIT => x"8000") + + port map(A => \cnt[15]_net_1\, B => \cnt[14]_net_1\, C => + \cnt[13]_net_1\, D => \cnt[12]_net_1\, Y => m30_e_1); + + \cnt[4]\ : SLE + port map(D => \cnt_s[4]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[4]_net_1\); + + \cnt[9]\ : SLE + port map(D => \cnt_s[9]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[9]_net_1\); + + \cnt[0]\ : SLE + port map(D => \cnt_s[0]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[0]_net_1\); + + \cnt_RNI2LPM72[23]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[23]_net_1\, D => GND_net_1, FCI => \cnt_cry[22]\, S + => \cnt_s[23]\, Y => OPEN, FCO => \cnt_cry[23]\); + + \cnt_RNIFU83F1[14]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[14]_net_1\, D => GND_net_1, FCI => \cnt_cry[13]\, S + => \cnt_s[14]\, Y => OPEN, FCO => \cnt_cry[14]\); + + \cnt_RNIAQCC[13]\ : CFG4 + generic map(INIT => x"8000") + + port map(A => \cnt[16]_net_1\, B => \cnt[15]_net_1\, C => + \cnt[14]_net_1\, D => \cnt[13]_net_1\, Y => m13_e_1); + + tmp_clk_RNO_1 : CFG4 + generic map(INIT => x"010F") + + port map(A => \cnt[16]_net_1\, B => N_88, C => + \cnt[18]_net_1\, D => \cnt[17]_net_1\, Y => N_94); + + \GND\ : GND + port map(Y => GND_net_1); + + tmp_clk_RNO_3 : CFG3 + generic map(INIT => x"8C") + + port map(A => \cnt[7]_net_1\, B => m30_e_1, C => N_176, Y + => N_88); + + \cnt[23]\ : SLE + port map(D => \cnt_s[23]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[23]_net_1\); + + \cnt_RNINARD11[9]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[9]_net_1\, D => GND_net_1, FCI => \cnt_cry[8]\, S + => \cnt_s[9]\, Y => OPEN, FCO => \cnt_cry[9]\); + + \cnt[20]\ : SLE + port map(D => \cnt_s[20]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[20]_net_1\); + + \cnt_RNIFEO722[21]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[21]_net_1\, D => GND_net_1, FCI => \cnt_cry[20]\, S + => \cnt_s[21]\, Y => OPEN, FCO => \cnt_cry[21]\); + + \cnt[13]\ : SLE + port map(D => \cnt_s[13]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[13]_net_1\); + + \cnt_RNITNTM5[0]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[0]_net_1\, D => GND_net_1, FCI => cnt_cry_cy, S => + \cnt_s[0]\, Y => OPEN, FCO => \cnt_cry[0]\); + + \cnt_RNIDPA541[10]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[10]_net_1\, D => GND_net_1, FCI => \cnt_cry[9]\, S + => \cnt_s[10]\, Y => OPEN, FCO => \cnt_cry[10]\); + + \cnt_RNIT9AEA2[24]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[24]_net_1\, D => GND_net_1, FCI => \cnt_cry[23]\, S + => \cnt_s[24]\, Y => OPEN, FCO => \cnt_cry[24]\); + + \cnt[18]\ : SLE + port map(D => \cnt_s[18]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[18]_net_1\); + + \cnt_RNIIH0I1[12]\ : CFG3 + generic map(INIT => x"8C") + + port map(A => \cnt[12]_net_1\, B => m13_e_1, C => N_176, Y + => N_87); + + \cnt[7]\ : SLE + port map(D => \cnt_s[7]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[7]_net_1\); + + tmp_clk_RNO_2 : CFG4 + generic map(INIT => x"7FFF") + + port map(A => \cnt[22]_net_1\, B => \cnt[21]_net_1\, C => + \cnt[20]_net_1\, D => \cnt[19]_net_1\, Y => m39_e_1); + + \cnt[10]\ : SLE + port map(D => \cnt_s[10]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[10]_net_1\); + + \cnt_RNI678IK1[16]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[16]_net_1\, D => GND_net_1, FCI => \cnt_cry[15]\, S + => \cnt_s[16]\, Y => OPEN, FCO => \cnt_cry[16]\); + + \cnt_RNI4JC9[21]\ : CFG3 + generic map(INIT => x"80") + + port map(A => \cnt[24]_net_1\, B => \cnt[22]_net_1\, C => + \cnt[21]_net_1\, Y => m21_e_2); + + \cnt_RNIS2O8R[7]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[7]_net_1\, D => GND_net_1, FCI => \cnt_cry[6]\, S + => \cnt_s[7]\, Y => OPEN, FCO => \cnt_cry[7]\); + + \cnt[3]\ : SLE + port map(D => \cnt_s[3]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[3]_net_1\); + + \cnt[25]\ : SLE + port map(D => \cnt_s[25]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[25]_net_1\); + + \cnt_RNI9M9BU[8]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[8]_net_1\, D => GND_net_1, FCI => \cnt_cry[7]\, S + => \cnt_s[8]\, Y => OPEN, FCO => \cnt_cry[8]\); + + \cnt_RNI34FP8[1]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[1]_net_1\, D => GND_net_1, FCI => \cnt_cry[0]\, S + => \cnt_s[1]\, Y => OPEN, FCO => \cnt_cry[1]\); + + \cnt_RNI49QS61[11]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[11]_net_1\, D => GND_net_1, FCI => \cnt_cry[10]\, S + => \cnt_s[11]\, Y => OPEN, FCO => \cnt_cry[11]\); + + \cnt_RNIPVQ5D2[25]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[25]_net_1\, D => GND_net_1, FCI => \cnt_cry[24]\, S + => \cnt_s[25]\, Y => OPEN, FCO => \cnt_cry[25]\); + + \cnt[22]\ : SLE + port map(D => \cnt_s[22]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[22]_net_1\); + + \cnt[15]\ : SLE + port map(D => \cnt_s[15]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[15]_net_1\); + + \cnt_RNIGG66O[6]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[6]_net_1\, D => GND_net_1, FCI => \cnt_cry[5]\, S + => \cnt_s[6]\, Y => OPEN, FCO => \cnt_cry[6]\); + + \cnt[24]\ : SLE + port map(D => \cnt_s[24]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[24]_net_1\); + + \cnt_RNIIVHUE[3]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[3]_net_1\, D => GND_net_1, FCI => \cnt_cry[2]\, S + => \cnt_s[3]\, Y => OPEN, FCO => \cnt_cry[3]\); + + \cnt[5]\ : SLE + port map(D => \cnt_s[5]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[5]_net_1\); + + \cnt_RNI3TN9N1[17]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[17]_net_1\, D => GND_net_1, FCI => \cnt_cry[16]\, S + => \cnt_s[17]\, Y => OPEN, FCO => \cnt_cry[17]\); + + \cnt_RNINS7GV1[20]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => \cnt_RNIOCCK2_Y[27]\, C => + \cnt[20]_net_1\, D => GND_net_1, FCI => \cnt_cry[19]\, S + => \cnt_s[20]\, Y => OPEN, FCO => \cnt_cry[20]\); + + \cnt[12]\ : SLE + port map(D => \cnt_s[12]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[12]_net_1\); + + \cnt[14]\ : SLE + port map(D => \cnt_s[14]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[14]_net_1\); + + \cnt[21]\ : SLE + port map(D => \cnt_s[21]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[21]_net_1\); + + +end DEF_ARCH; + +library ieee; +use ieee.std_logic_1164.all; +library smartfusion2; +use smartfusion2.all; + +entity ClkGen_1 is + + port( led2 : out std_logic; + reset : in std_logic; + clk_c : in std_logic; + SW2_c : in std_logic + ); + +end ClkGen_1; + +architecture DEF_ARCH of ClkGen_1 is + + component CFG3 + generic (INIT:std_logic_vector(7 downto 0) := x"00"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component SLE + port( D : in std_logic := 'U'; + CLK : in std_logic := 'U'; + EN : in std_logic := 'U'; + ALn : in std_logic := 'U'; + ADn : in std_logic := 'U'; + SLn : in std_logic := 'U'; + SD : in std_logic := 'U'; + LAT : in std_logic := 'U'; + Q : out std_logic + ); + end component; + + component ARI1 + generic (INIT:std_logic_vector(19 downto 0) := x"00000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + FCI : in std_logic := 'U'; + S : out std_logic; + Y : out std_logic; + FCO : out std_logic + ); + end component; + + component CFG4 + generic (INIT:std_logic_vector(15 downto 0) := x"0000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component VCC + port( Y : out std_logic + ); + end component; + + component GND + port( Y : out std_logic + ); + end component; + + component CFG2 + generic (INIT:std_logic_vector(3 downto 0) := x"0"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + signal VCC_net_1, un7_cntlto31_0_0_0, GND_net_1, + \cnt[0]_net_1\, \cnt_s[0]\, \cnt[1]_net_1\, \cnt_s[1]\, + \cnt[2]_net_1\, \cnt_s[2]\, \cnt[3]_net_1\, \cnt_s[3]\, + \cnt[4]_net_1\, \cnt_s[4]\, \cnt[5]_net_1\, \cnt_s[5]\, + \cnt[6]_net_1\, \cnt_s[6]\, \cnt[7]_net_1\, \cnt_s[7]\, + \cnt[8]_net_1\, \cnt_s[8]\, \cnt[9]_net_1\, \cnt_s[9]\, + \cnt[10]_net_1\, \cnt_s[10]\, \cnt[11]_net_1\, + \cnt_s[11]\, \cnt[12]_net_1\, \cnt_s[12]\, + \cnt[13]_net_1\, \cnt_s[13]\, \cnt[14]_net_1\, + \cnt_s[14]\, \cnt[15]_net_1\, \cnt_s[15]\, + \cnt[16]_net_1\, \cnt_s[16]\, \cnt[17]_net_1\, + \cnt_s[17]\, \cnt[18]_net_1\, \cnt_s[18]\, + \cnt[19]_net_1\, \cnt_s[19]\, \cnt[20]_net_1\, + \cnt_s[20]\, \cnt[21]_net_1\, \cnt_s[21]\, + \cnt[22]_net_1\, \cnt_s[22]\, \cnt[23]_net_1\, + \cnt_s[23]\, \cnt[24]_net_1\, \cnt_s[24]\, + \cnt[25]_net_1\, \cnt_s[25]\, \cnt[26]_net_1\, + \cnt_s[26]\, cnt_cry_cy, un14_cntlto31_0_o3_RNIE29S2_Y, + N_314_tz, \un14_cntlto31_0_o3\, \un14_cntlto31_0_a2\, + \cnt_cry[0]\, \cnt_cry[1]\, \cnt_cry[2]\, \cnt_cry[3]\, + \cnt_cry[4]\, \cnt_cry[5]\, \cnt_cry[6]\, \cnt_cry[7]\, + \cnt_cry[8]\, \cnt_cry[9]\, \cnt_cry[10]\, \cnt_cry[11]\, + \cnt_cry[12]\, \cnt_cry[13]\, \cnt_cry[14]\, + \cnt_cry[15]\, \cnt_cry[16]\, \cnt_cry[17]\, + \cnt_cry[18]\, \cnt_cry[19]\, \cnt_cry[20]\, + \cnt_cry[21]\, \cnt_cry[22]\, \cnt_cry[23]\, + \cnt_cry[24]\, \un14_cntlto31_0_o2_3\, + \un14_cntlto31_0_o2_0\, N_125_3, \un7_cntlto31_0_a2_1\, + \un14_cntlto31_0_o3_0\, \un7_cntlto31_0_a2_0\, + \un7_cntlto31_0_a2\, \un7_cntlto31_0_a3\ : std_logic; + +begin + + + un14_cntlto31_0_o2_0 : CFG3 + generic map(INIT => x"7F") + + port map(A => \cnt[14]_net_1\, B => \cnt[13]_net_1\, C => + \cnt[12]_net_1\, Y => \un14_cntlto31_0_o2_0\); + + \cnt[19]\ : SLE + port map(D => \cnt_s[19]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[19]_net_1\); + + un14_cntlto31_0_o3_RNIE29S2 : ARI1 + generic map(INIT => x"4F444") + + port map(A => N_314_tz, B => \cnt[26]_net_1\, C => + \un14_cntlto31_0_o3\, D => \un14_cntlto31_0_a2\, FCI => + VCC_net_1, S => OPEN, Y => un14_cntlto31_0_o3_RNIE29S2_Y, + FCO => cnt_cry_cy); + + tmp_clk : SLE + port map(D => un7_cntlto31_0_0_0, CLK => clk_c, EN => SW2_c, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => led2); + + \cnt[2]\ : SLE + port map(D => \cnt_s[2]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[2]_net_1\); + + \cnt_RNI8FM2F2[23]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[23]_net_1\, D => GND_net_1, FCI => + \cnt_cry[22]\, S => \cnt_s[23]\, Y => OPEN, FCO => + \cnt_cry[23]\); + + \cnt[8]\ : SLE + port map(D => \cnt_s[8]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[8]_net_1\); + + \cnt[26]\ : SLE + port map(D => \cnt_s[26]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[26]_net_1\); + + \cnt[1]\ : SLE + port map(D => \cnt_s[1]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[1]_net_1\); + + \cnt_RNI9QSRV[9]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[9]_net_1\, D => GND_net_1, FCI => \cnt_cry[8]\, + S => \cnt_s[9]\, Y => OPEN, FCO => \cnt_cry[9]\); + + \cnt[11]\ : SLE + port map(D => \cnt_s[11]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[11]_net_1\); + + \cnt_RNIL94VS[8]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[8]_net_1\, D => GND_net_1, FCI => \cnt_cry[7]\, + S => \cnt_s[8]\, Y => OPEN, FCO => \cnt_cry[8]\); + + un14_cntlto31_0_o3_0_RNIA4EM1 : CFG4 + generic map(INIT => x"0073") + + port map(A => \cnt[16]_net_1\, B => \cnt[17]_net_1\, C => + \un14_cntlto31_0_o3_0\, D => \cnt[24]_net_1\, Y => + N_314_tz); + + \cnt_RNI5IPL8[1]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[1]_net_1\, D => GND_net_1, FCI => \cnt_cry[0]\, + S => \cnt_s[1]\, Y => OPEN, FCO => \cnt_cry[1]\); + + \cnt_RNI2C7FN1[16]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[16]_net_1\, D => GND_net_1, FCI => + \cnt_cry[15]\, S => \cnt_s[16]\, Y => OPEN, FCO => + \cnt_cry[16]\); + + un14_cntlto31_0_o3 : CFG4 + generic map(INIT => x"0FDF") + + port map(A => \cnt[23]_net_1\, B => \un14_cntlto31_0_o2_3\, + C => \cnt[25]_net_1\, D => \cnt[24]_net_1\, Y => + \un14_cntlto31_0_o3\); + + \cnt_RNIBISU42[20]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[20]_net_1\, D => GND_net_1, FCI => + \cnt_cry[19]\, S => \cnt_s[20]\, Y => OPEN, FCO => + \cnt_cry[20]\); + + \cnt[17]\ : SLE + port map(D => \cnt_s[17]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[17]_net_1\); + + \cnt[16]\ : SLE + port map(D => \cnt_s[16]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[16]_net_1\); + + un7_cntlto31_0_a2_0 : CFG4 + generic map(INIT => x"5551") + + port map(A => \cnt[15]_net_1\, B => \cnt[11]_net_1\, C => + \un14_cntlto31_0_o2_0\, D => \un7_cntlto31_0_a2_1\, Y => + \un7_cntlto31_0_a2_0\); + + \cnt_RNI9GQA82[21]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[21]_net_1\, D => GND_net_1, FCI => + \cnt_cry[20]\, S => \cnt_s[21]\, Y => OPEN, FCO => + \cnt_cry[21]\); + + \cnt_RNI9GKEI2[24]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[24]_net_1\, D => GND_net_1, FCI => + \cnt_cry[23]\, S => \cnt_s[24]\, Y => OPEN, FCO => + \cnt_cry[24]\); + + \cnt_RNIVBGBD1[13]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[13]_net_1\, D => GND_net_1, FCI => + \cnt_cry[12]\, S => \cnt_s[13]\, Y => OPEN, FCO => + \cnt_cry[13]\); + + \cnt_RNI0BA3K1[15]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[15]_net_1\, D => GND_net_1, FCI => + \cnt_cry[14]\, S => \cnt_s[15]\, Y => OPEN, FCO => + \cnt_cry[15]\); + + \VCC\ : VCC + port map(Y => VCC_net_1); + + \cnt_RNI2QB2Q[7]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[7]_net_1\, D => GND_net_1, FCI => \cnt_cry[6]\, + S => \cnt_s[7]\, Y => OPEN, FCO => \cnt_cry[7]\); + + \cnt_RNIVADNG1[14]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[14]_net_1\, D => GND_net_1, FCI => + \cnt_cry[13]\, S => \cnt_s[14]\, Y => OPEN, FCO => + \cnt_cry[14]\); + + \cnt[6]\ : SLE + port map(D => \cnt_s[6]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[6]_net_1\); + + \cnt[4]\ : SLE + port map(D => \cnt_s[4]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[4]_net_1\); + + \cnt[9]\ : SLE + port map(D => \cnt_s[9]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[9]_net_1\); + + \cnt_RNIGBJ5N[6]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[6]_net_1\, D => GND_net_1, FCI => \cnt_cry[5]\, + S => \cnt_s[6]\, Y => OPEN, FCO => \cnt_cry[6]\); + + \cnt_RNIBIIQL2[25]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[25]_net_1\, D => GND_net_1, FCI => + \cnt_cry[24]\, S => \cnt_s[25]\, Y => OPEN, FCO => + \cnt_s[26]\); + + \cnt_RNI5LP731[10]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[10]_net_1\, D => GND_net_1, FCI => \cnt_cry[9]\, + S => \cnt_s[10]\, Y => OPEN, FCO => \cnt_cry[10]\); + + \cnt_RNI5E4RQ1[17]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[17]_net_1\, D => GND_net_1, FCI => + \cnt_cry[16]\, S => \cnt_s[17]\, Y => OPEN, FCO => + \cnt_cry[17]\); + + \cnt_RNI0EJV91[12]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[12]_net_1\, D => GND_net_1, FCI => + \cnt_cry[11]\, S => \cnt_s[12]\, Y => OPEN, FCO => + \cnt_cry[12]\); + + un7_cntlto31_0_0 : CFG4 + generic map(INIT => x"FF10") + + port map(A => \cnt[25]_net_1\, B => \cnt[23]_net_1\, C => + \un14_cntlto31_0_a2\, D => \un7_cntlto31_0_a3\, Y => + un7_cntlto31_0_0_0); + + \cnt[0]\ : SLE + port map(D => \cnt_s[0]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[0]_net_1\); + + \cnt_RNIIRHIB[2]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[2]_net_1\, D => GND_net_1, FCI => \cnt_cry[1]\, + S => \cnt_s[2]\, Y => OPEN, FCO => \cnt_cry[2]\); + + \GND\ : GND + port map(Y => GND_net_1); + + \cnt_RNI8FOMB2[22]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[22]_net_1\, D => GND_net_1, FCI => + \cnt_cry[21]\, S => \cnt_s[22]\, Y => OPEN, FCO => + \cnt_cry[22]\); + + un7_cntlto31_0_a2_1 : CFG2 + generic map(INIT => x"2") + + port map(A => N_125_3, B => \cnt[6]_net_1\, Y => + \un7_cntlto31_0_a2_1\); + + \cnt[23]\ : SLE + port map(D => \cnt_s[23]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[23]_net_1\); + + \cnt_RNI2HMJ61[11]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[11]_net_1\, D => GND_net_1, FCI => + \cnt_cry[10]\, S => \cnt_s[11]\, Y => OPEN, FCO => + \cnt_cry[11]\); + + \cnt_RNI06AFE[3]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[3]_net_1\, D => GND_net_1, FCI => \cnt_cry[2]\, + S => \cnt_s[3]\, Y => OPEN, FCO => \cnt_cry[3]\); + + \cnt[20]\ : SLE + port map(D => \cnt_s[20]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[20]_net_1\); + + \cnt[13]\ : SLE + port map(D => \cnt_s[13]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[13]_net_1\); + + un14_cntlto31_0_o2_3 : CFG4 + generic map(INIT => x"7FFF") + + port map(A => \cnt[22]_net_1\, B => \cnt[21]_net_1\, C => + \cnt[20]_net_1\, D => \cnt[19]_net_1\, Y => + \un14_cntlto31_0_o2_3\); + + \cnt[18]\ : SLE + port map(D => \cnt_s[18]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[18]_net_1\); + + \cnt[7]\ : SLE + port map(D => \cnt_s[7]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[7]_net_1\); + + \cnt[10]\ : SLE + port map(D => \cnt_s[10]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[10]_net_1\); + + un14_cntlto31_0_a2_1_3 : CFG4 + generic map(INIT => x"0001") + + port map(A => \cnt[10]_net_1\, B => \cnt[9]_net_1\, C => + \cnt[8]_net_1\, D => \cnt[7]_net_1\, Y => N_125_3); + + \cnt[3]\ : SLE + port map(D => \cnt_s[3]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[3]_net_1\); + + \cnt[25]\ : SLE + port map(D => \cnt_s[25]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[25]_net_1\); + + un14_cntlto31_0_o3_0 : CFG4 + generic map(INIT => x"F7F5") + + port map(A => \cnt[15]_net_1\, B => \cnt[11]_net_1\, C => + \un14_cntlto31_0_o2_0\, D => N_125_3, Y => + \un14_cntlto31_0_o3_0\); + + \cnt_RNIFH2CH[4]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[4]_net_1\, D => GND_net_1, FCI => \cnt_cry[3]\, + S => \cnt_s[4]\, Y => OPEN, FCO => \cnt_cry[4]\); + + \cnt[22]\ : SLE + port map(D => \cnt_s[22]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[22]_net_1\); + + \cnt[15]\ : SLE + port map(D => \cnt_s[15]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[15]_net_1\); + + \cnt_RNIVTQ8K[5]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[5]_net_1\, D => GND_net_1, FCI => \cnt_cry[4]\, + S => \cnt_s[5]\, Y => OPEN, FCO => \cnt_cry[5]\); + + \cnt[24]\ : SLE + port map(D => \cnt_s[24]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[24]_net_1\); + + un7_cntlto31_0_a3 : CFG4 + generic map(INIT => x"000D") + + port map(A => \cnt[24]_net_1\, B => \un7_cntlto31_0_a2\, C + => \cnt[26]_net_1\, D => \cnt[25]_net_1\, Y => + \un7_cntlto31_0_a3\); + + un14_cntlto31_0_a2 : CFG3 + generic map(INIT => x"45") + + port map(A => \cnt[26]_net_1\, B => \un14_cntlto31_0_o2_3\, + C => \cnt[18]_net_1\, Y => \un14_cntlto31_0_a2\); + + \cnt_RNIP91P5[0]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[0]_net_1\, D => GND_net_1, FCI => cnt_cry_cy, S + => \cnt_s[0]\, Y => OPEN, FCO => \cnt_cry[0]\); + + \cnt_RNIELUI12[19]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[19]_net_1\, D => GND_net_1, FCI => + \cnt_cry[18]\, S => \cnt_s[19]\, Y => OPEN, FCO => + \cnt_cry[19]\); + + \cnt[5]\ : SLE + port map(D => \cnt_s[5]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[5]_net_1\); + + un7_cntlto31_0_a2 : CFG4 + generic map(INIT => x"0031") + + port map(A => \cnt[16]_net_1\, B => \cnt[17]_net_1\, C => + \un7_cntlto31_0_a2_0\, D => \cnt[23]_net_1\, Y => + \un7_cntlto31_0_a2\); + + \cnt[12]\ : SLE + port map(D => \cnt_s[12]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[12]_net_1\); + + \cnt_RNI9H17U1[18]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNIE29S2_Y, + C => \cnt[18]_net_1\, D => GND_net_1, FCI => + \cnt_cry[17]\, S => \cnt_s[18]\, Y => OPEN, FCO => + \cnt_cry[18]\); + + \cnt[14]\ : SLE + port map(D => \cnt_s[14]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[14]_net_1\); + + \cnt[21]\ : SLE + port map(D => \cnt_s[21]\, CLK => clk_c, EN => SW2_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[21]_net_1\); + + +end DEF_ARCH; + +library ieee; +use ieee.std_logic_1164.all; +library smartfusion2; +use smartfusion2.all; + +entity Reset_out is + + port( reset : out std_logic; + clk_c : in std_logic; + SW1_c : in std_logic; + SW2_c : in std_logic + ); + +end Reset_out; + +architecture DEF_ARCH of Reset_out is + + component VCC + port( Y : out std_logic + ); + end component; + + component CLKINT + port( A : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component GND + port( Y : out std_logic + ); + end component; + + component CFG2 + generic (INIT:std_logic_vector(3 downto 0) := x"0"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component SLE + port( D : in std_logic := 'U'; + CLK : in std_logic := 'U'; + EN : in std_logic := 'U'; + ALn : in std_logic := 'U'; + ADn : in std_logic := 'U'; + SLn : in std_logic := 'U'; + SD : in std_logic := 'U'; + LAT : in std_logic := 'U'; + Q : out std_logic + ); + end component; + + signal reset_0, VCC_net_1, un2_sw1_i_0, GND_net_1 + : std_logic; + +begin + + + \VCC\ : VCC + port map(Y => VCC_net_1); + + reset_RNIREK : CLKINT + port map(A => reset_0, Y => reset); + + \GND\ : GND + port map(Y => GND_net_1); + + reset_RNO : CFG2 + generic map(INIT => x"7") + + port map(A => SW1_c, B => SW2_c, Y => un2_sw1_i_0); + + \reset\ : SLE + port map(D => un2_sw1_i_0, CLK => clk_c, EN => VCC_net_1, + ALn => VCC_net_1, ADn => VCC_net_1, SLn => VCC_net_1, SD + => GND_net_1, LAT => GND_net_1, Q => reset_0); + + +end DEF_ARCH; + +library ieee; +use ieee.std_logic_1164.all; +library smartfusion2; +use smartfusion2.all; + +entity ClkGenNoSwitch is + + port( led0 : out std_logic; + reset : in std_logic; + clk_c : in std_logic + ); + +end ClkGenNoSwitch; + +architecture DEF_ARCH of ClkGenNoSwitch is + + component CFG3 + generic (INIT:std_logic_vector(7 downto 0) := x"00"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component ARI1 + generic (INIT:std_logic_vector(19 downto 0) := x"00000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + FCI : in std_logic := 'U'; + S : out std_logic; + Y : out std_logic; + FCO : out std_logic + ); + end component; + + component SLE + port( D : in std_logic := 'U'; + CLK : in std_logic := 'U'; + EN : in std_logic := 'U'; + ALn : in std_logic := 'U'; + ADn : in std_logic := 'U'; + SLn : in std_logic := 'U'; + SD : in std_logic := 'U'; + LAT : in std_logic := 'U'; + Q : out std_logic + ); + end component; + + component CFG4 + generic (INIT:std_logic_vector(15 downto 0) := x"0000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component VCC + port( Y : out std_logic + ); + end component; + + component GND + port( Y : out std_logic + ); + end component; + + component CFG2 + generic (INIT:std_logic_vector(3 downto 0) := x"0"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + signal VCC_net_1, \un7_cntlto31_0\, GND_net_1, + \cnt[0]_net_1\, \cnt_s[0]\, \cnt[1]_net_1\, \cnt_s[1]\, + \cnt[2]_net_1\, \cnt_s[2]\, \cnt[3]_net_1\, \cnt_s[3]\, + \cnt[4]_net_1\, \cnt_s[4]\, \cnt[5]_net_1\, \cnt_s[5]\, + \cnt[6]_net_1\, \cnt_s[6]\, \cnt[7]_net_1\, \cnt_s[7]\, + \cnt[8]_net_1\, \cnt_s[8]\, \cnt[9]_net_1\, \cnt_s[9]\, + \cnt[10]_net_1\, \cnt_s[10]\, \cnt[11]_net_1\, + \cnt_s[11]\, \cnt[12]_net_1\, \cnt_s[12]\, + \cnt[13]_net_1\, \cnt_s[13]\, \cnt[14]_net_1\, + \cnt_s[14]\, \cnt[15]_net_1\, \cnt_s[15]\, + \cnt[16]_net_1\, \cnt_s[16]\, \cnt[17]_net_1\, + \cnt_s[17]\, \cnt[18]_net_1\, \cnt_s[18]\, + \cnt[19]_net_1\, \cnt_s[19]\, \cnt[20]_net_1\, + \cnt_s[20]\, \cnt[21]_net_1\, \cnt_s[21]\, + \cnt[22]_net_1\, \cnt_s[22]\, \cnt[23]_net_1\, + \cnt_s[23]\, \cnt[24]_net_1\, \cnt_s[24]\, + \cnt[25]_net_1\, \cnt_s[25]\, N_39, \cnt_s[26]\, + cnt_cry_cy, un14_cntlto31_0_o3_RNINP5T1_Y, N_312_tz, N_16, + N_29, \cnt_cry[0]\, \cnt_cry[1]\, \cnt_cry[2]\, + \cnt_cry[3]\, \cnt_cry[4]\, \cnt_cry[5]\, \cnt_cry[6]\, + \cnt_cry[7]\, \cnt_cry[8]\, \cnt_cry[9]\, \cnt_cry[10]\, + \cnt_cry[11]\, \cnt_cry[12]\, \cnt_cry[13]\, + \cnt_cry[14]\, \cnt_cry[15]\, \cnt_cry[16]\, + \cnt_cry[17]\, \cnt_cry[18]\, \cnt_cry[19]\, + \cnt_cry[20]\, \cnt_cry[21]\, \cnt_cry[22]\, + \cnt_cry[23]\, \cnt_cry[24]\, N_9, N_6, N_30_3, N_30, + N_18, N_31, N_32, N_27 : std_logic; + +begin + + + un14_cntlto31_0_o2_0 : CFG3 + generic map(INIT => x"7F") + + port map(A => \cnt[14]_net_1\, B => \cnt[13]_net_1\, C => + \cnt[12]_net_1\, Y => N_6); + + \cnt_RNI9OAM51[15]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[15]_net_1\, D => GND_net_1, FCI => + \cnt_cry[14]\, S => \cnt_s[15]\, Y => OPEN, FCO => + \cnt_cry[15]\); + + \cnt[19]\ : SLE + port map(D => \cnt_s[19]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[19]_net_1\); + + \cnt_RNIO7H711[13]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[13]_net_1\, D => GND_net_1, FCI => + \cnt_cry[12]\, S => \cnt_s[13]\, Y => OPEN, FCO => + \cnt_cry[13]\); + + tmp_clk : SLE + port map(D => \un7_cntlto31_0\, CLK => clk_c, EN => + VCC_net_1, ALn => reset, ADn => VCC_net_1, SLn => + VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => led0); + + \cnt[2]\ : SLE + port map(D => \cnt_s[2]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[2]_net_1\); + + \cnt[8]\ : SLE + port map(D => \cnt_s[8]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[8]_net_1\); + + \cnt[26]\ : SLE + port map(D => \cnt_s[26]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => N_39); + + \cnt[1]\ : SLE + port map(D => \cnt_s[1]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[1]_net_1\); + + un14_cntlto31_0_o3_0_RNI6DVC1 : CFG4 + generic map(INIT => x"0073") + + port map(A => \cnt[16]_net_1\, B => \cnt[17]_net_1\, C => + N_18, D => \cnt[24]_net_1\, Y => N_312_tz); + + \cnt[11]\ : SLE + port map(D => \cnt_s[11]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[11]_net_1\); + + \cnt_RNI2JU9O[9]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[9]_net_1\, D => GND_net_1, FCI => \cnt_cry[8]\, + S => \cnt_s[9]\, Y => OPEN, FCO => \cnt_cry[9]\); + + \cnt_RNIQ8HCC1[18]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[18]_net_1\, D => GND_net_1, FCI => + \cnt_cry[17]\, S => \cnt_s[18]\, Y => OPEN, FCO => + \cnt_cry[18]\); + + un14_cntlto31_0_o3 : CFG4 + generic map(INIT => x"0FDF") + + port map(A => \cnt[23]_net_1\, B => N_9, C => + \cnt[25]_net_1\, D => \cnt[24]_net_1\, Y => N_16); + + un14_cntlto31_0_o3_RNINP5T1 : ARI1 + generic map(INIT => x"4CE0A") + + port map(A => N_312_tz, B => N_16, C => N_29, D => N_39, + FCI => VCC_net_1, S => OPEN, Y => + un14_cntlto31_0_o3_RNINP5T1_Y, FCO => cnt_cry_cy); + + \cnt[17]\ : SLE + port map(D => \cnt_s[17]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[17]_net_1\); + + \cnt_RNI3INT71[16]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[16]_net_1\, D => GND_net_1, FCI => + \cnt_cry[15]\, S => \cnt_s[16]\, Y => OPEN, FCO => + \cnt_cry[16]\); + + \cnt[16]\ : SLE + port map(D => \cnt_s[16]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[16]_net_1\); + + un7_cntlto31_0_a2_0 : CFG4 + generic map(INIT => x"3331") + + port map(A => \cnt[11]_net_1\, B => \cnt[15]_net_1\, C => + N_30, D => N_6, Y => N_31); + + \VCC\ : VCC + port map(Y => VCC_net_1); + + \cnt_RNIUC45A1[17]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[17]_net_1\, D => GND_net_1, FCI => + \cnt_cry[16]\, S => \cnt_s[17]\, Y => OPEN, FCO => + \cnt_cry[17]\); + + \cnt_RNI1H40V[12]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[12]_net_1\, D => GND_net_1, FCI => + \cnt_cry[11]\, S => \cnt_s[12]\, Y => OPEN, FCO => + \cnt_cry[12]\); + + \cnt[6]\ : SLE + port map(D => \cnt_s[6]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[6]_net_1\); + + \cnt_RNIP97AL1[22]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[22]_net_1\, D => GND_net_1, FCI => + \cnt_cry[21]\, S => \cnt_s[22]\, Y => OPEN, FCO => + \cnt_cry[22]\); + + \cnt_RNIM6BHQ[10]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[10]_net_1\, D => GND_net_1, FCI => \cnt_cry[9]\, + S => \cnt_s[10]\, Y => OPEN, FCO => \cnt_cry[10]\); + + \cnt[4]\ : SLE + port map(D => \cnt_s[4]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[4]_net_1\); + + \cnt[9]\ : SLE + port map(D => \cnt_s[9]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[9]_net_1\); + + un7_cntlto31_0 : CFG4 + generic map(INIT => x"FF10") + + port map(A => \cnt[25]_net_1\, B => \cnt[23]_net_1\, C => + N_29, D => N_27, Y => \un7_cntlto31_0\); + + \cnt[0]\ : SLE + port map(D => \cnt_s[0]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[0]_net_1\); + + \cnt_RNIBVIQJ[7]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[7]_net_1\, D => GND_net_1, FCI => \cnt_cry[6]\, + S => \cnt_s[7]\, Y => OPEN, FCO => \cnt_cry[7]\); + + \cnt_RNIGPH3D[4]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[4]_net_1\, D => GND_net_1, FCI => \cnt_cry[3]\, + S => \cnt_s[4]\, Y => OPEN, FCO => \cnt_cry[4]\); + + \GND\ : GND + port map(Y => GND_net_1); + + \cnt_RNIQAR44[0]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[0]_net_1\, D => GND_net_1, FCI => cnt_cry_cy, S + => \cnt_s[0]\, Y => OPEN, FCO => \cnt_cry[0]\); + + \cnt_RNICRBRG1[20]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[20]_net_1\, D => GND_net_1, FCI => + \cnt_cry[19]\, S => \cnt_s[20]\, Y => OPEN, FCO => + \cnt_cry[20]\); + + \cnt_RNI3G6K8[2]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[2]_net_1\, D => GND_net_1, FCI => \cnt_cry[1]\, + S => \cnt_s[2]\, Y => OPEN, FCO => \cnt_cry[2]\); + + un7_cntlto31_0_a2_1 : CFG2 + generic map(INIT => x"2") + + port map(A => N_30_3, B => \cnt[6]_net_1\, Y => N_30); + + \cnt[23]\ : SLE + port map(D => \cnt_s[23]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[23]_net_1\); + + \cnt_RNIOF7BF[5]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[5]_net_1\, D => GND_net_1, FCI => \cnt_cry[4]\, + S => \cnt_s[5]\, Y => OPEN, FCO => \cnt_cry[5]\); + + \cnt[20]\ : SLE + port map(D => \cnt_s[20]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[20]_net_1\); + + \cnt_RNIMO82M[8]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[8]_net_1\, D => GND_net_1, FCI => \cnt_cry[7]\, + S => \cnt_s[8]\, Y => OPEN, FCO => \cnt_cry[8]\); + + \cnt[13]\ : SLE + port map(D => \cnt_s[13]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[13]_net_1\); + + un14_cntlto31_0_o2_3 : CFG4 + generic map(INIT => x"7FFF") + + port map(A => \cnt[22]_net_1\, B => \cnt[21]_net_1\, C => + \cnt[20]_net_1\, D => \cnt[19]_net_1\, Y => N_9); + + \cnt[18]\ : SLE + port map(D => \cnt_s[18]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[18]_net_1\); + + \cnt_RNI4NG0S1[25]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[25]_net_1\, D => GND_net_1, FCI => + \cnt_cry[24]\, S => \cnt_s[25]\, Y => OPEN, FCO => + \cnt_s[26]\); + + \cnt[7]\ : SLE + port map(D => \cnt_s[7]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[7]_net_1\); + + \cnt[10]\ : SLE + port map(D => \cnt_s[10]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[10]_net_1\); + + \cnt_RNI94SRA[3]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[3]_net_1\, D => GND_net_1, FCI => \cnt_cry[2]\, + S => \cnt_s[3]\, Y => OPEN, FCO => \cnt_cry[3]\); + + \cnt_RNIN5UJE1[19]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[19]_net_1\, D => GND_net_1, FCI => + \cnt_cry[18]\, S => \cnt_s[19]\, Y => OPEN, FCO => + \cnt_cry[19]\); + + \cnt_RNIH2LHN1[23]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[23]_net_1\, D => GND_net_1, FCI => + \cnt_cry[22]\, S => \cnt_s[23]\, Y => OPEN, FCO => + \cnt_cry[23]\); + + \cnt_RNIAS2PP1[24]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[24]_net_1\, D => GND_net_1, FCI => + \cnt_cry[23]\, S => \cnt_s[24]\, Y => OPEN, FCO => + \cnt_cry[24]\); + + un14_cntlto31_0_a2_1_3 : CFG4 + generic map(INIT => x"0001") + + port map(A => \cnt[10]_net_1\, B => \cnt[9]_net_1\, C => + \cnt[8]_net_1\, D => \cnt[7]_net_1\, Y => N_30_3); + + \cnt[3]\ : SLE + port map(D => \cnt_s[3]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[3]_net_1\); + + \cnt[25]\ : SLE + port map(D => \cnt_s[25]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[25]_net_1\); + + \cnt_RNIUSGC6[1]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[1]_net_1\, D => GND_net_1, FCI => \cnt_cry[0]\, + S => \cnt_s[1]\, Y => OPEN, FCO => \cnt_cry[1]\); + + \cnt_RNIGVTE31[14]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[14]_net_1\, D => GND_net_1, FCI => + \cnt_cry[13]\, S => \cnt_s[14]\, Y => OPEN, FCO => + \cnt_cry[14]\); + + \cnt_RNI17TIH[6]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[6]_net_1\, D => GND_net_1, FCI => \cnt_cry[5]\, + S => \cnt_s[6]\, Y => OPEN, FCO => \cnt_cry[6]\); + + \cnt_RNIBRNOS[11]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[11]_net_1\, D => GND_net_1, FCI => + \cnt_cry[10]\, S => \cnt_s[11]\, Y => OPEN, FCO => + \cnt_cry[11]\); + + \cnt_RNI2IP2J1[21]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNINP5T1_Y, + C => \cnt[21]_net_1\, D => GND_net_1, FCI => + \cnt_cry[20]\, S => \cnt_s[21]\, Y => OPEN, FCO => + \cnt_cry[21]\); + + un14_cntlto31_0_o3_0 : CFG4 + generic map(INIT => x"FF73") + + port map(A => \cnt[11]_net_1\, B => \cnt[15]_net_1\, C => + N_30_3, D => N_6, Y => N_18); + + \cnt[22]\ : SLE + port map(D => \cnt_s[22]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[22]_net_1\); + + \cnt[15]\ : SLE + port map(D => \cnt_s[15]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[15]_net_1\); + + \cnt[24]\ : SLE + port map(D => \cnt_s[24]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[24]_net_1\); + + un7_cntlto31_0_a3 : CFG4 + generic map(INIT => x"1011") + + port map(A => \cnt[25]_net_1\, B => N_39, C => N_32, D => + \cnt[24]_net_1\, Y => N_27); + + un14_cntlto31_0_a2 : CFG3 + generic map(INIT => x"45") + + port map(A => N_39, B => N_9, C => \cnt[18]_net_1\, Y => + N_29); + + \cnt[5]\ : SLE + port map(D => \cnt_s[5]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[5]_net_1\); + + un7_cntlto31_0_a2 : CFG4 + generic map(INIT => x"0031") + + port map(A => \cnt[16]_net_1\, B => \cnt[17]_net_1\, C => + N_31, D => \cnt[23]_net_1\, Y => N_32); + + \cnt[12]\ : SLE + port map(D => \cnt_s[12]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[12]_net_1\); + + \cnt[14]\ : SLE + port map(D => \cnt_s[14]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[14]_net_1\); + + \cnt[21]\ : SLE + port map(D => \cnt_s[21]\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[21]_net_1\); + + +end DEF_ARCH; + +library ieee; +use ieee.std_logic_1164.all; +library smartfusion2; +use smartfusion2.all; + +entity Display is + + port( green_led1_c : out std_logic; + reset : in std_logic; + clk_c : in std_logic; + red_led2_c : out std_logic; + SW2_c : in std_logic; + SW1_c : in std_logic; + led1 : in std_logic; + led2 : in std_logic; + led : in std_logic; + led0 : in std_logic + ); + +end Display; + +architecture DEF_ARCH of Display is + + component CFG4 + generic (INIT:std_logic_vector(15 downto 0) := x"0000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component SLE + port( D : in std_logic := 'U'; + CLK : in std_logic := 'U'; + EN : in std_logic := 'U'; + ALn : in std_logic := 'U'; + ADn : in std_logic := 'U'; + SLn : in std_logic := 'U'; + SD : in std_logic := 'U'; + LAT : in std_logic := 'U'; + Q : out std_logic + ); + end component; + + component VCC + port( Y : out std_logic + ); + end component; + + component GND + port( Y : out std_logic + ); + end component; + + signal VCC_net_1, \green_led1_4\, GND_net_1, \red_led2_3\ + : std_logic; + +begin + + + red_led2_3 : CFG4 + generic map(INIT => x"F2D0") + + port map(A => SW2_c, B => SW1_c, C => led1, D => led2, Y + => \red_led2_3\); + + red_led2 : SLE + port map(D => \red_led2_3\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => red_led2_c); + + \VCC\ : VCC + port map(Y => VCC_net_1); + + green_led1 : SLE + port map(D => \green_led1_4\, CLK => clk_c, EN => VCC_net_1, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => green_led1_c); + + \GND\ : GND + port map(Y => GND_net_1); + + green_led1_4 : CFG4 + generic map(INIT => x"FB40") + + port map(A => SW2_c, B => SW1_c, C => led, D => led0, Y => + \green_led1_4\); + + +end DEF_ARCH; + +library ieee; +use ieee.std_logic_1164.all; +library smartfusion2; +use smartfusion2.all; + +entity ClkGen is + + port( led : out std_logic; + reset : in std_logic; + clk_c : in std_logic; + SW1_c : in std_logic + ); + +end ClkGen; + +architecture DEF_ARCH of ClkGen is + + component ARI1 + generic (INIT:std_logic_vector(19 downto 0) := x"00000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + FCI : in std_logic := 'U'; + S : out std_logic; + Y : out std_logic; + FCO : out std_logic + ); + end component; + + component CFG3 + generic (INIT:std_logic_vector(7 downto 0) := x"00"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component SLE + port( D : in std_logic := 'U'; + CLK : in std_logic := 'U'; + EN : in std_logic := 'U'; + ALn : in std_logic := 'U'; + ADn : in std_logic := 'U'; + SLn : in std_logic := 'U'; + SD : in std_logic := 'U'; + LAT : in std_logic := 'U'; + Q : out std_logic + ); + end component; + + component CFG4 + generic (INIT:std_logic_vector(15 downto 0) := x"0000"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + C : in std_logic := 'U'; + D : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component VCC + port( Y : out std_logic + ); + end component; + + component GND + port( Y : out std_logic + ); + end component; + + component CFG2 + generic (INIT:std_logic_vector(3 downto 0) := x"0"); + + port( A : in std_logic := 'U'; + B : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + signal VCC_net_1, \un7_cntlto31_0_0\, GND_net_1, + \cnt[0]_net_1\, \cnt_s[0]\, \cnt[1]_net_1\, \cnt_s[1]\, + \cnt[2]_net_1\, \cnt_s[2]\, \cnt[3]_net_1\, \cnt_s[3]\, + \cnt[4]_net_1\, \cnt_s[4]\, \cnt[5]_net_1\, \cnt_s[5]\, + \cnt[6]_net_1\, \cnt_s[6]\, \cnt[7]_net_1\, \cnt_s[7]\, + \cnt[8]_net_1\, \cnt_s[8]\, \cnt[9]_net_1\, \cnt_s[9]\, + \cnt[10]_net_1\, \cnt_s[10]\, \cnt[11]_net_1\, + \cnt_s[11]\, \cnt[12]_net_1\, \cnt_s[12]\, + \cnt[13]_net_1\, \cnt_s[13]\, \cnt[14]_net_1\, + \cnt_s[14]\, \cnt[15]_net_1\, \cnt_s[15]\, + \cnt[16]_net_1\, \cnt_s[16]\, \cnt[17]_net_1\, + \cnt_s[17]\, \cnt[18]_net_1\, \cnt_s[18]\, + \cnt[19]_net_1\, \cnt_s[19]\, \cnt[20]_net_1\, + \cnt_s[20]\, \cnt[21]_net_1\, \cnt_s[21]\, + \cnt[22]_net_1\, \cnt_s[22]\, \cnt[23]_net_1\, + \cnt_s[23]\, \cnt[24]_net_1\, \cnt_s[24]\, + \cnt[25]_net_1\, \cnt_s[25]\, cnt_cry_cy, + un14_cntlto31_0_o3_RNI33E32_Y, N_313_tz, + un14_cntlto31_0_o3_1, un14_cntlto31_0_a2_0, \cnt_cry[0]\, + \cnt_cry[1]\, \cnt_cry[2]\, \cnt_cry[3]\, \cnt_cry[4]\, + \cnt_cry[5]\, \cnt_cry[6]\, \cnt_cry[7]\, \cnt_cry[8]\, + \cnt_cry[9]\, \cnt_cry[10]\, \cnt_cry[11]\, \cnt_cry[12]\, + \cnt_cry[13]\, \cnt_cry[14]\, \cnt_cry[15]\, + \cnt_cry[16]\, \cnt_cry[17]\, \cnt_cry[18]\, + \cnt_cry[19]\, \cnt_cry[20]\, \cnt_cry[21]\, + \cnt_cry[22]\, \cnt_cry[23]\, un14_cntlto31_0_o2_3_0, + un14_cntlto31_0_o2_0_0, N_59_3, un7_cntlto31_0_a2_1_0, + un14_cntlto31_0_o3_0_0, un7_cntlto31_0_a2_0_0, + un7_cntlto31_0_a2_2, un7_cntlto31_0_a3_0 : std_logic; + +begin + + + \cnt_RNIJCPBI1[19]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[19]_net_1\, D => GND_net_1, FCI => + \cnt_cry[18]\, S => \cnt_s[19]\, Y => OPEN, FCO => + \cnt_cry[19]\); + + \cnt_RNIBP7DB1[16]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[16]_net_1\, D => GND_net_1, FCI => + \cnt_cry[15]\, S => \cnt_s[16]\, Y => OPEN, FCO => + \cnt_cry[16]\); + + un14_cntlto31_0_o2_0 : CFG3 + generic map(INIT => x"7F") + + port map(A => \cnt[13]_net_1\, B => \cnt[12]_net_1\, C => + \cnt[11]_net_1\, Y => un14_cntlto31_0_o2_0_0); + + \cnt[19]\ : SLE + port map(D => \cnt_s[19]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[19]_net_1\); + + \cnt_RNI9GDAP1[22]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[22]_net_1\, D => GND_net_1, FCI => + \cnt_cry[21]\, S => \cnt_s[22]\, Y => OPEN, FCO => + \cnt_cry[22]\); + + \cnt_RNI07SO61[14]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[14]_net_1\, D => GND_net_1, FCI => + \cnt_cry[13]\, S => \cnt_s[14]\, Y => OPEN, FCO => + \cnt_cry[14]\); + + \cnt_RNI5DE4C[3]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[3]_net_1\, D => GND_net_1, FCI => \cnt_cry[2]\, + S => \cnt_s[3]\, Y => OPEN, FCO => \cnt_cry[3]\); + + tmp_clk : SLE + port map(D => \un7_cntlto31_0_0\, CLK => clk_c, EN => SW1_c, + ALn => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => led); + + \cnt[2]\ : SLE + port map(D => \cnt_s[2]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[2]_net_1\); + + \cnt[8]\ : SLE + port map(D => \cnt_s[8]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[8]_net_1\); + + \cnt[1]\ : SLE + port map(D => \cnt_s[1]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[1]_net_1\); + + \cnt_RNI26U37[1]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[1]_net_1\, D => GND_net_1, FCI => \cnt_cry[0]\, + S => \cnt_s[1]\, Y => OPEN, FCO => \cnt_cry[1]\); + + \cnt[11]\ : SLE + port map(D => \cnt_s[11]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[11]_net_1\); + + un14_cntlto31_0_o3 : CFG4 + generic map(INIT => x"0FDF") + + port map(A => \cnt[22]_net_1\, B => un14_cntlto31_0_o2_3_0, + C => \cnt[24]_net_1\, D => \cnt[23]_net_1\, Y => + un14_cntlto31_0_o3_1); + + \cnt_RNI8IMKE[4]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[4]_net_1\, D => GND_net_1, FCI => \cnt_cry[3]\, + S => \cnt_s[4]\, Y => OPEN, FCO => \cnt_cry[4]\); + + \cnt[17]\ : SLE + port map(D => \cnt_s[17]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[17]_net_1\); + + un14_cntlto31_0_o3_RNI33E32 : ARI1 + generic map(INIT => x"4F444") + + port map(A => N_313_tz, B => \cnt[25]_net_1\, C => + un14_cntlto31_0_o3_1, D => un14_cntlto31_0_a2_0, FCI => + VCC_net_1, S => OPEN, Y => un14_cntlto31_0_o3_RNI33E32_Y, + FCO => cnt_cry_cy); + + \cnt[16]\ : SLE + port map(D => \cnt_s[16]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[16]_net_1\); + + un7_cntlto31_0_a2_0 : CFG4 + generic map(INIT => x"5551") + + port map(A => \cnt[14]_net_1\, B => \cnt[10]_net_1\, C => + un14_cntlto31_0_o2_0_0, D => un7_cntlto31_0_a2_1_0, Y => + un7_cntlto31_0_a2_0_0); + + \cnt_RNI6RV5R[9]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[9]_net_1\, D => GND_net_1, FCI => \cnt_cry[8]\, + S => \cnt_s[9]\, Y => OPEN, FCO => \cnt_cry[9]\); + + \VCC\ : VCC + port map(Y => VCC_net_1); + + \cnt[6]\ : SLE + port map(D => \cnt_s[6]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[6]_net_1\); + + \cnt[4]\ : SLE + port map(D => \cnt_s[4]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[4]_net_1\); + + \cnt[9]\ : SLE + port map(D => \cnt_s[9]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[9]_net_1\); + + un7_cntlto31_0_0 : CFG4 + generic map(INIT => x"FF10") + + port map(A => \cnt[24]_net_1\, B => \cnt[22]_net_1\, C => + un14_cntlto31_0_a2_0, D => un7_cntlto31_0_a3_0, Y => + \un7_cntlto31_0_0\); + + \cnt[0]\ : SLE + port map(D => \cnt_s[0]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[0]_net_1\); + + \cnt_RNIT8KKR1[23]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[23]_net_1\, D => GND_net_1, FCI => + \cnt_cry[22]\, S => \cnt_s[23]\, Y => OPEN, FCO => + \cnt_cry[23]\); + + \cnt_RNI420MK1[20]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[20]_net_1\, D => GND_net_1, FCI => + \cnt_cry[19]\, S => \cnt_s[20]\, Y => OPEN, FCO => + \cnt_cry[20]\); + + \cnt_RNICOU4H[5]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[5]_net_1\, D => GND_net_1, FCI => \cnt_cry[4]\, + S => \cnt_s[5]\, Y => OPEN, FCO => \cnt_cry[5]\); + + \GND\ : GND + port map(Y => GND_net_1); + + un7_cntlto31_0_a2_1 : CFG2 + generic map(INIT => x"2") + + port map(A => N_59_3, B => \cnt[5]_net_1\, Y => + un7_cntlto31_0_a2_1_0); + + \cnt[23]\ : SLE + port map(D => \cnt_s[23]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[23]_net_1\); + + \cnt_RNI396K9[2]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[2]_net_1\, D => GND_net_1, FCI => \cnt_cry[1]\, + S => \cnt_s[2]\, Y => OPEN, FCO => \cnt_cry[2]\); + + \cnt[20]\ : SLE + port map(D => \cnt_s[20]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[20]_net_1\); + + \cnt_RNI2KDND1[17]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[17]_net_1\, D => GND_net_1, FCI => + \cnt_cry[16]\, S => \cnt_s[17]\, Y => OPEN, FCO => + \cnt_cry[17]\); + + \cnt_RNILV1391[15]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[15]_net_1\, D => GND_net_1, FCI => + \cnt_cry[14]\, S => \cnt_s[15]\, Y => OPEN, FCO => + \cnt_cry[15]\); + + \cnt_RNIQFJ1G1[18]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[18]_net_1\, D => GND_net_1, FCI => + \cnt_cry[17]\, S => \cnt_s[18]\, Y => OPEN, FCO => + \cnt_cry[18]\); + + \cnt[13]\ : SLE + port map(D => \cnt_s[13]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[13]_net_1\); + + \cnt_RNIN7F5M[7]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[7]_net_1\, D => GND_net_1, FCI => \cnt_cry[6]\, + S => \cnt_s[7]\, Y => OPEN, FCO => \cnt_cry[7]\); + + \cnt_RNI73BQV[11]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[11]_net_1\, D => GND_net_1, FCI => + \cnt_cry[10]\, S => \cnt_s[11]\, Y => OPEN, FCO => + \cnt_cry[11]\); + + un14_cntlto31_0_o2_3 : CFG4 + generic map(INIT => x"7FFF") + + port map(A => \cnt[21]_net_1\, B => \cnt[20]_net_1\, C => + \cnt[19]_net_1\, D => \cnt[18]_net_1\, Y => + un14_cntlto31_0_o2_3_0); + + \cnt[18]\ : SLE + port map(D => \cnt_s[18]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[18]_net_1\); + + \cnt[7]\ : SLE + port map(D => \cnt_s[7]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[7]_net_1\); + + \cnt[10]\ : SLE + port map(D => \cnt_s[10]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[10]_net_1\); + + \cnt_RNICFME41[13]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[13]_net_1\, D => GND_net_1, FCI => + \cnt_cry[12]\, S => \cnt_s[13]\, Y => OPEN, FCO => + \cnt_cry[13]\); + + \cnt_RNIHV6LJ[6]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[6]_net_1\, D => GND_net_1, FCI => \cnt_cry[5]\, + S => \cnt_s[6]\, Y => OPEN, FCO => \cnt_cry[6]\); + + un14_cntlto31_0_o3_0_RNI3K631 : CFG4 + generic map(INIT => x"0073") + + port map(A => \cnt[15]_net_1\, B => \cnt[16]_net_1\, C => + un14_cntlto31_0_o3_0_0, D => \cnt[23]_net_1\, Y => + N_313_tz); + + un14_cntlto31_0_a2_1_3 : CFG4 + generic map(INIT => x"0001") + + port map(A => \cnt[9]_net_1\, B => \cnt[8]_net_1\, C => + \cnt[7]_net_1\, D => \cnt[6]_net_1\, Y => N_59_3); + + \cnt[3]\ : SLE + port map(D => \cnt_s[3]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[3]_net_1\); + + \cnt[25]\ : SLE + port map(D => \cnt_s[25]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[25]_net_1\); + + \cnt_RNIUGNLO[8]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[8]_net_1\, D => GND_net_1, FCI => \cnt_cry[7]\, + S => \cnt_s[8]\, Y => OPEN, FCO => \cnt_cry[8]\); + + \cnt_RNIME5GT[10]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[10]_net_1\, D => GND_net_1, FCI => \cnt_cry[9]\, + S => \cnt_s[10]\, Y => OPEN, FCO => \cnt_cry[10]\); + + \cnt_RNII2RUT1[24]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[24]_net_1\, D => GND_net_1, FCI => + \cnt_cry[23]\, S => \cnt_s[24]\, Y => OPEN, FCO => + \cnt_s[25]\); + + \cnt_RNI24MJ4[0]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[0]_net_1\, D => GND_net_1, FCI => cnt_cry_cy, S + => \cnt_s[0]\, Y => OPEN, FCO => \cnt_cry[0]\); + + \cnt_RNIMO60N1[21]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[21]_net_1\, D => GND_net_1, FCI => + \cnt_cry[20]\, S => \cnt_s[21]\, Y => OPEN, FCO => + \cnt_cry[21]\); + + un14_cntlto31_0_o3_0 : CFG4 + generic map(INIT => x"F7F5") + + port map(A => \cnt[14]_net_1\, B => \cnt[10]_net_1\, C => + un14_cntlto31_0_o2_0_0, D => N_59_3, Y => + un14_cntlto31_0_o3_0_0); + + \cnt_RNIPOG421[12]\ : ARI1 + generic map(INIT => x"48800") + + port map(A => VCC_net_1, B => un14_cntlto31_0_o3_RNI33E32_Y, + C => \cnt[12]_net_1\, D => GND_net_1, FCI => + \cnt_cry[11]\, S => \cnt_s[12]\, Y => OPEN, FCO => + \cnt_cry[12]\); + + \cnt[22]\ : SLE + port map(D => \cnt_s[22]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[22]_net_1\); + + \cnt[15]\ : SLE + port map(D => \cnt_s[15]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[15]_net_1\); + + \cnt[24]\ : SLE + port map(D => \cnt_s[24]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[24]_net_1\); + + un7_cntlto31_0_a3 : CFG4 + generic map(INIT => x"000D") + + port map(A => \cnt[23]_net_1\, B => un7_cntlto31_0_a2_2, C + => \cnt[25]_net_1\, D => \cnt[24]_net_1\, Y => + un7_cntlto31_0_a3_0); + + un14_cntlto31_0_a2 : CFG3 + generic map(INIT => x"45") + + port map(A => \cnt[25]_net_1\, B => un14_cntlto31_0_o2_3_0, + C => \cnt[17]_net_1\, Y => un14_cntlto31_0_a2_0); + + \cnt[5]\ : SLE + port map(D => \cnt_s[5]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[5]_net_1\); + + un7_cntlto31_0_a2 : CFG4 + generic map(INIT => x"0031") + + port map(A => \cnt[15]_net_1\, B => \cnt[16]_net_1\, C => + un7_cntlto31_0_a2_0_0, D => \cnt[22]_net_1\, Y => + un7_cntlto31_0_a2_2); + + \cnt[12]\ : SLE + port map(D => \cnt_s[12]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[12]_net_1\); + + \cnt[14]\ : SLE + port map(D => \cnt_s[14]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[14]_net_1\); + + \cnt[21]\ : SLE + port map(D => \cnt_s[21]\, CLK => clk_c, EN => SW1_c, ALn + => reset, ADn => VCC_net_1, SLn => VCC_net_1, SD => + GND_net_1, LAT => GND_net_1, Q => \cnt[21]_net_1\); + + +end DEF_ARCH; + +library ieee; +use ieee.std_logic_1164.all; +library smartfusion2; +use smartfusion2.all; + +entity LedBlinkingDSpeed is + + port( clk : in std_logic; + SW1 : in std_logic; + SW2 : in std_logic; + green_led1 : out std_logic; + red_led1 : out std_logic; + green_led2 : out std_logic; + red_led2 : out std_logic + ); + +end LedBlinkingDSpeed; + +architecture DEF_ARCH of LedBlinkingDSpeed is + + component OUTBUF + generic (IOSTD:string := ""); + + port( D : in std_logic := 'U'; + PAD : out std_logic + ); + end component; + + component ClkGenNoSwitch_1 + port( led1 : out std_logic; + reset : in std_logic := 'U'; + clk_c : in std_logic := 'U' + ); + end component; + + component ClkGen_1 + port( led2 : out std_logic; + reset : in std_logic := 'U'; + clk_c : in std_logic := 'U'; + SW2_c : in std_logic := 'U' + ); + end component; + + component INBUF + generic (IOSTD:string := ""); + + port( PAD : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component Reset_out + port( reset : out std_logic; + clk_c : in std_logic := 'U'; + SW1_c : in std_logic := 'U'; + SW2_c : in std_logic := 'U' + ); + end component; + + component ClkGenNoSwitch + port( led0 : out std_logic; + reset : in std_logic := 'U'; + clk_c : in std_logic := 'U' + ); + end component; + + component GND + port( Y : out std_logic + ); + end component; + + component CLKINT + port( A : in std_logic := 'U'; + Y : out std_logic + ); + end component; + + component VCC + port( Y : out std_logic + ); + end component; + + component Display + port( green_led1_c : out std_logic; + reset : in std_logic := 'U'; + clk_c : in std_logic := 'U'; + red_led2_c : out std_logic; + SW2_c : in std_logic := 'U'; + SW1_c : in std_logic := 'U'; + led1 : in std_logic := 'U'; + led2 : in std_logic := 'U'; + led : in std_logic := 'U'; + led0 : in std_logic := 'U' + ); + end component; + + component ClkGen + port( led : out std_logic; + reset : in std_logic := 'U'; + clk_c : in std_logic := 'U'; + SW1_c : in std_logic := 'U' + ); + end component; + + signal reset, GND_net_1, VCC_net_1, led0, led, led1, led2, + clk_c, SW1_c, SW2_c, green_led1_c, red_led2_c, \clk_ibuf\ + : std_logic; + + for all : ClkGenNoSwitch_1 + Use entity work.ClkGenNoSwitch_1(DEF_ARCH); + for all : ClkGen_1 + Use entity work.ClkGen_1(DEF_ARCH); + for all : Reset_out + Use entity work.Reset_out(DEF_ARCH); + for all : ClkGenNoSwitch + Use entity work.ClkGenNoSwitch(DEF_ARCH); + for all : Display + Use entity work.Display(DEF_ARCH); + for all : ClkGen + Use entity work.ClkGen(DEF_ARCH); +begin + + + red_led2_obuf : OUTBUF + port map(D => red_led2_c, PAD => red_led2); + + Initial_blinking_SW2 : ClkGenNoSwitch_1 + port map(led1 => led1, reset => reset, clk_c => clk_c); + + Fast_clk_SW2 : ClkGen_1 + port map(led2 => led2, reset => reset, clk_c => clk_c, + SW2_c => SW2_c); + + clk_ibuf : INBUF + port map(PAD => clk, Y => \clk_ibuf\); + + Clear_outputs : Reset_out + port map(reset => reset, clk_c => clk_c, SW1_c => SW1_c, + SW2_c => SW2_c); + + red_led1_obuf : OUTBUF + port map(D => GND_net_1, PAD => red_led1); + + Initial_blinking_SW1 : ClkGenNoSwitch + port map(led0 => led0, reset => reset, clk_c => clk_c); + + green_led1_obuf : OUTBUF + port map(D => green_led1_c, PAD => green_led1); + + \GND\ : GND + port map(Y => GND_net_1); + + clk_ibuf_RNIVTI2 : CLKINT + port map(A => \clk_ibuf\, Y => clk_c); + + \VCC\ : VCC + port map(Y => VCC_net_1); + + green_led2_obuf : OUTBUF + port map(D => GND_net_1, PAD => green_led2); + + SW2_ibuf : INBUF + port map(PAD => SW2, Y => SW2_c); + + Display_out : Display + port map(green_led1_c => green_led1_c, reset => reset, + clk_c => clk_c, red_led2_c => red_led2_c, SW2_c => SW2_c, + SW1_c => SW1_c, led1 => led1, led2 => led2, led => led, + led0 => led0); + + SW1_ibuf : INBUF + port map(PAD => SW1, Y => SW1_c); + + Fast_clk_SW1 : ClkGen + port map(led => led, reset => reset, clk_c => clk_c, SW1_c + => SW1_c); + + +end DEF_ARCH; diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed_multi_srs_gen.htm b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_multi_srs_gen.htm new file mode 100644 index 0000000..9733aaf --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_multi_srs_gen.htm @@ -0,0 +1,9 @@ + + + syntmp/LedBlinkingDSpeed_multi_srs_gen_srr.htm log file + + + + + + diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed_scck.rpt b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_scck.rpt new file mode 100644 index 0000000..989b8b1 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_scck.rpt @@ -0,0 +1,28 @@ +# Synopsys Constraint Checker(syntax only), version mapact, Build 1659R, built Dec 10 2015 +# Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +# Written on Sun Oct 23 02:59:32 2016 + + +##### DESIGN INFO ####################################################### + +Top View: "LedBlinkingDSpeed" +Constraint File(s): "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc" + +#Run constraint checker to find more issues with constraints. +######################################################################### + + + +No issues found in constraint syntax. + + + +Clock Summary +************* + +Start Requested Requested Clock Clock +Clock Frequency Period Type Group +----------------------------------------------------------------------------------- +LedBlinkingDSpeed|clk 50.0 MHz 20.000 declared default_clkgroup +=================================================================================== diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed_sdc.sdc b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_sdc.sdc new file mode 100644 index 0000000..1fd91e9 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_sdc.sdc @@ -0,0 +1,50 @@ +# Written by Synplify Pro version mapact, Build 1659R. Synopsys Run ID: sid1477216772 +# Top Level Design Parameters + +# Clocks +create_clock -period 20.000 -waveform {0.000 10.000} -name {LedBlinkingDSpeed|clk} [get_ports {clk}] + +# Virtual Clocks + +# Generated Clocks + +# Paths Between Clocks + +# Multicycle Constraints + +# Point-to-point Delay Constraints + +# False Path Constraints + +# Output Load Constraints + +# Driving Cell Constraints + +# Input Delay Constraints + +# Output Delay Constraints + +# Wire Loads + +# Other Constraints + +# syn_hier Attributes + +# set_case Attributes + +# Clock Delay Constraints + +# syn_mode Attributes + +# Cells + +# Port DRC Rules + +# Input Transition Constraints + +# Unused constraints (intentionally commented out) + +# Non-forward-annotatable constraints (intentionally commented out) + +# Block Path constraints + diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.bak b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.bak new file mode 100644 index 0000000..e474318 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.bak @@ -0,0 +1,70 @@ +#-- Synopsys, Inc. +#-- Version J-2015.03M-SP1-2 +#-- Project file C:\Users\ashj\Documents\LEARNING\Microsemi\Lab2_VHDL\synthesis\LedBlinkingDSpeed_syn.prj + +#project files +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/ClkGen.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/ClkGenNoSwitch.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/Display.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/Reset_out.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd" +add_file -fpga_constraint "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc" + + + +#implementation: "synthesis" +impl -add synthesis -type fpga + +#device options +set_option -technology IGLOO2 +set_option -part M2GL025 +set_option -package VF256 +set_option -speed_grade STD +set_option -part_companion "" + +#compilation/mapping options +set_option -use_fsm_explorer 0 +set_option -top_module "work.LedBlinkingDSpeed" + +# mapper_options +set_option -frequency 100.000 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# actel_options +set_option -rw_check_on_ram 0 + +# Microsemi G4 +set_option -run_prop_extract 1 +set_option -maxfan 10000 +set_option -clock_globalthreshold 2 +set_option -async_globalthreshold 12 +set_option -globalthreshold 5000 +set_option -low_power_ram_decomp 0 +set_option -disable_io_insertion 0 +set_option -opcond COMTC +set_option -retiming 0 +set_option -report_path 4000 +set_option -update_models_cp 0 +set_option -preserve_registers 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +# Compiler Options +set_option -vhdl2008 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./LedBlinkingDSpeed.edn" +impl -active "synthesis" diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.prj b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.prj new file mode 100644 index 0000000..e474318 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.prj @@ -0,0 +1,70 @@ +#-- Synopsys, Inc. +#-- Version J-2015.03M-SP1-2 +#-- Project file C:\Users\ashj\Documents\LEARNING\Microsemi\Lab2_VHDL\synthesis\LedBlinkingDSpeed_syn.prj + +#project files +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/ClkGen.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/ClkGenNoSwitch.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/Display.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/Reset_out.vhd" +add_file -vhdl -lib work "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd" +add_file -fpga_constraint "C:/Users/ashj/Documents/LEARNING/Microsemi/Lab2_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc" + + + +#implementation: "synthesis" +impl -add synthesis -type fpga + +#device options +set_option -technology IGLOO2 +set_option -part M2GL025 +set_option -package VF256 +set_option -speed_grade STD +set_option -part_companion "" + +#compilation/mapping options +set_option -use_fsm_explorer 0 +set_option -top_module "work.LedBlinkingDSpeed" + +# mapper_options +set_option -frequency 100.000 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# actel_options +set_option -rw_check_on_ram 0 + +# Microsemi G4 +set_option -run_prop_extract 1 +set_option -maxfan 10000 +set_option -clock_globalthreshold 2 +set_option -async_globalthreshold 12 +set_option -globalthreshold 5000 +set_option -low_power_ram_decomp 0 +set_option -disable_io_insertion 0 +set_option -opcond COMTC +set_option -retiming 0 +set_option -report_path 4000 +set_option -update_models_cp 0 +set_option -preserve_registers 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +# Compiler Options +set_option -vhdl2008 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./LedBlinkingDSpeed.edn" +impl -active "synthesis" diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.tcl b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.tcl new file mode 100644 index 0000000..58168c5 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.tcl @@ -0,0 +1,3 @@ +project -load "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/synthesis/LedBlinkingDSpeed_syn.prj" +project -run +project -save diff --git a/Lab2_VHDL/synthesis/LedBlinkingDSpeed_synplify.fdc b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_synplify.fdc new file mode 100644 index 0000000..bd2e5a0 --- /dev/null +++ b/Lab2_VHDL/synthesis/LedBlinkingDSpeed_synplify.fdc @@ -0,0 +1,4 @@ +#0 define_false_path +#1001 create_clock -name {LedBlinkingDSpeed|clk} -period {20} -waveform {0 10} {[get_ports { clk }]} +create_clock -name {LedBlinkingDSpeed|clk} -period {20.000} -waveform {0.000 10.000} [get_ports {clk}] + diff --git a/Lab2_VHDL/synthesis/backup/LedBlinkingDSpeed.srr b/Lab2_VHDL/synthesis/backup/LedBlinkingDSpeed.srr new file mode 100644 index 0000000..9d3aa7d --- /dev/null +++ b/Lab2_VHDL/synthesis/backup/LedBlinkingDSpeed.srr @@ -0,0 +1,554 @@ +#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 +#install: C:\tools\Microsemi\Libero_SoC_v11.7\Synplify +#OS: Windows 7 6.1 +#Hostname: LOSANGLAP73674 + +#Implementation: synthesis + +Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode +Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode +Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns +@N:"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Top entity is set to LedBlinkingDSpeed. +VHDL syntax check successful! +@N: CD231 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus ('U'="1000000000") +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Synthesizing work.ledblinkingdspeed.architecture_ledblinkingdspeed +@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":86:11:86:23|Signal scale_factor0 is undriven +@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":87:11:87:23|Signal scale_factor1 is undriven +@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":88:11:88:23|Signal scale_factor3 is undriven +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":54:7:54:13|Synthesizing work.display.architecture_display +@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:18:82:20|Referenced variable sw2 is not in sensitivity list +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:24:82:26|Referenced variable sw1 is not in sensitivity list +Post processing for work.display.architecture_display +@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to red_led1 assign '0'; register removed by optimization +@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to green_led2 assign '0'; register removed by optimization +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":56:7:56:12|Synthesizing work.clkgen.architecture_clkgen +@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":76:4:76:10|Incomplete sensitivity list - assuming completeness +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":79:21:79:25|Referenced variable scale is not in sensitivity list +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":83:33:83:34|Referenced variable sw is not in sensitivity list +Post processing for work.clkgen.architecture_clkgen +@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal cnt[31:0]. +@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal tmp_clk. +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":56:7:56:20|Synthesizing work.clkgennoswitch.architecture_clkgennoswitch +@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness +@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":80:21:80:25|Referenced variable scale is not in sensitivity list +Post processing for work.clkgennoswitch.architecture_clkgennoswitch +@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd":55:7:55:15|Synthesizing work.reset_out.architecture_reset_out +Post processing for work.reset_out.architecture_reset_out +Post processing for work.ledblinkingdspeed.architecture_ledblinkingdspeed + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:53:20 2016 + +###########################################################] +Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:53:20 2016 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:53:20 2016 + +###########################################################] +Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:53:22 2016 + +###########################################################] +Pre-mapping Report + +Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 +Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2015.03M-SP1-2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +Reading constraint file: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc +@L: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_scck.rpt +Printing clock summary report in "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF667 |Clock conversion disabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + +syn_allowed_resources : blockrams=31 set on top level netlist LedBlinkingDSpeed + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) + + + +@S |Clock Summary +***************** + +Start Requested Requested Clock Clock +Clock Frequency Period Type Group +----------------------------------------------------------------------------------- +LedBlinkingDSpeed|clk 50.0 MHz 20.000 declared default_clkgroup +=================================================================================== + +Finished Pre Mapping Phase. +@N: BN225 |Writing default property annotation file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap. +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:53:22 2016 + +###########################################################] +Map & Optimize Report + +Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 +Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2015.03M-SP1-2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF667 |Clock conversion disabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB) + +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Found counter in view:work.ClkGenNoSwitch(architecture_clkgennoswitch) inst cnt[31:0] +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Found counter in view:work.ClkGen(architecture_clkgen) inst cnt[31:0] +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Found counter in view:work.ClkGenNoSwitch_0(architecture_clkgennoswitch) inst cnt[31:0] +@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Found counter in view:work.ClkGen_0(architecture_clkgen) inst cnt[31:0] + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[10] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[11] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[12] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[13] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[14] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[15] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[16] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[17] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[18] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[19] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[20] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[21] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[22] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[23] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[24] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[25] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[9] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[10] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[11] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[12] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[13] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[14] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[15] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[16] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[17] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[18] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[19] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[20] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[21] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[22] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[23] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[24] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[25] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[11] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[12] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[13] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[14] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[15] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[16] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[17] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[18] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[19] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[20] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[21] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[22] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[23] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[24] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[25] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[10] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[11] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[12] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[13] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[14] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[15] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[16] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[17] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[18] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[19] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[20] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[21] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[22] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[23] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[24] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[25] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs +@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:00s 13.03ns 67 / 47 +@N: FP130 |Promoting Net reset on CLKINT I_196 +@N: FP130 |Promoting Net clk_c on CLKINT I_197 + +Added 0 Buffers +Added 0 Cells via replication + Added 0 Sequential Cells via replication + Added 0 Combinational Cells via replication + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +Clock optimization not enabled +1 non-gated/non-generated clock tree(s) driving 47 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +================================= Non-Gated/Non-Generated Clocks ================================= +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +-------------------------------------------------------------------------------------------------- +@K:CKID0001 clk clock definition on port 47 Display_out.red_led2 +================================================================================================== + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + + +Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 133MB) + +Writing Analyst data base C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) + +Writing EDIF Netlist and constraint files +@N: BW103 |Synopsys Constraint File time units using default value of 1ns +@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF +J-2015.03M-SP1-2 + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 133MB) + +Found clock LedBlinkingDSpeed|clk with period 20.00ns + + +@S |##### START OF TIMING REPORT #####[ +# Timing Report written on Sun Oct 23 02:53:23 2016 +# + + +Top view: LedBlinkingDSpeed +Requested Frequency: 50.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc + +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: 14.415 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +-------------------------------------------------------------------------------------------------------------------------- +LedBlinkingDSpeed|clk 50.0 MHz 179.0 MHz 20.000 5.585 14.415 declared default_clkgroup +========================================================================================================================== + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +------------------------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +------------------------------------------------------------------------------------------------------------------------------------- +LedBlinkingDSpeed|clk LedBlinkingDSpeed|clk | 20.000 14.415 | No paths - | No paths - | No paths - +===================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: LedBlinkingDSpeed|clk +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------------- +Initial_blinking_SW2.cnt[5] LedBlinkingDSpeed|clk SLE Q cnt[5] 0.108 14.415 +Initial_blinking_SW2.cnt[6] LedBlinkingDSpeed|clk SLE Q cnt[6] 0.108 14.509 +Initial_blinking_SW2.cnt[7] LedBlinkingDSpeed|clk SLE Q cnt[7] 0.108 14.584 +Initial_blinking_SW2.cnt[8] LedBlinkingDSpeed|clk SLE Q cnt[8] 0.108 14.632 +Initial_blinking_SW2.cnt[4] LedBlinkingDSpeed|clk SLE Q cnt[4] 0.108 15.151 +Fast_clk_SW1.cnt[3] LedBlinkingDSpeed|clk SLE Q cnt[3] 0.108 15.196 +Fast_clk_SW1.cnt[1] LedBlinkingDSpeed|clk SLE Q cnt[1] 0.108 15.219 +Fast_clk_SW2.cnt[3] LedBlinkingDSpeed|clk SLE Q cnt[3] 0.108 15.232 +Initial_blinking_SW1.cnt[3] LedBlinkingDSpeed|clk SLE Q cnt[3] 0.108 15.232 +Initial_blinking_SW2.cnt[9] LedBlinkingDSpeed|clk SLE Q cnt[9] 0.108 15.245 +======================================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------------------------- +Initial_blinking_SW2.cnt[9] LedBlinkingDSpeed|clk SLE D cnt_s[9] 19.745 14.415 +Initial_blinking_SW2.cnt[8] LedBlinkingDSpeed|clk SLE D cnt_s[8] 19.745 14.431 +Initial_blinking_SW2.cnt[7] LedBlinkingDSpeed|clk SLE D cnt_s[7] 19.745 14.447 +Initial_blinking_SW2.cnt[6] LedBlinkingDSpeed|clk SLE D cnt_s[6] 19.745 14.464 +Initial_blinking_SW2.cnt[5] LedBlinkingDSpeed|clk SLE D cnt_s[5] 19.745 14.480 +Initial_blinking_SW2.cnt[1] LedBlinkingDSpeed|clk SLE D cnt_s[1] 19.745 14.495 +Initial_blinking_SW2.cnt[2] LedBlinkingDSpeed|clk SLE D cnt_s[2] 19.745 14.495 +Initial_blinking_SW2.cnt[3] LedBlinkingDSpeed|clk SLE D cnt_s[3] 19.745 14.495 +Initial_blinking_SW2.cnt[4] LedBlinkingDSpeed|clk SLE D cnt_s[4] 19.745 14.495 +Fast_clk_SW1.cnt[7] LedBlinkingDSpeed|clk SLE D cnt_s[7] 19.745 15.196 +=========================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 20.000 + - Setup time: 0.255 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 19.745 + + - Propagation time: 5.330 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 14.415 + + Number of logic level(s): 12 + Starting point: Initial_blinking_SW2.cnt[5] / Q + Ending point: Initial_blinking_SW2.cnt[9] / D + The start point is clocked by LedBlinkingDSpeed|clk [rising] on pin CLK + The end point is clocked by LedBlinkingDSpeed|clk [rising] on pin CLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------------------------- +Initial_blinking_SW2.cnt[5] SLE Q Out 0.108 0.108 - +cnt[5] Net - - 0.674 - 2 +Initial_blinking_SW2.un7_cntlto31_0_o3_0 CFG4 D In - 0.783 - +Initial_blinking_SW2.un7_cntlto31_0_o3_0 CFG4 Y Out 0.317 1.100 - +un7_cntlto31_0_o3_0_0 Net - - 0.630 - 2 +Initial_blinking_SW2.un14_cntlto31_0_o2 CFG4 B In - 1.730 - +Initial_blinking_SW2.un14_cntlto31_0_o2 CFG4 Y Out 0.165 1.895 - +un14_cntlto31_0_o2 Net - - 0.630 - 2 +Initial_blinking_SW2.un14_cntlto31_0_o2_RNIC1E4 ARI1 B In - 2.525 - +Initial_blinking_SW2.un14_cntlto31_0_o2_RNIC1E4 ARI1 Y Out 0.165 2.689 - +un14_cntlto31_0_o2_RNIC1E4_Y Net - - 1.136 - 9 +Initial_blinking_SW2.cnt_RNIV1K91[1] ARI1 B In - 3.825 - +Initial_blinking_SW2.cnt_RNIV1K91[1] ARI1 FCO Out 0.201 4.026 - +cnt_cry[1] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIQ37S1[2] ARI1 FCI In - 4.026 - +Initial_blinking_SW2.cnt_RNIQ37S1[2] ARI1 FCO Out 0.016 4.042 - +cnt_cry[2] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIM6QE2[3] ARI1 FCI In - 4.042 - +Initial_blinking_SW2.cnt_RNIM6QE2[3] ARI1 FCO Out 0.016 4.058 - +cnt_cry[3] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIJAD13[4] ARI1 FCI In - 4.058 - +Initial_blinking_SW2.cnt_RNIJAD13[4] ARI1 FCO Out 0.016 4.075 - +cnt_cry[4] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIHF0K3[5] ARI1 FCI In - 4.075 - +Initial_blinking_SW2.cnt_RNIHF0K3[5] ARI1 FCO Out 0.016 4.091 - +cnt_cry[5] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIGLJ64[6] ARI1 FCI In - 4.091 - +Initial_blinking_SW2.cnt_RNIGLJ64[6] ARI1 FCO Out 0.016 4.107 - +cnt_cry[6] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIGS6P4[7] ARI1 FCI In - 4.107 - +Initial_blinking_SW2.cnt_RNIGS6P4[7] ARI1 FCO Out 0.016 4.123 - +cnt_cry[7] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIH4QB5[8] ARI1 FCI In - 4.123 - +Initial_blinking_SW2.cnt_RNIH4QB5[8] ARI1 FCO Out 0.016 4.140 - +cnt_cry[8] Net - - 0.000 - 1 +Initial_blinking_SW2.cnt_RNIJDDU5[9] ARI1 FCI In - 4.140 - +Initial_blinking_SW2.cnt_RNIJDDU5[9] ARI1 S Out 0.073 4.213 - +cnt_s[9] Net - - 1.117 - 1 +Initial_blinking_SW2.cnt[9] SLE D In - 5.330 - +============================================================================================================== +Total path delay (propagation time + setup) of 5.585 is 1.398(25.0%) logic and 4.188(75.0%) route. +Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value + + + +##### END OF TIMING REPORT #####] + + +Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 133MB) + + +Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 133MB) + +--------------------------------------- +Resource Usage Report for LedBlinkingDSpeed + +Mapping to part: m2gl025vf256std +Cell usage: +CLKINT 2 uses +CFG2 3 uses +CFG3 5 uses +CFG4 11 uses + +Carry primitives used for arithmetic functions: +ARI1 40 uses + + +Sequential Cells: +SLE 47 uses + +DSP Blocks: 0 + +I/O ports: 7 +I/O primitives: 7 +INBUF 3 uses +OUTBUF 4 uses + + +Global Clock Buffers: 2 + + +Total LUTs: 59 + +Extra resources required for RAM and MACC interface logic during P&R: + +RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; +RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; +MACC Interface Logic : SLEs = 0; LUTs = 0; + +Total number of SLEs after P&R: 47 + 0 + 0 + 0 = 47; +Total number of LUTs after P&R: 59 + 0 + 0 + 0 = 59; + +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 133MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sun Oct 23 02:53:23 2016 + +###########################################################] diff --git a/Lab2_VHDL/synthesis/dm/layer0.xdm b/Lab2_VHDL/synthesis/dm/layer0.xdm new file mode 100644 index 0000000..7c592c9 --- /dev/null +++ b/Lab2_VHDL/synthesis/dm/layer0.xdm @@ -0,0 +1,121 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +SS1SS1SS +S +SF<1kCsOR"b=B0:\F#FD\OvHsCF#lpH\HsLCFF_1B4_P4\3(1b$MD$HV\LDH\8PE.Ujj\lMkCOsH38PE"=RN"Rc"DP="E"8DRHOD#"0=-R4"b#DH0-="4>"/ +"/ +"/ +S1SS1S"/ + +SF<1kCsOR"b=Bw:\ks0kCu\wtvq\HFOs#HCl\CBsNP0HCNAFsQ8\tmpm.N\pLe._]\7pE\8D7bH#D3N$P"E8R"N=4R4"DP="E"8DRHOD#"0=-R4"b#DH0R="4/d">S +S +SF<1kCsOR"b=Bw:\ks0kCu\wtvq\HFOs#HCl\CBsNP0HCNAFsQ8\tmpm.N\pLe._]\7pE\8DpAC8D HMH7Mo1CbC8E3P8N"R=d"4"=RD"8PEDO"RD0H#=4"R.jR4R4gR4b"RD0H#=4"-" +/>S1 +!S<-v-RFD8kCFRsF-0R-S> + + + + +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s )CC#0k_F0s3NO0EHCkO0ssC_C0#C_0Fk"=RD"8PED +">SWSS +S"/ +"/ + +SR +SR +SR +SR"/ +/S<7>CV +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s BtD CFMh10IHONE3sHOE00COk_sCOoD CFMM#0IHORE"DP="E"8D>S +SSqS"/ +"/ + +SRSqSSqSSqS + + + +/S<7>CV +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s BtD CNM3sHOE00COk_sCOoD CRM"DP="E"8D>S +S +SRSqS +SRSqS"/ +"/ +"/ + + +/S<7>CV +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s 7bH#D3N$NEsOHO0C0Cks_#8Hb$DN"=RD"8PED +">SWSS +S"/ +"/ + +SR"/ +"/ +"/ +S +S +/S<7>CV +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s pAC8D HMH7Mo1CbC8s3NO0EHCkO0sDC_CD8LHHM M#o8b8CC"=RD"8PED +">SWSS +SS +SSqSSqSSqSS +SSqS + + +SC<)V=RM"sIF C3)#_C0F3k0NEsOHO0C0Cks_#sCCF0_kR0"HB="DsCN_0Fkb#k0"S> +SWSS/S<)>CV +S +SSR +S)S)S4" +SSSS +S +SC<)V=RM"sIF D3B MtChIF1HE0O3ONsECH0Os0kCD_O MoCMIF#HE0O"=RH"HQM0DHN_HLDMM HoW_1. +">SR/ +S +S +SWSS/S<)>CV + +SWSS/S<)>CV +/S<7>CV +]sC + +@ diff --git a/Lab2_VHDL/synthesis/rpt_LedBlinkingDSpeed.areasrr b/Lab2_VHDL/synthesis/rpt_LedBlinkingDSpeed.areasrr new file mode 100644 index 0000000..5f22ee8 --- /dev/null +++ b/Lab2_VHDL/synthesis/rpt_LedBlinkingDSpeed.areasrr @@ -0,0 +1,180 @@ +#### START OF AREA REPORT #####[ + +Part: M2GL025VF256STD (Microsemi) + +--------------------------------------------------------------------------------- +######## Utilization report for Top level view: LedBlinkingDSpeed ######## +================================================================================= + +SEQUENTIAL ELEMENTS +Name Total elements Utilization Notes +------------------------------------------------- +SLE 115 100 % +================================================= +Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed: 115 (38.72 % Utilization) + + +COMBINATIONAL LOGIC +Name Total elements Utilization Notes +------------------------------------------------------ +CFG 51 100 % +ARI1 108 100 % +BLACK BOX 20 100 % +====================================================== +Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed: 179 (60.27 % Utilization) + + +GLOBAL BUFFERS +Name Total elements Utilization Notes +--------------------------------------------------- +GLOBAL 2 100 % +=================================================== +Total GLOBAL BUFFERS in the block LedBlinkingDSpeed: 2 (0.67 % Utilization) + + +IO PADS +Name Total elements Utilization Notes +------------------------------------------------- +IO 7 100 % +================================================= +Total IO PADS in the block LedBlinkingDSpeed: 7 (2.36 % Utilization) + +------------------------------------------------------------ +######## Utilization report for cell: ClkGen ######## +Instance path: LedBlinkingDSpeed.ClkGen +============================================================ + +SEQUENTIAL ELEMENTS +Name Total elements Utilization Notes +------------------------------------------------- +SLE 27 23.5 % +================================================= +Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGen: 27 (9.09 % Utilization) + + +COMBINATIONAL LOGIC +Name Total elements Utilization Notes +------------------------------------------------------ +CFG 12 23.5 % +ARI1 26 24.1 % +BLACK BOX 6 30. % +====================================================== +Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGen: 44 (14.81 % Utilization) + +-------------------------------------------------------------------- +######## Utilization report for cell: ClkGenNoSwitch ######## +Instance path: LedBlinkingDSpeed.ClkGenNoSwitch +==================================================================== + +SEQUENTIAL ELEMENTS +Name Total elements Utilization Notes +------------------------------------------------- +SLE 28 24.3 % +================================================= +Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGenNoSwitch: 28 (9.43 % Utilization) + + +COMBINATIONAL LOGIC +Name Total elements Utilization Notes +------------------------------------------------------ +CFG 12 23.5 % +ARI1 27 25. % +BLACK BOX 5 25. % +====================================================== +Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGenNoSwitch: 44 (14.81 % Utilization) + +---------------------------------------------------------------------- +######## Utilization report for cell: ClkGenNoSwitch_1 ######## +Instance path: LedBlinkingDSpeed.ClkGenNoSwitch_1 +====================================================================== + +SEQUENTIAL ELEMENTS +Name Total elements Utilization Notes +------------------------------------------------- +SLE 29 25.2 % +================================================= +Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGenNoSwitch_1: 29 (9.76 % Utilization) + + +COMBINATIONAL LOGIC +Name Total elements Utilization Notes +------------------------------------------------------ +CFG 12 23.5 % +ARI1 28 25.9 % +BLACK BOX 4 20. % +====================================================== +Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGenNoSwitch_1: 44 (14.81 % Utilization) + +-------------------------------------------------------------- +######## Utilization report for cell: ClkGen_1 ######## +Instance path: LedBlinkingDSpeed.ClkGen_1 +============================================================== + +SEQUENTIAL ELEMENTS +Name Total elements Utilization Notes +------------------------------------------------- +SLE 28 24.3 % +================================================= +Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGen_1: 28 (9.43 % Utilization) + + +COMBINATIONAL LOGIC +Name Total elements Utilization Notes +------------------------------------------------------ +CFG 12 23.5 % +ARI1 27 25. % +BLACK BOX 5 25. % +====================================================== +Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGen_1: 44 (14.81 % Utilization) + +------------------------------------------------------------- +######## Utilization report for cell: Display ######## +Instance path: LedBlinkingDSpeed.Display +============================================================= + +SEQUENTIAL ELEMENTS +Name Total elements Utilization Notes +------------------------------------------------- +SLE 2 1.74 % +================================================= +Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.Display: 2 (0.67 % Utilization) + + +COMBINATIONAL LOGIC +Name Total elements Utilization Notes +------------------------------------------------- +CFG 2 3.92 % +================================================= +Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.Display: 2 (0.67 % Utilization) + +--------------------------------------------------------------- +######## Utilization report for cell: Reset_out ######## +Instance path: LedBlinkingDSpeed.Reset_out +=============================================================== + +SEQUENTIAL ELEMENTS +Name Total elements Utilization Notes +------------------------------------------------- +SLE 1 0.870 % +================================================= +Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.Reset_out: 1 (0.34 % Utilization) + + +COMBINATIONAL LOGIC +Name Total elements Utilization Notes +------------------------------------------------- +CFG 1 1.96 % +================================================= +Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.Reset_out: 1 (0.34 % Utilization) + + +GLOBAL BUFFERS +Name Total elements Utilization Notes +--------------------------------------------------- +GLOBAL 1 50. % +=================================================== +Total GLOBAL BUFFERS in the block LedBlinkingDSpeed.Reset_out: 1 (0.34 % Utilization) + + +##### END OF AREA REPORT #####] + diff --git a/Lab2_VHDL/synthesis/rpt_LedBlinkingDSpeed_areasrr.htm b/Lab2_VHDL/synthesis/rpt_LedBlinkingDSpeed_areasrr.htm new file mode 100644 index 0000000..4d358aa --- /dev/null +++ b/Lab2_VHDL/synthesis/rpt_LedBlinkingDSpeed_areasrr.htm @@ -0,0 +1,205 @@ + +#### START OF AREA REPORT #####[
+Part:			M2GL025VF256STD (Microsemi)
+
+Click here to go to specific block report:
+
LedBlinkingDSpeed

Reset_out

ClkGenNoSwitch

ClkGen

ClkGenNoSwitch_1

ClkGen_1

Display


+---------------------------------------------------------------------------------
+########   Utilization report for  Top level view:   LedBlinkingDSpeed   ########
+=================================================================================
+
+SEQUENTIAL ELEMENTS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+SLE      115                100 %                
+=================================================
+Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed:	115 (38.72 % Utilization)
+
+
Top

+
+COMBINATIONAL LOGIC
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+CFG           51                 100 %                
+ARI1          108                100 %                
+BLACK BOX     20                 100 %                
+======================================================
+Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed:	179 (60.27 % Utilization)
+
+
Top

+
+GLOBAL BUFFERS
+Name       Total elements     Utilization     Notes
+---------------------------------------------------
+GLOBAL     2                  100 %                
+===================================================
+Total GLOBAL BUFFERS in the block LedBlinkingDSpeed:	2 (0.67 % Utilization)
+
+
Top

+
+IO PADS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+IO       7                  100 %                
+=================================================
+Total IO PADS in the block LedBlinkingDSpeed:	7 (2.36 % Utilization)
+
+
Top

+
+------------------------------------------------------------
+########   Utilization report for  cell:   ClkGen   ########
+Instance path:   LedBlinkingDSpeed.ClkGen                   
+============================================================
+
+SEQUENTIAL ELEMENTS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+SLE      27                 23.5 %               
+=================================================
+Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGen:	27 (9.09 % Utilization)
+
+
Top

+
+COMBINATIONAL LOGIC
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+CFG           12                 23.5 %               
+ARI1          26                 24.1 %               
+BLACK BOX     6                  30. %                
+======================================================
+Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGen:	44 (14.81 % Utilization)
+
+
Top

+
+--------------------------------------------------------------------
+########   Utilization report for  cell:   ClkGenNoSwitch   ########
+Instance path:   LedBlinkingDSpeed.ClkGenNoSwitch                   
+====================================================================
+
+SEQUENTIAL ELEMENTS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+SLE      28                 24.3 %               
+=================================================
+Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGenNoSwitch:	28 (9.43 % Utilization)
+
+
Top

+
+COMBINATIONAL LOGIC
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+CFG           12                 23.5 %               
+ARI1          27                 25. %                
+BLACK BOX     5                  25. %                
+======================================================
+Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGenNoSwitch:	44 (14.81 % Utilization)
+
+
Top

+
+----------------------------------------------------------------------
+########   Utilization report for  cell:   ClkGenNoSwitch_1   ########
+Instance path:   LedBlinkingDSpeed.ClkGenNoSwitch_1                   
+======================================================================
+
+SEQUENTIAL ELEMENTS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+SLE      29                 25.2 %               
+=================================================
+Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGenNoSwitch_1:	29 (9.76 % Utilization)
+
+
Top

+
+COMBINATIONAL LOGIC
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+CFG           12                 23.5 %               
+ARI1          28                 25.9 %               
+BLACK BOX     4                  20. %                
+======================================================
+Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGenNoSwitch_1:	44 (14.81 % Utilization)
+
+
Top

+
+--------------------------------------------------------------
+########   Utilization report for  cell:   ClkGen_1   ########
+Instance path:   LedBlinkingDSpeed.ClkGen_1                   
+==============================================================
+
+SEQUENTIAL ELEMENTS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+SLE      28                 24.3 %               
+=================================================
+Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.ClkGen_1:	28 (9.43 % Utilization)
+
+
Top

+
+COMBINATIONAL LOGIC
+Name          Total elements     Utilization     Notes
+------------------------------------------------------
+CFG           12                 23.5 %               
+ARI1          27                 25. %                
+BLACK BOX     5                  25. %                
+======================================================
+Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.ClkGen_1:	44 (14.81 % Utilization)
+
+
Top

+
+-------------------------------------------------------------
+########   Utilization report for  cell:   Display   ########
+Instance path:   LedBlinkingDSpeed.Display                   
+=============================================================
+
+SEQUENTIAL ELEMENTS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+SLE      2                  1.74 %               
+=================================================
+Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.Display:	2 (0.67 % Utilization)
+
+
Top

+
+COMBINATIONAL LOGIC
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+CFG      2                  3.92 %               
+=================================================
+Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.Display:	2 (0.67 % Utilization)
+
+
Top

+
+---------------------------------------------------------------
+########   Utilization report for  cell:   Reset_out   ########
+Instance path:   LedBlinkingDSpeed.Reset_out                   
+===============================================================
+
+SEQUENTIAL ELEMENTS
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+SLE      1                  0.870 %              
+=================================================
+Total SEQUENTIAL ELEMENTS in the block LedBlinkingDSpeed.Reset_out:	1 (0.34 % Utilization)
+
+
Top

+
+COMBINATIONAL LOGIC
+Name     Total elements     Utilization     Notes
+-------------------------------------------------
+CFG      1                  1.96 %               
+=================================================
+Total COMBINATIONAL LOGIC in the block LedBlinkingDSpeed.Reset_out:	1 (0.34 % Utilization)
+
+
Top

+
+GLOBAL BUFFERS
+Name       Total elements     Utilization     Notes
+---------------------------------------------------
+GLOBAL     1                  50. %                
+===================================================
+Total GLOBAL BUFFERS in the block LedBlinkingDSpeed.Reset_out:	1 (0.34 % Utilization)
+
+
Top

+
+##### END OF AREA REPORT #####]
+
diff --git a/Lab2_VHDL/synthesis/run_options.txt b/Lab2_VHDL/synthesis/run_options.txt
new file mode 100644
index 0000000..db8851c
--- /dev/null
+++ b/Lab2_VHDL/synthesis/run_options.txt
@@ -0,0 +1,72 @@
+#--  Synopsys, Inc.
+#--  Version J-2015.03M-SP1-2
+#--  Project file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\run_options.txt
+#--  Written on Sun Oct 23 02:59:30 2016
+
+
+#project files
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/ClkGen.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/ClkGenNoSwitch.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/Display.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/Reset_out.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd"
+add_file -fpga_constraint "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc"
+
+
+
+#implementation: "synthesis"
+impl -add synthesis -type fpga
+
+#device options
+set_option -technology IGLOO2
+set_option -part M2GL025
+set_option -package VF256
+set_option -speed_grade STD
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "work.LedBlinkingDSpeed"
+
+# mapper_options
+set_option -frequency 100.000
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# actel_options
+set_option -rw_check_on_ram 0
+
+# Microsemi G4
+set_option -run_prop_extract 1
+set_option -maxfan 10000
+set_option -clock_globalthreshold 2
+set_option -async_globalthreshold 12
+set_option -globalthreshold 5000
+set_option -low_power_ram_decomp 0
+set_option -disable_io_insertion 0
+set_option -opcond COMTC
+set_option -retiming 0
+set_option -report_path 4000
+set_option -update_models_cp 0
+set_option -preserve_registers 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+# Compiler Options
+set_option -vhdl2008 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./LedBlinkingDSpeed.edn"
+impl -active "synthesis"
diff --git a/Lab2_VHDL/synthesis/scratchproject.prs b/Lab2_VHDL/synthesis/scratchproject.prs
new file mode 100644
index 0000000..2d90b12
--- /dev/null
+++ b/Lab2_VHDL/synthesis/scratchproject.prs
@@ -0,0 +1,70 @@
+#--  Synopsys, Inc.
+#--  Version J-2015.03M-SP1-2
+#--  Project file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/ClkGen.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/ClkGenNoSwitch.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/Display.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/Reset_out.vhd"
+add_file -vhdl -lib work "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/hdl/LedBlinkingDSpeed.vhd"
+add_file -fpga_constraint "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/designer/LedBlinkingDSpeed/synthesis.fdc"
+
+
+
+#implementation: "synthesis"
+impl -add C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis -type fpga
+
+#device options
+set_option -technology IGLOO2
+set_option -part M2GL025
+set_option -package VF256
+set_option -speed_grade STD
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -use_fsm_explorer 0
+set_option -top_module "work.LedBlinkingDSpeed"
+
+# mapper_options
+set_option -frequency 100.000
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# actel_options
+set_option -rw_check_on_ram 0
+
+# Microsemi G4
+set_option -run_prop_extract 1
+set_option -maxfan 10000
+set_option -clock_globalthreshold 2
+set_option -async_globalthreshold 12
+set_option -globalthreshold 5000
+set_option -low_power_ram_decomp 0
+set_option -disable_io_insertion 0
+set_option -opcond COMTC
+set_option -retiming 0
+set_option -report_path 4000
+set_option -update_models_cp 0
+set_option -preserve_registers 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+# Compiler Options
+set_option -vhdl2008 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "C:/Future/FPGA/Microsemi/CreativeBoard/IGLOO2/Lab2_VHDL/synthesis/LedBlinkingDSpeed.edn"
+impl -active "synthesis"
diff --git a/Lab2_VHDL/synthesis/synlog.tcl b/Lab2_VHDL/synthesis/synlog.tcl
new file mode 100644
index 0000000..099895b
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog.tcl
@@ -0,0 +1 @@
+run_tcl -fg LedBlinkingDSpeed_syn.tcl
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_compiler.srr b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_compiler.srr
new file mode 100644
index 0000000..37f446c
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_compiler.srr
@@ -0,0 +1,64 @@
+Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N|Running in 64-bit mode
+Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N|Running in 64-bit mode
+Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N: CD720 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
+@N:"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Top entity is set to LedBlinkingDSpeed.
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd changed - recompiling
+VHDL syntax check successful!
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd changed - recompiling
+@N: CD231 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Synthesizing work.ledblinkingdspeed.architecture_ledblinkingdspeed 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":93:11:93:23|Signal scale_factor0 is undriven 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":94:11:94:23|Signal scale_factor1 is undriven 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":95:11:95:23|Signal scale_factor3 is undriven 
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":54:7:54:13|Synthesizing work.display.architecture_display 
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:18:82:20|Referenced variable sw2 is not in sensitivity list
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:24:82:26|Referenced variable sw1 is not in sensitivity list
+Post processing for work.display.architecture_display
+@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to red_led1 assign '0'; register removed by optimization
+@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to green_led2 assign '0'; register removed by optimization
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":56:7:56:12|Synthesizing work.clkgen.architecture_clkgen 
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":76:4:76:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":79:21:79:25|Referenced variable scale is not in sensitivity list
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":83:33:83:34|Referenced variable sw is not in sensitivity list
+Post processing for work.clkgen.architecture_clkgen
+@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal cnt[31:0].
+@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal tmp_clk.
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":56:7:56:20|Synthesizing work.clkgennoswitch.architecture_clkgennoswitch 
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":80:21:80:25|Referenced variable scale is not in sensitivity list
+Post processing for work.clkgennoswitch.architecture_clkgennoswitch
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd":55:7:55:15|Synthesizing work.reset_out.architecture_reset_out 
+Post processing for work.reset_out.architecture_reset_out
+Post processing for work.ledblinkingdspeed.architecture_ledblinkingdspeed
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:30 2016
+
+###########################################################]
+Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N|Running in 64-bit mode
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:30 2016
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:30 2016
+
+###########################################################]
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_compiler.srr.rptmap b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_compiler.srr.rptmap
new file mode 100644
index 0000000..d5c4fe4
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/LedBlinkingDSpeed_compiler.srr,LedBlinkingDSpeed_compiler.srr,Compile Log
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.srr b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.srr
new file mode 100644
index 0000000..d223325
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.srr
@@ -0,0 +1,417 @@
+Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
+Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2015.03M-SP1-2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF667 |Clock conversion disabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
+
+@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Found counter in view:work.ClkGenNoSwitch(architecture_clkgennoswitch) inst cnt[31:0]
+@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Found counter in view:work.ClkGen(architecture_clkgen) inst cnt[31:0]
+@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Found counter in view:work.ClkGenNoSwitch_0(architecture_clkgennoswitch) inst cnt[31:0]
+@N:"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Found counter in view:work.ClkGen_0(architecture_clkgen) inst cnt[31:0]
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:00s		    10.53ns		 165 /       115
+@N: FP130 |Promoting Net reset on CLKINT  I_103 
+@N: FP130 |Promoting Net clk_c on CLKINT  I_104 
+
+Added 0 Buffers
+Added 0 Cells via replication
+	Added 0 Sequential Cells via replication
+	Added 0 Combinational Cells via replication
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+Clock optimization not enabled
+1 non-gated/non-generated clock tree(s) driving 115 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+================================= Non-Gated/Non-Generated Clocks =================================
+Clock Tree ID     Driving Element     Drive Element Type           Fanout     Sample Instance     
+--------------------------------------------------------------------------------------------------
+@K:CKID0001       clk                 clock definition on port     115        Display_out.red_led2
+==================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 134MB)
+
+Writing Analyst data base C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+Writing EDIF Netlist and constraint files
+@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
+@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
+J-2015.03M-SP1-2
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+Found clock LedBlinkingDSpeed|clk with period 20.00ns 
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Sun Oct 23 02:59:33 2016
+#
+
+
+Top view:               LedBlinkingDSpeed
+Requested Frequency:    50.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc
+                       
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 12.640
+
+                          Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock            Frequency     Frequency     Period        Period        Slack      Type         Group           
+--------------------------------------------------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk     50.0 MHz      135.9 MHz     20.000        7.360         12.640     declared     default_clkgroup
+==========================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------
+Starting               Ending                 |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk  LedBlinkingDSpeed|clk  |  20.000      12.640  |  No paths    -      |  No paths    -      |  No paths    -    
+=====================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: LedBlinkingDSpeed|clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                 Starting                                               Arrival           
+Instance                         Reference                 Type     Pin     Net         Time        Slack 
+                                 Clock                                                                    
+----------------------------------------------------------------------------------------------------------
+Initial_blinking_SW2.cnt[8]      LedBlinkingDSpeed|clk     SLE      Q       cnt[8]      0.108       12.640
+Initial_blinking_SW2.cnt[9]      LedBlinkingDSpeed|clk     SLE      Q       cnt[9]      0.108       12.734
+Initial_blinking_SW2.cnt[13]     LedBlinkingDSpeed|clk     SLE      Q       cnt[13]     0.108       12.747
+Initial_blinking_SW2.cnt[10]     LedBlinkingDSpeed|clk     SLE      Q       cnt[10]     0.108       12.809
+Initial_blinking_SW2.cnt[14]     LedBlinkingDSpeed|clk     SLE      Q       cnt[14]     0.108       12.825
+Initial_blinking_SW2.cnt[11]     LedBlinkingDSpeed|clk     SLE      Q       cnt[11]     0.108       12.857
+Initial_blinking_SW2.cnt[15]     LedBlinkingDSpeed|clk     SLE      Q       cnt[15]     0.108       12.871
+Initial_blinking_SW2.cnt[16]     LedBlinkingDSpeed|clk     SLE      Q       cnt[16]     0.108       12.948
+Fast_clk_SW2.cnt[7]              LedBlinkingDSpeed|clk     SLE      Q       cnt[7]      0.087       13.391
+Fast_clk_SW1.cnt[6]              LedBlinkingDSpeed|clk     SLE      Q       cnt[6]      0.087       13.407
+==========================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                 Starting                                                 Required           
+Instance                         Reference                 Type     Pin     Net           Time         Slack 
+                                 Clock                                                                       
+-------------------------------------------------------------------------------------------------------------
+Initial_blinking_SW2.cnt[26]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[26]     19.745       12.640
+Initial_blinking_SW2.cnt[25]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[25]     19.745       12.656
+Initial_blinking_SW2.cnt[24]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[24]     19.745       12.673
+Initial_blinking_SW2.cnt[23]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[23]     19.745       12.689
+Initial_blinking_SW2.cnt[22]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[22]     19.745       12.705
+Initial_blinking_SW2.cnt[21]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[21]     19.745       12.722
+Initial_blinking_SW2.cnt[20]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[20]     19.745       12.738
+Initial_blinking_SW2.cnt[19]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[19]     19.745       12.754
+Initial_blinking_SW2.cnt[18]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[18]     19.745       12.770
+Initial_blinking_SW2.cnt[17]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[17]     19.745       12.787
+=============================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      20.000
+    - Setup time:                            0.255
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         19.745
+
+    - Propagation time:                      7.105
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     12.640
+
+    Number of logic level(s):                32
+    Starting point:                          Initial_blinking_SW2.cnt[8] / Q
+    Ending point:                            Initial_blinking_SW2.cnt[26] / D
+    The start point is clocked by            LedBlinkingDSpeed|clk [rising] on pin CLK
+    The end   point is clocked by            LedBlinkingDSpeed|clk [rising] on pin CLK
+
+Instance / Net                                      Pin      Pin               Arrival     No. of    
+Name                                       Type     Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------
+Initial_blinking_SW2.cnt[8]                SLE      Q        Out     0.108     0.108       -         
+cnt[8]                                     Net      -        -       0.674     -           2         
+Initial_blinking_SW2.cnt_RNI8JG21[10]      CFG4     D        In      -         0.783       -         
+Initial_blinking_SW2.cnt_RNI8JG21[10]      CFG4     Y        Out     0.317     1.100       -         
+N_176                                      Net      -        -       0.630     -           2         
+Initial_blinking_SW2.cnt_RNIIH0I1[12]      CFG3     C        In      -         1.730       -         
+Initial_blinking_SW2.cnt_RNIIH0I1[12]      CFG3     Y        Out     0.226     1.956       -         
+N_87                                       Net      -        -       0.556     -           1         
+Initial_blinking_SW2.cnt_RNI4GAR1[17]      CFG4     B        In      -         2.511       -         
+Initial_blinking_SW2.cnt_RNI4GAR1[17]      CFG4     Y        Out     0.148     2.660       -         
+N_93                                       Net      -        -       0.556     -           1         
+Initial_blinking_SW2.cnt_RNI9EVA2[20]      CFG4     C        In      -         3.216       -         
+Initial_blinking_SW2.cnt_RNI9EVA2[20]      CFG4     Y        Out     0.226     3.441       -         
+N_103                                      Net      -        -       0.556     -           1         
+Initial_blinking_SW2.cnt_RNIOCCK2[27]      ARI1     B        In      -         3.997       -         
+Initial_blinking_SW2.cnt_RNIOCCK2[27]      ARI1     Y        Out     0.165     4.161       -         
+cnt_RNIOCCK2_Y[27]                         Net      -        -       1.145     -           27        
+Initial_blinking_SW2.cnt_RNITNTM5[0]       ARI1     B        In      -         5.306       -         
+Initial_blinking_SW2.cnt_RNITNTM5[0]       ARI1     FCO      Out     0.201     5.507       -         
+cnt_cry[0]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI34FP8[1]       ARI1     FCI      In      -         5.507       -         
+Initial_blinking_SW2.cnt_RNI34FP8[1]       ARI1     FCO      Out     0.016     5.523       -         
+cnt_cry[1]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIAH0SB[2]       ARI1     FCI      In      -         5.523       -         
+Initial_blinking_SW2.cnt_RNIAH0SB[2]       ARI1     FCO      Out     0.016     5.540       -         
+cnt_cry[2]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIIVHUE[3]       ARI1     FCI      In      -         5.540       -         
+Initial_blinking_SW2.cnt_RNIIVHUE[3]       ARI1     FCO      Out     0.016     5.556       -         
+cnt_cry[3]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIRE31I[4]       ARI1     FCI      In      -         5.556       -         
+Initial_blinking_SW2.cnt_RNIRE31I[4]       ARI1     FCO      Out     0.016     5.572       -         
+cnt_cry[4]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI5VK3L[5]       ARI1     FCI      In      -         5.572       -         
+Initial_blinking_SW2.cnt_RNI5VK3L[5]       ARI1     FCO      Out     0.016     5.589       -         
+cnt_cry[5]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIGG66O[6]       ARI1     FCI      In      -         5.589       -         
+Initial_blinking_SW2.cnt_RNIGG66O[6]       ARI1     FCO      Out     0.016     5.605       -         
+cnt_cry[6]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIS2O8R[7]       ARI1     FCI      In      -         5.605       -         
+Initial_blinking_SW2.cnt_RNIS2O8R[7]       ARI1     FCO      Out     0.016     5.621       -         
+cnt_cry[7]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI9M9BU[8]       ARI1     FCI      In      -         5.621       -         
+Initial_blinking_SW2.cnt_RNI9M9BU[8]       ARI1     FCO      Out     0.016     5.638       -         
+cnt_cry[8]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNINARD11[9]      ARI1     FCI      In      -         5.638       -         
+Initial_blinking_SW2.cnt_RNINARD11[9]      ARI1     FCO      Out     0.016     5.654       -         
+cnt_cry[9]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIDPA541[10]     ARI1     FCI      In      -         5.654       -         
+Initial_blinking_SW2.cnt_RNIDPA541[10]     ARI1     FCO      Out     0.016     5.670       -         
+cnt_cry[10]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI49QS61[11]     ARI1     FCI      In      -         5.670       -         
+Initial_blinking_SW2.cnt_RNI49QS61[11]     ARI1     FCO      Out     0.016     5.686       -         
+cnt_cry[11]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNISP9K91[12]     ARI1     FCI      In      -         5.686       -         
+Initial_blinking_SW2.cnt_RNISP9K91[12]     ARI1     FCO      Out     0.016     5.703       -         
+cnt_cry[12]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNILBPBC1[13]     ARI1     FCI      In      -         5.703       -         
+Initial_blinking_SW2.cnt_RNILBPBC1[13]     ARI1     FCO      Out     0.016     5.719       -         
+cnt_cry[13]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIFU83F1[14]     ARI1     FCI      In      -         5.719       -         
+Initial_blinking_SW2.cnt_RNIFU83F1[14]     ARI1     FCO      Out     0.016     5.735       -         
+cnt_cry[14]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIAIOQH1[15]     ARI1     FCI      In      -         5.735       -         
+Initial_blinking_SW2.cnt_RNIAIOQH1[15]     ARI1     FCO      Out     0.016     5.752       -         
+cnt_cry[15]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI678IK1[16]     ARI1     FCI      In      -         5.752       -         
+Initial_blinking_SW2.cnt_RNI678IK1[16]     ARI1     FCO      Out     0.016     5.768       -         
+cnt_cry[16]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI3TN9N1[17]     ARI1     FCI      In      -         5.768       -         
+Initial_blinking_SW2.cnt_RNI3TN9N1[17]     ARI1     FCO      Out     0.016     5.784       -         
+cnt_cry[17]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI1K71Q1[18]     ARI1     FCI      In      -         5.784       -         
+Initial_blinking_SW2.cnt_RNI1K71Q1[18]     ARI1     FCO      Out     0.016     5.801       -         
+cnt_cry[18]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI0CNOS1[19]     ARI1     FCI      In      -         5.801       -         
+Initial_blinking_SW2.cnt_RNI0CNOS1[19]     ARI1     FCO      Out     0.016     5.817       -         
+cnt_cry[19]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNINS7GV1[20]     ARI1     FCI      In      -         5.817       -         
+Initial_blinking_SW2.cnt_RNINS7GV1[20]     ARI1     FCO      Out     0.016     5.833       -         
+cnt_cry[20]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIFEO722[21]     ARI1     FCI      In      -         5.833       -         
+Initial_blinking_SW2.cnt_RNIFEO722[21]     ARI1     FCO      Out     0.016     5.849       -         
+cnt_cry[21]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI819V42[22]     ARI1     FCI      In      -         5.849       -         
+Initial_blinking_SW2.cnt_RNI819V42[22]     ARI1     FCO      Out     0.016     5.866       -         
+cnt_cry[22]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI2LPM72[23]     ARI1     FCI      In      -         5.866       -         
+Initial_blinking_SW2.cnt_RNI2LPM72[23]     ARI1     FCO      Out     0.016     5.882       -         
+cnt_cry[23]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIT9AEA2[24]     ARI1     FCI      In      -         5.882       -         
+Initial_blinking_SW2.cnt_RNIT9AEA2[24]     ARI1     FCO      Out     0.016     5.898       -         
+cnt_cry[24]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIPVQ5D2[25]     ARI1     FCI      In      -         5.898       -         
+Initial_blinking_SW2.cnt_RNIPVQ5D2[25]     ARI1     FCO      Out     0.016     5.915       -         
+cnt_cry[25]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIMMBTF2[26]     ARI1     FCI      In      -         5.915       -         
+Initial_blinking_SW2.cnt_RNIMMBTF2[26]     ARI1     S        Out     0.073     5.988       -         
+cnt_s[26]                                  Net      -        -       1.117     -           1         
+Initial_blinking_SW2.cnt[26]               SLE      D        In      -         7.105       -         
+=====================================================================================================
+Total path delay (propagation time + setup) of 7.360 is 2.126(28.9%) logic and 5.234(71.1%) route.
+Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
+
+
+
+##### END OF TIMING REPORT #####]
+
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+---------------------------------------
+Resource Usage Report for LedBlinkingDSpeed 
+
+Mapping to part: m2gl025vf256std
+Cell usage:
+CLKINT          2 uses
+CFG2           4 uses
+CFG3           9 uses
+CFG4           38 uses
+
+Carry primitives used for arithmetic functions:
+ARI1           108 uses
+
+
+Sequential Cells: 
+SLE            115 uses
+
+DSP Blocks:    0
+
+I/O ports: 7
+I/O primitives: 7
+INBUF          3 uses
+OUTBUF         4 uses
+
+
+Global Clock Buffers: 2
+
+
+Total LUTs:    159
+
+Extra resources required for RAM and MACC interface logic during P&R:
+
+RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
+RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
+MACC     Interface Logic : SLEs = 0; LUTs = 0;
+
+Total number of SLEs after P&R:  115 + 0 + 0 + 0 = 115;
+Total number of LUTs after P&R:  159 + 0 + 0 + 0 = 159;
+
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 135MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:34 2016
+
+###########################################################]
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.srr_Min b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.srr_Min
new file mode 100644
index 0000000..e88fd99
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.srr_Min
@@ -0,0 +1,134 @@
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Sun Oct 23 02:59:33 2016
+#
+
+
+Top view:               LedBlinkingDSpeed
+Requested Frequency:    50.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc
+                       
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 0.545
+
+                          Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock            Frequency     Frequency     Period        Period        Slack      Type         Group           
+--------------------------------------------------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk     50.0 MHz      135.9 MHz     20.000        7.360         12.640     declared     default_clkgroup
+==========================================================================================================================
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                        |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------
+Starting               Ending                 |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk  LedBlinkingDSpeed|clk  |  0.000       0.545  |  No paths    -      |  No paths    -      |  No paths    -    
+====================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: LedBlinkingDSpeed|clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                 Starting                                               Arrival          
+Instance                         Reference                 Type     Pin     Net         Time        Slack
+                                 Clock                                                                   
+---------------------------------------------------------------------------------------------------------
+Fast_clk_SW1.tmp_clk             LedBlinkingDSpeed|clk     SLE      Q       led         0.061       0.545
+Initial_blinking_SW2.tmp_clk     LedBlinkingDSpeed|clk     SLE      Q       led1        0.061       0.545
+Initial_blinking_SW2.cnt[25]     LedBlinkingDSpeed|clk     SLE      Q       cnt[25]     0.076       0.591
+Fast_clk_SW2.tmp_clk             LedBlinkingDSpeed|clk     SLE      Q       led2        0.061       0.593
+Initial_blinking_SW1.tmp_clk     LedBlinkingDSpeed|clk     SLE      Q       led0        0.061       0.593
+Fast_clk_SW1.cnt[24]             LedBlinkingDSpeed|clk     SLE      Q       cnt[24]     0.076       0.623
+Fast_clk_SW2.cnt[25]             LedBlinkingDSpeed|clk     SLE      Q       cnt[25]     0.076       0.623
+Initial_blinking_SW1.cnt[25]     LedBlinkingDSpeed|clk     SLE      Q       cnt[25]     0.076       0.623
+Initial_blinking_SW2.cnt[27]     LedBlinkingDSpeed|clk     SLE      Q       cnt[27]     0.076       0.636
+Fast_clk_SW1.cnt[22]             LedBlinkingDSpeed|clk     SLE      Q       cnt[22]     0.076       0.657
+=========================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                 Starting                                                          Required          
+Instance                         Reference                 Type     Pin     Net                    Time         Slack
+                                 Clock                                                                               
+---------------------------------------------------------------------------------------------------------------------
+Display_out.green_led1           LedBlinkingDSpeed|clk     SLE      D       green_led1_4           0.179        0.545
+Display_out.red_led2             LedBlinkingDSpeed|clk     SLE      D       red_led2_3             0.179        0.545
+Initial_blinking_SW2.tmp_clk     LedBlinkingDSpeed|clk     SLE      D       tmp_clk_RNO            0.179        0.591
+Fast_clk_SW2.tmp_clk             LedBlinkingDSpeed|clk     SLE      D       un7_cntlto31_0_0_0     0.179        0.623
+Fast_clk_SW1.tmp_clk             LedBlinkingDSpeed|clk     SLE      D       un7_cntlto31_0_0       0.179        0.623
+Initial_blinking_SW1.tmp_clk     LedBlinkingDSpeed|clk     SLE      D       un7_cntlto31_0         0.179        0.623
+Fast_clk_SW1.cnt[25]             LedBlinkingDSpeed|clk     SLE      D       cnt_s[25]              0.179        0.709
+Initial_blinking_SW1.cnt[26]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[26]              0.179        0.709
+Fast_clk_SW2.cnt[26]             LedBlinkingDSpeed|clk     SLE      D       cnt_s[26]              0.179        0.709
+Initial_blinking_SW2.cnt[27]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[27]              0.179        0.719
+=====================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+    Propagation time:                        0.724
+    + Clock delay at starting point:         0.000 (ideal)
+    - Requested Period:                      0.000
+    - Hold time:                             0.179
+    - Clock delay at ending point:           0.000 (ideal)
+    = Slack (critical) :                     0.545
+
+    Number of logic level(s):                1
+    Starting point:                          Fast_clk_SW1.tmp_clk / Q
+    Ending point:                            Display_out.green_led1 / D
+    The start point is clocked by            LedBlinkingDSpeed|clk [rising] on pin CLK
+    The end   point is clocked by            LedBlinkingDSpeed|clk [rising] on pin CLK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                         Type     Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+Fast_clk_SW1.tmp_clk         SLE      Q        Out     0.061     0.061       -         
+led                          Net      -        -       0.409     -           1         
+Display_out.green_led1_4     CFG4     C        In      -         0.471       -         
+Display_out.green_led1_4     CFG4     Y        Out     0.142     0.613       -         
+green_led1_4                 Net      -        -       0.111     -           1         
+Display_out.green_led1       SLE      D        In      -         0.724       -         
+=======================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.szr b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.szr
new file mode 100644
index 0000000..55a72a6
Binary files /dev/null and b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.szr differ
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.xck b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.xck
new file mode 100644
index 0000000..fdb538a
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_fpga_mapper.xck
@@ -0,0 +1 @@
+CKID0001:@|S:clk@|E:Display_out.red_led2@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_multi_srs_gen.srr b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_multi_srs_gen.srr
new file mode 100644
index 0000000..7a97d10
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_multi_srs_gen.srr
@@ -0,0 +1,10 @@
+Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N|Running in 64-bit mode
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:31 2016
+
+###########################################################]
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_premap.srr b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_premap.srr
new file mode 100644
index 0000000..97431c4
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_premap.srr
@@ -0,0 +1,48 @@
+Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
+Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2015.03M-SP1-2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+Reading constraint file: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc
+@L: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_scck.rpt 
+Printing clock  summary report in "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF667 |Clock conversion disabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+syn_allowed_resources : blockrams=31  set on top level netlist LedBlinkingDSpeed
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
+
+
+
+@S |Clock Summary
+*****************
+
+Start                     Requested     Requested     Clock        Clock           
+Clock                     Frequency     Period        Type         Group           
+-----------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk     50.0 MHz      20.000        declared     default_clkgroup
+===================================================================================
+
+Finished Pre Mapping Phase.
+@N: BN225 |Writing default property annotation file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap.
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:32 2016
+
+###########################################################]
diff --git a/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_premap.szr b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_premap.szr
new file mode 100644
index 0000000..112d825
Binary files /dev/null and b/Lab2_VHDL/synthesis/synlog/LedBlinkingDSpeed_premap.szr differ
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_notes.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_notes.txt
new file mode 100644
index 0000000..c141b4a
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_notes.txt
@@ -0,0 +1,12 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
+@N:"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Top entity is set to LedBlinkingDSpeed.
+@N: CD231 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Synthesizing work.ledblinkingdspeed.architecture_ledblinkingdspeed 
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":54:7:54:13|Synthesizing work.display.architecture_display 
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":56:7:56:12|Synthesizing work.clkgen.architecture_clkgen 
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":56:7:56:20|Synthesizing work.clkgennoswitch.architecture_clkgennoswitch 
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd":55:7:55:15|Synthesizing work.reset_out.architecture_reset_out 
+@N|Running in 64-bit mode
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_runstatus.xml b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_runstatus.xml
new file mode 100644
index 0000000..7410092
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+
+
+
+ 
+  
+    C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_compiler.srr
+    Synopsys HDL Compiler
+   
+  
+    Completed    
+  
+ 
+			
+  11
+  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_compiler_notes.txt
+  
+			
+  15
+  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_compiler_warnings.txt
+  
+			
+  0
+  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_compiler_errors.txt
+  
+			
+  -
+  
+			
+  0h:00m:00s
+  
+			
+  -
+  
+			
+  1477216770
+  
+			
+
\ No newline at end of file
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_warnings.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_warnings.txt
new file mode 100644
index 0000000..8acc1b6
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_compiler_warnings.txt
@@ -0,0 +1,16 @@
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":93:11:93:23|Signal scale_factor0 is undriven 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":94:11:94:23|Signal scale_factor1 is undriven 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":95:11:95:23|Signal scale_factor3 is undriven 
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:18:82:20|Referenced variable sw2 is not in sensitivity list
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:24:82:26|Referenced variable sw1 is not in sensitivity list
+@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to red_led1 assign '0'; register removed by optimization
+@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to green_led2 assign '0'; register removed by optimization
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":76:4:76:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":79:21:79:25|Referenced variable scale is not in sensitivity list
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":83:33:83:34|Referenced variable sw is not in sensitivity list
+@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal cnt[31:0].
+@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal tmp_clk.
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":80:21:80:25|Referenced variable scale is not in sensitivity list
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_area_report.xml b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_area_report.xml
new file mode 100644
index 0000000..8b8db68
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_area_report.xml
@@ -0,0 +1,33 @@
+
+
+
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_fpga_mapper_resourceusage.rpt
+Resource Usage
+
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_fpga_mapper_hier_area_report.xml
+Hierarchical Area Report
+
+
+108
+
+
+115
+
+
+0
+
+
+7
+
+
+2
+
+
+159
+
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_combined_clk.rpt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_combined_clk.rpt
new file mode 100644
index 0000000..5fcedea
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_combined_clk.rpt
@@ -0,0 +1,18 @@
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+Clock optimization not enabled
+1 non-gated/non-generated clock tree(s) driving 115 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+================================= Non-Gated/Non-Generated Clocks =================================
+Clock Tree ID     Driving Element     Drive Element Type           Fanout     Sample Instance     
+--------------------------------------------------------------------------------------------------
+@K:CKID0001       clk                 clock definition on port     115        Display_out.red_led2
+==================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_errors.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_errors.txt
new file mode 100644
index 0000000..e69de29
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_hier_area.csv b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_hier_area.csv
new file mode 100644
index 0000000..cd2a72b
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_hier_area.csv
@@ -0,0 +1,9 @@
+
+. Module name, SLE, CFG, ARI1, BUFFER, MACC, RAM1K18, RAM64X18, GLOBAL, IO
+. LedBlinkingDSpeed, 115, 51, 108, 0, 0, 0, 0, 2, 7
+.	. ClkGen, 27, 12, 26, 0, 0, 0, 0, 0, 0
+.	. ClkGenNoSwitch, 28, 12, 27, 0, 0, 0, 0, 0, 0
+.	. ClkGenNoSwitch_1, 29, 12, 28, 0, 0, 0, 0, 0, 0
+.	. ClkGen_1, 28, 12, 27, 0, 0, 0, 0, 0, 0
+.	. Display, 2, 2, 0, 0, 0, 0, 0, 0, 0
+.	. Reset_out, 1, 1, 0, 0, 0, 0, 0, 1, 0
\ No newline at end of file
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_hier_area_report.xml b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_hier_area_report.xml
new file mode 100644
index 0000000..c6deaa8
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_hier_area_report.xml
@@ -0,0 +1,103 @@
+
+
+
+
+Module name
+SLE
+CFG
+ARI1
+BUFFER
+MACC
+RAM1K18
+RAM64X18
+GLOBAL
+IO
+
+
+LedBlinkingDSpeed
+115
+51
+108
+0
+0
+0
+0
+2
+7
+
+ClkGen
+27
+12
+26
+0
+0
+0
+0
+0
+0
+
+
+ClkGenNoSwitch
+28
+12
+27
+0
+0
+0
+0
+0
+0
+
+
+ClkGenNoSwitch_1
+29
+12
+28
+0
+0
+0
+0
+0
+0
+
+
+ClkGen_1
+28
+12
+27
+0
+0
+0
+0
+0
+0
+
+
+Display
+2
+2
+0
+0
+0
+0
+0
+0
+0
+
+
+Reset_out
+1
+1
+0
+0
+0
+0
+0
+1
+0
+
+
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_notes.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_notes.txt
new file mode 100644
index 0000000..0cd9926
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_notes.txt
@@ -0,0 +1,30 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF667 |Clock conversion disabled 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd":81:4:81:5|Removing sequential instance Initial_blinking_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: BN362 :"c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd":80:4:80:5|Removing sequential instance Fast_clk_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N: FP130 |Promoting Net reset on CLKINT  I_103 
+@N: FP130 |Promoting Net clk_c on CLKINT  I_104 
+@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
+@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_opt_report.xml b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_opt_report.xml
new file mode 100644
index 0000000..1be12d5
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+
+
+
+
+1 / 0
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_fpga_mapper_combined_clk.rpt
+START OF CLOCK OPTIMIZATION REPORT
+
+
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_resourceusage.rpt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_resourceusage.rpt
new file mode 100644
index 0000000..80dbebb
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_resourceusage.rpt
@@ -0,0 +1,38 @@
+Resource Usage Report for LedBlinkingDSpeed 
+
+Mapping to part: m2gl025vf256std
+Cell usage:
+CLKINT          2 uses
+CFG2           4 uses
+CFG3           9 uses
+CFG4           38 uses
+
+Carry primitives used for arithmetic functions:
+ARI1           108 uses
+
+
+Sequential Cells: 
+SLE            115 uses
+
+DSP Blocks:    0
+
+I/O ports: 7
+I/O primitives: 7
+INBUF          3 uses
+OUTBUF         4 uses
+
+
+Global Clock Buffers: 2
+
+
+Total LUTs:    159
+
+Extra resources required for RAM and MACC interface logic during P&R:
+
+RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
+RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
+MACC     Interface Logic : SLEs = 0; LUTs = 0;
+
+Total number of SLEs after P&R:  115 + 0 + 0 + 0 = 115;
+Total number of LUTs after P&R:  159 + 0 + 0 + 0 = 159;
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_runstatus.xml b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_runstatus.xml
new file mode 100644
index 0000000..ca850e7
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+
+
+
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_fpga_mapper.srr
+Synopsys Generic Technology Mapper
+
+
+Completed
+
+
+
+30
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_fpga_mapper_notes.txt
+
+
+
+0
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_fpga_mapper_warnings.txt
+
+
+
+0
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_fpga_mapper_errors.txt
+
+
+
+0h:00m:01s
+
+
+0h:00m:01s
+
+
+135MB
+
+
+1477216773
+
+
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_timing_report.xml b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_timing_report.xml
new file mode 100644
index 0000000..42e45e0
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_timing_report.xml
@@ -0,0 +1,23 @@
+
+
+
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_fpga_mapper.srr
+START OF TIMING REPORT
+
+
+Clock Name
+Req Freq
+Est Freq
+Slack
+
+
+LedBlinkingDSpeed|clk
+50.0 MHz
+135.9 MHz
+12.640
+
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_warnings.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_fpga_mapper_warnings.txt
new file mode 100644
index 0000000..e69de29
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_errors.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_errors.txt
new file mode 100644
index 0000000..e69de29
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_notes.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_notes.txt
new file mode 100644
index 0000000..f192e2b
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_notes.txt
@@ -0,0 +1,3 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF667 |Clock conversion disabled 
+@N: BN225 |Writing default property annotation file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap.
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_runstatus.xml b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_runstatus.xml
new file mode 100644
index 0000000..c39882f
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_runstatus.xml
@@ -0,0 +1,46 @@
+
+
+
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_premap.srr
+Synopsys Generic Technology Pre-mapping
+
+
+Completed
+
+
+
+3
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_premap_notes.txt
+
+
+
+0
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_premap_warnings.txt
+
+
+
+0
+
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_premap_errors.txt
+
+
+
+0h:00m:00s
+
+
+0h:00m:00s
+
+
+133MB
+
+
+1477216772
+
+
+
diff --git a/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_warnings.txt b/Lab2_VHDL/synthesis/synlog/report/LedBlinkingDSpeed_premap_warnings.txt
new file mode 100644
index 0000000..e69de29
diff --git a/Lab2_VHDL/synthesis/synlog/syntax_constraint_check.rpt.rptmap b/Lab2_VHDL/synthesis/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644
index 0000000..d8bab10
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./LedBlinkingDSpeed_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
diff --git a/Lab2_VHDL/synthesis/synplify.log b/Lab2_VHDL/synthesis/synplify.log
new file mode 100644
index 0000000..11c9207
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synplify.log
@@ -0,0 +1,99 @@
+sourcing C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\message_override.tcl
+
+
+Starting:    C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\mbin\synbatch.exe
+Install:     C:\tools\Microsemi\Libero_SoC_v11.7\Synplify
+Hostname:    LOSANGLAP73674
+Date:        Sun Oct 23 02:59:30 2016
+Version:     J-2015.03M-SP1-2
+
+Arguments:   -product synplify_pro -licensetype synplifypro_actel -batch -log synplify.log LedBlinkingDSpeed_syn.tcl
+ProductType: synplify_pro
+
+License checkout: synplifypro_actel
+License: synplifypro_actel node-locked 
+Licensed Vendor: actel
+License Option: actel_oem
+
+Running in Vendor Mode
+
+
+auto_infer_blackbox is not supported in current product.
+
+log file: "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr"
+
+Running: synthesis in foreground
+
+
+
+Running LedBlinkingDSpeed_syn|synthesis
+
+
+Running: compile (Compile) on LedBlinkingDSpeed_syn|synthesis
+
+
+Running: compile_flow (Compile Process) on LedBlinkingDSpeed_syn|synthesis
+
+
+Running: compiler (Compile Input) on LedBlinkingDSpeed_syn|synthesis
+
+Copied C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs to C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srs
+
+
+compiler Completed
+Return Code: 0
+Run Time:0h:00m:01s
+
+
+Running: multi_srs_gen (Multi-srs Generator) on LedBlinkingDSpeed_syn|synthesis
+
+Copied C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs to C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_s.srs
+
+
+multi_srs_gen Completed
+Return Code: 0
+Run Time:0h:00m:00s
+
+Copied C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_mult.srs to C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srs
+
+Complete: Compile Process on LedBlinkingDSpeed_syn|synthesis
+
+
+Running: premap (Pre-mapping) on LedBlinkingDSpeed_syn|synthesis
+
+Copied C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap to C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_s.sap
+
+Copied C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.fse to C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_s.fse
+
+
+premap Completed
+Return Code: 0
+Run Time:0h:00m:01s
+
+Complete: Compile on LedBlinkingDSpeed_syn|synthesis
+
+
+Running: map (Map) on LedBlinkingDSpeed_syn|synthesis
+
+
+Running: fpga_mapper (Map & Optimize) on LedBlinkingDSpeed_syn|synthesis
+
+Copied C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_m.srm to C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srm
+
+
+fpga_mapper Completed
+Return Code: 0
+Run Time:0h:00m:02s
+
+Complete: Map on LedBlinkingDSpeed_syn|synthesis
+
+Complete: Logic Synthesis on LedBlinkingDSpeed_syn|synthesis
+
+TCL script complete: "LedBlinkingDSpeed_syn.tcl"
+
+exit status=0
+
+exit status=0
+
+License checkin: synplifypro_actel
+
diff --git a/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed.plg b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed.plg
new file mode 100644
index 0000000..aac1e0f
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed.plg
@@ -0,0 +1,17 @@
+@P:  Worst Slack : 12.640
+@P:  LedBlinkingDSpeed|clk - Estimated Frequency : 135.9 MHz
+@P:  LedBlinkingDSpeed|clk - Requested Frequency : 50.0 MHz
+@P:  LedBlinkingDSpeed|clk - Estimated Period : 7.360
+@P:  LedBlinkingDSpeed|clk - Requested Period : 20.000
+@P:  LedBlinkingDSpeed|clk - Slack : 12.640
+@P:  Worst Slack(min analysis) : 0.545
+@P:  LedBlinkingDSpeed|clk - Estimated Frequency(min analysis) : 135.9 MHz
+@P:  LedBlinkingDSpeed|clk - Requested Frequency(min analysis) : 50.0 MHz
+@P:  LedBlinkingDSpeed|clk - Estimated Period(min analysis) : 7.360
+@P:  LedBlinkingDSpeed|clk - Requested Period(min analysis) : 20.000
+@P:  LedBlinkingDSpeed|clk - Slack(min analysis) : 12.640
+@P: LedBlinkingDSpeed Part : m2gl025vf256std
+@P: LedBlinkingDSpeed Register bits  : 115 
+@P: LedBlinkingDSpeed DSP Blocks  : 0
+@P: LedBlinkingDSpeed I/O primitives : 7
+@P:  CPU Time : 0h:00m:01s
diff --git a/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_multi_srs_gen_srr.htm b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_multi_srs_gen_srr.htm
new file mode 100644
index 0000000..6e2e833
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_multi_srs_gen_srr.htm
@@ -0,0 +1,13 @@
+
+
+Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:53:22 2016
+
+###########################################################]
+
+

diff --git a/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_multi_srs_gen_toc.htm b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_multi_srs_gen_toc.htm
new file mode 100644
index 0000000..bb3836b
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_multi_srs_gen_toc.htm
@@ -0,0 +1,23 @@
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
+ 
\ No newline at end of file
diff --git a/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_srr.htm b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_srr.htm
new file mode 100644
index 0000000..2291185
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_srr.htm
@@ -0,0 +1,555 @@
+
+
+#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015
+#install: C:\tools\Microsemi\Libero_SoC_v11.7\Synplify
+#OS: Windows 7 6.1
+#Hostname: LOSANGLAP73674
+
+#Implementation: synthesis
+
+Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N:CD720 : std.vhd(146) | Setting time resolution to ns
+@N: : LedBlinkingDSpeed.vhd(60) | Top entity is set to LedBlinkingDSpeed.
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd changed - recompiling
+VHDL syntax check successful!
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd changed - recompiling
+@N:CD231 : std1164.vhd(890) | Using onehot encoding for type mvl9plus ('U'="1000000000")
+@N:CD630 : LedBlinkingDSpeed.vhd(60) | Synthesizing work.ledblinkingdspeed.architecture_ledblinkingdspeed 
+@W:CD638 : LedBlinkingDSpeed.vhd(93) | Signal scale_factor0 is undriven 
+@W:CD638 : LedBlinkingDSpeed.vhd(94) | Signal scale_factor1 is undriven 
+@W:CD638 : LedBlinkingDSpeed.vhd(95) | Signal scale_factor3 is undriven 
+@N:CD630 : Display.vhd(54) | Synthesizing work.display.architecture_display 
+@W:CG296 : Display.vhd(77) | Incomplete sensitivity list - assuming completeness
+@W:CG290 : Display.vhd(82) | Referenced variable sw2 is not in sensitivity list
+@W:CG290 : Display.vhd(82) | Referenced variable sw1 is not in sensitivity list
+Post processing for work.display.architecture_display
+@W:CL111 : Display.vhd(84) | All reachable assignments to red_led1 assign '0'; register removed by optimization
+@W:CL111 : Display.vhd(84) | All reachable assignments to green_led2 assign '0'; register removed by optimization
+@N:CD630 : ClkGen.vhd(56) | Synthesizing work.clkgen.architecture_clkgen 
+@W:CG296 : ClkGen.vhd(76) | Incomplete sensitivity list - assuming completeness
+@W:CG290 : ClkGen.vhd(79) | Referenced variable scale is not in sensitivity list
+@W:CG290 : ClkGen.vhd(83) | Referenced variable sw is not in sensitivity list
+Post processing for work.clkgen.architecture_clkgen
+@W:CL113 : ClkGen.vhd(80) | Feedback mux created for signal cnt[31:0].
+@W:CL113 : ClkGen.vhd(80) | Feedback mux created for signal tmp_clk.
+@N:CD630 : ClkGenNoSwitch.vhd(56) | Synthesizing work.clkgennoswitch.architecture_clkgennoswitch 
+@W:CG296 : ClkGenNoSwitch.vhd(77) | Incomplete sensitivity list - assuming completeness
+@W:CG290 : ClkGenNoSwitch.vhd(80) | Referenced variable scale is not in sensitivity list
+Post processing for work.clkgennoswitch.architecture_clkgennoswitch
+@N:CD630 : Reset_out.vhd(55) | Synthesizing work.reset_out.architecture_reset_out 
+Post processing for work.reset_out.architecture_reset_out
+Post processing for work.ledblinkingdspeed.architecture_ledblinkingdspeed
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:30 2016
+
+###########################################################]
+Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N: :  | Running in 64-bit mode 
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:30 2016
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:30 2016
+
+###########################################################]
+Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
+@N: :  | Running in 64-bit mode 
+File C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:31 2016
+
+###########################################################]
+Pre-mapping Report
+
+Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
+Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2015.03M-SP1-2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+Reading constraint file: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc
+Linked File: LedBlinkingDSpeed_scck.rpt
+Printing clock  summary report in "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF667 :  | Clock conversion disabled  
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+syn_allowed_resources : blockrams=31  set on top level netlist LedBlinkingDSpeed
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
+
+
+
+@S |Clock Summary
+*****************
+
+Start                     Requested     Requested     Clock        Clock           
+Clock                     Frequency     Period        Type         Group           
+-----------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk     50.0 MHz      20.000        declared     default_clkgroup
+===================================================================================
+
+Finished Pre Mapping Phase.
+@N:BN225 :  | Writing default property annotation file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap. 
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:32 2016
+
+###########################################################]
+Map & Optimize Report
+
+Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
+Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2015.03M-SP1-2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF667 :  | Clock conversion disabled  
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
+
+@N: : clkgennoswitch.vhd(81) | Found counter in view:work.ClkGenNoSwitch(architecture_clkgennoswitch) inst cnt[31:0]
+@N: : clkgen.vhd(80) | Found counter in view:work.ClkGen(architecture_clkgen) inst cnt[31:0]
+@N: : clkgennoswitch.vhd(81) | Found counter in view:work.ClkGenNoSwitch_0(architecture_clkgennoswitch) inst cnt[31:0]
+@N: : clkgen.vhd(80) | Found counter in view:work.ClkGen_0(architecture_clkgen) inst cnt[31:0]
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW1.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgennoswitch.vhd(81) | Removing sequential instance Initial_blinking_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW2.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+@N:BN362 : clkgen.vhd(80) | Removing sequential instance Fast_clk_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs 
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:00s		    10.53ns		 165 /       115
+@N:FP130 :  | Promoting Net reset on CLKINT  I_103  
+@N:FP130 :  | Promoting Net clk_c on CLKINT  I_104  
+
+Added 0 Buffers
+Added 0 Cells via replication
+	Added 0 Sequential Cells via replication
+	Added 0 Combinational Cells via replication
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+Clock optimization not enabled
+1 non-gated/non-generated clock tree(s) driving 115 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+================================= Non-Gated/Non-Generated Clocks =================================
+Clock Tree ID     Driving Element     Drive Element Type           Fanout     Sample Instance     
+--------------------------------------------------------------------------------------------------
+ClockId0001        clk                 clock definition on port     115        Display_out.red_led2
+==================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 134MB)
+
+Writing Analyst data base C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)
+
+Writing EDIF Netlist and constraint files
+@N:BW103 :  | Synopsys Constraint File time units using default value of 1ns  
+@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  
+J-2015.03M-SP1-2
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+Found clock LedBlinkingDSpeed|clk with period 20.00ns 
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Sun Oct 23 02:59:33 2016
+#
+
+
+Top view:               LedBlinkingDSpeed
+Requested Frequency:    50.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc
+                       
+@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 
+
+@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 12.640
+
+                          Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock            Frequency     Frequency     Period        Period        Slack      Type         Group           
+--------------------------------------------------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk     50.0 MHz      135.9 MHz     20.000        7.360         12.640     declared     default_clkgroup
+==========================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------
+Starting               Ending                 |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------
+LedBlinkingDSpeed|clk  LedBlinkingDSpeed|clk  |  20.000      12.640  |  No paths    -      |  No paths    -      |  No paths    -    
+=====================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: LedBlinkingDSpeed|clk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                 Starting                                               Arrival           
+Instance                         Reference                 Type     Pin     Net         Time        Slack 
+                                 Clock                                                                    
+----------------------------------------------------------------------------------------------------------
+Initial_blinking_SW2.cnt[8]      LedBlinkingDSpeed|clk     SLE      Q       cnt[8]      0.108       12.640
+Initial_blinking_SW2.cnt[9]      LedBlinkingDSpeed|clk     SLE      Q       cnt[9]      0.108       12.734
+Initial_blinking_SW2.cnt[13]     LedBlinkingDSpeed|clk     SLE      Q       cnt[13]     0.108       12.747
+Initial_blinking_SW2.cnt[10]     LedBlinkingDSpeed|clk     SLE      Q       cnt[10]     0.108       12.809
+Initial_blinking_SW2.cnt[14]     LedBlinkingDSpeed|clk     SLE      Q       cnt[14]     0.108       12.825
+Initial_blinking_SW2.cnt[11]     LedBlinkingDSpeed|clk     SLE      Q       cnt[11]     0.108       12.857
+Initial_blinking_SW2.cnt[15]     LedBlinkingDSpeed|clk     SLE      Q       cnt[15]     0.108       12.871
+Initial_blinking_SW2.cnt[16]     LedBlinkingDSpeed|clk     SLE      Q       cnt[16]     0.108       12.948
+Fast_clk_SW2.cnt[7]              LedBlinkingDSpeed|clk     SLE      Q       cnt[7]      0.087       13.391
+Fast_clk_SW1.cnt[6]              LedBlinkingDSpeed|clk     SLE      Q       cnt[6]      0.087       13.407
+==========================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                 Starting                                                 Required           
+Instance                         Reference                 Type     Pin     Net           Time         Slack 
+                                 Clock                                                                       
+-------------------------------------------------------------------------------------------------------------
+Initial_blinking_SW2.cnt[26]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[26]     19.745       12.640
+Initial_blinking_SW2.cnt[25]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[25]     19.745       12.656
+Initial_blinking_SW2.cnt[24]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[24]     19.745       12.673
+Initial_blinking_SW2.cnt[23]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[23]     19.745       12.689
+Initial_blinking_SW2.cnt[22]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[22]     19.745       12.705
+Initial_blinking_SW2.cnt[21]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[21]     19.745       12.722
+Initial_blinking_SW2.cnt[20]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[20]     19.745       12.738
+Initial_blinking_SW2.cnt[19]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[19]     19.745       12.754
+Initial_blinking_SW2.cnt[18]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[18]     19.745       12.770
+Initial_blinking_SW2.cnt[17]     LedBlinkingDSpeed|clk     SLE      D       cnt_s[17]     19.745       12.787
+=============================================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      20.000
+    - Setup time:                            0.255
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         19.745
+
+    - Propagation time:                      7.105
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     12.640
+
+    Number of logic level(s):                32
+    Starting point:                          Initial_blinking_SW2.cnt[8] / Q
+    Ending point:                            Initial_blinking_SW2.cnt[26] / D
+    The start point is clocked by            LedBlinkingDSpeed|clk [rising] on pin CLK
+    The end   point is clocked by            LedBlinkingDSpeed|clk [rising] on pin CLK
+
+Instance / Net                                      Pin      Pin               Arrival     No. of    
+Name                                       Type     Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------
+Initial_blinking_SW2.cnt[8]                SLE      Q        Out     0.108     0.108       -         
+cnt[8]                                     Net      -        -       0.674     -           2         
+Initial_blinking_SW2.cnt_RNI8JG21[10]      CFG4     D        In      -         0.783       -         
+Initial_blinking_SW2.cnt_RNI8JG21[10]      CFG4     Y        Out     0.317     1.100       -         
+N_176                                      Net      -        -       0.630     -           2         
+Initial_blinking_SW2.cnt_RNIIH0I1[12]      CFG3     C        In      -         1.730       -         
+Initial_blinking_SW2.cnt_RNIIH0I1[12]      CFG3     Y        Out     0.226     1.956       -         
+N_87                                       Net      -        -       0.556     -           1         
+Initial_blinking_SW2.cnt_RNI4GAR1[17]      CFG4     B        In      -         2.511       -         
+Initial_blinking_SW2.cnt_RNI4GAR1[17]      CFG4     Y        Out     0.148     2.660       -         
+N_93                                       Net      -        -       0.556     -           1         
+Initial_blinking_SW2.cnt_RNI9EVA2[20]      CFG4     C        In      -         3.216       -         
+Initial_blinking_SW2.cnt_RNI9EVA2[20]      CFG4     Y        Out     0.226     3.441       -         
+N_103                                      Net      -        -       0.556     -           1         
+Initial_blinking_SW2.cnt_RNIOCCK2[27]      ARI1     B        In      -         3.997       -         
+Initial_blinking_SW2.cnt_RNIOCCK2[27]      ARI1     Y        Out     0.165     4.161       -         
+cnt_RNIOCCK2_Y[27]                         Net      -        -       1.145     -           27        
+Initial_blinking_SW2.cnt_RNITNTM5[0]       ARI1     B        In      -         5.306       -         
+Initial_blinking_SW2.cnt_RNITNTM5[0]       ARI1     FCO      Out     0.201     5.507       -         
+cnt_cry[0]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI34FP8[1]       ARI1     FCI      In      -         5.507       -         
+Initial_blinking_SW2.cnt_RNI34FP8[1]       ARI1     FCO      Out     0.016     5.523       -         
+cnt_cry[1]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIAH0SB[2]       ARI1     FCI      In      -         5.523       -         
+Initial_blinking_SW2.cnt_RNIAH0SB[2]       ARI1     FCO      Out     0.016     5.540       -         
+cnt_cry[2]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIIVHUE[3]       ARI1     FCI      In      -         5.540       -         
+Initial_blinking_SW2.cnt_RNIIVHUE[3]       ARI1     FCO      Out     0.016     5.556       -         
+cnt_cry[3]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIRE31I[4]       ARI1     FCI      In      -         5.556       -         
+Initial_blinking_SW2.cnt_RNIRE31I[4]       ARI1     FCO      Out     0.016     5.572       -         
+cnt_cry[4]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI5VK3L[5]       ARI1     FCI      In      -         5.572       -         
+Initial_blinking_SW2.cnt_RNI5VK3L[5]       ARI1     FCO      Out     0.016     5.589       -         
+cnt_cry[5]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIGG66O[6]       ARI1     FCI      In      -         5.589       -         
+Initial_blinking_SW2.cnt_RNIGG66O[6]       ARI1     FCO      Out     0.016     5.605       -         
+cnt_cry[6]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIS2O8R[7]       ARI1     FCI      In      -         5.605       -         
+Initial_blinking_SW2.cnt_RNIS2O8R[7]       ARI1     FCO      Out     0.016     5.621       -         
+cnt_cry[7]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI9M9BU[8]       ARI1     FCI      In      -         5.621       -         
+Initial_blinking_SW2.cnt_RNI9M9BU[8]       ARI1     FCO      Out     0.016     5.638       -         
+cnt_cry[8]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNINARD11[9]      ARI1     FCI      In      -         5.638       -         
+Initial_blinking_SW2.cnt_RNINARD11[9]      ARI1     FCO      Out     0.016     5.654       -         
+cnt_cry[9]                                 Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIDPA541[10]     ARI1     FCI      In      -         5.654       -         
+Initial_blinking_SW2.cnt_RNIDPA541[10]     ARI1     FCO      Out     0.016     5.670       -         
+cnt_cry[10]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI49QS61[11]     ARI1     FCI      In      -         5.670       -         
+Initial_blinking_SW2.cnt_RNI49QS61[11]     ARI1     FCO      Out     0.016     5.686       -         
+cnt_cry[11]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNISP9K91[12]     ARI1     FCI      In      -         5.686       -         
+Initial_blinking_SW2.cnt_RNISP9K91[12]     ARI1     FCO      Out     0.016     5.703       -         
+cnt_cry[12]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNILBPBC1[13]     ARI1     FCI      In      -         5.703       -         
+Initial_blinking_SW2.cnt_RNILBPBC1[13]     ARI1     FCO      Out     0.016     5.719       -         
+cnt_cry[13]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIFU83F1[14]     ARI1     FCI      In      -         5.719       -         
+Initial_blinking_SW2.cnt_RNIFU83F1[14]     ARI1     FCO      Out     0.016     5.735       -         
+cnt_cry[14]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIAIOQH1[15]     ARI1     FCI      In      -         5.735       -         
+Initial_blinking_SW2.cnt_RNIAIOQH1[15]     ARI1     FCO      Out     0.016     5.752       -         
+cnt_cry[15]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI678IK1[16]     ARI1     FCI      In      -         5.752       -         
+Initial_blinking_SW2.cnt_RNI678IK1[16]     ARI1     FCO      Out     0.016     5.768       -         
+cnt_cry[16]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI3TN9N1[17]     ARI1     FCI      In      -         5.768       -         
+Initial_blinking_SW2.cnt_RNI3TN9N1[17]     ARI1     FCO      Out     0.016     5.784       -         
+cnt_cry[17]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI1K71Q1[18]     ARI1     FCI      In      -         5.784       -         
+Initial_blinking_SW2.cnt_RNI1K71Q1[18]     ARI1     FCO      Out     0.016     5.801       -         
+cnt_cry[18]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI0CNOS1[19]     ARI1     FCI      In      -         5.801       -         
+Initial_blinking_SW2.cnt_RNI0CNOS1[19]     ARI1     FCO      Out     0.016     5.817       -         
+cnt_cry[19]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNINS7GV1[20]     ARI1     FCI      In      -         5.817       -         
+Initial_blinking_SW2.cnt_RNINS7GV1[20]     ARI1     FCO      Out     0.016     5.833       -         
+cnt_cry[20]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIFEO722[21]     ARI1     FCI      In      -         5.833       -         
+Initial_blinking_SW2.cnt_RNIFEO722[21]     ARI1     FCO      Out     0.016     5.849       -         
+cnt_cry[21]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI819V42[22]     ARI1     FCI      In      -         5.849       -         
+Initial_blinking_SW2.cnt_RNI819V42[22]     ARI1     FCO      Out     0.016     5.866       -         
+cnt_cry[22]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNI2LPM72[23]     ARI1     FCI      In      -         5.866       -         
+Initial_blinking_SW2.cnt_RNI2LPM72[23]     ARI1     FCO      Out     0.016     5.882       -         
+cnt_cry[23]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIT9AEA2[24]     ARI1     FCI      In      -         5.882       -         
+Initial_blinking_SW2.cnt_RNIT9AEA2[24]     ARI1     FCO      Out     0.016     5.898       -         
+cnt_cry[24]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIPVQ5D2[25]     ARI1     FCI      In      -         5.898       -         
+Initial_blinking_SW2.cnt_RNIPVQ5D2[25]     ARI1     FCO      Out     0.016     5.915       -         
+cnt_cry[25]                                Net      -        -       0.000     -           1         
+Initial_blinking_SW2.cnt_RNIMMBTF2[26]     ARI1     FCI      In      -         5.915       -         
+Initial_blinking_SW2.cnt_RNIMMBTF2[26]     ARI1     S        Out     0.073     5.988       -         
+cnt_s[26]                                  Net      -        -       1.117     -           1         
+Initial_blinking_SW2.cnt[26]               SLE      D        In      -         7.105       -         
+=====================================================================================================
+Total path delay (propagation time + setup) of 7.360 is 2.126(28.9%) logic and 5.234(71.1%) route.
+Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
+
+
+
+##### END OF TIMING REPORT #####]
+
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)
+
+---------------------------------------
+Resource Usage Report for LedBlinkingDSpeed 
+
+Mapping to part: m2gl025vf256std
+Cell usage:
+CLKINT          2 uses
+CFG2           4 uses
+CFG3           9 uses
+CFG4           38 uses
+
+Carry primitives used for arithmetic functions:
+ARI1           108 uses
+
+
+Sequential Cells: 
+SLE            115 uses
+
+DSP Blocks:    0
+
+I/O ports: 7
+I/O primitives: 7
+INBUF          3 uses
+OUTBUF         4 uses
+
+
+Global Clock Buffers: 2
+
+
+Total LUTs:    159
+
+Extra resources required for RAM and MACC interface logic during P&R:
+
+RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
+RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
+MACC     Interface Logic : SLEs = 0; LUTs = 0;
+
+Total number of SLEs after P&R:  115 + 0 + 0 + 0 = 115;
+Total number of LUTs after P&R:  159 + 0 + 0 + 0 = 159;
+
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 135MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Oct 23 02:59:34 2016
+
+###########################################################]
+
+

diff --git a/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_toc.htm b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_toc.htm
new file mode 100644
index 0000000..c705fd8
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/LedBlinkingDSpeed_toc.htm
@@ -0,0 +1,43 @@
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
+ 
\ No newline at end of file
diff --git a/Lab2_VHDL/synthesis/syntmp/closed.png b/Lab2_VHDL/synthesis/syntmp/closed.png
new file mode 100644
index 0000000..0d78634
Binary files /dev/null and b/Lab2_VHDL/synthesis/syntmp/closed.png differ
diff --git a/Lab2_VHDL/synthesis/syntmp/cmdrec_compiler.log b/Lab2_VHDL/synthesis/syntmp/cmdrec_compiler.log
new file mode 100644
index 0000000..175ce8d
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/cmdrec_compiler.log
@@ -0,0 +1,11 @@
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\c_hdl.exe  -osyn  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs  -top  work.LedBlinkingDSpeed  -hdllog  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_compiler.srr  -encrypt  -mp  1  -vhdl  -prodtype  synplify_pro  -infer_seqShift -primux -dspmac -pqdpadd -fixsmult -sdff_counter -divnmod -nram  -encrypt  -pro  -dmgen  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -vhdl2008  -ignore_undefined_lib  -lib work C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd -lib work C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd -lib work C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd -lib work C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd -lib work C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd 
+rc:0 success:1
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs|o|1477216770|7473
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_compiler.srr|o|1477216770|5931
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd|i|1477216350|4624
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd|i|1477216350|4722
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd|i|1477216350|4734
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd|i|1477216350|3699
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd|i|1477216739|8890
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin\c_hdl.exe|i|1449250522|1295872
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\c_hdl.exe|i|1449250524|1897472
diff --git a/Lab2_VHDL/synthesis/syntmp/cmdrec_fpga_mapper.log b/Lab2_VHDL/synthesis/syntmp/cmdrec_fpga_mapper.log
new file mode 100644
index 0000000..bc964c3
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/cmdrec_fpga_mapper.log
@@ -0,0 +1,16 @@
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis   -part M2GL025  -package VF256  -grade STD    -maxfan 10000 -clock_globalthreshold 2 -async_globalthreshold 12 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -RWCheckOnRam 0 -summaryfile C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_fpga_mapper.xml  -top_level_module  work.LedBlinkingDSpeed  -licensetype  synplifypro_actel  -flow mapping  -mp  1  -prjfile  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\scratchproject.prs  -implementation  synthesis  -multisrs  -oedif  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn   -freq 100.000   -tcl  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_prem.srd  -sap  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap  -otap  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.tap  -omap  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.map  -devicelib  C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v  -sap  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap  -ologparam  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\syntmp\LedBlinkingDSpeed.plg  -osyn  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srm  -prjdir  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\  -prjname  LedBlinkingDSpeed_syn  -log  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_fpga_mapper.srr 
+rc:0 success:1
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\scratchproject.prs|o|1477216400|2331
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn|o|1477216773|182614
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc|i|1477216769|315
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_prem.srd|i|1477216772|10498
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap|o|1477216772|3780
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.tap|o|0|0
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.map|o|1477216774|28
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v|i|1449250530|16387
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap|o|1477216772|3780
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\syntmp\LedBlinkingDSpeed.plg|o|1477216774|895
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srm|o|1477216773|8001
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_fpga_mapper.srr|o|1477216774|30527
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin\m_generic.exe|i|1449767944|15814144
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\m_generic.exe|i|1449769556|27632640
diff --git a/Lab2_VHDL/synthesis/syntmp/cmdrec_multi_srs_gen.log b/Lab2_VHDL/synthesis/syntmp/cmdrec_multi_srs_gen.log
new file mode 100644
index 0000000..88dc19c
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/cmdrec_multi_srs_gen.log
@@ -0,0 +1,7 @@
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\syn_nfilter.exe  -link  -top  work.LedBlinkingDSpeed  -multisrs  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs  -osyn  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_mult.srs  -log  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_multi_srs_gen.srr 
+rc:0 success:1
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_comp.srs|i|1477216770|7473
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_mult.srs|o|1477216771|4627
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_multi_srs_gen.srr|o|1477216771|506
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin\syn_nfilter.exe|i|1449250524|3007488
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\syn_nfilter.exe|i|1449250526|3974144
diff --git a/Lab2_VHDL/synthesis/syntmp/cmdrec_premap.log b/Lab2_VHDL/synthesis/syntmp/cmdrec_premap.log
new file mode 100644
index 0000000..504750f
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/cmdrec_premap.log
@@ -0,0 +1,15 @@
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\m_generic.exe  -mp  1  -prjfile  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\scratchproject.prs  -implementation  synthesis  -prodtype  synplify_pro  -encrypt  -pro  -rundir  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis   -part M2GL025  -package VF256  -grade STD    -maxfan 10000 -clock_globalthreshold 2 -async_globalthreshold 12 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -RWCheckOnRam 0 -summaryfile C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\report\LedBlinkingDSpeed_premap.xml  -top_level_module  work.LedBlinkingDSpeed  -oedif  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn  -conchk_prepass  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_cck_prepass.rpt   -freq 100.000   -tcl  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_mult.srs  -flow prepass  -gcc_prepass  -osrd  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_prem.srd  -qsap  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap  -devicelib  C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v  -ologparam  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\syntmp\LedBlinkingDSpeed.plg  -osyn  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_prem.srd  -prjdir  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\  -prjname  LedBlinkingDSpeed_syn  -log  C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_premap.srr 
+rc:0 success:1
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\scratchproject.prs|o|1477216400|2331
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.edn|o|1477216470|79911
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed_cck_prepass.rpt|o|0|0
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\designer\LedBlinkingDSpeed\synthesis.fdc|i|1477216769|315
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_mult.srs|i|1477216771|4627
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_prem.srd|o|1477216772|10498
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap|o|1477216772|3780
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v|i|1449250530|16387
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\syntmp\LedBlinkingDSpeed.plg|o|1477216772|0
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synwork\LedBlinkingDSpeed_prem.srd|o|1477216772|10498
+C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\synlog\LedBlinkingDSpeed_premap.srr|o|1477216772|2708
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin\m_generic.exe|i|1449767944|15814144
+C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\bin64\m_generic.exe|i|1449769556|27632640
diff --git a/Lab2_VHDL/synthesis/syntmp/open.png b/Lab2_VHDL/synthesis/syntmp/open.png
new file mode 100644
index 0000000..a227005
Binary files /dev/null and b/Lab2_VHDL/synthesis/syntmp/open.png differ
diff --git a/Lab2_VHDL/synthesis/syntmp/run_option.xml b/Lab2_VHDL/synthesis/syntmp/run_option.xml
new file mode 100644
index 0000000..23f422e
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/run_option.xml
@@ -0,0 +1,20 @@
+ 
+ 
+ 
+     
+     
+     
+     
+     
+     
+     
+     
+
+
diff --git a/Lab2_VHDL/synthesis/syntmp/statusReport.html b/Lab2_VHDL/synthesis/syntmp/statusReport.html
new file mode 100644
index 0000000..49f5f7d
--- /dev/null
+++ b/Lab2_VHDL/synthesis/syntmp/statusReport.html
@@ -0,0 +1,110 @@
+ 
+ 			 			
+			Project Status Summary Page
+			
+			
+			
+ 			
+ 			
+
 
+ 
+ 
+ 		  
+		 
+
+
+ 
+ 
+  
 	     
Project Settings
  Project Name  LedBlinkingDSpeed_syn  Implementation Name  synthesis 
 
  Top Module  work.LedBlinkingDSpeed  Retiming  0 
  Resource Sharing  1  Fanout Guide  10000 
  Disable I/O Insertion  0  FSM Compiler  1 

	 
+ 				   
+         
+ 		
+ 			
+			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
+ 			
+         
+  
+  
+ 
+ 
+
+
+
+
+
+ 
+
+ 
+  
+ 
+
+
+
+
+
+
+ 
+
+ 
+  
+ 
+
+
+
+
+
+
+ 
+
+
+  
+  
+     
Run Status
Job NameStatusCPU TimeReal TimeMemoryDate/Time
 (compiler)Complete11150-0m:00s-10/23/2016
2:59:30 AM
 (premap)Complete3000m:00s0m:00s133MB10/23/2016
2:59:32 AM
 (fpga_mapper)Complete30000m:01s0m:01s135MB10/23/2016
2:59:33 AM
Multi-srs GeneratorComplete0m:00s10/23/2016
2:59:31 AM		 		

+ 
 
+ 
+ 				   
+ 
+  
+  
+
+
+
+ 
+
+
+
+ 
+
+
+
+ 
+
+    
Area Summary
 
 
 
Carry Cells 108Sequential Cells 115
DSP Blocks (MACC)
+(dsp_used) 0I/O Cells 7
Global Clock Buffers 2LUTs
+(total_luts) 159

 
+ 
+ 				   
+ 
+  
+ 
+    
+ 
+ 
+ 
Timing Summary
 
 
Clock NameReq FreqEst FreqSlack
 LedBlinkingDSpeed|clk50.0 MHz135.9 MHz12.640

+
 
+ 
+ 				   
+  
+
+ 
+
+    
Optimizations Summary
 
Combined Clock Conversion 1 / 0

 
+
 
+
 
+ 
\ No newline at end of file
diff --git a/Lab2_VHDL/synthesis/synwork/.cckTransfer b/Lab2_VHDL/synthesis/synwork/.cckTransfer
new file mode 100644
index 0000000..d229bd6
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/.cckTransfer differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_comp.fdep b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_comp.fdep
new file mode 100644
index 0000000..803a01d
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_comp.fdep
@@ -0,0 +1,45 @@
+#OPTIONS:"|-layerid|0|-orig_srs|C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\synthesis\\synwork\\LedBlinkingDSpeed_comp.srs|-top|work.LedBlinkingDSpeed|-prodtype|synplify_pro|-infer_seqShift|-primux|-dspmac|-pqdpadd|-fixsmult|-sdff_counter|-divnmod|-nram|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\bin64\\c_vhdl.exe":1449250526
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\location.map":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\snps_haps_pkg.vhd":1449250532
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std1164.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std_textio.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\numeric.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\umr_capim.vhd":1449250532
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\arith.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\unsigned.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\hyperents.vhd":1449250532
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\ClkGen.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\ClkGenNoSwitch.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\Display.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\Reset_out.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\LedBlinkingDSpeed.vhd":1477216739
+0			"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd" vhdl
+1			"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd" vhdl
+2			"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd" vhdl
+3			"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd" vhdl
+4			"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd" vhdl
+#Dependency Lists(Uses List)
+0 -1
+1 -1
+2 -1
+3 -1
+4 2 0 1 3
+#Dependency Lists(Users Of)
+0 4
+1 4
+2 4
+3 4
+4 -1
+#Design Unit to File Association
+module work ledblinkingdspeed 4
+arch work ledblinkingdspeed architecture_ledblinkingdspeed 4
+module work reset_out 3
+arch work reset_out architecture_reset_out 3
+module work display 2
+arch work display architecture_display 2
+module work clkgennoswitch 1
+arch work clkgennoswitch architecture_clkgennoswitch 1
+module work clkgen 0
+arch work clkgen architecture_clkgen 0
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_comp.srs b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_comp.srs
new file mode 100644
index 0000000..a448448
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_comp.srs differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_m.srm b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_m.srm
new file mode 100644
index 0000000..75e3af4
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_m.srm differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_m_srm/1.srm b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_m_srm/1.srm
new file mode 100644
index 0000000..0fb9902
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_m_srm/1.srm differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult.srs b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult.srs
new file mode 100644
index 0000000..75ff6c9
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult.srs differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult_srs/1.srs b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult_srs/1.srs
new file mode 100644
index 0000000..0bd3da3
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult_srs/1.srs differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult_srs/skeleton.srs b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult_srs/skeleton.srs
new file mode 100644
index 0000000..142dd99
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_mult_srs/skeleton.srs differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_prem.fse b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_prem.fse
new file mode 100644
index 0000000..e69de29
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_prem.srd b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_prem.srd
new file mode 100644
index 0000000..5008271
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_prem.srd differ
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.fse b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.fse
new file mode 100644
index 0000000..e69de29
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.sap b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.sap
new file mode 100644
index 0000000..133b8e4
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.sap
@@ -0,0 +1,199 @@
+%%% protect protected_file
+@ER
+8BNDCsk_F00bk#
+;
+osHRC0#C;H
+NR$3#MD_OF_O	CsG0NHO0FpMR;8
+
+R#7Hb$DN_0Fk;o
+
+HCRs8C_D8
+.;N3HR#_$MOODF	G_C0OsN0MHFR
+p;
+IMRFRs	pAC8D	HMH7Mo1CbC8sRNO0EHCkO0sDC_CD8LHHM	M#o8b8CC;o
+
+HDRBC_NsFbk0k;0#
+RNH3M#$_FODOC	_GN0sOF0HM;Rv
+H
+oRHQM0DHN_HLDMM	HoW_14N;
+H#R3$OM_D	FO_0CGs0NOHRFMv
+;
+owHRN_#0O_D	1;W4
+RNH3M#$_FODOC	_GN0sOF0HM;Rv
+H
+oRHQM0DHN_HLDMM	HoW_1.N;
+H#R3$OM_D	FO_0CGs0NOHRFMv
+;
+owHRN_#0O_D	1;W.
+RNH3M#$_FODOC	_GN0sOF0HM;Rv
+H
+oR#7Hb$DN_0Fk;H
+NR$3#MD_OF_O	CsG0NHO0FvMR;8
+
+R#wN0D_O	W_1.
+;
+oOHRMd0r49:j;H
+NR$3#MD_OF_O	CsG0NHO0FpMR;8
+
+R#wN0D_O	W_14
+;
+oOHRMd0r49:j;H
+NR$3#MD_OF_O	CsG0NHO0FpMR;8
+
+RHQM0DHN_HLDMM	HoW_1.
+;
+oOHRMd0r49:j;H
+NR$3#MD_OF_O	CsG0NHO0FpMR;8
+
+RHQM0DHN_HLDMM	HoW_14
+;
+oOHRMd0r49:j;H
+NR$3#MD_OF_O	CsG0NHO0FpMR;
+
+
+
+R
+8BNDCsk_F00bk#
+;
+osHRC0#C;H
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNH3FODOC	_8RoC"#sHC
+";oBbR;b
+NR#3H_FODO4	R;b
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNb3FODOC	_8RoC"#sHC
+";oOMRD
+	;N3MRHO#_D	FOR
+4;N3MROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+MOR3D	FO_oC8CsR"H"#C;8
+
+R#7Hb$DN_0Fk;o
+
+HsRoC_CMD4C8;H
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNH3FODOC	_8RoC"#sHC
+";N3HRNM#$OC_s#RC0"sM:C0#C"o;
+b;RB
+RNb3_H#OODF	;R4
+RNb3FODO"	RpAC8D	HMH7Mo1CbC8D|O	
+";N3bROODF	8_Co"CRsCH#"
+;
+osHRCD8_C;8.
+RNH3FODO"	RpAC8D	HMH7Mo1CbC8D|O	
+";N3HROODF	8_Co"CRsCH#"N;
+HNR3#O$M_#sCC"0RMC:s#"C0;b
+oR
+B;N3bRHO#_D	FOR
+4;N3bROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+bOR3D	FO_oC8CsR"H"#C;M
+oR	OD;M
+NR#3H_FODO4	R;M
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNM3FODOC	_8RoC"#sHC
+";
+IMRFRs	pAC8D	HMH7Mo1CbC8sRNO0EHCkO0sDC_CD8LHHM	M#o8b8CC;M
+oR	OD;M
+NR#3H_FODO4	R;M
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNM3FODOC	_8RoC"#sHC
+";N3PR#_$MObFlH_DCbMFH0;R4
+R
+8w0N#_	OD_.1W;o
+
+HlR0bD_O	N;
+HOR3D	FORC"p8HADMM	Hob71C|C8O"D	;H
+NRD3OF_O	CC8oRH"s#;C"
+RNH3FODOC	_MDNLCMR":.1W"N;
+HNR3#O$M_#sCC"0RMC:s#"C0;b
+oR
+B;N3bRHO#_D	FOR
+4;N3bROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+bOR3D	FO_oC8CsR"H"#C;o
+
+HMRO04rd:;j9
+RNH3FODO"	RpAC8D	HMH7Mo1CbC8D|O	
+";N3HROODF	8_Co"CRsCH#"N;
+HOR3D	FO_NCMLRDC"1M:W;."
+RNH3$N#MsO_C0#CR:"MsCC#0
+";oBbR;b
+NR#3H_FODO4	R;b
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNb3FODOC	_8RoC"#sHC
+";oOMRDM	Q;M
+NR#3H_FODO4	R;M
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNM3FODOC	_8RoC"#sHC
+";
+w8RN_#0O_D	1;W4
+H
+oRb0l_	OD;H
+NRD3OFRO	"8pCAMDH	oHM7C1bCO8|D;	"
+RNH3FODOC	_8RoC"#sHC
+";N3HROODF	M_CNCLDR:"M1"W4;H
+NR#3N$_MOsCC#0MR":#sCC;0"
+RobBN;
+bHR3#D_OFRO	4N;
+bOR3D	FORC"p8HADMM	Hob71C|C8O"D	;b
+NRD3OF_O	CC8oRH"s#;C"
+H
+oR0OMr:d4j
+9;N3HROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+HOR3D	FO_oC8CsR"H"#C;H
+NRD3OF_O	CLMND"CRMW:14
+";N3HRNM#$OC_s#RC0"sM:C0#C"o;
+b;RB
+RNb3_H#OODF	;R4
+RNb3FODO"	RpAC8D	HMH7Mo1CbC8D|O	
+";N3bROODF	8_Co"CRsCH#"o;
+MDRO	;QM
+RNM3_H#OODF	;R4
+RNM3FODO"	RpAC8D	HMH7Mo1CbC8D|O	
+";N3MROODF	8_Co"CRsCH#"
+;
+8MRQHN0HDD_LHHM	M1o_W
+.;
+RoH0_lbO;D	
+RNH3FODO"	RpAC8D	HMH7Mo1CbC8D|O	
+";N3HROODF	8_Co"CRsCH#"N;
+HNR3#O$M_#sCC"0RMC:s#"C0;b
+oR
+B;N3bRHO#_D	FOR
+4;N3bROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+bOR3D	FO_oC8CsR"H"#C;o
+
+HMRO04rd:;j9
+RNH3FODO"	RpAC8D	HMH7Mo1CbC8D|O	
+";N3HROODF	8_Co"CRsCH#"N;
+HNR3#O$M_#sCC"0RMC:s#"C0;b
+oR
+B;N3bRHO#_D	FOR
+4;N3bROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+bOR3D	FO_oC8CsR"H"#C;M
+oR	ODQ
+M;N3MRHO#_D	FOR
+4;N3MROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+MOR3D	FO_oC8CsR"H"#C;8
+
+RHQM0DHN_HLDMM	HoW_14
+;
+o0HRlOb_D
+	;N3HROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+HOR3D	FO_oC8CsR"H"#C;H
+NR#3N$_MOsCC#0MR":#sCC;0"
+RobBN;
+bHR3#D_OFRO	4N;
+bOR3D	FORC"p8HADMM	Hob71C|C8O"D	;b
+NRD3OF_O	CC8oRH"s#;C"
+H
+oR0OMr:d4j
+9;N3HROODF	pR"CD8AHHM	M1o7b8CC|	OD"N;
+HOR3D	FO_oC8CsR"H"#C;H
+NR#3N$_MOsCC#0MR":#sCC;0"
+RobBN;
+bHR3#D_OFRO	4N;
+bOR3D	FORC"p8HADMM	Hob71C|C8O"D	;b
+NRD3OF_O	CC8oRH"s#;C"
+RoMOQD	MN;
+MHR3#D_OFRO	4N;
+MOR3D	FORC"p8HADMM	Hob71C|C8O"D	;M
+NRD3OF_O	CC8oRH"s#;C"
diff --git a/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.srs b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.srs
new file mode 100644
index 0000000..a448448
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/LedBlinkingDSpeed_s.srs differ
diff --git a/Lab2_VHDL/synthesis/synwork/_mh_info b/Lab2_VHDL/synthesis/synwork/_mh_info
new file mode 100644
index 0000000..37bc105
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synwork/_mh_info
@@ -0,0 +1 @@
+|1|
diff --git a/Lab2_VHDL/synthesis/synwork/layer0.fdep b/Lab2_VHDL/synthesis/synwork/layer0.fdep
new file mode 100644
index 0000000..d4af3d6
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synwork/layer0.fdep
@@ -0,0 +1,52 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\synthesis\\synwork\\LedBlinkingDSpeed_comp.srs|-top|work.LedBlinkingDSpeed|-prodtype|synplify_pro|-infer_seqShift|-primux|-dspmac|-pqdpadd|-fixsmult|-sdff_counter|-divnmod|-nram|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\bin64\\c_vhdl.exe":1449250526
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\location.map":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\snps_haps_pkg.vhd":1449250532
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std1164.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std_textio.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\numeric.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\umr_capim.vhd":1449250532
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\arith.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\unsigned.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\hyperents.vhd":1449250532
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\ClkGen.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\ClkGenNoSwitch.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\Display.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\Reset_out.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\LedBlinkingDSpeed.vhd":1477216739
+0 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd" vhdl
+1 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd" vhdl
+2 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd" vhdl
+3 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd" vhdl
+4 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+1 -1
+2 -1
+3 -1
+4 3 1 0 2 
+
+# Dependency Lists (Users Of)
+0 4 
+1 4 
+2 4 
+3 4 
+4 -1
+
+# Design Unit to File Association
+arch work clkgen architecture_clkgen 0
+module work clkgen 0
+arch work clkgennoswitch architecture_clkgennoswitch 1
+module work clkgennoswitch 1
+arch work display architecture_display 2
+module work display 2
+arch work reset_out architecture_reset_out 3
+module work reset_out 3
+arch work ledblinkingdspeed architecture_ledblinkingdspeed 4
+module work ledblinkingdspeed 4
+
+
+# Configuration files used
diff --git a/Lab2_VHDL/synthesis/synwork/layer0.fdeporig b/Lab2_VHDL/synthesis/synwork/layer0.fdeporig
new file mode 100644
index 0000000..12c4af8
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synwork/layer0.fdeporig
@@ -0,0 +1,49 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\synthesis\\synwork\\LedBlinkingDSpeed_comp.srs|-top|work.LedBlinkingDSpeed|-prodtype|synplify_pro|-infer_seqShift|-primux|-dspmac|-pqdpadd|-fixsmult|-sdff_counter|-divnmod|-nram|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\bin64\\c_vhdl.exe":1449250526
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\location.map":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\snps_haps_pkg.vhd":1449250532
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std1164.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\std_textio.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\numeric.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\umr_capim.vhd":1449250532
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\arith.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd2008\\unsigned.vhd":1449250534
+#CUR:"C:\\tools\\Microsemi\\Libero_SoC_v11.7\\Synplify\\lib\\vhd\\hyperents.vhd":1449250532
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\ClkGen.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\ClkGenNoSwitch.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\Display.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\Reset_out.vhd":1477216350
+#CUR:"C:\\Future\\FPGA\\Microsemi\\CreativeBoard\\IGLOO2\\Lab2_VHDL\\hdl\\LedBlinkingDSpeed.vhd":1477216739
+0 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd" vhdl
+1 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd" vhdl
+2 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd" vhdl
+3 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd" vhdl
+4 "C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+1 -1
+2 -1
+3 -1
+4 3 1 0 2 
+
+# Dependency Lists (Users Of)
+0 4 
+1 4 
+2 4 
+3 4 
+4 -1
+
+# Design Unit to File Association
+arch work clkgen architecture_clkgen 0
+module work clkgen 0
+arch work clkgennoswitch architecture_clkgennoswitch 1
+module work clkgennoswitch 1
+arch work display architecture_display 2
+module work display 2
+arch work reset_out architecture_reset_out 3
+module work reset_out 3
+arch work ledblinkingdspeed architecture_ledblinkingdspeed 4
+module work ledblinkingdspeed 4
diff --git a/Lab2_VHDL/synthesis/synwork/layer0.srs b/Lab2_VHDL/synthesis/synwork/layer0.srs
new file mode 100644
index 0000000..3e0c4da
Binary files /dev/null and b/Lab2_VHDL/synthesis/synwork/layer0.srs differ
diff --git a/Lab2_VHDL/synthesis/synwork/layer0.tlg b/Lab2_VHDL/synthesis/synwork/layer0.tlg
new file mode 100644
index 0000000..0d581db
--- /dev/null
+++ b/Lab2_VHDL/synthesis/synwork/layer0.tlg
@@ -0,0 +1,26 @@
+@N: CD231 :"C:\tools\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":60:7:60:23|Synthesizing work.ledblinkingdspeed.architecture_ledblinkingdspeed 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":93:11:93:23|Signal scale_factor0 is undriven 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":94:11:94:23|Signal scale_factor1 is undriven 
+@W: CD638 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd":95:11:95:23|Signal scale_factor3 is undriven 
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":54:7:54:13|Synthesizing work.display.architecture_display 
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:18:82:20|Referenced variable sw2 is not in sensitivity list
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":82:24:82:26|Referenced variable sw1 is not in sensitivity list
+Post processing for work.display.architecture_display
+@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to red_led1 assign '0'; register removed by optimization
+@W: CL111 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd":84:8:84:9|All reachable assignments to green_led2 assign '0'; register removed by optimization
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":56:7:56:12|Synthesizing work.clkgen.architecture_clkgen 
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":76:4:76:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":79:21:79:25|Referenced variable scale is not in sensitivity list
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":83:33:83:34|Referenced variable sw is not in sensitivity list
+Post processing for work.clkgen.architecture_clkgen
+@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal cnt[31:0].
+@W: CL113 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd":80:4:80:5|Feedback mux created for signal tmp_clk.
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":56:7:56:20|Synthesizing work.clkgennoswitch.architecture_clkgennoswitch 
+@W: CG296 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":77:4:77:10|Incomplete sensitivity list - assuming completeness
+@W: CG290 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd":80:21:80:25|Referenced variable scale is not in sensitivity list
+Post processing for work.clkgennoswitch.architecture_clkgennoswitch
+@N: CD630 :"C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd":55:7:55:15|Synthesizing work.reset_out.architecture_reset_out 
+Post processing for work.reset_out.architecture_reset_out
+Post processing for work.ledblinkingdspeed.architecture_ledblinkingdspeed
diff --git a/Lab2_VHDL/tooldata/ClkGenNoSwitch_tools.xml b/Lab2_VHDL/tooldata/ClkGenNoSwitch_tools.xml
new file mode 100644
index 0000000..4ddd3a6
--- /dev/null
+++ b/Lab2_VHDL/tooldata/ClkGenNoSwitch_tools.xml
@@ -0,0 +1 @@
+falseERRORLOCK1250002falsefalsefalsefalsefalsefalsefalsefalsefalsefalseflashlockfalsedefaultfullfalsepasskeypasskeyfalsefalseflashlockfalsefalsefalsetruefalsetruetrue100falsefalseselected_featuresfalsefree_running_clkOFF400000ONfree_running_clkOFF400000ONfree_running_clkOFF400000ONOFFOFF400000ONONOFFOFFON400000ON2.5ONONfalsetruefalseVHDLPDC_PLACEPDC_PLACEfalseERRORLOCKverilogUserBlockBlocktruetruetrueCompany1.0RCOSC_1MHZSUSPENDMAXfalsefalseVIOLATIONSfalse5false0trueWORST_SLACK1falsetruefalsefalseselected_featuresfalse""falseVHDLtruetruetrueXMLfalsetruefalsetruetruefalsetruefalse
\ No newline at end of file
diff --git a/Lab2_VHDL/Lab2_VHDL/tooldata/Lab2_VHDL.log b/Lab2_VHDL/tooldata/Lab2_VHDL.log
similarity index 83%
rename from Lab2_VHDL/Lab2_VHDL/tooldata/Lab2_VHDL.log
rename to Lab2_VHDL/tooldata/Lab2_VHDL.log
index 26f02e1..64d0a5e 100644
--- a/Lab2_VHDL/Lab2_VHDL/tooldata/Lab2_VHDL.log
+++ b/Lab2_VHDL/tooldata/Lab2_VHDL.log
@@ -1,5 +1,5 @@
 Project Name: Lab2_VHDL
-Location: C:\Users\ashj\Documents\LEARNING\Microsemi\Lab2_VHDL\Lab2_VHDL
+Location: C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL
 Description: 
 Preferred HDL Type: VHDL
 
diff --git a/Lab2_VHDL/tooldata/Lab2_VHDL.msg b/Lab2_VHDL/tooldata/Lab2_VHDL.msg
new file mode 100644
index 0000000..e489449
--- /dev/null
+++ b/Lab2_VHDL/tooldata/Lab2_VHDL.msg
@@ -0,0 +1,60 @@
+HelpInfo,C:\tools\Microsemi\Libero_SoC_v11.7\\\Synplify\\lib\html,fpgahelp.qhc,errormessages.mp,C:\tools\Microsemi\Libero_SoC_v11.7\\\Synplify\\bin\mbin\assistant
+Implementation;Synthesis;RootName:LedBlinkingDSpeed
+Implementation;Synthesis|| CD638 ||@W:Signal scale_factor0 is undriven ||LedBlinkingDSpeed.srr(23);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/23||LedBlinkingDSpeed.vhd(93);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd'/linenumber/93
+Implementation;Synthesis|| CD638 ||@W:Signal scale_factor1 is undriven ||LedBlinkingDSpeed.srr(24);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/24||LedBlinkingDSpeed.vhd(94);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd'/linenumber/94
+Implementation;Synthesis|| CD638 ||@W:Signal scale_factor3 is undriven ||LedBlinkingDSpeed.srr(25);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/25||LedBlinkingDSpeed.vhd(95);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\LedBlinkingDSpeed.vhd'/linenumber/95
+Implementation;Synthesis|| CG296 ||@W:Incomplete sensitivity list - assuming completeness||LedBlinkingDSpeed.srr(27);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/27||Display.vhd(77);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd'/linenumber/77
+Implementation;Synthesis|| CG290 ||@W:Referenced variable sw2 is not in sensitivity list||LedBlinkingDSpeed.srr(28);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/28||Display.vhd(82);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd'/linenumber/82
+Implementation;Synthesis|| CG290 ||@W:Referenced variable sw1 is not in sensitivity list||LedBlinkingDSpeed.srr(29);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/29||Display.vhd(82);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd'/linenumber/82
+Implementation;Synthesis|| CL111 ||@W:All reachable assignments to red_led1 assign '0'; register removed by optimization||LedBlinkingDSpeed.srr(31);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/31||Display.vhd(84);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd'/linenumber/84
+Implementation;Synthesis|| CL111 ||@W:All reachable assignments to green_led2 assign '0'; register removed by optimization||LedBlinkingDSpeed.srr(32);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/32||Display.vhd(84);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Display.vhd'/linenumber/84
+Implementation;Synthesis|| CG296 ||@W:Incomplete sensitivity list - assuming completeness||LedBlinkingDSpeed.srr(34);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/34||ClkGen.vhd(76);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd'/linenumber/76
+Implementation;Synthesis|| CG290 ||@W:Referenced variable scale is not in sensitivity list||LedBlinkingDSpeed.srr(35);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/35||ClkGen.vhd(79);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd'/linenumber/79
+Implementation;Synthesis|| CG290 ||@W:Referenced variable sw is not in sensitivity list||LedBlinkingDSpeed.srr(36);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/36||ClkGen.vhd(83);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd'/linenumber/83
+Implementation;Synthesis|| CL113 ||@W:Feedback mux created for signal cnt[31:0].||LedBlinkingDSpeed.srr(38);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/38||ClkGen.vhd(80);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd'/linenumber/80
+Implementation;Synthesis|| CL113 ||@W:Feedback mux created for signal tmp_clk.||LedBlinkingDSpeed.srr(39);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/39||ClkGen.vhd(80);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGen.vhd'/linenumber/80
+Implementation;Synthesis|| CG296 ||@W:Incomplete sensitivity list - assuming completeness||LedBlinkingDSpeed.srr(41);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/41||ClkGenNoSwitch.vhd(77);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd'/linenumber/77
+Implementation;Synthesis|| CG290 ||@W:Referenced variable scale is not in sensitivity list||LedBlinkingDSpeed.srr(42);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/42||ClkGenNoSwitch.vhd(80);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\ClkGenNoSwitch.vhd'/linenumber/80
+Implementation;Synthesis|| CD630 ||@N: Synthesizing work.reset_out.architecture_reset_out ||LedBlinkingDSpeed.srr(44);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/44||Reset_out.vhd(55);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\hdl\Reset_out.vhd'/linenumber/55
+Implementation;Synthesis||null||@N: Running in 64-bit mode||LedBlinkingDSpeed.srr(55);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/55||null;null
+Implementation;Synthesis||null||@N: Running in 64-bit mode||LedBlinkingDSpeed.srr(73);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/73||null;null
+Implementation;Synthesis|| MF248 ||@N: Running in 64-bit mode.||LedBlinkingDSpeed.srr(93);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/93||null;null
+Implementation;Synthesis|| MF667 ||@N: Clock conversion disabled ||LedBlinkingDSpeed.srr(94);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/94||null;null
+Implementation;Synthesis|| BN225 ||@N: Writing default property annotation file C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.sap.||LedBlinkingDSpeed.srr(123);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/123||null;null
+Implementation;Synthesis|| MF248 ||@N: Running in 64-bit mode.||LedBlinkingDSpeed.srr(140);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/140||null;null
+Implementation;Synthesis|| MF667 ||@N: Clock conversion disabled ||LedBlinkingDSpeed.srr(141);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/141||null;null
+Implementation;Synthesis||null||@N: Found counter in view:work.ClkGenNoSwitch(architecture_clkgennoswitch) inst cnt[31:0]||LedBlinkingDSpeed.srr(165);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/165||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis||null||@N: Found counter in view:work.ClkGen(architecture_clkgen) inst cnt[31:0]||LedBlinkingDSpeed.srr(166);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/166||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis||null||@N: Found counter in view:work.ClkGenNoSwitch_0(architecture_clkgennoswitch) inst cnt[31:0]||LedBlinkingDSpeed.srr(167);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/167||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis||null||@N: Found counter in view:work.ClkGen_0(architecture_clkgen) inst cnt[31:0]||LedBlinkingDSpeed.srr(168);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/168||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(190);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/190||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(191);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/191||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(192);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/192||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(193);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/193||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(194);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/194||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW1.cnt[26] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(195);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/195||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW1.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(196);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/196||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW1.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(197);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/197||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW1.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(198);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/198||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW1.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(199);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/199||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW1.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(200);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/200||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(201);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/201||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(202);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/202||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(203);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/203||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Initial_blinking_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(204);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/204||clkgennoswitch.vhd(81);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgennoswitch.vhd'/linenumber/81
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW2.cnt[27] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(205);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/205||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW2.cnt[28] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(206);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/206||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW2.cnt[29] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(207);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/207||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW2.cnt[30] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(208);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/208||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| BN362 ||@N: Removing sequential instance Fast_clk_SW2.cnt[31] in hierarchy view:work.LedBlinkingDSpeed(architecture_ledblinkingdspeed) because there are no references to its outputs ||LedBlinkingDSpeed.srr(209);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/209||clkgen.vhd(80);liberoaction://cross_probe/hdl/file/'c:\future\fpga\microsemi\creativeboard\igloo2\lab2_vhdl\hdl\clkgen.vhd'/linenumber/80
+Implementation;Synthesis|| FP130 ||@N: Promoting Net reset on CLKINT  I_103 ||LedBlinkingDSpeed.srr(216);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/216||null;null
+Implementation;Synthesis|| FP130 ||@N: Promoting Net clk_c on CLKINT  I_104 ||LedBlinkingDSpeed.srr(217);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/217||null;null
+Implementation;Synthesis|| BW103 ||@N: Synopsys Constraint File time units using default value of 1ns ||LedBlinkingDSpeed.srr(255);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/255||null;null
+Implementation;Synthesis|| BW107 ||@N: Synopsys Constraint File capacitance units using default value of 1pF ||LedBlinkingDSpeed.srr(256);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/256||null;null
+Implementation;Synthesis|| MT320 ||@N: Timing report estimates place and route data. Please look at the place and route timing report for final timing.||LedBlinkingDSpeed.srr(278);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/278||null;null
+Implementation;Synthesis|| MT322 ||@N: Clock constraints cover only FF-to-FF paths associated with the clock.||LedBlinkingDSpeed.srr(280);liberoaction://cross_probe/hdl/file/'C:\Future\FPGA\Microsemi\CreativeBoard\IGLOO2\Lab2_VHDL\synthesis\LedBlinkingDSpeed.srr'/linenumber/280||null;null
+Implementation;Synthesis||(null)||Please refer to the log file for details about 15 Warning(s)||LedBlinkingDSpeed.srr;liberoaction://open_report/file/LedBlinkingDSpeed.srr||(null);(null)
+Implementation;Place and Route;RootName:LedBlinkingDSpeed
+Implementation;Place and Route||(null)||Please refer to the log file for details about 3 Info(s)||LedBlinkingDSpeed_layout_log.log;liberoaction://open_report/file/LedBlinkingDSpeed_layout_log.log||(null);(null)
+Implementation;Generate Bitstream;RootName:LedBlinkingDSpeed
+Implementation;Generate Bitstream||(null)||Please refer to the log file for details||LedBlinkingDSpeed_generateBitstream.log;liberoaction://open_report/file/LedBlinkingDSpeed_generateBitstream.log||(null);(null)
diff --git a/Lab2_VHDL/tooldata/LedBlinkingDSpeed_tools.xml b/Lab2_VHDL/tooldata/LedBlinkingDSpeed_tools.xml
new file mode 100644
index 0000000..45e71dd
--- /dev/null
+++ b/Lab2_VHDL/tooldata/LedBlinkingDSpeed_tools.xml
@@ -0,0 +1 @@
+falseERRORLOCK1250002falsefalsehdl\ClkGen.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsehdl\ClkGenNoSwitch.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsehdl\Display.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsehdl\LedBlinkingDSpeed.vhdHDLHDL_FILESETtruetruetrue1477216739falsefalsefalsehdl\Reset_out.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalseconstraint\LedBlinkingDSpeed_sdc.sdcSDC_ROOTDESIGNER_FILESETtruetruetrue1477216351falsefalsefalsesynthesis\LedBlinkingDSpeed_sdc.sdcSDC_ROOTOTHER_SYNTHESIS_FILESETtruefalsetrue1477216773falsefalsefalsesynthesis\LedBlinkingDSpeed.ednEDNHDL_FILESETtruefalsetrue1477216773falsefalsefalsesynthesis\synplify.logLOGOTHER_FILESETtruefalsetrue0falsefalsefalsesynthesis\LedBlinkingDSpeed.srrLOGOTHER_FILESETtruefalsetrue0falsefalsefalsesynthesis\LedBlinkingDSpeed.areasrrLOGOTHER_FILESETtruefalsetrue0falsefalsefalsesynthesis\run_options.txtLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_compile_netlist_resources.xmlLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_compile_netlist_hier_resources.csvLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_compile_netlist_combinational_loops.xmlLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_rwnetlist.logLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_compile_netlist.logLOGOTHER_FILESETtruefalsetrue0falsefalsefalsefalsefalsefalsefalsefalsefalsefalsefalseflashlockfalsedefaultfullfalsepasskeypasskeyfalsefalseflashlockfalsefalsefalsetruefalsehdl\ClkGen.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsehdl\ClkGenNoSwitch.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsehdl\Display.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsehdl\LedBlinkingDSpeed.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsehdl\Reset_out.vhdHDLHDL_FILESETtruetruetrue1477216350falsefalsefalsestimulus\LedBlinkingDSpeed_tb.vhdTB_HDLSTIMULUS_FILESETtruetruetrue1477216428falsefalsefalsetruetrue100falsefalseselected_featuresfalsefree_running_clkOFF400000ONfree_running_clkOFF400000ONfree_running_clkOFF400000ONOFFOFF400000ONONOFFOFFON400000ON2.5ONONfalsetruefalseVHDLsynthesis\LedBlinkingDSpeed.ednHDLHDL_FILESETtruetruetrue1477216773falsefalsefalsesynthesis\LedBlinkingDSpeed.vhdHDLANY_SIMULATION_FILESETtruetruefalse1477216578falsefalsefalsestimulus\LedBlinkingDSpeed_tb.vhdTB_HDLSTIMULUS_FILESETtruetruetrue1477216428falsefalsefalsePDC_PLACEPDC_PLACEconstraint\LedBlinkingDSpeed_sdc.sdcSDC_PRJDESIGNER_FILESETtruefalsetrue1477216351falsefalsefalsefalseERRORLOCKverilogUserBlockBlocktruetruetrueCompany1.0RCOSC_1MHZSUSPENDMAXfalsefalseVIOLATIONSfalse5false0trueWORST_SLACK1falsetrueconstraint\io\LedBlinkingDSpeed.io.pdcPDCDESIGNER_FILESETtruetruetrue1477216351falsefalsefalsesynthesis\LedBlinkingDSpeed_sdc.sdcSDC_SYNOTHER_SYNTHESIS_FILESETtruefalsetrue1477216773falsefalsefalseconstraint\LedBlinkingDSpeed_sdc.sdcSDC_PRJDESIGNER_FILESETtruetruetrue1477216351falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_glb_net_report.xmlLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_mindelay_repair_report.rptLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_iteration_summary.rptLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_layout_combinational_loops.xmlLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_pinrpt_name.rptLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_pinrpt_number.rptLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_bankrpt.rptLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_ioff.xmlLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_layout_log.logLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_place_and_route_constraint_coverage.xmlLOGOTHER_FILESETtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed.mapMAPtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed.dcaDCAtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_inst.dbDBtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_pkg_pin.dbDBtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_probe.dbDBtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_sii_block.dbDBtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_init_config.txtRPTtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_init_config_lock_bits.txtRPTtruefalsetrue0falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_init_config.xmlLOGOTHER_FILESETtruefalsetrue0falsefalsefalsefalsefalseselected_featuresfalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed.ipdFPROPROG_FILESETtruefalsetrue1477216926falsefalsefalsedesigner\LedBlinkingDSpeed\LedBlinkingDSpeed_fp\LedBlinkingDSpeed_generateBitstream.logLOGOTHER_FILESETtruefalsetrue0falsefalsefalse""designer\LedBlinkingDSpeed\LedBlinkingDSpeed_fp\LedBlinkingDSpeed_PROGRAM.logLOGOTHER_FILESETtruefalsetrue0falsefalsefalsefalseVHDLtruetruetrueXMLfalsetruefalsetruetruefalsetruefalseconstraint\LedBlinkingDSpeed_sdc.sdcSDC_PRJDESIGNER_FILESETtruetruetrue1477216351falsefalsefalse
\ No newline at end of file
diff --git a/Lab2_VHDL/tooldata/libero.12888 b/Lab2_VHDL/tooldata/libero.12888
new file mode 100644
index 0000000..53e5b18
--- /dev/null
+++ b/Lab2_VHDL/tooldata/libero.12888
@@ -0,0 +1,3 @@
+libero
+1
+libero,12888:57900:0