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PipelineCPU.eda.rpt
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PipelineCPU.eda.rpt
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EDA Netlist Writer report for PipelineCPU
Tue Jun 17 23:31:07 2014
Quartus II 32-bit Version 12.0 Build 178 05/31/2012 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Jun 17 23:31:07 2014 ;
; Revision Name ; PipelineCPU ;
; Top-level Entity Name ; PipelineCPU ;
; Family ; Cyclone II ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+-----------------------------------------------------------------------------+
; Simulation Generated Files ;
+-----------------------------------------------------------------------------+
; Generated Files ;
+-----------------------------------------------------------------------------+
; D:/Documents/GitRepository/lab06/simulation/modelsim/PipelineCPU.vo ;
; D:/Documents/GitRepository/lab06/simulation/modelsim/PipelineCPU_fast.vo ;
; D:/Documents/GitRepository/lab06/simulation/modelsim/PipelineCPU_v.sdo ;
; D:/Documents/GitRepository/lab06/simulation/modelsim/PipelineCPU_v_fast.sdo ;
+-----------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 12.0 Build 178 05/31/2012 SJ Full Version
Info: Processing started: Tue Jun 17 23:30:40 2014
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off PipelineCPU -c PipelineCPU
Info (204026): Generated files "PipelineCPU.vo", "PipelineCPU_fast.vo", "PipelineCPU_v.sdo" and "PipelineCPU_v_fast.sdo" in directory "D:/Documents/GitRepository/lab06/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 334 megabytes
Info: Processing ended: Tue Jun 17 23:31:08 2014
Info: Elapsed time: 00:00:28
Info: Total CPU time (on all processors): 00:00:13