diff --git a/.gitignore b/.gitignore index fd3052069..5884017ca 100644 --- a/.gitignore +++ b/.gitignore @@ -15,6 +15,8 @@ Library *.o.* logs* log* +Log* *.map *.srec *.verilog +*.log diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index cd655167b..da813113c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,7 @@ variables: NUCLEI_SDK: git@gito:software/library/nuclei-sdk.git - SDK_BRANCH: dev_xlspike_next - SOC: xlspike + SDK_BRANCH: develop + SOC: demosoc RUNTARGET: qemu IMAGE: rego.corp.nucleisys.com/software/sdkbuild IMAGE_TAG: latest @@ -19,8 +19,12 @@ stages: build_doc: stage: build + interruptible: true retry: 1 only: + refs: + - master + - develop changes: - NMSIS/doc/source/**/**/**/* - .gitlab-ci.yml @@ -36,6 +40,7 @@ build_doc: before_script: - apt update - apt install -y doxygen python3 make latexmk texlive-base texlive-latex-extra python3-pip + - pip3 config set global.index-url https://pypi.tuna.tsinghua.edu.cn/simple - pip3 install -r NMSIS/doc/requirements.txt script: - cd NMSIS/doc @@ -48,7 +53,12 @@ build_doc: build_library: stage: build + interruptible: true retry: 1 + only: + refs: + - master + - develop artifacts: when: always name: "nmsis_library-${CI_COMMIT_SHA::8}" @@ -68,7 +78,12 @@ build_library: build_align_library: stage: build + interruptible: true retry: 1 + only: + refs: + - master + - develop artifacts: when: always name: "nmsis_align_library-${CI_COMMIT_SHA::8}" @@ -86,6 +101,12 @@ build_align_library: .test_job_template: &test_job_template_default stage: test + timeout: 4h + interruptible: true + only: + refs: + - master + - develop before_script: # prepare for docker ssh environment ## https://docs.gitlab.com/ee/ci/ssh_keys/#ssh-keys-when-using-the-docker-executor @@ -99,7 +120,10 @@ build_align_library: # https://serverfault.com/questions/469052/ssh-failing-from-script-working-on-command-line-git - ssh-keyscan gito > ~/.ssh/known_hosts - apt install -y python3 python3-pip + - pip3 config set global.index-url https://pypi.tuna.tsinghua.edu.cn/simple + - python3 -m pip install --upgrade pip - pip3 install prettytable==2.1.0 psutil==5.8.0 pyserial==3.5 markdown + - export SDK_COPY_OBJECTS="elf,map" dependencies: - build_library @@ -114,14 +138,17 @@ test_nn_library: script: - git clone -b $SDK_BRANCH $NUCLEI_SDK NMSIS/nuclei_sdk - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) + - pip3 install -r $NUCLEI_SDK_ROOT/tools/scripts/requirements.txt - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs + # change ilm/dlm size from 64K to 1M for demosoc + - sed -i "s/64K/1M/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld - mkdir $NMSIS_LOGS - source NMSIS/env.sh - export SILENT=1 - cd NMSIS - make gen_nnref_lib - - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_nn.json --logdir $NMSIS_LOGS/nmsis_nn --parallel=-j --run_target $RUNTARGET --run + - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_nn.json --logdir $NMSIS_LOGS/nmsis_nn --parallel=-j --make_options "SIMU=$RUNTARGET" --run_target $RUNTARGET --run test_dsp_library: <<: *test_job_template_default @@ -134,16 +161,24 @@ test_dsp_library: script: - git clone -b $SDK_BRANCH $NUCLEI_SDK NMSIS/nuclei_sdk - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) + - pip3 install -r $NUCLEI_SDK_ROOT/tools/scripts/requirements.txt - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs + # change ilm/dlm size from 64K to 1M for demosoc + - sed -i "s/64K/1M/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld - mkdir $NMSIS_LOGS - source NMSIS/env.sh - export SILENT=1 - cd NMSIS - - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_dsp.json --logdir $NMSIS_LOGS/nmsis_dsp --parallel=-j --run_target $RUNTARGET --run + - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_dsp.json --logdir $NMSIS_LOGS/nmsis_dsp --parallel=-j --make_options "SIMU=$RUNTARGET" --run_target $RUNTARGET --run release_benchmark: stage: release + interruptible: true + only: + refs: + - master + - develop artifacts: name: "nmsis_test_log-${CI_COMMIT_SHA::8}" paths: @@ -155,6 +190,30 @@ release_benchmark: script: - ls -lh NMSIS/Logs +release_nmsis: + stage: release + interruptible: true + only: + refs: + - master + - develop + artifacts: + name: "nmsis_release-${CI_COMMIT_SHA::8}" + paths: + - NMSIS/Core + - NMSIS/DSP/Include + - NMSIS/DSP/PrivateInclude + - NMSIS/NN/Include + - NMSIS/Library + - NMSIS/npk.yml + - NMSIS/build.mk + expire_in: 2 day + dependencies: + - build_library + script: + - ls -lh NMSIS/Library + - cat NMSIS/npk.yml + deploy_website: stage: release only: diff --git a/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld b/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld index 25b874357..558f8156e 100644 --- a/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld +++ b/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld @@ -124,6 +124,7 @@ SECTIONS .ialign : { + . = ALIGN(4); /* Create a section label as _ilm which located at flash */ PROVIDE( _ilm = . ); } >flash AT>flash @@ -170,13 +171,6 @@ SECTIONS KEEP (*(SORT_NONE(.fini))) } >flash AT>flash - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - PROVIDE( _eilm = . ); - .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -233,6 +227,11 @@ SECTIONS KEEP (*(.dtors)) } >flash AT>flash + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE (_eilm = .); + .lalign : { . = ALIGN(4); @@ -267,8 +266,6 @@ SECTIONS PROVIDE( _edata = . ); PROVIDE( edata = . ); - . = ALIGN(8); - PROVIDE( _fbss = . ); PROVIDE( __bss_start = . ); @@ -279,7 +276,12 @@ SECTIONS PROVIDE( __tls_end = . ); } >ram AT>ram - .bss (NOLOAD) : + .tbss_space (NOLOAD) : ALIGN(8) + { + . = . + SIZEOF(.tbss); + } >ram AT>ram + + .bss (NOLOAD) : ALIGN(8) { *(.sbss*) *(.gnu.linkonce.sb.*) @@ -289,7 +291,6 @@ SECTIONS . = ALIGN(4); } >ram AT>ram - . = ALIGN(16); PROVIDE( _end = . ); PROVIDE( end = . ); @@ -298,7 +299,7 @@ SECTIONS * 2. __heap_start and __heap_end symbol need to be defined * 3. reserved at least __HEAP_SIZE space for heap */ - .heap (NOLOAD) : + .heap (NOLOAD) : ALIGN(16) { . = ALIGN(16); PROVIDE( __heap_start = . ); diff --git a/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S b/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S index c17c7da1c..3c150851e 100644 --- a/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S +++ b/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S @@ -41,19 +41,7 @@ .weak eclic_msip_handler .weak eclic_mtip_handler - .weak eclic_irq19_handler - .weak eclic_irq20_handler - .weak eclic_irq21_handler - .weak eclic_irq22_handler - .weak eclic_irq23_handler - .weak eclic_irq24_handler - .weak eclic_irq25_handler - .weak eclic_irq26_handler - .weak eclic_irq27_handler - .weak eclic_irq28_handler - .weak eclic_irq29_handler - .weak eclic_irq30_handler - .weak eclic_irq31_handler + /* TODO: add vendor interrupt handlers */ .globl vector_base .type vector_base, @object @@ -83,22 +71,23 @@ vector_base: DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 17: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 18: Reserved */ - DECLARE_INT_HANDLER eclic_irq19_handler /* 19: Interrupt 19 */ - - DECLARE_INT_HANDLER eclic_irq20_handler /* 20: Interrupt 20 */ - DECLARE_INT_HANDLER eclic_irq21_handler /* 21: Interrupt 21 */ - DECLARE_INT_HANDLER eclic_irq22_handler /* 22: Interrupt 22 */ - DECLARE_INT_HANDLER eclic_irq23_handler /* 23: Interrupt 23 */ - - DECLARE_INT_HANDLER eclic_irq24_handler /* 24: Interrupt 24 */ - DECLARE_INT_HANDLER eclic_irq25_handler /* 25: Interrupt 25 */ - DECLARE_INT_HANDLER eclic_irq26_handler /* 26: Interrupt 26 */ - DECLARE_INT_HANDLER eclic_irq27_handler /* 27: Interrupt 27 */ - - DECLARE_INT_HANDLER eclic_irq28_handler /* 28: Interrupt 28 */ - DECLARE_INT_HANDLER eclic_irq29_handler /* 29: Interrupt 29 */ - DECLARE_INT_HANDLER eclic_irq30_handler /* 30: Interrupt 30 */ - DECLARE_INT_HANDLER eclic_irq31_handler /* 31: Interrupt 31 */ + /* TODO: Adjust Vendor Defined External Interrupts */ + DECLARE_INT_HANDLER default_intexc_handler /* 19: Interrupt 19 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 20: Interrupt 20 */ + DECLARE_INT_HANDLER default_intexc_handler /* 21: Interrupt 21 */ + DECLARE_INT_HANDLER default_intexc_handler /* 22: Interrupt 22 */ + DECLARE_INT_HANDLER default_intexc_handler /* 23: Interrupt 23 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 24: Interrupt 24 */ + DECLARE_INT_HANDLER default_intexc_handler /* 25: Interrupt 25 */ + DECLARE_INT_HANDLER default_intexc_handler /* 26: Interrupt 26 */ + DECLARE_INT_HANDLER default_intexc_handler /* 27: Interrupt 27 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 28: Interrupt 28 */ + DECLARE_INT_HANDLER default_intexc_handler /* 29: Interrupt 29 */ + DECLARE_INT_HANDLER default_intexc_handler /* 30: Interrupt 30 */ + DECLARE_INT_HANDLER default_intexc_handler /* 31: Interrupt 31 */ /*** Startup Code Section ***/ diff --git a/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld b/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld index 5d4188f6b..7ba1f0f2b 100644 --- a/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld +++ b/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld @@ -124,6 +124,7 @@ SECTIONS .ialign : { + . = ALIGN(4); /* Create a section label as _ilm which located at flash */ PROVIDE( _ilm = . ); } >flash AT>flash @@ -170,13 +171,6 @@ SECTIONS KEEP (*(SORT_NONE(.fini))) } >flash AT>flash - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - PROVIDE( _eilm = . ); - .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -233,6 +227,11 @@ SECTIONS KEEP (*(.dtors)) } >flash AT>flash + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE (_eilm = .); + .lalign : { . = ALIGN(4); @@ -267,8 +266,6 @@ SECTIONS PROVIDE( _edata = . ); PROVIDE( edata = . ); - . = ALIGN(8); - PROVIDE( _fbss = . ); PROVIDE( __bss_start = . ); @@ -279,7 +276,12 @@ SECTIONS PROVIDE( __tls_end = . ); } >ram AT>ram - .bss (NOLOAD) : + .tbss_space (NOLOAD) : ALIGN(8) + { + . = . + SIZEOF(.tbss); + } >ram AT>ram + + .bss (NOLOAD) : ALIGN(8) { *(.sbss*) *(.gnu.linkonce.sb.*) @@ -289,7 +291,6 @@ SECTIONS . = ALIGN(4); } >ram AT>ram - . = ALIGN(16); PROVIDE( _end = . ); PROVIDE( end = . ); @@ -298,7 +299,7 @@ SECTIONS * 2. __heap_start and __heap_end symbol need to be defined * 3. reserved at least __HEAP_SIZE space for heap */ - .heap (NOLOAD) : + .heap (NOLOAD) : ALIGN(16) { . = ALIGN(16); PROVIDE( __heap_start = . ); diff --git a/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S b/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S index bdf4174c1..b85c75e33 100644 --- a/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S +++ b/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S @@ -41,19 +41,7 @@ .weak eclic_msip_handler .weak eclic_mtip_handler - .weak eclic_irq19_handler - .weak eclic_irq20_handler - .weak eclic_irq21_handler - .weak eclic_irq22_handler - .weak eclic_irq23_handler - .weak eclic_irq24_handler - .weak eclic_irq25_handler - .weak eclic_irq26_handler - .weak eclic_irq27_handler - .weak eclic_irq28_handler - .weak eclic_irq29_handler - .weak eclic_irq30_handler - .weak eclic_irq31_handler + /* TODO: add vendor interrupt handlers */ .globl vector_base .type vector_base, @object @@ -83,22 +71,23 @@ vector_base: DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 17: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 18: Reserved */ - DECLARE_INT_HANDLER eclic_irq19_handler /* 19: Interrupt 19 */ - - DECLARE_INT_HANDLER eclic_irq20_handler /* 20: Interrupt 20 */ - DECLARE_INT_HANDLER eclic_irq21_handler /* 21: Interrupt 21 */ - DECLARE_INT_HANDLER eclic_irq22_handler /* 22: Interrupt 22 */ - DECLARE_INT_HANDLER eclic_irq23_handler /* 23: Interrupt 23 */ - - DECLARE_INT_HANDLER eclic_irq24_handler /* 24: Interrupt 24 */ - DECLARE_INT_HANDLER eclic_irq25_handler /* 25: Interrupt 25 */ - DECLARE_INT_HANDLER eclic_irq26_handler /* 26: Interrupt 26 */ - DECLARE_INT_HANDLER eclic_irq27_handler /* 27: Interrupt 27 */ - - DECLARE_INT_HANDLER eclic_irq28_handler /* 28: Interrupt 28 */ - DECLARE_INT_HANDLER eclic_irq29_handler /* 29: Interrupt 29 */ - DECLARE_INT_HANDLER eclic_irq30_handler /* 30: Interrupt 30 */ - DECLARE_INT_HANDLER eclic_irq31_handler /* 31: Interrupt 31 */ + /* TODO: Adjust Vendor Defined External Interrupts */ + DECLARE_INT_HANDLER default_intexc_handler /* 19: Interrupt 19 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 20: Interrupt 20 */ + DECLARE_INT_HANDLER default_intexc_handler /* 21: Interrupt 21 */ + DECLARE_INT_HANDLER default_intexc_handler /* 22: Interrupt 22 */ + DECLARE_INT_HANDLER default_intexc_handler /* 23: Interrupt 23 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 24: Interrupt 24 */ + DECLARE_INT_HANDLER default_intexc_handler /* 25: Interrupt 25 */ + DECLARE_INT_HANDLER default_intexc_handler /* 26: Interrupt 26 */ + DECLARE_INT_HANDLER default_intexc_handler /* 27: Interrupt 27 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 28: Interrupt 28 */ + DECLARE_INT_HANDLER default_intexc_handler /* 29: Interrupt 29 */ + DECLARE_INT_HANDLER default_intexc_handler /* 30: Interrupt 30 */ + DECLARE_INT_HANDLER default_intexc_handler /* 31: Interrupt 31 */ /*** Startup Code Section ***/ diff --git a/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld b/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld index 90f50ab16..81a00f1c1 100644 --- a/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld +++ b/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld @@ -124,6 +124,7 @@ SECTIONS .ialign : { + . = ALIGN(4); /* Create a section label as _ilm which located at flash */ PROVIDE( _ilm = . ); } >flash AT>flash @@ -170,13 +171,6 @@ SECTIONS KEEP (*(SORT_NONE(.fini))) } >flash AT>flash - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - PROVIDE( _eilm = . ); - .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -233,6 +227,11 @@ SECTIONS KEEP (*(.dtors)) } >flash AT>flash + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE (_eilm = .); + .lalign : { . = ALIGN(4); @@ -267,8 +266,6 @@ SECTIONS PROVIDE( _edata = . ); PROVIDE( edata = . ); - . = ALIGN(8); - PROVIDE( _fbss = . ); PROVIDE( __bss_start = . ); @@ -279,7 +276,12 @@ SECTIONS PROVIDE( __tls_end = . ); } >ram AT>ram - .bss (NOLOAD) : + .tbss_space (NOLOAD) : ALIGN(8) + { + . = . + SIZEOF(.tbss); + } >ram AT>ram + + .bss (NOLOAD) : ALIGN(8) { *(.sbss*) *(.gnu.linkonce.sb.*) @@ -289,7 +291,6 @@ SECTIONS . = ALIGN(4); } >ram AT>ram - . = ALIGN(16); PROVIDE( _end = . ); PROVIDE( end = . ); @@ -298,7 +299,7 @@ SECTIONS * 2. __heap_start and __heap_end symbol need to be defined * 3. reserved at least __HEAP_SIZE space for heap */ - .heap (NOLOAD) : + .heap (NOLOAD) : ALIGN(16) { . = ALIGN(16); PROVIDE( __heap_start = . ); diff --git a/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S b/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S index 8bdb493bc..0e6d5be65 100644 --- a/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S +++ b/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S @@ -41,39 +41,7 @@ .weak eclic_msip_handler .weak eclic_mtip_handler - /* TODO: Adjust vendor interrupt handlers */ - .weak eclic_irq19_handler - .weak eclic_irq20_handler - .weak eclic_irq21_handler - .weak eclic_irq22_handler - .weak eclic_irq23_handler - .weak eclic_irq24_handler - .weak eclic_irq25_handler - .weak eclic_irq26_handler - .weak eclic_irq27_handler - .weak eclic_irq28_handler - .weak eclic_irq29_handler - .weak eclic_irq30_handler - .weak eclic_irq31_handler - .weak eclic_irq32_handler - .weak eclic_irq33_handler - .weak eclic_irq34_handler - .weak eclic_irq35_handler - .weak eclic_irq36_handler - .weak eclic_irq37_handler - .weak eclic_irq38_handler - .weak eclic_irq39_handler - .weak eclic_irq40_handler - .weak eclic_irq41_handler - .weak eclic_irq42_handler - .weak eclic_irq43_handler - .weak eclic_irq44_handler - .weak eclic_irq45_handler - .weak eclic_irq46_handler - .weak eclic_irq47_handler - .weak eclic_irq48_handler - .weak eclic_irq49_handler - .weak eclic_irq50_handler + /* TODO: add vendor interrupt handlers */ .globl vector_base .type vector_base, @object @@ -104,46 +72,46 @@ vector_base: DECLARE_INT_HANDLER default_intexc_handler /* 17: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 18: Reserved */ /* TODO: Adjust Vendor Defined External Interrupts */ - DECLARE_INT_HANDLER eclic_irq19_handler /* 19: Interrupt 19 */ - - DECLARE_INT_HANDLER eclic_irq20_handler /* 20: Interrupt 20 */ - DECLARE_INT_HANDLER eclic_irq21_handler /* 21: Interrupt 21 */ - DECLARE_INT_HANDLER eclic_irq22_handler /* 22: Interrupt 22 */ - DECLARE_INT_HANDLER eclic_irq23_handler /* 23: Interrupt 23 */ - - DECLARE_INT_HANDLER eclic_irq24_handler /* 24: Interrupt 24 */ - DECLARE_INT_HANDLER eclic_irq25_handler /* 25: Interrupt 25 */ - DECLARE_INT_HANDLER eclic_irq26_handler /* 26: Interrupt 26 */ - DECLARE_INT_HANDLER eclic_irq27_handler /* 27: Interrupt 27 */ - - DECLARE_INT_HANDLER eclic_irq28_handler /* 28: Interrupt 28 */ - DECLARE_INT_HANDLER eclic_irq29_handler /* 29: Interrupt 29 */ - DECLARE_INT_HANDLER eclic_irq30_handler /* 30: Interrupt 30 */ - DECLARE_INT_HANDLER eclic_irq31_handler /* 31: Interrupt 31 */ - - DECLARE_INT_HANDLER eclic_irq32_handler /* 32: Interrupt 32 */ - DECLARE_INT_HANDLER eclic_irq33_handler /* 33: Interrupt 33 */ - DECLARE_INT_HANDLER eclic_irq34_handler /* 34: Interrupt 34 */ - DECLARE_INT_HANDLER eclic_irq35_handler /* 35: Interrupt 35 */ - - DECLARE_INT_HANDLER eclic_irq36_handler /* 36: Interrupt 36 */ - DECLARE_INT_HANDLER eclic_irq37_handler /* 37: Interrupt 37 */ - DECLARE_INT_HANDLER eclic_irq38_handler /* 38: Interrupt 38 */ - DECLARE_INT_HANDLER eclic_irq39_handler /* 39: Interrupt 39 */ - - DECLARE_INT_HANDLER eclic_irq40_handler /* 40: Interrupt 40 */ - DECLARE_INT_HANDLER eclic_irq41_handler /* 41: Interrupt 41 */ - DECLARE_INT_HANDLER eclic_irq42_handler /* 42: Interrupt 42 */ - DECLARE_INT_HANDLER eclic_irq43_handler /* 43: Interrupt 43 */ - - DECLARE_INT_HANDLER eclic_irq44_handler /* 44: Interrupt 44 */ - DECLARE_INT_HANDLER eclic_irq45_handler /* 45: Interrupt 45 */ - DECLARE_INT_HANDLER eclic_irq46_handler /* 46: Interrupt 46 */ - DECLARE_INT_HANDLER eclic_irq47_handler /* 47: Interrupt 47 */ - - DECLARE_INT_HANDLER eclic_irq48_handler /* 48: Interrupt 48 */ - DECLARE_INT_HANDLER eclic_irq49_handler /* 49: Interrupt 49 */ - DECLARE_INT_HANDLER eclic_irq50_handler /* 50: Interrupt 50 */ + DECLARE_INT_HANDLER default_intexc_handler /* 19: Interrupt 19 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 20: Interrupt 20 */ + DECLARE_INT_HANDLER default_intexc_handler /* 21: Interrupt 21 */ + DECLARE_INT_HANDLER default_intexc_handler /* 22: Interrupt 22 */ + DECLARE_INT_HANDLER default_intexc_handler /* 23: Interrupt 23 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 24: Interrupt 24 */ + DECLARE_INT_HANDLER default_intexc_handler /* 25: Interrupt 25 */ + DECLARE_INT_HANDLER default_intexc_handler /* 26: Interrupt 26 */ + DECLARE_INT_HANDLER default_intexc_handler /* 27: Interrupt 27 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 28: Interrupt 28 */ + DECLARE_INT_HANDLER default_intexc_handler /* 29: Interrupt 29 */ + DECLARE_INT_HANDLER default_intexc_handler /* 30: Interrupt 30 */ + DECLARE_INT_HANDLER default_intexc_handler /* 31: Interrupt 31 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 32: Interrupt 32 */ + DECLARE_INT_HANDLER default_intexc_handler /* 33: Interrupt 33 */ + DECLARE_INT_HANDLER default_intexc_handler /* 34: Interrupt 34 */ + DECLARE_INT_HANDLER default_intexc_handler /* 35: Interrupt 35 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 36: Interrupt 36 */ + DECLARE_INT_HANDLER default_intexc_handler /* 37: Interrupt 37 */ + DECLARE_INT_HANDLER default_intexc_handler /* 38: Interrupt 38 */ + DECLARE_INT_HANDLER default_intexc_handler /* 39: Interrupt 39 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 40: Interrupt 40 */ + DECLARE_INT_HANDLER default_intexc_handler /* 41: Interrupt 41 */ + DECLARE_INT_HANDLER default_intexc_handler /* 42: Interrupt 42 */ + DECLARE_INT_HANDLER default_intexc_handler /* 43: Interrupt 43 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 44: Interrupt 44 */ + DECLARE_INT_HANDLER default_intexc_handler /* 45: Interrupt 45 */ + DECLARE_INT_HANDLER default_intexc_handler /* 46: Interrupt 46 */ + DECLARE_INT_HANDLER default_intexc_handler /* 47: Interrupt 47 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 48: Interrupt 48 */ + DECLARE_INT_HANDLER default_intexc_handler /* 49: Interrupt 49 */ + DECLARE_INT_HANDLER default_intexc_handler /* 50: Interrupt 50 */ /* Please adjust the above part of interrupt definition code * according to your device interrupt number and its configuration */ diff --git a/NMSIS/Core/Include/core_compatiable.h b/NMSIS/Core/Include/core_compatiable.h index 316a309fa..ee11d696c 100644 --- a/NMSIS/Core/Include/core_compatiable.h +++ b/NMSIS/Core/Include/core_compatiable.h @@ -25,6 +25,8 @@ extern "C" { #endif +#include "core_feature_base.h" + /* ===== ARM Compatiable Functions ===== */ /** * \defgroup NMSIS_Core_ARMCompatiable_Functions ARM Compatiable Functions diff --git a/NMSIS/Core/Include/core_feature_base.h b/NMSIS/Core/Include/core_feature_base.h index 8382f846a..8656848b4 100644 --- a/NMSIS/Core/Include/core_feature_base.h +++ b/NMSIS/Core/Include/core_feature_base.h @@ -23,12 +23,13 @@ * @brief Base core feature API for Nuclei N/NX Core */ #include -#include "riscv_encoding.h" #ifdef __cplusplus extern "C" { #endif +#include "nmsis_compiler.h" + /** * \defgroup NMSIS_Core_Registers Register Define and Type Definitions * \brief Type definitions and defines for core registers. diff --git a/NMSIS/Core/Include/core_feature_bitmanip.h b/NMSIS/Core/Include/core_feature_bitmanip.h index 1c2f66db1..552509832 100644 --- a/NMSIS/Core/Include/core_feature_bitmanip.h +++ b/NMSIS/Core/Include/core_feature_bitmanip.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__BITMANIP_PRESENT) && (__BITMANIP_PRESENT == 1) /* ########################### CPU Bitmanipulation Intrinsic Functions ########################### */ diff --git a/NMSIS/Core/Include/core_feature_cache.h b/NMSIS/Core/Include/core_feature_cache.h index 6e9a66b99..987aed360 100644 --- a/NMSIS/Core/Include/core_feature_cache.h +++ b/NMSIS/Core/Include/core_feature_cache.h @@ -34,8 +34,10 @@ extern "C" { #endif -#if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)) \ - || (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)) +#include "core_feature_base.h" + + +#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) /* ########################## Cache functions #################################### */ /** @@ -191,6 +193,7 @@ __STATIC_FORCEINLINE void DisableICache(void) __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); } +#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) /** * \brief Get I-Cache Information * \details @@ -218,33 +221,6 @@ __STATIC_FORCEINLINE int32_t GetICacheInfo(CacheInfo_Type *info) return 0; } -/** - * \brief Get D-Cache Information - * \details - * This function get D-Cache Information - * \remarks - * - This function can be called in M-Mode only. - * - You can use this function in combination with cache lines operations - * \sa - * - \ref GetICacheInfo - */ -__STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info) -{ - if (info == NULL) { - return -1; - } - CSR_MDCFGINFO_Type csr_ccfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO); - info->setperway = (1 << csr_ccfg.b.set) << 3; - info->ways = (1 + csr_ccfg.b.way); - if (csr_ccfg.b.lsize == 0) { - info->linesize = 0; - } else { - info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3; - } - info->size = info->setperway * info->ways * info->linesize; - return 0; -} - /** * \brief Invalidate one I-Cache line specified by address in M-Mode * \details @@ -640,7 +616,7 @@ __STATIC_FORCEINLINE void UInvalICache(void) { __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL_ALL); } - +#endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */ /** @} */ /* End of Doxygen Group NMSIS_Core_ICache */ #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */ @@ -681,6 +657,34 @@ __STATIC_FORCEINLINE void DisableDCache(void) __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); } +#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) +/** + * \brief Get D-Cache Information + * \details + * This function get D-Cache Information + * \remarks + * - This function can be called in M-Mode only. + * - You can use this function in combination with cache lines operations + * \sa + * - \ref GetICacheInfo + */ +__STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info) +{ + if (info == NULL) { + return -1; + } + CSR_MDCFGINFO_Type csr_ccfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO); + info->setperway = (1 << csr_ccfg.b.set) << 3; + info->ways = (1 + csr_ccfg.b.way); + if (csr_ccfg.b.lsize == 0) { + info->linesize = 0; + } else { + info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3; + } + info->size = info->setperway * info->ways * info->linesize; + return 0; +} + /** * \brief Invalidate one D-Cache line specified by address in M-Mode * \details @@ -1384,6 +1388,7 @@ __STATIC_FORCEINLINE void UFlushInvalDCache(void) { __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL_ALL); } +#endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */ /** @} */ /* End of Doxygen Group NMSIS_Core_DCache */ #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */ diff --git a/NMSIS/Core/Include/core_feature_dsp.h b/NMSIS/Core/Include/core_feature_dsp.h index e7efd7116..d8ce384c0 100644 --- a/NMSIS/Core/Include/core_feature_dsp.h +++ b/NMSIS/Core/Include/core_feature_dsp.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__INC_INTRINSIC_API) && (__INC_INTRINSIC_API == 1) diff --git a/NMSIS/Core/Include/core_feature_eclic.h b/NMSIS/Core/Include/core_feature_eclic.h index 296a4c639..7a45aa2c3 100644 --- a/NMSIS/Core/Include/core_feature_eclic.h +++ b/NMSIS/Core/Include/core_feature_eclic.h @@ -36,6 +36,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) /** * \defgroup NMSIS_Core_ECLIC_Registers Register Define and Type Definitions Of ECLIC @@ -712,10 +714,16 @@ __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) vec_base += ((unsigned long)IRQn) * sizeof(unsigned long); (* (unsigned long *) vec_base) = vector; #if (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)) +#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)) MFlushDCacheLine((unsigned long)vec_base); #endif +#endif #if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)) +#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)) MInvalICacheLine((unsigned long)vec_base); +#else + __FENCE_I(); +#endif #endif } @@ -748,7 +756,8 @@ __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) * This function set exception handler address to 'CSR_MTVEC'. * \param [in] addr Exception handler address * \remarks - * - This function use to set exception handler address to 'CSR_MTVEC'. Address is 4 bytes align. + * - This function use to set exception handler address to 'CSR_MTVEC'. + * Address need to be aligned to 64 bytes. * \sa * - \ref __get_exc_entry */ @@ -765,7 +774,8 @@ __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) * This function get exception handler address from 'CSR_MTVEC'. * \return Exception handler address * \remarks - * - This function use to get exception handler address from 'CSR_MTVEC'. Address is 4 bytes align + * - This function use to get exception handler address from 'CSR_MTVEC'. + * Address need to be aligned to 64 bytes. * \sa * - \ref __set_exc_entry */ diff --git a/NMSIS/Core/Include/core_feature_fpu.h b/NMSIS/Core/Include/core_feature_fpu.h index c9e13b79d..a4c68990c 100644 --- a/NMSIS/Core/Include/core_feature_fpu.h +++ b/NMSIS/Core/Include/core_feature_fpu.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + /* ===== FPU Operations ===== */ /** * \defgroup NMSIS_Core_FPU_Functions FPU Functions diff --git a/NMSIS/Core/Include/core_feature_pmp.h b/NMSIS/Core/Include/core_feature_pmp.h index 997dfaee1..8347af0d4 100644 --- a/NMSIS/Core/Include/core_feature_pmp.h +++ b/NMSIS/Core/Include/core_feature_pmp.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) /* ===== PMP Operations ===== */ /** diff --git a/NMSIS/Core/Include/core_feature_timer.h b/NMSIS/Core/Include/core_feature_timer.h index 0fb4f9e94..881a01c9a 100644 --- a/NMSIS/Core/Include/core_feature_timer.h +++ b/NMSIS/Core/Include/core_feature_timer.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) /** * \defgroup NMSIS_Core_SysTimer_Registers Register Define and Type Definitions Of System Timer @@ -114,7 +116,15 @@ typedef struct { */ __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) { +#if __RISCV_XLEN == 32 + uint8_t *addr; + addr = (uint8_t *)(&(SysTimer->MTIMER)); + __SW(addr, 0); // prevent carry + __SW(addr + 4, (uint32_t)(value >> 32)); + __SW(addr, (uint32_t)(value)); +#else SysTimer->MTIMER = value; +#endif } /** @@ -131,9 +141,9 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) #if __RISCV_XLEN == 32 volatile uint32_t high0, low, high; uint64_t full; - void *addr; + uint8_t *addr; - addr = (void *)(&(SysTimer->MTIMER)); + addr = (uint8_t *)(&(SysTimer->MTIMER)); high0 = __LW(addr + 4); low = __LW(addr); @@ -163,12 +173,21 @@ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) { unsigned long hartid = __RV_CSR_READ(CSR_MHARTID); if (hartid == 0) { +#if __RISCV_XLEN == 32 + uint8_t *addr; + addr = (uint8_t *)(&(SysTimer->MTIMERCMP)); + __SW(addr, -1U); // prevent load > timecmp + __SW(addr + 4, (uint32_t)(value >> 32)); + __SW(addr, (uint32_t)(value)); +#else SysTimer->MTIMERCMP = value; +#endif } else { - void *addr = (void *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); #if __RISCV_XLEN == 32 - __SW(addr, (uint32_t)value); + __SW(addr, -1U); // prevent load > timecmp __SW(addr + 4, (uint32_t)(value >> 32)); + __SW(addr, (uint32_t)value); #else __SD(addr, value); #endif @@ -191,7 +210,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) return SysTimer->MTIMERCMP; } else { uint64_t full; - void *addr = (void *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); #if __RISCV_XLEN == 32 // MTIMECMP didn't increase uint32_t high, low; @@ -275,7 +294,7 @@ __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) if (hartid == 0) { SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk; } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, SysTimer_MSIP_MSIP_Msk); } } @@ -295,7 +314,7 @@ __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) if (hartid == 0) { SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk; } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, 0); } } @@ -317,7 +336,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) if (hartid == 0) { return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk); } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); return __LW(addr); } } @@ -334,7 +353,7 @@ __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) if (hartid == 0) { SysTimer->MSIP = (msip & SysTimer_MSIP_Msk); } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, msip); } } @@ -363,7 +382,7 @@ __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) */ __STATIC_FORCEINLINE void SysTimer_SendIPI(uint32_t hartid) { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, 1); } @@ -375,7 +394,7 @@ __STATIC_FORCEINLINE void SysTimer_SendIPI(uint32_t hartid) */ __STATIC_FORCEINLINE void SysTimer_ClearIPI(uint32_t hartid) { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, 0); } diff --git a/NMSIS/Core/Include/core_feature_vector.h b/NMSIS/Core/Include/core_feature_vector.h index df826cc8e..6d3893f93 100644 --- a/NMSIS/Core/Include/core_feature_vector.h +++ b/NMSIS/Core/Include/core_feature_vector.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__VECTOR_PRESENT) && (__VECTOR_PRESENT == 1) /* ########################### CPU Vector Intrinsic Functions ########################### */ diff --git a/NMSIS/Core/Include/nmsis_gcc.h b/NMSIS/Core/Include/nmsis_gcc.h index 9f7eb9d26..a92c37395 100644 --- a/NMSIS/Core/Include/nmsis_gcc.h +++ b/NMSIS/Core/Include/nmsis_gcc.h @@ -23,12 +23,13 @@ * @brief NMSIS compiler GCC header file */ #include -#include "riscv_encoding.h" #ifdef __cplusplus extern "C" { #endif +#include "riscv_encoding.h" + /* ######################### Startup and Lowlevel Init ######################## */ /** * \defgroup NMSIS_Core_CompilerControl Compiler Control @@ -42,11 +43,6 @@ * The header file nmsis_compiler.h is also included by each Device Header File so that these definitions are available. * @{ */ -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin diff --git a/NMSIS/Core/Include/nmsis_version.h b/NMSIS/Core/Include/nmsis_version.h index 0972cd7a1..dc43e8e0a 100644 --- a/NMSIS/Core/Include/nmsis_version.h +++ b/NMSIS/Core/Include/nmsis_version.h @@ -72,7 +72,7 @@ * The NMSIS patch version can be used to * show bug fixes in this package. **/ -#define __NMSIS_VERSION_PATCH (3U) +#define __NMSIS_VERSION_PATCH (4U) /** * \brief Represent the NMSIS Version * \details diff --git a/NMSIS/Core/Include/riscv_encoding.h b/NMSIS/Core/Include/riscv_encoding.h index cbf90a728..1e00e6db2 100644 --- a/NMSIS/Core/Include/riscv_encoding.h +++ b/NMSIS/Core/Include/riscv_encoding.h @@ -18,10 +18,12 @@ #ifndef __RISCV_ENCODING_H__ #define __RISCV_ENCODING_H__ -#include "riscv_bits.h" #ifdef __cplusplus extern "C" { #endif + +#include "riscv_bits.h" + /** * \defgroup NMSIS_Core_CSR_Encoding Core CSR Encodings * \ingroup NMSIS_Core diff --git a/NMSIS/DSP/Include/riscv_math_types.h b/NMSIS/DSP/Include/riscv_math_types.h index 9be85073c..258cea2c5 100755 --- a/NMSIS/DSP/Include/riscv_math_types.h +++ b/NMSIS/DSP/Include/riscv_math_types.h @@ -70,19 +70,27 @@ extern "C" #define __NMSIS_GENERIC #if (defined (__riscv_dsp)) + #undef __DSP_PRESENT #define __DSP_PRESENT 1 #undef __RISCV_FEATURE_DSP #define __RISCV_FEATURE_DSP 1 #endif #if (defined (__riscv_vector)) + #undef __VECTOR_PRESENT #define __VECTOR_PRESENT 1 #undef __RISCV_FEATURE_VECTOR #define __RISCV_FEATURE_VECTOR 1 #endif +#if (defined (__riscv_bitmainp)) + #define __BITMANIP_PRESENT 1 + #undef __RISCV_FEATURE_BITMANIP + #define __RISCV_FEATURE_BITMANIP 1 +#endif + /* Include intrinisc header files for rvb/rvp/rvv */ #undef __INC_INTRINSIC_API -#define __INC_INTRINSIC_API 1 +#define __INC_INTRINSIC_API 1 #include "nmsis_core.h" #undef __NMSIS_GENERIC @@ -105,6 +113,11 @@ extern "C" #define RISCV_MATH_VECTOR 1 #endif +/* evaluate RISCV Bitmanip feature */ +#if (defined(__riscv_bitmainp)) + #define RISCV_MATH_BITMANIP 1 +#endif + #if defined ( __GNUC__ ) #define LOW_OPTIMIZATION_ENTER \ __attribute__(( optimize("-O1") )) diff --git a/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt index 4782fc368..f5f85f3e6 100644 --- a/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_base_math) diff --git a/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt b/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt index 36c20af3f..a4f7ade56 100755 --- a/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_bayes) diff --git a/NMSIS/DSP/Source/CMakeLists.txt b/NMSIS/DSP/Source/CMakeLists.txt index f18133b5d..471e60f52 100755 --- a/NMSIS/DSP/Source/CMakeLists.txt +++ b/NMSIS/DSP/Source/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) SET(CMAKE_C_COMPILER riscv-nuclei-elf-gcc) SET(CMAKE_CXX_COMPILER riscv-nuclei-elf-g++) diff --git a/NMSIS/DSP/Source/CommonTables/CMakeLists.txt b/NMSIS/DSP/Source/CommonTables/CMakeLists.txt index 764ff89d8..6cfd089be 100644 --- a/NMSIS/DSP/Source/CommonTables/CMakeLists.txt +++ b/NMSIS/DSP/Source/CommonTables/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_common_table) diff --git a/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt index 3d23b3e8e..fac2f2b0b 100644 --- a/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_complex) diff --git a/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c b/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c index ae7a2b56c..df7f3cea7 100644 --- a/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c +++ b/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c @@ -127,7 +127,7 @@ void riscv_cmplx_mult_cmplx_q15( d = *pSrcB++; /* store result in 3.13 format in destination buffer. */ -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -140,7 +140,7 @@ void riscv_cmplx_mult_cmplx_q15( c = *pSrcB++; d = *pSrcB++; -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -153,7 +153,7 @@ void riscv_cmplx_mult_cmplx_q15( c = *pSrcB++; d = *pSrcB++; -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -166,7 +166,7 @@ void riscv_cmplx_mult_cmplx_q15( c = *pSrcB++; d = *pSrcB++; -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -200,7 +200,7 @@ void riscv_cmplx_mult_cmplx_q15( d = *pSrcB++; /* store result in 3.13 format in destination buffer. */ -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else diff --git a/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt b/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt index ac45a7261..1262fd0c0 100644 --- a/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_controller) diff --git a/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt b/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt index 8bc097aef..365853bd6 100755 --- a/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_distance) diff --git a/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt index 5faa87d72..f031c89da 100644 --- a/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_fast_math) diff --git a/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt b/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt index 097704be9..f96534571 100644 --- a/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_filtering) diff --git a/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt b/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt index e387fdba7..2569516c7 100755 --- a/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_interpolation) diff --git a/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt b/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt index 414ae9771..2391e9f4b 100644 --- a/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_matrix) diff --git a/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt index 53fabdfff..4dccfdaf8 100755 --- a/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_quaternion_math) diff --git a/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt b/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt index 30925eda5..70114adbe 100755 --- a/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_svm) diff --git a/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt b/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt index f69d7f56c..d776e2f80 100644 --- a/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_statistic) diff --git a/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt b/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt index 7dfec1dfa..6f93f2fa8 100644 --- a/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_support) diff --git a/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt b/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt index 4f2e6665d..bc5f255f5 100644 --- a/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_transform) diff --git a/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt b/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt index ae8d59d31..956e68401 100644 --- a/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNActivation) diff --git a/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt b/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt index 316803564..30bd9fb70 100755 --- a/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNBasicMaths) diff --git a/NMSIS/NN/Source/CMakeLists.txt b/NMSIS/NN/Source/CMakeLists.txt index 0d0994329..fc6642313 100644 --- a/NMSIS/NN/Source/CMakeLists.txt +++ b/NMSIS/NN/Source/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) SET(CMAKE_C_COMPILER riscv-nuclei-elf-gcc) SET(CMAKE_CXX_COMPILER riscv-nuclei-elf-g++) diff --git a/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt b/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt index c6cc9aeec..34918b48d 100644 --- a/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNConcatenation) diff --git a/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt b/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt index 4df17b4e3..b449124c2 100644 --- a/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNConvolutions) diff --git a/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt b/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt index 05f6e57e6..ee95a3df8 100644 --- a/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNFullyConnected) diff --git a/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt b/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt index e3c6409b9..2a151f2c0 100644 --- a/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSupport) diff --git a/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt b/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt index 755896615..85fb8fb60 100644 --- a/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNPooling) diff --git a/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c b/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c index 26d875a7a..8637b7a96 100644 --- a/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c +++ b/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c @@ -61,6 +61,33 @@ static void buffer_scale_back_q7_to_q7(q7_t * buffer, q7_t * target, uint16_t le } } +static void buffer_scale_back_q15_to_q7(q15_t *buffer, q7_t *target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t)(buffer[i] / scale); + } +} + +// TODO: to be optimized in RVV +static void accumulate_q7_to_q15(q15_t *base, q7_t *target, const uint16_t length) +{ + vint8m4_t tval; + vint16m8_t dval; + size_t l; + uint32_t cnt = length; + + for (; (l = vsetvl_e16m8(cnt)) > 0; cnt -= l) { + tval = vle8_v_i8m4(target, l); + dval = vle16_v_i16m8(base, l); + vse16_v_i16m8(base, vwadd_wv_i16m8(dval, tval, l), l); + target += l; + base += l; + } +} + #else #if defined (RISCV_MATH_DSP) @@ -420,17 +447,20 @@ void riscv_avepool_q7_HWC(q7_t *Im_in, } /* first step is to copy over initial data */ - riscv_q7_to_q7_no_shift(win_start, (q7_t *)buffer, ch_im_in); + //riscv_q7_to_q7_no_shift(win_start, (q7_t *)buffer, ch_im_in); + riscv_q7_to_q15_no_shift(win_start, buffer, ch_im_in); count = 1; /* start the max operation from the second part */ win_start += ch_im_in; for (; win_start < win_stop; win_start += ch_im_in) { - riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, win_start, ch_im_in); + //riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, win_start, ch_im_in); + accumulate_q7_to_q15(buffer, win_start, ch_im_in); count++; } - buffer_scale_back_q7_to_q7(buffer, target, ch_im_in, count); + //buffer_scale_back_q7_to_q7(buffer, target, ch_im_in, count); + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); // riscv_scale_q7((q7_t *)buffer,(1/ch_im_in),0,target,count); } } @@ -462,7 +492,8 @@ void riscv_avepool_q7_HWC(q7_t *Im_in, } /* copy over the first row */ - riscv_q7_to_q7_no_shift(row_start, (q7_t *)buffer, dim_im_out * ch_im_in); + riscv_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + //riscv_q7_to_q7_no_shift(row_start, (q7_t *)buffer, dim_im_out * ch_im_in); count = 1; /* move over to next row */ @@ -470,10 +501,12 @@ void riscv_avepool_q7_HWC(q7_t *Im_in, for (; row_start < row_end; row_start += dim_im_in * ch_im_in) { - riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, row_start, dim_im_out * ch_im_in); + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + //riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, row_start, dim_im_out * ch_im_in); count++; } - buffer_scale_back_q7_to_q7(buffer, target, dim_im_out * ch_im_in, count); + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + //buffer_scale_back_q7_to_q7(buffer, target, dim_im_out * ch_im_in, count); // riscv_scale_q7((q7_t *)buffer,ch_im_in,0,target,count); } diff --git a/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt b/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt index 93f2d08fa..1b14fb459 100644 --- a/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNReshape) diff --git a/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt b/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt index d64d807ec..8bd9debad 100644 --- a/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSVDF) diff --git a/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt b/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt index f0da004ad..6a6831a62 100644 --- a/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSoftmax) diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Makefile b/NMSIS/NN/Tests/Cases/Makefile.common similarity index 89% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Makefile rename to NMSIS/NN/Tests/Cases/Makefile.common index 3601363b1..bf86c1d19 100644 --- a/NMSIS/NN/NN_Lib_Tests/nn_test/Makefile +++ b/NMSIS/NN/Tests/Cases/Makefile.common @@ -5,7 +5,7 @@ NUCLEI_SDK_NMSIS ?= $(NUCLEI_SDK_ROOT)/NMSIS SRCDIRS = . -INCDIRS = . $(NUCLEI_SDK_NMSIS)/NN/NN_Lib_Tests/nn_test/Ref_Implementations +INCDIRS = . .. $(NUCLEI_SDK_NMSIS)/NN/Tests/Ref/Source LIBDIRS = $(NUCLEI_SDK_NMSIS)/Library/NNREF/GCC diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/bench.h b/NMSIS/NN/Tests/Cases/bench.h similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/bench.h rename to NMSIS/NN/Tests/Cases/bench.h diff --git a/NMSIS/NN/Tests/Cases/full/Makefile b/NMSIS/NN/Tests/Cases/full/Makefile new file mode 100644 index 000000000..ab3546b88 --- /dev/null +++ b/NMSIS/NN/Tests/Cases/full/Makefile @@ -0,0 +1,3 @@ +BUILD_ROOT_DIR = ../ + +include $(BUILD_ROOT_DIR)/Makefile.common diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/riscv_nnexamples_nn_test.cpp b/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp similarity index 98% rename from NMSIS/NN/NN_Lib_Tests/nn_test/riscv_nnexamples_nn_test.cpp rename to NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp index cff6981ac..752d57112 100644 --- a/NMSIS/NN/NN_Lib_Tests/nn_test/riscv_nnexamples_nn_test.cpp +++ b/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp @@ -1035,6 +1035,11 @@ int main() q7_t *pool_out_ref = test3; q7_t *pool_out_opt = test3 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH / 2; + srand(__RV_CSR_READ(mcycle)); + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + test1[i] = rand(); + } // copy over the img input for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { @@ -1083,7 +1088,7 @@ int main() riscv_avepool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *) test2, pool_out_opt); BENCH_END(riscv_avepool_q7_HWC); - verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); delete[]test1; delete[]test2; @@ -1193,7 +1198,8 @@ int main() #ifdef TEST_SVD #define SVD_SIZE 2048 test1 = new q7_t[SVD_SIZE*2]; - test2 = new q15_t[SVD_SIZE*2]; + q15_t *test2_ref = new q15_t[SVD_SIZE*3]; + q15_t *test2_opt = new q15_t[SVD_SIZE*3]; test3 = new q7_t[SVD_SIZE*2]; q7_t *test20; @@ -1205,6 +1211,7 @@ int main() q31_t *test22; test22 = new q31_t[SVD_SIZE*2]; + srand(__RV_CSR_READ(mcycle)); for (int i=0;i>> Build and install %s library for config %s" % (libsrc, key)) _, _, buildlog = nlb.get_build_artifacts(key) target_alias = aliascfgs.get(key, []) - ret = nlb.build(key, target_alias, buildcfgs[key], libroot, parallel) + ret = nlb.build(key, target_alias, buildcfgs[key], libroot, parallel, norebuild) cost_time = round(time.time() - start_time, 2) rst_table.add_row([key, ret, cost_time, buildlog]) @@ -175,7 +183,7 @@ def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, start_time = time.time() print(">>> Build and install %s library for config %s" % (libsrc, target)) _, _, buildlog = nlb.get_build_artifacts(target) - ret = nlb.build(target, buildcfgs[target], libroot, parallel) + ret = nlb.build(target, buildcfgs[target], libroot, parallel, norebuild) cost_time = round(time.time() - start_time, 2) rst_table.add_row([target, ret, cost_time, buildlog]) if ret == False: @@ -197,6 +205,7 @@ def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, parser.add_argument('--lib_src', default="DSP/Source", help="Where library source code's cmakefile located") parser.add_argument('--lib_prefix', default="nmsis_dsp", help="Library prefix") parser.add_argument('--lib_root', default="Library/DSP/GCC", help="Library built and generate to") + parser.add_argument('--norebuild', action='store_true', help="Don't clean build directories, and rebuild it, just reuse previous build objects for faster build") parser.add_argument('--strip', action='store_true', help="If specified, the installed library will strip out debug symbols") parser.add_argument('--target', default="all", help="if target = all, it means run all the targets defined in config") parser.add_argument('--parallel', default="-j4", help="parallel build library, default -j4") @@ -211,8 +220,10 @@ def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, sys.exit(1) buildcfgs = get_buildcfgs(jsoncfg) aliascfgs = get_aliascfgs(jsoncfg) - runrst = install_library(args.lib_src, buildcfgs, aliascfgs, args.lib_prefix, args.lib_root, args.target, args.strip, args.parallel, args.ignore_fail) + runrst = install_library(args.lib_src, buildcfgs, aliascfgs, args.lib_prefix, args.lib_root, args.target, args.strip, args.parallel, args.ignore_fail, args.norebuild) print("Build Library %s with config %s, generated into %s status: %s" %(args.lib_src, args.config, args.lib_root, runrst)) + if args.norebuild: + print("!!!Use Caution: This build is not fully rebuilt, please take care!!!!") if runrst: sys.exit(0) else: diff --git a/NMSIS/Scripts/Build/nmsis_dsp.json b/NMSIS/Scripts/Build/nmsis_dsp.json index 17101c713..ff10670c7 100644 --- a/NMSIS/Scripts/Build/nmsis_dsp.json +++ b/NMSIS/Scripts/Build/nmsis_dsp.json @@ -22,6 +22,18 @@ "RISCV_ARCH" : "rv32imafdc", "RISCV_ABI": "ilp32d" }, + "rv32imacb" : { + "RISCV_ARCH" : "rv32imacb", + "RISCV_ABI": "ilp32" + }, + "rv32imafcb" : { + "RISCV_ARCH" : "rv32imafcb", + "RISCV_ABI": "ilp32f" + }, + "rv32imafdcb" : { + "RISCV_ARCH" : "rv32imafdcb", + "RISCV_ABI": "ilp32d" + }, "rv32imacp" : { "RISCV_ARCH" : "rv32imacp", "RISCV_ABI": "ilp32", @@ -37,6 +49,21 @@ "RISCV_ABI": "ilp32d", "DSP64" : "ON" }, + "rv32imacbp" : { + "RISCV_ARCH" : "rv32imacbp", + "RISCV_ABI": "ilp32", + "DSP64" : "ON" + }, + "rv32imafcbp" : { + "RISCV_ARCH" : "rv32imafcbp", + "RISCV_ABI": "ilp32f", + "DSP64" : "ON" + }, + "rv32imafdcbp" : { + "RISCV_ARCH" : "rv32imafdcbp", + "RISCV_ABI": "ilp32d", + "DSP64" : "ON" + }, "rv64imac" : { "RISCV_ARCH" : "rv64imac", "RISCV_ABI": "lp64" @@ -49,6 +76,18 @@ "RISCV_ARCH" : "rv64imafdc", "RISCV_ABI": "lp64d" }, + "rv64imacb" : { + "RISCV_ARCH" : "rv64imacb", + "RISCV_ABI": "lp64" + }, + "rv64imafcb" : { + "RISCV_ARCH" : "rv64imafcb", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcb" : { + "RISCV_ARCH" : "rv64imafdcb", + "RISCV_ABI": "lp64d" + }, "rv64imacp" : { "RISCV_ARCH" : "rv64imacp", "RISCV_ABI": "lp64" @@ -61,6 +100,18 @@ "RISCV_ARCH" : "rv64imafdcp", "RISCV_ABI": "lp64d" }, + "rv64imafdcbp" : { + "RISCV_ARCH" : "rv64imafdcbp", + "RISCV_ABI": "lp64d" + }, + "rv64imacbp" : { + "RISCV_ARCH" : "rv64imacbp", + "RISCV_ABI": "lp64" + }, + "rv64imafcbp" : { + "RISCV_ARCH" : "rv64imafcbp", + "RISCV_ABI": "lp64f" + }, "rv64imafcv" : { "RISCV_ARCH" : "rv64imafcv", "RISCV_ABI": "lp64f" @@ -69,6 +120,14 @@ "RISCV_ARCH" : "rv64imafdcv", "RISCV_ABI": "lp64d" }, + "rv64imafcbv" : { + "RISCV_ARCH" : "rv64imafcbv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbv" : { + "RISCV_ARCH" : "rv64imafdcbv", + "RISCV_ABI": "lp64d" + }, "rv64imafcpv" : { "RISCV_ARCH" : "rv64imafcpv", "RISCV_ABI": "lp64f" @@ -76,6 +135,14 @@ "rv64imafdcpv" : { "RISCV_ARCH" : "rv64imafdcpv", "RISCV_ABI": "lp64d" + }, + "rv64imafcbpv" : { + "RISCV_ARCH" : "rv64imafcbpv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbpv" : { + "RISCV_ARCH" : "rv64imafdcbpv", + "RISCV_ABI": "lp64d" } } } diff --git a/NMSIS/Scripts/Build/nmsis_nn.json b/NMSIS/Scripts/Build/nmsis_nn.json index df96e49da..c63b45d91 100644 --- a/NMSIS/Scripts/Build/nmsis_nn.json +++ b/NMSIS/Scripts/Build/nmsis_nn.json @@ -22,6 +22,18 @@ "RISCV_ARCH" : "rv32imafdc", "RISCV_ABI": "ilp32d" }, + "rv32imacb" : { + "RISCV_ARCH" : "rv32imacb", + "RISCV_ABI": "ilp32" + }, + "rv32imafcb" : { + "RISCV_ARCH" : "rv32imafcb", + "RISCV_ABI": "ilp32f" + }, + "rv32imafdcb" : { + "RISCV_ARCH" : "rv32imafdcb", + "RISCV_ABI": "ilp32d" + }, "rv32imacp" : { "RISCV_ARCH" : "rv32imacp", "RISCV_ABI": "ilp32", @@ -37,6 +49,21 @@ "RISCV_ABI": "ilp32d", "DSP64" : "ON" }, + "rv32imacbp" : { + "RISCV_ARCH" : "rv32imacbp", + "RISCV_ABI": "ilp32", + "DSP64" : "ON" + }, + "rv32imafcbp" : { + "RISCV_ARCH" : "rv32imafcbp", + "RISCV_ABI": "ilp32f", + "DSP64" : "ON" + }, + "rv32imafdcbp" : { + "RISCV_ARCH" : "rv32imafdcbp", + "RISCV_ABI": "ilp32d", + "DSP64" : "ON" + }, "rv64imac" : { "RISCV_ARCH" : "rv64imac", "RISCV_ABI": "lp64" @@ -49,6 +76,18 @@ "RISCV_ARCH" : "rv64imafdc", "RISCV_ABI": "lp64d" }, + "rv64imacb" : { + "RISCV_ARCH" : "rv64imacb", + "RISCV_ABI": "lp64" + }, + "rv64imafcb" : { + "RISCV_ARCH" : "rv64imafcb", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcb" : { + "RISCV_ARCH" : "rv64imafdcb", + "RISCV_ABI": "lp64d" + }, "rv64imacp" : { "RISCV_ARCH" : "rv64imacp", "RISCV_ABI": "lp64" @@ -61,6 +100,18 @@ "RISCV_ARCH" : "rv64imafdcp", "RISCV_ABI": "lp64d" }, + "rv64imafdcbp" : { + "RISCV_ARCH" : "rv64imafdcbp", + "RISCV_ABI": "lp64d" + }, + "rv64imacbp" : { + "RISCV_ARCH" : "rv64imacbp", + "RISCV_ABI": "lp64" + }, + "rv64imafcbp" : { + "RISCV_ARCH" : "rv64imafcbp", + "RISCV_ABI": "lp64f" + }, "rv64imafcv" : { "RISCV_ARCH" : "rv64imafcv", "RISCV_ABI": "lp64f" @@ -69,6 +120,14 @@ "RISCV_ARCH" : "rv64imafdcv", "RISCV_ABI": "lp64d" }, + "rv64imafcbv" : { + "RISCV_ARCH" : "rv64imafcbv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbv" : { + "RISCV_ARCH" : "rv64imafdcbv", + "RISCV_ABI": "lp64d" + }, "rv64imafcpv" : { "RISCV_ARCH" : "rv64imafcpv", "RISCV_ABI": "lp64f" @@ -76,6 +135,14 @@ "rv64imafdcpv" : { "RISCV_ARCH" : "rv64imafdcpv", "RISCV_ABI": "lp64d" + }, + "rv64imafcbpv" : { + "RISCV_ARCH" : "rv64imafcbpv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbpv" : { + "RISCV_ARCH" : "rv64imafdcbpv", + "RISCV_ABI": "lp64d" } } } diff --git a/NMSIS/Scripts/Build/nmsis_nnref.json b/NMSIS/Scripts/Build/nmsis_nnref.json index aa0838cd2..f29e2fd40 100644 --- a/NMSIS/Scripts/Build/nmsis_nnref.json +++ b/NMSIS/Scripts/Build/nmsis_nnref.json @@ -32,11 +32,11 @@ } }, "alias_target" : { - "rv32imac" : ["rv32imacp"], - "rv32imafc" : ["rv32imafcp"], - "rv32imafdc" : ["rv32imafdcp"], - "rv64imac" : ["rv64imacp"], - "rv64imafc" : ["rv64imafcp", "rv64imafcv", "rv64imafcpv"], - "rv64imafdc" : ["rv64imafdcp", "rv64imafdcv", "rv64imafdcpv"] + "rv32imac" : ["rv32imacp", "rv32imacb", "rv32imacbp"], + "rv32imafc" : ["rv32imafcp", "rv32imafcb", "rv32imafcbp"], + "rv32imafdc" : ["rv32imafdcp", "rv32imafdcb", "rv32imafdcbp"], + "rv64imac" : ["rv64imacp", "rv64imacb", "rv64imacbp"], + "rv64imafc" : ["rv64imafcb", "rv64imafcp", "rv64imafcv", "rv64imafcbp", "rv64imafcbv", "rv64imafcpv", "rv64imafcbpv"], + "rv64imafdc" : ["rv64imafdcb", "rv64imafdcp", "rv64imafdcv", "rv64imafdcbp", "rv64imafdcbv", "rv64imafdcpv", "rv64imafdcbpv"] } } diff --git a/NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh b/NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh new file mode 100755 index 000000000..068d836b4 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh @@ -0,0 +1,74 @@ +#!/bin/env bash +LOGROOT=${LOGROOT:-gen} +DRYRUN=${DRYRUN:-0} +RUNON=${RUNON-nothing} +TOOL_VER=${TOOL_VER:-2022.01} + +SCRIPTDIR=$(dirname $(readlink -f $BASH_SOURCE)) + +DEVTOOL_ENV=${DEVTOOL_ENV:-/home/share/devtools/env.sh} + +TOOL_VER=$TOOL_VER source $DEVTOOL_ENV + +source $SCRIPTDIR/setup.sh +LOGROOT=$(readlink -f $LOGROOT) + +if [ ! -d $LOGROOT ] ; then + mkdir -p $LOGROOT +fi + +function describe_repo { + local repodir=${1} + local repodesc=${2:-repogit.txt} + repodir=$(readlink -f $repodir) + if [ -d ${repodir}/.git ] ; then + pushd ${repodir} + echo "Git Repo $repodir Information:" >> ${repodesc} + gitver=$(git describe --tags --always --abbrev=10 --dirty) + gitslog=$(git log --oneline -1) + echo "git describe version: $gitver" >> ${repodesc} + echo "git shortlog: $gitslog" >> ${repodesc} + git submodule >> ${repodesc} + popd + else + echo "$repodir not a git repo" >> ${repodesc} + fi +} + +function describe_build { + logfile=$1 + echo -n "Build Date: " > $logfile + date >> $logfile + echo "Nuclei GNU Toolchain Version:" >> $logfile + riscv-nuclei-elf-gcc -v >> $logfile 2>&1 +} + +function record_buildinfo { + BUILDTXT=$LOGROOT/build.txt + + describe_build $BUILDTXT + describe_repo $NUCLEI_SDK_ROOT $BUILDTXT + describe_repo $NUCLEI_SDK_NMSIS/.. $BUILDTXT +} + +function changelinkscript { + echo "Change demosoc linker script to 512K" + sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld +} + +record_buildinfo + +changelinkscript + +NSDK_RUNNER_PY="$NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_runner.py" + +pushd $NUCLEI_SDK_NMSIS +for lib in nmsis_dsp nmsis_nn +do + RUNNER_CMD="python3 $NSDK_RUNNER_PY --appyaml $SCRIPTDIR/$lib.yaml --logdir $LOGROOT/$lib --runon $RUNON --cfgloc $SCRIPTDIR" + echo $RUNNER_CMD + if [[ $DRYRUN == 0 ]] ; then + eval $RUNNER_CMD + fi +done +popd diff --git a/NMSIS/Scripts/Configs/fpga/n200.json b/NMSIS/Scripts/Configs/fpga/n200.json new file mode 100644 index 000000000..6b8aecb0d --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n200.json @@ -0,0 +1,12 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "200" + }, + "build_configs": { + "rv32imac": { "CORE": "n203" }, + "rv32imacb": { "CORE": "n203", "ARCH_EXT": "b" } + } +} diff --git a/NMSIS/Scripts/Configs/fpga/n300.json b/NMSIS/Scripts/Configs/fpga/n300.json new file mode 100644 index 000000000..ad6c31503 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n300.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "300" + }, + "build_configs": { + "rv32imac": {"CORE":"n300"}, + "rv32imacb": {"CORE":"n300", "ARCH_EXT":"b"}, + "rv32imacp": {"CORE":"n300", "ARCH_EXT":"p"}, + "rv32imacbp": {"CORE":"n300", "ARCH_EXT":"bp"}, + "rv32imafc": {"CORE":"n300f", "ARCH_EXT":""}, + "rv32imafcb": {"CORE":"n300f", "ARCH_EXT":"b"}, + "rv32imafcp": {"CORE":"n300f", "ARCH_EXT":"p"}, + "rv32imafcbp": {"CORE":"n300f", "ARCH_EXT":"bp"}, + "rv32imafdc": {"CORE":"n300fd", "ARCH_EXT":""}, + "rv32imafdcb": {"CORE":"n300fd", "ARCH_EXT":"b"}, + "rv32imafdcp": {"CORE":"n300fd", "ARCH_EXT":"p"}, + "rv32imafdcbp": {"CORE":"n300fd", "ARCH_EXT":"bp"} + } +} diff --git a/NMSIS/Scripts/Configs/fpga/n600.json b/NMSIS/Scripts/Configs/fpga/n600.json new file mode 100644 index 000000000..3628a26dc --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n600.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "600" + }, + "build_configs": { + "rv32imac": { "CORE": "n600" }, + "rv32imacb": { "CORE": "n600", "ARCH_EXT": "b" }, + "rv32imacp": { "CORE": "n600", "ARCH_EXT": "p" }, + "rv32imacbp": { "CORE": "n600", "ARCH_EXT": "bp" }, + "rv32imafc": { "CORE": "n600f", "ARCH_EXT": "" }, + "rv32imafcb": { "CORE": "n600f", "ARCH_EXT": "b" }, + "rv32imafcp": { "CORE": "n600f", "ARCH_EXT": "p" }, + "rv32imafcbp": { "CORE": "n600f", "ARCH_EXT": "bp" }, + "rv32imafdc": { "CORE": "n600fd", "ARCH_EXT": "" }, + "rv32imafdcb": { "CORE": "n600fd", "ARCH_EXT": "b" }, + "rv32imafdcp": { "CORE": "n600fd", "ARCH_EXT": "p" }, + "rv32imafdcbp": { "CORE": "n600fd", "ARCH_EXT": "bp" } + } +} \ No newline at end of file diff --git a/NMSIS/Scripts/Configs/fpga/n900.json b/NMSIS/Scripts/Configs/fpga/n900.json new file mode 100644 index 000000000..6fef0ece6 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n900.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "900" + }, + "build_configs": { + "rv32imac": {"CORE":"n900"}, + "rv32imacb": {"CORE":"n900", "ARCH_EXT":"b"}, + "rv32imacp": {"CORE":"n900", "ARCH_EXT":"p"}, + "rv32imacbp": {"CORE":"n900", "ARCH_EXT":"bp"}, + "rv32imafc": {"CORE":"n900f", "ARCH_EXT":""}, + "rv32imafcb": {"CORE":"n900f", "ARCH_EXT":"b"}, + "rv32imafcp": {"CORE":"n900f", "ARCH_EXT":"p"}, + "rv32imafcbp": {"CORE":"n900f", "ARCH_EXT":"bp"}, + "rv32imafdc": {"CORE":"n900fd", "ARCH_EXT":""}, + "rv32imafdcb": {"CORE":"n900fd", "ARCH_EXT":"b"}, + "rv32imafdcp": {"CORE":"n900fd", "ARCH_EXT":"p"}, + "rv32imafdcbp": {"CORE":"n900fd", "ARCH_EXT":"bp"} + } +} diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json new file mode 100644 index 000000000..a33ebe520 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json @@ -0,0 +1,25 @@ +{ + "run_config": { + "target": "hardware", + "hardware": { + "timeout": 480 + }, + "qemu": { + "timeout": 240 + } + }, + "parallel": "-j", + "copy_objects": true, + "build_target": "clean all", + "build_config": { + "SOC": "demosoc" + }, + "checks": { + "PASS": ["passed", "Passed"], + "FAIL": ["MEPC", "failed", "Failed", "FAILURE", "ERROR", "test error apprears"] + }, + "appdirs": [ + "DSP/Examples/RISCV", + "DSP/Test" + ] +} \ No newline at end of file diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml new file mode 100644 index 000000000..784b7c4e7 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml @@ -0,0 +1,91 @@ +runcfg: + runner: fpga + +environment: + fpgaloc: Scripts/Configs/fpga + ncycmloc: Scripts/Configs/fpga + cfgloc: Scripts/Configs/fpga + +# fpga runners +fpga_runners: + ddr200t_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ddr200t + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Digilent/210251A08870 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT4JUVF6 + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB1 + ku060_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ku060 + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Xilinx/13724327082c01 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT6JGAXS + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB4 + +ncycm_runners: + n200: + model: n200_software_best_config_cymodel + n300: + model: n300_software_best_config_cymodel + n900: + model: n900_software_best_config_cymodel + ux900: + model: ux900_software_best_config_cymodel + n600: + model: n600_software_best_config_cymodel + ux600: + model: ux600_software_best_config_cymodel + +# configs +configs: + n200: + fpga: ddr200t + # bitstream path related to this yaml's loc or abs path + bitstream: n200_software_best_config_ddr200t_16M.bit + ncycm: n200 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n200.json + # cpu core name + n300: + fpga: ddr200t + bitstream: n300_software_best_config_ddr200t_16M.bit + ncycm: n300 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n300.json + # cpu core name + n600: + fpga: ku060 + bitstream: n600_software_best_config_ku060_16M.bit + ncycm: n600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n600.json + ux600: + fpga: ku060 + bitstream: ux600_software_best_config_ku060_16M.bit + ncycm: ux600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: ux600.json + # cpu core name + n900: + fpga: ku060 + bitstream: n900_software_best_config_ku060_16M.bit + ncycm: n900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n900.json + ux900: + fpga: ku060 + bitstream: ux900_software_best_config_ku060_16M.bit + ncycm: ux900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: ux900.json diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_nn.json b/NMSIS/Scripts/Configs/fpga/nmsis_nn.json new file mode 100644 index 000000000..3da7f8925 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_nn.json @@ -0,0 +1,32 @@ +{ + "run_config": { + "target" : "hardware", + "hardware" : { + "timeout": 480 + }, + "qemu" : { + "timeout": 240 + } + }, + "parallel": "-j", + "copy_objects": true, + "build_target": "clean all", + "build_config": { + "SOC": "demosoc" + }, + "checks": { + "PASS": ["passed", "Passed"], + "FAIL": ["MEPC", "failed", "Failed", "FAILURE", "ERROR", "test error apprears"] + }, + "appdirs": [ + "NN/Examples/RISCV/cifar10", + "NN/Tests/Cases/" + ], + "appconfig": { + "NN/Examples/RISCV/cifar10": { + "checks": { + "PASS": ["label 3: 45, Cat, 35.43%"] + } + } + } +} diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml b/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml new file mode 100644 index 000000000..2a2c6ff11 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml @@ -0,0 +1,91 @@ +runcfg: + runner: fpga + +environment: + fpgaloc: Scripts/Configs/fpga + ncycmloc: Scripts/Configs/fpga + cfgloc: Scripts/Configs/fpga + +# fpga runners +fpga_runners: + ddr200t_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ddr200t + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Digilent/210251A08870 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT4JUVF6 + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB1 + ku060_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ku060 + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Xilinx/13724327082c01 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT6JGAXS + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB4 + +ncycm_runners: + n200: + model: n200_software_best_config_cymodel + n300: + model: n300_software_best_config_cymodel + n900: + model: n900_software_best_config_cymodel + ux900: + model: ux900_software_best_config_cymodel + n600: + model: n600_software_best_config_cymodel + ux600: + model: ux600_software_best_config_cymodel + +# configs +configs: + n200: + fpga: ddr200t + # bitstream path related to this yaml's loc or abs path + bitstream: n200_software_best_config_ddr200t_16M.bit + ncycm: n200 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n200.json + # cpu core name + n300: + fpga: ddr200t + bitstream: n300_software_best_config_ddr200t_16M.bit + ncycm: n300 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n300.json + # cpu core name + n600: + fpga: ku060 + bitstream: n600_software_best_config_ku060_16M.bit + ncycm: n600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n600.json + ux600: + fpga: ku060 + bitstream: ux600_software_best_config_ku060_16M.bit + ncycm: ux600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: ux600.json + # cpu core name + n900: + fpga: ku060 + bitstream: n900_software_best_config_ku060_16M.bit + ncycm: n900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n900.json + ux900: + fpga: ku060 + bitstream: ux900_software_best_config_ku060_16M.bit + ncycm: ux900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: ux900.json diff --git a/NMSIS/Scripts/Configs/fpga/setup.sh b/NMSIS/Scripts/Configs/fpga/setup.sh new file mode 100644 index 000000000..3c0f1748b --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/setup.sh @@ -0,0 +1,18 @@ +#!/bin/env bash +SCRIPTDIR=$(dirname $(readlink -f $BASH_SOURCE)) +NSDK_ROOT=${NSDK_ROOT:-${SCRIPTDIR}/../../../../../nuclei-sdk} +NMSIS_ROOT=${NMSIS_ROOT:-${SCRIPTDIR}/../../../} + +NSDK_ROOT=$(readlink -f ${NSDK_ROOT}) +NMSIS_ROOT=$(readlink -f ${NMSIS_ROOT}) + +echo "Export NUCLEI_SDK_ROOT and NUCLEI_SDK_NMSIS" +export NUCLEI_SDK_ROOT=$NSDK_ROOT +export NUCLEI_SDK_NMSIS=$NMSIS_ROOT +unset NSDK_ROOT NMSIS_ROOT + +echo "NUCLEI_SDK_ROOT=$NUCLEI_SDK_ROOT" +echo "NUCLEI_SDK_NMSIS=$NUCLEI_SDK_NMSIS" + +echo "Only copy elf and map file when do bench" +export SDK_COPY_OBJECTS="elf,map" \ No newline at end of file diff --git a/NMSIS/Scripts/Configs/fpga/ux600.json b/NMSIS/Scripts/Configs/fpga/ux600.json new file mode 100644 index 000000000..6a33f0227 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/ux600.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "600" + }, + "build_configs": { + "rv64imac": { "CORE": "ux600" }, + "rv64imacb": { "CORE": "ux600", "ARCH_EXT": "b" }, + "rv64imacp": { "CORE": "ux600", "ARCH_EXT": "p" }, + "rv64imacbp": { "CORE": "ux600", "ARCH_EXT": "bp" }, + "rv64imafc": { "CORE": "ux600f", "ARCH_EXT": "" }, + "rv64imafcb": { "CORE": "ux600f", "ARCH_EXT": "b" }, + "rv64imafcp": { "CORE": "ux600f", "ARCH_EXT": "p" }, + "rv64imafcbp": { "CORE": "ux600f", "ARCH_EXT": "bp" }, + "rv64imafdc": { "CORE": "ux600fd", "ARCH_EXT": "" }, + "rv64imafdcb": { "CORE": "ux600fd", "ARCH_EXT": "b" }, + "rv64imafdcp": { "CORE": "ux600fd", "ARCH_EXT": "p" }, + "rv64imafdcbp": { "CORE": "ux600fd", "ARCH_EXT": "bp" } + } +} \ No newline at end of file diff --git a/NMSIS/Scripts/Configs/fpga/ux900.json b/NMSIS/Scripts/Configs/fpga/ux900.json new file mode 100644 index 000000000..b6787fa67 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/ux900.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "900" + }, + "build_configs": { + "rv64imac": {"CORE":"ux900"}, + "rv64imacb": {"CORE":"ux900", "ARCH_EXT":"b"}, + "rv64imacp": {"CORE":"ux900", "ARCH_EXT":"p"}, + "rv64imacbp": {"CORE":"ux900", "ARCH_EXT":"bp"}, + "rv64imafc": {"CORE":"ux900f", "ARCH_EXT":""}, + "rv64imafcb": {"CORE":"ux900f", "ARCH_EXT":"b"}, + "rv64imafcp": {"CORE":"ux900f", "ARCH_EXT":"p"}, + "rv64imafcbp": {"CORE":"ux900f", "ARCH_EXT":"bp"}, + "rv64imafdc": {"CORE":"ux900fd", "ARCH_EXT":""}, + "rv64imafdcb": {"CORE":"ux900fd", "ARCH_EXT":"b"}, + "rv64imafdcp": {"CORE":"ux900fd", "ARCH_EXT":"p"}, + "rv64imafdcbp": {"CORE":"ux900fd", "ARCH_EXT":"bp"} + } +} diff --git a/NMSIS/Scripts/Runner/nmsis_dsp.json b/NMSIS/Scripts/Runner/nmsis_dsp.json index a3ad730fc..0275fa6a3 100644 --- a/NMSIS/Scripts/Runner/nmsis_dsp.json +++ b/NMSIS/Scripts/Runner/nmsis_dsp.json @@ -1,19 +1,22 @@ { "run_config": { - "target" : "xlspike", - "xlspike" : { + "target": "qemu", + "xlspike": { "timeout": 480 + }, + "qemu": { + "timeout": 240 } }, "parallel": "-j", - "copy_objects": true, + "copy_objects": false, "build_target": "clean all", "build_config": { - "SOC": "xlspike", + "SOC": "demosoc", "DOWNLOAD": "ilm" }, "checks": { - "PASS": ["passed", "Passed", "SUCCESS"], + "PASS": ["passed", "Passed"], "FAIL": ["MEPC", "failed", "Failed", "FAILURE", "ERROR", "test error apprears"] }, "appdirs": [ @@ -21,21 +24,37 @@ "DSP/Test" ], "build_configs": { - "rv32imac": {"CORE": "n300", "ARCH_EXT":""}, - "rv32imafc": {"CORE": "n300f", "ARCH_EXT":""}, - "rv32imafdc": {"CORE": "n300fd", "ARCH_EXT":""}, - "rv32imacp": {"CORE": "n300", "ARCH_EXT":"p"}, - "rv32imafcp": {"CORE": "n300f", "ARCH_EXT":"p"}, - "rv32imafdcp": {"CORE": "n300fd", "ARCH_EXT":"p"}, - "rv64imac": {"CORE": "nx600", "ARCH_EXT":""}, - "rv64imafc": {"CORE": "nx600f", "ARCH_EXT":""}, - "rv64imafdc": {"CORE": "nx600fd", "ARCH_EXT":""}, - "rv64imacp": {"CORE": "nx600", "ARCH_EXT":"p"}, - "rv64imafcp": {"CORE": "nx600f", "ARCH_EXT":"p"}, - "rv64imafdcp": {"CORE": "nx600fd", "ARCH_EXT":"p"}, - "rv64imafcv": {"CORE": "nx600f", "ARCH_EXT":"v"}, - "rv64imafdcv": {"CORE": "nx600fd", "ARCH_EXT":"v"}, - "rv64imafcpv": {"CORE": "nx600f", "ARCH_EXT":"pv"}, - "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"} + "rv32imac": { "CORE": "n300", "ARCH_EXT": "" }, + "rv32imafc": { "CORE": "n300f", "ARCH_EXT": "" }, + "rv32imafdc": { "CORE": "n300fd", "ARCH_EXT": "" }, + "rv32imacb": { "CORE": "n300", "ARCH_EXT": "b" }, + "rv32imafcb": { "CORE": "n300f", "ARCH_EXT": "b" }, + "rv32imafdcb": { "CORE": "n300fd", "ARCH_EXT": "b" }, + "rv32imacp": { "CORE": "n300", "ARCH_EXT": "p" }, + "rv32imafcp": { "CORE": "n300f", "ARCH_EXT": "p" }, + "rv32imafdcp": { "CORE": "n300fd", "ARCH_EXT": "p" }, + "rv32imacbp": { "CORE": "n300", "ARCH_EXT": "bp" }, + "rv32imafcbp": { "CORE": "n300f", "ARCH_EXT": "bp" }, + "rv32imafdcbp": { "CORE": "n300fd", "ARCH_EXT": "bp" }, + "rv64imac": { "CORE": "nx600", "ARCH_EXT": "" }, + "rv64imafc": { "CORE": "nx600f", "ARCH_EXT": "" }, + "rv64imafdc": { "CORE": "nx600fd", "ARCH_EXT": "" }, + "rv64imacb": { "CORE": "nx600", "ARCH_EXT": "b" }, + "rv64imafcb": { "CORE": "nx600f", "ARCH_EXT": "b" }, + "rv64imafdcb": { "CORE": "nx600fd", "ARCH_EXT": "b" }, + "rv64imacp": { "CORE": "nx600", "ARCH_EXT": "p" }, + "rv64imafcp": { "CORE": "nx600f", "ARCH_EXT": "p" }, + "rv64imafdcp": { "CORE": "nx600fd", "ARCH_EXT": "p" }, + "rv64imacbp": { "CORE": "nx600", "ARCH_EXT": "bp" }, + "rv64imafcbp": { "CORE": "nx600f", "ARCH_EXT": "bp" }, + "rv64imafdcbp": { "CORE": "nx600fd", "ARCH_EXT": "bp" }, + "rv64imafcv": { "CORE": "nx600f", "ARCH_EXT": "v" }, + "rv64imafdcv": { "CORE": "nx600fd", "ARCH_EXT": "v" }, + "rv64imafcbv": { "CORE": "nx600f", "ARCH_EXT": "bv" }, + "rv64imafdcbv": { "CORE": "nx600fd", "ARCH_EXT": "bv" }, + "rv64imafcpv": { "CORE": "nx600f", "ARCH_EXT": "pv" }, + "rv64imafdcpv": { "CORE": "nx600fd", "ARCH_EXT": "pv" }, + "rv64imafcbpv": { "CORE": "nx600f", "ARCH_EXT": "bpv" }, + "rv64imafdcbpv": { "CORE": "nx600fd", "ARCH_EXT": "bpv" } } -} +} \ No newline at end of file diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index 7fbb4df1e..9187a9d9c 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -1,42 +1,61 @@ { "run_config": { - "target" : "xlspike", - "xlspike" : { + "target": "qemu", + "xlspike": { "timeout": 480 + }, + "qemu": { + "timeout": 240 } }, "parallel": "-j", "copy_objects": true, "build_target": "clean all", "build_config": { - "SOC": "xlspike", + "SOC": "demosoc", "DOWNLOAD": "ilm" }, "checks": { - "PASS": ["passed", "Passed", "SUCCESS"], + "PASS": ["passed", "Passed"], "FAIL": ["MEPC", "failed", "Failed", "FAILURE"] }, "appdirs": [ "NN/Examples/RISCV", - "NN/NN_Lib_Tests/nn_test" + "NN/Tests/Cases" ], "build_configs": { - "rv32imac": {"CORE": "n300", "ARCH_EXT":""}, - "rv32imafc": {"CORE": "n300f", "ARCH_EXT":""}, - "rv32imafdc": {"CORE": "n300fd", "ARCH_EXT":""}, - "rv32imacp": {"CORE": "n300", "ARCH_EXT":"p"}, - "rv32imafcp": {"CORE": "n300f", "ARCH_EXT":"p"}, - "rv32imafdcp": {"CORE": "n300fd", "ARCH_EXT":"p"}, - "rv64imac": {"CORE": "nx600", "ARCH_EXT":""}, - "rv64imafc": {"CORE": "nx600f", "ARCH_EXT":""}, - "rv64imafdc": {"CORE": "nx600fd", "ARCH_EXT":""}, - "rv64imacp": {"CORE": "nx600", "ARCH_EXT":"p"}, - "rv64imafcp": {"CORE": "nx600f", "ARCH_EXT":"p"}, - "rv64imafdcp": {"CORE": "nx600fd", "ARCH_EXT":"p"}, - "rv64imafcv": {"CORE": "nx600f", "ARCH_EXT":"v"}, - "rv64imafdcv": {"CORE": "nx600fd", "ARCH_EXT":"v"}, - "rv64imafcpv": {"CORE": "nx600f", "ARCH_EXT":"pv"}, - "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"} + "rv32imac": { "CORE": "n300", "ARCH_EXT": "" }, + "rv32imafc": { "CORE": "n300f", "ARCH_EXT": "" }, + "rv32imafdc": { "CORE": "n300fd", "ARCH_EXT": "" }, + "rv32imacb": { "CORE": "n300", "ARCH_EXT": "b" }, + "rv32imafcb": { "CORE": "n300f", "ARCH_EXT": "b" }, + "rv32imafdcb": { "CORE": "n300fd", "ARCH_EXT": "b" }, + "rv32imacp": { "CORE": "n300", "ARCH_EXT": "p" }, + "rv32imafcp": { "CORE": "n300f", "ARCH_EXT": "p" }, + "rv32imafdcp": { "CORE": "n300fd", "ARCH_EXT": "p" }, + "rv32imacbp": { "CORE": "n300", "ARCH_EXT": "bp" }, + "rv32imafcbp": { "CORE": "n300f", "ARCH_EXT": "bp" }, + "rv32imafdcbp": { "CORE": "n300fd", "ARCH_EXT": "bp" }, + "rv64imac": { "CORE": "nx600", "ARCH_EXT": "" }, + "rv64imafc": { "CORE": "nx600f", "ARCH_EXT": "" }, + "rv64imafdc": { "CORE": "nx600fd", "ARCH_EXT": "" }, + "rv64imacb": { "CORE": "nx600", "ARCH_EXT": "b" }, + "rv64imafcb": { "CORE": "nx600f", "ARCH_EXT": "b" }, + "rv64imafdcb": { "CORE": "nx600fd", "ARCH_EXT": "b" }, + "rv64imacp": { "CORE": "nx600", "ARCH_EXT": "p" }, + "rv64imafcp": { "CORE": "nx600f", "ARCH_EXT": "p" }, + "rv64imafdcp": { "CORE": "nx600fd", "ARCH_EXT": "p" }, + "rv64imacbp": { "CORE": "nx600", "ARCH_EXT": "bp" }, + "rv64imafcbp": { "CORE": "nx600f", "ARCH_EXT": "bp" }, + "rv64imafdcbp": { "CORE": "nx600fd", "ARCH_EXT": "bp" }, + "rv64imafcv": { "CORE": "nx600f", "ARCH_EXT": "v" }, + "rv64imafdcv": { "CORE": "nx600fd", "ARCH_EXT": "v" }, + "rv64imafcbv": { "CORE": "nx600f", "ARCH_EXT": "bv" }, + "rv64imafdcbv": { "CORE": "nx600fd", "ARCH_EXT": "bv" }, + "rv64imafcpv": { "CORE": "nx600f", "ARCH_EXT": "pv" }, + "rv64imafdcpv": { "CORE": "nx600fd", "ARCH_EXT": "pv" }, + "rv64imafcbpv": { "CORE": "nx600f", "ARCH_EXT": "bpv" }, + "rv64imafdcbpv": { "CORE": "nx600fd", "ARCH_EXT": "bpv" } }, "appconfig": { "NN/Examples/RISCV/cifar10": { @@ -50,4 +69,4 @@ } } } -} +} \ No newline at end of file diff --git a/NMSIS/doc/source/changelog.rst b/NMSIS/doc/source/changelog.rst index 2de4db5f3..e44403f97 100644 --- a/NMSIS/doc/source/changelog.rst +++ b/NMSIS/doc/source/changelog.rst @@ -3,6 +3,49 @@ Changelog ========= +V1.0.4 +------ + +This is the version ``V1.0.4`` release of Nuclei MCU Software Interface Standard(NMSIS). + +* **NMSIS-Core** + + - add ``__CCM_PRESENT`` macro in NMSIS-Core, if CCM hardware unit is present in your CPU, + ``__CCM_PRESENT`` macro need to be set to 1 in ``.h`` + - Fixed mtvec related api comment in ``core_feature_eclic.h`` + - Add safely write mtime/mtimecmp register for 32bit risc-v processor + - rearrage #include header files for all NMSIS Core header files + - removed some not good #pragma gcc diagnostic lines in ``nmsis_gcc.h`` + +* **NMSIS-DSP** + + - Add initial bitmainp extension support + - Fix bug in riscv_cmplx_mult_cmplx_q15 function when XLEN=64 + +* **NMSIS-NN** + + - Add initial bitmainp extension support + - Change riscv_maxpool_q7_HWC implementation for rvv + - Re-org NN_Lib_Tests to Tests + +* **Build System** + + - Change minimal version of cmake to 3.14 + - Add REBUILD=0 to reuse previous generated Makefile + +* **Device Tempates** + + - Fix bss section lma and vma not aligned and tbss space not reserved + +* **CI** + + - Change NMSIS to use Nuclei SDK demosoc as ci run target + - only run ci on master/develop branch + +* **Documentation** + + - Update get started guide for dsp/nn library + V1.0.3 ------ diff --git a/NMSIS/doc/source/conf.py b/NMSIS/doc/source/conf.py index a52fb36a7..7166c2e25 100644 --- a/NMSIS/doc/source/conf.py +++ b/NMSIS/doc/source/conf.py @@ -21,10 +21,10 @@ author = 'Nuclei' # The short X.Y version -version = '1.0.3' +version = '1.0.4' # The full version, including alpha/beta/rc tags -release = '1.0.3' +release = '1.0.4' # -- General configuration --------------------------------------------------- diff --git a/NMSIS/doc/source/dsp/get_started.rst b/NMSIS/doc/source/dsp/get_started.rst index 679ff7064..81024dd9d 100644 --- a/NMSIS/doc/source/dsp/get_started.rst +++ b/NMSIS/doc/source/dsp/get_started.rst @@ -8,10 +8,10 @@ Here we will describe how to run the nmsis dsp examples in Nuclei QEMU. Preparation ----------- -* Nuclei SDK, ``master`` branch(>= 0.3.5 release) -* Nuclei RISCV GNU Toolchain 2022.01 -* Nuclei QEMU 2022.01 -* CMake >= 3.5 +* Nuclei SDK, ``master`` branch(>= 0.3.7 release) +* Nuclei RISCV GNU Toolchain 2022.04 +* Nuclei QEMU 2022.04 +* CMake >= 3.14 * Python 3 Tool Setup @@ -73,12 +73,19 @@ How to run ---------- 1. Set environment variables ``NUCLEI_SDK_ROOT`` and ``NUCLEI_SDK_NMSIS``, - and set Nuclei SDK SoC to `demosoc` + and set Nuclei SDK SoC to `demosoc`, and change ilm/dlm size from 64K to 512K. .. code-block:: shell export NUCLEI_SDK_ROOT=/path/to/nuclei_sdk export NUCLEI_SDK_NMSIS=/path/to/NMSIS/NMSIS + # Setup SDK development environment + cd $NUCLEI_SDK_ROOT + source setup.sh + cd - + # !!!!Take Care!!!! + # change this link script will make compiled example can only run on bitstream which has 512K ILM/DLM + sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld export SOC=demosoc 2. Due to many of the examples could not be placed in 64K ILM and 64K DLM, and diff --git a/NMSIS/doc/source/nn/get_started.rst b/NMSIS/doc/source/nn/get_started.rst index 5e3bfbf9c..3ac93a064 100644 --- a/NMSIS/doc/source/nn/get_started.rst +++ b/NMSIS/doc/source/nn/get_started.rst @@ -8,10 +8,10 @@ Here we will describe how to run the nmsis nn examples in Nuclei QEMU. Preparation ----------- -* Nuclei SDK, ``master`` branch(>= 0.3.5 release) -* Nuclei RISCV GNU Toolchain 2022.01 -* Nuclei QEMU 2022.01 -* CMake >= 3.5 +* Nuclei SDK, ``master`` branch(>= 0.3.7 release) +* Nuclei RISCV GNU Toolchain 2022.04 +* Nuclei QEMU 2022.04 +* CMake >= 3.14 * Python 3 Tool Setup @@ -75,12 +75,19 @@ How to run ---------- 1. Set environment variables ``NUCLEI_SDK_ROOT`` and ``NUCLEI_SDK_NMSIS``, - and set Nuclei SDK SoC to `demosoc` + and set Nuclei SDK SoC to `demosoc`, and change ilm/dlm size from 64K to 512K. .. code-block:: shell export NUCLEI_SDK_ROOT=/path/to/nuclei_sdk export NUCLEI_SDK_NMSIS=/path/to/NMSIS/NMSIS + # Setup SDK development environment + cd $NUCLEI_SDK_ROOT + source setup.sh + cd - + # !!!!Take Care!!!! + # change this link script will make compiled example can only run on bitstream which has 512K ILM/DLM + sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld export SOC=demosoc 2. Due to many of the examples could not be placed in 64K ILM and 64K DLM, and @@ -105,7 +112,7 @@ How to run 3. Let us take ``cifar10`` for example, ``cd $NUCLEI_SDK_NMSIS/NN/Examples/RISCV/cifar10/`` to first -3. Run with RISCV DSP enabled and Vector enabled NMSIS-NN library for CORE ``nx900fd`` +4. Run with RISCV DSP enabled and Vector enabled NMSIS-NN library for CORE ``nx900fd`` .. code-block:: @@ -117,7 +124,7 @@ How to run make ARCH_EXT=pv CORE=nx900fd run_qemu -4. Run with RISCV DSP disabled and Vector disabled NMSIS-NN library for CORE ``nx900fd`` +5. Run with RISCV DSP disabled and Vector disabled NMSIS-NN library for CORE ``nx900fd`` .. code-block:: shell diff --git a/NMSIS/npk.yml b/NMSIS/npk.yml index bdd16aca6..4784fd87f 100644 --- a/NMSIS/npk.yml +++ b/NMSIS/npk.yml @@ -1,7 +1,7 @@ ## Package Base Information name: csp-nsdk_nmsis owner: nuclei -version: 1.0.3 +version: 1.0.4 description: NMSIS in Nuclei SDK type: csp keywords: @@ -20,10 +20,17 @@ configuration: description: RISC-V ARCH for NMSIS library value: >- [ "rv32imac", "rv32imafc", "rv32imafdc", + "rv32imacb", "rv32imafcb", "rv32imafdcb", "rv32imacp", "rv32imafcp", "rv32imafdcp", + "rv32imacbp", "rv32imafcbp", "rv32imafdcbp", "rv64imac", "rv64imafc", "rv64imafdc", + "rv64imacb", "rv64imafcb", "rv64imafdcb", "rv64imacp", "rv64imafcp", "rv64imafdcp", - "rv64imafcv", "rv64imafdcv", "rv64imafcpv", "rv64imafdcpv" ] + "rv64imacbp", "rv64imafcbp", "rv64imafdcbp", + "rv64imafcv", "rv64imafdcv", + "rv64imafcbv", "rv64imafdcbv", + "rv64imafcpv", "rv64imafdcpv", + "rv64imafcbpv", "rv64imafdcbpv" ] nmsislibsel: default_value: none type: choices