From 3de69ca706ac84b15d0e609201bffce9c80eaac0 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Tue, 11 Jan 2022 16:43:16 +0800 Subject: [PATCH 01/38] Scripts: add more b/p/v library and test combinations Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Build/nmsis_dsp.json | 67 ++++++++++++++++++++++++++++ NMSIS/Scripts/Build/nmsis_nn.json | 67 ++++++++++++++++++++++++++++ NMSIS/Scripts/Build/nmsis_nnref.json | 12 ++--- NMSIS/Scripts/Runner/nmsis_dsp.json | 18 +++++++- NMSIS/Scripts/Runner/nmsis_nn.json | 18 +++++++- 5 files changed, 174 insertions(+), 8 deletions(-) diff --git a/NMSIS/Scripts/Build/nmsis_dsp.json b/NMSIS/Scripts/Build/nmsis_dsp.json index 17101c713..ff10670c7 100644 --- a/NMSIS/Scripts/Build/nmsis_dsp.json +++ b/NMSIS/Scripts/Build/nmsis_dsp.json @@ -22,6 +22,18 @@ "RISCV_ARCH" : "rv32imafdc", "RISCV_ABI": "ilp32d" }, + "rv32imacb" : { + "RISCV_ARCH" : "rv32imacb", + "RISCV_ABI": "ilp32" + }, + "rv32imafcb" : { + "RISCV_ARCH" : "rv32imafcb", + "RISCV_ABI": "ilp32f" + }, + "rv32imafdcb" : { + "RISCV_ARCH" : "rv32imafdcb", + "RISCV_ABI": "ilp32d" + }, "rv32imacp" : { "RISCV_ARCH" : "rv32imacp", "RISCV_ABI": "ilp32", @@ -37,6 +49,21 @@ "RISCV_ABI": "ilp32d", "DSP64" : "ON" }, + "rv32imacbp" : { + "RISCV_ARCH" : "rv32imacbp", + "RISCV_ABI": "ilp32", + "DSP64" : "ON" + }, + "rv32imafcbp" : { + "RISCV_ARCH" : "rv32imafcbp", + "RISCV_ABI": "ilp32f", + "DSP64" : "ON" + }, + "rv32imafdcbp" : { + "RISCV_ARCH" : "rv32imafdcbp", + "RISCV_ABI": "ilp32d", + "DSP64" : "ON" + }, "rv64imac" : { "RISCV_ARCH" : "rv64imac", "RISCV_ABI": "lp64" @@ -49,6 +76,18 @@ "RISCV_ARCH" : "rv64imafdc", "RISCV_ABI": "lp64d" }, + "rv64imacb" : { + "RISCV_ARCH" : "rv64imacb", + "RISCV_ABI": "lp64" + }, + "rv64imafcb" : { + "RISCV_ARCH" : "rv64imafcb", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcb" : { + "RISCV_ARCH" : "rv64imafdcb", + "RISCV_ABI": "lp64d" + }, "rv64imacp" : { "RISCV_ARCH" : "rv64imacp", "RISCV_ABI": "lp64" @@ -61,6 +100,18 @@ "RISCV_ARCH" : "rv64imafdcp", "RISCV_ABI": "lp64d" }, + "rv64imafdcbp" : { + "RISCV_ARCH" : "rv64imafdcbp", + "RISCV_ABI": "lp64d" + }, + "rv64imacbp" : { + "RISCV_ARCH" : "rv64imacbp", + "RISCV_ABI": "lp64" + }, + "rv64imafcbp" : { + "RISCV_ARCH" : "rv64imafcbp", + "RISCV_ABI": "lp64f" + }, "rv64imafcv" : { "RISCV_ARCH" : "rv64imafcv", "RISCV_ABI": "lp64f" @@ -69,6 +120,14 @@ "RISCV_ARCH" : "rv64imafdcv", "RISCV_ABI": "lp64d" }, + "rv64imafcbv" : { + "RISCV_ARCH" : "rv64imafcbv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbv" : { + "RISCV_ARCH" : "rv64imafdcbv", + "RISCV_ABI": "lp64d" + }, "rv64imafcpv" : { "RISCV_ARCH" : "rv64imafcpv", "RISCV_ABI": "lp64f" @@ -76,6 +135,14 @@ "rv64imafdcpv" : { "RISCV_ARCH" : "rv64imafdcpv", "RISCV_ABI": "lp64d" + }, + "rv64imafcbpv" : { + "RISCV_ARCH" : "rv64imafcbpv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbpv" : { + "RISCV_ARCH" : "rv64imafdcbpv", + "RISCV_ABI": "lp64d" } } } diff --git a/NMSIS/Scripts/Build/nmsis_nn.json b/NMSIS/Scripts/Build/nmsis_nn.json index df96e49da..c63b45d91 100644 --- a/NMSIS/Scripts/Build/nmsis_nn.json +++ b/NMSIS/Scripts/Build/nmsis_nn.json @@ -22,6 +22,18 @@ "RISCV_ARCH" : "rv32imafdc", "RISCV_ABI": "ilp32d" }, + "rv32imacb" : { + "RISCV_ARCH" : "rv32imacb", + "RISCV_ABI": "ilp32" + }, + "rv32imafcb" : { + "RISCV_ARCH" : "rv32imafcb", + "RISCV_ABI": "ilp32f" + }, + "rv32imafdcb" : { + "RISCV_ARCH" : "rv32imafdcb", + "RISCV_ABI": "ilp32d" + }, "rv32imacp" : { "RISCV_ARCH" : "rv32imacp", "RISCV_ABI": "ilp32", @@ -37,6 +49,21 @@ "RISCV_ABI": "ilp32d", "DSP64" : "ON" }, + "rv32imacbp" : { + "RISCV_ARCH" : "rv32imacbp", + "RISCV_ABI": "ilp32", + "DSP64" : "ON" + }, + "rv32imafcbp" : { + "RISCV_ARCH" : "rv32imafcbp", + "RISCV_ABI": "ilp32f", + "DSP64" : "ON" + }, + "rv32imafdcbp" : { + "RISCV_ARCH" : "rv32imafdcbp", + "RISCV_ABI": "ilp32d", + "DSP64" : "ON" + }, "rv64imac" : { "RISCV_ARCH" : "rv64imac", "RISCV_ABI": "lp64" @@ -49,6 +76,18 @@ "RISCV_ARCH" : "rv64imafdc", "RISCV_ABI": "lp64d" }, + "rv64imacb" : { + "RISCV_ARCH" : "rv64imacb", + "RISCV_ABI": "lp64" + }, + "rv64imafcb" : { + "RISCV_ARCH" : "rv64imafcb", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcb" : { + "RISCV_ARCH" : "rv64imafdcb", + "RISCV_ABI": "lp64d" + }, "rv64imacp" : { "RISCV_ARCH" : "rv64imacp", "RISCV_ABI": "lp64" @@ -61,6 +100,18 @@ "RISCV_ARCH" : "rv64imafdcp", "RISCV_ABI": "lp64d" }, + "rv64imafdcbp" : { + "RISCV_ARCH" : "rv64imafdcbp", + "RISCV_ABI": "lp64d" + }, + "rv64imacbp" : { + "RISCV_ARCH" : "rv64imacbp", + "RISCV_ABI": "lp64" + }, + "rv64imafcbp" : { + "RISCV_ARCH" : "rv64imafcbp", + "RISCV_ABI": "lp64f" + }, "rv64imafcv" : { "RISCV_ARCH" : "rv64imafcv", "RISCV_ABI": "lp64f" @@ -69,6 +120,14 @@ "RISCV_ARCH" : "rv64imafdcv", "RISCV_ABI": "lp64d" }, + "rv64imafcbv" : { + "RISCV_ARCH" : "rv64imafcbv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbv" : { + "RISCV_ARCH" : "rv64imafdcbv", + "RISCV_ABI": "lp64d" + }, "rv64imafcpv" : { "RISCV_ARCH" : "rv64imafcpv", "RISCV_ABI": "lp64f" @@ -76,6 +135,14 @@ "rv64imafdcpv" : { "RISCV_ARCH" : "rv64imafdcpv", "RISCV_ABI": "lp64d" + }, + "rv64imafcbpv" : { + "RISCV_ARCH" : "rv64imafcbpv", + "RISCV_ABI": "lp64f" + }, + "rv64imafdcbpv" : { + "RISCV_ARCH" : "rv64imafdcbpv", + "RISCV_ABI": "lp64d" } } } diff --git a/NMSIS/Scripts/Build/nmsis_nnref.json b/NMSIS/Scripts/Build/nmsis_nnref.json index aa0838cd2..f29e2fd40 100644 --- a/NMSIS/Scripts/Build/nmsis_nnref.json +++ b/NMSIS/Scripts/Build/nmsis_nnref.json @@ -32,11 +32,11 @@ } }, "alias_target" : { - "rv32imac" : ["rv32imacp"], - "rv32imafc" : ["rv32imafcp"], - "rv32imafdc" : ["rv32imafdcp"], - "rv64imac" : ["rv64imacp"], - "rv64imafc" : ["rv64imafcp", "rv64imafcv", "rv64imafcpv"], - "rv64imafdc" : ["rv64imafdcp", "rv64imafdcv", "rv64imafdcpv"] + "rv32imac" : ["rv32imacp", "rv32imacb", "rv32imacbp"], + "rv32imafc" : ["rv32imafcp", "rv32imafcb", "rv32imafcbp"], + "rv32imafdc" : ["rv32imafdcp", "rv32imafdcb", "rv32imafdcbp"], + "rv64imac" : ["rv64imacp", "rv64imacb", "rv64imacbp"], + "rv64imafc" : ["rv64imafcb", "rv64imafcp", "rv64imafcv", "rv64imafcbp", "rv64imafcbv", "rv64imafcpv", "rv64imafcbpv"], + "rv64imafdc" : ["rv64imafdcb", "rv64imafdcp", "rv64imafdcv", "rv64imafdcbp", "rv64imafdcbv", "rv64imafdcpv", "rv64imafdcbpv"] } } diff --git a/NMSIS/Scripts/Runner/nmsis_dsp.json b/NMSIS/Scripts/Runner/nmsis_dsp.json index a3ad730fc..a2c74fcc4 100644 --- a/NMSIS/Scripts/Runner/nmsis_dsp.json +++ b/NMSIS/Scripts/Runner/nmsis_dsp.json @@ -24,18 +24,34 @@ "rv32imac": {"CORE": "n300", "ARCH_EXT":""}, "rv32imafc": {"CORE": "n300f", "ARCH_EXT":""}, "rv32imafdc": {"CORE": "n300fd", "ARCH_EXT":""}, + "rv32imacb": {"CORE": "n300", "ARCH_EXT":"b"}, + "rv32imafcb": {"CORE": "n300f", "ARCH_EXT":"b"}, + "rv32imafdcb": {"CORE": "n300fd", "ARCH_EXT":"b"}, "rv32imacp": {"CORE": "n300", "ARCH_EXT":"p"}, "rv32imafcp": {"CORE": "n300f", "ARCH_EXT":"p"}, "rv32imafdcp": {"CORE": "n300fd", "ARCH_EXT":"p"}, + "rv32imacbp": {"CORE": "n300", "ARCH_EXT":"bp"}, + "rv32imafcbp": {"CORE": "n300f", "ARCH_EXT":"bp"}, + "rv32imafdcbp": {"CORE": "n300fd", "ARCH_EXT":"bp"}, "rv64imac": {"CORE": "nx600", "ARCH_EXT":""}, "rv64imafc": {"CORE": "nx600f", "ARCH_EXT":""}, "rv64imafdc": {"CORE": "nx600fd", "ARCH_EXT":""}, + "rv64imacb": {"CORE": "nx600", "ARCH_EXT":"b"}, + "rv64imafcb": {"CORE": "nx600f", "ARCH_EXT":"b"}, + "rv64imafdcb": {"CORE": "nx600fd", "ARCH_EXT":"b"}, "rv64imacp": {"CORE": "nx600", "ARCH_EXT":"p"}, "rv64imafcp": {"CORE": "nx600f", "ARCH_EXT":"p"}, "rv64imafdcp": {"CORE": "nx600fd", "ARCH_EXT":"p"}, + "rv64imacbp": {"CORE": "nx600", "ARCH_EXT":"bp"}, + "rv64imafcbp": {"CORE": "nx600f", "ARCH_EXT":"bp"}, + "rv64imafdcbp": {"CORE": "nx600fd", "ARCH_EXT":"bp"}, "rv64imafcv": {"CORE": "nx600f", "ARCH_EXT":"v"}, "rv64imafdcv": {"CORE": "nx600fd", "ARCH_EXT":"v"}, + "rv64imafcbv": {"CORE": "nx600f", "ARCH_EXT":"bv"}, + "rv64imafdcbv": {"CORE": "nx600fd", "ARCH_EXT":"bv"}, "rv64imafcpv": {"CORE": "nx600f", "ARCH_EXT":"pv"}, - "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"} + "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"}, + "rv64imafcbpv": {"CORE": "nx600f", "ARCH_EXT":"bpv"}, + "rv64imafdcbpv": {"CORE": "nx600fd", "ARCH_EXT":"bpv"} } } diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index 7fbb4df1e..4ef306b4a 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -24,19 +24,35 @@ "rv32imac": {"CORE": "n300", "ARCH_EXT":""}, "rv32imafc": {"CORE": "n300f", "ARCH_EXT":""}, "rv32imafdc": {"CORE": "n300fd", "ARCH_EXT":""}, + "rv32imacb": {"CORE": "n300", "ARCH_EXT":"b"}, + "rv32imafcb": {"CORE": "n300f", "ARCH_EXT":"b"}, + "rv32imafdcb": {"CORE": "n300fd", "ARCH_EXT":"b"}, "rv32imacp": {"CORE": "n300", "ARCH_EXT":"p"}, "rv32imafcp": {"CORE": "n300f", "ARCH_EXT":"p"}, "rv32imafdcp": {"CORE": "n300fd", "ARCH_EXT":"p"}, + "rv32imacbp": {"CORE": "n300", "ARCH_EXT":"bp"}, + "rv32imafcbp": {"CORE": "n300f", "ARCH_EXT":"bp"}, + "rv32imafdcbp": {"CORE": "n300fd", "ARCH_EXT":"bp"}, "rv64imac": {"CORE": "nx600", "ARCH_EXT":""}, "rv64imafc": {"CORE": "nx600f", "ARCH_EXT":""}, "rv64imafdc": {"CORE": "nx600fd", "ARCH_EXT":""}, + "rv64imacb": {"CORE": "nx600", "ARCH_EXT":"b"}, + "rv64imafcb": {"CORE": "nx600f", "ARCH_EXT":"b"}, + "rv64imafdcb": {"CORE": "nx600fd", "ARCH_EXT":"b"}, "rv64imacp": {"CORE": "nx600", "ARCH_EXT":"p"}, "rv64imafcp": {"CORE": "nx600f", "ARCH_EXT":"p"}, "rv64imafdcp": {"CORE": "nx600fd", "ARCH_EXT":"p"}, + "rv64imacbp": {"CORE": "nx600", "ARCH_EXT":"bp"}, + "rv64imafcbp": {"CORE": "nx600f", "ARCH_EXT":"bp"}, + "rv64imafdcbp": {"CORE": "nx600fd", "ARCH_EXT":"bp"}, "rv64imafcv": {"CORE": "nx600f", "ARCH_EXT":"v"}, "rv64imafdcv": {"CORE": "nx600fd", "ARCH_EXT":"v"}, + "rv64imafcbv": {"CORE": "nx600f", "ARCH_EXT":"bv"}, + "rv64imafdcbv": {"CORE": "nx600fd", "ARCH_EXT":"bv"}, "rv64imafcpv": {"CORE": "nx600f", "ARCH_EXT":"pv"}, - "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"} + "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"}, + "rv64imafcbpv": {"CORE": "nx600f", "ARCH_EXT":"bpv"}, + "rv64imafdcbpv": {"CORE": "nx600fd", "ARCH_EXT":"bpv"} }, "appconfig": { "NN/Examples/RISCV/cifar10": { From 5824248cc5af7f0350dd8f41a985839d67e52df5 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 12 Jan 2022 17:50:13 +0800 Subject: [PATCH 02/38] ci: timeout 4h for dsp/nn test and interruptible Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index cd655167b..d32efb61f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -86,6 +86,8 @@ build_align_library: .test_job_template: &test_job_template_default stage: test + timeout: 4h + interruptible: true before_script: # prepare for docker ssh environment ## https://docs.gitlab.com/ee/ci/ssh_keys/#ssh-keys-when-using-the-docker-executor From 3a739e6c53138d3ef5e996eab460c3d56486d892 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 14:36:47 +0800 Subject: [PATCH 03/38] Core: update NMSIS Core changes from Nuclei SDK 0.3.6 Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Core/Include/core_compatiable.h | 2 + NMSIS/Core/Include/core_feature_base.h | 3 +- NMSIS/Core/Include/core_feature_bitmanip.h | 2 + NMSIS/Core/Include/core_feature_cache.h | 65 ++++++++++++---------- NMSIS/Core/Include/core_feature_dsp.h | 2 + NMSIS/Core/Include/core_feature_eclic.h | 14 ++++- NMSIS/Core/Include/core_feature_fpu.h | 2 + NMSIS/Core/Include/core_feature_pmp.h | 2 + NMSIS/Core/Include/core_feature_timer.h | 21 ++++++- NMSIS/Core/Include/core_feature_vector.h | 2 + NMSIS/Core/Include/nmsis_gcc.h | 8 +-- NMSIS/Core/Include/nmsis_version.h | 2 +- NMSIS/Core/Include/riscv_encoding.h | 4 +- 13 files changed, 87 insertions(+), 42 deletions(-) diff --git a/NMSIS/Core/Include/core_compatiable.h b/NMSIS/Core/Include/core_compatiable.h index 316a309fa..ee11d696c 100644 --- a/NMSIS/Core/Include/core_compatiable.h +++ b/NMSIS/Core/Include/core_compatiable.h @@ -25,6 +25,8 @@ extern "C" { #endif +#include "core_feature_base.h" + /* ===== ARM Compatiable Functions ===== */ /** * \defgroup NMSIS_Core_ARMCompatiable_Functions ARM Compatiable Functions diff --git a/NMSIS/Core/Include/core_feature_base.h b/NMSIS/Core/Include/core_feature_base.h index 8382f846a..8656848b4 100644 --- a/NMSIS/Core/Include/core_feature_base.h +++ b/NMSIS/Core/Include/core_feature_base.h @@ -23,12 +23,13 @@ * @brief Base core feature API for Nuclei N/NX Core */ #include -#include "riscv_encoding.h" #ifdef __cplusplus extern "C" { #endif +#include "nmsis_compiler.h" + /** * \defgroup NMSIS_Core_Registers Register Define and Type Definitions * \brief Type definitions and defines for core registers. diff --git a/NMSIS/Core/Include/core_feature_bitmanip.h b/NMSIS/Core/Include/core_feature_bitmanip.h index 40f692734..9c748259d 100644 --- a/NMSIS/Core/Include/core_feature_bitmanip.h +++ b/NMSIS/Core/Include/core_feature_bitmanip.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__BITMANIP_PRESENT) && (__BITMANIP_PRESENT == 1) /* ########################### CPU Bitmanipulation Intrinsic Functions ########################### */ diff --git a/NMSIS/Core/Include/core_feature_cache.h b/NMSIS/Core/Include/core_feature_cache.h index 6e9a66b99..987aed360 100644 --- a/NMSIS/Core/Include/core_feature_cache.h +++ b/NMSIS/Core/Include/core_feature_cache.h @@ -34,8 +34,10 @@ extern "C" { #endif -#if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)) \ - || (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)) +#include "core_feature_base.h" + + +#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) /* ########################## Cache functions #################################### */ /** @@ -191,6 +193,7 @@ __STATIC_FORCEINLINE void DisableICache(void) __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); } +#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) /** * \brief Get I-Cache Information * \details @@ -218,33 +221,6 @@ __STATIC_FORCEINLINE int32_t GetICacheInfo(CacheInfo_Type *info) return 0; } -/** - * \brief Get D-Cache Information - * \details - * This function get D-Cache Information - * \remarks - * - This function can be called in M-Mode only. - * - You can use this function in combination with cache lines operations - * \sa - * - \ref GetICacheInfo - */ -__STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info) -{ - if (info == NULL) { - return -1; - } - CSR_MDCFGINFO_Type csr_ccfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO); - info->setperway = (1 << csr_ccfg.b.set) << 3; - info->ways = (1 + csr_ccfg.b.way); - if (csr_ccfg.b.lsize == 0) { - info->linesize = 0; - } else { - info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3; - } - info->size = info->setperway * info->ways * info->linesize; - return 0; -} - /** * \brief Invalidate one I-Cache line specified by address in M-Mode * \details @@ -640,7 +616,7 @@ __STATIC_FORCEINLINE void UInvalICache(void) { __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL_ALL); } - +#endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */ /** @} */ /* End of Doxygen Group NMSIS_Core_ICache */ #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */ @@ -681,6 +657,34 @@ __STATIC_FORCEINLINE void DisableDCache(void) __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); } +#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) +/** + * \brief Get D-Cache Information + * \details + * This function get D-Cache Information + * \remarks + * - This function can be called in M-Mode only. + * - You can use this function in combination with cache lines operations + * \sa + * - \ref GetICacheInfo + */ +__STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info) +{ + if (info == NULL) { + return -1; + } + CSR_MDCFGINFO_Type csr_ccfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO); + info->setperway = (1 << csr_ccfg.b.set) << 3; + info->ways = (1 + csr_ccfg.b.way); + if (csr_ccfg.b.lsize == 0) { + info->linesize = 0; + } else { + info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3; + } + info->size = info->setperway * info->ways * info->linesize; + return 0; +} + /** * \brief Invalidate one D-Cache line specified by address in M-Mode * \details @@ -1384,6 +1388,7 @@ __STATIC_FORCEINLINE void UFlushInvalDCache(void) { __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL_ALL); } +#endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */ /** @} */ /* End of Doxygen Group NMSIS_Core_DCache */ #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */ diff --git a/NMSIS/Core/Include/core_feature_dsp.h b/NMSIS/Core/Include/core_feature_dsp.h index 9f361154c..6e9e16c95 100644 --- a/NMSIS/Core/Include/core_feature_dsp.h +++ b/NMSIS/Core/Include/core_feature_dsp.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #include diff --git a/NMSIS/Core/Include/core_feature_eclic.h b/NMSIS/Core/Include/core_feature_eclic.h index 296a4c639..7a45aa2c3 100644 --- a/NMSIS/Core/Include/core_feature_eclic.h +++ b/NMSIS/Core/Include/core_feature_eclic.h @@ -36,6 +36,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) /** * \defgroup NMSIS_Core_ECLIC_Registers Register Define and Type Definitions Of ECLIC @@ -712,10 +714,16 @@ __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) vec_base += ((unsigned long)IRQn) * sizeof(unsigned long); (* (unsigned long *) vec_base) = vector; #if (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)) +#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)) MFlushDCacheLine((unsigned long)vec_base); #endif +#endif #if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)) +#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)) MInvalICacheLine((unsigned long)vec_base); +#else + __FENCE_I(); +#endif #endif } @@ -748,7 +756,8 @@ __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) * This function set exception handler address to 'CSR_MTVEC'. * \param [in] addr Exception handler address * \remarks - * - This function use to set exception handler address to 'CSR_MTVEC'. Address is 4 bytes align. + * - This function use to set exception handler address to 'CSR_MTVEC'. + * Address need to be aligned to 64 bytes. * \sa * - \ref __get_exc_entry */ @@ -765,7 +774,8 @@ __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) * This function get exception handler address from 'CSR_MTVEC'. * \return Exception handler address * \remarks - * - This function use to get exception handler address from 'CSR_MTVEC'. Address is 4 bytes align + * - This function use to get exception handler address from 'CSR_MTVEC'. + * Address need to be aligned to 64 bytes. * \sa * - \ref __set_exc_entry */ diff --git a/NMSIS/Core/Include/core_feature_fpu.h b/NMSIS/Core/Include/core_feature_fpu.h index c9e13b79d..a4c68990c 100644 --- a/NMSIS/Core/Include/core_feature_fpu.h +++ b/NMSIS/Core/Include/core_feature_fpu.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + /* ===== FPU Operations ===== */ /** * \defgroup NMSIS_Core_FPU_Functions FPU Functions diff --git a/NMSIS/Core/Include/core_feature_pmp.h b/NMSIS/Core/Include/core_feature_pmp.h index 997dfaee1..8347af0d4 100644 --- a/NMSIS/Core/Include/core_feature_pmp.h +++ b/NMSIS/Core/Include/core_feature_pmp.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) /* ===== PMP Operations ===== */ /** diff --git a/NMSIS/Core/Include/core_feature_timer.h b/NMSIS/Core/Include/core_feature_timer.h index 0fb4f9e94..43e777e8d 100644 --- a/NMSIS/Core/Include/core_feature_timer.h +++ b/NMSIS/Core/Include/core_feature_timer.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) /** * \defgroup NMSIS_Core_SysTimer_Registers Register Define and Type Definitions Of System Timer @@ -114,7 +116,15 @@ typedef struct { */ __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) { +#if __RISCV_XLEN == 32 + void *addr; + addr = (void *)(&(SysTimer->MTIMER)); + __SW(addr, 0); // prevent carry + __SW(addr + 4, (uint32_t)(value >> 32)); + __SW(addr, (uint32_t)(value)); +#else SysTimer->MTIMER = value; +#endif } /** @@ -163,12 +173,21 @@ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) { unsigned long hartid = __RV_CSR_READ(CSR_MHARTID); if (hartid == 0) { +#if __RISCV_XLEN == 32 + void *addr; + addr = (void *)(&(SysTimer->MTIMERCMP)); + __SW(addr, -1U); // prevent load > timecmp + __SW(addr + 4, (uint32_t)(value >> 32)); + __SW(addr, (uint32_t)(value)); +#else SysTimer->MTIMERCMP = value; +#endif } else { void *addr = (void *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); #if __RISCV_XLEN == 32 - __SW(addr, (uint32_t)value); + __SW(addr, -1U); // prevent load > timecmp __SW(addr + 4, (uint32_t)(value >> 32)); + __SW(addr, (uint32_t)value); #else __SD(addr, value); #endif diff --git a/NMSIS/Core/Include/core_feature_vector.h b/NMSIS/Core/Include/core_feature_vector.h index e44d4c501..205b31474 100644 --- a/NMSIS/Core/Include/core_feature_vector.h +++ b/NMSIS/Core/Include/core_feature_vector.h @@ -32,6 +32,8 @@ extern "C" { #endif +#include "core_feature_base.h" + #if defined(__VECTOR_PRESENT) && (__VECTOR_PRESENT == 1) /* ########################### CPU Vector Intrinsic Functions ########################### */ diff --git a/NMSIS/Core/Include/nmsis_gcc.h b/NMSIS/Core/Include/nmsis_gcc.h index 9f7eb9d26..a92c37395 100644 --- a/NMSIS/Core/Include/nmsis_gcc.h +++ b/NMSIS/Core/Include/nmsis_gcc.h @@ -23,12 +23,13 @@ * @brief NMSIS compiler GCC header file */ #include -#include "riscv_encoding.h" #ifdef __cplusplus extern "C" { #endif +#include "riscv_encoding.h" + /* ######################### Startup and Lowlevel Init ######################## */ /** * \defgroup NMSIS_Core_CompilerControl Compiler Control @@ -42,11 +43,6 @@ * The header file nmsis_compiler.h is also included by each Device Header File so that these definitions are available. * @{ */ -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin diff --git a/NMSIS/Core/Include/nmsis_version.h b/NMSIS/Core/Include/nmsis_version.h index 0972cd7a1..dc43e8e0a 100644 --- a/NMSIS/Core/Include/nmsis_version.h +++ b/NMSIS/Core/Include/nmsis_version.h @@ -72,7 +72,7 @@ * The NMSIS patch version can be used to * show bug fixes in this package. **/ -#define __NMSIS_VERSION_PATCH (3U) +#define __NMSIS_VERSION_PATCH (4U) /** * \brief Represent the NMSIS Version * \details diff --git a/NMSIS/Core/Include/riscv_encoding.h b/NMSIS/Core/Include/riscv_encoding.h index cbf90a728..1e00e6db2 100644 --- a/NMSIS/Core/Include/riscv_encoding.h +++ b/NMSIS/Core/Include/riscv_encoding.h @@ -18,10 +18,12 @@ #ifndef __RISCV_ENCODING_H__ #define __RISCV_ENCODING_H__ -#include "riscv_bits.h" #ifdef __cplusplus extern "C" { #endif + +#include "riscv_bits.h" + /** * \defgroup NMSIS_Core_CSR_Encoding Core CSR Encodings * \ingroup NMSIS_Core From 749a49a8bca9c642423c6e9e21cd9c83a713cff1 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 14:37:11 +0800 Subject: [PATCH 04/38] env: change version to 0.1.4-dev Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/doc/source/changelog.rst | 15 +++++++++++++++ NMSIS/doc/source/conf.py | 4 ++-- NMSIS/npk.yml | 2 +- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/NMSIS/doc/source/changelog.rst b/NMSIS/doc/source/changelog.rst index eff7cfc75..6ff032170 100644 --- a/NMSIS/doc/source/changelog.rst +++ b/NMSIS/doc/source/changelog.rst @@ -3,6 +3,21 @@ Changelog ========= +V1.0.4-dev +---------- + +This is the version ``V1.0.4-dev`` release of Nuclei MCU Software Interface Standard(NMSIS), which is still in development. + +* **NMSIS-Core** + + - add ``__CCM_PRESENT`` macro in NMSIS-Core, if CCM hardware unit is present in your CPU, + ``__CCM_PRESENT`` macro need to be set to 1 in ``.h`` + - Fixed mtvec related api comment in ``core_feature_eclic.h`` + - Add safely write mtime/mtimecmp register for 32bit risc-v processor + - rearrage #include header files for all NMSIS Core header files + - removed some not good #pragma gcc diagnostic lines in ``nmsis_gcc.h`` + + V1.0.3 ------ diff --git a/NMSIS/doc/source/conf.py b/NMSIS/doc/source/conf.py index a52fb36a7..b46ee257a 100644 --- a/NMSIS/doc/source/conf.py +++ b/NMSIS/doc/source/conf.py @@ -21,10 +21,10 @@ author = 'Nuclei' # The short X.Y version -version = '1.0.3' +version = '1.0.4-dev' # The full version, including alpha/beta/rc tags -release = '1.0.3' +release = '1.0.4-dev' # -- General configuration --------------------------------------------------- diff --git a/NMSIS/npk.yml b/NMSIS/npk.yml index bdd16aca6..c5eef3fab 100644 --- a/NMSIS/npk.yml +++ b/NMSIS/npk.yml @@ -1,7 +1,7 @@ ## Package Base Information name: csp-nsdk_nmsis owner: nuclei -version: 1.0.3 +version: 1.0.4-dev description: NMSIS in Nuclei SDK type: csp keywords: From 803515b64a2813cb6cf05cb9309ae2a7d951e32a Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 15:59:52 +0800 Subject: [PATCH 05/38] DSP: add RISCV_MATH_BITMANIP when riscv b-ext is used Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/DSP/Include/riscv_math_types.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/NMSIS/DSP/Include/riscv_math_types.h b/NMSIS/DSP/Include/riscv_math_types.h index f7c04b2ea..11470441a 100755 --- a/NMSIS/DSP/Include/riscv_math_types.h +++ b/NMSIS/DSP/Include/riscv_math_types.h @@ -101,6 +101,11 @@ extern "C" #define RISCV_MATH_VECTOR 1 #endif +/* evaluate RISCV Bitmanip feature */ +#if (defined(__riscv_bitmainp)) + #define RISCV_MATH_BITMANIP 1 +#endif + #if defined ( __GNUC__ ) #define LOW_OPTIMIZATION_ENTER \ __attribute__(( optimize("-O1") )) From bc059d42a4ed7c33a884409715ff259fd7c05ccc Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 16:01:53 +0800 Subject: [PATCH 06/38] npk: add more libraries choices for NMSIS DSP/NN Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/npk.yml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/NMSIS/npk.yml b/NMSIS/npk.yml index c5eef3fab..796934809 100644 --- a/NMSIS/npk.yml +++ b/NMSIS/npk.yml @@ -20,10 +20,17 @@ configuration: description: RISC-V ARCH for NMSIS library value: >- [ "rv32imac", "rv32imafc", "rv32imafdc", + "rv32imacb", "rv32imafcb", "rv32imafdcb", "rv32imacp", "rv32imafcp", "rv32imafdcp", + "rv32imacbp", "rv32imafcbp", "rv32imafdcbp", "rv64imac", "rv64imafc", "rv64imafdc", + "rv64imacb", "rv64imafcb", "rv64imafdcb", "rv64imacp", "rv64imafcp", "rv64imafdcp", - "rv64imafcv", "rv64imafdcv", "rv64imafcpv", "rv64imafdcpv" ] + "rv64imacbp", "rv64imafcbp", "rv64imafdcbp", + "rv64imafcv", "rv64imafdcv", + "rv64imafcbv", "rv64imafdcbv", + "rv64imafcpv", "rv64imafdcpv", + "rv64imafcbpv", "rv64imafdcbpv" ] nmsislibsel: default_value: none type: choices From 9efdcaf5bfc4bbf3d6d1d4b8ac8a1e5aaa2271c0 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 16:34:16 +0800 Subject: [PATCH 07/38] ci: change NMSIS to use Nuclei SDK demosoc as ci run target Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 12 ++++++++---- NMSIS/Scripts/Runner/nmsis_dsp.json | 7 +++++-- NMSIS/Scripts/Runner/nmsis_nn.json | 7 +++++-- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d32efb61f..da9bb3651 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,7 @@ variables: NUCLEI_SDK: git@gito:software/library/nuclei-sdk.git - SDK_BRANCH: dev_xlspike_next - SOC: xlspike + SDK_BRANCH: master + SOC: demosoc RUNTARGET: qemu IMAGE: rego.corp.nucleisys.com/software/sdkbuild IMAGE_TAG: latest @@ -118,12 +118,14 @@ test_nn_library: - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs + # change ilm/dlm size from 64K to 512K for demosoc + - sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld - mkdir $NMSIS_LOGS - source NMSIS/env.sh - export SILENT=1 - cd NMSIS - make gen_nnref_lib - - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_nn.json --logdir $NMSIS_LOGS/nmsis_nn --parallel=-j --run_target $RUNTARGET --run + - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_nn.json --logdir $NMSIS_LOGS/nmsis_nn --parallel=-j --make_options "SIMU=$RUNTARGET" --run_target $RUNTARGET --run test_dsp_library: <<: *test_job_template_default @@ -138,11 +140,13 @@ test_dsp_library: - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs + # change ilm/dlm size from 64K to 512K for demosoc + - sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld - mkdir $NMSIS_LOGS - source NMSIS/env.sh - export SILENT=1 - cd NMSIS - - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_dsp.json --logdir $NMSIS_LOGS/nmsis_dsp --parallel=-j --run_target $RUNTARGET --run + - python3 $NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_bench.py --appcfg Scripts/Runner/nmsis_dsp.json --logdir $NMSIS_LOGS/nmsis_dsp --parallel=-j --make_options "SIMU=$RUNTARGET" --run_target $RUNTARGET --run release_benchmark: stage: release diff --git a/NMSIS/Scripts/Runner/nmsis_dsp.json b/NMSIS/Scripts/Runner/nmsis_dsp.json index a2c74fcc4..f415535b5 100644 --- a/NMSIS/Scripts/Runner/nmsis_dsp.json +++ b/NMSIS/Scripts/Runner/nmsis_dsp.json @@ -1,15 +1,18 @@ { "run_config": { - "target" : "xlspike", + "target" : "qemu", "xlspike" : { "timeout": 480 + }, + "qemu" : { + "timeout": 240 } }, "parallel": "-j", "copy_objects": true, "build_target": "clean all", "build_config": { - "SOC": "xlspike", + "SOC": "demosoc", "DOWNLOAD": "ilm" }, "checks": { diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index 4ef306b4a..2fcb74b7f 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -1,15 +1,18 @@ { "run_config": { - "target" : "xlspike", + "target" : "qemu", "xlspike" : { "timeout": 480 + }, + "qemu" : { + "timeout": 240 } }, "parallel": "-j", "copy_objects": true, "build_target": "clean all", "build_config": { - "SOC": "xlspike", + "SOC": "demosoc", "DOWNLOAD": "ilm" }, "checks": { From 6c817059cb739aaf3198870c0ccfbdba94c1055c Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 16:51:23 +0800 Subject: [PATCH 08/38] ci: only run ci on master/develop branch Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index da9bb3651..85136f036 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -21,6 +21,9 @@ build_doc: stage: build retry: 1 only: + refs: + - master + - develop changes: - NMSIS/doc/source/**/**/**/* - .gitlab-ci.yml @@ -49,6 +52,10 @@ build_doc: build_library: stage: build retry: 1 + only: + refs: + - master + - develop artifacts: when: always name: "nmsis_library-${CI_COMMIT_SHA::8}" @@ -69,6 +76,10 @@ build_library: build_align_library: stage: build retry: 1 + only: + refs: + - master + - develop artifacts: when: always name: "nmsis_align_library-${CI_COMMIT_SHA::8}" @@ -88,6 +99,10 @@ build_align_library: stage: test timeout: 4h interruptible: true + only: + refs: + - master + - develop before_script: # prepare for docker ssh environment ## https://docs.gitlab.com/ee/ci/ssh_keys/#ssh-keys-when-using-the-docker-executor @@ -150,6 +165,10 @@ test_dsp_library: release_benchmark: stage: release + only: + refs: + - master + - develop artifacts: name: "nmsis_test_log-${CI_COMMIT_SHA::8}" paths: From b51bf31667e200b3a45746a963ce9923bfa5bac2 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 18:05:19 +0800 Subject: [PATCH 09/38] ci: DSP/Test/TransformFunction/dct4 and DSP/Examples/RISCV/riscv_linear_interp_example need more than 512K Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 85136f036..d40a83c4d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -133,8 +133,8 @@ test_nn_library: - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs - # change ilm/dlm size from 64K to 512K for demosoc - - sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld + # change ilm/dlm size from 64K to 1M for demosoc + - sed -i "s/64K/1M/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld - mkdir $NMSIS_LOGS - source NMSIS/env.sh - export SILENT=1 @@ -155,8 +155,8 @@ test_dsp_library: - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs - # change ilm/dlm size from 64K to 512K for demosoc - - sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld + # change ilm/dlm size from 64K to 1M for demosoc + - sed -i "s/64K/1M/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld - mkdir $NMSIS_LOGS - source NMSIS/env.sh - export SILENT=1 From ccae31694c9255fcf475e23a0a158f77985c473a Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 28 Feb 2022 18:29:02 +0800 Subject: [PATCH 10/38] NN: re-org NN_Lib_Tests to Tests Signed-off-by: Huaqi Fang <578567190@qq.com> --- .../Makefile => Tests/Cases/Makefile.common} | 2 +- .../nn_test => Tests/Cases}/bench.h | 0 NMSIS/NN/Tests/Cases/full/Makefile | 3 +++ .../Cases/full}/riscv_nnexamples_nn_test.cpp | 0 .../Cases/full}/riscv_nnexamples_nn_test.h | 0 .../nn_test => Tests/Cases}/setup.sh | 0 NMSIS/NN/{NN_Lib_Tests => Tests}/Makefile | 2 +- .../nn_test => Tests/Ref}/CMakeLists.txt | 6 +++--- .../ActivationFunctions/CMakeLists.txt | 0 .../riscv_nn_activations_q15_ref.c | 0 .../riscv_nn_activations_q7_ref.c | 0 .../ActivationFunctions/riscv_relu6_s8_ref.c | 0 .../ActivationFunctions/riscv_relu_q15_ref.c | 0 .../ActivationFunctions/riscv_relu_q7_ref.c | 0 .../Source}/BasicMathFunctions/CMakeLists.txt | 0 .../riscv_elementwise_add_s8_ref.c | 0 .../riscv_elementwise_mul_s8_ref.c | 0 .../Ref/Source}/CMakeLists.txt | 20 +++++++++---------- .../ConcatenationFunctions/CMakeLists.txt | 0 .../riscv_concatenation_s8_w_ref.c | 0 .../riscv_concatenation_s8_x_ref.c | 0 .../riscv_concatenation_s8_y_ref.c | 0 .../riscv_concatenation_s8_z_ref.c | 0 .../ConvolutionFunctions/CMakeLists.txt | 0 .../riscv_convolve_1_x_n_s8_ref.c | 0 ...v_convolve_1x1_HWC_q7_fast_nonsquare_ref.c | 0 .../riscv_convolve_1x1_s8_fast_ref.c | 0 .../riscv_convolve_HWC_q15_basic_ref.c | 0 ...iscv_convolve_HWC_q15_fast_nonsquare_ref.c | 0 .../riscv_convolve_HWC_q15_fast_ref.c | 0 .../riscv_convolve_HWC_q7_RGB_ref.c | 0 ...iscv_convolve_HWC_q7_basic_nonsquare_ref.c | 0 .../riscv_convolve_HWC_q7_basic_ref.c | 0 ...riscv_convolve_HWC_q7_fast_nonsquare_ref.c | 0 .../riscv_convolve_HWC_q7_fast_ref.c | 0 .../riscv_convolve_s8_ref.c | 0 .../riscv_convolve_wrapper_s8_ref.c | 0 .../riscv_depthwise_conv_3x3_s8_ref.c | 0 .../riscv_depthwise_conv_s8_opt_ref.c | 0 .../riscv_depthwise_conv_s8_ref.c | 0 .../riscv_depthwise_conv_u8_basic_ver1_ref.c | 0 .../riscv_depthwise_conv_wrapper_s8_ref.c | 0 ...wise_separable_conv_HWC_q7_nonsquare_ref.c | 0 ...iscv_depthwise_separable_conv_HWC_q7_ref.c | 0 .../riscv_nn_depthwise_conv_s8_core_ref.c | 0 .../riscv_nn_mat_mult_kernel_q7_q15_ref.c | 0 ..._nn_mat_mult_kernel_q7_q15_reordered_ref.c | 0 ...iscv_nn_mat_mult_kernel_q7_reordered_ref.c | 0 .../riscv_nn_mat_mult_kernel_s8_s16_ref.c | 0 ..._nn_mat_mult_kernel_s8_s16_reordered_ref.c | 0 .../riscv_nn_mat_mult_s8_ref.c | 0 .../FullyConnectedFunctions/CMakeLists.txt | 0 ...v_fully_connected_mat_q7_vec_q15_opt_ref.c | 0 ...riscv_fully_connected_mat_q7_vec_q15_ref.c | 0 .../riscv_fully_connected_q15_opt_ref.c | 0 .../riscv_fully_connected_q15_ref.c | 0 .../riscv_fully_connected_q7_opt_ref.c | 0 .../riscv_fully_connected_q7_ref.c | 0 .../riscv_fully_connected_s8_ref.c | 0 .../Source}/NNSupportFunctions/CMakeLists.txt | 0 .../riscv_nn_accumulate_q7_to_q15_ref.c | 0 .../NNSupportFunctions/riscv_nn_add_q7_ref.c | 0 ...scv_nn_depthwise_conv_nt_t_padded_s8_ref.c | 0 .../riscv_nn_depthwise_conv_nt_t_s8_ref.c | 0 .../riscv_nn_mat_mul_core_1x_s8_ref.c | 0 .../riscv_nn_mat_mul_core_4x_s8_ref.c | 0 .../riscv_nn_mat_mult_nt_t_s8_ref.c | 0 .../riscv_nn_mult_q15_ref.c | 0 .../NNSupportFunctions/riscv_nn_mult_q7_ref.c | 0 .../riscv_nn_vec_mat_mult_t_s8_ref.c | 0 .../riscv_nn_vec_mat_mult_t_svdf_s8.c | 0 .../NNSupportFunctions/riscv_nntables.c | 0 .../riscv_q7_to_q15_no_shift_ref.c | 0 .../riscv_q7_to_q15_reordered_no_shift_ref.c | 0 ...iscv_q7_to_q15_reordered_with_offset_ref.c | 0 .../riscv_q7_to_q15_with_offset_ref.c | 0 .../riscv_q7_to_q7_no_shift_ref.c | 0 .../riscv_q7_to_q7_reordered_no_shift_ref.c | 0 .../Source}/PoolingFunctions/CMakeLists.txt | 0 .../PoolingFunctions/riscv_avgpool_s8_ref.c | 0 .../PoolingFunctions/riscv_max_pool_s8_ref.c | 0 .../PoolingFunctions/riscv_pool_q7_HWC_ref.c | 0 .../Source}/ReshapeFunctions/CMakeLists.txt | 0 .../ReshapeFunctions/riscv_reshape_s8_ref.c | 0 .../Ref/Source}/SVDFunctions/CMakeLists.txt | 0 .../Ref/Source}/SVDFunctions/riscv_svdf_s8.c | 0 .../Source}/SoftmaxFunctions/CMakeLists.txt | 0 .../SoftmaxFunctions/riscv_softmax_q15_ref.c | 0 .../SoftmaxFunctions/riscv_softmax_q7_ref.c | 0 .../SoftmaxFunctions/riscv_softmax_s8_ref.c | 0 .../SoftmaxFunctions/riscv_softmax_u8_ref.c | 0 .../riscv_softmax_with_batch_q7_ref.c | 0 .../Source}/fully_connected_testing_weights.h | 0 .../Ref/Source}/ref_functions.h | 0 .../Ref/Source}/riscv_convolve_HWC_q15_ref.c | 0 .../riscv_convolve_HWC_q15_ref_nonsquare.c | 0 .../Ref/Source}/riscv_convolve_HWC_q7_ref.c | 0 .../riscv_convolve_HWC_q7_ref_nonsquare.c | 0 ...iscv_depthwise_separable_conv_HWC_q7_ref.c | 0 ...wise_separable_conv_HWC_q7_ref_nonsquare.c | 0 ...v_fully_connected_mat_q7_vec_q15_opt_ref.c | 0 ...riscv_fully_connected_mat_q7_vec_q15_ref.c | 0 .../riscv_fully_connected_q15_opt_ref.c | 0 .../Source}/riscv_fully_connected_q15_ref.c | 0 .../riscv_fully_connected_q7_opt_ref.c | 0 .../Source}/riscv_fully_connected_q7_ref.c | 0 .../Ref/Source}/riscv_nn_mult_ref.c | 0 .../Ref/Source}/riscv_pool_ref.c | 0 .../Ref/Source}/riscv_relu_ref.c | 0 109 files changed, 18 insertions(+), 15 deletions(-) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Makefile => Tests/Cases/Makefile.common} (89%) rename NMSIS/NN/{NN_Lib_Tests/nn_test => Tests/Cases}/bench.h (100%) create mode 100644 NMSIS/NN/Tests/Cases/full/Makefile rename NMSIS/NN/{NN_Lib_Tests/nn_test => Tests/Cases/full}/riscv_nnexamples_nn_test.cpp (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test => Tests/Cases/full}/riscv_nnexamples_nn_test.h (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test => Tests/Cases}/setup.sh (100%) rename NMSIS/NN/{NN_Lib_Tests => Tests}/Makefile (99%) rename NMSIS/NN/{NN_Lib_Tests/nn_test => Tests/Ref}/CMakeLists.txt (84%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ActivationFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ActivationFunctions/riscv_nn_activations_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ActivationFunctions/riscv_nn_activations_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ActivationFunctions/riscv_relu6_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ActivationFunctions/riscv_relu_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ActivationFunctions/riscv_relu_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/BasicMathFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/BasicMathFunctions/riscv_elementwise_add_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/CMakeLists.txt (61%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConcatenationFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_reordered_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_reordered_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_reordered_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ConvolutionFunctions/riscv_nn_mat_mult_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/riscv_fully_connected_q15_opt_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/riscv_fully_connected_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/riscv_fully_connected_q7_opt_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/riscv_fully_connected_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/FullyConnectedFunctions/riscv_fully_connected_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_accumulate_q7_to_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_add_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_padded_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_mat_mul_core_1x_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_mat_mul_core_4x_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_mat_mult_nt_t_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_mult_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_mult_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_vec_mat_mult_t_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nn_vec_mat_mult_t_svdf_s8.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_nntables.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_q7_to_q15_no_shift_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_q7_to_q15_reordered_no_shift_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_q7_to_q15_reordered_with_offset_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_q7_to_q15_with_offset_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_q7_to_q7_no_shift_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/NNSupportFunctions/riscv_q7_to_q7_reordered_no_shift_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/PoolingFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/PoolingFunctions/riscv_avgpool_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/PoolingFunctions/riscv_max_pool_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/PoolingFunctions/riscv_pool_q7_HWC_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ReshapeFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ReshapeFunctions/riscv_reshape_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SVDFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SVDFunctions/riscv_svdf_s8.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SoftmaxFunctions/CMakeLists.txt (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SoftmaxFunctions/riscv_softmax_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SoftmaxFunctions/riscv_softmax_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SoftmaxFunctions/riscv_softmax_s8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SoftmaxFunctions/riscv_softmax_u8_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/fully_connected_testing_weights.h (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/ref_functions.h (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_convolve_HWC_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_convolve_HWC_q15_ref_nonsquare.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_convolve_HWC_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_convolve_HWC_q7_ref_nonsquare.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_depthwise_separable_conv_HWC_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_fully_connected_mat_q7_vec_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_fully_connected_q15_opt_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_fully_connected_q15_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_fully_connected_q7_opt_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_fully_connected_q7_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_nn_mult_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_pool_ref.c (100%) rename NMSIS/NN/{NN_Lib_Tests/nn_test/Ref_Implementations => Tests/Ref/Source}/riscv_relu_ref.c (100%) diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Makefile b/NMSIS/NN/Tests/Cases/Makefile.common similarity index 89% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Makefile rename to NMSIS/NN/Tests/Cases/Makefile.common index 3601363b1..bf86c1d19 100644 --- a/NMSIS/NN/NN_Lib_Tests/nn_test/Makefile +++ b/NMSIS/NN/Tests/Cases/Makefile.common @@ -5,7 +5,7 @@ NUCLEI_SDK_NMSIS ?= $(NUCLEI_SDK_ROOT)/NMSIS SRCDIRS = . -INCDIRS = . $(NUCLEI_SDK_NMSIS)/NN/NN_Lib_Tests/nn_test/Ref_Implementations +INCDIRS = . .. $(NUCLEI_SDK_NMSIS)/NN/Tests/Ref/Source LIBDIRS = $(NUCLEI_SDK_NMSIS)/Library/NNREF/GCC diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/bench.h b/NMSIS/NN/Tests/Cases/bench.h similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/bench.h rename to NMSIS/NN/Tests/Cases/bench.h diff --git a/NMSIS/NN/Tests/Cases/full/Makefile b/NMSIS/NN/Tests/Cases/full/Makefile new file mode 100644 index 000000000..ab3546b88 --- /dev/null +++ b/NMSIS/NN/Tests/Cases/full/Makefile @@ -0,0 +1,3 @@ +BUILD_ROOT_DIR = ../ + +include $(BUILD_ROOT_DIR)/Makefile.common diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/riscv_nnexamples_nn_test.cpp b/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/riscv_nnexamples_nn_test.cpp rename to NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/riscv_nnexamples_nn_test.h b/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.h similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/riscv_nnexamples_nn_test.h rename to NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.h diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/setup.sh b/NMSIS/NN/Tests/Cases/setup.sh similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/setup.sh rename to NMSIS/NN/Tests/Cases/setup.sh diff --git a/NMSIS/NN/NN_Lib_Tests/Makefile b/NMSIS/NN/Tests/Makefile similarity index 99% rename from NMSIS/NN/NN_Lib_Tests/Makefile rename to NMSIS/NN/Tests/Makefile index f32fc04d4..51d15b915 100644 --- a/NMSIS/NN/NN_Lib_Tests/Makefile +++ b/NMSIS/NN/Tests/Makefile @@ -23,7 +23,7 @@ RISCV_MODEL ?= medany RISCV_ARCH_DEFINE = -DRISCV_ARCH=$(RISCV_ARCH) -DRISCV_ABI=$(RISCV_ABI) -DRISCV_MODEL=$(RISCV_MODEL) -TARGET_CMAKE_ROOT=nn_test +TARGET_CMAKE_ROOT=Ref TARGET_CMAKE_BUILD=$(TARGET_CMAKE_ROOT)/$(BUILD) TARGET_CMAKEFILE=$(TARGET_CMAKE_ROOT)/CMakeLists.txt TARGET_LIB_ROOT = $(LIBIRAY_ROOT)/$(TARGET)/$(TOOLCHAIN) diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/CMakeLists.txt b/NMSIS/NN/Tests/Ref/CMakeLists.txt similarity index 84% rename from NMSIS/NN/NN_Lib_Tests/nn_test/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/CMakeLists.txt index e0502243a..f80fbd461 100644 --- a/NMSIS/NN/NN_Lib_Tests/nn_test/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/CMakeLists.txt @@ -26,7 +26,7 @@ add_definitions(-g) SET(NN ${ROOT}/NN) SET(DSP ${ROOT}/DSP) SET(CORE ${ROOT}/Core) -SET(REF_NN ${NN}/NN_Lib_Tests/nn_test) +SET(REF_NN ${NN}/Tests/Ref) INCLUDE_DIRECTORIES(${CORE}/Include) @@ -34,8 +34,8 @@ list(APPEND CMAKE_MODULE_PATH ${REF_NN}) add_library(REF_NN INTERFACE) -add_subdirectory(Ref_Implementations) +add_subdirectory(Source) target_link_libraries(REF_NN INTERFACE REF_NN_IMP) ### Includes -target_include_directories(REF_NN INTERFACE "${REF_ROOT}/Ref_Implementations") +target_include_directories(REF_NN INTERFACE "${REF_NN}/Source") diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/CMakeLists.txt similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/ActivationFunctions/CMakeLists.txt diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q15_ref.c b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_nn_activations_q15_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q15_ref.c rename to NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_nn_activations_q15_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_nn_activations_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_nn_activations_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_relu6_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_relu6_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_relu6_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_relu6_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_relu_q15_ref.c b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_relu_q15_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_relu_q15_ref.c rename to NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_relu_q15_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_relu_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_relu_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ActivationFunctions/riscv_relu_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/ActivationFunctions/riscv_relu_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/BasicMathFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/CMakeLists.txt similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/BasicMathFunctions/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/CMakeLists.txt diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/BasicMathFunctions/riscv_elementwise_add_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/riscv_elementwise_add_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/BasicMathFunctions/riscv_elementwise_add_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/riscv_elementwise_add_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/CMakeLists.txt similarity index 61% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/CMakeLists.txt index 8043128a6..2d593573c 100644 --- a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/CMakeLists.txt @@ -14,19 +14,19 @@ file(GLOB SRC_ReshapeFunctions "ReshapeFunctions/*_*.c") file(GLOB SRC_SoftmaxFunctions "SoftmaxFunctions/*_*.c") file(GLOB SRC_SVDFunctions "SVDFunctions/*_*.c") -add_library(REF_NN_IMP STATIC ${SRC} - ${SRC_ActivationFunctions} - ${SRC_BasicMathFunctions} - ${SRC_ConcatenationFunctions} - ${SRC_ConvolutionFunctions} - ${SRC_FullyConnectedFunctions} - ${SRC_NNSupportFunctions} - ${SRC_PoolingFunctions} - ${SRC_ReshapeFunctions} +add_library(REF_NN_IMP STATIC ${SRC} + ${SRC_ActivationFunctions} + ${SRC_BasicMathFunctions} + ${SRC_ConcatenationFunctions} + ${SRC_ConvolutionFunctions} + ${SRC_FullyConnectedFunctions} + ${SRC_NNSupportFunctions} + ${SRC_PoolingFunctions} + ${SRC_ReshapeFunctions} ${SRC_SoftmaxFunctions} ${SRC_SVDFunctions}) ### Includes -target_include_directories(REF_NN_IMP PUBLIC "${REF_NN}/Ref_Implementations") +target_include_directories(REF_NN_IMP PUBLIC "${REF_NN}/Source") target_include_directories(REF_NN_IMP PUBLIC "${NN}/Include") target_include_directories(REF_NN_IMP PUBLIC "${DSP}/Include") diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/CMakeLists.txt similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/CMakeLists.txt diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c b/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c b/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c b/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c b/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/CMakeLists.txt similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/CMakeLists.txt diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c rename to NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_ref.c b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_ref.c 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from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ReshapeFunctions/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/CMakeLists.txt diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ReshapeFunctions/riscv_reshape_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/riscv_reshape_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ReshapeFunctions/riscv_reshape_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/riscv_reshape_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SVDFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/SVDFunctions/CMakeLists.txt similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SVDFunctions/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/SVDFunctions/CMakeLists.txt diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SVDFunctions/riscv_svdf_s8.c b/NMSIS/NN/Tests/Ref/Source/SVDFunctions/riscv_svdf_s8.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SVDFunctions/riscv_svdf_s8.c rename to NMSIS/NN/Tests/Ref/Source/SVDFunctions/riscv_svdf_s8.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/CMakeLists.txt similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/CMakeLists.txt rename to NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/CMakeLists.txt diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q15_ref.c b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_q15_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q15_ref.c rename to NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_q15_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_s8_ref.c b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_s8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_s8_ref.c rename to NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_s8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_u8_ref.c b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_u8_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_u8_ref.c rename to NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_u8_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h b/NMSIS/NN/Tests/Ref/Source/fully_connected_testing_weights.h similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h rename to NMSIS/NN/Tests/Ref/Source/fully_connected_testing_weights.h diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h b/NMSIS/NN/Tests/Ref/Source/ref_functions.h similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h rename to NMSIS/NN/Tests/Ref/Source/ref_functions.h diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q15_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q15_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q15_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q15_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q15_ref_nonsquare.c b/NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q15_ref_nonsquare.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q15_ref_nonsquare.c rename to NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q15_ref_nonsquare.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q7_ref_nonsquare.c b/NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q7_ref_nonsquare.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_convolve_HWC_q7_ref_nonsquare.c rename to NMSIS/NN/Tests/Ref/Source/riscv_convolve_HWC_q7_ref_nonsquare.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_depthwise_separable_conv_HWC_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_depthwise_separable_conv_HWC_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c b/NMSIS/NN/Tests/Ref/Source/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c rename to NMSIS/NN/Tests/Ref/Source/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_mat_q7_vec_q15_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_mat_q7_vec_q15_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q15_opt_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q15_opt_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q15_opt_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q15_opt_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q15_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q15_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q15_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q15_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q7_opt_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q7_opt_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q7_opt_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q7_opt_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q7_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q7_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_fully_connected_q7_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_fully_connected_q7_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_nn_mult_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_nn_mult_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_nn_mult_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_nn_mult_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_pool_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_pool_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_pool_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_pool_ref.c diff --git a/NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_relu_ref.c b/NMSIS/NN/Tests/Ref/Source/riscv_relu_ref.c similarity index 100% rename from NMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/riscv_relu_ref.c rename to NMSIS/NN/Tests/Ref/Source/riscv_relu_ref.c From e93e6b31a57ca9bb911fca1b28d6fb22438cbf6e Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Tue, 1 Mar 2022 09:50:47 +0800 Subject: [PATCH 11/38] env: sync env files for NN test cases Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Build/Makefile.nmsis | 2 +- NMSIS/Scripts/Runner/nmsis_nn.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/NMSIS/Scripts/Build/Makefile.nmsis b/NMSIS/Scripts/Build/Makefile.nmsis index 06dc120ae..efb09ebf9 100644 --- a/NMSIS/Scripts/Build/Makefile.nmsis +++ b/NMSIS/Scripts/Build/Makefile.nmsis @@ -37,7 +37,7 @@ gen_nn_lib: gen_nnref_lib: @echo "Generated NN Reference library for configuration file $(NNREF_JSON_CONFIG)" - ./Scripts/Build/nlbuild.py --config $(NNREF_JSON_CONFIG) --lib_src NN/NN_Lib_Tests/nn_test \ + ./Scripts/Build/nlbuild.py --config $(NNREF_JSON_CONFIG) --lib_src NN/Tests/Ref \ --lib_prefix nmsis_nnref --lib_root $(LIBIRAY_ROOT)/NNREF/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) \ --parallel="$(PARALLEL_OPTS)" diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index 2fcb74b7f..6d960ef08 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -21,7 +21,7 @@ }, "appdirs": [ "NN/Examples/RISCV", - "NN/NN_Lib_Tests/nn_test" + "NN/Tests/Cases" ], "build_configs": { "rv32imac": {"CORE": "n300", "ARCH_EXT":""}, From 903bcae844877237a3cb3c208da56ca432e4b5e0 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 2 Mar 2022 13:19:17 +0800 Subject: [PATCH 12/38] env: don't copy objects when do build Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Runner/nmsis_dsp.json | 2 +- NMSIS/Scripts/Runner/nmsis_nn.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/NMSIS/Scripts/Runner/nmsis_dsp.json b/NMSIS/Scripts/Runner/nmsis_dsp.json index f415535b5..4c4b49d51 100644 --- a/NMSIS/Scripts/Runner/nmsis_dsp.json +++ b/NMSIS/Scripts/Runner/nmsis_dsp.json @@ -9,7 +9,7 @@ } }, "parallel": "-j", - "copy_objects": true, + "copy_objects": false, "build_target": "clean all", "build_config": { "SOC": "demosoc", diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index 6d960ef08..e53b794f5 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -9,7 +9,7 @@ } }, "parallel": "-j", - "copy_objects": true, + "copy_objects": false, "build_target": "clean all", "build_config": { "SOC": "demosoc", From 3276cda8b76f4a00781457d89c4b929d04c9407c Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 2 Mar 2022 17:26:49 +0800 Subject: [PATCH 13/38] env: ignore *.log and Log* Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index fd3052069..5884017ca 100644 --- a/.gitignore +++ b/.gitignore @@ -15,6 +15,8 @@ Library *.o.* logs* log* +Log* *.map *.srec *.verilog +*.log From 2de912bcb2bac846d41cdb03c7bf17b8801ece43 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Tue, 8 Mar 2022 13:53:40 +0800 Subject: [PATCH 14/38] build: bump cmake required minimal version to 3.14 -S -B options required by cmake used now CMAKE_AR is also required, you can download latest cmake here: https://cmake.org/download/ and install it to your path to overwrite system default one. For example ubuntu 18.04: 1. wget https://github.com/Kitware/CMake/releases/download/v3.23.0-rc2/cmake-3.23.0-rc2-linux-x86_64.sh 2. sudo bash cmake-3.23.0-rc2-linux-x86_64.sh --prefix=/usr --skip-license --exclude-subdir 3. cmake --version Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/CMakeLists.txt | 2 +- NMSIS/DSP/Source/CommonTables/CMakeLists.txt | 2 +- NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt | 2 +- NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/CMakeLists.txt | 2 +- NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/SVDFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/ActivationFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/CMakeLists.txt | 2 +- .../NN/Tests/Ref/Source/FullyConnectedFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/NNSupportFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/PoolingFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/SVDFunctions/CMakeLists.txt | 2 +- NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/CMakeLists.txt | 2 +- 39 files changed, 39 insertions(+), 39 deletions(-) diff --git a/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt index 4782fc368..f5f85f3e6 100644 --- a/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_base_math) diff --git a/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt b/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt index 36c20af3f..a4f7ade56 100755 --- a/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/BayesFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_bayes) diff --git a/NMSIS/DSP/Source/CMakeLists.txt b/NMSIS/DSP/Source/CMakeLists.txt index f18133b5d..471e60f52 100755 --- a/NMSIS/DSP/Source/CMakeLists.txt +++ b/NMSIS/DSP/Source/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) SET(CMAKE_C_COMPILER riscv-nuclei-elf-gcc) SET(CMAKE_CXX_COMPILER riscv-nuclei-elf-g++) diff --git a/NMSIS/DSP/Source/CommonTables/CMakeLists.txt b/NMSIS/DSP/Source/CommonTables/CMakeLists.txt index 764ff89d8..6cfd089be 100644 --- a/NMSIS/DSP/Source/CommonTables/CMakeLists.txt +++ b/NMSIS/DSP/Source/CommonTables/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_common_table) diff --git a/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt index 3d23b3e8e..fac2f2b0b 100644 --- a/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_complex) diff --git a/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt b/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt index ac45a7261..1262fd0c0 100644 --- a/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_controller) diff --git a/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt b/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt index 8bc097aef..365853bd6 100755 --- a/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_distance) diff --git a/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt index 5faa87d72..f031c89da 100644 --- a/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_fast_math) diff --git a/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt b/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt index 097704be9..f96534571 100644 --- a/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_filtering) diff --git a/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt b/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt index e387fdba7..2569516c7 100755 --- a/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_interpolation) diff --git a/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt b/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt index 414ae9771..2391e9f4b 100644 --- a/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_matrix) diff --git a/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt b/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt index 53fabdfff..4dccfdaf8 100755 --- a/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_quaternion_math) diff --git a/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt b/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt index 30925eda5..70114adbe 100755 --- a/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/SVMFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_svm) diff --git a/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt b/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt index f69d7f56c..d776e2f80 100644 --- a/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_statistic) diff --git a/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt b/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt index 7dfec1dfa..6f93f2fa8 100644 --- a/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/SupportFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_support) diff --git a/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt b/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt index 4f2e6665d..bc5f255f5 100644 --- a/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt +++ b/NMSIS/DSP/Source/TransformFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.14) project(riscv_transform) diff --git a/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt b/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt index ae8d59d31..956e68401 100644 --- a/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ActivationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNActivation) diff --git a/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt b/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt index 316803564..30bd9fb70 100755 --- a/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNBasicMaths) diff --git a/NMSIS/NN/Source/CMakeLists.txt b/NMSIS/NN/Source/CMakeLists.txt index 0d0994329..fc6642313 100644 --- a/NMSIS/NN/Source/CMakeLists.txt +++ b/NMSIS/NN/Source/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) SET(CMAKE_C_COMPILER riscv-nuclei-elf-gcc) SET(CMAKE_CXX_COMPILER riscv-nuclei-elf-g++) diff --git a/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt b/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt index c6cc9aeec..34918b48d 100644 --- a/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNConcatenation) diff --git a/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt b/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt index 4df17b4e3..b449124c2 100644 --- a/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNConvolutions) diff --git a/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt b/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt index 05f6e57e6..ee95a3df8 100644 --- a/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNFullyConnected) diff --git a/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt b/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt index e3c6409b9..2a151f2c0 100644 --- a/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSupport) diff --git a/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt b/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt index 755896615..85fb8fb60 100644 --- a/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/PoolingFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNPooling) diff --git a/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt b/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt index 93f2d08fa..1b14fb459 100644 --- a/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNReshape) diff --git a/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt b/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt index d64d807ec..8bd9debad 100644 --- a/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/SVDFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSVDF) diff --git a/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt b/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt index f0da004ad..6a6831a62 100644 --- a/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt +++ b/NMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSoftmax) diff --git a/NMSIS/NN/Tests/Ref/CMakeLists.txt b/NMSIS/NN/Tests/Ref/CMakeLists.txt index f80fbd461..2fec616b7 100644 --- a/NMSIS/NN/Tests/Ref/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) SET(CMAKE_C_COMPILER riscv-nuclei-elf-gcc) SET(CMAKE_CXX_COMPILER riscv-nuclei-elf-g++) diff --git a/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/CMakeLists.txt index ae8d59d31..956e68401 100644 --- a/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/ActivationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNActivation) diff --git a/NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/CMakeLists.txt index 316803564..30bd9fb70 100755 --- a/NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/BasicMathFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNBasicMaths) diff --git a/NMSIS/NN/Tests/Ref/Source/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/CMakeLists.txt index 2d593573c..21f8d7c06 100644 --- a/NMSIS/NN/Tests/Ref/Source/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(REF_NN_IMP) diff --git a/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/CMakeLists.txt index c6cc9aeec..34918b48d 100644 --- a/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/ConcatenationFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNConcatenation) diff --git a/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/CMakeLists.txt index 4df17b4e3..b449124c2 100644 --- a/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/ConvolutionFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNConvolutions) diff --git a/NMSIS/NN/Tests/Ref/Source/FullyConnectedFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/FullyConnectedFunctions/CMakeLists.txt index 05f6e57e6..ee95a3df8 100644 --- a/NMSIS/NN/Tests/Ref/Source/FullyConnectedFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/FullyConnectedFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNFullyConnected) diff --git a/NMSIS/NN/Tests/Ref/Source/NNSupportFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/NNSupportFunctions/CMakeLists.txt index e3c6409b9..2a151f2c0 100644 --- a/NMSIS/NN/Tests/Ref/Source/NNSupportFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/NNSupportFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSupport) diff --git a/NMSIS/NN/Tests/Ref/Source/PoolingFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/PoolingFunctions/CMakeLists.txt index 755896615..85fb8fb60 100644 --- a/NMSIS/NN/Tests/Ref/Source/PoolingFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/PoolingFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNPooling) diff --git a/NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/CMakeLists.txt index 93f2d08fa..1b14fb459 100644 --- a/NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/ReshapeFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNReshape) diff --git a/NMSIS/NN/Tests/Ref/Source/SVDFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/SVDFunctions/CMakeLists.txt index a1b41b4f0..e68b04a5e 100644 --- a/NMSIS/NN/Tests/Ref/Source/SVDFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/SVDFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISSVD) diff --git a/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/CMakeLists.txt b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/CMakeLists.txt index f0da004ad..6a6831a62 100644 --- a/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/CMakeLists.txt +++ b/NMSIS/NN/Tests/Ref/Source/SoftmaxFunctions/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required (VERSION 3.5) +cmake_minimum_required (VERSION 3.14) project(NMSISNNSoftmax) From 29829ef0c06ba49aed05193eb1f262476e1e4c79 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Tue, 8 Mar 2022 14:01:41 +0800 Subject: [PATCH 15/38] doc: update cmake requirement in get started guide Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/doc/source/dsp/get_started.rst | 2 +- NMSIS/doc/source/nn/get_started.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/NMSIS/doc/source/dsp/get_started.rst b/NMSIS/doc/source/dsp/get_started.rst index 0fa535785..aeafd62a9 100644 --- a/NMSIS/doc/source/dsp/get_started.rst +++ b/NMSIS/doc/source/dsp/get_started.rst @@ -11,7 +11,7 @@ Preparation * Nuclei SDK, ``dev_xlspike_next`` branch * Nuclei RISCV GNU Toolchain 2021.12 * Nuclei xl_spike -* CMake >= 3.5 +* CMake >= 3.14 * Python 3 Tool Setup diff --git a/NMSIS/doc/source/nn/get_started.rst b/NMSIS/doc/source/nn/get_started.rst index d156747df..c556ebff0 100644 --- a/NMSIS/doc/source/nn/get_started.rst +++ b/NMSIS/doc/source/nn/get_started.rst @@ -11,7 +11,7 @@ Preparation * Nuclei SDK, ``dev_xlspike_next`` branch * Nuclei RISCV GNU Toolchain 2021.12 * Nuclei xl_spike -* CMake >= 3.5 +* CMake >= 3.14 * Python 3 Tool Setup From eef22d290f61ac8dd4211c7717505a2abd47b145 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 11 Mar 2022 09:43:42 +0800 Subject: [PATCH 16/38] Device: Fix bss section lma and vma not aligned and tbss space not reserved Signed-off-by: Huaqi Fang <578567190@qq.com> --- .../NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld | 25 ++++++++++--------- .../NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld | 25 ++++++++++--------- .../Vendor/Device/Source/GCC/gcc_Device.ld | 25 ++++++++++--------- 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld b/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld index 25b874357..558f8156e 100644 --- a/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld +++ b/Device/Nuclei/NUCLEI_N/Source/GCC/gcc_NUCLEI_N.ld @@ -124,6 +124,7 @@ SECTIONS .ialign : { + . = ALIGN(4); /* Create a section label as _ilm which located at flash */ PROVIDE( _ilm = . ); } >flash AT>flash @@ -170,13 +171,6 @@ SECTIONS KEEP (*(SORT_NONE(.fini))) } >flash AT>flash - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - PROVIDE( _eilm = . ); - .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -233,6 +227,11 @@ SECTIONS KEEP (*(.dtors)) } >flash AT>flash + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE (_eilm = .); + .lalign : { . = ALIGN(4); @@ -267,8 +266,6 @@ SECTIONS PROVIDE( _edata = . ); PROVIDE( edata = . ); - . = ALIGN(8); - PROVIDE( _fbss = . ); PROVIDE( __bss_start = . ); @@ -279,7 +276,12 @@ SECTIONS PROVIDE( __tls_end = . ); } >ram AT>ram - .bss (NOLOAD) : + .tbss_space (NOLOAD) : ALIGN(8) + { + . = . + SIZEOF(.tbss); + } >ram AT>ram + + .bss (NOLOAD) : ALIGN(8) { *(.sbss*) *(.gnu.linkonce.sb.*) @@ -289,7 +291,6 @@ SECTIONS . = ALIGN(4); } >ram AT>ram - . = ALIGN(16); PROVIDE( _end = . ); PROVIDE( end = . ); @@ -298,7 +299,7 @@ SECTIONS * 2. __heap_start and __heap_end symbol need to be defined * 3. reserved at least __HEAP_SIZE space for heap */ - .heap (NOLOAD) : + .heap (NOLOAD) : ALIGN(16) { . = ALIGN(16); PROVIDE( __heap_start = . ); diff --git a/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld b/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld index 5d4188f6b..7ba1f0f2b 100644 --- a/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld +++ b/Device/Nuclei/NUCLEI_NX/Source/GCC/gcc_NUCLEI_NX.ld @@ -124,6 +124,7 @@ SECTIONS .ialign : { + . = ALIGN(4); /* Create a section label as _ilm which located at flash */ PROVIDE( _ilm = . ); } >flash AT>flash @@ -170,13 +171,6 @@ SECTIONS KEEP (*(SORT_NONE(.fini))) } >flash AT>flash - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - PROVIDE( _eilm = . ); - .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -233,6 +227,11 @@ SECTIONS KEEP (*(.dtors)) } >flash AT>flash + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE (_eilm = .); + .lalign : { . = ALIGN(4); @@ -267,8 +266,6 @@ SECTIONS PROVIDE( _edata = . ); PROVIDE( edata = . ); - . = ALIGN(8); - PROVIDE( _fbss = . ); PROVIDE( __bss_start = . ); @@ -279,7 +276,12 @@ SECTIONS PROVIDE( __tls_end = . ); } >ram AT>ram - .bss (NOLOAD) : + .tbss_space (NOLOAD) : ALIGN(8) + { + . = . + SIZEOF(.tbss); + } >ram AT>ram + + .bss (NOLOAD) : ALIGN(8) { *(.sbss*) *(.gnu.linkonce.sb.*) @@ -289,7 +291,6 @@ SECTIONS . = ALIGN(4); } >ram AT>ram - . = ALIGN(16); PROVIDE( _end = . ); PROVIDE( end = . ); @@ -298,7 +299,7 @@ SECTIONS * 2. __heap_start and __heap_end symbol need to be defined * 3. reserved at least __HEAP_SIZE space for heap */ - .heap (NOLOAD) : + .heap (NOLOAD) : ALIGN(16) { . = ALIGN(16); PROVIDE( __heap_start = . ); diff --git a/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld b/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld index 90f50ab16..81a00f1c1 100644 --- a/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld +++ b/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_Device.ld @@ -124,6 +124,7 @@ SECTIONS .ialign : { + . = ALIGN(4); /* Create a section label as _ilm which located at flash */ PROVIDE( _ilm = . ); } >flash AT>flash @@ -170,13 +171,6 @@ SECTIONS KEEP (*(SORT_NONE(.fini))) } >flash AT>flash - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - PROVIDE( _eilm = . ); - .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -233,6 +227,11 @@ SECTIONS KEEP (*(.dtors)) } >flash AT>flash + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE (_eilm = .); + .lalign : { . = ALIGN(4); @@ -267,8 +266,6 @@ SECTIONS PROVIDE( _edata = . ); PROVIDE( edata = . ); - . = ALIGN(8); - PROVIDE( _fbss = . ); PROVIDE( __bss_start = . ); @@ -279,7 +276,12 @@ SECTIONS PROVIDE( __tls_end = . ); } >ram AT>ram - .bss (NOLOAD) : + .tbss_space (NOLOAD) : ALIGN(8) + { + . = . + SIZEOF(.tbss); + } >ram AT>ram + + .bss (NOLOAD) : ALIGN(8) { *(.sbss*) *(.gnu.linkonce.sb.*) @@ -289,7 +291,6 @@ SECTIONS . = ALIGN(4); } >ram AT>ram - . = ALIGN(16); PROVIDE( _end = . ); PROVIDE( end = . ); @@ -298,7 +299,7 @@ SECTIONS * 2. __heap_start and __heap_end symbol need to be defined * 3. reserved at least __HEAP_SIZE space for heap */ - .heap (NOLOAD) : + .heap (NOLOAD) : ALIGN(16) { . = ALIGN(16); PROVIDE( __heap_start = . ); From 75230f2d18a9dd867410b513e4ff50f77415e0f3 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 14 Mar 2022 10:54:30 +0800 Subject: [PATCH 17/38] build: Add REBUILD=0 to reuse previous generated Makefile This will solve the issue #10 in gito Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Build/Makefile.build | 1 + NMSIS/Scripts/Build/Makefile.nmsis | 21 ++++++++++++++++----- NMSIS/Scripts/Build/nlbuild.py | 29 ++++++++++++++++++++--------- 3 files changed, 37 insertions(+), 14 deletions(-) diff --git a/NMSIS/Scripts/Build/Makefile.build b/NMSIS/Scripts/Build/Makefile.build index c80c4562a..c8ea2651d 100644 --- a/NMSIS/Scripts/Build/Makefile.build +++ b/NMSIS/Scripts/Build/Makefile.build @@ -56,6 +56,7 @@ help: @echo "RISCV_ABI RISC-V ABI, eg. RISCV_ARCH=lp64d" @echo "RISCV_MODEL RISC-V Model, eg. RISCV_MODEL=medany" @echo "PARALLEL Compile library in PARALLEL, enable PARALLEL by PARALLEL=1" + @echo "REBUILD Do full rebuild library, default REBUILD=1 to full rebuild, use REBUILD=0 to rebuild generated Makefile" @echo "By default, the installed library will be saved into $(LIBIRAY_ROOT)" all: clean info install strip diff --git a/NMSIS/Scripts/Build/Makefile.nmsis b/NMSIS/Scripts/Build/Makefile.nmsis index efb09ebf9..7113f3b20 100644 --- a/NMSIS/Scripts/Build/Makefile.nmsis +++ b/NMSIS/Scripts/Build/Makefile.nmsis @@ -5,6 +5,7 @@ BUILD_ROOT ?= build TOOLCHAIN ?= GCC BUILD_TARGET ?= all PARALLEL_OPTS ?= -j8 +REBUILD ?= 1 # Build Configuration DSP64 ?= ON @@ -23,33 +24,43 @@ MAKE_INFO += DSP64=$(DSP64) LOOPUNROLL=$(LOOPUNROLL) \ ROUNDING=$(ROUNDING) MATRIXCHECK=$(MATRIXCHECK) RISCV_UNALIGN=$(RISCV_UNALIGN) +ifeq ($(REBUILD),0) +EXTRA_NLOPTS += --norebuild +else +EXTRA_NLOPTS += +endif + .PHONY: gen_dsp_lib gen_nn_lib gen_unalign_dsp_lib gen_unalign_nn_lib gen gen_unalign gen_dsp_lib: @echo "Generated DSP library for configuration file $(DSP_JSON_CONFIG)" ./Scripts/Build/nlbuild.py --config $(DSP_JSON_CONFIG) --lib_src DSP/Source --lib_prefix nmsis_dsp \ - --lib_root $(LIBIRAY_ROOT)/DSP/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" + --lib_root $(LIBIRAY_ROOT)/DSP/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" \ + $(EXTRA_NLOPTS) gen_nn_lib: @echo "Generated NN library for configuration file $(NN_JSON_CONFIG)" ./Scripts/Build/nlbuild.py --config $(NN_JSON_CONFIG) --lib_src NN/Source --lib_prefix nmsis_nn \ - --lib_root $(LIBIRAY_ROOT)/NN/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" + --lib_root $(LIBIRAY_ROOT)/NN/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" \ + $(EXTRA_NLOPTS) gen_nnref_lib: @echo "Generated NN Reference library for configuration file $(NNREF_JSON_CONFIG)" ./Scripts/Build/nlbuild.py --config $(NNREF_JSON_CONFIG) --lib_src NN/Tests/Ref \ --lib_prefix nmsis_nnref --lib_root $(LIBIRAY_ROOT)/NNREF/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) \ - --parallel="$(PARALLEL_OPTS)" + --parallel="$(PARALLEL_OPTS)" $(EXTRA_NLOPTS) gen_unalign_dsp_lib: @echo "Generated DSP library for configuration file $(UNALIGN_DSP_JSON_CONFIG)" ./Scripts/Build/nlbuild.py --config $(UNALIGN_DSP_JSON_CONFIG) --lib_src DSP/Source --lib_prefix nmsis_dsp \ - --lib_root $(LIBIRAY_ROOT)/DSP/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" + --lib_root $(LIBIRAY_ROOT)/DSP/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" \ + $(EXTRA_NLOPTS) gen_unalign_nn_lib: @echo "Generated NN library for configuration file $(UNALIGN_NN_JSON_CONFIG)" ./Scripts/Build/nlbuild.py --config $(UNALIGN_NN_JSON_CONFIG) --lib_src NN/Source --lib_prefix nmsis_nn \ - --lib_root $(LIBIRAY_ROOT)/NN/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" + --lib_root $(LIBIRAY_ROOT)/NN/$(TOOLCHAIN) --strip --target $(BUILD_TARGET) --parallel="$(PARALLEL_OPTS)" \ + $(EXTRA_NLOPTS) gen_unalign: gen_unalign_dsp_lib gen_unalign_nn_lib @echo "All libraries are generated into $(LIBIRAY_ROOT)" diff --git a/NMSIS/Scripts/Build/nlbuild.py b/NMSIS/Scripts/Build/nlbuild.py index 46aa2f8ad..6d022d794 100755 --- a/NMSIS/Scripts/Build/nlbuild.py +++ b/NMSIS/Scripts/Build/nlbuild.py @@ -56,7 +56,7 @@ def get_build_artifacts(self, target:str): buildlog = os.path.join(builddir, "build.log") return builddir, cmakelog, buildlog - def build(self, target:str, target_alias:list, config:dict, installdir:str, parallel="-j"): + def build(self, target:str, target_alias:list, config:dict, installdir:str, parallel="-j", norebuild=False): if isinstance(config, dict) == False: return False cmakefile = os.path.join(self.nl_src, "CMakeLists.txt") @@ -68,11 +68,19 @@ def build(self, target:str, target_alias:list, config:dict, installdir:str, para for key in config: cmakeopts += "-D%s=%s " % (key, config[key]) nl_buildir, nl_cmakelog, nl_buildlog = self.get_build_artifacts(target) - mkdirs(nl_buildir, True) - cmake_cmd = "cmake %s -S %s -B %s 2>&1 | tee %s" % (cmakeopts, abs_nlsrc, nl_buildir, nl_cmakelog) - print("Configure project %s for target %s, log record in %s" % (self.nl_src, target, nl_cmakelog)) - run_command(cmake_cmd) makefile = os.path.join(nl_buildir, "Makefile") + genmake = False + if (os.path.isfile(makefile) == False): + genmake = True + elif norebuild == False: + genmake = True + if genmake == True: + mkdirs(nl_buildir, True) + print("Configure project %s for target %s, log record in %s" % (self.nl_src, target, nl_cmakelog)) + cmake_cmd = "cmake %s -S %s -B %s 2>&1 | tee %s" % (cmakeopts, abs_nlsrc, nl_buildir, nl_cmakelog) + run_command(cmake_cmd) + else: + print("Reuse previous generated Makefile configured by cmake!") if os.path.isfile(makefile) == False: print("Makefile for project %s is not generated" % (self.nl_src)) return False @@ -145,7 +153,7 @@ def strip_library(libroot): run_command(strip_cmd) pass -def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, target:str="all", strip=True, parallel="-j", ignore_fail=False): +def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, target:str="all", strip=True, parallel="-j", ignore_fail=False, norebuild=False): if isinstance(buildcfgs, dict) == False: print("No build configuration found") return False @@ -160,7 +168,7 @@ def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, print(">>> Build and install %s library for config %s" % (libsrc, key)) _, _, buildlog = nlb.get_build_artifacts(key) target_alias = aliascfgs.get(key, []) - ret = nlb.build(key, target_alias, buildcfgs[key], libroot, parallel) + ret = nlb.build(key, target_alias, buildcfgs[key], libroot, parallel, norebuild) cost_time = round(time.time() - start_time, 2) rst_table.add_row([key, ret, cost_time, buildlog]) @@ -175,7 +183,7 @@ def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, start_time = time.time() print(">>> Build and install %s library for config %s" % (libsrc, target)) _, _, buildlog = nlb.get_build_artifacts(target) - ret = nlb.build(target, buildcfgs[target], libroot, parallel) + ret = nlb.build(target, buildcfgs[target], libroot, parallel, norebuild) cost_time = round(time.time() - start_time, 2) rst_table.add_row([target, ret, cost_time, buildlog]) if ret == False: @@ -197,6 +205,7 @@ def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, parser.add_argument('--lib_src', default="DSP/Source", help="Where library source code's cmakefile located") parser.add_argument('--lib_prefix', default="nmsis_dsp", help="Library prefix") parser.add_argument('--lib_root', default="Library/DSP/GCC", help="Library built and generate to") + parser.add_argument('--norebuild', action='store_true', help="Don't clean build directories, and rebuild it, just reuse previous build objects for faster build") parser.add_argument('--strip', action='store_true', help="If specified, the installed library will strip out debug symbols") parser.add_argument('--target', default="all", help="if target = all, it means run all the targets defined in config") parser.add_argument('--parallel', default="-j4", help="parallel build library, default -j4") @@ -211,8 +220,10 @@ def install_library(libsrc, buildcfgs:dict, aliascfgs:dict, libprefix, libroot, sys.exit(1) buildcfgs = get_buildcfgs(jsoncfg) aliascfgs = get_aliascfgs(jsoncfg) - runrst = install_library(args.lib_src, buildcfgs, aliascfgs, args.lib_prefix, args.lib_root, args.target, args.strip, args.parallel, args.ignore_fail) + runrst = install_library(args.lib_src, buildcfgs, aliascfgs, args.lib_prefix, args.lib_root, args.target, args.strip, args.parallel, args.ignore_fail, args.norebuild) print("Build Library %s with config %s, generated into %s status: %s" %(args.lib_src, args.config, args.lib_root, runrst)) + if args.norebuild: + print("!!!Use Caution: This build is not fully rebuilt, please take care!!!!") if runrst: sys.exit(0) else: From 989c64d5e42633e8c0aeebf78beb509e1d7d5775 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 11 Mar 2022 19:01:14 +0800 Subject: [PATCH 18/38] ci: change to use nsdk runner Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d40a83c4d..13bd30132 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,6 +1,6 @@ variables: NUCLEI_SDK: git@gito:software/library/nuclei-sdk.git - SDK_BRANCH: master + SDK_BRANCH: hqfang/nsdk_runner SOC: demosoc RUNTARGET: qemu IMAGE: rego.corp.nucleisys.com/software/sdkbuild @@ -116,6 +116,8 @@ build_align_library: # https://serverfault.com/questions/469052/ssh-failing-from-script-working-on-command-line-git - ssh-keyscan gito > ~/.ssh/known_hosts - apt install -y python3 python3-pip + - pip3 config set global.index-url https://pypi.tuna.tsinghua.edu.cn/simple + - python3 -m pip install --upgrade pip - pip3 install prettytable==2.1.0 psutil==5.8.0 pyserial==3.5 markdown dependencies: - build_library @@ -131,6 +133,7 @@ test_nn_library: script: - git clone -b $SDK_BRANCH $NUCLEI_SDK NMSIS/nuclei_sdk - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) + - pip3 install -r $NUCLEI_SDK_ROOT/tools/scripts/requirements.txt - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs # change ilm/dlm size from 64K to 1M for demosoc @@ -153,6 +156,7 @@ test_dsp_library: script: - git clone -b $SDK_BRANCH $NUCLEI_SDK NMSIS/nuclei_sdk - export NUCLEI_SDK_ROOT=$(readlink -f NMSIS/nuclei_sdk) + - pip3 install -r $NUCLEI_SDK_ROOT/tools/scripts/requirements.txt - export NUCLEI_SDK_NMSIS=$(readlink -f NMSIS) - export NMSIS_LOGS=$NUCLEI_SDK_NMSIS/Logs # change ilm/dlm size from 64K to 1M for demosoc From c3fec61b82418c237d7e5b764bb9812b11f0fb63 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 11 Mar 2022 19:02:27 +0800 Subject: [PATCH 19/38] ci: enable ci run on this branch Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 13bd30132..e5e98f9cf 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -23,7 +23,7 @@ build_doc: only: refs: - master - - develop + - hqfang/nsdk_runner changes: - NMSIS/doc/source/**/**/**/* - .gitlab-ci.yml @@ -55,7 +55,7 @@ build_library: only: refs: - master - - develop + - hqfang/nsdk_runner artifacts: when: always name: "nmsis_library-${CI_COMMIT_SHA::8}" @@ -79,7 +79,7 @@ build_align_library: only: refs: - master - - develop + - hqfang/nsdk_runner artifacts: when: always name: "nmsis_align_library-${CI_COMMIT_SHA::8}" @@ -102,7 +102,7 @@ build_align_library: only: refs: - master - - develop + - hqfang/nsdk_runner before_script: # prepare for docker ssh environment ## https://docs.gitlab.com/ee/ci/ssh_keys/#ssh-keys-when-using-the-docker-executor @@ -172,7 +172,7 @@ release_benchmark: only: refs: - master - - develop + - hqfang/nsdk_runner artifacts: name: "nmsis_test_log-${CI_COMMIT_SHA::8}" paths: From 500444921e93e0605d936811207c1010c858dc4f Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Mon, 14 Mar 2022 10:08:24 +0800 Subject: [PATCH 20/38] ci: install pip packages using tsinghua server Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e5e98f9cf..fc607e7a8 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -39,6 +39,7 @@ build_doc: before_script: - apt update - apt install -y doxygen python3 make latexmk texlive-base texlive-latex-extra python3-pip + - pip3 config set global.index-url https://pypi.tuna.tsinghua.edu.cn/simple - pip3 install -r NMSIS/doc/requirements.txt script: - cd NMSIS/doc From 45c465282f6bb5d6dc53dde1248168e2169218d3 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 16 Mar 2022 09:31:48 +0800 Subject: [PATCH 21/38] env: update dsp and nn passed checker Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Runner/nmsis_dsp.json | 2 +- NMSIS/Scripts/Runner/nmsis_nn.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/NMSIS/Scripts/Runner/nmsis_dsp.json b/NMSIS/Scripts/Runner/nmsis_dsp.json index 4c4b49d51..d69ab7887 100644 --- a/NMSIS/Scripts/Runner/nmsis_dsp.json +++ b/NMSIS/Scripts/Runner/nmsis_dsp.json @@ -16,7 +16,7 @@ "DOWNLOAD": "ilm" }, "checks": { - "PASS": ["passed", "Passed", "SUCCESS"], + "PASS": ["passed", "Passed"], "FAIL": ["MEPC", "failed", "Failed", "FAILURE", "ERROR", "test error apprears"] }, "appdirs": [ diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index e53b794f5..acea6fe3a 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -16,7 +16,7 @@ "DOWNLOAD": "ilm" }, "checks": { - "PASS": ["passed", "Passed", "SUCCESS"], + "PASS": ["passed", "Passed"], "FAIL": ["MEPC", "failed", "Failed", "FAILURE"] }, "appdirs": [ From d91a8451a36df4ce9184c101225553f27c00e462 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 18 Mar 2022 13:33:30 +0800 Subject: [PATCH 22/38] Scripts: update nsdk_bench configs Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Runner/nmsis_dsp.json | 72 ++++++++++++++--------------- NMSIS/Scripts/Runner/nmsis_nn.json | 72 ++++++++++++++--------------- 2 files changed, 72 insertions(+), 72 deletions(-) diff --git a/NMSIS/Scripts/Runner/nmsis_dsp.json b/NMSIS/Scripts/Runner/nmsis_dsp.json index d69ab7887..0275fa6a3 100644 --- a/NMSIS/Scripts/Runner/nmsis_dsp.json +++ b/NMSIS/Scripts/Runner/nmsis_dsp.json @@ -1,10 +1,10 @@ { "run_config": { - "target" : "qemu", - "xlspike" : { + "target": "qemu", + "xlspike": { "timeout": 480 }, - "qemu" : { + "qemu": { "timeout": 240 } }, @@ -24,37 +24,37 @@ "DSP/Test" ], "build_configs": { - "rv32imac": {"CORE": "n300", "ARCH_EXT":""}, - "rv32imafc": {"CORE": "n300f", "ARCH_EXT":""}, - "rv32imafdc": {"CORE": "n300fd", "ARCH_EXT":""}, - "rv32imacb": {"CORE": "n300", "ARCH_EXT":"b"}, - "rv32imafcb": {"CORE": "n300f", "ARCH_EXT":"b"}, - "rv32imafdcb": {"CORE": "n300fd", "ARCH_EXT":"b"}, - "rv32imacp": {"CORE": "n300", "ARCH_EXT":"p"}, - "rv32imafcp": {"CORE": "n300f", "ARCH_EXT":"p"}, - "rv32imafdcp": {"CORE": "n300fd", "ARCH_EXT":"p"}, - "rv32imacbp": {"CORE": "n300", "ARCH_EXT":"bp"}, - "rv32imafcbp": {"CORE": "n300f", "ARCH_EXT":"bp"}, - "rv32imafdcbp": {"CORE": "n300fd", "ARCH_EXT":"bp"}, - "rv64imac": {"CORE": "nx600", "ARCH_EXT":""}, - "rv64imafc": {"CORE": "nx600f", "ARCH_EXT":""}, - "rv64imafdc": {"CORE": "nx600fd", "ARCH_EXT":""}, - "rv64imacb": {"CORE": "nx600", "ARCH_EXT":"b"}, - "rv64imafcb": {"CORE": "nx600f", "ARCH_EXT":"b"}, - "rv64imafdcb": {"CORE": "nx600fd", "ARCH_EXT":"b"}, - "rv64imacp": {"CORE": "nx600", "ARCH_EXT":"p"}, - "rv64imafcp": {"CORE": "nx600f", "ARCH_EXT":"p"}, - "rv64imafdcp": {"CORE": "nx600fd", "ARCH_EXT":"p"}, - "rv64imacbp": {"CORE": "nx600", "ARCH_EXT":"bp"}, - "rv64imafcbp": {"CORE": "nx600f", "ARCH_EXT":"bp"}, - "rv64imafdcbp": {"CORE": "nx600fd", "ARCH_EXT":"bp"}, - "rv64imafcv": {"CORE": "nx600f", "ARCH_EXT":"v"}, - "rv64imafdcv": {"CORE": "nx600fd", "ARCH_EXT":"v"}, - "rv64imafcbv": {"CORE": "nx600f", "ARCH_EXT":"bv"}, - "rv64imafdcbv": {"CORE": "nx600fd", "ARCH_EXT":"bv"}, - "rv64imafcpv": {"CORE": "nx600f", "ARCH_EXT":"pv"}, - "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"}, - "rv64imafcbpv": {"CORE": "nx600f", "ARCH_EXT":"bpv"}, - "rv64imafdcbpv": {"CORE": "nx600fd", "ARCH_EXT":"bpv"} + "rv32imac": { "CORE": "n300", "ARCH_EXT": "" }, + "rv32imafc": { "CORE": "n300f", "ARCH_EXT": "" }, + "rv32imafdc": { "CORE": "n300fd", "ARCH_EXT": "" }, + "rv32imacb": { "CORE": "n300", "ARCH_EXT": "b" }, + "rv32imafcb": { "CORE": "n300f", "ARCH_EXT": "b" }, + "rv32imafdcb": { "CORE": "n300fd", "ARCH_EXT": "b" }, + "rv32imacp": { "CORE": "n300", "ARCH_EXT": "p" }, + "rv32imafcp": { "CORE": "n300f", "ARCH_EXT": "p" }, + "rv32imafdcp": { "CORE": "n300fd", "ARCH_EXT": "p" }, + "rv32imacbp": { "CORE": "n300", "ARCH_EXT": "bp" }, + "rv32imafcbp": { "CORE": "n300f", "ARCH_EXT": "bp" }, + "rv32imafdcbp": { "CORE": "n300fd", "ARCH_EXT": "bp" }, + "rv64imac": { "CORE": "nx600", "ARCH_EXT": "" }, + "rv64imafc": { "CORE": "nx600f", "ARCH_EXT": "" }, + "rv64imafdc": { "CORE": "nx600fd", "ARCH_EXT": "" }, + "rv64imacb": { "CORE": "nx600", "ARCH_EXT": "b" }, + "rv64imafcb": { "CORE": "nx600f", "ARCH_EXT": "b" }, + "rv64imafdcb": { "CORE": "nx600fd", "ARCH_EXT": "b" }, + "rv64imacp": { "CORE": "nx600", "ARCH_EXT": "p" }, + "rv64imafcp": { "CORE": "nx600f", "ARCH_EXT": "p" }, + "rv64imafdcp": { "CORE": "nx600fd", "ARCH_EXT": "p" }, + "rv64imacbp": { "CORE": "nx600", "ARCH_EXT": "bp" }, + "rv64imafcbp": { "CORE": "nx600f", "ARCH_EXT": "bp" }, + "rv64imafdcbp": { "CORE": "nx600fd", "ARCH_EXT": "bp" }, + "rv64imafcv": { "CORE": "nx600f", "ARCH_EXT": "v" }, + "rv64imafdcv": { "CORE": "nx600fd", "ARCH_EXT": "v" }, + "rv64imafcbv": { "CORE": "nx600f", "ARCH_EXT": "bv" }, + "rv64imafdcbv": { "CORE": "nx600fd", "ARCH_EXT": "bv" }, + "rv64imafcpv": { "CORE": "nx600f", "ARCH_EXT": "pv" }, + "rv64imafdcpv": { "CORE": "nx600fd", "ARCH_EXT": "pv" }, + "rv64imafcbpv": { "CORE": "nx600f", "ARCH_EXT": "bpv" }, + "rv64imafdcbpv": { "CORE": "nx600fd", "ARCH_EXT": "bpv" } } -} +} \ No newline at end of file diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index acea6fe3a..0dc3915c8 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -1,10 +1,10 @@ { "run_config": { - "target" : "qemu", - "xlspike" : { + "target": "qemu", + "xlspike": { "timeout": 480 }, - "qemu" : { + "qemu": { "timeout": 240 } }, @@ -24,38 +24,38 @@ "NN/Tests/Cases" ], "build_configs": { - "rv32imac": {"CORE": "n300", "ARCH_EXT":""}, - "rv32imafc": {"CORE": "n300f", "ARCH_EXT":""}, - "rv32imafdc": {"CORE": "n300fd", "ARCH_EXT":""}, - "rv32imacb": {"CORE": "n300", "ARCH_EXT":"b"}, - "rv32imafcb": {"CORE": "n300f", "ARCH_EXT":"b"}, - "rv32imafdcb": {"CORE": "n300fd", "ARCH_EXT":"b"}, - "rv32imacp": {"CORE": "n300", "ARCH_EXT":"p"}, - "rv32imafcp": {"CORE": "n300f", "ARCH_EXT":"p"}, - "rv32imafdcp": {"CORE": "n300fd", "ARCH_EXT":"p"}, - "rv32imacbp": {"CORE": "n300", "ARCH_EXT":"bp"}, - "rv32imafcbp": {"CORE": "n300f", "ARCH_EXT":"bp"}, - "rv32imafdcbp": {"CORE": "n300fd", "ARCH_EXT":"bp"}, - "rv64imac": {"CORE": "nx600", "ARCH_EXT":""}, - "rv64imafc": {"CORE": "nx600f", "ARCH_EXT":""}, - "rv64imafdc": {"CORE": "nx600fd", "ARCH_EXT":""}, - "rv64imacb": {"CORE": "nx600", "ARCH_EXT":"b"}, - "rv64imafcb": {"CORE": "nx600f", "ARCH_EXT":"b"}, - "rv64imafdcb": {"CORE": "nx600fd", "ARCH_EXT":"b"}, - "rv64imacp": {"CORE": "nx600", "ARCH_EXT":"p"}, - "rv64imafcp": {"CORE": "nx600f", "ARCH_EXT":"p"}, - "rv64imafdcp": {"CORE": "nx600fd", "ARCH_EXT":"p"}, - "rv64imacbp": {"CORE": "nx600", "ARCH_EXT":"bp"}, - "rv64imafcbp": {"CORE": "nx600f", "ARCH_EXT":"bp"}, - "rv64imafdcbp": {"CORE": "nx600fd", "ARCH_EXT":"bp"}, - "rv64imafcv": {"CORE": "nx600f", "ARCH_EXT":"v"}, - "rv64imafdcv": {"CORE": "nx600fd", "ARCH_EXT":"v"}, - "rv64imafcbv": {"CORE": "nx600f", "ARCH_EXT":"bv"}, - "rv64imafdcbv": {"CORE": "nx600fd", "ARCH_EXT":"bv"}, - "rv64imafcpv": {"CORE": "nx600f", "ARCH_EXT":"pv"}, - "rv64imafdcpv": {"CORE": "nx600fd", "ARCH_EXT":"pv"}, - "rv64imafcbpv": {"CORE": "nx600f", "ARCH_EXT":"bpv"}, - "rv64imafdcbpv": {"CORE": "nx600fd", "ARCH_EXT":"bpv"} + "rv32imac": { "CORE": "n300", "ARCH_EXT": "" }, + "rv32imafc": { "CORE": "n300f", "ARCH_EXT": "" }, + "rv32imafdc": { "CORE": "n300fd", "ARCH_EXT": "" }, + "rv32imacb": { "CORE": "n300", "ARCH_EXT": "b" }, + "rv32imafcb": { "CORE": "n300f", "ARCH_EXT": "b" }, + "rv32imafdcb": { "CORE": "n300fd", "ARCH_EXT": "b" }, + "rv32imacp": { "CORE": "n300", "ARCH_EXT": "p" }, + "rv32imafcp": { "CORE": "n300f", "ARCH_EXT": "p" }, + "rv32imafdcp": { "CORE": "n300fd", "ARCH_EXT": "p" }, + "rv32imacbp": { "CORE": "n300", "ARCH_EXT": "bp" }, + "rv32imafcbp": { "CORE": "n300f", "ARCH_EXT": "bp" }, + "rv32imafdcbp": { "CORE": "n300fd", "ARCH_EXT": "bp" }, + "rv64imac": { "CORE": "nx600", "ARCH_EXT": "" }, + "rv64imafc": { "CORE": "nx600f", "ARCH_EXT": "" }, + "rv64imafdc": { "CORE": "nx600fd", "ARCH_EXT": "" }, + "rv64imacb": { "CORE": "nx600", "ARCH_EXT": "b" }, + "rv64imafcb": { "CORE": "nx600f", "ARCH_EXT": "b" }, + "rv64imafdcb": { "CORE": "nx600fd", "ARCH_EXT": "b" }, + "rv64imacp": { "CORE": "nx600", "ARCH_EXT": "p" }, + "rv64imafcp": { "CORE": "nx600f", "ARCH_EXT": "p" }, + "rv64imafdcp": { "CORE": "nx600fd", "ARCH_EXT": "p" }, + "rv64imacbp": { "CORE": "nx600", "ARCH_EXT": "bp" }, + "rv64imafcbp": { "CORE": "nx600f", "ARCH_EXT": "bp" }, + "rv64imafdcbp": { "CORE": "nx600fd", "ARCH_EXT": "bp" }, + "rv64imafcv": { "CORE": "nx600f", "ARCH_EXT": "v" }, + "rv64imafdcv": { "CORE": "nx600fd", "ARCH_EXT": "v" }, + "rv64imafcbv": { "CORE": "nx600f", "ARCH_EXT": "bv" }, + "rv64imafdcbv": { "CORE": "nx600fd", "ARCH_EXT": "bv" }, + "rv64imafcpv": { "CORE": "nx600f", "ARCH_EXT": "pv" }, + "rv64imafdcpv": { "CORE": "nx600fd", "ARCH_EXT": "pv" }, + "rv64imafcbpv": { "CORE": "nx600f", "ARCH_EXT": "bpv" }, + "rv64imafdcbpv": { "CORE": "nx600fd", "ARCH_EXT": "bpv" } }, "appconfig": { "NN/Examples/RISCV/cifar10": { @@ -69,4 +69,4 @@ } } } -} +} \ No newline at end of file From edcf8264b26184e713360e7aa53624888a73eab6 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 18 Mar 2022 15:40:44 +0800 Subject: [PATCH 23/38] configs: add nsdk_runner template configs Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Configs/fpga/n300.json | 22 +++++++ NMSIS/Scripts/Configs/fpga/n900.json | 22 +++++++ NMSIS/Scripts/Configs/fpga/nmsis_dsp.json | 24 ++++++++ NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml | 72 +++++++++++++++++++++++ NMSIS/Scripts/Configs/fpga/nmsis_nn.json | 32 ++++++++++ NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml | 72 +++++++++++++++++++++++ NMSIS/Scripts/Configs/fpga/ux900.json | 22 +++++++ 7 files changed, 266 insertions(+) create mode 100644 NMSIS/Scripts/Configs/fpga/n300.json create mode 100644 NMSIS/Scripts/Configs/fpga/n900.json create mode 100644 NMSIS/Scripts/Configs/fpga/nmsis_dsp.json create mode 100644 NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml create mode 100644 NMSIS/Scripts/Configs/fpga/nmsis_nn.json create mode 100644 NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml create mode 100644 NMSIS/Scripts/Configs/fpga/ux900.json diff --git a/NMSIS/Scripts/Configs/fpga/n300.json b/NMSIS/Scripts/Configs/fpga/n300.json new file mode 100644 index 000000000..ad6c31503 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n300.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "300" + }, + "build_configs": { + "rv32imac": {"CORE":"n300"}, + "rv32imacb": {"CORE":"n300", "ARCH_EXT":"b"}, + "rv32imacp": {"CORE":"n300", "ARCH_EXT":"p"}, + "rv32imacbp": {"CORE":"n300", "ARCH_EXT":"bp"}, + "rv32imafc": {"CORE":"n300f", "ARCH_EXT":""}, + "rv32imafcb": {"CORE":"n300f", "ARCH_EXT":"b"}, + "rv32imafcp": {"CORE":"n300f", "ARCH_EXT":"p"}, + "rv32imafcbp": {"CORE":"n300f", "ARCH_EXT":"bp"}, + "rv32imafdc": {"CORE":"n300fd", "ARCH_EXT":""}, + "rv32imafdcb": {"CORE":"n300fd", "ARCH_EXT":"b"}, + "rv32imafdcp": {"CORE":"n300fd", "ARCH_EXT":"p"}, + "rv32imafdcbp": {"CORE":"n300fd", "ARCH_EXT":"bp"} + } +} diff --git a/NMSIS/Scripts/Configs/fpga/n900.json b/NMSIS/Scripts/Configs/fpga/n900.json new file mode 100644 index 000000000..6fef0ece6 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n900.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "900" + }, + "build_configs": { + "rv32imac": {"CORE":"n900"}, + "rv32imacb": {"CORE":"n900", "ARCH_EXT":"b"}, + "rv32imacp": {"CORE":"n900", "ARCH_EXT":"p"}, + "rv32imacbp": {"CORE":"n900", "ARCH_EXT":"bp"}, + "rv32imafc": {"CORE":"n900f", "ARCH_EXT":""}, + "rv32imafcb": {"CORE":"n900f", "ARCH_EXT":"b"}, + "rv32imafcp": {"CORE":"n900f", "ARCH_EXT":"p"}, + "rv32imafcbp": {"CORE":"n900f", "ARCH_EXT":"bp"}, + "rv32imafdc": {"CORE":"n900fd", "ARCH_EXT":""}, + "rv32imafdcb": {"CORE":"n900fd", "ARCH_EXT":"b"}, + "rv32imafdcp": {"CORE":"n900fd", "ARCH_EXT":"p"}, + "rv32imafdcbp": {"CORE":"n900fd", "ARCH_EXT":"bp"} + } +} diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json new file mode 100644 index 000000000..0bb3f5af8 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json @@ -0,0 +1,24 @@ +{ + "run_config": { + "target" : "hardware", + "hardware" : { + "timeout": 480 + }, + "qemu" : { + "timeout": 240 + } + }, + "parallel": "-j", + "copy_objects": true, + "build_target": "clean all", + "build_config": { + "SOC": "demosoc" + }, + "checks": { + "PASS": ["passed", "Passed"], + "FAIL": ["MEPC", "failed", "Failed", "FAILURE", "ERROR", "test error apprears"] + }, + "appdirs": [ + "DSP/Test" + ] +} diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml new file mode 100644 index 000000000..d1e9e9a31 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml @@ -0,0 +1,72 @@ +runcfg: + runner: fpga + +environment: + fpgaloc: Scripts/Configs/fpga + ncycmloc: Scripts/Configs/fpga + cfgloc: Scripts/Configs/fpga + +# fpga runners +fpga_runners: + ddr200t_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ddr200t + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Digilent/210251A08870 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT4JUVF6 + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB1 + ku060_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ku060 + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Xilinx/13724327082c01 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT6JGAXS + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB4 + +ncycm_runners: + n200: + model: n200_software_best_config_cymodel + n300: + model: n300_software_best_config_cymodel + n900: + model: n900_software_best_config_cymodel + ux900: + model: ux900_software_best_config_cymodel + +# configs +configs: + n200: + fpga: ddr200t + # bitstream path related to this yaml's loc or abs path + bitstream: n200_software_best_config_ddr200t_16M.bit + ncycm: n200 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n200.json + # cpu core name + n300: + fpga: ddr200t + bitstream: n300_software_best_config_ddr200t_16M.bit + ncycm: n300 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n300.json + # cpu core name + n900: + fpga: ku060 + bitstream: n900_software_best_config_ku060_16M.bit + ncycm: n900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n900.json + ux900: + fpga: ku060 + bitstream: ux900_software_best_config_ku060_16M.bit + ncycm: ux900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: ux900.json diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_nn.json b/NMSIS/Scripts/Configs/fpga/nmsis_nn.json new file mode 100644 index 000000000..3da7f8925 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_nn.json @@ -0,0 +1,32 @@ +{ + "run_config": { + "target" : "hardware", + "hardware" : { + "timeout": 480 + }, + "qemu" : { + "timeout": 240 + } + }, + "parallel": "-j", + "copy_objects": true, + "build_target": "clean all", + "build_config": { + "SOC": "demosoc" + }, + "checks": { + "PASS": ["passed", "Passed"], + "FAIL": ["MEPC", "failed", "Failed", "FAILURE", "ERROR", "test error apprears"] + }, + "appdirs": [ + "NN/Examples/RISCV/cifar10", + "NN/Tests/Cases/" + ], + "appconfig": { + "NN/Examples/RISCV/cifar10": { + "checks": { + "PASS": ["label 3: 45, Cat, 35.43%"] + } + } + } +} diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml b/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml new file mode 100644 index 000000000..58e0d4201 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml @@ -0,0 +1,72 @@ +runcfg: + runner: fpga + +environment: + fpgaloc: Scripts/Configs/fpga + ncycmloc: Scripts/Configs/fpga + cfgloc: Scripts/Configs/fpga + +# fpga runners +fpga_runners: + ddr200t_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ddr200t + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Digilent/210251A08870 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT4JUVF6 + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB1 + ku060_1: + # ddr200t/mcu200t/ku060/vcu118 + board_type: ku060 + # serial number, such as Digilent/210308AC59C6 + fpga_serial: Xilinx/13724327082c01 + # ftdi_serial number, such as FT4JUVF6 + ftdi_serial: FT6JGAXS + # serial_port number, such as /dev/ttyUSB1 + serial_port: /dev/ttyUSB4 + +ncycm_runners: + n200: + model: n200_software_best_config_cymodel + n300: + model: n300_software_best_config_cymodel + n900: + model: n900_software_best_config_cymodel + ux900: + model: ux900_software_best_config_cymodel + +# configs +configs: + n200: + fpga: ddr200t + # bitstream path related to this yaml's loc or abs path + bitstream: n200_software_best_config_ddr200t_16M.bit + ncycm: n200 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n200.json + # cpu core name + n300: + fpga: ddr200t + bitstream: n300_software_best_config_ddr200t_16M.bit + ncycm: n300 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n300.json + # cpu core name + n900: + fpga: ku060 + bitstream: n900_software_best_config_ku060_16M.bit + ncycm: n900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n900.json + ux900: + fpga: ku060 + bitstream: ux900_software_best_config_ku060_16M.bit + ncycm: ux900 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: ux900.json diff --git a/NMSIS/Scripts/Configs/fpga/ux900.json b/NMSIS/Scripts/Configs/fpga/ux900.json new file mode 100644 index 000000000..b6787fa67 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/ux900.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "900" + }, + "build_configs": { + "rv64imac": {"CORE":"ux900"}, + "rv64imacb": {"CORE":"ux900", "ARCH_EXT":"b"}, + "rv64imacp": {"CORE":"ux900", "ARCH_EXT":"p"}, + "rv64imacbp": {"CORE":"ux900", "ARCH_EXT":"bp"}, + "rv64imafc": {"CORE":"ux900f", "ARCH_EXT":""}, + "rv64imafcb": {"CORE":"ux900f", "ARCH_EXT":"b"}, + "rv64imafcp": {"CORE":"ux900f", "ARCH_EXT":"p"}, + "rv64imafcbp": {"CORE":"ux900f", "ARCH_EXT":"bp"}, + "rv64imafdc": {"CORE":"ux900fd", "ARCH_EXT":""}, + "rv64imafdcb": {"CORE":"ux900fd", "ARCH_EXT":"b"}, + "rv64imafdcp": {"CORE":"ux900fd", "ARCH_EXT":"p"}, + "rv64imafdcbp": {"CORE":"ux900fd", "ARCH_EXT":"bp"} + } +} From d62153f222d13c6bafd8afdf6e82480a8fa6644b Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 18 Mar 2022 16:01:15 +0800 Subject: [PATCH 24/38] tools: add script to setup nuclei-sdk and nmsis env Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Configs/fpga/setup.sh | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 NMSIS/Scripts/Configs/fpga/setup.sh diff --git a/NMSIS/Scripts/Configs/fpga/setup.sh b/NMSIS/Scripts/Configs/fpga/setup.sh new file mode 100644 index 000000000..53216c74d --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/setup.sh @@ -0,0 +1,18 @@ +#!/bin/env bash +SCRIPTDIR=$(dirname $(readlink -f $BASH_SOURCE)) +NSDK_ROOT=${NSDK_ROOT:-${SCRIPTDIR}/../../../../../../nuclei-sdk} +NMSIS_ROOT=${NMSIS_ROOT:-${SCRIPTDIR}/../../../} + +NSDK_ROOT=$(readlink -f ${NSDK_ROOT}) +NMSIS_ROOT=$(readlink -f ${NMSIS_ROOT}) + +echo "Export NUCLEI_SDK_ROOT and NUCLEI_SDK_NMSIS" +export NUCLEI_SDK_ROOT=$NSDK_ROOT +export NUCLEI_SDK_NMSIS=$NMSIS_ROOT +unset NSDK_ROOT NMSIS_ROOT + +echo "NUCLEI_SDK_ROOT=$NUCLEI_SDK_ROOT" +echo "NUCLEI_SDK_NMSIS=$NUCLEI_SDK_NMSIS" + +echo "Only copy elf and map file when do bench" +export SDK_COPY_OBJECTS="elf,map" \ No newline at end of file From e038899bdc97ab33a035cd64a17c877b1df2bdd7 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 18 Mar 2022 16:02:36 +0800 Subject: [PATCH 25/38] ci: make ci interruptiable and only save elf and map objects Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 5 +++++ NMSIS/Scripts/Runner/nmsis_nn.json | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index fc607e7a8..2fa275a74 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -19,6 +19,7 @@ stages: build_doc: stage: build + interruptible: true retry: 1 only: refs: @@ -52,6 +53,7 @@ build_doc: build_library: stage: build + interruptible: true retry: 1 only: refs: @@ -76,6 +78,7 @@ build_library: build_align_library: stage: build + interruptible: true retry: 1 only: refs: @@ -120,6 +123,7 @@ build_align_library: - pip3 config set global.index-url https://pypi.tuna.tsinghua.edu.cn/simple - python3 -m pip install --upgrade pip - pip3 install prettytable==2.1.0 psutil==5.8.0 pyserial==3.5 markdown + - export SDK_COPY_OBJECTS="elf,map" dependencies: - build_library @@ -170,6 +174,7 @@ test_dsp_library: release_benchmark: stage: release + interruptible: true only: refs: - master diff --git a/NMSIS/Scripts/Runner/nmsis_nn.json b/NMSIS/Scripts/Runner/nmsis_nn.json index 0dc3915c8..9187a9d9c 100644 --- a/NMSIS/Scripts/Runner/nmsis_nn.json +++ b/NMSIS/Scripts/Runner/nmsis_nn.json @@ -9,7 +9,7 @@ } }, "parallel": "-j", - "copy_objects": false, + "copy_objects": true, "build_target": "clean all", "build_config": { "SOC": "demosoc", From b7347ef9fc71faba3f928ee40ddee8d15191f12a Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Tue, 22 Mar 2022 14:15:42 +0800 Subject: [PATCH 26/38] scripts: add scripts to generate nmsis dsp/nn elfs Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh | 74 ++++++++++++++++++++ NMSIS/Scripts/Configs/fpga/n200.json | 12 ++++ NMSIS/Scripts/Configs/fpga/n600.json | 22 ++++++ NMSIS/Scripts/Configs/fpga/nmsis_dsp.json | 9 +-- NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml | 19 +++++ NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml | 19 +++++ NMSIS/Scripts/Configs/fpga/setup.sh | 2 +- NMSIS/Scripts/Configs/fpga/ux600.json | 22 ++++++ 8 files changed, 174 insertions(+), 5 deletions(-) create mode 100755 NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh create mode 100644 NMSIS/Scripts/Configs/fpga/n200.json create mode 100644 NMSIS/Scripts/Configs/fpga/n600.json create mode 100644 NMSIS/Scripts/Configs/fpga/ux600.json diff --git a/NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh b/NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh new file mode 100755 index 000000000..068d836b4 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/gen_nmsis_elfs.sh @@ -0,0 +1,74 @@ +#!/bin/env bash +LOGROOT=${LOGROOT:-gen} +DRYRUN=${DRYRUN:-0} +RUNON=${RUNON-nothing} +TOOL_VER=${TOOL_VER:-2022.01} + +SCRIPTDIR=$(dirname $(readlink -f $BASH_SOURCE)) + +DEVTOOL_ENV=${DEVTOOL_ENV:-/home/share/devtools/env.sh} + +TOOL_VER=$TOOL_VER source $DEVTOOL_ENV + +source $SCRIPTDIR/setup.sh +LOGROOT=$(readlink -f $LOGROOT) + +if [ ! -d $LOGROOT ] ; then + mkdir -p $LOGROOT +fi + +function describe_repo { + local repodir=${1} + local repodesc=${2:-repogit.txt} + repodir=$(readlink -f $repodir) + if [ -d ${repodir}/.git ] ; then + pushd ${repodir} + echo "Git Repo $repodir Information:" >> ${repodesc} + gitver=$(git describe --tags --always --abbrev=10 --dirty) + gitslog=$(git log --oneline -1) + echo "git describe version: $gitver" >> ${repodesc} + echo "git shortlog: $gitslog" >> ${repodesc} + git submodule >> ${repodesc} + popd + else + echo "$repodir not a git repo" >> ${repodesc} + fi +} + +function describe_build { + logfile=$1 + echo -n "Build Date: " > $logfile + date >> $logfile + echo "Nuclei GNU Toolchain Version:" >> $logfile + riscv-nuclei-elf-gcc -v >> $logfile 2>&1 +} + +function record_buildinfo { + BUILDTXT=$LOGROOT/build.txt + + describe_build $BUILDTXT + describe_repo $NUCLEI_SDK_ROOT $BUILDTXT + describe_repo $NUCLEI_SDK_NMSIS/.. $BUILDTXT +} + +function changelinkscript { + echo "Change demosoc linker script to 512K" + sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld +} + +record_buildinfo + +changelinkscript + +NSDK_RUNNER_PY="$NUCLEI_SDK_ROOT/tools/scripts/nsdk_cli/nsdk_runner.py" + +pushd $NUCLEI_SDK_NMSIS +for lib in nmsis_dsp nmsis_nn +do + RUNNER_CMD="python3 $NSDK_RUNNER_PY --appyaml $SCRIPTDIR/$lib.yaml --logdir $LOGROOT/$lib --runon $RUNON --cfgloc $SCRIPTDIR" + echo $RUNNER_CMD + if [[ $DRYRUN == 0 ]] ; then + eval $RUNNER_CMD + fi +done +popd diff --git a/NMSIS/Scripts/Configs/fpga/n200.json b/NMSIS/Scripts/Configs/fpga/n200.json new file mode 100644 index 000000000..6b8aecb0d --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n200.json @@ -0,0 +1,12 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "200" + }, + "build_configs": { + "rv32imac": { "CORE": "n203" }, + "rv32imacb": { "CORE": "n203", "ARCH_EXT": "b" } + } +} diff --git a/NMSIS/Scripts/Configs/fpga/n600.json b/NMSIS/Scripts/Configs/fpga/n600.json new file mode 100644 index 000000000..3628a26dc --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/n600.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "600" + }, + "build_configs": { + "rv32imac": { "CORE": "n600" }, + "rv32imacb": { "CORE": "n600", "ARCH_EXT": "b" }, + "rv32imacp": { "CORE": "n600", "ARCH_EXT": "p" }, + "rv32imacbp": { "CORE": "n600", "ARCH_EXT": "bp" }, + "rv32imafc": { "CORE": "n600f", "ARCH_EXT": "" }, + "rv32imafcb": { "CORE": "n600f", "ARCH_EXT": "b" }, + "rv32imafcp": { "CORE": "n600f", "ARCH_EXT": "p" }, + "rv32imafcbp": { "CORE": "n600f", "ARCH_EXT": "bp" }, + "rv32imafdc": { "CORE": "n600fd", "ARCH_EXT": "" }, + "rv32imafdcb": { "CORE": "n600fd", "ARCH_EXT": "b" }, + "rv32imafdcp": { "CORE": "n600fd", "ARCH_EXT": "p" }, + "rv32imafdcbp": { "CORE": "n600fd", "ARCH_EXT": "bp" } + } +} \ No newline at end of file diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json index 0bb3f5af8..a33ebe520 100644 --- a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json +++ b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.json @@ -1,10 +1,10 @@ { "run_config": { - "target" : "hardware", - "hardware" : { + "target": "hardware", + "hardware": { "timeout": 480 }, - "qemu" : { + "qemu": { "timeout": 240 } }, @@ -19,6 +19,7 @@ "FAIL": ["MEPC", "failed", "Failed", "FAILURE", "ERROR", "test error apprears"] }, "appdirs": [ + "DSP/Examples/RISCV", "DSP/Test" ] -} +} \ No newline at end of file diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml index d1e9e9a31..784b7c4e7 100644 --- a/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml +++ b/NMSIS/Scripts/Configs/fpga/nmsis_dsp.yaml @@ -36,6 +36,10 @@ ncycm_runners: model: n900_software_best_config_cymodel ux900: model: ux900_software_best_config_cymodel + n600: + model: n600_software_best_config_cymodel + ux600: + model: ux600_software_best_config_cymodel # configs configs: @@ -56,6 +60,21 @@ configs: appcfg: nmsis_dsp.json hwcfg: n300.json # cpu core name + n600: + fpga: ku060 + bitstream: n600_software_best_config_ku060_16M.bit + ncycm: n600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: n600.json + ux600: + fpga: ku060 + bitstream: ux600_software_best_config_ku060_16M.bit + ncycm: ux600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_dsp.json + hwcfg: ux600.json + # cpu core name n900: fpga: ku060 bitstream: n900_software_best_config_ku060_16M.bit diff --git a/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml b/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml index 58e0d4201..2a2c6ff11 100644 --- a/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml +++ b/NMSIS/Scripts/Configs/fpga/nmsis_nn.yaml @@ -36,6 +36,10 @@ ncycm_runners: model: n900_software_best_config_cymodel ux900: model: ux900_software_best_config_cymodel + n600: + model: n600_software_best_config_cymodel + ux600: + model: ux600_software_best_config_cymodel # configs configs: @@ -56,6 +60,21 @@ configs: appcfg: nmsis_nn.json hwcfg: n300.json # cpu core name + n600: + fpga: ku060 + bitstream: n600_software_best_config_ku060_16M.bit + ncycm: n600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: n600.json + ux600: + fpga: ku060 + bitstream: ux600_software_best_config_ku060_16M.bit + ncycm: ux600 + openocd_cfg: SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg + appcfg: nmsis_nn.json + hwcfg: ux600.json + # cpu core name n900: fpga: ku060 bitstream: n900_software_best_config_ku060_16M.bit diff --git a/NMSIS/Scripts/Configs/fpga/setup.sh b/NMSIS/Scripts/Configs/fpga/setup.sh index 53216c74d..3c0f1748b 100644 --- a/NMSIS/Scripts/Configs/fpga/setup.sh +++ b/NMSIS/Scripts/Configs/fpga/setup.sh @@ -1,6 +1,6 @@ #!/bin/env bash SCRIPTDIR=$(dirname $(readlink -f $BASH_SOURCE)) -NSDK_ROOT=${NSDK_ROOT:-${SCRIPTDIR}/../../../../../../nuclei-sdk} +NSDK_ROOT=${NSDK_ROOT:-${SCRIPTDIR}/../../../../../nuclei-sdk} NMSIS_ROOT=${NMSIS_ROOT:-${SCRIPTDIR}/../../../} NSDK_ROOT=$(readlink -f ${NSDK_ROOT}) diff --git a/NMSIS/Scripts/Configs/fpga/ux600.json b/NMSIS/Scripts/Configs/fpga/ux600.json new file mode 100644 index 000000000..6a33f0227 --- /dev/null +++ b/NMSIS/Scripts/Configs/fpga/ux600.json @@ -0,0 +1,22 @@ +{ + "build_config": { + "SOC": "demosoc", + "BOARD": "nuclei_fpga_eval", + "DOWNLOAD": "ilm", + "CPU_SERIES": "600" + }, + "build_configs": { + "rv64imac": { "CORE": "ux600" }, + "rv64imacb": { "CORE": "ux600", "ARCH_EXT": "b" }, + "rv64imacp": { "CORE": "ux600", "ARCH_EXT": "p" }, + "rv64imacbp": { "CORE": "ux600", "ARCH_EXT": "bp" }, + "rv64imafc": { "CORE": "ux600f", "ARCH_EXT": "" }, + "rv64imafcb": { "CORE": "ux600f", "ARCH_EXT": "b" }, + "rv64imafcp": { "CORE": "ux600f", "ARCH_EXT": "p" }, + "rv64imafcbp": { "CORE": "ux600f", "ARCH_EXT": "bp" }, + "rv64imafdc": { "CORE": "ux600fd", "ARCH_EXT": "" }, + "rv64imafdcb": { "CORE": "ux600fd", "ARCH_EXT": "b" }, + "rv64imafdcp": { "CORE": "ux600fd", "ARCH_EXT": "p" }, + "rv64imafdcbp": { "CORE": "ux600fd", "ARCH_EXT": "bp" } + } +} \ No newline at end of file From eb4d9becc9297598d2aa5d15bd92cf82867d4670 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Tue, 22 Mar 2022 16:50:24 +0800 Subject: [PATCH 27/38] nn: fix svd test case not right Signed-off-by: Huaqi Fang <578567190@qq.com> --- .../Cases/full/riscv_nnexamples_nn_test.cpp | 39 +++++++++++-------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp b/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp index cff6981ac..752d57112 100644 --- a/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp +++ b/NMSIS/NN/Tests/Cases/full/riscv_nnexamples_nn_test.cpp @@ -1035,6 +1035,11 @@ int main() q7_t *pool_out_ref = test3; q7_t *pool_out_opt = test3 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH / 2; + srand(__RV_CSR_READ(mcycle)); + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + test1[i] = rand(); + } // copy over the img input for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { @@ -1083,7 +1088,7 @@ int main() riscv_avepool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *) test2, pool_out_opt); BENCH_END(riscv_avepool_q7_HWC); - verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); delete[]test1; delete[]test2; @@ -1193,7 +1198,8 @@ int main() #ifdef TEST_SVD #define SVD_SIZE 2048 test1 = new q7_t[SVD_SIZE*2]; - test2 = new q15_t[SVD_SIZE*2]; + q15_t *test2_ref = new q15_t[SVD_SIZE*3]; + q15_t *test2_opt = new q15_t[SVD_SIZE*3]; test3 = new q7_t[SVD_SIZE*2]; q7_t *test20; @@ -1205,6 +1211,7 @@ int main() q31_t *test22; test22 = new q31_t[SVD_SIZE*2]; + srand(__RV_CSR_READ(mcycle)); for (int i=0;i Date: Tue, 22 Mar 2022 17:20:32 +0800 Subject: [PATCH 28/38] NN: change riscv_maxpool_q7_HWC implementation, rvv opt is not done Signed-off-by: Huaqi Fang <578567190@qq.com> --- .../PoolingFunctions/riscv_pool_q7_HWC.c | 45 ++++++++++++++++--- 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c b/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c index 26d875a7a..59885662d 100644 --- a/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c +++ b/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c @@ -61,6 +61,33 @@ static void buffer_scale_back_q7_to_q7(q7_t * buffer, q7_t * target, uint16_t le } } +static void buffer_scale_back_q15_to_q7(q15_t *buffer, q7_t *target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t)(buffer[i] / scale); + } +} + +// TODO: to be optimized in RVV +static void accumulate_q7_to_q15(q15_t *base, q7_t *target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; +// uint16_t cnt = length >> 2; + uint16_t cnt = length; + q31_t in; + + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + #else #if defined (RISCV_MATH_DSP) @@ -420,17 +447,20 @@ void riscv_avepool_q7_HWC(q7_t *Im_in, } /* first step is to copy over initial data */ - riscv_q7_to_q7_no_shift(win_start, (q7_t *)buffer, ch_im_in); + //riscv_q7_to_q7_no_shift(win_start, (q7_t *)buffer, ch_im_in); + riscv_q7_to_q15_no_shift(win_start, buffer, ch_im_in); count = 1; /* start the max operation from the second part */ win_start += ch_im_in; for (; win_start < win_stop; win_start += ch_im_in) { - riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, win_start, ch_im_in); + //riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, win_start, ch_im_in); + accumulate_q7_to_q15(buffer, win_start, ch_im_in); count++; } - buffer_scale_back_q7_to_q7(buffer, target, ch_im_in, count); + //buffer_scale_back_q7_to_q7(buffer, target, ch_im_in, count); + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); // riscv_scale_q7((q7_t *)buffer,(1/ch_im_in),0,target,count); } } @@ -462,7 +492,8 @@ void riscv_avepool_q7_HWC(q7_t *Im_in, } /* copy over the first row */ - riscv_q7_to_q7_no_shift(row_start, (q7_t *)buffer, dim_im_out * ch_im_in); + riscv_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + //riscv_q7_to_q7_no_shift(row_start, (q7_t *)buffer, dim_im_out * ch_im_in); count = 1; /* move over to next row */ @@ -470,10 +501,12 @@ void riscv_avepool_q7_HWC(q7_t *Im_in, for (; row_start < row_end; row_start += dim_im_in * ch_im_in) { - riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, row_start, dim_im_out * ch_im_in); + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + //riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, row_start, dim_im_out * ch_im_in); count++; } - buffer_scale_back_q7_to_q7(buffer, target, dim_im_out * ch_im_in, count); + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + //buffer_scale_back_q7_to_q7(buffer, target, dim_im_out * ch_im_in, count); // riscv_scale_q7((q7_t *)buffer,ch_im_in,0,target,count); } From 95ac11e6ffa4b8f2793dde1e0296d1bf6bb602cc Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Tue, 22 Mar 2022 18:42:43 +0800 Subject: [PATCH 29/38] NN: add optimized rvv version of accumulate_q7_to_q15 Signed-off-by: Huaqi Fang <578567190@qq.com> --- .../PoolingFunctions/riscv_pool_q7_HWC.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c b/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c index 59885662d..8637b7a96 100644 --- a/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c +++ b/NMSIS/NN/Source/PoolingFunctions/riscv_pool_q7_HWC.c @@ -74,17 +74,17 @@ static void buffer_scale_back_q15_to_q7(q15_t *buffer, q7_t *target, uint16_t le // TODO: to be optimized in RVV static void accumulate_q7_to_q15(q15_t *base, q7_t *target, const uint16_t length) { - q15_t *pCnt = base; - q7_t *pV = target; - q31_t v1, v2, vo1, vo2; -// uint16_t cnt = length >> 2; - uint16_t cnt = length; - q31_t in; - - while (cnt > 0u) - { - *pCnt++ += *pV++; - cnt--; + vint8m4_t tval; + vint16m8_t dval; + size_t l; + uint32_t cnt = length; + + for (; (l = vsetvl_e16m8(cnt)) > 0; cnt -= l) { + tval = vle8_v_i8m4(target, l); + dval = vle16_v_i16m8(base, l); + vse16_v_i16m8(base, vwadd_wv_i16m8(dval, tval, l), l); + target += l; + base += l; } } From c748e8439952c17cb0e8af3bd55dde0d362c63e2 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 23 Mar 2022 15:34:45 +0800 Subject: [PATCH 30/38] DSP: Fix test DSP/Test/TransformFunction/dct4 RV64 with p enabled not working. Found bug in implementation of riscv_cmplx_mult_cmplx_q15 when XLEN=64 Signed-off-by: Huaqi Fang <578567190@qq.com> --- .../ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c b/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c index ae7a2b56c..df7f3cea7 100644 --- a/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c +++ b/NMSIS/DSP/Source/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c @@ -127,7 +127,7 @@ void riscv_cmplx_mult_cmplx_q15( d = *pSrcB++; /* store result in 3.13 format in destination buffer. */ -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -140,7 +140,7 @@ void riscv_cmplx_mult_cmplx_q15( c = *pSrcB++; d = *pSrcB++; -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -153,7 +153,7 @@ void riscv_cmplx_mult_cmplx_q15( c = *pSrcB++; d = *pSrcB++; -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -166,7 +166,7 @@ void riscv_cmplx_mult_cmplx_q15( c = *pSrcB++; d = *pSrcB++; -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else @@ -200,7 +200,7 @@ void riscv_cmplx_mult_cmplx_q15( d = *pSrcB++; /* store result in 3.13 format in destination buffer. */ -#if defined(RISCV_MATH_DSP) +#if defined(RISCV_MATH_DSP) && __RISCV_XLEN == 32 *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); #else From f26754a6b135f06ec01f042fca397d887ea3126d Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 23 Mar 2022 15:36:16 +0800 Subject: [PATCH 31/38] Core: sync changes from nuclei-sdk Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/Core/Include/core_feature_bitmanip.h | 2 ++ NMSIS/Core/Include/core_feature_dsp.h | 2 ++ NMSIS/Core/Include/core_feature_timer.h | 28 +++++++++++----------- NMSIS/Core/Include/core_feature_vector.h | 2 ++ 4 files changed, 20 insertions(+), 14 deletions(-) diff --git a/NMSIS/Core/Include/core_feature_bitmanip.h b/NMSIS/Core/Include/core_feature_bitmanip.h index 9c748259d..552509832 100644 --- a/NMSIS/Core/Include/core_feature_bitmanip.h +++ b/NMSIS/Core/Include/core_feature_bitmanip.h @@ -53,7 +53,9 @@ */ /** @} */ /* End of Doxygen Group NMSIS_Core_Bitmanip_Intrinsic */ +#if defined(__INC_INTRINSIC_API) && (__INC_INTRINSIC_API == 1) #include +#endif #endif /* defined(__BITMANIP_PRESENT) && (__BITMANIP_PRESENT == 1) */ diff --git a/NMSIS/Core/Include/core_feature_dsp.h b/NMSIS/Core/Include/core_feature_dsp.h index 6e9e16c95..d8ce384c0 100644 --- a/NMSIS/Core/Include/core_feature_dsp.h +++ b/NMSIS/Core/Include/core_feature_dsp.h @@ -36,7 +36,9 @@ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) +#if defined(__INC_INTRINSIC_API) && (__INC_INTRINSIC_API == 1) #include +#endif /* ########################### CPU SIMD DSP Intrinsic Functions ########################### */ /** diff --git a/NMSIS/Core/Include/core_feature_timer.h b/NMSIS/Core/Include/core_feature_timer.h index 43e777e8d..881a01c9a 100644 --- a/NMSIS/Core/Include/core_feature_timer.h +++ b/NMSIS/Core/Include/core_feature_timer.h @@ -117,8 +117,8 @@ typedef struct { __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) { #if __RISCV_XLEN == 32 - void *addr; - addr = (void *)(&(SysTimer->MTIMER)); + uint8_t *addr; + addr = (uint8_t *)(&(SysTimer->MTIMER)); __SW(addr, 0); // prevent carry __SW(addr + 4, (uint32_t)(value >> 32)); __SW(addr, (uint32_t)(value)); @@ -141,9 +141,9 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) #if __RISCV_XLEN == 32 volatile uint32_t high0, low, high; uint64_t full; - void *addr; + uint8_t *addr; - addr = (void *)(&(SysTimer->MTIMER)); + addr = (uint8_t *)(&(SysTimer->MTIMER)); high0 = __LW(addr + 4); low = __LW(addr); @@ -174,8 +174,8 @@ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) unsigned long hartid = __RV_CSR_READ(CSR_MHARTID); if (hartid == 0) { #if __RISCV_XLEN == 32 - void *addr; - addr = (void *)(&(SysTimer->MTIMERCMP)); + uint8_t *addr; + addr = (uint8_t *)(&(SysTimer->MTIMERCMP)); __SW(addr, -1U); // prevent load > timecmp __SW(addr + 4, (uint32_t)(value >> 32)); __SW(addr, (uint32_t)(value)); @@ -183,7 +183,7 @@ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) SysTimer->MTIMERCMP = value; #endif } else { - void *addr = (void *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); #if __RISCV_XLEN == 32 __SW(addr, -1U); // prevent load > timecmp __SW(addr + 4, (uint32_t)(value >> 32)); @@ -210,7 +210,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) return SysTimer->MTIMERCMP; } else { uint64_t full; - void *addr = (void *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MTIMECMP_BASE(hartid)); #if __RISCV_XLEN == 32 // MTIMECMP didn't increase uint32_t high, low; @@ -294,7 +294,7 @@ __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) if (hartid == 0) { SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk; } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, SysTimer_MSIP_MSIP_Msk); } } @@ -314,7 +314,7 @@ __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) if (hartid == 0) { SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk; } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, 0); } } @@ -336,7 +336,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) if (hartid == 0) { return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk); } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); return __LW(addr); } } @@ -353,7 +353,7 @@ __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) if (hartid == 0) { SysTimer->MSIP = (msip & SysTimer_MSIP_Msk); } else { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, msip); } } @@ -382,7 +382,7 @@ __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) */ __STATIC_FORCEINLINE void SysTimer_SendIPI(uint32_t hartid) { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, 1); } @@ -394,7 +394,7 @@ __STATIC_FORCEINLINE void SysTimer_SendIPI(uint32_t hartid) */ __STATIC_FORCEINLINE void SysTimer_ClearIPI(uint32_t hartid) { - void *addr = (void *)(SysTimer_CLINT_MSIP_BASE(hartid)); + uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid)); __SW(addr, 0); } diff --git a/NMSIS/Core/Include/core_feature_vector.h b/NMSIS/Core/Include/core_feature_vector.h index 205b31474..6d3893f93 100644 --- a/NMSIS/Core/Include/core_feature_vector.h +++ b/NMSIS/Core/Include/core_feature_vector.h @@ -57,7 +57,9 @@ */ /** @} */ /* End of Doxygen Group NMSIS_Core_Vector_Intrinsic */ +#if defined(__INC_INTRINSIC_API) && (__INC_INTRINSIC_API == 1) #include +#endif #endif /* defined(__VECTOR_PRESENT) && (__VECTOR_PRESENT == 1) */ From d35b45b47afaf54420441a769262422b5ec51e8c Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 23 Mar 2022 15:53:47 +0800 Subject: [PATCH 32/38] DSP: adapt riscv math header for bitmainp Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/DSP/Include/riscv_math_types.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/NMSIS/DSP/Include/riscv_math_types.h b/NMSIS/DSP/Include/riscv_math_types.h index 11470441a..b794c1963 100755 --- a/NMSIS/DSP/Include/riscv_math_types.h +++ b/NMSIS/DSP/Include/riscv_math_types.h @@ -70,16 +70,27 @@ extern "C" #define __NMSIS_GENERIC #if (defined (__riscv_dsp)) + #undef __DSP_PRESENT #define __DSP_PRESENT 1 #undef __RISCV_FEATURE_DSP #define __RISCV_FEATURE_DSP 1 #endif #if (defined (__riscv_vector)) + #undef __VECTOR_PRESENT #define __VECTOR_PRESENT 1 #undef __RISCV_FEATURE_VECTOR #define __RISCV_FEATURE_VECTOR 1 #endif +#if (defined (__riscv_bitmainp)) + #define __BITMANIP_PRESENT 1 + #undef __RISCV_FEATURE_BITMANIP + #define __RISCV_FEATURE_BITMANIP 1 +#endif + +#undef __INC_INTRINSIC_API +#define __INC_INTRINSIC_API 1 + #include "nmsis_core.h" #undef __NMSIS_GENERIC From 1029724daebe6c6eccb7f34187f6306dffe70572 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 23 Mar 2022 15:54:36 +0800 Subject: [PATCH 33/38] ci: use develop branch of nuclei-sdk Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2fa275a74..f86946dcf 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,6 +1,6 @@ variables: NUCLEI_SDK: git@gito:software/library/nuclei-sdk.git - SDK_BRANCH: hqfang/nsdk_runner + SDK_BRANCH: develop SOC: demosoc RUNTARGET: qemu IMAGE: rego.corp.nucleisys.com/software/sdkbuild From 55f841c16509a25b454ebb75ea2f6d1b7087aa80 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 23 Mar 2022 15:56:06 +0800 Subject: [PATCH 34/38] Revert "ci: enable ci run on this branch" This reverts commit c3fec61b82418c237d7e5b764bb9812b11f0fb63. --- .gitlab-ci.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f86946dcf..65b8bb49f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -24,7 +24,7 @@ build_doc: only: refs: - master - - hqfang/nsdk_runner + - develop changes: - NMSIS/doc/source/**/**/**/* - .gitlab-ci.yml @@ -58,7 +58,7 @@ build_library: only: refs: - master - - hqfang/nsdk_runner + - develop artifacts: when: always name: "nmsis_library-${CI_COMMIT_SHA::8}" @@ -83,7 +83,7 @@ build_align_library: only: refs: - master - - hqfang/nsdk_runner + - develop artifacts: when: always name: "nmsis_align_library-${CI_COMMIT_SHA::8}" @@ -106,7 +106,7 @@ build_align_library: only: refs: - master - - hqfang/nsdk_runner + - develop before_script: # prepare for docker ssh environment ## https://docs.gitlab.com/ee/ci/ssh_keys/#ssh-keys-when-using-the-docker-executor @@ -178,7 +178,7 @@ release_benchmark: only: refs: - master - - hqfang/nsdk_runner + - develop artifacts: name: "nmsis_test_log-${CI_COMMIT_SHA::8}" paths: From 69a4fd4a7351ad78dca2bf641575cc12e4f9326a Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 30 Mar 2022 09:51:06 +0800 Subject: [PATCH 35/38] doc: update doc for changelog and dsp/nn get started Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/doc/source/changelog.rst | 28 ++++++++++++++++++++++ NMSIS/doc/source/dsp/get_started.rst | 36 ++++++++++++++++++---------- NMSIS/doc/source/nn/get_started.rst | 35 +++++++++++++++++---------- 3 files changed, 73 insertions(+), 26 deletions(-) diff --git a/NMSIS/doc/source/changelog.rst b/NMSIS/doc/source/changelog.rst index 6ff032170..eb7bc295d 100644 --- a/NMSIS/doc/source/changelog.rst +++ b/NMSIS/doc/source/changelog.rst @@ -17,6 +17,34 @@ This is the version ``V1.0.4-dev`` release of Nuclei MCU Software Interface Stan - rearrage #include header files for all NMSIS Core header files - removed some not good #pragma gcc diagnostic lines in ``nmsis_gcc.h`` +* **NMSIS-DSP** + + - Add initial bitmainp extension support + - Fix bug in riscv_cmplx_mult_cmplx_q15 function when XLEN=64 + +* **NMSIS-NN** + + - Add initial bitmainp extension support + - Change riscv_maxpool_q7_HWC implementation for rvv + - Re-org NN_Lib_Tests to Tests + +* **Build System** + + - Change minimal version of cmake to 3.14 + - Add REBUILD=0 to reuse previous generated Makefile + +* **Device Tempates** + + - Fix bss section lma and vma not aligned and tbss space not reserved + +* **CI** + + - Change NMSIS to use Nuclei SDK demosoc as ci run target + - only run ci on master/develop branch + +* **Documentation** + + - Update get started guide for dsp/nn library V1.0.3 ------ diff --git a/NMSIS/doc/source/dsp/get_started.rst b/NMSIS/doc/source/dsp/get_started.rst index aeafd62a9..05ebe0523 100644 --- a/NMSIS/doc/source/dsp/get_started.rst +++ b/NMSIS/doc/source/dsp/get_started.rst @@ -8,9 +8,9 @@ Here we will describe how to run the nmsis dsp examples in Nuclei Spike. Preparation ----------- -* Nuclei SDK, ``dev_xlspike_next`` branch -* Nuclei RISCV GNU Toolchain 2021.12 -* Nuclei xl_spike +* Nuclei SDK, ``develop`` branch +* Nuclei RISCV GNU Toolchain 2022.04 +* Nuclei xl_spike or qemu * CMake >= 3.14 * Python 3 @@ -73,36 +73,46 @@ How to run ---------- 1. Set environment variables ``NUCLEI_SDK_ROOT`` and ``NUCLEI_SDK_NMSIS``, - and set Nuclei SDK SoC to `xlspike` + and set Nuclei SDK SoC to `demosoc`, and change ilm/dlm size from 64K to 512K .. code-block:: shell export NUCLEI_SDK_ROOT=/path/to/nuclei_sdk export NUCLEI_SDK_NMSIS=/path/to/NMSIS/NMSIS - export SOC=xlspike + # Setup SDK development environment + cd $NUCLEI_SDK_ROOT + source setup.sh + cd - + # !!!!Take Care!!!! + # change this link script will make compiled example can only run on bitstream which has 512K ILM/DLM + sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld + export SOC=demosoc 2. Let us take ``./riscv_class_marks_example/`` for example 3. ``cd ./riscv_class_marks_example/`` -4. Run with RISCV DSP enabled and Vector enabled NMSIS-DSP library for CORE ``ux900fd`` +4. Run with RISCV DSP enabled and Vector enabled NMSIS-DSP library for CORE ``nx900fd`` .. code-block:: shell # Clean project - make ARCH_EXT=pv CORE=ux900fd clean + make ARCH_EXT=pv CORE=nx900fd clean # Build project - make ARCH_EXT=pv CORE=ux900fd all + make ARCH_EXT=pv CORE=nx900fd all # Run application using xl_spike - make ARCH_EXT=pv CORE=ux900fd run + make ARCH_EXT=pv CORE=nx900fd run_xlspike + # Run application using qemu + make ARCH_EXT=pv CORE=nx900fd run_qemu -5. Run with RISCV DSP disabled and Vector disabled NMSIS-DSP library for CORE ``ux900fd`` +5. Run with RISCV DSP disabled and Vector disabled NMSIS-DSP library for CORE ``nx900fd`` .. code-block:: shell - make ARCH_EXT= CORE=ux900fd clean - make ARCH_EXT= CORE=ux900fd all - make ARCH_EXT= CORE=ux900fd run + make ARCH_EXT= CORE=nx900fd clean + make ARCH_EXT= CORE=nx900fd all + make ARCH_EXT=pv CORE=nx900fd run_xlspike + make ARCH_EXT=pv CORE=nx900fd run_qemu .. note:: diff --git a/NMSIS/doc/source/nn/get_started.rst b/NMSIS/doc/source/nn/get_started.rst index c556ebff0..377010d54 100644 --- a/NMSIS/doc/source/nn/get_started.rst +++ b/NMSIS/doc/source/nn/get_started.rst @@ -8,9 +8,9 @@ Here we will describe how to run the nmsis nn examples in Nuclei Spike. Preparation ----------- -* Nuclei SDK, ``dev_xlspike_next`` branch -* Nuclei RISCV GNU Toolchain 2021.12 -* Nuclei xl_spike +* Nuclei SDK, ``develop`` branch +* Nuclei RISCV GNU Toolchain 2022.04 +* Nuclei xl_spike or qemu * CMake >= 3.14 * Python 3 @@ -75,37 +75,46 @@ How to run ---------- 1. Set environment variables ``NUCLEI_SDK_ROOT`` and ``NUCLEI_SDK_NMSIS``, - and set Nuclei SDK SoC to `xlspike` + and set Nuclei SDK SoC to `demosoc`, and change ilm/dlm size from 64K to 512K .. code-block:: shell export NUCLEI_SDK_ROOT=/path/to/nuclei_sdk export NUCLEI_SDK_NMSIS=/path/to/NMSIS/NMSIS - export SOC=xlspike + # Setup SDK development environment + cd $NUCLEI_SDK_ROOT + source setup.sh + cd - + # !!!!Take Care!!!! + # change this link script will make compiled example can only run on bitstream which has 512K ILM/DLM + sed -i "s/64K/512K/g" $NUCLEI_SDK_ROOT/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld + export SOC=demosoc 2. Let us take ``./cifar10/`` for example 2. ``cd ./cifar10/`` -3. Run with RISCV DSP enabled and Vector enabled NMSIS-NN library for CORE ``ux900fd`` +3. Run with RISCV DSP enabled and Vector enabled NMSIS-NN library for CORE ``nx900fd`` .. code-block:: # Clean project - make ARCH_EXT=pv CORE=ux900fd clean + make ARCH_EXT=pv CORE=nx900fd clean # Build project - make ARCH_EXT=pv CORE=ux900fd all + make ARCH_EXT=pv CORE=nx900fd all # Run application using xl_spike - make ARCH_EXT=pv CORE=ux900fd run + make ARCH_EXT=pv CORE=nx900fd run_xlspike + # Run application using qemu + make ARCH_EXT=pv CORE=nx900fd run_qemu -4. Run with RISCV DSP disabled and Vector disabled NMSIS-NN library for CORE ``ux900fd`` +4. Run with RISCV DSP disabled and Vector disabled NMSIS-NN library for CORE ``nx900fd`` .. code-block:: shell - make ARCH_EXT= CORE=ux900fd clean - make ARCH_EXT= CORE=ux900fd all - make ARCH_EXT= CORE=ux900fd run + make ARCH_EXT= CORE=nx900fd clean + make ARCH_EXT= CORE=nx900fd all + make ARCH_EXT= CORE=nx900fd run .. note:: From 3f813125c6f5420764290a3556dea0bff3850dfe Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 30 Mar 2022 10:02:44 +0800 Subject: [PATCH 36/38] Device: Remove .vtable_ilm and undefined interrupt default to default interrupt handler Signed-off-by: Huaqi Fang <578567190@qq.com> --- .../NUCLEI_N/Source/GCC/startup_NUCLEI_N.S | 57 +++----- .../NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S | 57 +++----- .../Vendor/Device/Source/GCC/startup_Device.S | 124 ++++++------------ 3 files changed, 77 insertions(+), 161 deletions(-) diff --git a/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S b/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S index edbc38de6..737dac31a 100644 --- a/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S +++ b/Device/Nuclei/NUCLEI_N/Source/GCC/startup_NUCLEI_N.S @@ -34,33 +34,11 @@ #endif .endm - /* - * Put the interrupt vectors in this section according to vector remapped or not: - * .vtable: vector table's LMA and VMA are the same, it is not remapped - * .vtable_ilm: vector table's LMA and VMA are different, it is remapped, and - * VECTOR_TABLE_REMAPPED need to be defined - */ -#if defined(VECTOR_TABLE_REMAPPED) - .section .vtable_ilm -#else .section .vtable -#endif .weak eclic_msip_handler .weak eclic_mtip_handler - .weak eclic_irq19_handler - .weak eclic_irq20_handler - .weak eclic_irq21_handler - .weak eclic_irq22_handler - .weak eclic_irq23_handler - .weak eclic_irq24_handler - .weak eclic_irq25_handler - .weak eclic_irq26_handler - .weak eclic_irq27_handler - .weak eclic_irq28_handler - .weak eclic_irq29_handler - .weak eclic_irq30_handler - .weak eclic_irq31_handler + /* TODO: add vendor interrupt handlers */ .globl vector_base .type vector_base, @object @@ -90,22 +68,23 @@ vector_base: DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 17: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 18: Reserved */ - DECLARE_INT_HANDLER eclic_irq19_handler /* 19: Interrupt 19 */ - - DECLARE_INT_HANDLER eclic_irq20_handler /* 20: Interrupt 20 */ - DECLARE_INT_HANDLER eclic_irq21_handler /* 21: Interrupt 21 */ - DECLARE_INT_HANDLER eclic_irq22_handler /* 22: Interrupt 22 */ - DECLARE_INT_HANDLER eclic_irq23_handler /* 23: Interrupt 23 */ - - DECLARE_INT_HANDLER eclic_irq24_handler /* 24: Interrupt 24 */ - DECLARE_INT_HANDLER eclic_irq25_handler /* 25: Interrupt 25 */ - DECLARE_INT_HANDLER eclic_irq26_handler /* 26: Interrupt 26 */ - DECLARE_INT_HANDLER eclic_irq27_handler /* 27: Interrupt 27 */ - - DECLARE_INT_HANDLER eclic_irq28_handler /* 28: Interrupt 28 */ - DECLARE_INT_HANDLER eclic_irq29_handler /* 29: Interrupt 29 */ - DECLARE_INT_HANDLER eclic_irq30_handler /* 30: Interrupt 30 */ - DECLARE_INT_HANDLER eclic_irq31_handler /* 31: Interrupt 31 */ + /* TODO: Adjust Vendor Defined External Interrupts */ + DECLARE_INT_HANDLER default_intexc_handler /* 19: Interrupt 19 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 20: Interrupt 20 */ + DECLARE_INT_HANDLER default_intexc_handler /* 21: Interrupt 21 */ + DECLARE_INT_HANDLER default_intexc_handler /* 22: Interrupt 22 */ + DECLARE_INT_HANDLER default_intexc_handler /* 23: Interrupt 23 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 24: Interrupt 24 */ + DECLARE_INT_HANDLER default_intexc_handler /* 25: Interrupt 25 */ + DECLARE_INT_HANDLER default_intexc_handler /* 26: Interrupt 26 */ + DECLARE_INT_HANDLER default_intexc_handler /* 27: Interrupt 27 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 28: Interrupt 28 */ + DECLARE_INT_HANDLER default_intexc_handler /* 29: Interrupt 29 */ + DECLARE_INT_HANDLER default_intexc_handler /* 30: Interrupt 30 */ + DECLARE_INT_HANDLER default_intexc_handler /* 31: Interrupt 31 */ /*** Startup Code Section ***/ diff --git a/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S b/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S index faa3ac002..cb4a545af 100644 --- a/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S +++ b/Device/Nuclei/NUCLEI_NX/Source/GCC/startup_NUCLEI_NX.S @@ -34,33 +34,11 @@ #endif .endm - /* - * Put the interrupt vectors in this section according to vector remapped or not: - * .vtable: vector table's LMA and VMA are the same, it is not remapped - * .vtable_ilm: vector table's LMA and VMA are different, it is remapped, and - * VECTOR_TABLE_REMAPPED need to be defined - */ -#if defined(VECTOR_TABLE_REMAPPED) - .section .vtable_ilm -#else .section .vtable -#endif .weak eclic_msip_handler .weak eclic_mtip_handler - .weak eclic_irq19_handler - .weak eclic_irq20_handler - .weak eclic_irq21_handler - .weak eclic_irq22_handler - .weak eclic_irq23_handler - .weak eclic_irq24_handler - .weak eclic_irq25_handler - .weak eclic_irq26_handler - .weak eclic_irq27_handler - .weak eclic_irq28_handler - .weak eclic_irq29_handler - .weak eclic_irq30_handler - .weak eclic_irq31_handler + /* TODO: add vendor interrupt handlers */ .globl vector_base .type vector_base, @object @@ -90,22 +68,23 @@ vector_base: DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 17: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 18: Reserved */ - DECLARE_INT_HANDLER eclic_irq19_handler /* 19: Interrupt 19 */ - - DECLARE_INT_HANDLER eclic_irq20_handler /* 20: Interrupt 20 */ - DECLARE_INT_HANDLER eclic_irq21_handler /* 21: Interrupt 21 */ - DECLARE_INT_HANDLER eclic_irq22_handler /* 22: Interrupt 22 */ - DECLARE_INT_HANDLER eclic_irq23_handler /* 23: Interrupt 23 */ - - DECLARE_INT_HANDLER eclic_irq24_handler /* 24: Interrupt 24 */ - DECLARE_INT_HANDLER eclic_irq25_handler /* 25: Interrupt 25 */ - DECLARE_INT_HANDLER eclic_irq26_handler /* 26: Interrupt 26 */ - DECLARE_INT_HANDLER eclic_irq27_handler /* 27: Interrupt 27 */ - - DECLARE_INT_HANDLER eclic_irq28_handler /* 28: Interrupt 28 */ - DECLARE_INT_HANDLER eclic_irq29_handler /* 29: Interrupt 29 */ - DECLARE_INT_HANDLER eclic_irq30_handler /* 30: Interrupt 30 */ - DECLARE_INT_HANDLER eclic_irq31_handler /* 31: Interrupt 31 */ + /* TODO: Adjust Vendor Defined External Interrupts */ + DECLARE_INT_HANDLER default_intexc_handler /* 19: Interrupt 19 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 20: Interrupt 20 */ + DECLARE_INT_HANDLER default_intexc_handler /* 21: Interrupt 21 */ + DECLARE_INT_HANDLER default_intexc_handler /* 22: Interrupt 22 */ + DECLARE_INT_HANDLER default_intexc_handler /* 23: Interrupt 23 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 24: Interrupt 24 */ + DECLARE_INT_HANDLER default_intexc_handler /* 25: Interrupt 25 */ + DECLARE_INT_HANDLER default_intexc_handler /* 26: Interrupt 26 */ + DECLARE_INT_HANDLER default_intexc_handler /* 27: Interrupt 27 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 28: Interrupt 28 */ + DECLARE_INT_HANDLER default_intexc_handler /* 29: Interrupt 29 */ + DECLARE_INT_HANDLER default_intexc_handler /* 30: Interrupt 30 */ + DECLARE_INT_HANDLER default_intexc_handler /* 31: Interrupt 31 */ /*** Startup Code Section ***/ diff --git a/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S b/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S index 05159e119..f564a49f8 100644 --- a/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S +++ b/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S @@ -34,53 +34,11 @@ #endif .endm - /* - * Put the interrupt vectors in this section according to vector remapped or not: - * .vtable: vector table's LMA and VMA are the same, it is not remapped - * .vtable_ilm: vector table's LMA and VMA are different, it is remapped, and - * VECTOR_TABLE_REMAPPED need to be defined - */ -#if defined(VECTOR_TABLE_REMAPPED) - .section .vtable_ilm -#else .section .vtable -#endif .weak eclic_msip_handler .weak eclic_mtip_handler - /* TODO: Adjust vendor interrupt handlers */ - .weak eclic_irq19_handler - .weak eclic_irq20_handler - .weak eclic_irq21_handler - .weak eclic_irq22_handler - .weak eclic_irq23_handler - .weak eclic_irq24_handler - .weak eclic_irq25_handler - .weak eclic_irq26_handler - .weak eclic_irq27_handler - .weak eclic_irq28_handler - .weak eclic_irq29_handler - .weak eclic_irq30_handler - .weak eclic_irq31_handler - .weak eclic_irq32_handler - .weak eclic_irq33_handler - .weak eclic_irq34_handler - .weak eclic_irq35_handler - .weak eclic_irq36_handler - .weak eclic_irq37_handler - .weak eclic_irq38_handler - .weak eclic_irq39_handler - .weak eclic_irq40_handler - .weak eclic_irq41_handler - .weak eclic_irq42_handler - .weak eclic_irq43_handler - .weak eclic_irq44_handler - .weak eclic_irq45_handler - .weak eclic_irq46_handler - .weak eclic_irq47_handler - .weak eclic_irq48_handler - .weak eclic_irq49_handler - .weak eclic_irq50_handler + /* TODO: add vendor interrupt handlers */ .globl vector_base .type vector_base, @object @@ -111,46 +69,46 @@ vector_base: DECLARE_INT_HANDLER default_intexc_handler /* 17: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 18: Reserved */ /* TODO: Adjust Vendor Defined External Interrupts */ - DECLARE_INT_HANDLER eclic_irq19_handler /* 19: Interrupt 19 */ - - DECLARE_INT_HANDLER eclic_irq20_handler /* 20: Interrupt 20 */ - DECLARE_INT_HANDLER eclic_irq21_handler /* 21: Interrupt 21 */ - DECLARE_INT_HANDLER eclic_irq22_handler /* 22: Interrupt 22 */ - DECLARE_INT_HANDLER eclic_irq23_handler /* 23: Interrupt 23 */ - - DECLARE_INT_HANDLER eclic_irq24_handler /* 24: Interrupt 24 */ - DECLARE_INT_HANDLER eclic_irq25_handler /* 25: Interrupt 25 */ - DECLARE_INT_HANDLER eclic_irq26_handler /* 26: Interrupt 26 */ - DECLARE_INT_HANDLER eclic_irq27_handler /* 27: Interrupt 27 */ - - DECLARE_INT_HANDLER eclic_irq28_handler /* 28: Interrupt 28 */ - DECLARE_INT_HANDLER eclic_irq29_handler /* 29: Interrupt 29 */ - DECLARE_INT_HANDLER eclic_irq30_handler /* 30: Interrupt 30 */ - DECLARE_INT_HANDLER eclic_irq31_handler /* 31: Interrupt 31 */ - - DECLARE_INT_HANDLER eclic_irq32_handler /* 32: Interrupt 32 */ - DECLARE_INT_HANDLER eclic_irq33_handler /* 33: Interrupt 33 */ - DECLARE_INT_HANDLER eclic_irq34_handler /* 34: Interrupt 34 */ - DECLARE_INT_HANDLER eclic_irq35_handler /* 35: Interrupt 35 */ - - DECLARE_INT_HANDLER eclic_irq36_handler /* 36: Interrupt 36 */ - DECLARE_INT_HANDLER eclic_irq37_handler /* 37: Interrupt 37 */ - DECLARE_INT_HANDLER eclic_irq38_handler /* 38: Interrupt 38 */ - DECLARE_INT_HANDLER eclic_irq39_handler /* 39: Interrupt 39 */ - - DECLARE_INT_HANDLER eclic_irq40_handler /* 40: Interrupt 40 */ - DECLARE_INT_HANDLER eclic_irq41_handler /* 41: Interrupt 41 */ - DECLARE_INT_HANDLER eclic_irq42_handler /* 42: Interrupt 42 */ - DECLARE_INT_HANDLER eclic_irq43_handler /* 43: Interrupt 43 */ - - DECLARE_INT_HANDLER eclic_irq44_handler /* 44: Interrupt 44 */ - DECLARE_INT_HANDLER eclic_irq45_handler /* 45: Interrupt 45 */ - DECLARE_INT_HANDLER eclic_irq46_handler /* 46: Interrupt 46 */ - DECLARE_INT_HANDLER eclic_irq47_handler /* 47: Interrupt 47 */ - - DECLARE_INT_HANDLER eclic_irq48_handler /* 48: Interrupt 48 */ - DECLARE_INT_HANDLER eclic_irq49_handler /* 49: Interrupt 49 */ - DECLARE_INT_HANDLER eclic_irq50_handler /* 50: Interrupt 50 */ + DECLARE_INT_HANDLER default_intexc_handler /* 19: Interrupt 19 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 20: Interrupt 20 */ + DECLARE_INT_HANDLER default_intexc_handler /* 21: Interrupt 21 */ + DECLARE_INT_HANDLER default_intexc_handler /* 22: Interrupt 22 */ + DECLARE_INT_HANDLER default_intexc_handler /* 23: Interrupt 23 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 24: Interrupt 24 */ + DECLARE_INT_HANDLER default_intexc_handler /* 25: Interrupt 25 */ + DECLARE_INT_HANDLER default_intexc_handler /* 26: Interrupt 26 */ + DECLARE_INT_HANDLER default_intexc_handler /* 27: Interrupt 27 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 28: Interrupt 28 */ + DECLARE_INT_HANDLER default_intexc_handler /* 29: Interrupt 29 */ + DECLARE_INT_HANDLER default_intexc_handler /* 30: Interrupt 30 */ + DECLARE_INT_HANDLER default_intexc_handler /* 31: Interrupt 31 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 32: Interrupt 32 */ + DECLARE_INT_HANDLER default_intexc_handler /* 33: Interrupt 33 */ + DECLARE_INT_HANDLER default_intexc_handler /* 34: Interrupt 34 */ + DECLARE_INT_HANDLER default_intexc_handler /* 35: Interrupt 35 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 36: Interrupt 36 */ + DECLARE_INT_HANDLER default_intexc_handler /* 37: Interrupt 37 */ + DECLARE_INT_HANDLER default_intexc_handler /* 38: Interrupt 38 */ + DECLARE_INT_HANDLER default_intexc_handler /* 39: Interrupt 39 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 40: Interrupt 40 */ + DECLARE_INT_HANDLER default_intexc_handler /* 41: Interrupt 41 */ + DECLARE_INT_HANDLER default_intexc_handler /* 42: Interrupt 42 */ + DECLARE_INT_HANDLER default_intexc_handler /* 43: Interrupt 43 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 44: Interrupt 44 */ + DECLARE_INT_HANDLER default_intexc_handler /* 45: Interrupt 45 */ + DECLARE_INT_HANDLER default_intexc_handler /* 46: Interrupt 46 */ + DECLARE_INT_HANDLER default_intexc_handler /* 47: Interrupt 47 */ + + DECLARE_INT_HANDLER default_intexc_handler /* 48: Interrupt 48 */ + DECLARE_INT_HANDLER default_intexc_handler /* 49: Interrupt 49 */ + DECLARE_INT_HANDLER default_intexc_handler /* 50: Interrupt 50 */ /* Please adjust the above part of interrupt definition code * according to your device interrupt number and its configuration */ From 49a5402dc00f6dfeccc860da74f5c20bc64fe54f Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 30 Mar 2022 10:05:11 +0800 Subject: [PATCH 37/38] env: bump version to v1.0.4 Signed-off-by: Huaqi Fang <578567190@qq.com> --- NMSIS/doc/source/changelog.rst | 6 +++--- NMSIS/doc/source/conf.py | 4 ++-- NMSIS/npk.yml | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/NMSIS/doc/source/changelog.rst b/NMSIS/doc/source/changelog.rst index eb7bc295d..775ea7ded 100644 --- a/NMSIS/doc/source/changelog.rst +++ b/NMSIS/doc/source/changelog.rst @@ -3,10 +3,10 @@ Changelog ========= -V1.0.4-dev ----------- +V1.0.4 +------ -This is the version ``V1.0.4-dev`` release of Nuclei MCU Software Interface Standard(NMSIS), which is still in development. +This is the version ``V1.0.4`` release of Nuclei MCU Software Interface Standard(NMSIS). * **NMSIS-Core** diff --git a/NMSIS/doc/source/conf.py b/NMSIS/doc/source/conf.py index b46ee257a..7166c2e25 100644 --- a/NMSIS/doc/source/conf.py +++ b/NMSIS/doc/source/conf.py @@ -21,10 +21,10 @@ author = 'Nuclei' # The short X.Y version -version = '1.0.4-dev' +version = '1.0.4' # The full version, including alpha/beta/rc tags -release = '1.0.4-dev' +release = '1.0.4' # -- General configuration --------------------------------------------------- diff --git a/NMSIS/npk.yml b/NMSIS/npk.yml index 796934809..4784fd87f 100644 --- a/NMSIS/npk.yml +++ b/NMSIS/npk.yml @@ -1,7 +1,7 @@ ## Package Base Information name: csp-nsdk_nmsis owner: nuclei -version: 1.0.4-dev +version: 1.0.4 description: NMSIS in Nuclei SDK type: csp keywords: From 22e72aae292fb9e0ad4dc10cbff36282025a1985 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Wed, 30 Mar 2022 10:39:03 +0800 Subject: [PATCH 38/38] ci: add release_nmsis job Signed-off-by: Huaqi Fang <578567190@qq.com> --- .gitlab-ci.yml | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 65b8bb49f..da813113c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -190,6 +190,30 @@ release_benchmark: script: - ls -lh NMSIS/Logs +release_nmsis: + stage: release + interruptible: true + only: + refs: + - master + - develop + artifacts: + name: "nmsis_release-${CI_COMMIT_SHA::8}" + paths: + - NMSIS/Core + - NMSIS/DSP/Include + - NMSIS/DSP/PrivateInclude + - NMSIS/NN/Include + - NMSIS/Library + - NMSIS/npk.yml + - NMSIS/build.mk + expire_in: 2 day + dependencies: + - build_library + script: + - ls -lh NMSIS/Library + - cat NMSIS/npk.yml + deploy_website: stage: release only: