From 64f8697e38ee301c1f1a272899ff119e110e78a1 Mon Sep 17 00:00:00 2001 From: David Wang Date: Fri, 18 Aug 2017 11:41:49 +0800 Subject: [PATCH] Disable native and foreign interrupts in thread handlers for arm32 The tee handlers can decide when the native interrupts can be enabled. Signed-off-by: David Wang --- core/arch/arm/kernel/thread_a32.S | 32 +++++++++++++++---------------- core/arch/arm/tee/arch_svc.c | 5 +++++ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/core/arch/arm/kernel/thread_a32.S b/core/arch/arm/kernel/thread_a32.S index c7016f254a2..ebcf492f4ff 100644 --- a/core/arch/arm/kernel/thread_a32.S +++ b/core/arch/arm/kernel/thread_a32.S @@ -656,12 +656,12 @@ thread_abort_handler: thread_und_handler: UNWIND( .fnstart) UNWIND( .cantunwind) -#if defined(CFG_ARM_GICV3) /* - * Disable FIQ which is used as foreign interrupt in GICv3 mode + * Disable both foreign and native interrupts in the thread handlers. + * The tee handlers can decide when the native interrupts should + * be enabled. */ - cpsid f -#endif + cpsid f /* IRQ is already masked by the hardware */ /* * Switch to abort mode to use that stack instead. */ @@ -679,12 +679,12 @@ UNWIND( .cantunwind) b .thread_abort_generic thread_dabort_handler: -#if defined(CFG_ARM_GICV3) /* - * Disable FIQ which is used as foreign interrupt in GICv3 mode + * Disable both foreign and native interrupts in the thread handlers. + * The tee handlers can decide when the native interrupts should + * be enabled. */ - cpsid f -#endif + cpsid f /* IRQ is already masked by the hardware */ push {r0-r11, ip} sub r1, lr, #8 mrs r0, spsr @@ -693,12 +693,12 @@ thread_dabort_handler: b .thread_abort_generic thread_pabort_handler: -#if defined(CFG_ARM_GICV3) /* - * Disable FIQ which is used as foreign interrupt in GICv3 mode + * Disable both foreign and native interrupts in the thread handlers. + * The tee handlers can decide when the native interrupts should + * be enabled. */ - cpsid f -#endif + cpsid f /* IRQ is already masked by the hardware */ push {r0-r11, ip} sub r1, lr, #4 mrs r0, spsr @@ -730,12 +730,12 @@ END_FUNC thread_abort_handler LOCAL_FUNC thread_svc_handler , : UNWIND( .fnstart) UNWIND( .cantunwind) -#if defined(CFG_ARM_GICV3) /* - * Disable FIQ which is used as foreign interrupt in GICv3 mode + * Disable both foreign and native interrupts in the thread handlers. + * The tee handlers can decide when the native interrupts should + * be enabled. */ - cpsid f -#endif + cpsid f /* IRQ is already masked by the hardware */ push {r0-r7, lr} mrs r0, spsr push {r0} diff --git a/core/arch/arm/tee/arch_svc.c b/core/arch/arm/tee/arch_svc.c index a0e78745478..f74bee30044 100644 --- a/core/arch/arm/tee/arch_svc.c +++ b/core/arch/arm/tee/arch_svc.c @@ -196,10 +196,15 @@ void __weak tee_svc_handler(struct thread_svc_regs *regs) size_t scn; size_t max_args; syscall_t scf; + uint32_t state; COMPILE_TIME_ASSERT(ARRAY_SIZE(tee_svc_syscall_table) == (TEE_SCN_MAX + 1)); + /* Enable native interupts */ + state = thread_get_exceptions(); + thread_unmask_exceptions(state & ~THREAD_EXCP_NATIVE_INTR); + thread_user_save_vfp(); /* TA has just entered kernel mode */