The mask of native interrupt in arm32 abort/svc modes

[david-wang-2015]

Hi,
It seems in arm32 mode, the abort/svc handlers don't take care of the native interrupt mask (in GICv2, it's FIQ). After the quick check, it seems for the cpu0 it's masked (I guess BL2 did this?) while for the other cpus, it's unmasked.
Can anybody help me to understand if the native interrupt should or should not be masked in these modes?
I'm doing the fix of GICv3 for these modes as the foreign interrupt is FIQ which is not masked by hardware in arm32.
Thanks.

[jenswi-linaro]

Foreign interrupts should always be masked before the abort/svc handler is called. The svc handler ('tee_svc_handler()`) will enable them if needed.

Native interrupts can be enabled when the svc handler (tee_svc_handler()) is called. I think it should be OK to have native interrupts enabled for abort handler too.

Since we need to make some changes what do you think about this:
Both native and foreign interrupts are masked before the handler is called. Then the handler itself can decide when they can be unmasked.

So basically adding an unconditional cpsid f at the beginning of thread_und_handler(), thread_svc_handler(), thread_pabort_handler() and thread_dabort_handler() and then a call at the beginning of tee_svc_handler() to re-enable native interrupts.

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