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Optee on iMX6UL with barebox bootloader #2477

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vsivanagulu opened this issue Aug 1, 2018 · 6 comments
Closed

Optee on iMX6UL with barebox bootloader #2477

vsivanagulu opened this issue Aug 1, 2018 · 6 comments

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@vsivanagulu
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vsivanagulu commented Aug 1, 2018 •
edited
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We are trying to port optee feature to iMX6UL custom board with barebox bootloader.
When running the xtest, we are getting the below crash report.
Please help me find the issue.
Attached boot log
bootlog.txt
Attached error
log.txt
Reference:
@jforissier
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Hi @vsivanagulu,

Does OP-TEE and the kernel driver initialize properly?
Here is what you should typically see. Messages with a D/TC or I/TC prefix are from OP-TEE core and are sent to the secure console UART ; others are from the Linux kernel. Assuming OP-TEE debug messages are enabled i.e., CFG_TEE_CORE_LOG_LEVEL=3. This is running on HiKey960 (8 cores):

...
D/TC:0 add_phys_mem:526 TEE_SHMEM_START type NSEC_SHM 0x3ee00000 size 0x00200000
D/TC:0 add_phys_mem:526 TA_RAM_START type TA_RAM 0x3f100000 size 0x00f00000
D/TC:0 add_phys_mem:526 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x3f02f000 size 0x000d1000
D/TC:0 add_phys_mem:526 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x3f000000 size 0x0002f000
D/TC:0 add_phys_mem:526 CONSOLE_UART_BASE type IO_NSEC 0xfff00000 size 0x00100000
D/TC:0 verify_special_mem_areas:470 NSEC DDR memory [40000000 c0000000]
D/TC:0 verify_special_mem_areas:470 NSEC DDR memory [0 3e000000]
D/TC:0 add_va_space:565 type RES_VASPACE size 0x00a00000
D/TC:0 add_va_space:565 type SHM_VASPACE size 0x02000000
D/TC:0 dump_mmap_table:698 type TEE_RAM_RX   va 0x3f000000..0x3f02efff pa 0x3f000000..0x3f02efff size 0x0002f000 (smallpg)
D/TC:0 dump_mmap_table:698 type TEE_RAM_RW   va 0x3f02f000..0x3f0fffff pa 0x3f02f000..0x3f0fffff size 0x000d1000 (smallpg)
D/TC:0 dump_mmap_table:698 type NSEC_SHM     va 0x3f100000..0x3f2fffff pa 0x3ee00000..0x3effffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:698 type RES_VASPACE  va 0x3f300000..0x3fcfffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0 dump_mmap_table:698 type SHM_VASPACE  va 0x3fd00000..0x41cfffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0 dump_mmap_table:698 type TA_RAM       va 0x41d00000..0x42bfffff pa 0x3f100000..0x3fffffff size 0x00f00000 (pgdir)
D/TC:0 dump_mmap_table:698 type IO_NSEC      va 0x42c00000..0x42cfffff pa 0xfff00000..0xffffffff size 0x00100000 (pgdir)
D/TC:0 core_mmu_alloc_l2:238 L2 table used: 1/4
I/TC:  
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[0] with top at 0x3f05da38
D/TC:0 init_canaries:164 watch *0x3f05da3c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[1] with top at 0x3f05e078
D/TC:0 init_canaries:164 watch *0x3f05e07c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[2] with top at 0x3f05e6b8
D/TC:0 init_canaries:164 watch *0x3f05e6bc
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[3] with top at 0x3f05ecf8
D/TC:0 init_canaries:164 watch *0x3f05ecfc
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[4] with top at 0x3f05f338
D/TC:0 init_canaries:164 watch *0x3f05f33c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[5] with top at 0x3f05f978
D/TC:0 init_canaries:164 watch *0x3f05f97c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[6] with top at 0x3f05ffb8
D/TC:0 init_canaries:164 watch *0x3f05ffbc
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[7] with top at 0x3f0605f8
D/TC:0 init_canaries:164 watch *0x3f0605fc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[0] with top at 0x3f060e38
D/TC:0 init_canaries:165 watch *0x3f060e3c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[1] with top at 0x3f061678
D/TC:0 init_canaries:165 watch *0x3f06167c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[2] with top at 0x3f061eb8
D/TC:0 init_canaries:165 watch *0x3f061ebc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[3] with top at 0x3f0626f8
D/TC:0 init_canaries:165 watch *0x3f0626fc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[4] with top at 0x3f062f38
D/TC:0 init_canaries:165 watch *0x3f062f3c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[5] with top at 0x3f063778
D/TC:0 init_canaries:165 watch *0x3f06377c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[6] with top at 0x3f063fb8
D/TC:0 init_canaries:165 watch *0x3f063fbc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[7] with top at 0x3f0647f8
D/TC:0 init_canaries:165 watch *0x3f0647fc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[0] with top at 0x3f066838
D/TC:0 init_canaries:167 watch *0x3f06683c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[1] with top at 0x3f068878
D/TC:0 init_canaries:167 watch *0x3f06887c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[2] with top at 0x3f06a8b8
D/TC:0 init_canaries:167 watch *0x3f06a8bc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[3] with top at 0x3f06c8f8
D/TC:0 init_canaries:167 watch *0x3f06c8fc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[4] with top at 0x3f06e938
D/TC:0 init_canaries:167 watch *0x3f06e93c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[5] with top at 0x3f070978
D/TC:0 init_canaries:167 watch *0x3f07097c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[6] with top at 0x3f0729b8
D/TC:0 init_canaries:167 watch *0x3f0729bc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[7] with top at 0x3f0749f8
D/TC:0 init_canaries:167 watch *0x3f0749fc
I/TC:  OP-TEE version: 3.2.0 #1 Wed Aug  1 12:04:20 UTC 2018 arm
D/TC:0 tee_ta_register_ta_store:534 Registering TA store: 'REE' (priority 10)
D/TC:0 tee_ta_register_ta_store:534 Registering TA store: 'Secure Storage TA' (priority 9)
D/TC:0 mobj_mapped_shm_init:559 Shared memory address range: 3fd00000, 41d00000
I/TC:  Initialized
D/TC:0 init_primary_helper:917 Primary CPU switching to normal world boot
...
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.13.0-rc1-linaro-hikey960 (jerome@jfw540) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11)) #102 SMP PREEMPT Wed Aug 1 14:07:18 CEST 2018
[    0.000000] Boot CPU: AArch64 Processor [410fd034]
[    0.000000] Machine model: HiKey960
...
[    0.125515] smp: Bringing up secondary CPUs ...
D/TC:  generic_boot_cpu_on_handler:956 cpu 1: a0 0x3f003458
D/TC:  init_secondary_helper:941 Secondary CPU Switching to normal world boot
D/TC:  generic_boot_cpu_on_handler:956 cpu 2: a0 0x3f003458
D/TC:  init_secondary_helper:941 Secondary CPU Switching to normal world boot
D/TC:  generic_boot_cpu_on_handler:956 cpu 3: a0 0x3f003458
D/TC:  init_secondary_helper:941 Secondary CPU Switching to normal world boot
D/TC:  generic_boot_cpu_on_handler:956 cpu 4: a0 0x3f003458
D/TC:  init_secondary_helper:941 Secondary CPU Switching to normal world boot
D/TC:  generic_boot_cpu_on_handler:956 cpu 5: a0 0x3f003458
D/TC:  init_secondary_helper:941 Secondary CPU Switching to normal world boot
D/TC:  generic_boot_cpu_on_handler:956 cpu 6: a0 0x3f003458
D/TC:  init_secondary_helper:941 Secondary CPU Switching to normal world boot
D/TC:  generic_boot_cpu_on_handler:956 cpu 7: a0 0x3f003458
D/TC:  init_secondary_helper:941 Secondary CPU Switching to normal world boot
...
[    1.534945] optee: probing for conduit method from DT.
[    1.538613] optee: initialized driver

Have you configured the number of CPU cores properly? (CFG_TEE_CORE_NB_CORE).

@vsivanagulu
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vsivanagulu commented Aug 1, 2018 •
edited
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For some reasons the kernel doesn't load anymore and the optee os stops at this point after the logs.
I need to recollect the compilation procedure where the optee-os got loaded and the kernel had started booting!!

`barebox@myi.MX6UL_SOM:/ boot mmc
booting 'mmc'
mmc0: detected SD card version 2.0
mmc0: registered mmc0

Loading ARM Linux zImage '/mnt/mmc/zImage'
Read optee file to 0x9e000000, size 0x00044280
Loading devicetree from '/mnt/mmc/imx6ul-irco-io-board.dtb'
Starting with OP-TEE, adding PSCI device node
commandline:  console=ttymxc0,115200n8  root=/dev/mmcblk0p2 rootwait rw
Starting kernel in secure mode
D/TC:0 add_phys_mem:539 TEE_SHMEM_START type NSEC_SHM 0x9fe00000 size 0x00200000
D/TC:0 add_phys_mem:539 TA_RAM_START type TA_RAM 0x9e100000 size 0x01d00000
D/TC:0 add_phys_mem:539 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x9e03f000 size 0x000c1000
D/TC:0 add_phys_mem:539 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x9e000000 size 0x0003f000
D/TC:0 add_phys_mem:539 ROUNDDOWN(IRAM_BASE, CORE_MMU_DEVICE_SIZE) type TEE_COHERENT 0x00900000 size 0x00100000
D/TC:0 add_phys_mem:539 AIPS3_BASE type IO_SEC 0x02200000 size 0x00100000
D/TC:0 add_phys_mem:539 AIPS2_BASE type IO_SEC 0x02100000 size 0x00100000
D/TC:0 add_phys_mem:539 AIPS1_BASE type IO_SEC 0x02000000 size 0x00100000
D/TC:0 add_phys_mem:539 ANATOP_BASE type IO_SEC 0x02000000 size 0x00200000
D/TC:0 add_phys_mem:552 Physical mem map overlaps 0x2000000
D/TC:0 add_phys_mem:539 GIC_BASE type IO_SEC 0x00a00000 size 0x00100000
D/TC:0 add_phys_mem:539 CONSOLE_UART_BASE type IO_NSEC 0x02000000 size 0x00200000
D/TC:0 verify_special_mem_areas:477 No NSEC DDR memory area defined
D/TC:0 add_va_space:578 type RES_VASPACE size 0x00a00000
D/TC:0 add_va_space:578 type SHM_VASPACE size 0x02000000
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x98c00000..0x98cfffff pa 0x02100000..0x021fffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x98d00000..0x98efffff pa 0x02000000..0x021fffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x98f00000..0x98ffffff pa 0x00a00000..0x00afffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_NSEC      va 0x99000000..0x991fffff pa 0x02000000..0x021fffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type NSEC_SHM     va 0x99200000..0x993fffff pa 0x9fe00000..0x9fffffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type TA_RAM       va 0x99400000..0x9b0fffff pa 0x9e100000..0x9fdfffff size 0x01d00000 (pgdir)
D/TC:0 dump_mmap_table:711 type TEE_COHERENT va 0x9b200000..0x9b2fffff pa 0x00900000..0x009fffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type RES_VASPACE  va 0x9b300000..0x9bcfffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x9be00000..0x9befffff pa 0x02200000..0x022fffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type SHM_VASPACE  va 0x9bf00000..0x9defffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0 dump_mmap_table:711 type TEE_RAM_RX   va 0x9e000000..0x9e03efff pa 0x9e000000..0x9e03efff size 0x0003f000 (smallpg)
D/TC:0 dump_mmap_table:711 type TEE_RAM_RW   va 0x9e03f000..0x9e0fffff pa 0x9e03f000..0x9e0fffff size 0x000c1000 (smallpg)
D/TC:0 core_mmu_alloc_l2:238 L2 table used: 1/4
I/TC:  
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[0] with top at 0x9e03f9b8
D/TC:0 init_canaries:164 watch *0x9e03f9bc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[0] with top at 0x9e044278
D/TC:0 init_canaries:165 watch *0x9e04427c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[0] with top at 0x9e0419f8
D/TC:0 init_canaries:167 watch *0x9e0419fc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[1] with top at 0x9e043a38
D/TC:0 init_canaries:167 watch *0x9e043a3c
E/TC:0 init_fdt:797 Invalid Device Tree at 0x83000000: error -9
E/TC:0 Panic at core/arch/arm/kernel/generic_boot.c:798 <init_fdt>
E/TC:0 Call stack:
E/TC:0  0x9e00560d
D/TC:0 pop_vsp:184 vsp out of bounds 0x9e03f7c0`

@jforissier
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E/TC:0 init_fdt:797 Invalid Device Tree at 0x83000000: error -9

That is -FDT_ERR_BADMAGIC, so yeah, invalid DT blob...

@vsivanagulu
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Well, I tried to load the dtb and zImage of evk(which I believe is proven to work), yet the invalid dtb error shows up!
fyi: if global.bootm.tee=tee.bin is commented in my barebox's /env/boot/mmc, the evk zImage and dtb gets loaded and boots without any problem.

@vsivanagulu
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vsivanagulu commented Aug 2, 2018 •
edited by jbech-linaro
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Hi @jforissier
We compiled the optee-os without address parameters like "CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x80800000 CFG_DT_ADDR=0x83000000 CFG_DT=y DEBUG=y "
so the command to compile optee-os was:
"make PLATFORM=imx-mx6ulevk ARCH=arm CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4"
Now the tee.bin os logs seems to be ok yet the xtest crashes. please attached the attached log file.
log180802-1.txt

barebox@i.MX6UL-SOM:/ boot mmc -v
booting 'mmc'
mmc0: detected SD card version 2.0
mmc0: registered mmc0

Loading ARM Linux zImage '/mnt/mmc/zImage'
OS image not yet relocated
Passing control to ARM zImage handler
no OS load address, defaulting to 0x82000000
no initrd load address, defaulting to 0x82732000
Read optee file to 0x9e000000, size 0x00043280
Loading devicetree from '/mnt/mmc/imx6ul-irco-io-board.dtb'
Starting with OP-TEE, adding PSCI device node
commandline:  console=ttymxc0,115200n8  root=/dev/mmcblk0p2 rootwait rw

Starting kernel at 0x82000000, oftree at 0x82732000...
Starting kernel in secure mode
D/TC:0 add_phys_mem:539 TEE_SHMEM_START type NSEC_SHM 0x9fe00000 size 0x00200000
D/TC:0 add_phys_mem:539 TA_RAM_START type TA_RAM 0x9e100000 size 0x01d00000
D/TC:0 add_phys_mem:539 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x9e03e000 size 0x000c2000
D/TC:0 add_phys_mem:539 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x9e000000 size 0x0003e000
D/TC:0 add_phys_mem:539 ROUNDDOWN(IRAM_BASE, CORE_MMU_DEVICE_SIZE) type TEE_COHERENT 0x00900000 size 0x00100000
D/TC:0 add_phys_mem:539 AIPS3_BASE type IO_SEC 0x02200000 size 0x00100000
D/TC:0 add_phys_mem:539 AIPS2_BASE type IO_SEC 0x02100000 size 0x00100000
D/TC:0 add_phys_mem:539 AIPS1_BASE type IO_SEC 0x02000000 size 0x00100000
D/TC:0 add_phys_mem:539 ANATOP_BASE type IO_SEC 0x02000000 size 0x00200000
D/TC:0 add_phys_mem:552 Physical mem map overlaps 0x2000000
D/TC:0 add_phys_mem:539 GIC_BASE type IO_SEC 0x00a00000 size 0x00100000
D/TC:0 add_phys_mem:539 CONSOLE_UART_BASE type IO_NSEC 0x02000000 size 0x00200000
D/TC:0 verify_special_mem_areas:477 No NSEC DDR memory area defined
D/TC:0 add_va_space:578 type RES_VASPACE size 0x00a00000
D/TC:0 add_va_space:578 type SHM_VASPACE size 0x02000000
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x98c00000..0x98cfffff pa 0x02100000..0x021fffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x98d00000..0x98efffff pa 0x02000000..0x021fffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x98f00000..0x98ffffff pa 0x00a00000..0x00afffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_NSEC      va 0x99000000..0x991fffff pa 0x02000000..0x021fffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type NSEC_SHM     va 0x99200000..0x993fffff pa 0x9fe00000..0x9fffffff size 0x00200000 (pgdir)
D/TC:0 dump_mmap_table:711 type TA_RAM       va 0x99400000..0x9b0fffff pa 0x9e100000..0x9fdfffff size 0x01d00000 (pgdir)
D/TC:0 dump_mmap_table:711 type TEE_COHERENT va 0x9b200000..0x9b2fffff pa 0x00900000..0x009fffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type RES_VASPACE  va 0x9b300000..0x9bcfffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0 dump_mmap_table:711 type IO_SEC       va 0x9be00000..0x9befffff pa 0x02200000..0x022fffff size 0x00100000 (pgdir)
D/TC:0 dump_mmap_table:711 type SHM_VASPACE  va 0x9bf00000..0x9defffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0 dump_mmap_table:711 type TEE_RAM_RX   va 0x9e000000..0x9e03dfff pa 0x9e000000..0x9e03dfff size 0x0003e000 (smallpg)
D/TC:0 dump_mmap_table:711 type TEE_RAM_RW   va 0x9e03e000..0x9e0fffff pa 0x9e03e000..0x9e0fffff size 0x000c2000 (smallpg)
D/TC:0 core_mmu_alloc_l2:238 L2 table used: 1/4
I/TC:  
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[0] with top at 0x9e03e9b8
D/TC:0 init_canaries:164 watch *0x9e03e9bc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[0] with top at 0x9e043278
D/TC:0 init_canaries:165 watch *0x9e04327c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[0] with top at 0x9e0409f8
D/TC:0 init_canaries:167 watch *0x9e0409fc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[1] with top at 0x9e042a38
D/TC:0 init_canaries:167 watch *0x9e042a3c
I/TC:  OP-TEE version: 3.2.0-28-g414060f #9 Thu Aug  2 07:50:06 UTC 2018 arm
D/TC:0 tee_ta_register_ta_store:534 Registering TA store: 'REE' (priority 10)
D/TC:0 tee_ta_register_ta_store:534 Registering TA store: 'Secure Storage TA' (priority 9)
D/TC:0 mobj_mapped_shm_init:559 Shared memory address range: 9bf00000, 9df00000
E/TC:0 plat_rng_init:354 Warning: seeding RNG with zeroes
I/TC:  Initialized
D/TC:0 init_primary_helper:917 Primary CPU switching to normal world boot
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.12.4 (siva@siva-Vostro-3268) (gcc version 4.6.2 (OSELAS.Toolchain-2011.11.1 linaro-4.6-2011.11) ) #13 SMP Tue Jul 31 17:41:19 IST 2018
[    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt: Machine model: IO-Board
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] cma: Reserved 64 MiB at 0x99c00000
.
.
.

@vsivanagulu
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vsivanagulu commented Aug 7, 2018 •
edited
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I changed optee_os versions to 3.0.0 its working now.
Thanks all 👍

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@jforissier @vsivanagulu