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Keil.STM32H7xx_DFP.pdsc
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Keil.STM32H7xx_DFP.pdsc
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<?xml version="1.0" encoding="UTF-8"?>
<package schemaVersion="1.7.36" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/v1.7.36/schema/PACK.xsd">
<vendor>Keil</vendor>
<name>STM32H7xx_DFP</name>
<description overview="Documents/OVERVIEW.md">STMicroelectronics STM32H7 Series Device Support</description>
<url>https://www.keil.com/pack/</url>
<repository type="git">https://github.com/Open-CMSIS-Pack/STM32H7xx_DFP.git</repository>
<license>LICENSE</license>
<licenseSets>
<licenseSet id="all" default="true" gating="true">
<license name="LICENSE" title="Apache 2.0 open-source license" spdx="Apache-2.0"/>
</licenseSet>
</licenseSets>
<releases>
<release version="4.0.0-dev">
Updated for new CMSIS-Toolbox CubeMX integration
Removed CMSIS Drivers
Removed STM32CubeMX_FW_H7
Removed board drivers (ADC, Buttons, GLCD, LED...)
Removed all examples
Removed previous generator (gpdsc)
Added new global generator
Package Description (pdsc):
- Removed Device:Startup component
- Removed Device:STM32Cube HAL components
- Removed Device:STM32Cube LL components
- Removed Board descriptions
- Removed BSP components
- Removed compile device header from device description
- Removed unused conditions
- Replaced documentation files with permalinks
</release>
<release version="3.1.1" date="2023-07-04">
Board Support:
- Updated emWin examples
-- emWin LCD configuration for STM32H743I_EVAL
CMSIS-Driver:
- I2C: Updated I2C_GetPeriClock function implementation
</release>
<release version="3.1.0" date="2023-03-22">
Updated Pack to STM32Cube_FW_H7 Firmware Package version to V1.11.0
Device Support:
- Updated documentation
- Updated SVD files
Pack Description:
- Removed HAL dependency for component ::Device:Startup
- Removed unnecessary Documentation components (STM32H743I-EVAL and STM32H7B3I-EVAL)
Board Support:
- Updated STM32H743I_EVAL and STM32H7B3I_EVAL emWin LCD configuration
Examples:
- Updated linker script files (relating to LTO)
- Updated MPU region for SDRAM and SDRAM configuration
- Corrected EMAC DMA descriptors positioning for toolchains other than GNU
- Added command-line option for placement of unassigned sections (--any_placement=first_fit).
- Updated RTX_Config files
CMSIS-Driver:
- Updated documentation
- Updated necessary variables to volatile to avoid LTO problems
- EMAC:
-- Updated receive functions for HAL zero-copy concept
-- Corrected multicast address filtering
- I2C:
-- Corrected MasterTransmit and MasterReceive functions when not generating STOP condition (when xfer_pending is "true")
-- Corrected Bus Clear functionality
-- Corrected check if I2C peripheral is enabled in the CubeMx and improved user experience if it is not enabled
-- Added support for DMA and Data Cache handling
- MCI:
-- Improved PowerControl and Control functions
- SPI:
-- Corrected GetDataCount implementation
-- Corrected GetStatus function handling of Mode Fault
-- Improved robustness of Initialize, Uninitialize, PowerControl and Control functions
-- Updated DMA and Data Cache handling (improved code readability and maintainability)
- USART:
-- Corrected Flow Control capabilities
-- Corrected GetStatus function and status flags handling
-- Corrected GetTxCount and GetRxCount implementation
-- Updated DMA and Data Cache handling (improved code readability and maintainability)
- USBH:
-- Corrected check if Host mode is enabled
</release>
<release version="3.0.0" date="2022-02-28">
STM32CubeMX integration:
- New workflow concept (incompatible with earlier STM32H7xx_DFPs).
- Automatic migration of projects created with earlier STM32H7xx_DFPs.
- Added STM32CubeMX integration for Dual-core devices.
CMSIS-Driver:
- I2C: Added I2C interface for I2C5 (Driver_I2C5).
- USART:
-- LPUART1 interface accessed by Driver_USART21 (previously by Driver_USART9).
-- Added UART interface for USART9 (Driver_USART9).
-- Added UART interface for USART10 (Driver_USART10).
- MCI:
-- Updated retrieval of SDMMC kernel clock frequency in PowerControl function.
Examples:
- Migrated to new workflow concept.
- Added MPU configuration.
- Added linker scatter files.
</release>
<release version="2.8.0" date="2021-09-13">
Updated Pack to STM32Cube_FW_H7 Firmware Package version V1.9.0.
STM32CubeMX integration:
- Added support for BDMA, I2S, LIBJPEG, RNG, SPDIFRX, VREFBUF configurations (FrameworkCubeMX_gpdsc.ftl).
- Suppressed generation of the condition for the Debug Component (FrameworkCubeMX_gpdsc.ftl).
- Synchronized versions of generated component ::Device:STM32Cube Framework:STM32CubeMX (in gpdsc) and its bootstrap (in pdsc).
Package Description (pdsc):
- Updated schemaVersion (1.7.2).
- Corrected device in board description attribute 'mountedDevice'.
- Corrected RAM settings for STM32H72x, STM32H73x devices.
- Added debugProbe to board description.
- Added global define USE_HAL_DRIVER to the component ::Device:STM32Cube HAL:Common.
- Added global define USE_FULL_LL_DRIVER to the component ::Device:STM32Cube LL:Common.
Devices Support:
- Added SDF files (STM32H743.sdf, STM32H747.sdf).
Flash Programming Algorithms:
- Updated Flash Loader source code (Added CMSIS-CORE component).
CMSIS-Driver:
- Updated disclaimers.
- ETH: Removed Data Cache maintenance. DMA descriptors and frame buffers must be positioned in Non-cacheable memory.
- I2C:
-- Disabled DMA transfers.
-- Corrected pins configuration.
-- Synchronized to HAL V1.10.0.
- MCI:
-- Replaced empty delay loops with _NOP().
-- Improved DCache maintenance.
- SPI: Improved DCache maintenance.
- UART:
-- Added UART interface for LPUART1 (Driver_USART9).
-- Improved DCache maintenance.
- USBH:
-- Fixed port resume occasionally getting stuck in resume signaling.
-- Added compile time configuration for reducing Bulk IN NAK rate.
- USBD:
-- Added support for VBUS sensing.
-- Corrected USBD_GetFrameNumber function.
- OTG: Removed include of stm32h7xx_hal_pcd.h header.
Examples:
- Migrated CubeMX projects to V6.3.0.
- Overridden default HAL_InitTick function.
- Added scatter file to Network examples.
- Updated USB examples for STM32H743I_EVAL board.
- Changed Assembler option to armclang(Auto Select).
- Updated config files to CMSIS 5.8.0.
</release>
<release version="2.7.0" date="2020-10-30">
Devices Support:
- Added device description for STM32H735VGHx, STM32H725VGHx and STM32H725VEHx.
- Updated a subset of SVD files (STM32H723, STM32H73x, STM32H7A3x, STM32H7B3x).
- Updated Reference Manual for STM32H7A3/B3 and STM32H7B0.
</release>
<release version="2.6.0" date="2020-09-11">
Updated Pack to STM32Cube_FW_H7 Firmware Package version V1.8.0:
- Added device support for STM32H72x/H73x with 1MB ad 512 kB flash size.
- Added device support for STM32H730xxQ with 128KB flash size.
- Added support to the OSPI external Loader for the STM32H735G Disco board with ITCM RAM at 0x24000000.
- Updated external flash programming algorithms and added their projects (source code) for:
STM32H747I-EVAL_QSPI, STM32H747I-Disco_QSPI, STM32H7B3I-EVAL_OSPI, STM32H7B0I-EVAL_OSPI, STM32H7B0I-Disco_OSPI, STM32H7B3I-Disco_OSPI, STM32H735G-Disco_OSPI
- Updated SVD files.
- Updated Documentation.
CMSIS-Driver:
- ETH: Added data cache enable bit check.
- MCI:
-- Added handling for separate SD and MMC HAL layers.
-- Added busy signal handling after CMDREND interrupt.
-- Added data cache enable bit check.
Examples:
- Migrated CubeMX projects to V6.0.0
- Updated all USB Host/Device examples with user templates from MDK-Middleware v7.11.1
- Updated emWin driver for STM32H7B3I_EVAL board.
</release>
<release version="2.5.0" date="2020-03-23">
Board Support:
- Added STM32H7B3I_EVAL board support.
-- Blinky example
Flash Programming:
- Updated the internal Flash programming algorithm for STM32H7xxxG devices with 1MB flash size.
- Updated the external FMC-NOR programming algorithm for both STM32H743I Eval Rev B01 (2015) and B03 (2018).
- Added support for the external QSPI programming algorithm for the STM32H747I Disco board.
- Added support for the external MMC programming algorithm for the STM32H750B-Disco board.
</release>
<release version="2.4.0" date="2020-01-29">
Updated Pack to STM32Cube_FW_H7 Firmware Package version V1.6.0 (STM32CubeMX V5.5.0).
This pack adds device support for:
- Value line: STM32H7B0xx.
- Product lines: STM32H7A3xx/HB3xx.
Updated examples to use Arm Compiler 6 and
Added additional Flash Algorithms.
Updated SVD files.
</release>
<release version="2.3.1" date="2019-09-16">
Updated GPDSC freemarker template:
- Added support for IWDG, WWDG peripherals.
- Added support for Timebase Source set to TIMx.
CMSIS-Driver:
- ETH: Corrected GetRxFrameSize and ReadFrame functions to fix long latencies.
Updated board examples:
- Terminating app_main thread with osThreadExit() to avoid endless loop.
- Updated graphics examples for use with Segger emWin version 5.50.
</release>
<release version="2.3.0" date="2019-06-14">
Updated Pack to STM32Cube_FW_H7 Firmware Package version V1.4.0.
Requires STM32CubeMX version 5.2.1.
STM32CubeMX Integration:
- Only supported for single core devices.
- Updated MX_Device_h.ftl:
-- Added parsing of USART virtual mode.
-- Added handling for bracket symbols '(' and ')' in macro generation.
Updated Board Examples for STM32H743I_EVAL:
- Updated to MDK-Middleware V7.8.0.
- Updated to using CMSIS-RTOS2 RTX(Debug/Release).
- Updated to enabling the Event Recorder in debug targets.
CMSIS-Driver:
- CAN: Corrected CAN SRAM read/write to 4 byte accesses.
- ETH: Updated __MEMORY_AT macro supporting AC6.
- FDCAN: Updated __MEMORY_AT macro supporting AC6.
- MCI: Updated to HAL drivers version 1.5.0.
- USART: Updated Get Count functionality.
- USB Host: Enable VDD33USB voltage level detector if internal FS transceiver is used.
- USB Device
-- Updated to HAL drivers version 1.5.0.
-- Updated USBD_EndpointConfigure function to check that maximum packet size requested fits into configured FIFO (compile time configured).
- SPI
-- Corrected DCache Handling
-- Removed __HAL_SPI_ENABLE from SPI_Control function
</release>
<release version="2.2.0" date="2018-09-04">
Updated Pack to STM32Cube_FW_H7 Firmware Package version V1.3.0.
- Updated HAL to version V1.3.0.
Added device support for subfamily STM32H750.
CMSIS Driver:
- USB Device: Corrected transmitted count for non-control IN endpoints
</release>
<release version="2.1.0" date="2018-05-09">
Updated Pack to STM32Cube_FW_H7 Firmware Package version V1.21.0.
Reworked debug description and debug config files.
Updated device documentation.
CMSIS-Driver:
- CAN:
-- Changed FDCAN_ECR_TREC_.. to FDCAN_ECR_REC_.. to align with updated device header.
-- Corrected SetBitrate function.
- SPI: Corrected Slave select handling.
- USART: Corrected UARTx/USARTx related typing mistakes.
- I2C: master clock frequency generation corrected.
Board Support:
- STM32H743I_EVAL:
-- Updated LCDConf.c for STM32H743I_EVAL.
Board Examples:
- Validated using STM32CubeMX version 4.25.0 and STM32Cube_FW_H7 version 1.2.0.
- Updated Abstract.txt in examples reflecting Debug/Release targets.
- Changed Compiler optimization level to "level 1" for Debug target in all examples.
- Updated emWin examples to emWin V5.46e.
- Added Event Recorder to the USB Device and Host examples.
- Added SNMP_Agent Example.
- Updated SMTP_Client example.
</release>
<release version="2.0.0" date="2017-10-02">
This DFP requires STM32CubeMX V4.22.1 and STM32Cube_FW_H7 V1.1.0 or higher to be installed.
New projects require the component 'Device:STM32Cube Framework:STM32CubeMX' for configuration of pins and clocks.
Updated documentation for STM32Cube Framework usage.
Added CMSIS-Driver:
- CAN
- ETH
- I2C
- MCI
- SPI
- UART/USART
- USB Host / Device (no RTOS dependency)
Added example projects for STM32H743I EVAL Board:
- all projects have two targets 'debug' and 'release' and require CMSIS-RTOS2
- Blinky
- CAN
- emWin
- FileSystem
- Network
- USB
</release>
<release version="1.0.1" date="2017-08-03">
fixed location specified in debugvars configfile attribute
</release>
<release version="1.0.0" date="2017-06-01">
Initial release of STM32H7 Device Family Pack.
Based on STM32Cube_FW_H7 Firmware Package version V1.0.0 (2017-04-30)
Board Support for STM32H743I-EVAL Board:
- CMSIS-RTOS2 Blinky
- Fractal Demo
</release>
</releases>
<keywords> <!-- keywords for indexing -->
<keyword>ST</keyword>
<keyword>Device Support</keyword>
<keyword>Device Family Package STMicroelectronics</keyword>
<keyword>STM32H7</keyword>
<keyword>STM32H7xx</keyword>
</keywords>
<devices>
<family Dfamily="STM32H7 Series" Dvendor="STMicroelectronics:13">
<!--book name="Documentation/?.pdf" title="STM32H7xx HAL Drivers"/-->
<algorithm name="CMSIS/Flash/STM32H7B3I_EVAL_FMC-NOR.FLM" start="0x60000000" size="0x04000000" RAMstart="0x24000000" RAMsize="0xA0000" default="0" />
<algorithm name="CMSIS/Flash/MT25TL01G_STM32H747I-DISCO.FLM" start="0x90000000" size="0x08000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<algorithm name="CMSIS/Flash/MTFC4GACAJCN_STM32H750B-DISCO.FLM" start="0xA0000000" size="0x20000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<algorithm name="CMSIS/Flash/STM32H7xx_MT25TL01G.FLM" start="0x90000000" size="0x04000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<algorithm name="CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM" start="0x90000000" size="0x08000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<algorithm name="CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM" start="0x90000000" size="0x08000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<algorithm name="CMSIS/Flash/STM32H743I-eval_FMC.FLM" start="0x60000000" size="0x01000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<algorithm name="CMSIS/Flash/MX25LM51245G_STM32H7B3I-EVAL.FLM" start="0x90000000" size="0x04000000" RAMstart="0x24000000" RAMsize="0xA0000" default="0" />
<algorithm name="CMSIS/Flash/MX25LM51245G_STM32H7B3I-Disco.FLM" start="0x90000000" size="0x04000000" RAMstart="0x24000000" RAMsize="0xA0000" default="0" />
<algorithm name="CMSIS/Flash/MX25LM51245G_STM32H7B0-EVAL.FLM" start="0x90000000" size="0x04000000" RAMstart="0x24000000" RAMsize="0xA0000" default="0" />
<algorithm name="CMSIS/Flash/MX25LM51245G_STM32H7B0-Disco.FLM" start="0x90000000" size="0x04000000" RAMstart="0x24000000" RAMsize="0xA0000" default="0" />
<algorithm name="CMSIS/Flash/MX25LM51245G_STM32H735-Disco.FLM" start="0x90000000" size="0x04000000" RAMstart="0x24000000" RAMsize="0xFFF4" default="0" />
<algorithm name="CMSIS/Flash/MT25TL01G_STM32H747I-EVAL.FLM" start="0x90000000" size="0x08000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<!-- obsolete algorithms -->
<algorithm name="CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM" start="0x90000000" size="0x08000000" RAMstart="0x20000000" RAMsize="0xFFF4" default="0" />
<description>
The STM32H7 series now includes dual-core microcontrollers with Arm Cortex-M7 and Cortex-M4 cores able to run up to 480 MHz and 240 MHz respectively.
Our single-core Cortex-M7 STM32H7 series also benefits from this frequency increase and can now run up to 480 MHz as well.
Dual-core STM32H7 microcontrollers are available with an embedded SMPS for improved dynamic power efficiency.
Extended temperature range support up to 125 C (*) (ambient) will be available for certain devices for use in harsh environments including industrial applications.
STM32H7 devices embedding a crypto/hash processor support security services such as Secure Firmware Install and Secure Boot - Secure Firmware Upgrade allowing the installation of new application code in a secured manner.
All the other features that have made single-core STM32H7 MCUs a success are still available in the dual-core versions.
The STM32H7 series remains more than ever the microcontroller with an embedded Flash memory offering the highest performance on the market.
</description>
<sequences>
<!-- Override for Pre-Defined Sequences -->
<sequence name="TraceStart">
<block>
__var traceSWO = (__traceout & 0x1) != 0; // SWO (asynchronous) Trace Selected?
__var traceTPIU = (__traceout & 0x2) != 0; // TPIU (synchronous) Trace Selected?
</block>
<control if="traceSWO">
<block>
Sequence("EnableTraceSWO"); // Call SWO Trace Setup
</block>
</control>
<control if="traceTPIU">
<block>
Sequence("EnableTraceTPIU"); // Call TPIU Trace Setup
</block>
</control>
</sequence>
<sequence name="TraceStop">
<block>
// Nothing required for SWO Trace
__var traceSWO = (__traceout & 0x1) != 0; // SWO enabled?
__var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled?
</block>
<control if="traceSWO">
<block>
Sequence("DisableTraceSWO");
</block>
</control>
<control if="traceTPIU">
<block>
Sequence("DisableTraceTPIU");
</block>
</control>
</sequence>
<!-- User-Defined Sequences -->
<sequence name="CheckID">
<block>
__var pidr1 = 0;
__var pidr2 = 0;
__var jep106id = 0;
__var ROMTableBase = 0;
__ap = 2; // System debug access port (APB-AP)
ROMTableBase = ReadAP(0xF8) & ~0x3;
pidr1 = Read32(ROMTableBase + 0x0FE4);
pidr2 = Read32(ROMTableBase + 0x0FE8);
jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF);
</block>
<control if="jep106id != 0x20">
<block>
Query(0, "Not a genuine ST Device! Abort connection", 1);
Message(2, "Not a genuine ST Device! Abort connection.");
</block>
</control>
</sequence>
<sequence name="EnableTraceSWO">
<block>
__var value = 0;
Sequence("ConfigureTraceSWOPin");
__ap = 2; // Switch to System Debug Access Port
// Enable Trace Clock
// not necessary because already done in "DebugDeviceUnlock".
// Configure SWO Funnel (SWTF) at 0xE00E4000
value = Read32(0xE00E4000); // Read Trace Funnel CONTROL Register
value &= 0x00000F00; // Preserve Hold Time Settings,
value |= 0x00000001; // Enable ITM slave ports
Write32(0xE00E4000, value); // Update Trace Funnel CONTROL Register
</block>
</sequence>
<sequence name="DisableTraceSWO">
<block>
__var value = 0;
__ap = 2; // Switch to System Debug Access Port
// Disable Trace Clock
value = Read32(0xE00E1004); // Read DBGMCU_CR
value &= ~0x00100000; // DBGMCU_CR[20] : set TraceClkEn
Write32(0xE00E1004, value); // Update DBGMCU_CR
// Configure SWO Funnel (SWTF) at 0xE00E4000
value = Read32(0xE00E4000); // Read Trace Funnel CONTROL Register
value &= 0x00000F00; // Preserve Hold Time Settings, disable active slave ports
Write32(0xE00E4000, value); // Update Trace Funnel CONTROL Register
</block>
</sequence>
<sequence name="EnableTraceTPIU">
<block>
__var value = 0;
Sequence("ConfigureTraceTPIUPins");
__ap = 2; // Switch to System Debug Access Port
// Enable Trace Clock
// not necessary because already done in "DebugDeviceUnlock".
// Configure CoreSight Trace Funnel (CSTF) at 0xE00F3000
value = Read32(0xE00F3000); // Read Trace Funnel CONTROL Register
value &= 0x00000F00; // Preserve Hold Time Settings
value |= 0x00000003; // Enable ITM and ETM slave ports
Write32(0xE00F3000, value); // Update Trace Funnel CONTROL Register
</block>
</sequence>
<sequence name="DisableTraceTPIU">
<block>
__var value = 0;
__ap = 2; // Switch to System Debug Access Port
// Disable Trace Clock
value = Read32(0xE00E1004); // Read DBGMCU_CR
value &= ~0x00100000; // DBGMCU_CR[20] : set TraceClkEn
Write32(0xE00E1004, value); // Update DBGMCU_CR
// Configure CoreSight Trace Funnel (CSTF) at 0xE00F3000
value = Read32(0xE00F3000); // Read Trace Funnel CONTROL Register
value &= 0x00000FFC; // Preserve Hold Time Settings and other possibly set slave ports
Write32(0xE00F3000, value); // Update Trace Funnel CONTROL Register
</block>
</sequence>
<sequence name="ConfigureTraceSWOPin">
<block>
__var pin = 0;
__var port = 0;
__var portAdr = 0;
__var pos = 0;
__var SWO_Pin = 0x00010003; // PB3
</block>
<!-- configure SWO -->
<block info="configure SWO">
pin = ((SWO_Pin ) & 0x0000FFFF);
port = ((SWO_Pin >> 16) & 0x0000FFFF);
portAdr = 0x58020000 + (((SWO_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x58024540, ((Read32(0x58024540 ) ) | (1 << port)) ); // RCC_C1_AHB4ENR:IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</sequence>
<sequence name="ConfigureTraceTPIUPins">
<block>
__var pin = 8;
__var port = 0;
__var portAdr = 0;
__var pos = 0;
__var width = (__traceout & 0x003F0000) >> 16;
</block>
<!-- configure TRACECLK -->
<block info="configure TRACECLK">
pin = (TraceClk_Pin ) & 0x0000FFFF;
port = (TraceClk_Pin >> 16) & 0x0000FFFF;
portAdr = 0x58020000 + (((TraceClk_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x58024540, ((Read32(0x58024540 ) ) | (1 << port)) ); // RCC_C1_AHB4ENR:IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
<control if="width >= 1" info="TPIU port width 1">
<!-- configure TRACED0 -->
<block info="configure TRACED0">
pin = (TraceD0_Pin ) & 0x0000FFFF;
port = (TraceD0_Pin >> 16) & 0x0000FFFF;
portAdr = 0x58020000 + (((TraceD0_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x58024540, ((Read32(0x58024540 ) ) | (1 << port)) ); // RCC_C1_AHB4ENR:IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</control>
<control if="width >= 2" info="TPIU port width 2">
<!-- configure TRACED1 -->
<block info="configure TRACED1">
pin = (TraceD1_Pin ) & 0x0000FFFF;
port = (TraceD1_Pin >> 16) & 0x0000FFFF;
portAdr = 0x58020000 + (((TraceD1_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x58024540, ((Read32(0x58024540 ) ) | (1 << port)) ); // RCC_C1_AHB4ENR:IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</control>
<control if="width >= 4" info="TPIU port width 4">
<!-- configure TRACED2 -->
<block info="configure TRACED2">
pin = (TraceD2_Pin ) & 0x0000FFFF;
port = (TraceD2_Pin >> 16) & 0x0000FFFF;
portAdr = 0x58020000 + (((TraceD2_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x58024540, ((Read32(0x58024540 ) ) | (1 << port)) ); // RCC_C1_AHB4ENR:IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
<!-- configure TRACED3 -->
<block info="configure TRACED3">
pin = (TraceD3_Pin ) & 0x0000FFFF;
port = (TraceD3_Pin >> 16) & 0x0000FFFF;
portAdr = 0x58020000 + (((TraceD3_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x58024540, ((Read32(0x58024540 ) ) | (1 << port)) ); // RCC_C1_AHB4ENR:IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</control>
</sequence>
</sequences>
<!-- ************************ Subfamily 'STM32H742' **************************** -->
<subFamily DsubFamily="STM32H742">
<processor Dcore="Cortex-M7" DcoreVersion="r0p1" Dclock="480000000" Dmpu="MPU" Dfpu="DP_FPU" Dendian="Little-endian"/>
<book name="https://developer.arm.com/documentation/dui0646/latest" title="Cortex-M7 Generic User Guide"/>
<debug svd="CMSIS/SVD/STM32H742.svd"/>
<compile define="STM32H742xx"/>
<book name="https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf" title="STM32H742, STM32H743/753 and STM32H750 Reference Manual"/>
<book name="https://www.st.com/resource/en/datasheet/stm32h743vi.pdf" title="STM32H742xI/G STM32H743xI/G Data Sheet"/>
<debugvars configfile="CMSIS/Debug/STM32H742_743_753_750.dbgconf" version="1.1.0">
// Debug Access Variables, can be modified by user via copies of DBGCONF files as created by uVision. Also see sub-family level.
__var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBGMCU configuration register
// [ 8] DBGSTBY_D3, [ 7] DBGSTOP_D3
// [ 2] DBGSTBY_D1, [ 1] DBGSTOP_D1, [ 0] DBGSLEEP_D1
__var DbgMCU_APB3_Fz1 = 0x00000000; // DBGMCU_APB3FZ1: DBGMCU APB3 peripheral freeze register
__var DbgMCU_APB1L_Fz1 = 0x00000000; // DBGMCU_APB1LFZ1: DBGMCU APB1L peripheral freeze register
__var DbgMCU_APB2_Fz1 = 0x00000000; // DBGMCU_APB2FZ1: DBGMCU APB2 peripheral freeze register
__var DbgMCU_APB4_Fz1 = 0x00000000; // DBGMCU_APB4FZ1: DBGMCU APB4 peripheral freeze register
__var TraceClk_Pin = 0x00040002; // PE2
__var TraceD0_Pin = 0x00040003; // PE3
__var TraceD1_Pin = 0x00040004; // PE4
__var TraceD2_Pin = 0x00040005; // PE5
__var TraceD3_Pin = 0x00040006; // PE6
</debugvars>
<sequences>
<sequence name="DebugDeviceUnlock">
<block>
__var value = 0;
Sequence("CheckID");
__ap = 2; // Switch to System Debug Access Port
value = Read32(0xE00E1004); // Read DBGMCU_CR
value |= 0x00670000; // set preset values (enable all debug clocks by default)
// DBGMCU_CR[18] CKDBGD3EN, [17] CKDBGD2EN, [16] CKDBGD1EN
// DBGMCU_CR[22] D3DBGCKEN, [21] D1DBGCKEN
</block>
<control if="__traceout"> <!-- Enable Trace Clock and hence access to global trace components now -->
<block>
value |= 0x00100000; // DBGMCU_CR[20] TRACECLKEN
</block>
</control>
<block>
Write32(0xE00E1004, value); // Update DBGMCU_CR
</block>
<block info="DbgMCU registers">
Write32(0xE00E1004 , DbgMCU_CR | value); // DBGMCU_CR: Configure MCU Debug
Write32(0xE00E1034 , DbgMCU_APB3_Fz1 ); // DBGMCU_APB3FZ1: Configure APB3 peripheral freeze behavior
Write32(0xE00E103C , DbgMCU_APB1L_Fz1 ); // DBGMCU_APB1LFZ1: Configure APB1L peripheral freeze behavior
Write32(0xE00E104C , DbgMCU_APB2_Fz1 ); // DBGMCU_APB2FZ1: Configure APB2 peripheral freeze behavior
Write32(0xE00E1054 , DbgMCU_APB4_Fz1 ); // DBGMCU_APB4FZ1: Configure APB4 peripheral freeze behavior
</block>
</sequence>
</sequences>
<algorithm name="CMSIS/Flash/STM32H7x_2048.FLM" start="0x08000000" size="0x00200000" RAMstart="0x20000000" RAMsize="0x8000" default="1" />
<memory name="DTCMRAM" access="rwx" start="0x20000000" size="0x00020000" default="0" init="0"/>
<memory name="RAM_D1" access="rwx" start="0x24000000" size="0x00060000" default="1" init="0"/>
<memory name="RAM_D2" access="rwx" start="0x30000000" size="0x00008000" default="1" init="0"/>
<memory name="RAM_D2S2" access="rwx" start="0x30020000" size="0x00004000" default="1" init="0"/>
<memory name="RAM_D3" access="rwx" start="0x38000000" size="0x00010000" default="1" init="0"/>
<!--memory name="ITCMRAM" access="rwx" start="0x00000000" size="0x00010000" default="1" init="0"/-->
<!-- ************************* Device 'STM32H742AGIx' ***************************** -->
<device Dname="STM32H742AGIx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="BGA" n="169"/>
</device>
<!-- ************************* Device 'STM32H742AIIx' ***************************** -->
<device Dname="STM32H742AIIx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="BGA" n="169"/>
</device>
<!-- ************************* Device 'STM32H742BGTx' ***************************** -->
<device Dname="STM32H742BGTx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="QFP" n="208"/>
</device>
<!-- ************************* Device 'STM32H742BITx' ***************************** -->
<device Dname="STM32H742BITx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="QFP" n="208"/>
</device>
<!-- ************************* Device 'STM32H742IGKx' ***************************** -->
<device Dname="STM32H742IGKx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H742IGTx' ***************************** -->
<device Dname="STM32H742IGTx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="QFP" n="176"/>
</device>
<!-- ************************* Device 'STM32H742IIKx' ***************************** -->
<device Dname="STM32H742IIKx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H742IITx' ***************************** -->
<device Dname="STM32H742IITx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="QFP" n="176"/>
</device>
<!-- ************************* Device 'STM32H742VGHx' ***************************** -->
<device Dname="STM32H742VGHx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="BGA" n="100"/>
</device>
<!-- ************************* Device 'STM32H742VGTx' ***************************** -->
<device Dname="STM32H742VGTx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="QFP" n="100"/>
</device>
<!-- ************************* Device 'STM32H742VIHx' ***************************** -->
<device Dname="STM32H742VIHx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="BGA" n="100"/>
</device>
<!-- ************************* Device 'STM32H742VITx' ***************************** -->
<device Dname="STM32H742VITx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="QFP" n="100"/>
</device>
<!-- ************************* Device 'STM32H742XGHx' ***************************** -->
<device Dname="STM32H742XGHx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="BGA" n="240"/>
</device>
<!-- ************************* Device 'STM32H742XIHx' ***************************** -->
<device Dname="STM32H742XIHx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="BGA" n="240"/>
</device>
<!-- ************************* Device 'STM32H742ZGTx' ***************************** -->
<device Dname="STM32H742ZGTx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="QFP" n="144"/>
</device>
<!-- ************************* Device 'STM32H742ZITx' ***************************** -->
<device Dname="STM32H742ZITx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="QFP" n="144"/>
</device>
</subFamily>
<!-- ************************ Subfamily 'STM32H743' **************************** -->
<subFamily DsubFamily="STM32H743">
<processor Dcore="Cortex-M7" DcoreVersion="r0p1" Dclock="480000000" Dmpu="MPU" Dfpu="DP_FPU" Dendian="Little-endian"/>
<!-- Debug configuration settings -->
<debugconfig default="swd" swj="true" clock="400000000" sdf="CMSIS/Debug/STM32H743.sdf"/>
<debug svd="CMSIS/SVD/STM32H743.svd"/>
<compile define="STM32H743xx"/>
<book name="https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf" title="STM32H742, STM32H743/753 and STM32H750 Reference Manual"/>
<book name="https://www.st.com/resource/en/datasheet/stm32h743vi.pdf" title="STM32H742xI/G STM32H743xI/G Data Sheet"/>
<book name="https://developer.arm.com/documentation/dui0646/latest" title="Cortex-M7 Generic User Guide"/>
<debugvars configfile="CMSIS/Debug/STM32H742_743_753_750.dbgconf" version="1.1.0">
// Debug Access Variables, can be modified by user via copies of DBGCONF files as created by uVision. Also see sub-family level.
__var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBGMCU configuration register
// [ 8] DBGSTBY_D3, [ 7] DBGSTOP_D3
// [ 2] DBGSTBY_D1, [ 1] DBGSTOP_D1, [ 0] DBGSLEEP_D1
__var DbgMCU_APB3_Fz1 = 0x00000000; // DBGMCU_APB3FZ1: DBGMCU APB3 peripheral freeze register
__var DbgMCU_APB1L_Fz1 = 0x00000000; // DBGMCU_APB1LFZ1: DBGMCU APB1L peripheral freeze register
__var DbgMCU_APB2_Fz1 = 0x00000000; // DBGMCU_APB2FZ1: DBGMCU APB2 peripheral freeze register
__var DbgMCU_APB4_Fz1 = 0x00000000; // DBGMCU_APB4FZ1: DBGMCU APB4 peripheral freeze register
__var TraceClk_Pin = 0x00040002; // PE2
__var TraceD0_Pin = 0x00040003; // PE3
__var TraceD1_Pin = 0x00040004; // PE4
__var TraceD2_Pin = 0x00040005; // PE5
__var TraceD3_Pin = 0x00040006; // PE6
</debugvars>
<sequences>
<sequence name="DebugDeviceUnlock">
<block>
__var value = 0;
Sequence("CheckID");
__ap = 2; // Switch to System Debug Access Port
value = Read32(0xE00E1004); // Read DBGMCU_CR
value |= 0x00670000; // set preset values (enable all debug clocks by default)
// DBGMCU_CR[18] CKDBGD3EN, [17] CKDBGD2EN, [16] CKDBGD1EN
// DBGMCU_CR[22] D3DBGCKEN, [21] D1DBGCKEN
</block>
<control if="__traceout"> <!-- Enable Trace Clock and hence access to global trace components now -->
<block>
value |= 0x00100000; // DBGMCU_CR[20] TRACECLKEN
</block>
</control>
<block>
Write32(0xE00E1004, value); // Update DBGMCU_CR
</block>
<block info="DbgMCU registers">
Write32(0xE00E1004 , DbgMCU_CR | value); // DBGMCU_CR: Configure MCU Debug
Write32(0xE00E1034 , DbgMCU_APB3_Fz1 ); // DBGMCU_APB3FZ1: Configure APB3 peripheral freeze behavior
Write32(0xE00E103C , DbgMCU_APB1L_Fz1 ); // DBGMCU_APB1LFZ1: Configure APB1L peripheral freeze behavior
Write32(0xE00E104C , DbgMCU_APB2_Fz1 ); // DBGMCU_APB2FZ1: Configure APB2 peripheral freeze behavior
Write32(0xE00E1054 , DbgMCU_APB4_Fz1 ); // DBGMCU_APB4FZ1: Configure APB4 peripheral freeze behavior
</block>
</sequence>
</sequences>
<algorithm name="CMSIS/Flash/STM32H7x_2048.FLM" start="0x08000000" size="0x00200000" RAMstart="0x20000000" RAMsize="0x8000" default="1" />
<memory name="DTCMRAM" access="rwx" start="0x20000000" size="0x00020000" default="0" init="0"/>
<memory name="RAM_D1" access="rwx" start="0x24000000" size="0x00080000" default="1" init="0"/>
<memory name="RAM_D2" access="rwx" start="0x30000000" size="0x00048000" default="1" init="0"/>
<memory name="RAM_D3" access="rwx" start="0x38000000" size="0x00010000" default="1" init="0"/>
<!--memory name="ITCMRAM" access="rwx" start="0x00000000" size="0x00010000" default="1" init="0"/-->
<!-- ************************* Device 'STM32H743AGIx' ***************************** -->
<device Dname="STM32H743AGIx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="BGA" n="169"/>
</device>
<!-- ************************* Device 'STM32H743AIIx' ***************************** -->
<device Dname="STM32H743AIIx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="BGA" n="169"/>
</device>
<!-- ************************* Device 'STM32H743BGTx' ***************************** -->
<device Dname="STM32H743BGTx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="QFP" n="208"/>
</device>
<!-- ************************* Device 'STM32H743BITx' ***************************** -->
<device Dname="STM32H743BITx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="QFP" n="208"/>
</device>
<!-- ************************* Device 'STM32H743IGKx' ***************************** -->
<device Dname="STM32H743IGKx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H743IGTx' ***************************** -->
<device Dname="STM32H743IGTx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="QFP" n="169"/>
</device>
<!-- ************************* Device 'STM32H743IIKx' ***************************** -->
<device Dname="STM32H743IIKx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H743IITx' ***************************** -->
<device Dname="STM32H743IITx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00100000" default="1" startup="1"/>
<feature type="QFP" n="176"/>
</device>
<!-- ************************* Device 'STM32H743VGHx' ***************************** -->
<device Dname="STM32H743VGHx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="BGA" n="100"/>
</device>
<!-- ************************* Device 'STM32H743VGTx' ***************************** -->
<device Dname="STM32H743VGTx">
<memory name="FLASH_Bank1" access="rx" start="0x08000000" size="0x00080000" default="1" startup="1"/>
<memory name="FLASH_Bank2" access="rx" start="0x08100000" size="0x00080000" default="1" startup="1"/>
<feature type="QFP" n="100"/>
</device>