From 2d6f15b5e5ef2160276f88868478377dea3884e1 Mon Sep 17 00:00:00 2001 From: xiaoxiaohehe001 Date: Thu, 11 May 2023 05:19:29 +0000 Subject: [PATCH 1/2] support_act --- paddle/fluid/inference/tensorrt/op_teller.cc | 57 ++----------------- .../inference/test_trt_convert_activation.py | 17 +++++- test/ir/inference/test_trt_convert_gelu.py | 14 +++-- 3 files changed, 32 insertions(+), 56 deletions(-) diff --git a/paddle/fluid/inference/tensorrt/op_teller.cc b/paddle/fluid/inference/tensorrt/op_teller.cc index 84712e9aa6294..9a59d4f93aac7 100644 --- a/paddle/fluid/inference/tensorrt/op_teller.cc +++ b/paddle/fluid/inference/tensorrt/op_teller.cc @@ -105,7 +105,8 @@ struct SimpleOpTypeSetTeller : public Teller { "erf", "floor", "round", "sign", "silu", "logical_not", "reciprocal", "tanh_shrink", "logsigmoid", - "rsqrt", "swish"}; + "rsqrt", "swish", "hard_sigmoid", + "hard_swish", "leaky_relu"}; std::unordered_set unary_list = { "exp", "log", "sqrt", "abs", "sin", "cos", "tan", "tanh", "sinh", "cosh", @@ -967,20 +968,6 @@ struct SimpleOpTypeSetTeller : public Teller { } } - if (op_type == "hard_swish") { - if (desc.Input("X").size() != 1) { - VLOG(3) << "HardSwish op has only 1 input, but got " - << desc.Input("X").size(); - return false; - } - - if (desc.Output("Out").size() != 1) { - VLOG(3) << "HardSwish op has only 1 output, but got " - << desc.Output("Out").size(); - return false; - } - } - if (op_type == "squeeze2") { // If Attribute is Variable(s), HasAttr() will return False if (!desc.HasAttr("axes", /*with_attr_var=*/false)) { @@ -1646,8 +1633,10 @@ struct SimpleOpTypeSetTeller : public Teller { auto x_var_name = desc.Input("X")[0]; auto* x_var_desc = block->FindVar(x_var_name); const auto x_shape = x_var_desc->GetShape(); - if (x_shape.size() == 1) { - VLOG(3) << "gelu op does not support input's dim is 1 in tensorrt."; + if (!with_dynamic_shape && (x_shape.size() == 1 || x_shape.size() == 0)) { + VLOG(3) << op_type + << "gelu op does not support input's dim is 1 or 0 in tensorrt " + "static shape mode."; return false; } } @@ -1737,20 +1726,6 @@ struct SimpleOpTypeSetTeller : public Teller { } } - if (op_type == "leaky_relu") { - if (desc.Input("X").size() != 1) { - VLOG(3) << "Invalid number of TRT leaky_relu op converter " - "inputs. Expected 1, but received " - << desc.Input("X").size(); - return false; - } - if (desc.Output("Out").size() != 1) { - VLOG(3) << "output of leaky_relu op converter should be 1, got " - << desc.Output("Out").size(); - return false; - } - } - if (op_type == "pad") { if (!desc.HasAttr("pad_value") || !desc.HasAttr("paddings")) return false; const float pad_value = @@ -2390,26 +2365,6 @@ struct SimpleOpTypeSetTeller : public Teller { } } - if (op_type == "hard_sigmoid") { - if (!with_dynamic_shape) { - auto* block = desc.Block(); - if (block == nullptr) { - VLOG(3) << "The block desc is nullptr, we can't continue to analyze. " - "Developers need to check whether block_desc is passed in " - "the pass."; - return false; - } - auto x_var_name = desc.Input("X")[0]; - auto* x_var_desc = block->FindVar(x_var_name); - const auto x_shape = x_var_desc->GetShape(); - if (x_shape.size() == 1) { - VLOG(3) << "Hard sigmoid does not support 1-dimensional input in " - "tensorrt"; - return false; - } - } - } - if (op_type == "cast") { // trt 6015 result in Windows ppyolo_mbv3 TRT fp32 diff #if !IS_TRT_VERSION_GE(7000) diff --git a/test/ir/inference/test_trt_convert_activation.py b/test/ir/inference/test_trt_convert_activation.py index 4b7052e682da7..6c76e7bc0892f 100644 --- a/test/ir/inference/test_trt_convert_activation.py +++ b/test/ir/inference/test_trt_convert_activation.py @@ -60,6 +60,9 @@ def generate_input1(dims, batch, attrs: List[Dict[str, Any]]): "logsigmoid", "tanh_shrink", "softplus", + "hard_swish", + "hard_sigmoid", + "leaky_relu", ]: # few samples to reduce time # for beta in [-0.2, 0.5, 0.67, 3]: @@ -80,6 +83,18 @@ def generate_input1(dims, batch, attrs: List[Dict[str, Any]]): dics = [{"threshold": alpha}] if op_type == "softplus": dics = [{"beta": beta}] + if op_type == "hard_swish": + dics = [ + { + "threshold": 6.0, + "scale": 6.0, + "offset": 3.0, + } + ] + if op_type == "hard_sigmoid": + dics = [{"slope": beta, "offset": alpha}] + if op_type == "leaky_relu": + dics = [{"alpha": alpha}] ops_config = [ { @@ -152,7 +167,7 @@ def generate_trt_nodes_num(attrs, dynamic_shape): + runtime_version[2] * 10 < 8600 and self.dims == 0 - ) and program_config.ops[0].type in ["celu", "logsigmoid"]: + ) and program_config.ops[0].type in ["celu", "logsigmoid", "silu"]: return 0, 3 return 1, 2 diff --git a/test/ir/inference/test_trt_convert_gelu.py b/test/ir/inference/test_trt_convert_gelu.py index 6fe2d7819de91..1f3847ff207c0 100644 --- a/test/ir/inference/test_trt_convert_gelu.py +++ b/test/ir/inference/test_trt_convert_gelu.py @@ -29,7 +29,9 @@ def is_program_valid(self, program_config: ProgramConfig) -> bool: def sample_program_configs(self): def generate_input1(dims, attrs: List[Dict[str, Any]]): - if dims == 1: + if dims == 0: + return np.ones([]).astype(np.float32) + elif dims == 1: return np.ones([32]).astype(np.float32) elif dims == 2: return np.ones([3, 32]).astype(np.float32) @@ -38,7 +40,7 @@ def generate_input1(dims, attrs: List[Dict[str, Any]]): else: return np.ones([1, 3, 32, 32]).astype(np.float32) - for dims in [1, 2, 3, 4]: + for dims in [0, 1, 2, 3, 4]: for approximate in [True, False]: self.dims = dims dics = [{"approximate": approximate}] @@ -70,7 +72,11 @@ def sample_predictor_configs( self, program_config ) -> (paddle_infer.Config, List[int], float): def generate_dynamic_shape(attrs): - if self.dims == 1: + if self.dims == 0: + self.dynamic_shape.min_input_shape = {"input_data": []} + self.dynamic_shape.max_input_shape = {"input_data": []} + self.dynamic_shape.opt_input_shape = {"input_data": []} + elif self.dims == 1: self.dynamic_shape.min_input_shape = {"input_data": [1]} self.dynamic_shape.max_input_shape = {"input_data": [64]} self.dynamic_shape.opt_input_shape = {"input_data": [32]} @@ -104,7 +110,7 @@ def generate_trt_nodes_num(attrs, dynamic_shape): runtime_version = paddle_infer.get_trt_runtime_version() self.assertTrue(compile_version == runtime_version) # Dimension one only runs on Paddle OP - if self.dims == 1: + if not dynamic_shape and (self.dims == 1 or self.dims == 0): return 0, 3 if compile_version >= valid_version: return 1, 2 From bcc59de6872dd09781d1b0f3f91b0ac8e2e7c1ad Mon Sep 17 00:00:00 2001 From: xiaoxiaohehe001 Date: Thu, 11 May 2023 05:34:16 +0000 Subject: [PATCH 2/2] delete_silu --- paddle/fluid/inference/tensorrt/op_teller.cc | 13 ++++++------- test/ir/inference/test_trt_convert_activation.py | 2 +- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/paddle/fluid/inference/tensorrt/op_teller.cc b/paddle/fluid/inference/tensorrt/op_teller.cc index 9a59d4f93aac7..21547331aa08f 100644 --- a/paddle/fluid/inference/tensorrt/op_teller.cc +++ b/paddle/fluid/inference/tensorrt/op_teller.cc @@ -108,13 +108,12 @@ struct SimpleOpTypeSetTeller : public Teller { "rsqrt", "swish", "hard_sigmoid", "hard_swish", "leaky_relu"}; std::unordered_set unary_list = { - "exp", "log", "sqrt", "abs", "sin", - "cos", "tan", "tanh", "sinh", "cosh", - "asin", "acos", "atan", "asinh", "acosh", - "atanh", "ceil", "celu", "floor", "round", - "sign", "silu", "logical_not", "reciprocal", "tanh_shrink", - "logsigmoid", "erf", "bitwise_not", "equal", "not_equal", - "rsqrt"}; + "exp", "log", "sqrt", "abs", "sin", + "cos", "tan", "tanh", "sinh", "cosh", + "asin", "acos", "atan", "asinh", "acosh", + "atanh", "ceil", "celu", "floor", "round", + "sign", "logical_not", "reciprocal", "tanh_shrink", "logsigmoid", + "erf", "bitwise_not", "equal", "not_equal", "rsqrt"}; if (act_op_list.find(op_type) != act_op_list.end()) { auto* block = desc.Block(); if (block == nullptr) { diff --git a/test/ir/inference/test_trt_convert_activation.py b/test/ir/inference/test_trt_convert_activation.py index 6c76e7bc0892f..aac4fc3083bc3 100644 --- a/test/ir/inference/test_trt_convert_activation.py +++ b/test/ir/inference/test_trt_convert_activation.py @@ -167,7 +167,7 @@ def generate_trt_nodes_num(attrs, dynamic_shape): + runtime_version[2] * 10 < 8600 and self.dims == 0 - ) and program_config.ops[0].type in ["celu", "logsigmoid", "silu"]: + ) and program_config.ops[0].type in ["celu", "logsigmoid"]: return 0, 3 return 1, 2