diff --git a/.gitignore b/.gitignore index c23bb6bd1..777625777 100644 --- a/.gitignore +++ b/.gitignore @@ -78,6 +78,7 @@ piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/* !piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xci !piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.xco !piton/design/*/*/*/*/*/*/*/*/*/*/xilinx/*/ip_cores/*/*.coe +*.bd # Ignore files generated for DMBR unit testing piton/verif/diag/assembly/princeton/dmbr_stream_hyper_gen.s diff --git a/piton/design/chipset/include/mc_define.h b/piton/design/chipset/include/mc_define.h index 133877099..b33a0e8c5 100644 --- a/piton/design/chipset/include/mc_define.h +++ b/piton/design/chipset/include/mc_define.h @@ -105,6 +105,25 @@ `define DDR3_CS_WIDTH 2 `define DDR3_BG_WIDTH 2 `define DDR3_ODT_WIDTH 2 +`elsif ALVEO_BOARD + `define BOARD_MEM_SIZE_MB 16384 + `define WORDS_PER_BURST 8 + `define WORD_SIZE 8 // in bytes + `define MIG_APP_ADDR_WIDTH 32 + `define MIG_APP_CMD_WIDTH 3 + `define MIG_APP_DATA_WIDTH 512 + `define MIG_APP_MASK_WIDTH 64 + + `define DDR3_DQ_WIDTH 72 + `define DDR3_DQS_WIDTH 18 + `define DDR3_ADDR_WIDTH 17 + `define DDR3_BA_WIDTH 2 + `define DDR3_DM_WIDTH 0 + `define DDR3_CK_WIDTH 1 + `define DDR3_CKE_WIDTH 1 + `define DDR3_CS_WIDTH 1 + `define DDR3_BG_WIDTH 2 + `define DDR3_ODT_WIDTH 1 `elsif NEXYS4DDR_BOARD `define BOARD_MEM_SIZE_MB 256 `define WORDS_PER_BURST 8 diff --git a/piton/design/chipset/io_ctrl/xilinx/alveou200/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/alveou200/ip_cores/uart_16550/uart_16550.xci new file mode 100644 index 000000000..d9a73d5d6 --- /dev/null +++ b/piton/design/chipset/io_ctrl/xilinx/alveou200/ip_cores/uart_16550/uart_16550.xci @@ -0,0 +1,142 @@ + + + xilinx.com + xci + unknown + 1.0 + + + uart_16550 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 25000000 + virtexuplus + 0 + 0 + 1 + VERSAL_AI_CORE_ES1 + 66667000 + 1 + 25000000 + 25 + 0 + 0 + 16550 + 66667000 + 66.667 + 1 + 1 + uart_16550 + Custom + false + virtexuplus + + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 27 + TRUE + . + + . + 2021.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/alveou250/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/alveou250/ip_cores/uart_16550/uart_16550.xci new file mode 100644 index 000000000..d708239d3 --- /dev/null +++ b/piton/design/chipset/io_ctrl/xilinx/alveou250/ip_cores/uart_16550/uart_16550.xci @@ -0,0 +1,758 @@ + + + xilinx.com + xci + unknown + 1.0 + + + uart_16550 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 25000000 + virtexuplus + 0 + 0 + 1 + VERSAL_AI_CORE_ES1 + 66667000 + 1 + 25000000 + 25 + 0 + 0 + 16550 + 66667000 + 66.667 + 1 + 1 + uart_16550 + Custom + false + virtexuplus + xilinx.com:au250:part0:1.3 + + xcu250 + figd2104 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 28 + TRUE + . + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/mc/rtl/alveo_shell_top.sv b/piton/design/chipset/mc/rtl/alveo_shell_top.sv new file mode 100644 index 000000000..979bc9a47 --- /dev/null +++ b/piton/design/chipset/mc/rtl/alveo_shell_top.sv @@ -0,0 +1,327 @@ +/* + Copyright (c) 2023 Daniel Jiménez Mazure + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +`include "mc_define.h" + +`include "noc_axi4_bridge_define.vh" + +module alveo_shell_top ( + + input logic pcie_refclk_clk_n , + input logic pcie_refclk_clk_p , + input logic pcie_perstn , + input logic [15:0] pci_express_x16_rxn , + input logic [15:0] pci_express_x16_rxp , + output logic [15:0] pci_express_x16_txn , + output logic [15:0] pci_express_x16_txp , + input logic resetn , + + output logic c0_ddr4_act_n, + output logic [16:0] c0_ddr4_adr, + output logic [1:0] c0_ddr4_ba, + output logic [1:0] c0_ddr4_bg, + output logic [0:0] c0_ddr4_ck_c, + output logic [0:0] c0_ddr4_ck_t, + output logic [0:0] c0_ddr4_cke, + output logic [0:0] c0_ddr4_cs_n, + inout wire [71:0] c0_ddr4_dq, + inout wire [17:0] c0_ddr4_dqs_c, + inout wire [17:0] c0_ddr4_dqs_t, + output logic [0:0] c0_ddr4_odt, + output logic c0_ddr4_par, + output logic c0_ddr4_reset_n, + output logic c0_ddr4_ui_clk_sync_rst, + + // Reference clock + input logic c0_sysclk_clk_n, + input logic c0_sysclk_clk_p, + // input mc_clk , + // input mc_rstn , + output logic chip_rstn , + input logic chipset_clk , + input logic chipset_rstn , + output logic c0_init_calib_complete, + + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , + + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy +); + + logic mc_rst; + logic mc_clk; + + + logic trans_fifo_val; + logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + logic trans_fifo_rdy; + + logic fifo_trans_val; + logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + logic fifo_trans_rdy; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_awid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_awlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_awsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_awburst; + logic m_axi_awlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_awcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_awprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_awqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_awregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_awuser; + logic m_axi_awvalid; + logic m_axi_awready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_wid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_wdata; + logic [`AXI4_STRB_WIDTH -1:0] m_axi_wstrb; + logic m_axi_wlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_wuser; + logic m_axi_wvalid; + logic m_axi_wready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_arid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_araddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_arlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_arsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_arburst; + logic m_axi_arlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_arcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_arprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_arqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_arregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_aruser; + logic m_axi_arvalid; + logic m_axi_arready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_rid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_rdata; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_rresp; + logic m_axi_rlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_ruser; + logic m_axi_rvalid; + logic m_axi_rready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_bid; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_bresp; + logic [`AXI4_USER_WIDTH -1:0] m_axi_buser; + logic m_axi_bvalid; + logic m_axi_bready; + + noc_bidir_afifo mig_afifo ( + .clk_1 ( chipset_clk ), + .rst_1 ( ~chipset_rstn ), + + .clk_2 ( mc_clk ), + .rst_2 ( mc_rst ), + + // CPU --> MIG + .flit_in_val_1 ( mem_flit_in_val ), + .flit_in_data_1 ( mem_flit_in_data ), + .flit_in_rdy_1 ( mem_flit_in_rdy ), + + .flit_out_val_2 ( fifo_trans_val ), + .flit_out_data_2 ( fifo_trans_data ), + .flit_out_rdy_2 ( fifo_trans_rdy ), + + // MIG --> CPU + .flit_in_val_2 ( trans_fifo_val ), + .flit_in_data_2 ( trans_fifo_data ), + .flit_in_rdy_2 ( trans_fifo_rdy ), + + .flit_out_val_1 ( mem_flit_out_val ), + .flit_out_data_1 ( mem_flit_out_data ), + .flit_out_rdy_1 ( mem_flit_out_rdy ) + ); + + + noc_axi4_bridge noc_axi4_bridge ( + .clk ( mc_clk ), + .rst_n ( ~mc_rst ), + .uart_boot_en ( 1'b0 ), + .phy_init_done ( c0_init_calib_complete ), + + .src_bridge_vr_noc2_val ( fifo_trans_val ), + .src_bridge_vr_noc2_dat ( fifo_trans_data ), + .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), + + .bridge_dst_vr_noc3_val ( trans_fifo_val ), + .bridge_dst_vr_noc3_dat ( trans_fifo_data ), + .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + + .m_axi_wid ( m_axi_wid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_buser ( m_axi_buser ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + + .m_axi_rid ( m_axi_rid), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + + ); + + meep_shell meep_shell_i ( + + .c0_sysclk_clk_p ( c0_sysclk_clk_p ), + .c0_sysclk_clk_n ( c0_sysclk_clk_n ), + .c0_ddr4_ui_clk ( mc_clk ), + .c0_ddr4_ui_clk_sync_rst ( mc_rst ), + .c0_init_calib_complete ( c0_init_calib_complete ), + + // DDR4 physicall interface + .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( c0_ddr4_adr ), + .c0_ddr4_ba ( c0_ddr4_ba ), + .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address + .c0_ddr4_ck_t ( c0_ddr4_ck_t ), + .c0_ddr4_ck_c ( c0_ddr4_ck_c ), + .c0_ddr4_cke ( c0_ddr4_cke ), + .c0_ddr4_cs_n ( c0_ddr4_cs_n ), + .c0_ddr4_dq ( c0_ddr4_dq ), + .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .c0_ddr4_odt ( c0_ddr4_odt ), + .c0_ddr4_par ( c0_ddr4_par ), // output logic c0_ddr4_parity + .c0_ddr4_reset_n ( c0_ddr4_reset_n ), + + // DDR4 control interface, not used, grounded + .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_awvalid + .c0_ddr4_s_axi_ctrl_awready( ), // output logic c0_ddr4_s_axi_ctrl_awready + .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_awaddr + .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_wvalid + .c0_ddr4_s_axi_ctrl_wready ( ), // output logic c0_ddr4_s_axi_ctrl_wready + .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_wdata + .c0_ddr4_s_axi_ctrl_bvalid ( ), // output logic c0_ddr4_s_axi_ctrl_bvalid + .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_bready + .c0_ddr4_s_axi_ctrl_bresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_bresp + .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_arvalid + .c0_ddr4_s_axi_ctrl_arready( ), // output logic c0_ddr4_s_axi_ctrl_arready + .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_araddr + .c0_ddr4_s_axi_ctrl_rvalid ( ), // output logic c0_ddr4_s_axi_ctrl_rvalid + .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_rready + .c0_ddr4_s_axi_ctrl_rdata ( ), // output logic [31 : 0] c0_ddr4_s_axi_ctrl_rdata + .c0_ddr4_s_axi_ctrl_rresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_rresp + + .chip_rstn ( chip_rstn ), + + // AXI4 Memory Interface + .c0_ddr4_s_axi_awid ( m_axi_awid), // input logic [15 : 0] c0_ddr4_s_axi_awid + .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input logic [34 : 0] c0_ddr4_s_axi_awaddr + .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input logic [7 : 0] c0_ddr4_s_axi_awlen + .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input logic [2 : 0] c0_ddr4_s_axi_awsize + .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input logic [1 : 0] c0_ddr4_s_axi_awburst + .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input logic [0 : 0] c0_ddr4_s_axi_awlock + .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input logic [3 : 0] c0_ddr4_s_axi_awcache + .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input logic [2 : 0] c0_ddr4_s_axi_awprot + .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input logic [3 : 0] c0_ddr4_s_axi_awqos + .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input logic c0_ddr4_s_axi_awvalid + .c0_ddr4_s_axi_awready ( m_axi_awready), // output logic c0_ddr4_s_axi_awready + .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input logic [511 : 0] c0_ddr4_s_axi_wdata + .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input logic [63 : 0] c0_ddr4_s_axi_wstrb + .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input logic c0_ddr4_s_axi_wlast + .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input logic c0_ddr4_s_axi_wvalid + .c0_ddr4_s_axi_wready ( m_axi_wready), // output logic c0_ddr4_s_axi_wready + .c0_ddr4_s_axi_bready ( m_axi_bready), // input logic c0_ddr4_s_axi_bready + .c0_ddr4_s_axi_bid ( m_axi_bid), // output logic [15 : 0] c0_ddr4_s_axi_bid + .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output logic [1 : 0] c0_ddr4_s_axi_bresp + .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output logic c0_ddr4_s_axi_bvalid + .c0_ddr4_s_axi_arid ( m_axi_arid), // input logic [15 : 0] c0_ddr4_s_axi_arid + .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input logic [34 : 0] c0_ddr4_s_axi_araddr + .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input logic [7 : 0] c0_ddr4_s_axi_arlen + .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input logic [2 : 0] c0_ddr4_s_axi_arsize + .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input logic [1 : 0] c0_ddr4_s_axi_arburst + .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input logic [0 : 0] c0_ddr4_s_axi_arlock + .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input logic [3 : 0] c0_ddr4_s_axi_arcache + .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input logic [2 : 0] c0_ddr4_s_axi_arprot + .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input logic [3 : 0] c0_ddr4_s_axi_arqos + .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input logic c0_ddr4_s_axi_arvalid + .c0_ddr4_s_axi_arready ( m_axi_arready), // output logic c0_ddr4_s_axi_arready + .c0_ddr4_s_axi_rready ( m_axi_rready), // input logic c0_ddr4_s_axi_rready + .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output logic c0_ddr4_s_axi_rlast + .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output logic c0_ddr4_s_axi_rvalid + .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output logic [1 : 0] c0_ddr4_s_axi_rresp + .c0_ddr4_s_axi_rid ( m_axi_rid), // output logic [15 : 0] c0_ddr4_s_axi_rid + .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output logic [511 : 0] c0_ddr4_s_axi_rdata + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn) + ); + +endmodule + diff --git a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v index 688531032..baa5a9dbb 100644 --- a/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v +++ b/piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_ser.v @@ -50,6 +50,7 @@ localparam SEND_HEADER = 2'd1; localparam SEND_DATA = 2'd2; reg [`AXI4_DATA_WIDTH-1:0] data_in_f; +reg [`NOC_DATA_WIDTH-1:0] resp_header; wire in_go = in_val & in_rdy; wire flit_out_go = flit_out_val & flit_out_rdy; @@ -118,7 +119,6 @@ always @(posedge clk) begin end end -reg [`NOC_DATA_WIDTH-1:0] resp_header; always @(posedge clk) begin if (~rst_n) begin resp_header <= `NOC_DATA_WIDTH'b0; diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index fdbfddf60..5f38dcb24 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -88,7 +88,18 @@ module chipset( `ifdef F1_BOARD input sys_clk, -`else +`else // ifdef F1_BOARD +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , +`endif // ifdef ALVEO_BOARD // Oscillator clock `ifdef PITON_CHIPSET_CLKS_GEN `ifdef PITON_CHIPSET_DIFF_CLK @@ -244,11 +255,11 @@ module chipset( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef PITONSYS_DDR4_PARITY output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // PITONSYS_DDR4_PARITY `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -462,13 +473,13 @@ module chipset( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, - `elsif XUPP3R_BOARD + `elsif PITONSYS_NO_SWITCH // no switches :( `else input [7:0] sw, `endif - `ifdef XUPP3R_BOARD + `ifdef PITONSYS_LED_4 output [3:0] leds `else output [7:0] leds @@ -755,7 +766,7 @@ end `ifdef VCU118_BOARD assign uart_boot_en = sw[0]; assign uart_timeout_en = sw[1]; - `elsif XUPP3R_BOARD + `elsif PITONSYS_NO_SWITCH assign uart_boot_en = 1'b1; assign uart_timeout_en = 1'b0; `else @@ -808,7 +819,7 @@ end // Test points assign tp[7:0] = 8'd0; -`elsif XUPP3R_BOARD +`elsif PITONSYS_LED_4 assign leds[0] = ~piton_ready_n; assign leds[1] = init_calib_complete; assign leds[2] = processor_offchip_noc2_valid; @@ -1307,11 +1318,11 @@ chipset_impl_noc_power_test chipset_impl ( .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD - `ifdef XUPP3R_BOARD + `ifdef PITONSYS_DDR4_PARITY .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), - `endif // XUPP3R_BOARD + `endif // PITONSYS_DDR4_PARITY .ddr_odt(ddr_odt) `else // ifndef F1_BOARD .mc_clk(mc_clk), @@ -1420,6 +1431,20 @@ chipset_impl_noc_power_test chipset_impl ( `endif // PITON_FPGA_ETHERNETLITE `endif // endif PITONSYS_IOCTRL + + `ifdef ALVEO_BOARD + , // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + .chip_rstn (chip_rstn) + + `endif `ifdef PITON_RV64_PLATFORM `ifdef PITON_RV64_DEBUGUNIT diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 76bfff05b..55795d91e 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -87,6 +87,18 @@ module chipset_impl( // invalid access inside packet filter output invalid_access_o, +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , +`endif + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD @@ -152,11 +164,11 @@ module chipset_impl( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef PITONSYS_DDR4_PARITY output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // PITONSYS_DDR4_PARITY `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -464,8 +476,13 @@ assign chip_buf_noc3_data = {`NOC_DATA_WIDTH{1'b0}}; assign uart_timeout_en = 1'b0; `else // ifdef PITONSYS_UART `ifndef PITONSYS_UART_BOOT - assign uart_boot_en = 1'b0; - assign uart_timeout_en = 1'b0; + `ifndef ALVEO_BOARD + assign uart_boot_en = 1'b0; + assign uart_timeout_en = 1'b0; + `else + assign uart_boot_en = 1'b1; + assign uart_timeout_en = 1'b0; + `endif // endif ALVEO_BOARD `endif // endif PITONSYS_UART_BOOT `endif // endif PITONSYS_UART `endif // endif PITONSYS_IOCTRL @@ -778,6 +795,55 @@ credit_to_valrdy noc3_xbar_to_%s( .m_axi_bready(m_axi_bready), .ddr_ready(ddr_ready) ); + `elsif ALVEO_BOARD + alveo_shell_top alveo_shell_i ( + + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + + // DDR4 physicall interface + .c0_ddr4_act_n ( ddr_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( ddr_addr ), + .c0_ddr4_ba ( ddr_ba ), + .c0_ddr4_bg ( ddr_bg ), // bank group address + .c0_ddr4_ck_t ( ddr_ck_p ), + .c0_ddr4_ck_c ( ddr_ck_n ), + .c0_ddr4_cke ( ddr_cke ), + .c0_ddr4_cs_n ( ddr_cs_n ), + .c0_ddr4_dq ( ddr_dq ), + .c0_ddr4_dqs_c ( ddr_dqs_n ), + .c0_ddr4_dqs_t ( ddr_dqs_p ), + .c0_ddr4_odt ( ddr_odt ), + .c0_ddr4_par ( ddr_parity ), // output wire c0_ddr4_parity + .c0_ddr4_reset_n ( ddr_reset_n ), + + // DDR4 clock & reset + .c0_sysclk_clk_p ( mc_clk_p ), + .c0_sysclk_clk_n ( mc_clk_n ), + + .c0_init_calib_complete ( init_calib_complete ), + + .chip_rstn (chip_rstn ), + .chipset_clk (chipset_clk ), + .chipset_rstn (chipset_rst_n ), + + + .mem_flit_in_val(buf_mem_noc2_valid), + .mem_flit_in_data(buf_mem_noc2_data), + .mem_flit_in_rdy(mem_buf_noc2_ready), + + .mem_flit_out_val(mem_buf_noc3_valid), + .mem_flit_out_data(mem_buf_noc3_data), + .mem_flit_out_rdy(buf_mem_noc3_ready) + + ); `else mc_top mc_top( .mc_ui_clk_sync_rst(mc_ui_clk_sync_rst), @@ -1121,7 +1187,7 @@ fake_uart fake_uart ( // this is for selecting the right bootrom (1: baremetal, 0: linux) wire ariane_boot_sel; `ifdef PITON_FPGA_SYNTH - assign ariane_boot_sel = uart_boot_en; + assign ariane_boot_sel = uart_boot_en; `else `ifdef ARIANE_SIM_LINUX_BOOT assign ariane_boot_sel = 1'b0; diff --git a/piton/design/chipset/xilinx/alveou200/.gitignore b/piton/design/chipset/xilinx/alveou200/.gitignore new file mode 100644 index 000000000..9f8079437 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou200/.gitignore @@ -0,0 +1,2 @@ +!ip_cores +meep_shell diff --git a/piton/design/chipset/xilinx/alveou200/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/alveou200/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci new file mode 100644 index 000000000..f3ffc859e --- /dev/null +++ b/piton/design/chipset/xilinx/alveou200/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -0,0 +1,587 @@ + + + xilinx.com + xci + unknown + 1.0 + + + afifo_w64_d128_std + + + + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 7 + BlankString + 64 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 64 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplus + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x72 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1 + 7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 7 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + afifo_w64_d128_std + 64 + false + 7 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 64 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 64 + 128 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 7 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 7 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtexuplus + + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2021.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/alveou200/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/alveou200/ip_cores/clk_mmcm/clk_mmcm.xci new file mode 100644 index 000000000..83cb38011 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou200/ip_cores/clk_mmcm/clk_mmcm.xci @@ -0,0 +1,833 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_mmcm + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 100.000 + 0000 + 0000 + 100.00000 + 0000 + 0000 + 250.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100 + 0.000 + 1 + 0000 + 0000 + 8.00000 + BUFG + 50.0 + false + 250.00000 + 0.000 + 50.000 + 250.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 8.00000 + 0.000 + 50.000 + 8 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + 0000 + 0000 + 25.00000 + BUFG + 50.0 + false + 100.00000 + 180.000 + 50.000 + 100.000 + 180.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 25.00000 + 0.000 + 50.000 + 25.000 + 0.000 + 1 + 1 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + VCO + clk_in_sel + chipset_clk + mc_sys_clk + sd_sys_clk + chipset_passthru_clk + chipset_passthru_clk_n + net_phy_clk + net_axi_clk + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.4 + 12.5 + 1.0 + 1.0 + 4.0 + 1.0 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary__________156.25_______________35 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 32.000 + 0.000 + FALSE + 6.400 + 10.0 + 10.000 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 125 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + 10 + 0.500 + 180.000 + FALSE + 40 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 5 + None + 0.005 + 0.010 + FALSE + 128.000 + 2.000 + 7 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + chipset_clk__100.00000______0.000______50.0______191.885____204.239 + mc_sys_clk__250.00000______0.000______50.0______164.639____204.239 + sd_sys_clk___8.00000______0.000______50.0______301.256____204.239 + chipset_passthru_clk__100.00000______0.000______50.0______191.885____204.239 + chipset_passthru_clk_n__100.00000____180.000______50.0______191.885____204.239 + net_phy_clk__25.00000______0.000______50.0______245.996____204.239 + net_axi_clk__100.00000______0.000______50.0______191.885____204.239 + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 156.25 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1600.000 + 800.000 + clk_mmcm + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 35 + 100.000 + 100.000 + BUFG + 191.885 + false + 204.239 + 50.000 + 100 + 0.000 + 1 + true + BUFG + 164.639 + false + 204.239 + 50.000 + 250.000 + 0.000 + 1 + true + BUFG + 301.256 + false + 204.239 + 50.000 + 8 + 0.000 + 1 + true + BUFG + 191.885 + false + 204.239 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 191.885 + false + 204.239 + 50.000 + 100.000 + 180.000 + 1 + true + BUFG + 245.996 + false + 204.239 + 50.000 + 25.000 + 0.000 + 1 + true + BUFG + 191.885 + false + 204.239 + 50.000 + 100.000 + 0.000 + 1 + true + 600.000 + Custom + Custom + clk_in_sel + chipset_clk + false + mc_sys_clk + false + sd_sys_clk + false + chipset_passthru_clk + false + chipset_passthru_clk_n + false + net_phy_clk + false + net_axi_clk + false + CLK_VALID + auto + clk_mmcm + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + PS + No_Jitter + locked + OPTIMIZED + 32.000 + 0.000 + false + 6.400 + 10.0 + 10.000 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 125 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + 10 + 0.500 + 180.000 + false + 40 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + AUTO + 5 + None + 0.005 + 0.010 + false + 7 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 156.25 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + virtexuplus + + + xcu200 + fsgd2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 9 + TRUE + ../../../../alveou200_system.gen/clk_mmcm/ip/clk_mmcm + + . + 2021.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/alveou250/.gitignore b/piton/design/chipset/xilinx/alveou250/.gitignore new file mode 100644 index 000000000..9f8079437 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou250/.gitignore @@ -0,0 +1,2 @@ +!ip_cores +meep_shell diff --git a/piton/design/chipset/xilinx/alveou250/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/alveou250/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci new file mode 100644 index 000000000..91131fc05 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou250/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -0,0 +1,655 @@ + + + xilinx.com + xci + unknown + 1.0 + + + afifo_w64_d128_std + + + + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 7 + BlankString + 64 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 64 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplus + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x72 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1 + 7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 7 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + afifo_w64_d128_std + 64 + false + 7 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 64 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 64 + 128 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 7 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 7 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtexuplus + xilinx.com:au250:part0:1.3 + + xcu250 + figd2104 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 7 + TRUE + . + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/alveou250/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/alveou250/ip_cores/clk_mmcm/clk_mmcm.xci new file mode 100644 index 000000000..75b059223 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou250/ip_cores/clk_mmcm/clk_mmcm.xci @@ -0,0 +1,990 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_mmcm + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 100.000 + 0000 + 0000 + 100.00000 + 0000 + 0000 + 250.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100 + 0.000 + 1 + 0000 + 0000 + 8.00000 + BUFG + 50.0 + false + 250.00000 + 0.000 + 50.000 + 250.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 8.00000 + 0.000 + 50.000 + 8 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + 0000 + 0000 + 25.00000 + BUFG + 50.0 + false + 100.00000 + 180.000 + 50.000 + 100.000 + 180.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 25.00000 + 0.000 + 50.000 + 25.000 + 0.000 + 1 + 1 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + VCO + clk_in_sel + chipset_clk + mc_sys_clk + sd_sys_clk + chipset_passthru_clk + chipset_passthru_clk_n + net_phy_clk + net_axi_clk + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.4 + 12.5 + 1.0 + 1.0 + 4.0 + 1.0 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary__________156.25_______________35 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 32.000 + 0.000 + FALSE + 6.400 + 10.0 + 10.000 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 125 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + 10 + 0.500 + 180.000 + FALSE + 40 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 5 + None + 0.005 + 0.010 + FALSE + 128.000 + 2.000 + 7 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + chipset_clk__100.00000______0.000______50.0______191.885____204.239 + mc_sys_clk__250.00000______0.000______50.0______164.639____204.239 + sd_sys_clk___8.00000______0.000______50.0______301.256____204.239 + chipset_passthru_clk__100.00000______0.000______50.0______191.885____204.239 + chipset_passthru_clk_n__100.00000____180.000______50.0______191.885____204.239 + net_phy_clk__25.00000______0.000______50.0______245.996____204.239 + net_axi_clk__100.00000______0.000______50.0______191.885____204.239 + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 156.25 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1600.000 + 800.000 + clk_mmcm + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 35 + 100.000 + 100.000 + BUFG + 191.885 + false + 204.239 + 50.000 + 100 + 0.000 + 1 + true + BUFG + 164.639 + false + 204.239 + 50.000 + 250.000 + 0.000 + 1 + true + BUFG + 301.256 + false + 204.239 + 50.000 + 8 + 0.000 + 1 + true + BUFG + 191.885 + false + 204.239 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 191.885 + false + 204.239 + 50.000 + 100.000 + 180.000 + 1 + true + BUFG + 245.996 + false + 204.239 + 50.000 + 25.000 + 0.000 + 1 + true + BUFG + 191.885 + false + 204.239 + 50.000 + 100.000 + 0.000 + 1 + true + 600.000 + Custom + Custom + clk_in_sel + chipset_clk + false + mc_sys_clk + false + sd_sys_clk + false + chipset_passthru_clk + false + chipset_passthru_clk_n + false + net_phy_clk + false + net_axi_clk + false + CLK_VALID + auto + clk_mmcm + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + PS + No_Jitter + locked + OPTIMIZED + 32.000 + 0.000 + false + 6.400 + 10.0 + 10.000 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 125 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + 10 + 0.500 + 180.000 + false + 40 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + AUTO + 5 + None + 0.005 + 0.010 + false + 7 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 156.25 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + virtexuplus + xilinx.com:au250:part0:1.3 + + xcu250 + figd2104 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 10 + TRUE + ../../../../alveou200_system.gen/clk_mmcm/ip/clk_mmcm + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/include/piton_system.vh b/piton/design/include/piton_system.vh index 5b6618fd8..aa49c9854 100644 --- a/piton/design/include/piton_system.vh +++ b/piton/design/include/piton_system.vh @@ -122,6 +122,8 @@ `define PITON_CHIPSET_DIFF_CLK `elsif GENESYS2_BOARD `define PITON_CHIPSET_DIFF_CLK +`elsif ALVEO_BOARD + `define PITON_CHIPSET_DIFF_CLK `elsif PITON_BOARD `define PITON_CHIPSET_DIFF_CLK `define PITON_CHIPSET_DIFF_CLK_POLARITY_CAPS @@ -134,6 +136,8 @@ `define PITON_FPGA_RST_ACT_HIGH `elsif VCU118_BOARD `define PITON_FPGA_RST_ACT_HIGH +`elsif ALVEO_BOARD + `define PITON_FPGA_RST_ACT_HIGH `endif `ifdef XUPP3R_BOARD @@ -143,6 +147,9 @@ `undef PITON_FPGA_SD_BOOT `undef PITONSYS_SPI `define PITONSYS_AXI4_MEM +`elsif ALVEO_BOARD + `undef PITON_FPGA_SD_BOOT + `undef PITONSYS_SPI `endif // If PITON_FPGA_SD_BOOT is set we should always include SPI @@ -159,4 +166,15 @@ `define PITONSYS_DDR4 `elsif XUPP3R_BOARD `define PITONSYS_DDR4 +`elsif ALVEO_BOARD + `define PITONSYS_DDR4 +`endif + +`ifdef XUPP3R_BOARD + `define PITONSYS_DDR4_PARITY + `define PITONSYS_LED_4 + `define PITONSYS_NO_SWITCH +`elsif ALVEO_BOARD + `define PITONSYS_DDR4_PARITY + `define PITONSYS_NO_SWITCH `endif diff --git a/piton/design/rtl/system.v b/piton/design/rtl/system.v index e0ed161ac..84138985c 100644 --- a/piton/design/rtl/system.v +++ b/piton/design/rtl/system.v @@ -108,6 +108,17 @@ module system( `endif // endif PITON_PASSTHRU_CLKS_GEN `endif // endif PITON_SYS_INC_PASSTHRU +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , +`endif + `ifndef F1_BOARD `ifdef PITON_CHIPSET_CLKS_GEN `ifdef PITON_CHIPSET_DIFF_CLK @@ -142,7 +153,10 @@ module system( input sys_clk, `endif +`ifndef ALVEO_BOARD + input sys_rst_n, +`endif `ifndef PITON_FPGA_SYNTH input pll_rst_n, @@ -180,6 +194,7 @@ module system( `ifndef VCU118_BOARD `ifndef NEXYSVIDEO_BOARD `ifndef XUPP3R_BOARD +`ifndef ALVEO_BOARD `ifndef F1_BOARD input tck_i, input tms_i, @@ -187,6 +202,7 @@ module system( input td_i, output td_o, `endif//F1_BOARD +`endif // ALVEO_BOARD `endif//XUPP3R_BOARD `endif //NEXYSVIDEO_BOARD `endif //VCU118_BOARD @@ -230,11 +246,11 @@ module system( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 - `ifdef XUPP3R_BOARD + `ifdef PITONSYS_DDR4_PARITY output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, - `endif // XUPP3R_BOARD + `endif // PITONSYS_DDR4_PARITY `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -384,14 +400,16 @@ module system( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, -`elsif XUPP3R_BOARD +`elsif PITONSYS_NO_SWITCH // no switches :( `else input [7:0] sw, `endif -`ifdef XUPP3R_BOARD +`ifdef PITONSYS_LED_4 output [3:0] leds +`elsif ALVEO_BOARD + output hbm_cattrip `else output [7:0] leds `endif @@ -560,6 +578,13 @@ assign rtc = rtc_div[6]; assign uart_rts = 1'b0; `endif // VCU118_BOARD +`ifdef ALVEO_BOARD + + wire sys_rst_n; + assign hbm_cattrip = 1'b0; + +`endif + // Different reset active levels for different boards always @ * begin @@ -945,6 +970,17 @@ chipset chipset( .mc_clk_n(mc_clk_n), `endif // PITONSYS_DDR4 +`ifdef ALVEO_BOARD + .pcie_refclk_clk_n (pcie_refclk_clk_n) , + .pcie_refclk_clk_p (pcie_refclk_clk_p) , + .pcie_perstn (pcie_perstn) , + .pci_express_x16_rxn (pci_express_x16_rxn) , + .pci_express_x16_rxp (pci_express_x16_rxp) , + .pci_express_x16_txn (pci_express_x16_txn ) , + .pci_express_x16_txp (pci_express_x16_txp) , + .resetn (resetn), +`endif + `else // ifndef PITON_CHIPSET_CLKS_GEN .chipset_clk(chipset_clk), `ifndef PITONSYS_NO_MC @@ -1066,7 +1102,7 @@ chipset chipset( `ifndef NEXYSVIDEO_BOARD .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD -`ifdef XUPP3R_BOARD +`ifdef PITONSYS_DDR4_PARITY .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), @@ -1134,6 +1170,10 @@ chipset chipset( `endif // PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC +`ifdef ALVEO_BOARD + .chip_rstn (sys_rst_n), +`endif + `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART .uart_tx(uart_tx), @@ -1203,7 +1243,7 @@ chipset chipset( .btnc(btnc), `endif -`ifndef XUPP3R_BOARD +`ifndef PITONSYS_NO_SWITCH .sw(sw), `endif .leds(leds) diff --git a/piton/design/xilinx/alveou200/constraints.xdc b/piton/design/xilinx/alveou200/constraints.xdc new file mode 100644 index 000000000..447424fc8 --- /dev/null +++ b/piton/design/xilinx/alveou200/constraints.xdc @@ -0,0 +1,276 @@ +# Bitstream Configuration +# ------------------------------------------------------------------------ +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# ------------------------------------------------------------------------ + +# Don't time the GPIO reset signals +set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] + + + +# 156.25MHz General purpose system clock +set_property PACKAGE_PIN AU19 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN AV19 [get_ports chipset_clk_osc_n] + +set_property IOSTANDARD LVDS [get_ports chipset_clk*] + + +set_property PACKAGE_PIN AL20 [get_ports resetn] +set_property IOSTANDARD LVCMOS12 [get_ports resetn] + + +# UART +set_property PACKAGE_PIN BF18 [get_ports uart_rx] +set_property PACKAGE_PIN BB20 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS12 [get_ports uart_*] + +## +## PCIe MGTY Interface +## +set_property PACKAGE_PIN BD21 [get_ports pcie_perstn] +set_property IOSTANDARD LVCMOS12 [get_ports pcie_perstn] + +set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]}] +set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]}] +set_property PACKAGE_PIN BF5 [get_ports {pci_express_x16_txp[15]}] +set_property PACKAGE_PIN BF4 [get_ports {pci_express_x16_txn[15]}] +set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[14]}] +set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[14]}] +set_property PACKAGE_PIN BD5 [get_ports {pci_express_x16_txp[14]}] +set_property PACKAGE_PIN BD4 [get_ports {pci_express_x16_txn[14]}] +set_property PACKAGE_PIN AW4 [get_ports {pci_express_x16_rxp[13]}] +set_property PACKAGE_PIN AW3 [get_ports {pci_express_x16_rxn[13]}] +set_property PACKAGE_PIN BB5 [get_ports {pci_express_x16_txp[13]}] +set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_txn[13]}] +set_property PACKAGE_PIN AV2 [get_ports {pci_express_x16_rxp[12]}] +set_property PACKAGE_PIN AV1 [get_ports {pci_express_x16_rxn[12]}] +set_property PACKAGE_PIN AV7 [get_ports {pci_express_x16_txp[12]}] +set_property PACKAGE_PIN AV6 [get_ports {pci_express_x16_txn[12]}] +# Clock +set_property PACKAGE_PIN AM10 [get_ports pcie_refclk_clk_n] +set_property PACKAGE_PIN AM11 [get_ports pcie_refclk_clk_p] + +set_property PACKAGE_PIN AU4 [get_ports {pci_express_x16_rxp[11]}] +set_property PACKAGE_PIN AU3 [get_ports {pci_express_x16_rxn[11]}] +set_property PACKAGE_PIN AU9 [get_ports {pci_express_x16_txp[11]}] +set_property PACKAGE_PIN AU8 [get_ports {pci_express_x16_txn[11]}] +set_property PACKAGE_PIN AT2 [get_ports {pci_express_x16_rxp[10]}] +set_property PACKAGE_PIN AT1 [get_ports {pci_express_x16_rxn[10]}] +set_property PACKAGE_PIN AT7 [get_ports {pci_express_x16_txp[10]}] +set_property PACKAGE_PIN AT6 [get_ports {pci_express_x16_txn[10]}] +set_property PACKAGE_PIN AP2 [get_ports {pci_express_x16_rxp[8]}] +set_property PACKAGE_PIN AP1 [get_ports {pci_express_x16_rxn[8]}] +set_property PACKAGE_PIN AP7 [get_ports {pci_express_x16_txp[8]}] +set_property PACKAGE_PIN AP6 [get_ports {pci_express_x16_txn[8]}] +set_property PACKAGE_PIN AR4 [get_ports {pci_express_x16_rxp[9]}] +set_property PACKAGE_PIN AR3 [get_ports {pci_express_x16_rxn[9]}] +set_property PACKAGE_PIN AR9 [get_ports {pci_express_x16_txp[9]}] +set_property PACKAGE_PIN AR8 [get_ports {pci_express_x16_txn[9]}] +set_property PACKAGE_PIN AN4 [get_ports {pci_express_x16_rxp[7]}] +set_property PACKAGE_PIN AN3 [get_ports {pci_express_x16_rxn[7]}] +set_property PACKAGE_PIN AN9 [get_ports {pci_express_x16_txp[7]}] +set_property PACKAGE_PIN AN8 [get_ports {pci_express_x16_txn[7]}] +set_property PACKAGE_PIN AM2 [get_ports {pci_express_x16_rxp[6]}] +set_property PACKAGE_PIN AM1 [get_ports {pci_express_x16_rxn[6]}] +set_property PACKAGE_PIN AM7 [get_ports {pci_express_x16_txp[6]}] +set_property PACKAGE_PIN AM6 [get_ports {pci_express_x16_txn[6]}] +set_property PACKAGE_PIN AL4 [get_ports {pci_express_x16_rxp[5]}] +set_property PACKAGE_PIN AL3 [get_ports {pci_express_x16_rxn[5]}] +set_property PACKAGE_PIN AL9 [get_ports {pci_express_x16_txp[5]}] +set_property PACKAGE_PIN AL8 [get_ports {pci_express_x16_txn[5]}] +set_property PACKAGE_PIN AK2 [get_ports {pci_express_x16_rxp[4]}] +set_property PACKAGE_PIN AK1 [get_ports {pci_express_x16_rxn[4]}] +set_property PACKAGE_PIN AK7 [get_ports {pci_express_x16_txp[4]}] +set_property PACKAGE_PIN AK6 [get_ports {pci_express_x16_txn[4]}] +#set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 +set_property PACKAGE_PIN AJ4 [get_ports {pci_express_x16_rxp[3]}] +set_property PACKAGE_PIN AJ3 [get_ports {pci_express_x16_rxn[3]}] +set_property PACKAGE_PIN AJ9 [get_ports {pci_express_x16_txp[3]}] +set_property PACKAGE_PIN AJ8 [get_ports {pci_express_x16_txn[3]}] +set_property PACKAGE_PIN AH2 [get_ports {pci_express_x16_rxp[2]}] +set_property PACKAGE_PIN AH1 [get_ports {pci_express_x16_rxn[2]}] +set_property PACKAGE_PIN AH7 [get_ports {pci_express_x16_txp[2]}] +set_property PACKAGE_PIN AH6 [get_ports {pci_express_x16_txn[2]}] +set_property PACKAGE_PIN AG4 [get_ports {pci_express_x16_rxp[1]}] +set_property PACKAGE_PIN AG3 [get_ports {pci_express_x16_rxn[1]}] +set_property PACKAGE_PIN AG9 [get_ports {pci_express_x16_txp[1]}] +set_property PACKAGE_PIN AG8 [get_ports {pci_express_x16_txn[1]}] +set_property PACKAGE_PIN AF2 [get_ports {pci_express_x16_rxp[0]}] +set_property PACKAGE_PIN AF1 [get_ports {pci_express_x16_rxn[0]}] +set_property PACKAGE_PIN AF7 [get_ports {pci_express_x16_txp[0]}] +set_property PACKAGE_PIN AF6 [get_ports {pci_express_x16_txn[0]}] + +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] +set_clock_groups -asynchronous -group pcie_refclk + +#There are other 3 DDR chips in the u200, here it is only the C0 +#300MHz DDR0 system clock +set_property PACKAGE_PIN AY37 [get_ports mc_clk_p] +set_property PACKAGE_PIN AY38 [get_ports mc_clk_n] + +set_property -dict {PACKAGE_PIN AR36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[16]}] +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[15]}] +#set_property -dict {PACKAGE_PIN AN34 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_odt[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_42 +#set_property -dict {PACKAGE_PIN AM34 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_cs_n[3] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L22P_T3U_N6_DBC_AD0P_42 +set_property -dict {PACKAGE_PIN AR33 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cs_n[0]}] +set_property -dict {PACKAGE_PIN AN36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[13]}] +#set_property -dict {PACKAGE_PIN AN35 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[17] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L24P_T3U_N10_42 +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[14]}] +set_property -dict {PACKAGE_PIN AP34 IOSTANDARD SSTL12_DCI} [get_ports {ddr_odt[0]}] +#set_property -dict {PACKAGE_PIN AP33 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_cs_n[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L20N_T3L_N3_AD1N_42 +#set_property -dict {PACKAGE_PIN AN33 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_cs_n[2] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L20P_T3L_N2_AD1P_42 +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[0]}] +set_property -dict {PACKAGE_PIN AR35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[10]}] +set_property -dict {PACKAGE_PIN AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_n[0]}] +set_property -dict {PACKAGE_PIN AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_p[0]}] +#set_property -dict {PACKAGE_PIN AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_n[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L16N_T2U_N7_QBC_AD3N_42 +#set_property -dict {PACKAGE_PIN AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_p[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L16P_T2U_N6_QBC_AD3P_42 +set_property -dict {PACKAGE_PIN AT34 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[1]}] +set_property -dict {PACKAGE_PIN AU36 IOSTANDARD SSTL12_DCI} [get_ports ddr_parity] +set_property -dict {PACKAGE_PIN AT36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[0]}] +set_property -dict {PACKAGE_PIN AV37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[2]}] +set_property -dict {PACKAGE_PIN AV36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[1]}] +set_property -dict {PACKAGE_PIN AW36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[4]}] +set_property -dict {PACKAGE_PIN AW35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[3]}] +#set_property -dict {PACKAGE_PIN BA38 IOSTANDARD LVCMOS12 } [get_ports ddr4_sdram_c0_alert_n ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L11N_T1U_N9_GC_42 +set_property -dict {PACKAGE_PIN BA37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[8]}] +set_property -dict {PACKAGE_PIN BA40 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[7]}] +set_property -dict {PACKAGE_PIN BA39 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[11]}] +set_property -dict {PACKAGE_PIN BB37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[9]}] +set_property -dict {PACKAGE_PIN AY36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[5]}] +set_property -dict {PACKAGE_PIN AY35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[6]}] +#set_property -dict {PACKAGE_PIN BC40 IOSTANDARD SSTL12_DCI } [get_ports ddr_cke[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L9N_T1L_N5_AD12N_42 +set_property -dict {PACKAGE_PIN BC39 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[1]}] +set_property -dict {PACKAGE_PIN BB40 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[12]}] +set_property -dict {PACKAGE_PIN BB39 IOSTANDARD SSTL12_DCI} [get_ports ddr_act_n] +set_property -dict {PACKAGE_PIN BC38 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cke[0]}] +set_property -dict {PACKAGE_PIN BC37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[0]}] +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[66]}] +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[67]}] +set_property -dict {PACKAGE_PIN BF38 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[16]}] +set_property -dict {PACKAGE_PIN BE38 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[16]}] +set_property -dict {PACKAGE_PIN BD40 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[64]}] +set_property -dict {PACKAGE_PIN BD39 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[65]}] +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[71]}] +set_property -dict {PACKAGE_PIN BE40 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[70]}] +set_property -dict {PACKAGE_PIN BF37 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[68]}] +set_property -dict {PACKAGE_PIN BE37 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[69]}] +set_property -dict {PACKAGE_PIN BF40 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[17]}] +set_property -dict {PACKAGE_PIN BF39 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[17]}] +set_property -dict {PACKAGE_PIN AU32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[34]}] +set_property -dict {PACKAGE_PIN AT32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[35]}] +set_property -dict {PACKAGE_PIN AM32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[8]}] +set_property -dict {PACKAGE_PIN AM31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[8]}] +#set_property -dict {PACKAGE_PIN AT33 IOSTANDARD LVCMOS12 } [get_ports ddr4_sdram_c0_event_n ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_41 +set_property -dict {PACKAGE_PIN AM30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[33]}] +set_property -dict {PACKAGE_PIN AL30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[32]}] +set_property -dict {PACKAGE_PIN AR32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[38]}] +set_property -dict {PACKAGE_PIN AR31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[39]}] +set_property -dict {PACKAGE_PIN AN32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[37]}] +set_property -dict {PACKAGE_PIN AN31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[36]}] +set_property -dict {PACKAGE_PIN AP31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[9]}] +set_property -dict {PACKAGE_PIN AP30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[9]}] +set_property -dict {PACKAGE_PIN AV32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[25]}] +set_property -dict {PACKAGE_PIN AV31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[24]}] +set_property -dict {PACKAGE_PIN AW33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[6]}] +set_property -dict {PACKAGE_PIN AV33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[6]}] +set_property -dict {PACKAGE_PIN AU31 IOSTANDARD LVCMOS12} [get_ports ddr_reset_n] +set_property -dict {PACKAGE_PIN AW34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[27]}] +set_property -dict {PACKAGE_PIN AV34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[26]}] +set_property -dict {PACKAGE_PIN AY31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[29]}] +set_property -dict {PACKAGE_PIN AW31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[28]}] +set_property -dict {PACKAGE_PIN BA35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[30]}] +set_property -dict {PACKAGE_PIN BA34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[31]}] +set_property -dict {PACKAGE_PIN BA33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[7]}] +set_property -dict {PACKAGE_PIN BA32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[7]}] +set_property -dict {PACKAGE_PIN BB32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[17]}] +set_property -dict {PACKAGE_PIN BB31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[16]}] +set_property -dict {PACKAGE_PIN BB36 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[4]}] +set_property -dict {PACKAGE_PIN BB35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[4]}] +set_property -dict {PACKAGE_PIN AY33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[19]}] +set_property -dict {PACKAGE_PIN AY32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[18]}] +set_property -dict {PACKAGE_PIN BC33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[21]}] +set_property -dict {PACKAGE_PIN BC32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[20]}] +set_property -dict {PACKAGE_PIN BC34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[23]}] +set_property -dict {PACKAGE_PIN BB34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[22]}] +set_property -dict {PACKAGE_PIN BD31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[5]}] +set_property -dict {PACKAGE_PIN BC31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[5]}] +set_property -dict {PACKAGE_PIN BE33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[58]}] +set_property -dict {PACKAGE_PIN BD33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[57]}] +set_property -dict {PACKAGE_PIN BE36 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[14]}] +set_property -dict {PACKAGE_PIN BE35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[14]}] +set_property -dict {PACKAGE_PIN BD35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[59]}] +set_property -dict {PACKAGE_PIN BD34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[56]}] +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[61]}] +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[60]}] +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[63]}] +set_property -dict {PACKAGE_PIN BF34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[62]}] +set_property -dict {PACKAGE_PIN BE32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[15]}] +set_property -dict {PACKAGE_PIN BE31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[15]}] +set_property -dict {PACKAGE_PIN AP29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[40]}] +set_property -dict {PACKAGE_PIN AP28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[41]}] +set_property -dict {PACKAGE_PIN AL29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[10]}] +set_property -dict {PACKAGE_PIN AL28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[10]}] +set_property -dict {PACKAGE_PIN AN27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[42]}] +set_property -dict {PACKAGE_PIN AM27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[43]}] +set_property -dict {PACKAGE_PIN AR28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[47]}] +set_property -dict {PACKAGE_PIN AR27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[46]}] +set_property -dict {PACKAGE_PIN AN29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[44]}] +set_property -dict {PACKAGE_PIN AM29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[45]}] +set_property -dict {PACKAGE_PIN AT30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[11]}] +set_property -dict {PACKAGE_PIN AR30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[11]}] +set_property -dict {PACKAGE_PIN AV27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[49]}] +set_property -dict {PACKAGE_PIN AU27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[50]}] +set_property -dict {PACKAGE_PIN AU30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[12]}] +set_property -dict {PACKAGE_PIN AU29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[12]}] +set_property -dict {PACKAGE_PIN AT28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[48]}] +set_property -dict {PACKAGE_PIN AT27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[51]}] +set_property -dict {PACKAGE_PIN AV29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[52]}] +set_property -dict {PACKAGE_PIN AV28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[55]}] +set_property -dict {PACKAGE_PIN AY30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[53]}] +set_property -dict {PACKAGE_PIN AW30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[54]}] +set_property -dict {PACKAGE_PIN AY28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[13]}] +set_property -dict {PACKAGE_PIN AY27 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[13]}] +set_property -dict {PACKAGE_PIN BA28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[2]}] +set_property -dict {PACKAGE_PIN BA27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[3]}] +set_property -dict {PACKAGE_PIN BB30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[0]}] +set_property -dict {PACKAGE_PIN BA30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[0]}] +set_property -dict {PACKAGE_PIN AW29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[1]}] +set_property -dict {PACKAGE_PIN AW28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[0]}] +set_property -dict {PACKAGE_PIN BC27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[6]}] +set_property -dict {PACKAGE_PIN BB27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[7]}] +set_property -dict {PACKAGE_PIN BB29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[4]}] +set_property -dict {PACKAGE_PIN BA29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[5]}] +set_property -dict {PACKAGE_PIN BC26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[1]}] +set_property -dict {PACKAGE_PIN BB26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[1]}] +set_property -dict {PACKAGE_PIN BF28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[9]}] +set_property -dict {PACKAGE_PIN BE28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[8]}] +set_property -dict {PACKAGE_PIN BD29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[2]}] +set_property -dict {PACKAGE_PIN BD28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[2]}] +set_property -dict {PACKAGE_PIN BE30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[10]}] +set_property -dict {PACKAGE_PIN BD30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[11]}] +set_property -dict {PACKAGE_PIN BF27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[12]}] +set_property -dict {PACKAGE_PIN BE27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[13]}] +set_property -dict {PACKAGE_PIN BF30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[14]}] +set_property -dict {PACKAGE_PIN BF29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[15]}] +set_property -dict {PACKAGE_PIN BE26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[3]}] +set_property -dict {PACKAGE_PIN BD26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[3]}] +# + +set_property PACKAGE_PIN BC21 [get_ports hbm_cattrip] +set_property IOSTANDARD LVCMOS12 [get_ports hbm_cattrip] +set_property PULLDOWN true [get_ports hbm_cattrip] + +set_false_path -from [get_pins chipset/chipset_impl/alveo_shell_i/meep_shell_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/*/C] -to [get_pins chipset/chipset_impl/init_calib_complete_f_reg/D] diff --git a/piton/design/xilinx/alveou200/devices.xml b/piton/design/xilinx/alveou200/devices.xml new file mode 100644 index 000000000..8162e9c91 --- /dev/null +++ b/piton/design/xilinx/alveou200/devices.xml @@ -0,0 +1,57 @@ + + + + + chip + + + + mem + 0x0 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + net + 0xfff0d00000 + 0x100000 + + diff --git a/piton/design/xilinx/alveou200/devices_ariane.xml b/piton/design/xilinx/alveou200/devices_ariane.xml new file mode 100644 index 000000000..d34a2d136 --- /dev/null +++ b/piton/design/xilinx/alveou200/devices_ariane.xml @@ -0,0 +1,78 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x200000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + + + + ariane_debug + 0xfff1000000 + 0x1000 + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + + ariane_clint + 0xfff1020000 + 0xc0000 + + + + + ariane_plic + 0xfff1100000 + 0x4000000 + + + + + diff --git a/piton/design/xilinx/alveou250/constraints.xdc b/piton/design/xilinx/alveou250/constraints.xdc new file mode 100644 index 000000000..447424fc8 --- /dev/null +++ b/piton/design/xilinx/alveou250/constraints.xdc @@ -0,0 +1,276 @@ +# Bitstream Configuration +# ------------------------------------------------------------------------ +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# ------------------------------------------------------------------------ + +# Don't time the GPIO reset signals +set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] + + + +# 156.25MHz General purpose system clock +set_property PACKAGE_PIN AU19 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN AV19 [get_ports chipset_clk_osc_n] + +set_property IOSTANDARD LVDS [get_ports chipset_clk*] + + +set_property PACKAGE_PIN AL20 [get_ports resetn] +set_property IOSTANDARD LVCMOS12 [get_ports resetn] + + +# UART +set_property PACKAGE_PIN BF18 [get_ports uart_rx] +set_property PACKAGE_PIN BB20 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS12 [get_ports uart_*] + +## +## PCIe MGTY Interface +## +set_property PACKAGE_PIN BD21 [get_ports pcie_perstn] +set_property IOSTANDARD LVCMOS12 [get_ports pcie_perstn] + +set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]}] +set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]}] +set_property PACKAGE_PIN BF5 [get_ports {pci_express_x16_txp[15]}] +set_property PACKAGE_PIN BF4 [get_ports {pci_express_x16_txn[15]}] +set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[14]}] +set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[14]}] +set_property PACKAGE_PIN BD5 [get_ports {pci_express_x16_txp[14]}] +set_property PACKAGE_PIN BD4 [get_ports {pci_express_x16_txn[14]}] +set_property PACKAGE_PIN AW4 [get_ports {pci_express_x16_rxp[13]}] +set_property PACKAGE_PIN AW3 [get_ports {pci_express_x16_rxn[13]}] +set_property PACKAGE_PIN BB5 [get_ports {pci_express_x16_txp[13]}] +set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_txn[13]}] +set_property PACKAGE_PIN AV2 [get_ports {pci_express_x16_rxp[12]}] +set_property PACKAGE_PIN AV1 [get_ports {pci_express_x16_rxn[12]}] +set_property PACKAGE_PIN AV7 [get_ports {pci_express_x16_txp[12]}] +set_property PACKAGE_PIN AV6 [get_ports {pci_express_x16_txn[12]}] +# Clock +set_property PACKAGE_PIN AM10 [get_ports pcie_refclk_clk_n] +set_property PACKAGE_PIN AM11 [get_ports pcie_refclk_clk_p] + +set_property PACKAGE_PIN AU4 [get_ports {pci_express_x16_rxp[11]}] +set_property PACKAGE_PIN AU3 [get_ports {pci_express_x16_rxn[11]}] +set_property PACKAGE_PIN AU9 [get_ports {pci_express_x16_txp[11]}] +set_property PACKAGE_PIN AU8 [get_ports {pci_express_x16_txn[11]}] +set_property PACKAGE_PIN AT2 [get_ports {pci_express_x16_rxp[10]}] +set_property PACKAGE_PIN AT1 [get_ports {pci_express_x16_rxn[10]}] +set_property PACKAGE_PIN AT7 [get_ports {pci_express_x16_txp[10]}] +set_property PACKAGE_PIN AT6 [get_ports {pci_express_x16_txn[10]}] +set_property PACKAGE_PIN AP2 [get_ports {pci_express_x16_rxp[8]}] +set_property PACKAGE_PIN AP1 [get_ports {pci_express_x16_rxn[8]}] +set_property PACKAGE_PIN AP7 [get_ports {pci_express_x16_txp[8]}] +set_property PACKAGE_PIN AP6 [get_ports {pci_express_x16_txn[8]}] +set_property PACKAGE_PIN AR4 [get_ports {pci_express_x16_rxp[9]}] +set_property PACKAGE_PIN AR3 [get_ports {pci_express_x16_rxn[9]}] +set_property PACKAGE_PIN AR9 [get_ports {pci_express_x16_txp[9]}] +set_property PACKAGE_PIN AR8 [get_ports {pci_express_x16_txn[9]}] +set_property PACKAGE_PIN AN4 [get_ports {pci_express_x16_rxp[7]}] +set_property PACKAGE_PIN AN3 [get_ports {pci_express_x16_rxn[7]}] +set_property PACKAGE_PIN AN9 [get_ports {pci_express_x16_txp[7]}] +set_property PACKAGE_PIN AN8 [get_ports {pci_express_x16_txn[7]}] +set_property PACKAGE_PIN AM2 [get_ports {pci_express_x16_rxp[6]}] +set_property PACKAGE_PIN AM1 [get_ports {pci_express_x16_rxn[6]}] +set_property PACKAGE_PIN AM7 [get_ports {pci_express_x16_txp[6]}] +set_property PACKAGE_PIN AM6 [get_ports {pci_express_x16_txn[6]}] +set_property PACKAGE_PIN AL4 [get_ports {pci_express_x16_rxp[5]}] +set_property PACKAGE_PIN AL3 [get_ports {pci_express_x16_rxn[5]}] +set_property PACKAGE_PIN AL9 [get_ports {pci_express_x16_txp[5]}] +set_property PACKAGE_PIN AL8 [get_ports {pci_express_x16_txn[5]}] +set_property PACKAGE_PIN AK2 [get_ports {pci_express_x16_rxp[4]}] +set_property PACKAGE_PIN AK1 [get_ports {pci_express_x16_rxn[4]}] +set_property PACKAGE_PIN AK7 [get_ports {pci_express_x16_txp[4]}] +set_property PACKAGE_PIN AK6 [get_ports {pci_express_x16_txn[4]}] +#set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 +set_property PACKAGE_PIN AJ4 [get_ports {pci_express_x16_rxp[3]}] +set_property PACKAGE_PIN AJ3 [get_ports {pci_express_x16_rxn[3]}] +set_property PACKAGE_PIN AJ9 [get_ports {pci_express_x16_txp[3]}] +set_property PACKAGE_PIN AJ8 [get_ports {pci_express_x16_txn[3]}] +set_property PACKAGE_PIN AH2 [get_ports {pci_express_x16_rxp[2]}] +set_property PACKAGE_PIN AH1 [get_ports {pci_express_x16_rxn[2]}] +set_property PACKAGE_PIN AH7 [get_ports {pci_express_x16_txp[2]}] +set_property PACKAGE_PIN AH6 [get_ports {pci_express_x16_txn[2]}] +set_property PACKAGE_PIN AG4 [get_ports {pci_express_x16_rxp[1]}] +set_property PACKAGE_PIN AG3 [get_ports {pci_express_x16_rxn[1]}] +set_property PACKAGE_PIN AG9 [get_ports {pci_express_x16_txp[1]}] +set_property PACKAGE_PIN AG8 [get_ports {pci_express_x16_txn[1]}] +set_property PACKAGE_PIN AF2 [get_ports {pci_express_x16_rxp[0]}] +set_property PACKAGE_PIN AF1 [get_ports {pci_express_x16_rxn[0]}] +set_property PACKAGE_PIN AF7 [get_ports {pci_express_x16_txp[0]}] +set_property PACKAGE_PIN AF6 [get_ports {pci_express_x16_txn[0]}] + +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] +set_clock_groups -asynchronous -group pcie_refclk + +#There are other 3 DDR chips in the u200, here it is only the C0 +#300MHz DDR0 system clock +set_property PACKAGE_PIN AY37 [get_ports mc_clk_p] +set_property PACKAGE_PIN AY38 [get_ports mc_clk_n] + +set_property -dict {PACKAGE_PIN AR36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[16]}] +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[15]}] +#set_property -dict {PACKAGE_PIN AN34 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_odt[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_42 +#set_property -dict {PACKAGE_PIN AM34 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_cs_n[3] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L22P_T3U_N6_DBC_AD0P_42 +set_property -dict {PACKAGE_PIN AR33 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cs_n[0]}] +set_property -dict {PACKAGE_PIN AN36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[13]}] +#set_property -dict {PACKAGE_PIN AN35 IOSTANDARD SSTL12_DCI } [get_ports ddr_addr[17] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L24P_T3U_N10_42 +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[14]}] +set_property -dict {PACKAGE_PIN AP34 IOSTANDARD SSTL12_DCI} [get_ports {ddr_odt[0]}] +#set_property -dict {PACKAGE_PIN AP33 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_cs_n[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L20N_T3L_N3_AD1N_42 +#set_property -dict {PACKAGE_PIN AN33 IOSTANDARD SSTL12_DCI } [get_ports ddr4_sdram_c0_cs_n[2] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L20P_T3L_N2_AD1P_42 +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[0]}] +set_property -dict {PACKAGE_PIN AR35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[10]}] +set_property -dict {PACKAGE_PIN AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_n[0]}] +set_property -dict {PACKAGE_PIN AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_p[0]}] +#set_property -dict {PACKAGE_PIN AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_n[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L16N_T2U_N7_QBC_AD3N_42 +#set_property -dict {PACKAGE_PIN AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports ddr_ck_p[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L16P_T2U_N6_QBC_AD3P_42 +set_property -dict {PACKAGE_PIN AT34 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[1]}] +set_property -dict {PACKAGE_PIN AU36 IOSTANDARD SSTL12_DCI} [get_ports ddr_parity] +set_property -dict {PACKAGE_PIN AT36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[0]}] +set_property -dict {PACKAGE_PIN AV37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[2]}] +set_property -dict {PACKAGE_PIN AV36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[1]}] +set_property -dict {PACKAGE_PIN AW36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[4]}] +set_property -dict {PACKAGE_PIN AW35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[3]}] +#set_property -dict {PACKAGE_PIN BA38 IOSTANDARD LVCMOS12 } [get_ports ddr4_sdram_c0_alert_n ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L11N_T1U_N9_GC_42 +set_property -dict {PACKAGE_PIN BA37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[8]}] +set_property -dict {PACKAGE_PIN BA40 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[7]}] +set_property -dict {PACKAGE_PIN BA39 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[11]}] +set_property -dict {PACKAGE_PIN BB37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[9]}] +set_property -dict {PACKAGE_PIN AY36 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[5]}] +set_property -dict {PACKAGE_PIN AY35 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[6]}] +#set_property -dict {PACKAGE_PIN BC40 IOSTANDARD SSTL12_DCI } [get_ports ddr_cke[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L9N_T1L_N5_AD12N_42 +set_property -dict {PACKAGE_PIN BC39 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[1]}] +set_property -dict {PACKAGE_PIN BB40 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[12]}] +set_property -dict {PACKAGE_PIN BB39 IOSTANDARD SSTL12_DCI} [get_ports ddr_act_n] +set_property -dict {PACKAGE_PIN BC38 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cke[0]}] +set_property -dict {PACKAGE_PIN BC37 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[0]}] +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[66]}] +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[67]}] +set_property -dict {PACKAGE_PIN BF38 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[16]}] +set_property -dict {PACKAGE_PIN BE38 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[16]}] +set_property -dict {PACKAGE_PIN BD40 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[64]}] +set_property -dict {PACKAGE_PIN BD39 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[65]}] +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[71]}] +set_property -dict {PACKAGE_PIN BE40 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[70]}] +set_property -dict {PACKAGE_PIN BF37 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[68]}] +set_property -dict {PACKAGE_PIN BE37 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[69]}] +set_property -dict {PACKAGE_PIN BF40 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[17]}] +set_property -dict {PACKAGE_PIN BF39 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[17]}] +set_property -dict {PACKAGE_PIN AU32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[34]}] +set_property -dict {PACKAGE_PIN AT32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[35]}] +set_property -dict {PACKAGE_PIN AM32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[8]}] +set_property -dict {PACKAGE_PIN AM31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[8]}] +#set_property -dict {PACKAGE_PIN AT33 IOSTANDARD LVCMOS12 } [get_ports ddr4_sdram_c0_event_n ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_41 +set_property -dict {PACKAGE_PIN AM30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[33]}] +set_property -dict {PACKAGE_PIN AL30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[32]}] +set_property -dict {PACKAGE_PIN AR32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[38]}] +set_property -dict {PACKAGE_PIN AR31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[39]}] +set_property -dict {PACKAGE_PIN AN32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[37]}] +set_property -dict {PACKAGE_PIN AN31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[36]}] +set_property -dict {PACKAGE_PIN AP31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[9]}] +set_property -dict {PACKAGE_PIN AP30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[9]}] +set_property -dict {PACKAGE_PIN AV32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[25]}] +set_property -dict {PACKAGE_PIN AV31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[24]}] +set_property -dict {PACKAGE_PIN AW33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[6]}] +set_property -dict {PACKAGE_PIN AV33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[6]}] +set_property -dict {PACKAGE_PIN AU31 IOSTANDARD LVCMOS12} [get_ports ddr_reset_n] +set_property -dict {PACKAGE_PIN AW34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[27]}] +set_property -dict {PACKAGE_PIN AV34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[26]}] +set_property -dict {PACKAGE_PIN AY31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[29]}] +set_property -dict {PACKAGE_PIN AW31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[28]}] +set_property -dict {PACKAGE_PIN BA35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[30]}] +set_property -dict {PACKAGE_PIN BA34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[31]}] +set_property -dict {PACKAGE_PIN BA33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[7]}] +set_property -dict {PACKAGE_PIN BA32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[7]}] +set_property -dict {PACKAGE_PIN BB32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[17]}] +set_property -dict {PACKAGE_PIN BB31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[16]}] +set_property -dict {PACKAGE_PIN BB36 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[4]}] +set_property -dict {PACKAGE_PIN BB35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[4]}] +set_property -dict {PACKAGE_PIN AY33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[19]}] +set_property -dict {PACKAGE_PIN AY32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[18]}] +set_property -dict {PACKAGE_PIN BC33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[21]}] +set_property -dict {PACKAGE_PIN BC32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[20]}] +set_property -dict {PACKAGE_PIN BC34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[23]}] +set_property -dict {PACKAGE_PIN BB34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[22]}] +set_property -dict {PACKAGE_PIN BD31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[5]}] +set_property -dict {PACKAGE_PIN BC31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[5]}] +set_property -dict {PACKAGE_PIN BE33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[58]}] +set_property -dict {PACKAGE_PIN BD33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[57]}] +set_property -dict {PACKAGE_PIN BE36 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[14]}] +set_property -dict {PACKAGE_PIN BE35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[14]}] +set_property -dict {PACKAGE_PIN BD35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[59]}] +set_property -dict {PACKAGE_PIN BD34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[56]}] +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[61]}] +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[60]}] +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[63]}] +set_property -dict {PACKAGE_PIN BF34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[62]}] +set_property -dict {PACKAGE_PIN BE32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[15]}] +set_property -dict {PACKAGE_PIN BE31 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[15]}] +set_property -dict {PACKAGE_PIN AP29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[40]}] +set_property -dict {PACKAGE_PIN AP28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[41]}] +set_property -dict {PACKAGE_PIN AL29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[10]}] +set_property -dict {PACKAGE_PIN AL28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[10]}] +set_property -dict {PACKAGE_PIN AN27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[42]}] +set_property -dict {PACKAGE_PIN AM27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[43]}] +set_property -dict {PACKAGE_PIN AR28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[47]}] +set_property -dict {PACKAGE_PIN AR27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[46]}] +set_property -dict {PACKAGE_PIN AN29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[44]}] +set_property -dict {PACKAGE_PIN AM29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[45]}] +set_property -dict {PACKAGE_PIN AT30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[11]}] +set_property -dict {PACKAGE_PIN AR30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[11]}] +set_property -dict {PACKAGE_PIN AV27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[49]}] +set_property -dict {PACKAGE_PIN AU27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[50]}] +set_property -dict {PACKAGE_PIN AU30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[12]}] +set_property -dict {PACKAGE_PIN AU29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[12]}] +set_property -dict {PACKAGE_PIN AT28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[48]}] +set_property -dict {PACKAGE_PIN AT27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[51]}] +set_property -dict {PACKAGE_PIN AV29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[52]}] +set_property -dict {PACKAGE_PIN AV28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[55]}] +set_property -dict {PACKAGE_PIN AY30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[53]}] +set_property -dict {PACKAGE_PIN AW30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[54]}] +set_property -dict {PACKAGE_PIN AY28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[13]}] +set_property -dict {PACKAGE_PIN AY27 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[13]}] +set_property -dict {PACKAGE_PIN BA28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[2]}] +set_property -dict {PACKAGE_PIN BA27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[3]}] +set_property -dict {PACKAGE_PIN BB30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[0]}] +set_property -dict {PACKAGE_PIN BA30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[0]}] +set_property -dict {PACKAGE_PIN AW29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[1]}] +set_property -dict {PACKAGE_PIN AW28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[0]}] +set_property -dict {PACKAGE_PIN BC27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[6]}] +set_property -dict {PACKAGE_PIN BB27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[7]}] +set_property -dict {PACKAGE_PIN BB29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[4]}] +set_property -dict {PACKAGE_PIN BA29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[5]}] +set_property -dict {PACKAGE_PIN BC26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[1]}] +set_property -dict {PACKAGE_PIN BB26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[1]}] +set_property -dict {PACKAGE_PIN BF28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[9]}] +set_property -dict {PACKAGE_PIN BE28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[8]}] +set_property -dict {PACKAGE_PIN BD29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[2]}] +set_property -dict {PACKAGE_PIN BD28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[2]}] +set_property -dict {PACKAGE_PIN BE30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[10]}] +set_property -dict {PACKAGE_PIN BD30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[11]}] +set_property -dict {PACKAGE_PIN BF27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[12]}] +set_property -dict {PACKAGE_PIN BE27 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[13]}] +set_property -dict {PACKAGE_PIN BF30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[14]}] +set_property -dict {PACKAGE_PIN BF29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[15]}] +set_property -dict {PACKAGE_PIN BE26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[3]}] +set_property -dict {PACKAGE_PIN BD26 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[3]}] +# + +set_property PACKAGE_PIN BC21 [get_ports hbm_cattrip] +set_property IOSTANDARD LVCMOS12 [get_ports hbm_cattrip] +set_property PULLDOWN true [get_ports hbm_cattrip] + +set_false_path -from [get_pins chipset/chipset_impl/alveo_shell_i/meep_shell_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/*/C] -to [get_pins chipset/chipset_impl/init_calib_complete_f_reg/D] diff --git a/piton/design/xilinx/alveou250/devices.xml b/piton/design/xilinx/alveou250/devices.xml new file mode 100644 index 000000000..8162e9c91 --- /dev/null +++ b/piton/design/xilinx/alveou250/devices.xml @@ -0,0 +1,57 @@ + + + + + chip + + + + mem + 0x0 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + net + 0xfff0d00000 + 0x100000 + + diff --git a/piton/design/xilinx/alveou250/devices_ariane.xml b/piton/design/xilinx/alveou250/devices_ariane.xml new file mode 100644 index 000000000..d34a2d136 --- /dev/null +++ b/piton/design/xilinx/alveou250/devices_ariane.xml @@ -0,0 +1,78 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x200000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + + + + ariane_debug + 0xfff1000000 + 0x1000 + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + + ariane_clint + 0xfff1020000 + 0xc0000 + + + + + ariane_plic + 0xfff1100000 + 0x4000000 + + + + + diff --git a/piton/design/xilinx/design.tcl b/piton/design/xilinx/design.tcl index 61c944dd0..82c106c83 100644 --- a/piton/design/xilinx/design.tcl +++ b/piton/design/xilinx/design.tcl @@ -68,3 +68,7 @@ set DESIGN_PRJ_IP_FILES [concat \ ${PASSTHRU_PRJ_IP_FILES} \ ${CHIPSET_PRJ_IP_FILES} \ ] + +# Create an empty variable that will be filled in case the design uses a block design +# at board.tcl +set DESIGN_BD_FILES "" \ No newline at end of file diff --git a/piton/tools/src/proto/alveou200/board.tcl b/piton/tools/src/proto/alveou200/board.tcl new file mode 100644 index 000000000..7c726ff34 --- /dev/null +++ b/piton/tools/src/proto/alveou200/board.tcl @@ -0,0 +1,47 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# +set BOARD_PART "xilinx.com:au200:part0:1.3" +set FPGA_PART "xcu200-fsgd2104-2-e" +set VIVADO_FLOW_PERF_OPT 0 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" + +# Create a block design containing PCIe and GPIO using the FPGA_PART variable +# It will produce the "meep_shell.bd" file +set BD_NAME ${DV_ROOT}/design/chipset/xilinx/${BOARD}/meep_shell/meep_shell.bd + +if { ![file exists ${BD_NAME} ]} { + source $DV_ROOT/tools/src/proto/${BOARD}/meep_shell.tcl +} + +# Grab the file from where the above tcl script has placed it +set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/${BOARD}/meep_shell/meep_shell] + + + diff --git a/piton/tools/src/proto/alveou200/meep_shell.tcl b/piton/tools/src/proto/alveou200/meep_shell.tcl new file mode 100644 index 000000000..80c015d19 --- /dev/null +++ b/piton/tools/src/proto/alveou200/meep_shell.tcl @@ -0,0 +1,377 @@ +# Copyright (c) 2023 Daniel Jiménez Mazure +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors +# may be used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +################################################################ +# This is a generated script based on design: meep_shell +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + + +################################################################ +# START +################################################################ + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/${BOARD}/bd_alveo +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part $FPGA_PART + set_property BOARD_PART $BOARD_PART [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name meep_shell + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/${BOARD} +current_bd_design $design_name + + + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set C0_DDR4_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 C0_DDR4_0 ] + + set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi_ctrl + + set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $c0_sysclk + + set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + + # Create ports + set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] + set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] + set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set resetn [ create_bd_port -dir I -type rst resetn ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ + ] $axi_gpio_0 + + # Create instance: axi_xbar_pcie, and set properties + set axi_xbar_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar_pcie ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + CONFIG.M00_HAS_REGSLICE {4} \ + CONFIG.S00_HAS_REGSLICE {4} \ + CONFIG.S01_HAS_REGSLICE {4} \ + ] $axi_xbar_pcie + + # Create instance: chip_rstn, and set properties + set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DOUT_WIDTH {1} \ + ] $chip_rstn + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_InputClockPeriod {3331} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + ] $ddr4_0 + + # Create instance: proc_sys_rst_pcie, and set properties + set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] + + # Create instance: qdma_0, and set properties + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.PF0_SRIOV_CAP_INITIAL_VF {4} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.axilite_master_en {true} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.barlite_mb_pf1 {0} \ + CONFIG.barlite_mb_pf2 {0} \ + CONFIG.barlite_mb_pf3 {0} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pcie_blk_locn {X1Y2} \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_64bit_qdma {true} \ + CONFIG.pf0_bar2_enabled_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_64bit_qdma {true} \ + CONFIG.pf1_bar2_enabled_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar2_64bit_qdma {true} \ + CONFIG.pf2_bar2_enabled_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar2_64bit_qdma {true} \ + CONFIG.pf3_bar2_enabled_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X16} \ + CONFIG.testname {mm} \ + CONFIG.tl_pf_enable_reg {1} \ + ] $qdma_0 + + # Create instance: rst_ea_CLK0, and set properties + set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] + + # Create instance: sys_rstn, and set properties + set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + ] $sys_rstn + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $util_ds_buf + + # Create instance: vdd_0, and set properties + set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net C0_SYS_CLK_0_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net axi_xbar_pcie_M00_AXI [get_bd_intf_pins axi_xbar_pcie/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports C0_DDR4_0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net c0_ddr4_s_axi_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins axi_xbar_pcie/S01_AXI] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins axi_xbar_pcie/S00_AXI] [get_bd_intf_pins qdma_0/M_AXI] + connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] + connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_xbar_pcie/ACLK] [get_bd_pins axi_xbar_pcie/M00_ACLK] [get_bd_pins axi_xbar_pcie/S01_ACLK] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] + connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net -net proc_sys_rst_pcie_peripheral_aresetn [get_bd_pins axi_xbar_pcie/S00_ARESETN] [get_bd_pins proc_sys_rst_pcie/peripheral_aresetn] + connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_xbar_pcie/S00_ACLK] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] + connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] + connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] + connect_bd_net -net rst_ea_CLK0_interconnect_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins axi_xbar_pcie/ARESETN] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] + connect_bd_net -net rst_ea_CLK0_peripheral_aresetn [get_bd_pins axi_xbar_pcie/M00_ARESETN] [get_bd_pins axi_xbar_pcie/S01_ARESETN] [get_bd_pins rst_ea_CLK0/peripheral_aresetn] + connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] + connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] + connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] + + create_bd_port -dir O -type clk c0_ddr4_ui_clk + connect_bd_net [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + + # Exclude Address Segments + exclude_bd_addr_seg -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] + + # ################################################################## + # Final changes. Use this block to customize the bd + set_property name c0_ddr4 [get_bd_intf_ports C0_DDR4_0] + + # Decrease the PCIe speed for better timing results + set_property -dict [list CONFIG.pl_link_cap_max_link_speed {2.5_GT/s} CONFIG.axi_data_width {128_bit} CONFIG.plltype {CPLL} CONFIG.pf0_device_id {901F} CONFIG.pf2_device_id {921F} CONFIG.pf3_device_id {931F}] [get_bd_cells qdma_0] + + + # ################################################################### + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} + + diff --git a/piton/tools/src/proto/alveou250/board.tcl b/piton/tools/src/proto/alveou250/board.tcl new file mode 100644 index 000000000..f11e098f9 --- /dev/null +++ b/piton/tools/src/proto/alveou250/board.tcl @@ -0,0 +1,47 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# + +set BOARD_PART "xilinx.com:au250:part0:1.3" +set FPGA_PART "xcu250-figd2104-2L-e" +set VIVADO_FLOW_PERF_OPT 0 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" + +# Create a block design containing PCIe and GPIO using the FPGA_PART variable +# It will produce the "meep_shell.bd" file +set BD_NAME ${DV_ROOT}/design/chipset/xilinx/${BOARD}/meep_shell/meep_shell.bd +if { ![file exists ${BD_NAME} ]} { + source $DV_ROOT/tools/src/proto/${BOARD}/meep_shell.tcl +} + +# Grab the file from where the above tcl script has placed it +set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/alveou250/meep_shell/meep_shell] + + + diff --git a/piton/tools/src/proto/alveou250/meep_shell.tcl b/piton/tools/src/proto/alveou250/meep_shell.tcl new file mode 100644 index 000000000..b887457e9 --- /dev/null +++ b/piton/tools/src/proto/alveou250/meep_shell.tcl @@ -0,0 +1,392 @@ +# Copyright (c) 2023 Daniel Jiménez Mazure +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# 3. Neither the name of the copyright holder nor the names of its contributors +# may be used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +################################################################ +# This is a generated script based on design: meep_shell +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source meep_shell_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./tmp_proj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/alveou250/bd_alveo +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu250-figd2104-2L-e + set_property BOARD_PART xilinx.com:au250:part0:1.3 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name meep_shell + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou250 +current_bd_design $design_name + + + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set C0_DDR4_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 C0_DDR4_0 ] + + set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi_ctrl + + set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $c0_sysclk + + set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + + # Create ports + set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] + set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] + set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set resetn [ create_bd_port -dir I -type rst resetn ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ + ] $axi_gpio_0 + + # Create instance: axi_xbar_pcie, and set properties + set axi_xbar_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar_pcie ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + CONFIG.M00_HAS_REGSLICE {4} \ + CONFIG.S00_HAS_REGSLICE {4} \ + CONFIG.S01_HAS_REGSLICE {4} \ + ] $axi_xbar_pcie + + # Create instance: chip_rstn, and set properties + set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DOUT_WIDTH {1} \ + ] $chip_rstn + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_InputClockPeriod {3331} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + ] $ddr4_0 + + # Create instance: proc_sys_rst_pcie, and set properties + set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] + + # Create instance: qdma_0, and set properties + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.PF0_SRIOV_CAP_INITIAL_VF {4} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.axilite_master_en {true} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.barlite_mb_pf1 {0} \ + CONFIG.barlite_mb_pf2 {0} \ + CONFIG.barlite_mb_pf3 {0} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pcie_blk_locn {X0Y1} \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_64bit_qdma {true} \ + CONFIG.pf0_bar2_enabled_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_64bit_qdma {true} \ + CONFIG.pf1_bar2_enabled_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar2_64bit_qdma {true} \ + CONFIG.pf2_bar2_enabled_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar2_64bit_qdma {true} \ + CONFIG.pf3_bar2_enabled_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X16} \ + CONFIG.testname {mm} \ + CONFIG.tl_pf_enable_reg {1} \ + ] $qdma_0 + + # Create instance: rst_ea_CLK0, and set properties + set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] + + # Create instance: sys_rstn, and set properties + set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + ] $sys_rstn + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $util_ds_buf + + # Create instance: vdd_0, and set properties + set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net C0_SYS_CLK_0_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net axi_xbar_pcie_M00_AXI [get_bd_intf_pins axi_xbar_pcie/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports C0_DDR4_0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net c0_ddr4_s_axi_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins axi_xbar_pcie/S01_AXI] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins axi_xbar_pcie/S00_AXI] [get_bd_intf_pins qdma_0/M_AXI] + connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] + connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_xbar_pcie/ACLK] [get_bd_pins axi_xbar_pcie/M00_ACLK] [get_bd_pins axi_xbar_pcie/S01_ACLK] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] + connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net -net proc_sys_rst_pcie_peripheral_aresetn [get_bd_pins axi_xbar_pcie/S00_ARESETN] [get_bd_pins proc_sys_rst_pcie/peripheral_aresetn] + connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_xbar_pcie/S00_ACLK] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] + connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] + connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] + connect_bd_net -net rst_ea_CLK0_interconnect_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins axi_xbar_pcie/ARESETN] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] + connect_bd_net -net rst_ea_CLK0_peripheral_aresetn [get_bd_pins axi_xbar_pcie/M00_ARESETN] [get_bd_pins axi_xbar_pcie/S01_ARESETN] [get_bd_pins rst_ea_CLK0/peripheral_aresetn] + connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] + connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] + connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] + + create_bd_port -dir O -type clk c0_ddr4_ui_clk + connect_bd_net [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000400000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + + # Exclude Address Segments + exclude_bd_addr_seg -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] + + # ################################################################## + # Final changes. Use this block to customize the bd + set_property name c0_ddr4 [get_bd_intf_ports C0_DDR4_0] + + # Decrease the PCIe speed for better timing results + set_property -dict [list CONFIG.pl_link_cap_max_link_speed {2.5_GT/s} CONFIG.axi_data_width {128_bit} CONFIG.plltype {CPLL} CONFIG.pf0_device_id {901F} CONFIG.pf2_device_id {921F} CONFIG.pf3_device_id {931F}] [get_bd_cells qdma_0] + + + # ################################################################### + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} + + diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 04a332390..d2746651a 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,7 +25,7 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou200,100,16384;alveou250,100,16384 chipset chipset genesys2,66.667,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 diff --git a/piton/tools/src/proto/board.list b/piton/tools/src/proto/board.list index 6149781e9..4c3eb356f 100644 --- a/piton/tools/src/proto/board.list +++ b/piton/tools/src/proto/board.list @@ -30,3 +30,6 @@ nexysVideo vivado f1 vivado vcu118 vivado xupp3r vivado +alveou200 vivado +alveou250 vivado + diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 7bcf1d82d..5f0e59a9a 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -655,6 +655,7 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/alveo_shell_top.sv" \ "${DV_ROOT}/design/chipset/mc/rtl/noc_mig_bridge.v" \ "${DV_ROOT}/design/chipset/mc/rtl/memory_zeroer.v" \ "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 3a2f15efa..cf69dd5f3 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -62,10 +62,17 @@ foreach ip_file ${ALL_IP_FILE_PREFIXES} { lappend ALL_XCO_IP_FILES "${ip_file}.xco" } +set ALL_BD_FILES [list ] +foreach bd_file ${DESIGN_BD_FILES} { + lappend ALL_BD_FILES "${bd_file}.bd" +} + + set ALL_COE_FILES [concat ${DESIGN_COE_IP_FILES}] set ALL_PRJ_IP_FILES [concat ${DESIGN_PRJ_IP_FILES}] + # get pyhp globals # note that this may override some evironment vars! global ::env diff --git a/piton/tools/src/proto/fpga_lib.py b/piton/tools/src/proto/fpga_lib.py index 46f0870ea..a112534e1 100644 --- a/piton/tools/src/proto/fpga_lib.py +++ b/piton/tools/src/proto/fpga_lib.py @@ -48,6 +48,8 @@ NOC_PAYLOAD_WIDTH = 512 STORAGE_BLOCK_BIT_WIDTH = { "ddr": { "vc707":512, "vcu118":512, + "alveou200":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":128, "genesys2":256, @@ -56,6 +58,8 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou200":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -65,6 +69,8 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou200":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -76,6 +82,8 @@ STORAGE_ADDRESSABLE_BIT_WIDTH = { "ddr": { "vc707":64, "vcu118":64, + "alveou200":72, + "alveou250":72, "xupp3r":64, "nexys4ddr":16, "genesys2":32, @@ -84,6 +92,8 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou200":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -93,6 +103,8 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou200":512, + "alveou250":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -104,6 +116,8 @@ STORAGE_BIT_SIZE = { "ddr": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou200":2*8*2**30, + "alveou250":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, @@ -112,6 +126,8 @@ }, "bram": { "vc707":16384*512, "vcu118":16384*512, + "alveou200":16384*512, + "alveou250":16384*512, "xupp3r":16384*512, "nexys4ddr":16384*512, "genesys2":16384*512, @@ -121,6 +137,8 @@ }, "dmw": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou200":2*8*2**30, + "alveou250":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 376e7143f..8c3352fdf 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -64,6 +64,8 @@ def usage(): print(" genesys2", file=sys.stderr) print(" nexysVideo", file=sys.stderr) print(" f1", file=sys.stderr) + print(" alveou200", file=sys.stderr) + print(" alveou250", file=sys.stderr) print("\n -d, --design ", file=sys.stderr) print(" Name of design module to synthesize. The default is 'system', which", file=sys.stderr) print(" synthesizes a full system with chip and chipset. See", file=sys.stderr) @@ -514,7 +516,7 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1"}): + if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou200", "alveou250"}): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") diff --git a/piton/tools/src/proto/vivado/setup.tcl b/piton/tools/src/proto/vivado/setup.tcl index b63e811ae..c5a724e40 100644 --- a/piton/tools/src/proto/vivado/setup.tcl +++ b/piton/tools/src/proto/vivado/setup.tcl @@ -34,4 +34,5 @@ set ALL_FILES [concat \ $ALL_COE_FILES \ $ALL_PRJ_IP_FILES \ $ALL_XCI_IP_FILES \ + $ALL_BD_FILES \ ]