From 6ea0c5bead934e30b48a9d9a2f90605251a85c29 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Wed, 21 Nov 2018 22:20:09 +0900 Subject: [PATCH 1/2] enable_dump and disable_dump methods --- .../thread_/stream_dump_mask/Makefile | 29 ++++ .../test_thread_stream_dump_mask.py | 18 +++ .../thread_stream_dump_mask.py | 143 ++++++++++++++++++ veriloggen/fsm/fsm.py | 48 +++--- veriloggen/seq/seq.py | 38 +++-- veriloggen/stream/stream.py | 54 ++++--- veriloggen/thread/stream.py | 33 +++- 7 files changed, 297 insertions(+), 66 deletions(-) create mode 100644 tests/extension/thread_/stream_dump_mask/Makefile create mode 100644 tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py create mode 100644 tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py diff --git a/tests/extension/thread_/stream_dump_mask/Makefile b/tests/extension/thread_/stream_dump_mask/Makefile new file mode 100644 index 00000000..13c4fb29 --- /dev/null +++ b/tests/extension/thread_/stream_dump_mask/Makefile @@ -0,0 +1,29 @@ +TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) +ARGS= + +PYTHON=python3 +#PYTHON=python +#OPT=-m pdb +#OPT=-m cProfile -s time +#OPT=-m cProfile -o profile.rslt + +.PHONY: all +all: test + +.PHONY: run +run: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) + +.PHONY: test +test: + $(PYTHON) -m pytest -vv + +.PHONY: check +check: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v + iverilog -tnull -Wall tmp.v + rm -f tmp.v + +.PHONY: clean +clean: + rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd diff --git a/tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py b/tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py new file mode 100644 index 00000000..77213ea7 --- /dev/null +++ b/tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py @@ -0,0 +1,18 @@ +from __future__ import absolute_import +from __future__ import print_function + +import os +import veriloggen +import thread_stream_dump_mask + + +def test(request): + veriloggen.reset() + + simtype = request.config.getoption('--sim') + + rslt = thread_stream_dump_mask.run(filename=None, simtype=simtype, + outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') + + verify_rslt = rslt.splitlines()[-1] + assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py b/tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py new file mode 100644 index 00000000..8602675d --- /dev/null +++ b/tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py @@ -0,0 +1,143 @@ +from __future__ import absolute_import +from __future__ import print_function +import sys +import os + +# the next line can be removed after installation +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) + +from veriloggen import * +import veriloggen.thread as vthread +import veriloggen.types.axi as axi + + +def mkLed(): + m = Module('blinkled') + clk = m.Input('CLK') + rst = m.Input('RST') + + datawidth = 32 + addrwidth = 10 + myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth) + ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth) + ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth) + ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth) + + strm = vthread.Stream(m, 'mystream', clk, rst, + dump=True, dump_base=10, dump_mode='all') + a = strm.source('a') + b = strm.source('b') + c = a + b + strm.sink(c, 'c') + + def comp_stream(size, offset): + strm.set_source('a', ram_a, offset, size) + strm.set_source('b', ram_b, offset, size) + strm.set_sink('c', ram_c, offset, size) + strm.run() + strm.join() + strm.disable_dump() + + def comp_sequential(size, offset): + sum = 0 + for i in range(size): + a = ram_a.read(i + offset) + b = ram_b.read(i + offset) + sum = a + b + ram_c.write(i + offset, sum) + + def check(size, offset_stream, offset_seq): + all_ok = True + for i in range(size): + st = ram_c.read(i + offset_stream) + sq = ram_c.read(i + offset_seq) + if vthread.verilog.NotEql(st, sq): + all_ok = False + if all_ok: + print('# verify: PASSED') + else: + print('# verify: FAILED') + + def comp(size): + # stream + offset = 0 + myaxi.dma_read(ram_a, offset, 0, size) + myaxi.dma_read(ram_b, offset, 512, size) + comp_stream(size, offset) + comp_stream(size, offset) # dump disabled + myaxi.dma_write(ram_c, offset, 1024, size) + + # sequential + offset = size + myaxi.dma_read(ram_a, offset, 0, size) + myaxi.dma_read(ram_b, offset, 512, size) + comp_sequential(size, offset) + myaxi.dma_write(ram_c, offset, 1024 * 2, size) + + # verification + check(size, 0, offset) + + vthread.finish() + + th = vthread.Thread(m, 'th_comp', clk, rst, comp) + fsm = th.start(32) + + return m + + +def mkTest(memimg_name=None): + m = Module('test') + + # target instance + led = mkLed() + + # copy paras and ports + params = m.copy_params(led) + ports = m.copy_sim_ports(led) + + clk = ports['CLK'] + rst = ports['RST'] + + memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name) + memory.connect(ports, 'myaxi') + + uut = m.Instance(led, 'uut', + params=m.connect_params(led), + ports=m.connect_ports(led)) + + #simulation.setup_waveform(m, uut) + simulation.setup_clock(m, clk, hperiod=5) + init = simulation.setup_reset(m, rst, m.make_reset(), period=100) + + init.add( + Delay(1000000), + Systask('finish'), + ) + + return m + + +def run(filename='tmp.v', simtype='iverilog', outputfile=None): + + if outputfile is None: + outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out' + + memimg_name = 'memimg_' + outputfile + + test = mkTest(memimg_name=memimg_name) + + if filename is not None: + test.to_verilog(filename) + + sim = simulation.Simulator(test, sim=simtype) + rslt = sim.run(outputfile=outputfile) + lines = rslt.splitlines() + if simtype == 'verilator' and lines[-1].startswith('-'): + rslt = '\n'.join(lines[:-1]) + return rslt + + +if __name__ == '__main__': + rslt = run(filename='tmp.v') + print(rslt) diff --git a/veriloggen/fsm/fsm.py b/veriloggen/fsm/fsm.py index b22ba8e3..273056d3 100644 --- a/veriloggen/fsm/fsm.py +++ b/veriloggen/fsm/fsm.py @@ -83,7 +83,7 @@ def __init__(self, m, name, clk, rst, width=32, initname='init', if not nohook: self.m.add_hook(self.implement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def goto(self, dst, cond=None, else_dst=None): if cond is None and 'cond' in self.next_kwargs: cond = self.next_kwargs['cond'] @@ -130,7 +130,7 @@ def goto_from(self, src, dst, cond=None, else_dst=None): def inc(self): self._set_index(None) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def add(self, *statement, **kwargs): """ add new assignments """ kwargs.update(self.next_kwargs) @@ -152,11 +152,15 @@ def add(self, *statement, **kwargs): self._clear_last_if_statement() return self._add_statement(statement, **kwargs) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- + def add_reset(self, v): + return self.seq.add_reset(v) + + # ------------------------------------------------------------------------- def Prev(self, var, delay, initval=0, cond=None, prefix=None): return self.seq.Prev(var, delay, initval, cond, prefix) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def If(self, *cond): self._clear_elif_cond() @@ -267,7 +271,7 @@ def Clear(self): self._clear_elif_cond() return self - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- @property def current(self): return self.state_count @@ -314,7 +318,7 @@ def then(self): def here(self): return self.state == self.current - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def implement(self): if self.as_module: self.make_module() @@ -322,7 +326,7 @@ def implement(self): self.make_always() - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_always(self, reset=(), body=(), case=True): if self.done: #raise ValueError('make_always() has been already called.') @@ -340,7 +344,7 @@ def make_always(self, reset=(), body=(), case=True): part_body, )) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_module(self, reset=(), body=(), case=True): if self.done: #raise ValueError('make_always() has been already called.') @@ -530,7 +534,7 @@ def make_module(self, reset=(), body=(), case=True): sub = Submodule(self.m, m, 'inst_' + m.name, '_%s_' % self.name, arg_params=arg_params, arg_ports=arg_ports) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_case(self): indexes = set(self.body.keys()) indexes.update(set(self.jump.keys())) @@ -578,7 +582,7 @@ def make_if(self): for index in sorted(indexes, key=lambda x:x)]) return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_reset(self, reset): ret = collections.OrderedDict() @@ -621,11 +625,11 @@ def make_reset(self, reset): return list(ret.values()) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def set_index(self, index): return self._set_index(index) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _go(self, src, dst, cond=None, else_dst=None): self._add_jump(src, dst, cond, else_dst) return self @@ -633,7 +637,7 @@ def _go(self, src, dst, cond=None, else_dst=None): def _add_jump(self, src, dst, cond=None, else_dst=None): self.jump[src].append((dst, cond, else_dst)) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_statement(self, statement, index=None, keep=None, delay=None, cond=None, lazy_cond=False, eager_val=False, no_delay_cond=False): @@ -686,7 +690,7 @@ def _add_statement(self, statement, index=None, keep=None, delay=None, cond=None return self - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_dst_var(self, statement): for s in statement: values = self.dst_visitor.visit(s) @@ -695,7 +699,7 @@ def _add_dst_var(self, statement): if k not in self.dst_var: self.dst_var[k] = v - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_delayed_cond(self, statement, index, delay): name_prefix = '_'.join( ['', self.name, 'cond', str(index), str(self.tmp_count)]) @@ -709,7 +713,7 @@ def _add_delayed_cond(self, statement, index, delay): prev = tmp return prev - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_delayed_subst(self, subst, index, delay): if not isinstance(subst, vtypes.Subst): return subst @@ -734,7 +738,7 @@ def _add_delayed_subst(self, subst, index, delay): prev = tmp return left(prev) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _clear_next_kwargs(self): self.next_kwargs = {} @@ -756,7 +760,7 @@ def _make_cond(self, condlist): ret = vtypes.Ands(ret, cond) return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _set_index(self, index=None): if index is None: self.state_count += 1 @@ -784,7 +788,7 @@ def _get_mark_index(self, s): return index raise KeyError("No such mark in FSM marks: %s" % s.name) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_mark(self, index): index = self._to_index(index) if index not in self.mark: @@ -797,7 +801,7 @@ def _to_index(self, index): index = self._get_mark_index(index) return index - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_delayed_state(self, value): if not isinstance(value, int): raise TypeError("Delay amount must be int, not '%s'" % @@ -851,7 +855,7 @@ def _to_state_assign(self, dst, cond=None, else_dst=None): value = value.Else(self.state(else_dst_mark)) return value - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _cond_case(self, index): if index not in self.mark: self._set_mark(index) @@ -895,7 +899,7 @@ def _get_if_statement(self, index): def _get_delayed_if_statement(self, index, delay): return vtypes.If(self._delayed_cond_if(index, delay))(*self.delayed_body[delay][index]) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def __call__(self, *statement, **kwargs): return self.add(*statement, **kwargs) diff --git a/veriloggen/seq/seq.py b/veriloggen/seq/seq.py index 2572a506..8367d169 100644 --- a/veriloggen/seq/seq.py +++ b/veriloggen/seq/seq.py @@ -98,7 +98,7 @@ def __init__(self, m, name, clk, rst=None, nohook=False, as_module=False): if not nohook: self.m.add_hook(self.implement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def add(self, *statement, **kwargs): """ Adding a new assignment. This method is usually called via __call__(). """ kwargs.update(self.next_kwargs) @@ -120,7 +120,13 @@ def add(self, *statement, **kwargs): self._clear_last_if_statement() return self._add_statement(statement, **kwargs) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- + def add_reset(self, v): + k = str(v) + if k not in self.dst_var: + self.dst_var[k] = v + + # ------------------------------------------------------------------------- def Prev(self, var, delay, initval=0, cond=None, prefix=None): """ returns a value with the specified delay """ if not isinstance(delay, int): @@ -168,7 +174,7 @@ def Prev(self, var, delay, initval=0, cond=None, prefix=None): return p - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def If(self, *cond): self._clear_elif_cond() @@ -278,7 +284,7 @@ def Clear(self): self._clear_elif_cond() return self - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- @property def current_delay(self): if 'delay' in self.next_kwargs: @@ -305,7 +311,7 @@ def last_condition(self): def then(self): return self.last_condition - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def update(self, src): if not isinstance(src, Seq): @@ -341,7 +347,7 @@ def update(self, src): # Invalidated source Seq src.done = True - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def implement(self): if self.as_module: self.make_module() @@ -349,7 +355,7 @@ def implement(self): self.make_always() - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_always(self, reset=(), body=()): if self.done: #raise ValueError('make_always() has been already called.') @@ -374,7 +380,7 @@ def make_always(self, reset=(), body=()): part_body, )) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_module(self, reset=(), body=()): if self.done: #raise ValueError('make_always() has been already called.') @@ -520,7 +526,7 @@ def make_module(self, reset=(), body=()): sub = Submodule(self.m, m, 'inst_' + m.name, '_%s_' % self.name, arg_params=arg_params, arg_ports=arg_ports) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_code(self): ret = [] @@ -531,7 +537,7 @@ def make_code(self): ret.extend(self.body) return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_reset(self): ret = [] for dst in self.dst_var.values(): @@ -540,7 +546,7 @@ def make_reset(self): ret.append(v) return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_statement(self, statement, keep=None, delay=None, cond=None, lazy_cond=False, eager_val=False, no_delay_cond=False): @@ -590,7 +596,7 @@ def _add_statement(self, statement, keep=None, delay=None, cond=None, return self - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_dst_var(self, statement): for s in statement: values = self.dst_visitor.visit(s) @@ -599,7 +605,7 @@ def _add_dst_var(self, statement): if k not in self.dst_var: self.dst_var[k] = v - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_delayed_cond(self, statement, delay): name_prefix = '_'.join(['', self.name, 'cond', str(self.tmp_count)]) self.tmp_count += 1 @@ -611,7 +617,7 @@ def _add_delayed_cond(self, statement, delay): prev = tmp return prev - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_delayed_subst(self, subst, delay): if not isinstance(subst, vtypes.Subst): return subst @@ -636,7 +642,7 @@ def _add_delayed_subst(self, subst, delay): prev = tmp return left(prev) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _clear_next_kwargs(self): self.next_kwargs = {} @@ -658,6 +664,6 @@ def _make_cond(self, condlist): ret = vtypes.Ands(ret, cond) return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def __call__(self, *statement, **kwargs): return self.add(*statement, **kwargs) diff --git a/veriloggen/stream/stream.py b/veriloggen/stream/stream.py index 074acdec..85530fdd 100644 --- a/veriloggen/stream/stream.py +++ b/veriloggen/stream/stream.py @@ -88,6 +88,22 @@ def __init__(self, *nodes, **opts): '_stream_seq_%d' % self.object_id) self.seq = Seq(self.module, seq_name, self.clock, self.reset) + if self.dump: + dump_enable_name = '_stream_dump_enable_%d' % self.object_id + dump_enable = self.module.Reg(dump_enable_name, initval=0) + dump_mask_name = '_stream_dump_mask_%d' % self.object_id + dump_mask = self.module.Reg(dump_mask_name, initval=0) + dump_step_name = '_stream_dump_step_%d' % self.object_id + dump_step = self.module.Reg(dump_step_name, 32, + initval=0, signed=True) + self.dump_enable = dump_enable + self.dump_mask = dump_mask + self.dump_step = dump_step + + if self.seq: + self.seq.add_reset(self.dump_enable) + self.seq.add_reset(self.dump_mask) + # ------------------------------------------------------------------------- def add(self, *nodes): self.nodes.update(set(nodes)) @@ -229,25 +245,17 @@ def implement(self, m=None, clock=None, reset=None, aswire=None, seq_name=None): return m def add_dump(self, m, seq, input_vars, output_vars, all_vars): - dump_enable_name = '_stream_dump_enable_%d' % self.object_id - dump_enable = m.Reg(dump_enable_name, initval=0) - dump_step_name = '_stream_dump_step_%d' % self.object_id - dump_step = m.Reg(dump_step_name, 32, initval=0, signed=True) - - self.dump_step = dump_step - self.dump_enable = dump_enable - pipeline_depth = self.pipeline_depth() log_pipeline_depth = max( int(math.ceil(math.log(pipeline_depth, 10))), 1) seq( - dump_step(0) + self.dump_step(0) ) for i in range(pipeline_depth + 1): - seq.If(seq.Prev(dump_enable, i))( - dump_step.inc() + seq.If(seq.Prev(self.dump_enable, i))( + self.dump_step.inc() ) def get_name(obj): @@ -351,9 +359,9 @@ def get_name(obj): name_alignment, name, ' = ', vfmt]) stage = input_var.end_stage if input_var.end_stage is not None else 0 - enable = seq.Prev(dump_enable, stage) + enable = seq.Prev(self.dump_enable, stage) enables.append(enable) - age = seq.Prev(dump_step, stage) + age = seq.Prev(self.dump_step, stage) if input_var.point == 0: sig_data = input_var.sig_data @@ -361,8 +369,8 @@ def get_name(obj): sig_data = vtypes.Div(vtypes.SystemTask('itor', input_var.sig_data), 1.0 * (2 ** input_var.point)) - seq.If(enable)( - vtypes.Display(fmt, dump_step, stage, age, sig_data) + seq.If(enable, vtypes.Not(self.dump_mask))( + vtypes.Display(fmt, self.dump_step, stage, age, sig_data) ) for var in sorted(all_vars, key=lambda x: (-1, x.object_id) @@ -384,9 +392,9 @@ def get_name(obj): 'stage:%', str(log_pipeline_depth), 'd, age:%d> ', name_alignment, name, ' = ', vfmt]) - enable = seq.Prev(dump_enable, stage) + enable = seq.Prev(self.dump_enable, stage) enables.append(enable) - age = seq.Prev(dump_step, stage) + age = seq.Prev(self.dump_step, stage) if var.point == 0: sig_data = var.sig_data @@ -394,8 +402,8 @@ def get_name(obj): sig_data = vtypes.Div(vtypes.SystemTask('itor', var.sig_data), 1.0 * (2 ** var.point)) - seq.If(enable)( - vtypes.Display(fmt, dump_step, stage, age, sig_data) + seq.If(enable, vtypes.Not(self.dump_mask))( + vtypes.Display(fmt, self.dump_step, stage, age, sig_data) ) for output_var in sorted(output_vars, key=lambda x: x.object_id): @@ -418,9 +426,9 @@ def get_name(obj): name_alignment, name, ' = ', vfmt]) stage = output_var.end_stage if output_var.end_stage is not None else 0 - enable = seq.Prev(dump_enable, stage) + enable = seq.Prev(self.dump_enable, stage) enables.append(enable) - age = seq.Prev(dump_step, stage) + age = seq.Prev(self.dump_step, stage) if output_var.point == 0: sig_data = output_var.output_sig_data @@ -428,8 +436,8 @@ def get_name(obj): sig_data = vtypes.Div(vtypes.SystemTask('itor', output_var.output_sig_data), 1.0 * (2 ** output_var.point)) - seq.If(enable)( - vtypes.Display(fmt, dump_step, stage, age, sig_data) + seq.If(enable, vtypes.Not(self.dump_mask))( + vtypes.Display(fmt, self.dump_step, stage, age, sig_data) ) # ------------------------------------------------------------------------- diff --git a/veriloggen/thread/stream.py b/veriloggen/thread/stream.py index 6dafe40b..517e1bcf 100644 --- a/veriloggen/thread/stream.py +++ b/veriloggen/thread/stream.py @@ -46,7 +46,8 @@ class Stream(BaseStream): 'read_sink', 'run', 'join', 'done', 'source_join', 'source_done', - 'sink_join', 'sink_done') + 'sink_join', 'sink_done', + 'enable_dump', 'disable_dump') ram_delay = 4 def __init__(self, m, name, clk, rst, @@ -965,7 +966,7 @@ def run(self, fsm): if self.dump: dump_delay = self.ram_delay + 1 - self.fsm.seq.If(self.seq.Prev(start_cond, dump_delay))( + self.seq.If(self.seq.Prev(start_cond, dump_delay))( self.dump_enable(1) ) @@ -1025,7 +1026,7 @@ def run(self, fsm): if self.dump: dump_delay = 1 - self.fsm.seq.If(self.seq.Prev(end_cond, dump_delay))( + self.seq.If(self.seq.Prev(end_cond, dump_delay))( self.dump_enable(0) ) @@ -1149,6 +1150,28 @@ def sink_join(self, fsm): def sink_done(self, fsm): return vtypes.Not(self.sink_busy) + def enable_dump(self, fsm): + if not self.dump: + raise TypeError('dump mode is disabled.') + + self.seq.If(fsm.here)( + self.dump_mask(0) + ) + + fsm.goto_next() + return self.dump_mask + + def disable_dump(self, fsm): + if not self.dump: + raise TypeError('dump mode is disabled.') + + self.seq.If(fsm.here)( + self.dump_mask(1) + ) + + fsm.goto_next() + return self.dump_mask + def _setup_source_ram(self, ram, var, port, set_cond): if ram._id() in var.source_ram_id_map: ram_id = var.source_ram_id_map[ram._id()] @@ -1249,7 +1272,7 @@ def _setup_source_ram_dump(self, ram, var, read_enable, read_data): dump_ram_step.inc() ) - self.seq.If(enable)( + self.seq.If(enable, vtypes.Not(self.dump_mask))( vtypes.Display(fmt, dump_ram_step, age, addr, data) ) @@ -1683,7 +1706,7 @@ def _setup_sink_ram_dump(self, ram, var, write_enable): else: data = var.sink_ram_wdata - self.seq.If(enable)( + self.seq.If(enable, vtypes.Not(self.dump_mask))( vtypes.Display(fmt, self.dump_step, age, addr, data) ) From 95e3559cdd3c650764483b02890abb99569e21d3 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Wed, 21 Nov 2018 23:12:18 +0900 Subject: [PATCH 2/2] 1.4.3 --- veriloggen/utils/VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/veriloggen/utils/VERSION b/veriloggen/utils/VERSION index 9df886c4..428b770e 100644 --- a/veriloggen/utils/VERSION +++ b/veriloggen/utils/VERSION @@ -1 +1 @@ -1.4.2 +1.4.3