From b35b657524f0ac2ef1bff93bef92f8827e3e8027 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Mon, 3 Dec 2018 15:11:51 +0900 Subject: [PATCH 1/5] Updated the name of memcpy example --- examples/thread_memcpy_ipcore/thread_memcpy_ipcore.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/examples/thread_memcpy_ipcore/thread_memcpy_ipcore.py b/examples/thread_memcpy_ipcore/thread_memcpy_ipcore.py index 57ba062b..947fceda 100644 --- a/examples/thread_memcpy_ipcore/thread_memcpy_ipcore.py +++ b/examples/thread_memcpy_ipcore/thread_memcpy_ipcore.py @@ -14,10 +14,9 @@ def mkMemcpy(): - m = Module('blinkled') + m = Module('memcpy') clk = m.Input('CLK') rst = m.Input('RST') - led = m.OutputReg('led', 8, initval=0) datawidth = 32 addrwidth = 10 From b2f80c577b87787f4d4a374e13c443ecc4e11290 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Mon, 3 Dec 2018 15:24:52 +0900 Subject: [PATCH 2/5] Updated check code --- examples/thread_memcpy_ipcore/test_thread_memcpy_ipcore.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/examples/thread_memcpy_ipcore/test_thread_memcpy_ipcore.py b/examples/thread_memcpy_ipcore/test_thread_memcpy_ipcore.py index 99d1d0fd..d7741c22 100644 --- a/examples/thread_memcpy_ipcore/test_thread_memcpy_ipcore.py +++ b/examples/thread_memcpy_ipcore/test_thread_memcpy_ipcore.py @@ -8,7 +8,6 @@ reg uut_CLK; reg uut_RST; - wire [8-1:0] uut_led; wire [32-1:0] uut_maxi_awaddr; wire [8-1:0] uut_maxi_awlen; wire uut_maxi_awvalid; @@ -40,12 +39,11 @@ wire uut_saxi_rvalid; reg uut_saxi_rready; - blinkled + memcpy uut ( .CLK(uut_CLK), .RST(uut_RST), - .led(uut_led), .maxi_awaddr(uut_maxi_awaddr), .maxi_awlen(uut_maxi_awlen), .maxi_awvalid(uut_maxi_awvalid), @@ -978,11 +976,10 @@ -module blinkled +module memcpy ( input CLK, input RST, - output reg [8-1:0] led, output reg [32-1:0] maxi_awaddr, output reg [8-1:0] maxi_awlen, output reg maxi_awvalid, From a6713d78705c0d0e6e5629f4a9cf14004a2b6e65 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Sun, 9 Dec 2018 12:07:55 +0900 Subject: [PATCH 3/5] Complement2, Abs, and Sign --- veriloggen/core/vtypes.py | 24 ++++++++++ veriloggen/stream/stypes.py | 88 ++++++++++++++++++++++++++++++++++++- 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/veriloggen/core/vtypes.py b/veriloggen/core/vtypes.py index c1272b7f..92d34efb 100644 --- a/veriloggen/core/vtypes.py +++ b/veriloggen/core/vtypes.py @@ -283,6 +283,9 @@ def __pos__(self): def __invert__(self): raise TypeError('Not allowed operation.') + def __abs__(self): + raise TypeError('Not allowed operation.') + def __getitem__(self, r): raise TypeError('Not allowed operation.') @@ -361,6 +364,9 @@ def __pos__(self): def __invert__(self): return Unot(self) + def __abs__(self): + return Abs(self) + def __getitem__(self, r): if isinstance(r, slice): size = self._len() @@ -1745,6 +1751,24 @@ def Mux(condition, true_value, false_value): return Cond(condition, true_value, false_value) +def Complement2(var): + if isinstance(var, (int, bool, float)): + return abs(var) + + return Ulnot(var) + Int(1) + + +def Abs(var): + return Mux(Sign(var), Complement2(var), var) + + +def Sign(var): + if isinstance(var, (int, bool, float)): + return var < 0 + + return var < Int(0, signed=True) + + class Sensitive(VeriloggenNode): def __init__(self, name): diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index 4d20bc30..64306418 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -346,6 +346,9 @@ def __neg__(self): def __pos__(self): return Uplus(self) + def __abs__(self): + return Abs(self) + def __getitem__(self, r): if isinstance(r, slice): size = self.bit_length() @@ -1134,7 +1137,12 @@ def eval(self): class Unot(_UnaryLogicalOperator): def eval(self): - return ~ self.right.eval() + right = self.right.eval() + try: + v = ~right + except: + v = Ulnot(right) + return v class Uand(_UnaryLogicalOperator): @@ -1322,6 +1330,9 @@ def _implement(self, m, seq, svalid=None, senable=None): m.Assign(data(rdata)) + def eval(self): + return self + class _SpecialOperator(_Operator): latency = 1 @@ -1668,6 +1679,81 @@ def _implement(self, m, seq, svalid=None, senable=None): m.Instance(inst, self.name('lut'), ports=ports) +class Complement2(_SpecialOperator): + + def __init__(self, var): + _SpecialOperator.__init__(self, var) + self.op = vtypes.Complement2 + + def _set_attributes(self): + self.width = self.var.bit_length() + self.point = self.var.get_point() + self.signed = self.var.get_signed() + + @property + def var(self): + return self.args[0] + + @var.setter + def var(self, var): + self.args[0] = var + + def eval(self): + var = self.var.eval() + ret = Complement2(var) + return ret + + +class Abs(_SpecialOperator): + + def __init__(self, var): + _SpecialOperator.__init__(self, var) + self.op = vtypes.Abs + + def _set_attributes(self): + self.width = self.var.bit_length() + self.point = self.var.get_point() + self.signed = self.var.get_signed() + + @property + def var(self): + return self.args[0] + + @var.setter + def var(self, var): + self.args[0] = var + + def eval(self): + var = self.var.eval() + ret = abs(var) + return ret + + +class Sign(_SpecialOperator): + + def __init__(self, var): + _SpecialOperator.__init__(self, var) + self.op = vtypes.Sign + + def _set_attributes(self): + self.width = self.var.bit_length() + self.point = self.var.get_point() + self.signed = self.var.get_signed() + + @property + def var(self): + return self.args[0] + + @var.setter + def var(self, var): + self.args[0] = var + + def eval(self): + var = self.var.eval() + ret = Sign(var) + return ret + + class _Delay(_UnaryOperator): def __init__(self, right): From 053f53f146f3ba82a4ea64de562733ed5a0724d5 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 11 Dec 2018 00:14:28 +0900 Subject: [PATCH 4/5] Bug fix of vtypes.Sign. --- veriloggen/core/vtypes.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/veriloggen/core/vtypes.py b/veriloggen/core/vtypes.py index 92d34efb..11c9d950 100644 --- a/veriloggen/core/vtypes.py +++ b/veriloggen/core/vtypes.py @@ -1755,7 +1755,7 @@ def Complement2(var): if isinstance(var, (int, bool, float)): return abs(var) - return Ulnot(var) + Int(1) + return Unot(var) + Int(1) def Abs(var): From a79f49e3957ecb6dce3edc981bf748e1d0cf1381 Mon Sep 17 00:00:00 2001 From: shtaxxx Date: Tue, 11 Dec 2018 12:05:56 +0900 Subject: [PATCH 5/5] version 1.5.4 --- veriloggen/utils/VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/veriloggen/utils/VERSION b/veriloggen/utils/VERSION index 8af85beb..94fe62c2 100644 --- a/veriloggen/utils/VERSION +++ b/veriloggen/utils/VERSION @@ -1 +1 @@ -1.5.3 +1.5.4