diff --git a/examples/dataflow_example/test_dataflow_example.py b/examples/dataflow_example/test_dataflow_example.py index 96da4785..8394ddfb 100644 --- a/examples/dataflow_example/test_dataflow_example.py +++ b/examples/dataflow_example/test_dataflow_example.py @@ -8,13 +8,13 @@ reg CLK; reg RST; - reg [32-1:0] xdata; + reg signed [32-1:0] xdata; reg xvalid; wire xready; - reg [32-1:0] ydata; + reg signed [32-1:0] ydata; reg yvalid; wire yready; - wire [32-1:0] zdata; + wire signed [32-1:0] zdata; wire zvalid; reg zready; @@ -504,18 +504,18 @@ ( input CLK, input RST, - input [32-1:0] xdata, + input signed [32-1:0] xdata, input xvalid, output xready, - input [32-1:0] ydata, + input signed [32-1:0] ydata, input yvalid, output yready, - output [32-1:0] zdata, + output signed [32-1:0] zdata, output zvalid, input zready ); - reg [32-1:0] _plus_data_0; + reg signed [32-1:0] _plus_data_0; reg _plus_valid_0; wire _plus_ready_0; assign xready = (_plus_ready_0 || !_plus_valid_0) && (xvalid && yvalid); diff --git a/examples/dataflow_radix2/test_dataflow_radix2.py b/examples/dataflow_radix2/test_dataflow_radix2.py index 878ad31c..864cc566 100644 --- a/examples/dataflow_radix2/test_dataflow_radix2.py +++ b/examples/dataflow_radix2/test_dataflow_radix2.py @@ -8,16 +8,16 @@ reg CLK; reg RST; - reg [32-1:0] din0re; - reg [32-1:0] din0im; - reg [32-1:0] din1re; - reg [32-1:0] din1im; - reg [32-1:0] cnstre; - reg [32-1:0] cnstim; - wire [32-1:0] dout1re; - wire [32-1:0] dout1im; - wire [32-1:0] dout0re; - wire [32-1:0] dout0im; + reg signed [32-1:0] din0re; + reg signed [32-1:0] din0im; + reg signed [32-1:0] din1re; + reg signed [32-1:0] din1im; + reg signed [32-1:0] cnstre; + reg signed [32-1:0] cnstim; + wire signed [32-1:0] dout1re; + wire signed [32-1:0] dout1im; + wire signed [32-1:0] dout0re; + wire signed [32-1:0] dout0im; radix2 uut @@ -143,41 +143,41 @@ ( input CLK, input RST, - input [32-1:0] din0re, - input [32-1:0] din0im, - input [32-1:0] din1re, - input [32-1:0] din1im, - input [32-1:0] cnstre, - input [32-1:0] cnstim, - output [32-1:0] dout1re, - output [32-1:0] dout1im, - output [32-1:0] dout0re, - output [32-1:0] dout0im + input signed [32-1:0] din0re, + input signed [32-1:0] din0im, + input signed [32-1:0] din1re, + input signed [32-1:0] din1im, + input signed [32-1:0] cnstre, + input signed [32-1:0] cnstim, + output signed [32-1:0] dout1re, + output signed [32-1:0] dout1im, + output signed [32-1:0] dout0re, + output signed [32-1:0] dout0im ); - reg [32-1:0] _plus_data_0; + reg signed [32-1:0] _plus_data_0; reg _plus_valid_0; wire _plus_ready_0; - reg [32-1:0] _plus_data_1; + reg signed [32-1:0] _plus_data_1; reg _plus_valid_1; wire _plus_ready_1; - reg [32-1:0] _minus_data_2; + reg signed [32-1:0] _minus_data_2; reg _minus_valid_2; wire _minus_ready_2; - reg [32-1:0] _minus_data_3; + reg signed [32-1:0] _minus_data_3; reg _minus_valid_3; wire _minus_ready_3; - reg [32-1:0] __delay_data_4; + reg signed [32-1:0] __delay_data_4; reg __delay_valid_4; wire __delay_ready_4; - reg [32-1:0] __delay_data_5; + reg signed [32-1:0] __delay_data_5; reg __delay_valid_5; wire __delay_ready_5; - wire [32-1:0] _times_data_6; + wire signed [32-1:0] _times_data_6; wire _times_valid_6; wire _times_ready_6; - wire [64-1:0] _times_odata_6; - reg [64-1:0] _times_data_reg_6; + wire signed [64-1:0] _times_odata_6; + reg signed [64-1:0] _times_data_reg_6; assign _times_data_6 = _times_data_reg_6; wire _times_ovalid_6; reg _times_valid_reg_6; @@ -200,11 +200,11 @@ .c(_times_odata_6) ); - wire [32-1:0] _times_data_7; + wire signed [32-1:0] _times_data_7; wire _times_valid_7; wire _times_ready_7; - wire [64-1:0] _times_odata_7; - reg [64-1:0] _times_data_reg_7; + wire signed [64-1:0] _times_odata_7; + reg signed [64-1:0] _times_data_reg_7; assign _times_data_7 = _times_data_reg_7; wire _times_ovalid_7; reg _times_valid_reg_7; @@ -227,11 +227,11 @@ .c(_times_odata_7) ); - wire [32-1:0] _times_data_8; + wire signed [32-1:0] _times_data_8; wire _times_valid_8; wire _times_ready_8; - wire [64-1:0] _times_odata_8; - reg [64-1:0] _times_data_reg_8; + wire signed [64-1:0] _times_odata_8; + reg signed [64-1:0] _times_data_reg_8; assign _times_data_8 = _times_data_reg_8; wire _times_ovalid_8; reg _times_valid_reg_8; @@ -256,11 +256,11 @@ assign _minus_ready_2 = (_times_ready_6 || !_times_valid_6) && (_minus_valid_2 && __delay_valid_4) && ((_times_ready_8 || !_times_valid_8) && (_minus_valid_2 && __delay_valid_5)); assign __delay_ready_5 = (_times_ready_7 || !_times_valid_7) && (_minus_valid_3 && __delay_valid_5) && ((_times_ready_8 || !_times_valid_8) && (_minus_valid_2 && __delay_valid_5)); - wire [32-1:0] _times_data_9; + wire signed [32-1:0] _times_data_9; wire _times_valid_9; wire _times_ready_9; - wire [64-1:0] _times_odata_9; - reg [64-1:0] _times_data_reg_9; + wire signed [64-1:0] _times_odata_9; + reg signed [64-1:0] _times_data_reg_9; assign _times_data_9 = _times_data_reg_9; wire _times_ovalid_9; reg _times_valid_reg_9; @@ -285,77 +285,77 @@ assign _minus_ready_3 = (_times_ready_7 || !_times_valid_7) && (_minus_valid_3 && __delay_valid_5) && ((_times_ready_9 || !_times_valid_9) && (_minus_valid_3 && __delay_valid_4)); assign __delay_ready_4 = (_times_ready_6 || !_times_valid_6) && (_minus_valid_2 && __delay_valid_4) && ((_times_ready_9 || !_times_valid_9) && (_minus_valid_3 && __delay_valid_4)); - reg [32-1:0] __delay_data_10; + reg signed [32-1:0] __delay_data_10; reg __delay_valid_10; wire __delay_ready_10; assign _plus_ready_0 = (__delay_ready_10 || !__delay_valid_10) && _plus_valid_0; - reg [32-1:0] __delay_data_11; + reg signed [32-1:0] __delay_data_11; reg __delay_valid_11; wire __delay_ready_11; assign _plus_ready_1 = (__delay_ready_11 || !__delay_valid_11) && _plus_valid_1; - reg [32-1:0] __delay_data_12; + reg signed [32-1:0] __delay_data_12; reg __delay_valid_12; wire __delay_ready_12; assign __delay_ready_10 = (__delay_ready_12 || !__delay_valid_12) && __delay_valid_10; - reg [32-1:0] __delay_data_13; + reg signed [32-1:0] __delay_data_13; reg __delay_valid_13; wire __delay_ready_13; assign __delay_ready_11 = (__delay_ready_13 || !__delay_valid_13) && __delay_valid_11; - reg [32-1:0] __delay_data_14; + reg signed [32-1:0] __delay_data_14; reg __delay_valid_14; wire __delay_ready_14; assign __delay_ready_12 = (__delay_ready_14 || !__delay_valid_14) && __delay_valid_12; - reg [32-1:0] __delay_data_15; + reg signed [32-1:0] __delay_data_15; reg __delay_valid_15; wire __delay_ready_15; assign __delay_ready_13 = (__delay_ready_15 || !__delay_valid_15) && __delay_valid_13; - reg [32-1:0] __delay_data_16; + reg signed [32-1:0] __delay_data_16; reg __delay_valid_16; wire __delay_ready_16; assign __delay_ready_14 = (__delay_ready_16 || !__delay_valid_16) && __delay_valid_14; - reg [32-1:0] __delay_data_17; + reg signed [32-1:0] __delay_data_17; reg __delay_valid_17; wire __delay_ready_17; assign __delay_ready_15 = (__delay_ready_17 || !__delay_valid_17) && __delay_valid_15; - reg [32-1:0] __delay_data_18; + reg signed [32-1:0] __delay_data_18; reg __delay_valid_18; wire __delay_ready_18; assign __delay_ready_16 = (__delay_ready_18 || !__delay_valid_18) && __delay_valid_16; - reg [32-1:0] __delay_data_19; + reg signed [32-1:0] __delay_data_19; reg __delay_valid_19; wire __delay_ready_19; assign __delay_ready_17 = (__delay_ready_19 || !__delay_valid_19) && __delay_valid_17; - reg [32-1:0] __delay_data_20; + reg signed [32-1:0] __delay_data_20; reg __delay_valid_20; wire __delay_ready_20; assign __delay_ready_18 = (__delay_ready_20 || !__delay_valid_20) && __delay_valid_18; - reg [32-1:0] __delay_data_21; + reg signed [32-1:0] __delay_data_21; reg __delay_valid_21; wire __delay_ready_21; assign __delay_ready_19 = (__delay_ready_21 || !__delay_valid_21) && __delay_valid_19; - reg [32-1:0] __delay_data_22; + reg signed [32-1:0] __delay_data_22; reg __delay_valid_22; wire __delay_ready_22; assign __delay_ready_20 = (__delay_ready_22 || !__delay_valid_22) && __delay_valid_20; - reg [32-1:0] __delay_data_23; + reg signed [32-1:0] __delay_data_23; reg __delay_valid_23; wire __delay_ready_23; assign __delay_ready_21 = (__delay_ready_23 || !__delay_valid_23) && __delay_valid_21; - reg [32-1:0] _minus_data_24; + reg signed [32-1:0] _minus_data_24; reg _minus_valid_24; wire _minus_ready_24; assign _times_ready_6 = (_minus_ready_24 || !_minus_valid_24) && (_times_valid_6 && _times_valid_7); assign _times_ready_7 = (_minus_ready_24 || !_minus_valid_24) && (_times_valid_6 && _times_valid_7); - reg [32-1:0] _plus_data_25; + reg signed [32-1:0] _plus_data_25; reg _plus_valid_25; wire _plus_ready_25; assign _times_ready_8 = (_plus_ready_25 || !_plus_valid_25) && (_times_valid_8 && _times_valid_9); assign _times_ready_9 = (_plus_ready_25 || !_plus_valid_25) && (_times_valid_8 && _times_valid_9); - reg [32-1:0] __delay_data_26; + reg signed [32-1:0] __delay_data_26; reg __delay_valid_26; wire __delay_ready_26; assign __delay_ready_22 = (__delay_ready_26 || !__delay_valid_26) && __delay_valid_22; - reg [32-1:0] __delay_data_27; + reg signed [32-1:0] __delay_data_27; reg __delay_valid_27; wire __delay_ready_27; assign __delay_ready_23 = (__delay_ready_27 || !__delay_valid_27) && __delay_valid_23; @@ -740,15 +740,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin @@ -833,15 +833,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin @@ -926,15 +926,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin @@ -1019,15 +1019,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/examples/dataflow_sort/test_dataflow_sort.py b/examples/dataflow_sort/test_dataflow_sort.py index 548f9db1..26562371 100644 --- a/examples/dataflow_sort/test_dataflow_sort.py +++ b/examples/dataflow_sort/test_dataflow_sort.py @@ -8,22 +8,22 @@ reg CLK; reg RST; - reg [32-1:0] din0; - reg [32-1:0] din1; - reg [32-1:0] din2; - reg [32-1:0] din3; - reg [32-1:0] din4; - reg [32-1:0] din5; - reg [32-1:0] din6; - reg [32-1:0] din7; - wire [32-1:0] dout0; - wire [32-1:0] dout1; - wire [32-1:0] dout7; - wire [32-1:0] dout6; - wire [32-1:0] dout5; - wire [32-1:0] dout4; - wire [32-1:0] dout3; - wire [32-1:0] dout2; + reg signed [32-1:0] din0; + reg signed [32-1:0] din1; + reg signed [32-1:0] din2; + reg signed [32-1:0] din3; + reg signed [32-1:0] din4; + reg signed [32-1:0] din5; + reg signed [32-1:0] din6; + reg signed [32-1:0] din7; + wire signed [32-1:0] dout0; + wire signed [32-1:0] dout1; + wire signed [32-1:0] dout7; + wire signed [32-1:0] dout6; + wire signed [32-1:0] dout5; + wire signed [32-1:0] dout4; + wire signed [32-1:0] dout3; + wire signed [32-1:0] dout2; sort uut @@ -960,149 +960,149 @@ ( input CLK, input RST, - input [32-1:0] din0, - input [32-1:0] din1, - input [32-1:0] din2, - input [32-1:0] din3, - input [32-1:0] din4, - input [32-1:0] din5, - input [32-1:0] din6, - input [32-1:0] din7, - output [32-1:0] dout0, - output [32-1:0] dout1, - output [32-1:0] dout7, - output [32-1:0] dout6, - output [32-1:0] dout5, - output [32-1:0] dout4, - output [32-1:0] dout3, - output [32-1:0] dout2 + input signed [32-1:0] din0, + input signed [32-1:0] din1, + input signed [32-1:0] din2, + input signed [32-1:0] din3, + input signed [32-1:0] din4, + input signed [32-1:0] din5, + input signed [32-1:0] din6, + input signed [32-1:0] din7, + output signed [32-1:0] dout0, + output signed [32-1:0] dout1, + output signed [32-1:0] dout7, + output signed [32-1:0] dout6, + output signed [32-1:0] dout5, + output signed [32-1:0] dout4, + output signed [32-1:0] dout3, + output signed [32-1:0] dout2 ); reg [1-1:0] _lessthan_data_0; reg _lessthan_valid_0; wire _lessthan_ready_0; - reg [32-1:0] __delay_data_1; + reg signed [32-1:0] __delay_data_1; reg __delay_valid_1; wire __delay_ready_1; - reg [32-1:0] __delay_data_2; + reg signed [32-1:0] __delay_data_2; reg __delay_valid_2; wire __delay_ready_2; - reg [32-1:0] __delay_data_3; + reg signed [32-1:0] __delay_data_3; reg __delay_valid_3; wire __delay_ready_3; - reg [32-1:0] __delay_data_4; + reg signed [32-1:0] __delay_data_4; reg __delay_valid_4; wire __delay_ready_4; - reg [32-1:0] __delay_data_5; + reg signed [32-1:0] __delay_data_5; reg __delay_valid_5; wire __delay_ready_5; - reg [32-1:0] __delay_data_6; + reg signed [32-1:0] __delay_data_6; reg __delay_valid_6; wire __delay_ready_6; - reg [32-1:0] __delay_data_7; + reg signed [32-1:0] __delay_data_7; reg __delay_valid_7; wire __delay_ready_7; - reg [32-1:0] __delay_data_8; + reg signed [32-1:0] __delay_data_8; reg __delay_valid_8; wire __delay_ready_8; - reg [32-1:0] _cond_data_9; + reg signed [32-1:0] _cond_data_9; reg _cond_valid_9; wire _cond_ready_9; - reg [32-1:0] _cond_data_10; + reg signed [32-1:0] _cond_data_10; reg _cond_valid_10; wire _cond_ready_10; assign _lessthan_ready_0 = (_cond_ready_9 || !_cond_valid_9) && (_lessthan_valid_0 && __delay_valid_2 && __delay_valid_1) && ((_cond_ready_10 || !_cond_valid_10) && (_lessthan_valid_0 && __delay_valid_1 && __delay_valid_2)); assign __delay_ready_1 = (_cond_ready_9 || !_cond_valid_9) && (_lessthan_valid_0 && __delay_valid_2 && __delay_valid_1) && ((_cond_ready_10 || !_cond_valid_10) && (_lessthan_valid_0 && __delay_valid_1 && __delay_valid_2)); assign __delay_ready_2 = (_cond_ready_9 || !_cond_valid_9) && (_lessthan_valid_0 && __delay_valid_2 && __delay_valid_1) && ((_cond_ready_10 || !_cond_valid_10) && (_lessthan_valid_0 && __delay_valid_1 && __delay_valid_2)); - reg [32-1:0] __delay_data_11; + reg signed [32-1:0] __delay_data_11; reg __delay_valid_11; wire __delay_ready_11; assign __delay_ready_3 = (__delay_ready_11 || !__delay_valid_11) && __delay_valid_3; - reg [32-1:0] __delay_data_12; + reg signed [32-1:0] __delay_data_12; reg __delay_valid_12; wire __delay_ready_12; assign __delay_ready_4 = (__delay_ready_12 || !__delay_valid_12) && __delay_valid_4; - reg [32-1:0] __delay_data_13; + reg signed [32-1:0] __delay_data_13; reg __delay_valid_13; wire __delay_ready_13; assign __delay_ready_5 = (__delay_ready_13 || !__delay_valid_13) && __delay_valid_5; - reg [32-1:0] __delay_data_14; + reg signed [32-1:0] __delay_data_14; reg __delay_valid_14; wire __delay_ready_14; assign __delay_ready_6 = (__delay_ready_14 || !__delay_valid_14) && __delay_valid_6; - reg [32-1:0] __delay_data_15; + reg signed [32-1:0] __delay_data_15; reg __delay_valid_15; wire __delay_ready_15; assign __delay_ready_7 = (__delay_ready_15 || !__delay_valid_15) && __delay_valid_7; - reg [32-1:0] __delay_data_16; + reg signed [32-1:0] __delay_data_16; reg __delay_valid_16; wire __delay_ready_16; assign __delay_ready_8 = (__delay_ready_16 || !__delay_valid_16) && __delay_valid_8; reg [1-1:0] _lessthan_data_17; reg _lessthan_valid_17; wire _lessthan_ready_17; - reg [32-1:0] __delay_data_18; + reg signed [32-1:0] __delay_data_18; reg __delay_valid_18; wire __delay_ready_18; assign __delay_ready_11 = (_lessthan_ready_17 || !_lessthan_valid_17) && (_cond_valid_10 && __delay_valid_11) && ((__delay_ready_18 || !__delay_valid_18) && __delay_valid_11); - reg [32-1:0] __delay_data_19; + reg signed [32-1:0] __delay_data_19; reg __delay_valid_19; wire __delay_ready_19; assign _cond_ready_10 = (_lessthan_ready_17 || !_lessthan_valid_17) && (_cond_valid_10 && __delay_valid_11) && ((__delay_ready_19 || !__delay_valid_19) && _cond_valid_10); - reg [32-1:0] __delay_data_20; + reg signed [32-1:0] __delay_data_20; reg __delay_valid_20; wire __delay_ready_20; assign __delay_ready_12 = (__delay_ready_20 || !__delay_valid_20) && __delay_valid_12; - reg [32-1:0] __delay_data_21; + reg signed [32-1:0] __delay_data_21; reg __delay_valid_21; wire __delay_ready_21; assign __delay_ready_13 = (__delay_ready_21 || !__delay_valid_21) && __delay_valid_13; - reg [32-1:0] __delay_data_22; + reg signed [32-1:0] __delay_data_22; reg __delay_valid_22; wire __delay_ready_22; assign __delay_ready_14 = (__delay_ready_22 || !__delay_valid_22) && __delay_valid_14; - reg [32-1:0] __delay_data_23; + reg signed [32-1:0] __delay_data_23; reg __delay_valid_23; wire __delay_ready_23; assign __delay_ready_15 = (__delay_ready_23 || !__delay_valid_23) && __delay_valid_15; - reg [32-1:0] __delay_data_24; + reg signed [32-1:0] __delay_data_24; reg __delay_valid_24; wire __delay_ready_24; assign __delay_ready_16 = (__delay_ready_24 || !__delay_valid_24) && __delay_valid_16; - reg [32-1:0] __delay_data_25; + reg signed [32-1:0] __delay_data_25; reg __delay_valid_25; wire __delay_ready_25; assign _cond_ready_9 = (__delay_ready_25 || !__delay_valid_25) && _cond_valid_9; - reg [32-1:0] _cond_data_26; + reg signed [32-1:0] _cond_data_26; reg _cond_valid_26; wire _cond_ready_26; - reg [32-1:0] _cond_data_27; + reg signed [32-1:0] _cond_data_27; reg _cond_valid_27; wire _cond_ready_27; assign _lessthan_ready_17 = (_cond_ready_26 || !_cond_valid_26) && (_lessthan_valid_17 && __delay_valid_19 && __delay_valid_18) && ((_cond_ready_27 || !_cond_valid_27) && (_lessthan_valid_17 && __delay_valid_18 && __delay_valid_19)); assign __delay_ready_18 = (_cond_ready_26 || !_cond_valid_26) && (_lessthan_valid_17 && __delay_valid_19 && __delay_valid_18) && ((_cond_ready_27 || !_cond_valid_27) && (_lessthan_valid_17 && __delay_valid_18 && __delay_valid_19)); assign __delay_ready_19 = (_cond_ready_26 || !_cond_valid_26) && (_lessthan_valid_17 && __delay_valid_19 && __delay_valid_18) && ((_cond_ready_27 || !_cond_valid_27) && (_lessthan_valid_17 && __delay_valid_18 && __delay_valid_19)); - reg [32-1:0] __delay_data_28; + reg signed [32-1:0] __delay_data_28; reg __delay_valid_28; wire __delay_ready_28; assign __delay_ready_20 = (__delay_ready_28 || !__delay_valid_28) && __delay_valid_20; - reg [32-1:0] __delay_data_29; + reg signed [32-1:0] __delay_data_29; reg __delay_valid_29; wire __delay_ready_29; assign __delay_ready_21 = (__delay_ready_29 || !__delay_valid_29) && __delay_valid_21; - reg [32-1:0] __delay_data_30; + reg signed [32-1:0] __delay_data_30; reg __delay_valid_30; wire __delay_ready_30; assign __delay_ready_22 = (__delay_ready_30 || !__delay_valid_30) && __delay_valid_22; - reg [32-1:0] __delay_data_31; + reg signed [32-1:0] __delay_data_31; reg __delay_valid_31; wire __delay_ready_31; assign __delay_ready_23 = (__delay_ready_31 || !__delay_valid_31) && __delay_valid_23; - reg [32-1:0] __delay_data_32; + reg signed [32-1:0] __delay_data_32; reg __delay_valid_32; wire __delay_ready_32; assign __delay_ready_24 = (__delay_ready_32 || !__delay_valid_32) && __delay_valid_24; - reg [32-1:0] __delay_data_33; + reg signed [32-1:0] __delay_data_33; reg __delay_valid_33; wire __delay_ready_33; assign __delay_ready_25 = (__delay_ready_33 || !__delay_valid_33) && __delay_valid_25; @@ -1112,69 +1112,69 @@ reg [1-1:0] _lessthan_data_35; reg _lessthan_valid_35; wire _lessthan_ready_35; - reg [32-1:0] __delay_data_36; + reg signed [32-1:0] __delay_data_36; reg __delay_valid_36; wire __delay_ready_36; assign __delay_ready_28 = (_lessthan_ready_34 || !_lessthan_valid_34) && (_cond_valid_27 && __delay_valid_28) && ((__delay_ready_36 || !__delay_valid_36) && __delay_valid_28); - reg [32-1:0] __delay_data_37; + reg signed [32-1:0] __delay_data_37; reg __delay_valid_37; wire __delay_ready_37; assign _cond_ready_27 = (_lessthan_ready_34 || !_lessthan_valid_34) && (_cond_valid_27 && __delay_valid_28) && ((__delay_ready_37 || !__delay_valid_37) && _cond_valid_27); - reg [32-1:0] __delay_data_38; + reg signed [32-1:0] __delay_data_38; reg __delay_valid_38; wire __delay_ready_38; assign __delay_ready_29 = (__delay_ready_38 || !__delay_valid_38) && __delay_valid_29; - reg [32-1:0] __delay_data_39; + reg signed [32-1:0] __delay_data_39; reg __delay_valid_39; wire __delay_ready_39; assign __delay_ready_30 = (__delay_ready_39 || !__delay_valid_39) && __delay_valid_30; - reg [32-1:0] __delay_data_40; + reg signed [32-1:0] __delay_data_40; reg __delay_valid_40; wire __delay_ready_40; assign __delay_ready_31 = (__delay_ready_40 || !__delay_valid_40) && __delay_valid_31; - reg [32-1:0] __delay_data_41; + reg signed [32-1:0] __delay_data_41; reg __delay_valid_41; wire __delay_ready_41; assign __delay_ready_32 = (__delay_ready_41 || !__delay_valid_41) && __delay_valid_32; - reg [32-1:0] __delay_data_42; + reg signed [32-1:0] __delay_data_42; reg __delay_valid_42; wire __delay_ready_42; assign _cond_ready_26 = (_lessthan_ready_35 || !_lessthan_valid_35) && (__delay_valid_33 && _cond_valid_26) && ((__delay_ready_42 || !__delay_valid_42) && _cond_valid_26); - reg [32-1:0] __delay_data_43; + reg signed [32-1:0] __delay_data_43; reg __delay_valid_43; wire __delay_ready_43; assign __delay_ready_33 = (_lessthan_ready_35 || !_lessthan_valid_35) && (__delay_valid_33 && _cond_valid_26) && ((__delay_ready_43 || !__delay_valid_43) && __delay_valid_33); - reg [32-1:0] _cond_data_44; + reg signed [32-1:0] _cond_data_44; reg _cond_valid_44; wire _cond_ready_44; - reg [32-1:0] _cond_data_45; + reg signed [32-1:0] _cond_data_45; reg _cond_valid_45; wire _cond_ready_45; assign _lessthan_ready_34 = (_cond_ready_44 || !_cond_valid_44) && (_lessthan_valid_34 && __delay_valid_37 && __delay_valid_36) && ((_cond_ready_45 || !_cond_valid_45) && (_lessthan_valid_34 && __delay_valid_36 && __delay_valid_37)); assign __delay_ready_36 = (_cond_ready_44 || !_cond_valid_44) && (_lessthan_valid_34 && __delay_valid_37 && __delay_valid_36) && ((_cond_ready_45 || !_cond_valid_45) && (_lessthan_valid_34 && __delay_valid_36 && __delay_valid_37)); assign __delay_ready_37 = (_cond_ready_44 || !_cond_valid_44) && (_lessthan_valid_34 && __delay_valid_37 && __delay_valid_36) && ((_cond_ready_45 || !_cond_valid_45) && (_lessthan_valid_34 && __delay_valid_36 && __delay_valid_37)); - reg [32-1:0] _cond_data_46; + reg signed [32-1:0] _cond_data_46; reg _cond_valid_46; wire _cond_ready_46; - reg [32-1:0] _cond_data_47; + reg signed [32-1:0] _cond_data_47; reg _cond_valid_47; wire _cond_ready_47; assign _lessthan_ready_35 = (_cond_ready_46 || !_cond_valid_46) && (_lessthan_valid_35 && __delay_valid_43 && __delay_valid_42) && ((_cond_ready_47 || !_cond_valid_47) && (_lessthan_valid_35 && __delay_valid_42 && __delay_valid_43)); assign __delay_ready_42 = (_cond_ready_46 || !_cond_valid_46) && (_lessthan_valid_35 && __delay_valid_43 && __delay_valid_42) && ((_cond_ready_47 || !_cond_valid_47) && (_lessthan_valid_35 && __delay_valid_42 && __delay_valid_43)); assign __delay_ready_43 = (_cond_ready_46 || !_cond_valid_46) && (_lessthan_valid_35 && __delay_valid_43 && __delay_valid_42) && ((_cond_ready_47 || !_cond_valid_47) && (_lessthan_valid_35 && __delay_valid_42 && __delay_valid_43)); - reg [32-1:0] __delay_data_48; + reg signed [32-1:0] __delay_data_48; reg __delay_valid_48; wire __delay_ready_48; assign __delay_ready_38 = (__delay_ready_48 || !__delay_valid_48) && __delay_valid_38; - reg [32-1:0] __delay_data_49; + reg signed [32-1:0] __delay_data_49; reg __delay_valid_49; wire __delay_ready_49; assign __delay_ready_39 = (__delay_ready_49 || !__delay_valid_49) && __delay_valid_39; - reg [32-1:0] __delay_data_50; + reg signed [32-1:0] __delay_data_50; reg __delay_valid_50; wire __delay_ready_50; assign __delay_ready_40 = (__delay_ready_50 || !__delay_valid_50) && __delay_valid_40; - reg [32-1:0] __delay_data_51; + reg signed [32-1:0] __delay_data_51; reg __delay_valid_51; wire __delay_ready_51; assign __delay_ready_41 = (__delay_ready_51 || !__delay_valid_51) && __delay_valid_41; @@ -1184,69 +1184,69 @@ reg [1-1:0] _lessthan_data_53; reg _lessthan_valid_53; wire _lessthan_ready_53; - reg [32-1:0] __delay_data_54; + reg signed [32-1:0] __delay_data_54; reg __delay_valid_54; wire __delay_ready_54; assign __delay_ready_48 = (_lessthan_ready_52 || !_lessthan_valid_52) && (_cond_valid_45 && __delay_valid_48) && ((__delay_ready_54 || !__delay_valid_54) && __delay_valid_48); - reg [32-1:0] __delay_data_55; + reg signed [32-1:0] __delay_data_55; reg __delay_valid_55; wire __delay_ready_55; assign _cond_ready_45 = (_lessthan_ready_52 || !_lessthan_valid_52) && (_cond_valid_45 && __delay_valid_48) && ((__delay_ready_55 || !__delay_valid_55) && _cond_valid_45); - reg [32-1:0] __delay_data_56; + reg signed [32-1:0] __delay_data_56; reg __delay_valid_56; wire __delay_ready_56; assign __delay_ready_49 = (__delay_ready_56 || !__delay_valid_56) && __delay_valid_49; - reg [32-1:0] __delay_data_57; + reg signed [32-1:0] __delay_data_57; reg __delay_valid_57; wire __delay_ready_57; assign __delay_ready_50 = (__delay_ready_57 || !__delay_valid_57) && __delay_valid_50; - reg [32-1:0] __delay_data_58; + reg signed [32-1:0] __delay_data_58; reg __delay_valid_58; wire __delay_ready_58; assign __delay_ready_51 = (__delay_ready_58 || !__delay_valid_58) && __delay_valid_51; - reg [32-1:0] __delay_data_59; + reg signed [32-1:0] __delay_data_59; reg __delay_valid_59; wire __delay_ready_59; assign _cond_ready_44 = (_lessthan_ready_53 || !_lessthan_valid_53) && (_cond_valid_47 && _cond_valid_44) && ((__delay_ready_59 || !__delay_valid_59) && _cond_valid_44); - reg [32-1:0] __delay_data_60; + reg signed [32-1:0] __delay_data_60; reg __delay_valid_60; wire __delay_ready_60; assign _cond_ready_47 = (_lessthan_ready_53 || !_lessthan_valid_53) && (_cond_valid_47 && _cond_valid_44) && ((__delay_ready_60 || !__delay_valid_60) && _cond_valid_47); - reg [32-1:0] __delay_data_61; + reg signed [32-1:0] __delay_data_61; reg __delay_valid_61; wire __delay_ready_61; assign _cond_ready_46 = (__delay_ready_61 || !__delay_valid_61) && _cond_valid_46; - reg [32-1:0] _cond_data_62; + reg signed [32-1:0] _cond_data_62; reg _cond_valid_62; wire _cond_ready_62; - reg [32-1:0] _cond_data_63; + reg signed [32-1:0] _cond_data_63; reg _cond_valid_63; wire _cond_ready_63; assign _lessthan_ready_52 = (_cond_ready_62 || !_cond_valid_62) && (_lessthan_valid_52 && __delay_valid_55 && __delay_valid_54) && ((_cond_ready_63 || !_cond_valid_63) && (_lessthan_valid_52 && __delay_valid_54 && __delay_valid_55)); assign __delay_ready_54 = (_cond_ready_62 || !_cond_valid_62) && (_lessthan_valid_52 && __delay_valid_55 && __delay_valid_54) && ((_cond_ready_63 || !_cond_valid_63) && (_lessthan_valid_52 && __delay_valid_54 && __delay_valid_55)); assign __delay_ready_55 = (_cond_ready_62 || !_cond_valid_62) && (_lessthan_valid_52 && __delay_valid_55 && __delay_valid_54) && ((_cond_ready_63 || !_cond_valid_63) && (_lessthan_valid_52 && __delay_valid_54 && __delay_valid_55)); - reg [32-1:0] _cond_data_64; + reg signed [32-1:0] _cond_data_64; reg _cond_valid_64; wire _cond_ready_64; - reg [32-1:0] _cond_data_65; + reg signed [32-1:0] _cond_data_65; reg _cond_valid_65; wire _cond_ready_65; assign _lessthan_ready_53 = (_cond_ready_64 || !_cond_valid_64) && (_lessthan_valid_53 && __delay_valid_60 && __delay_valid_59) && ((_cond_ready_65 || !_cond_valid_65) && (_lessthan_valid_53 && __delay_valid_59 && __delay_valid_60)); assign __delay_ready_59 = (_cond_ready_64 || !_cond_valid_64) && (_lessthan_valid_53 && __delay_valid_60 && __delay_valid_59) && ((_cond_ready_65 || !_cond_valid_65) && (_lessthan_valid_53 && __delay_valid_59 && __delay_valid_60)); assign __delay_ready_60 = (_cond_ready_64 || !_cond_valid_64) && (_lessthan_valid_53 && __delay_valid_60 && __delay_valid_59) && ((_cond_ready_65 || !_cond_valid_65) && (_lessthan_valid_53 && __delay_valid_59 && __delay_valid_60)); - reg [32-1:0] __delay_data_66; + reg signed [32-1:0] __delay_data_66; reg __delay_valid_66; wire __delay_ready_66; assign __delay_ready_56 = (__delay_ready_66 || !__delay_valid_66) && __delay_valid_56; - reg [32-1:0] __delay_data_67; + reg signed [32-1:0] __delay_data_67; reg __delay_valid_67; wire __delay_ready_67; assign __delay_ready_57 = (__delay_ready_67 || !__delay_valid_67) && __delay_valid_57; - reg [32-1:0] __delay_data_68; + reg signed [32-1:0] __delay_data_68; reg __delay_valid_68; wire __delay_ready_68; assign __delay_ready_58 = (__delay_ready_68 || !__delay_valid_68) && __delay_valid_58; - reg [32-1:0] __delay_data_69; + reg signed [32-1:0] __delay_data_69; reg __delay_valid_69; wire __delay_ready_69; assign __delay_ready_61 = (__delay_ready_69 || !__delay_valid_69) && __delay_valid_61; @@ -1259,70 +1259,70 @@ reg [1-1:0] _lessthan_data_72; reg _lessthan_valid_72; wire _lessthan_ready_72; - reg [32-1:0] __delay_data_73; + reg signed [32-1:0] __delay_data_73; reg __delay_valid_73; wire __delay_ready_73; assign __delay_ready_66 = (_lessthan_ready_70 || !_lessthan_valid_70) && (_cond_valid_63 && __delay_valid_66) && ((__delay_ready_73 || !__delay_valid_73) && __delay_valid_66); - reg [32-1:0] __delay_data_74; + reg signed [32-1:0] __delay_data_74; reg __delay_valid_74; wire __delay_ready_74; assign _cond_ready_63 = (_lessthan_ready_70 || !_lessthan_valid_70) && (_cond_valid_63 && __delay_valid_66) && ((__delay_ready_74 || !__delay_valid_74) && _cond_valid_63); - reg [32-1:0] __delay_data_75; + reg signed [32-1:0] __delay_data_75; reg __delay_valid_75; wire __delay_ready_75; assign __delay_ready_67 = (__delay_ready_75 || !__delay_valid_75) && __delay_valid_67; - reg [32-1:0] __delay_data_76; + reg signed [32-1:0] __delay_data_76; reg __delay_valid_76; wire __delay_ready_76; assign __delay_ready_68 = (__delay_ready_76 || !__delay_valid_76) && __delay_valid_68; - reg [32-1:0] __delay_data_77; + reg signed [32-1:0] __delay_data_77; reg __delay_valid_77; wire __delay_ready_77; assign _cond_ready_62 = (_lessthan_ready_71 || !_lessthan_valid_71) && (_cond_valid_65 && _cond_valid_62) && ((__delay_ready_77 || !__delay_valid_77) && _cond_valid_62); - reg [32-1:0] __delay_data_78; + reg signed [32-1:0] __delay_data_78; reg __delay_valid_78; wire __delay_ready_78; assign _cond_ready_65 = (_lessthan_ready_71 || !_lessthan_valid_71) && (_cond_valid_65 && _cond_valid_62) && ((__delay_ready_78 || !__delay_valid_78) && _cond_valid_65); - reg [32-1:0] __delay_data_79; + reg signed [32-1:0] __delay_data_79; reg __delay_valid_79; wire __delay_ready_79; assign _cond_ready_64 = (_lessthan_ready_72 || !_lessthan_valid_72) && (__delay_valid_69 && _cond_valid_64) && ((__delay_ready_79 || !__delay_valid_79) && _cond_valid_64); - reg [32-1:0] __delay_data_80; + reg signed [32-1:0] __delay_data_80; reg __delay_valid_80; wire __delay_ready_80; assign __delay_ready_69 = (_lessthan_ready_72 || !_lessthan_valid_72) && (__delay_valid_69 && _cond_valid_64) && ((__delay_ready_80 || !__delay_valid_80) && __delay_valid_69); - reg [32-1:0] _cond_data_81; + reg signed [32-1:0] _cond_data_81; reg _cond_valid_81; wire _cond_ready_81; - reg [32-1:0] _cond_data_82; + reg signed [32-1:0] _cond_data_82; reg _cond_valid_82; wire _cond_ready_82; assign _lessthan_ready_70 = (_cond_ready_81 || !_cond_valid_81) && (_lessthan_valid_70 && __delay_valid_74 && __delay_valid_73) && ((_cond_ready_82 || !_cond_valid_82) && (_lessthan_valid_70 && __delay_valid_73 && __delay_valid_74)); assign __delay_ready_73 = (_cond_ready_81 || !_cond_valid_81) && (_lessthan_valid_70 && __delay_valid_74 && __delay_valid_73) && ((_cond_ready_82 || !_cond_valid_82) && (_lessthan_valid_70 && __delay_valid_73 && __delay_valid_74)); assign __delay_ready_74 = (_cond_ready_81 || !_cond_valid_81) && (_lessthan_valid_70 && __delay_valid_74 && __delay_valid_73) && ((_cond_ready_82 || !_cond_valid_82) && (_lessthan_valid_70 && __delay_valid_73 && __delay_valid_74)); - reg [32-1:0] _cond_data_83; + reg signed [32-1:0] _cond_data_83; reg _cond_valid_83; wire _cond_ready_83; - reg [32-1:0] _cond_data_84; + reg signed [32-1:0] _cond_data_84; reg _cond_valid_84; wire _cond_ready_84; assign _lessthan_ready_71 = (_cond_ready_83 || !_cond_valid_83) && (_lessthan_valid_71 && __delay_valid_78 && __delay_valid_77) && ((_cond_ready_84 || !_cond_valid_84) && (_lessthan_valid_71 && __delay_valid_77 && __delay_valid_78)); assign __delay_ready_77 = (_cond_ready_83 || !_cond_valid_83) && (_lessthan_valid_71 && __delay_valid_78 && __delay_valid_77) && ((_cond_ready_84 || !_cond_valid_84) && (_lessthan_valid_71 && __delay_valid_77 && __delay_valid_78)); assign __delay_ready_78 = (_cond_ready_83 || !_cond_valid_83) && (_lessthan_valid_71 && __delay_valid_78 && __delay_valid_77) && ((_cond_ready_84 || !_cond_valid_84) && (_lessthan_valid_71 && __delay_valid_77 && __delay_valid_78)); - reg [32-1:0] _cond_data_85; + reg signed [32-1:0] _cond_data_85; reg _cond_valid_85; wire _cond_ready_85; - reg [32-1:0] _cond_data_86; + reg signed [32-1:0] _cond_data_86; reg _cond_valid_86; wire _cond_ready_86; assign _lessthan_ready_72 = (_cond_ready_85 || !_cond_valid_85) && (_lessthan_valid_72 && __delay_valid_80 && __delay_valid_79) && ((_cond_ready_86 || !_cond_valid_86) && (_lessthan_valid_72 && __delay_valid_79 && __delay_valid_80)); assign __delay_ready_79 = (_cond_ready_85 || !_cond_valid_85) && (_lessthan_valid_72 && __delay_valid_80 && __delay_valid_79) && ((_cond_ready_86 || !_cond_valid_86) && (_lessthan_valid_72 && __delay_valid_79 && __delay_valid_80)); assign __delay_ready_80 = (_cond_ready_85 || !_cond_valid_85) && (_lessthan_valid_72 && __delay_valid_80 && __delay_valid_79) && ((_cond_ready_86 || !_cond_valid_86) && (_lessthan_valid_72 && __delay_valid_79 && __delay_valid_80)); - reg [32-1:0] __delay_data_87; + reg signed [32-1:0] __delay_data_87; reg __delay_valid_87; wire __delay_ready_87; assign __delay_ready_75 = (__delay_ready_87 || !__delay_valid_87) && __delay_valid_75; - reg [32-1:0] __delay_data_88; + reg signed [32-1:0] __delay_data_88; reg __delay_valid_88; wire __delay_ready_88; assign __delay_ready_76 = (__delay_ready_88 || !__delay_valid_88) && __delay_valid_76; @@ -1335,70 +1335,70 @@ reg [1-1:0] _lessthan_data_91; reg _lessthan_valid_91; wire _lessthan_ready_91; - reg [32-1:0] __delay_data_92; + reg signed [32-1:0] __delay_data_92; reg __delay_valid_92; wire __delay_ready_92; assign __delay_ready_87 = (_lessthan_ready_89 || !_lessthan_valid_89) && (_cond_valid_82 && __delay_valid_87) && ((__delay_ready_92 || !__delay_valid_92) && __delay_valid_87); - reg [32-1:0] __delay_data_93; + reg signed [32-1:0] __delay_data_93; reg __delay_valid_93; wire __delay_ready_93; assign _cond_ready_82 = (_lessthan_ready_89 || !_lessthan_valid_89) && (_cond_valid_82 && __delay_valid_87) && ((__delay_ready_93 || !__delay_valid_93) && _cond_valid_82); - reg [32-1:0] __delay_data_94; + reg signed [32-1:0] __delay_data_94; reg __delay_valid_94; wire __delay_ready_94; assign __delay_ready_88 = (__delay_ready_94 || !__delay_valid_94) && __delay_valid_88; - reg [32-1:0] __delay_data_95; + reg signed [32-1:0] __delay_data_95; reg __delay_valid_95; wire __delay_ready_95; assign _cond_ready_81 = (_lessthan_ready_90 || !_lessthan_valid_90) && (_cond_valid_84 && _cond_valid_81) && ((__delay_ready_95 || !__delay_valid_95) && _cond_valid_81); - reg [32-1:0] __delay_data_96; + reg signed [32-1:0] __delay_data_96; reg __delay_valid_96; wire __delay_ready_96; assign _cond_ready_84 = (_lessthan_ready_90 || !_lessthan_valid_90) && (_cond_valid_84 && _cond_valid_81) && ((__delay_ready_96 || !__delay_valid_96) && _cond_valid_84); - reg [32-1:0] __delay_data_97; + reg signed [32-1:0] __delay_data_97; reg __delay_valid_97; wire __delay_ready_97; assign _cond_ready_83 = (_lessthan_ready_91 || !_lessthan_valid_91) && (_cond_valid_86 && _cond_valid_83) && ((__delay_ready_97 || !__delay_valid_97) && _cond_valid_83); - reg [32-1:0] __delay_data_98; + reg signed [32-1:0] __delay_data_98; reg __delay_valid_98; wire __delay_ready_98; assign _cond_ready_86 = (_lessthan_ready_91 || !_lessthan_valid_91) && (_cond_valid_86 && _cond_valid_83) && ((__delay_ready_98 || !__delay_valid_98) && _cond_valid_86); - reg [32-1:0] __delay_data_99; + reg signed [32-1:0] __delay_data_99; reg __delay_valid_99; wire __delay_ready_99; assign _cond_ready_85 = (__delay_ready_99 || !__delay_valid_99) && _cond_valid_85; - reg [32-1:0] _cond_data_100; + reg signed [32-1:0] _cond_data_100; reg _cond_valid_100; wire _cond_ready_100; - reg [32-1:0] _cond_data_101; + reg signed [32-1:0] _cond_data_101; reg _cond_valid_101; wire _cond_ready_101; assign _lessthan_ready_89 = (_cond_ready_100 || !_cond_valid_100) && (_lessthan_valid_89 && __delay_valid_93 && __delay_valid_92) && ((_cond_ready_101 || !_cond_valid_101) && (_lessthan_valid_89 && __delay_valid_92 && __delay_valid_93)); assign __delay_ready_92 = (_cond_ready_100 || !_cond_valid_100) && (_lessthan_valid_89 && __delay_valid_93 && __delay_valid_92) && ((_cond_ready_101 || !_cond_valid_101) && (_lessthan_valid_89 && __delay_valid_92 && __delay_valid_93)); assign __delay_ready_93 = (_cond_ready_100 || !_cond_valid_100) && (_lessthan_valid_89 && __delay_valid_93 && __delay_valid_92) && ((_cond_ready_101 || !_cond_valid_101) && (_lessthan_valid_89 && __delay_valid_92 && __delay_valid_93)); - reg [32-1:0] _cond_data_102; + reg signed [32-1:0] _cond_data_102; reg _cond_valid_102; wire _cond_ready_102; - reg [32-1:0] _cond_data_103; + reg signed [32-1:0] _cond_data_103; reg _cond_valid_103; wire _cond_ready_103; assign _lessthan_ready_90 = (_cond_ready_102 || !_cond_valid_102) && (_lessthan_valid_90 && __delay_valid_96 && __delay_valid_95) && ((_cond_ready_103 || !_cond_valid_103) && (_lessthan_valid_90 && __delay_valid_95 && __delay_valid_96)); assign __delay_ready_95 = (_cond_ready_102 || !_cond_valid_102) && (_lessthan_valid_90 && __delay_valid_96 && __delay_valid_95) && ((_cond_ready_103 || !_cond_valid_103) && (_lessthan_valid_90 && __delay_valid_95 && __delay_valid_96)); assign __delay_ready_96 = (_cond_ready_102 || !_cond_valid_102) && (_lessthan_valid_90 && __delay_valid_96 && __delay_valid_95) && ((_cond_ready_103 || !_cond_valid_103) && (_lessthan_valid_90 && __delay_valid_95 && __delay_valid_96)); - reg [32-1:0] _cond_data_104; + reg signed [32-1:0] _cond_data_104; reg _cond_valid_104; wire _cond_ready_104; - reg [32-1:0] _cond_data_105; + reg signed [32-1:0] _cond_data_105; reg _cond_valid_105; wire _cond_ready_105; assign _lessthan_ready_91 = (_cond_ready_104 || !_cond_valid_104) && (_lessthan_valid_91 && __delay_valid_98 && __delay_valid_97) && ((_cond_ready_105 || !_cond_valid_105) && (_lessthan_valid_91 && __delay_valid_97 && __delay_valid_98)); assign __delay_ready_97 = (_cond_ready_104 || !_cond_valid_104) && (_lessthan_valid_91 && __delay_valid_98 && __delay_valid_97) && ((_cond_ready_105 || !_cond_valid_105) && (_lessthan_valid_91 && __delay_valid_97 && __delay_valid_98)); assign __delay_ready_98 = (_cond_ready_104 || !_cond_valid_104) && (_lessthan_valid_91 && __delay_valid_98 && __delay_valid_97) && ((_cond_ready_105 || !_cond_valid_105) && (_lessthan_valid_91 && __delay_valid_97 && __delay_valid_98)); - reg [32-1:0] __delay_data_106; + reg signed [32-1:0] __delay_data_106; reg __delay_valid_106; wire __delay_ready_106; assign __delay_ready_94 = (__delay_ready_106 || !__delay_valid_106) && __delay_valid_94; - reg [32-1:0] __delay_data_107; + reg signed [32-1:0] __delay_data_107; reg __delay_valid_107; wire __delay_ready_107; assign __delay_ready_99 = (__delay_ready_107 || !__delay_valid_107) && __delay_valid_99; @@ -1414,69 +1414,69 @@ reg [1-1:0] _lessthan_data_111; reg _lessthan_valid_111; wire _lessthan_ready_111; - reg [32-1:0] __delay_data_112; + reg signed [32-1:0] __delay_data_112; reg __delay_valid_112; wire __delay_ready_112; assign __delay_ready_106 = (_lessthan_ready_108 || !_lessthan_valid_108) && (_cond_valid_101 && __delay_valid_106) && ((__delay_ready_112 || !__delay_valid_112) && __delay_valid_106); - reg [32-1:0] __delay_data_113; + reg signed [32-1:0] __delay_data_113; reg __delay_valid_113; wire __delay_ready_113; assign _cond_ready_101 = (_lessthan_ready_108 || !_lessthan_valid_108) && (_cond_valid_101 && __delay_valid_106) && ((__delay_ready_113 || !__delay_valid_113) && _cond_valid_101); - reg [32-1:0] __delay_data_114; + reg signed [32-1:0] __delay_data_114; reg __delay_valid_114; wire __delay_ready_114; assign _cond_ready_100 = (_lessthan_ready_109 || !_lessthan_valid_109) && (_cond_valid_103 && _cond_valid_100) && ((__delay_ready_114 || !__delay_valid_114) && _cond_valid_100); - reg [32-1:0] __delay_data_115; + reg signed [32-1:0] __delay_data_115; reg __delay_valid_115; wire __delay_ready_115; assign _cond_ready_103 = (_lessthan_ready_109 || !_lessthan_valid_109) && (_cond_valid_103 && _cond_valid_100) && ((__delay_ready_115 || !__delay_valid_115) && _cond_valid_103); - reg [32-1:0] __delay_data_116; + reg signed [32-1:0] __delay_data_116; reg __delay_valid_116; wire __delay_ready_116; assign _cond_ready_102 = (_lessthan_ready_110 || !_lessthan_valid_110) && (_cond_valid_105 && _cond_valid_102) && ((__delay_ready_116 || !__delay_valid_116) && _cond_valid_102); - reg [32-1:0] __delay_data_117; + reg signed [32-1:0] __delay_data_117; reg __delay_valid_117; wire __delay_ready_117; assign _cond_ready_105 = (_lessthan_ready_110 || !_lessthan_valid_110) && (_cond_valid_105 && _cond_valid_102) && ((__delay_ready_117 || !__delay_valid_117) && _cond_valid_105); - reg [32-1:0] __delay_data_118; + reg signed [32-1:0] __delay_data_118; reg __delay_valid_118; wire __delay_ready_118; assign _cond_ready_104 = (_lessthan_ready_111 || !_lessthan_valid_111) && (__delay_valid_107 && _cond_valid_104) && ((__delay_ready_118 || !__delay_valid_118) && _cond_valid_104); - reg [32-1:0] __delay_data_119; + reg signed [32-1:0] __delay_data_119; reg __delay_valid_119; wire __delay_ready_119; assign __delay_ready_107 = (_lessthan_ready_111 || !_lessthan_valid_111) && (__delay_valid_107 && _cond_valid_104) && ((__delay_ready_119 || !__delay_valid_119) && __delay_valid_107); - reg [32-1:0] _cond_data_120; + reg signed [32-1:0] _cond_data_120; reg _cond_valid_120; wire _cond_ready_120; - reg [32-1:0] _cond_data_121; + reg signed [32-1:0] _cond_data_121; reg _cond_valid_121; wire _cond_ready_121; assign _lessthan_ready_108 = (_cond_ready_120 || !_cond_valid_120) && (_lessthan_valid_108 && __delay_valid_113 && __delay_valid_112) && ((_cond_ready_121 || !_cond_valid_121) && (_lessthan_valid_108 && __delay_valid_112 && __delay_valid_113)); assign __delay_ready_112 = (_cond_ready_120 || !_cond_valid_120) && (_lessthan_valid_108 && __delay_valid_113 && __delay_valid_112) && ((_cond_ready_121 || !_cond_valid_121) && (_lessthan_valid_108 && __delay_valid_112 && __delay_valid_113)); assign __delay_ready_113 = (_cond_ready_120 || !_cond_valid_120) && (_lessthan_valid_108 && __delay_valid_113 && __delay_valid_112) && ((_cond_ready_121 || !_cond_valid_121) && (_lessthan_valid_108 && __delay_valid_112 && __delay_valid_113)); - reg [32-1:0] _cond_data_122; + reg signed [32-1:0] _cond_data_122; reg _cond_valid_122; wire _cond_ready_122; - reg [32-1:0] _cond_data_123; + reg signed [32-1:0] _cond_data_123; reg _cond_valid_123; wire _cond_ready_123; assign _lessthan_ready_109 = (_cond_ready_122 || !_cond_valid_122) && (_lessthan_valid_109 && __delay_valid_115 && __delay_valid_114) && ((_cond_ready_123 || !_cond_valid_123) && (_lessthan_valid_109 && __delay_valid_114 && __delay_valid_115)); assign __delay_ready_114 = (_cond_ready_122 || !_cond_valid_122) && (_lessthan_valid_109 && __delay_valid_115 && __delay_valid_114) && ((_cond_ready_123 || !_cond_valid_123) && (_lessthan_valid_109 && __delay_valid_114 && __delay_valid_115)); assign __delay_ready_115 = (_cond_ready_122 || !_cond_valid_122) && (_lessthan_valid_109 && __delay_valid_115 && __delay_valid_114) && ((_cond_ready_123 || !_cond_valid_123) && (_lessthan_valid_109 && __delay_valid_114 && __delay_valid_115)); - reg [32-1:0] _cond_data_124; + reg signed [32-1:0] _cond_data_124; reg _cond_valid_124; wire _cond_ready_124; - reg [32-1:0] _cond_data_125; + reg signed [32-1:0] _cond_data_125; reg _cond_valid_125; wire _cond_ready_125; assign _lessthan_ready_110 = (_cond_ready_124 || !_cond_valid_124) && (_lessthan_valid_110 && __delay_valid_117 && __delay_valid_116) && ((_cond_ready_125 || !_cond_valid_125) && (_lessthan_valid_110 && __delay_valid_116 && __delay_valid_117)); assign __delay_ready_116 = (_cond_ready_124 || !_cond_valid_124) && (_lessthan_valid_110 && __delay_valid_117 && __delay_valid_116) && ((_cond_ready_125 || !_cond_valid_125) && (_lessthan_valid_110 && __delay_valid_116 && __delay_valid_117)); assign __delay_ready_117 = (_cond_ready_124 || !_cond_valid_124) && (_lessthan_valid_110 && __delay_valid_117 && __delay_valid_116) && ((_cond_ready_125 || !_cond_valid_125) && (_lessthan_valid_110 && __delay_valid_116 && __delay_valid_117)); - reg [32-1:0] _cond_data_126; + reg signed [32-1:0] _cond_data_126; reg _cond_valid_126; wire _cond_ready_126; - reg [32-1:0] _cond_data_127; + reg signed [32-1:0] _cond_data_127; reg _cond_valid_127; wire _cond_ready_127; assign _lessthan_ready_111 = (_cond_ready_126 || !_cond_valid_126) && (_lessthan_valid_111 && __delay_valid_119 && __delay_valid_118) && ((_cond_ready_127 || !_cond_valid_127) && (_lessthan_valid_111 && __delay_valid_118 && __delay_valid_119)); @@ -1491,70 +1491,70 @@ reg [1-1:0] _lessthan_data_130; reg _lessthan_valid_130; wire _lessthan_ready_130; - reg [32-1:0] __delay_data_131; + reg signed [32-1:0] __delay_data_131; reg __delay_valid_131; wire __delay_ready_131; assign _cond_ready_120 = (_lessthan_ready_128 || !_lessthan_valid_128) && (_cond_valid_123 && _cond_valid_120) && ((__delay_ready_131 || !__delay_valid_131) && _cond_valid_120); - reg [32-1:0] __delay_data_132; + reg signed [32-1:0] __delay_data_132; reg __delay_valid_132; wire __delay_ready_132; assign _cond_ready_123 = (_lessthan_ready_128 || !_lessthan_valid_128) && (_cond_valid_123 && _cond_valid_120) && ((__delay_ready_132 || !__delay_valid_132) && _cond_valid_123); - reg [32-1:0] __delay_data_133; + reg signed [32-1:0] __delay_data_133; reg __delay_valid_133; wire __delay_ready_133; assign _cond_ready_122 = (_lessthan_ready_129 || !_lessthan_valid_129) && (_cond_valid_125 && _cond_valid_122) && ((__delay_ready_133 || !__delay_valid_133) && _cond_valid_122); - reg [32-1:0] __delay_data_134; + reg signed [32-1:0] __delay_data_134; reg __delay_valid_134; wire __delay_ready_134; assign _cond_ready_125 = (_lessthan_ready_129 || !_lessthan_valid_129) && (_cond_valid_125 && _cond_valid_122) && ((__delay_ready_134 || !__delay_valid_134) && _cond_valid_125); - reg [32-1:0] __delay_data_135; + reg signed [32-1:0] __delay_data_135; reg __delay_valid_135; wire __delay_ready_135; assign _cond_ready_124 = (_lessthan_ready_130 || !_lessthan_valid_130) && (_cond_valid_127 && _cond_valid_124) && ((__delay_ready_135 || !__delay_valid_135) && _cond_valid_124); - reg [32-1:0] __delay_data_136; + reg signed [32-1:0] __delay_data_136; reg __delay_valid_136; wire __delay_ready_136; assign _cond_ready_127 = (_lessthan_ready_130 || !_lessthan_valid_130) && (_cond_valid_127 && _cond_valid_124) && ((__delay_ready_136 || !__delay_valid_136) && _cond_valid_127); - reg [32-1:0] __delay_data_137; + reg signed [32-1:0] __delay_data_137; reg __delay_valid_137; wire __delay_ready_137; assign _cond_ready_126 = (__delay_ready_137 || !__delay_valid_137) && _cond_valid_126; - reg [32-1:0] __delay_data_138; + reg signed [32-1:0] __delay_data_138; reg __delay_valid_138; wire __delay_ready_138; assign _cond_ready_121 = (__delay_ready_138 || !__delay_valid_138) && _cond_valid_121; - reg [32-1:0] _cond_data_139; + reg signed [32-1:0] _cond_data_139; reg _cond_valid_139; wire _cond_ready_139; - reg [32-1:0] _cond_data_140; + reg signed [32-1:0] _cond_data_140; reg _cond_valid_140; wire _cond_ready_140; assign _lessthan_ready_128 = (_cond_ready_139 || !_cond_valid_139) && (_lessthan_valid_128 && __delay_valid_132 && __delay_valid_131) && ((_cond_ready_140 || !_cond_valid_140) && (_lessthan_valid_128 && __delay_valid_131 && __delay_valid_132)); assign __delay_ready_131 = (_cond_ready_139 || !_cond_valid_139) && (_lessthan_valid_128 && __delay_valid_132 && __delay_valid_131) && ((_cond_ready_140 || !_cond_valid_140) && (_lessthan_valid_128 && __delay_valid_131 && __delay_valid_132)); assign __delay_ready_132 = (_cond_ready_139 || !_cond_valid_139) && (_lessthan_valid_128 && __delay_valid_132 && __delay_valid_131) && ((_cond_ready_140 || !_cond_valid_140) && (_lessthan_valid_128 && __delay_valid_131 && __delay_valid_132)); - reg [32-1:0] _cond_data_141; + reg signed [32-1:0] _cond_data_141; reg _cond_valid_141; wire _cond_ready_141; - reg [32-1:0] _cond_data_142; + reg signed [32-1:0] _cond_data_142; reg _cond_valid_142; wire _cond_ready_142; assign _lessthan_ready_129 = (_cond_ready_141 || !_cond_valid_141) && (_lessthan_valid_129 && __delay_valid_134 && __delay_valid_133) && ((_cond_ready_142 || !_cond_valid_142) && (_lessthan_valid_129 && __delay_valid_133 && __delay_valid_134)); assign __delay_ready_133 = (_cond_ready_141 || !_cond_valid_141) && (_lessthan_valid_129 && __delay_valid_134 && __delay_valid_133) && ((_cond_ready_142 || !_cond_valid_142) && (_lessthan_valid_129 && __delay_valid_133 && __delay_valid_134)); assign __delay_ready_134 = (_cond_ready_141 || !_cond_valid_141) && (_lessthan_valid_129 && __delay_valid_134 && __delay_valid_133) && ((_cond_ready_142 || !_cond_valid_142) && (_lessthan_valid_129 && __delay_valid_133 && __delay_valid_134)); - reg [32-1:0] _cond_data_143; + reg signed [32-1:0] _cond_data_143; reg _cond_valid_143; wire _cond_ready_143; - reg [32-1:0] _cond_data_144; + reg signed [32-1:0] _cond_data_144; reg _cond_valid_144; wire _cond_ready_144; assign _lessthan_ready_130 = (_cond_ready_143 || !_cond_valid_143) && (_lessthan_valid_130 && __delay_valid_136 && __delay_valid_135) && ((_cond_ready_144 || !_cond_valid_144) && (_lessthan_valid_130 && __delay_valid_135 && __delay_valid_136)); assign __delay_ready_135 = (_cond_ready_143 || !_cond_valid_143) && (_lessthan_valid_130 && __delay_valid_136 && __delay_valid_135) && ((_cond_ready_144 || !_cond_valid_144) && (_lessthan_valid_130 && __delay_valid_135 && __delay_valid_136)); assign __delay_ready_136 = (_cond_ready_143 || !_cond_valid_143) && (_lessthan_valid_130 && __delay_valid_136 && __delay_valid_135) && ((_cond_ready_144 || !_cond_valid_144) && (_lessthan_valid_130 && __delay_valid_135 && __delay_valid_136)); - reg [32-1:0] __delay_data_145; + reg signed [32-1:0] __delay_data_145; reg __delay_valid_145; wire __delay_ready_145; assign __delay_ready_137 = (__delay_ready_145 || !__delay_valid_145) && __delay_valid_137; - reg [32-1:0] __delay_data_146; + reg signed [32-1:0] __delay_data_146; reg __delay_valid_146; wire __delay_ready_146; assign __delay_ready_138 = (__delay_ready_146 || !__delay_valid_146) && __delay_valid_138; @@ -1567,70 +1567,70 @@ reg [1-1:0] _lessthan_data_149; reg _lessthan_valid_149; wire _lessthan_ready_149; - reg [32-1:0] __delay_data_150; + reg signed [32-1:0] __delay_data_150; reg __delay_valid_150; wire __delay_ready_150; assign _cond_ready_139 = (_lessthan_ready_147 || !_lessthan_valid_147) && (_cond_valid_142 && _cond_valid_139) && ((__delay_ready_150 || !__delay_valid_150) && _cond_valid_139); - reg [32-1:0] __delay_data_151; + reg signed [32-1:0] __delay_data_151; reg __delay_valid_151; wire __delay_ready_151; assign _cond_ready_142 = (_lessthan_ready_147 || !_lessthan_valid_147) && (_cond_valid_142 && _cond_valid_139) && ((__delay_ready_151 || !__delay_valid_151) && _cond_valid_142); - reg [32-1:0] __delay_data_152; + reg signed [32-1:0] __delay_data_152; reg __delay_valid_152; wire __delay_ready_152; assign _cond_ready_141 = (_lessthan_ready_148 || !_lessthan_valid_148) && (_cond_valid_144 && _cond_valid_141) && ((__delay_ready_152 || !__delay_valid_152) && _cond_valid_141); - reg [32-1:0] __delay_data_153; + reg signed [32-1:0] __delay_data_153; reg __delay_valid_153; wire __delay_ready_153; assign _cond_ready_144 = (_lessthan_ready_148 || !_lessthan_valid_148) && (_cond_valid_144 && _cond_valid_141) && ((__delay_ready_153 || !__delay_valid_153) && _cond_valid_144); - reg [32-1:0] __delay_data_154; + reg signed [32-1:0] __delay_data_154; reg __delay_valid_154; wire __delay_ready_154; assign _cond_ready_143 = (_lessthan_ready_149 || !_lessthan_valid_149) && (__delay_valid_145 && _cond_valid_143) && ((__delay_ready_154 || !__delay_valid_154) && _cond_valid_143); - reg [32-1:0] __delay_data_155; + reg signed [32-1:0] __delay_data_155; reg __delay_valid_155; wire __delay_ready_155; assign __delay_ready_145 = (_lessthan_ready_149 || !_lessthan_valid_149) && (__delay_valid_145 && _cond_valid_143) && ((__delay_ready_155 || !__delay_valid_155) && __delay_valid_145); - reg [32-1:0] __delay_data_156; + reg signed [32-1:0] __delay_data_156; reg __delay_valid_156; wire __delay_ready_156; assign __delay_ready_146 = (__delay_ready_156 || !__delay_valid_156) && __delay_valid_146; - reg [32-1:0] __delay_data_157; + reg signed [32-1:0] __delay_data_157; reg __delay_valid_157; wire __delay_ready_157; assign _cond_ready_140 = (__delay_ready_157 || !__delay_valid_157) && _cond_valid_140; - reg [32-1:0] _cond_data_158; + reg signed [32-1:0] _cond_data_158; reg _cond_valid_158; wire _cond_ready_158; - reg [32-1:0] _cond_data_159; + reg signed [32-1:0] _cond_data_159; reg _cond_valid_159; wire _cond_ready_159; assign _lessthan_ready_147 = (_cond_ready_158 || !_cond_valid_158) && (_lessthan_valid_147 && __delay_valid_151 && __delay_valid_150) && ((_cond_ready_159 || !_cond_valid_159) && (_lessthan_valid_147 && __delay_valid_150 && __delay_valid_151)); assign __delay_ready_150 = (_cond_ready_158 || !_cond_valid_158) && (_lessthan_valid_147 && __delay_valid_151 && __delay_valid_150) && ((_cond_ready_159 || !_cond_valid_159) && (_lessthan_valid_147 && __delay_valid_150 && __delay_valid_151)); assign __delay_ready_151 = (_cond_ready_158 || !_cond_valid_158) && (_lessthan_valid_147 && __delay_valid_151 && __delay_valid_150) && ((_cond_ready_159 || !_cond_valid_159) && (_lessthan_valid_147 && __delay_valid_150 && __delay_valid_151)); - reg [32-1:0] _cond_data_160; + reg signed [32-1:0] _cond_data_160; reg _cond_valid_160; wire _cond_ready_160; - reg [32-1:0] _cond_data_161; + reg signed [32-1:0] _cond_data_161; reg _cond_valid_161; wire _cond_ready_161; assign _lessthan_ready_148 = (_cond_ready_160 || !_cond_valid_160) && (_lessthan_valid_148 && __delay_valid_153 && __delay_valid_152) && ((_cond_ready_161 || !_cond_valid_161) && (_lessthan_valid_148 && __delay_valid_152 && __delay_valid_153)); assign __delay_ready_152 = (_cond_ready_160 || !_cond_valid_160) && (_lessthan_valid_148 && __delay_valid_153 && __delay_valid_152) && ((_cond_ready_161 || !_cond_valid_161) && (_lessthan_valid_148 && __delay_valid_152 && __delay_valid_153)); assign __delay_ready_153 = (_cond_ready_160 || !_cond_valid_160) && (_lessthan_valid_148 && __delay_valid_153 && __delay_valid_152) && ((_cond_ready_161 || !_cond_valid_161) && (_lessthan_valid_148 && __delay_valid_152 && __delay_valid_153)); - reg [32-1:0] _cond_data_162; + reg signed [32-1:0] _cond_data_162; reg _cond_valid_162; wire _cond_ready_162; - reg [32-1:0] _cond_data_163; + reg signed [32-1:0] _cond_data_163; reg _cond_valid_163; wire _cond_ready_163; assign _lessthan_ready_149 = (_cond_ready_162 || !_cond_valid_162) && (_lessthan_valid_149 && __delay_valid_155 && __delay_valid_154) && ((_cond_ready_163 || !_cond_valid_163) && (_lessthan_valid_149 && __delay_valid_154 && __delay_valid_155)); assign __delay_ready_154 = (_cond_ready_162 || !_cond_valid_162) && (_lessthan_valid_149 && __delay_valid_155 && __delay_valid_154) && ((_cond_ready_163 || !_cond_valid_163) && (_lessthan_valid_149 && __delay_valid_154 && __delay_valid_155)); assign __delay_ready_155 = (_cond_ready_162 || !_cond_valid_162) && (_lessthan_valid_149 && __delay_valid_155 && __delay_valid_154) && ((_cond_ready_163 || !_cond_valid_163) && (_lessthan_valid_149 && __delay_valid_154 && __delay_valid_155)); - reg [32-1:0] __delay_data_164; + reg signed [32-1:0] __delay_data_164; reg __delay_valid_164; wire __delay_ready_164; assign __delay_ready_156 = (__delay_ready_164 || !__delay_valid_164) && __delay_valid_156; - reg [32-1:0] __delay_data_165; + reg signed [32-1:0] __delay_data_165; reg __delay_valid_165; wire __delay_ready_165; assign __delay_ready_157 = (__delay_ready_165 || !__delay_valid_165) && __delay_valid_157; @@ -1640,69 +1640,69 @@ reg [1-1:0] _lessthan_data_167; reg _lessthan_valid_167; wire _lessthan_ready_167; - reg [32-1:0] __delay_data_168; + reg signed [32-1:0] __delay_data_168; reg __delay_valid_168; wire __delay_ready_168; assign _cond_ready_158 = (_lessthan_ready_166 || !_lessthan_valid_166) && (_cond_valid_161 && _cond_valid_158) && ((__delay_ready_168 || !__delay_valid_168) && _cond_valid_158); - reg [32-1:0] __delay_data_169; + reg signed [32-1:0] __delay_data_169; reg __delay_valid_169; wire __delay_ready_169; assign _cond_ready_161 = (_lessthan_ready_166 || !_lessthan_valid_166) && (_cond_valid_161 && _cond_valid_158) && ((__delay_ready_169 || !__delay_valid_169) && _cond_valid_161); - reg [32-1:0] __delay_data_170; + reg signed [32-1:0] __delay_data_170; reg __delay_valid_170; wire __delay_ready_170; assign _cond_ready_160 = (_lessthan_ready_167 || !_lessthan_valid_167) && (_cond_valid_163 && _cond_valid_160) && ((__delay_ready_170 || !__delay_valid_170) && _cond_valid_160); - reg [32-1:0] __delay_data_171; + reg signed [32-1:0] __delay_data_171; reg __delay_valid_171; wire __delay_ready_171; assign _cond_ready_163 = (_lessthan_ready_167 || !_lessthan_valid_167) && (_cond_valid_163 && _cond_valid_160) && ((__delay_ready_171 || !__delay_valid_171) && _cond_valid_163); - reg [32-1:0] __delay_data_172; + reg signed [32-1:0] __delay_data_172; reg __delay_valid_172; wire __delay_ready_172; assign _cond_ready_162 = (__delay_ready_172 || !__delay_valid_172) && _cond_valid_162; - reg [32-1:0] __delay_data_173; + reg signed [32-1:0] __delay_data_173; reg __delay_valid_173; wire __delay_ready_173; assign __delay_ready_164 = (__delay_ready_173 || !__delay_valid_173) && __delay_valid_164; - reg [32-1:0] __delay_data_174; + reg signed [32-1:0] __delay_data_174; reg __delay_valid_174; wire __delay_ready_174; assign __delay_ready_165 = (__delay_ready_174 || !__delay_valid_174) && __delay_valid_165; - reg [32-1:0] __delay_data_175; + reg signed [32-1:0] __delay_data_175; reg __delay_valid_175; wire __delay_ready_175; assign _cond_ready_159 = (__delay_ready_175 || !__delay_valid_175) && _cond_valid_159; - reg [32-1:0] _cond_data_176; + reg signed [32-1:0] _cond_data_176; reg _cond_valid_176; wire _cond_ready_176; - reg [32-1:0] _cond_data_177; + reg signed [32-1:0] _cond_data_177; reg _cond_valid_177; wire _cond_ready_177; assign _lessthan_ready_166 = (_cond_ready_176 || !_cond_valid_176) && (_lessthan_valid_166 && __delay_valid_169 && __delay_valid_168) && ((_cond_ready_177 || !_cond_valid_177) && (_lessthan_valid_166 && __delay_valid_168 && __delay_valid_169)); assign __delay_ready_168 = (_cond_ready_176 || !_cond_valid_176) && (_lessthan_valid_166 && __delay_valid_169 && __delay_valid_168) && ((_cond_ready_177 || !_cond_valid_177) && (_lessthan_valid_166 && __delay_valid_168 && __delay_valid_169)); assign __delay_ready_169 = (_cond_ready_176 || !_cond_valid_176) && (_lessthan_valid_166 && __delay_valid_169 && __delay_valid_168) && ((_cond_ready_177 || !_cond_valid_177) && (_lessthan_valid_166 && __delay_valid_168 && __delay_valid_169)); - reg [32-1:0] _cond_data_178; + reg signed [32-1:0] _cond_data_178; reg _cond_valid_178; wire _cond_ready_178; - reg [32-1:0] _cond_data_179; + reg signed [32-1:0] _cond_data_179; reg _cond_valid_179; wire _cond_ready_179; assign _lessthan_ready_167 = (_cond_ready_178 || !_cond_valid_178) && (_lessthan_valid_167 && __delay_valid_171 && __delay_valid_170) && ((_cond_ready_179 || !_cond_valid_179) && (_lessthan_valid_167 && __delay_valid_170 && __delay_valid_171)); assign __delay_ready_170 = (_cond_ready_178 || !_cond_valid_178) && (_lessthan_valid_167 && __delay_valid_171 && __delay_valid_170) && ((_cond_ready_179 || !_cond_valid_179) && (_lessthan_valid_167 && __delay_valid_170 && __delay_valid_171)); assign __delay_ready_171 = (_cond_ready_178 || !_cond_valid_178) && (_lessthan_valid_167 && __delay_valid_171 && __delay_valid_170) && ((_cond_ready_179 || !_cond_valid_179) && (_lessthan_valid_167 && __delay_valid_170 && __delay_valid_171)); - reg [32-1:0] __delay_data_180; + reg signed [32-1:0] __delay_data_180; reg __delay_valid_180; wire __delay_ready_180; assign __delay_ready_172 = (__delay_ready_180 || !__delay_valid_180) && __delay_valid_172; - reg [32-1:0] __delay_data_181; + reg signed [32-1:0] __delay_data_181; reg __delay_valid_181; wire __delay_ready_181; assign __delay_ready_173 = (__delay_ready_181 || !__delay_valid_181) && __delay_valid_173; - reg [32-1:0] __delay_data_182; + reg signed [32-1:0] __delay_data_182; reg __delay_valid_182; wire __delay_ready_182; assign __delay_ready_174 = (__delay_ready_182 || !__delay_valid_182) && __delay_valid_174; - reg [32-1:0] __delay_data_183; + reg signed [32-1:0] __delay_data_183; reg __delay_valid_183; wire __delay_ready_183; assign __delay_ready_175 = (__delay_ready_183 || !__delay_valid_183) && __delay_valid_175; @@ -1712,205 +1712,205 @@ reg [1-1:0] _lessthan_data_185; reg _lessthan_valid_185; wire _lessthan_ready_185; - reg [32-1:0] __delay_data_186; + reg signed [32-1:0] __delay_data_186; reg __delay_valid_186; wire __delay_ready_186; assign _cond_ready_176 = (_lessthan_ready_184 || !_lessthan_valid_184) && (_cond_valid_179 && _cond_valid_176) && ((__delay_ready_186 || !__delay_valid_186) && _cond_valid_176); - reg [32-1:0] __delay_data_187; + reg signed [32-1:0] __delay_data_187; reg __delay_valid_187; wire __delay_ready_187; assign _cond_ready_179 = (_lessthan_ready_184 || !_lessthan_valid_184) && (_cond_valid_179 && _cond_valid_176) && ((__delay_ready_187 || !__delay_valid_187) && _cond_valid_179); - reg [32-1:0] __delay_data_188; + reg signed [32-1:0] __delay_data_188; reg __delay_valid_188; wire __delay_ready_188; assign _cond_ready_178 = (_lessthan_ready_185 || !_lessthan_valid_185) && (__delay_valid_180 && _cond_valid_178) && ((__delay_ready_188 || !__delay_valid_188) && _cond_valid_178); - reg [32-1:0] __delay_data_189; + reg signed [32-1:0] __delay_data_189; reg __delay_valid_189; wire __delay_ready_189; assign __delay_ready_180 = (_lessthan_ready_185 || !_lessthan_valid_185) && (__delay_valid_180 && _cond_valid_178) && ((__delay_ready_189 || !__delay_valid_189) && __delay_valid_180); - reg [32-1:0] __delay_data_190; + reg signed [32-1:0] __delay_data_190; reg __delay_valid_190; wire __delay_ready_190; assign __delay_ready_181 = (__delay_ready_190 || !__delay_valid_190) && __delay_valid_181; - reg [32-1:0] __delay_data_191; + reg signed [32-1:0] __delay_data_191; reg __delay_valid_191; wire __delay_ready_191; assign __delay_ready_182 = (__delay_ready_191 || !__delay_valid_191) && __delay_valid_182; - reg [32-1:0] __delay_data_192; + reg signed [32-1:0] __delay_data_192; reg __delay_valid_192; wire __delay_ready_192; assign __delay_ready_183 = (__delay_ready_192 || !__delay_valid_192) && __delay_valid_183; - reg [32-1:0] __delay_data_193; + reg signed [32-1:0] __delay_data_193; reg __delay_valid_193; wire __delay_ready_193; assign _cond_ready_177 = (__delay_ready_193 || !__delay_valid_193) && _cond_valid_177; - reg [32-1:0] _cond_data_194; + reg signed [32-1:0] _cond_data_194; reg _cond_valid_194; wire _cond_ready_194; - reg [32-1:0] _cond_data_195; + reg signed [32-1:0] _cond_data_195; reg _cond_valid_195; wire _cond_ready_195; assign _lessthan_ready_184 = (_cond_ready_194 || !_cond_valid_194) && (_lessthan_valid_184 && __delay_valid_187 && __delay_valid_186) && ((_cond_ready_195 || !_cond_valid_195) && (_lessthan_valid_184 && __delay_valid_186 && __delay_valid_187)); assign __delay_ready_186 = (_cond_ready_194 || !_cond_valid_194) && (_lessthan_valid_184 && __delay_valid_187 && __delay_valid_186) && ((_cond_ready_195 || !_cond_valid_195) && (_lessthan_valid_184 && __delay_valid_186 && __delay_valid_187)); assign __delay_ready_187 = (_cond_ready_194 || !_cond_valid_194) && (_lessthan_valid_184 && __delay_valid_187 && __delay_valid_186) && ((_cond_ready_195 || !_cond_valid_195) && (_lessthan_valid_184 && __delay_valid_186 && __delay_valid_187)); - reg [32-1:0] _cond_data_196; + reg signed [32-1:0] _cond_data_196; reg _cond_valid_196; wire _cond_ready_196; - reg [32-1:0] _cond_data_197; + reg signed [32-1:0] _cond_data_197; reg _cond_valid_197; wire _cond_ready_197; assign _lessthan_ready_185 = (_cond_ready_196 || !_cond_valid_196) && (_lessthan_valid_185 && __delay_valid_189 && __delay_valid_188) && ((_cond_ready_197 || !_cond_valid_197) && (_lessthan_valid_185 && __delay_valid_188 && __delay_valid_189)); assign __delay_ready_188 = (_cond_ready_196 || !_cond_valid_196) && (_lessthan_valid_185 && __delay_valid_189 && __delay_valid_188) && ((_cond_ready_197 || !_cond_valid_197) && (_lessthan_valid_185 && __delay_valid_188 && __delay_valid_189)); assign __delay_ready_189 = (_cond_ready_196 || !_cond_valid_196) && (_lessthan_valid_185 && __delay_valid_189 && __delay_valid_188) && ((_cond_ready_197 || !_cond_valid_197) && (_lessthan_valid_185 && __delay_valid_188 && __delay_valid_189)); - reg [32-1:0] __delay_data_198; + reg signed [32-1:0] __delay_data_198; reg __delay_valid_198; wire __delay_ready_198; assign __delay_ready_190 = (__delay_ready_198 || !__delay_valid_198) && __delay_valid_190; - reg [32-1:0] __delay_data_199; + reg signed [32-1:0] __delay_data_199; reg __delay_valid_199; wire __delay_ready_199; assign __delay_ready_191 = (__delay_ready_199 || !__delay_valid_199) && __delay_valid_191; - reg [32-1:0] __delay_data_200; + reg signed [32-1:0] __delay_data_200; reg __delay_valid_200; wire __delay_ready_200; assign __delay_ready_192 = (__delay_ready_200 || !__delay_valid_200) && __delay_valid_192; - reg [32-1:0] __delay_data_201; + reg signed [32-1:0] __delay_data_201; reg __delay_valid_201; wire __delay_ready_201; assign __delay_ready_193 = (__delay_ready_201 || !__delay_valid_201) && __delay_valid_193; reg [1-1:0] _lessthan_data_202; reg _lessthan_valid_202; wire _lessthan_ready_202; - reg [32-1:0] __delay_data_203; + reg signed [32-1:0] __delay_data_203; reg __delay_valid_203; wire __delay_ready_203; assign _cond_ready_194 = (_lessthan_ready_202 || !_lessthan_valid_202) && (_cond_valid_197 && _cond_valid_194) && ((__delay_ready_203 || !__delay_valid_203) && _cond_valid_194); - reg [32-1:0] __delay_data_204; + reg signed [32-1:0] __delay_data_204; reg __delay_valid_204; wire __delay_ready_204; assign _cond_ready_197 = (_lessthan_ready_202 || !_lessthan_valid_202) && (_cond_valid_197 && _cond_valid_194) && ((__delay_ready_204 || !__delay_valid_204) && _cond_valid_197); - reg [32-1:0] __delay_data_205; + reg signed [32-1:0] __delay_data_205; reg __delay_valid_205; wire __delay_ready_205; assign _cond_ready_196 = (__delay_ready_205 || !__delay_valid_205) && _cond_valid_196; - reg [32-1:0] __delay_data_206; + reg signed [32-1:0] __delay_data_206; reg __delay_valid_206; wire __delay_ready_206; assign __delay_ready_198 = (__delay_ready_206 || !__delay_valid_206) && __delay_valid_198; - reg [32-1:0] __delay_data_207; + reg signed [32-1:0] __delay_data_207; reg __delay_valid_207; wire __delay_ready_207; assign __delay_ready_199 = (__delay_ready_207 || !__delay_valid_207) && __delay_valid_199; - reg [32-1:0] __delay_data_208; + reg signed [32-1:0] __delay_data_208; reg __delay_valid_208; wire __delay_ready_208; assign __delay_ready_200 = (__delay_ready_208 || !__delay_valid_208) && __delay_valid_200; - reg [32-1:0] __delay_data_209; + reg signed [32-1:0] __delay_data_209; reg __delay_valid_209; wire __delay_ready_209; assign __delay_ready_201 = (__delay_ready_209 || !__delay_valid_209) && __delay_valid_201; - reg [32-1:0] __delay_data_210; + reg signed [32-1:0] __delay_data_210; reg __delay_valid_210; wire __delay_ready_210; assign _cond_ready_195 = (__delay_ready_210 || !__delay_valid_210) && _cond_valid_195; - reg [32-1:0] _cond_data_211; + reg signed [32-1:0] _cond_data_211; reg _cond_valid_211; wire _cond_ready_211; - reg [32-1:0] _cond_data_212; + reg signed [32-1:0] _cond_data_212; reg _cond_valid_212; wire _cond_ready_212; assign _lessthan_ready_202 = (_cond_ready_211 || !_cond_valid_211) && (_lessthan_valid_202 && __delay_valid_204 && __delay_valid_203) && ((_cond_ready_212 || !_cond_valid_212) && (_lessthan_valid_202 && __delay_valid_203 && __delay_valid_204)); assign __delay_ready_203 = (_cond_ready_211 || !_cond_valid_211) && (_lessthan_valid_202 && __delay_valid_204 && __delay_valid_203) && ((_cond_ready_212 || !_cond_valid_212) && (_lessthan_valid_202 && __delay_valid_203 && __delay_valid_204)); assign __delay_ready_204 = (_cond_ready_211 || !_cond_valid_211) && (_lessthan_valid_202 && __delay_valid_204 && __delay_valid_203) && ((_cond_ready_212 || !_cond_valid_212) && (_lessthan_valid_202 && __delay_valid_203 && __delay_valid_204)); - reg [32-1:0] __delay_data_213; + reg signed [32-1:0] __delay_data_213; reg __delay_valid_213; wire __delay_ready_213; assign __delay_ready_205 = (__delay_ready_213 || !__delay_valid_213) && __delay_valid_205; - reg [32-1:0] __delay_data_214; + reg signed [32-1:0] __delay_data_214; reg __delay_valid_214; wire __delay_ready_214; assign __delay_ready_206 = (__delay_ready_214 || !__delay_valid_214) && __delay_valid_206; - reg [32-1:0] __delay_data_215; + reg signed [32-1:0] __delay_data_215; reg __delay_valid_215; wire __delay_ready_215; assign __delay_ready_207 = (__delay_ready_215 || !__delay_valid_215) && __delay_valid_207; - reg [32-1:0] __delay_data_216; + reg signed [32-1:0] __delay_data_216; reg __delay_valid_216; wire __delay_ready_216; assign __delay_ready_208 = (__delay_ready_216 || !__delay_valid_216) && __delay_valid_208; - reg [32-1:0] __delay_data_217; + reg signed [32-1:0] __delay_data_217; reg __delay_valid_217; wire __delay_ready_217; assign __delay_ready_209 = (__delay_ready_217 || !__delay_valid_217) && __delay_valid_209; - reg [32-1:0] __delay_data_218; + reg signed [32-1:0] __delay_data_218; reg __delay_valid_218; wire __delay_ready_218; assign __delay_ready_210 = (__delay_ready_218 || !__delay_valid_218) && __delay_valid_210; reg [1-1:0] _lessthan_data_219; reg _lessthan_valid_219; wire _lessthan_ready_219; - reg [32-1:0] __delay_data_220; + reg signed [32-1:0] __delay_data_220; reg __delay_valid_220; wire __delay_ready_220; assign __delay_ready_213 = (_lessthan_ready_219 || !_lessthan_valid_219) && (__delay_valid_213 && _cond_valid_211) && ((__delay_ready_220 || !__delay_valid_220) && __delay_valid_213); - reg [32-1:0] __delay_data_221; + reg signed [32-1:0] __delay_data_221; reg __delay_valid_221; wire __delay_ready_221; assign _cond_ready_211 = (_lessthan_ready_219 || !_lessthan_valid_219) && (__delay_valid_213 && _cond_valid_211) && ((__delay_ready_221 || !__delay_valid_221) && _cond_valid_211); - reg [32-1:0] __delay_data_222; + reg signed [32-1:0] __delay_data_222; reg __delay_valid_222; wire __delay_ready_222; assign __delay_ready_214 = (__delay_ready_222 || !__delay_valid_222) && __delay_valid_214; - reg [32-1:0] __delay_data_223; + reg signed [32-1:0] __delay_data_223; reg __delay_valid_223; wire __delay_ready_223; assign __delay_ready_215 = (__delay_ready_223 || !__delay_valid_223) && __delay_valid_215; - reg [32-1:0] __delay_data_224; + reg signed [32-1:0] __delay_data_224; reg __delay_valid_224; wire __delay_ready_224; assign __delay_ready_216 = (__delay_ready_224 || !__delay_valid_224) && __delay_valid_216; - reg [32-1:0] __delay_data_225; + reg signed [32-1:0] __delay_data_225; reg __delay_valid_225; wire __delay_ready_225; assign __delay_ready_217 = (__delay_ready_225 || !__delay_valid_225) && __delay_valid_217; - reg [32-1:0] __delay_data_226; + reg signed [32-1:0] __delay_data_226; reg __delay_valid_226; wire __delay_ready_226; assign __delay_ready_218 = (__delay_ready_226 || !__delay_valid_226) && __delay_valid_218; - reg [32-1:0] __delay_data_227; + reg signed [32-1:0] __delay_data_227; reg __delay_valid_227; wire __delay_ready_227; assign _cond_ready_212 = (__delay_ready_227 || !__delay_valid_227) && _cond_valid_212; - reg [32-1:0] _cond_data_228; + reg signed [32-1:0] _cond_data_228; reg _cond_valid_228; wire _cond_ready_228; - reg [32-1:0] _cond_data_229; + reg signed [32-1:0] _cond_data_229; reg _cond_valid_229; wire _cond_ready_229; assign _lessthan_ready_219 = (_cond_ready_228 || !_cond_valid_228) && (_lessthan_valid_219 && __delay_valid_220 && __delay_valid_221) && ((_cond_ready_229 || !_cond_valid_229) && (_lessthan_valid_219 && __delay_valid_221 && __delay_valid_220)); assign __delay_ready_221 = (_cond_ready_228 || !_cond_valid_228) && (_lessthan_valid_219 && __delay_valid_220 && __delay_valid_221) && ((_cond_ready_229 || !_cond_valid_229) && (_lessthan_valid_219 && __delay_valid_221 && __delay_valid_220)); assign __delay_ready_220 = (_cond_ready_228 || !_cond_valid_228) && (_lessthan_valid_219 && __delay_valid_220 && __delay_valid_221) && ((_cond_ready_229 || !_cond_valid_229) && (_lessthan_valid_219 && __delay_valid_221 && __delay_valid_220)); - reg [32-1:0] __delay_data_230; + reg signed [32-1:0] __delay_data_230; reg __delay_valid_230; wire __delay_ready_230; assign __delay_ready_222 = (__delay_ready_230 || !__delay_valid_230) && __delay_valid_222; - reg [32-1:0] __delay_data_231; + reg signed [32-1:0] __delay_data_231; reg __delay_valid_231; wire __delay_ready_231; assign __delay_ready_223 = (__delay_ready_231 || !__delay_valid_231) && __delay_valid_223; - reg [32-1:0] __delay_data_232; + reg signed [32-1:0] __delay_data_232; reg __delay_valid_232; wire __delay_ready_232; assign __delay_ready_224 = (__delay_ready_232 || !__delay_valid_232) && __delay_valid_224; - reg [32-1:0] __delay_data_233; + reg signed [32-1:0] __delay_data_233; reg __delay_valid_233; wire __delay_ready_233; assign __delay_ready_225 = (__delay_ready_233 || !__delay_valid_233) && __delay_valid_225; - reg [32-1:0] __delay_data_234; + reg signed [32-1:0] __delay_data_234; reg __delay_valid_234; wire __delay_ready_234; assign __delay_ready_226 = (__delay_ready_234 || !__delay_valid_234) && __delay_valid_226; - reg [32-1:0] __delay_data_235; + reg signed [32-1:0] __delay_data_235; reg __delay_valid_235; wire __delay_ready_235; assign __delay_ready_227 = (__delay_ready_235 || !__delay_valid_235) && __delay_valid_227; diff --git a/tests/extension/stream_/iadd_validready/Makefile b/examples/thread_myverilog_ipcore/Makefile similarity index 88% rename from tests/extension/stream_/iadd_validready/Makefile rename to examples/thread_myverilog_ipcore/Makefile index 499ae3b1..72892809 100644 --- a/tests/extension/stream_/iadd_validready/Makefile +++ b/examples/thread_myverilog_ipcore/Makefile @@ -13,6 +13,7 @@ all: test .PHONY: run run: $(PYTHON) $(OPT) $(TARGET) $(ARGS) + make compile run -C ipgen_*_v1_00_a/test/ .PHONY: test test: @@ -27,3 +28,4 @@ check: .PHONY: clean clean: rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd + rm -rf ipgen_*_v1_00_a diff --git a/examples/thread_myverilog_ipcore/test_thread_myverilog_ipcore.py b/examples/thread_myverilog_ipcore/test_thread_myverilog_ipcore.py new file mode 100644 index 00000000..00dc988f --- /dev/null +++ b/examples/thread_myverilog_ipcore/test_thread_myverilog_ipcore.py @@ -0,0 +1,2100 @@ +from __future__ import absolute_import +from __future__ import print_function +import veriloggen +import thread_myverilog_ipcore + +expected_verilog = """ +module test # +( + parameter DATA_WIDTH = 32, + parameter ADDR_WIDTH = 10 +) +( + +); + + reg CLK; + reg RST; + wire [8-1:0] led; + wire [32-1:0] maxi_awaddr; + wire [8-1:0] maxi_awlen; + wire maxi_awvalid; + reg maxi_awready; + wire [32-1:0] maxi_wdata; + wire [4-1:0] maxi_wstrb; + wire maxi_wlast; + wire maxi_wvalid; + reg maxi_wready; + wire [32-1:0] maxi_araddr; + wire [8-1:0] maxi_arlen; + wire maxi_arvalid; + reg maxi_arready; + reg [32-1:0] maxi_rdata; + reg maxi_rlast; + reg maxi_rvalid; + wire maxi_rready; + reg [32-1:0] saxi_awaddr; + reg saxi_awvalid; + wire saxi_awready; + reg [32-1:0] saxi_wdata; + reg [4-1:0] saxi_wstrb; + reg saxi_wvalid; + wire saxi_wready; + reg [32-1:0] saxi_araddr; + reg saxi_arvalid; + wire saxi_arready; + wire [32-1:0] saxi_rdata; + wire saxi_rvalid; + reg saxi_rready; + + blinkled + #( + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH) + ) + uut + ( + .CLK(CLK), + .RST(RST), + .led(led), + .maxi_awaddr(maxi_awaddr), + .maxi_awlen(maxi_awlen), + .maxi_awvalid(maxi_awvalid), + .maxi_awready(maxi_awready), + .maxi_wdata(maxi_wdata), + .maxi_wstrb(maxi_wstrb), + .maxi_wlast(maxi_wlast), + .maxi_wvalid(maxi_wvalid), + .maxi_wready(maxi_wready), + .maxi_araddr(maxi_araddr), + .maxi_arlen(maxi_arlen), + .maxi_arvalid(maxi_arvalid), + .maxi_arready(maxi_arready), + .maxi_rdata(maxi_rdata), + .maxi_rlast(maxi_rlast), + .maxi_rvalid(maxi_rvalid), + .maxi_rready(maxi_rready), + .saxi_awaddr(saxi_awaddr), + .saxi_awvalid(saxi_awvalid), + .saxi_awready(saxi_awready), + .saxi_wdata(saxi_wdata), + .saxi_wstrb(saxi_wstrb), + .saxi_wvalid(saxi_wvalid), + .saxi_wready(saxi_wready), + .saxi_araddr(saxi_araddr), + .saxi_arvalid(saxi_arvalid), + .saxi_arready(saxi_arready), + .saxi_rdata(saxi_rdata), + .saxi_rvalid(saxi_rvalid), + .saxi_rready(saxi_rready) + ); + + wire [32-1:0] memory_awaddr; + wire [8-1:0] memory_awlen; + wire memory_awvalid; + reg memory_awready; + wire [32-1:0] memory_wdata; + wire [4-1:0] memory_wstrb; + wire memory_wlast; + wire memory_wvalid; + reg memory_wready; + wire [32-1:0] memory_araddr; + wire [8-1:0] memory_arlen; + wire memory_arvalid; + reg memory_arready; + reg [32-1:0] memory_rdata; + reg memory_rlast; + reg memory_rvalid; + wire memory_rready; + reg [8-1:0] _memory_mem [0:2**20-1]; + + initial begin + $readmemh("_memory_memimg_.out", _memory_mem); + end + + reg [32-1:0] _memory_fsm; + localparam _memory_fsm_init = 0; + reg [33-1:0] _write_count; + reg [32-1:0] _write_addr; + reg [33-1:0] _read_count; + reg [32-1:0] _read_addr; + reg [33-1:0] _sleep_count; + reg [32-1:0] _d1__memory_fsm; + reg __memory_fsm_cond_100_0_1; + reg __memory_fsm_cond_200_1_1; + reg __memory_fsm_cond_211_2_1; + assign memory_awaddr = maxi_awaddr; + assign memory_awlen = maxi_awlen; + assign memory_awvalid = maxi_awvalid; + wire _tmp_0; + assign _tmp_0 = memory_awready; + + always @(*) begin + maxi_awready = _tmp_0; + end + + assign memory_wdata = maxi_wdata; + assign memory_wstrb = maxi_wstrb; + assign memory_wlast = maxi_wlast; + assign memory_wvalid = maxi_wvalid; + wire _tmp_1; + assign _tmp_1 = memory_wready; + + always @(*) begin + maxi_wready = _tmp_1; + end + + assign memory_araddr = maxi_araddr; + assign memory_arlen = maxi_arlen; + assign memory_arvalid = maxi_arvalid; + wire _tmp_2; + assign _tmp_2 = memory_arready; + + always @(*) begin + maxi_arready = _tmp_2; + end + + + always @(*) begin + maxi_rdata <= memory_rdata; + end + + wire _tmp_3; + assign _tmp_3 = memory_rlast; + + always @(*) begin + maxi_rlast = _tmp_3; + end + + wire _tmp_4; + assign _tmp_4 = memory_rvalid; + + always @(*) begin + maxi_rvalid = _tmp_4; + end + + assign memory_rready = maxi_rready; + reg [32-1:0] _saxi_awaddr; + reg _saxi_awvalid; + wire _saxi_awready; + reg [32-1:0] _saxi_wdata; + reg [4-1:0] _saxi_wstrb; + reg _saxi_wvalid; + wire _saxi_wready; + reg [32-1:0] _saxi_araddr; + reg _saxi_arvalid; + wire _saxi_arready; + wire [32-1:0] _saxi_rdata; + wire _saxi_rvalid; + wire _saxi_rready; + wire [32-1:0] _tmp_5; + assign _tmp_5 = _saxi_awaddr; + + always @(*) begin + saxi_awaddr = _tmp_5; + end + + wire _tmp_6; + assign _tmp_6 = _saxi_awvalid; + + always @(*) begin + saxi_awvalid = _tmp_6; + end + + assign _saxi_awready = saxi_awready; + wire [32-1:0] _tmp_7; + assign _tmp_7 = _saxi_wdata; + + always @(*) begin + saxi_wdata = _tmp_7; + end + + wire [4-1:0] _tmp_8; + assign _tmp_8 = _saxi_wstrb; + + always @(*) begin + saxi_wstrb = _tmp_8; + end + + wire _tmp_9; + assign _tmp_9 = _saxi_wvalid; + + always @(*) begin + saxi_wvalid = _tmp_9; + end + + assign _saxi_wready = saxi_wready; + wire [32-1:0] _tmp_10; + assign _tmp_10 = _saxi_araddr; + + always @(*) begin + saxi_araddr = _tmp_10; + end + + wire _tmp_11; + assign _tmp_11 = _saxi_arvalid; + + always @(*) begin + saxi_arvalid = _tmp_11; + end + + assign _saxi_arready = saxi_arready; + assign _saxi_rdata = saxi_rdata; + assign _saxi_rvalid = saxi_rvalid; + wire _tmp_12; + assign _tmp_12 = _saxi_rready; + + always @(*) begin + saxi_rready = _tmp_12; + end + + reg [32-1:0] counter; + reg [32-1:0] th_ctrl; + localparam th_ctrl_init = 0; + reg signed [32-1:0] _th_ctrl_i_12; + reg signed [32-1:0] _th_ctrl_awaddr_13; + reg __saxi_cond_0_1; + reg __saxi_cond_1_1; + reg signed [32-1:0] _th_ctrl_src_offset_14; + reg __saxi_cond_2_1; + reg __saxi_cond_3_1; + reg signed [32-1:0] _th_ctrl_dst_offset_15; + reg __saxi_cond_4_1; + reg __saxi_cond_5_1; + reg signed [32-1:0] _th_ctrl_start_time_16; + reg __saxi_cond_6_1; + reg __saxi_cond_7_1; + reg signed [32-1:0] _th_ctrl_araddr_17; + reg __saxi_cond_8_1; + reg [32-1:0] _tmp_13; + reg signed [32-1:0] _th_ctrl_v_18; + reg __saxi_cond_9_1; + assign _saxi_rready = (th_ctrl == 25) || (th_ctrl == 29); + reg [32-1:0] _tmp_14; + reg signed [32-1:0] _th_ctrl_end_time_19; + reg signed [32-1:0] _th_ctrl_time_20; + + initial begin + $dumpfile("uut.vcd"); + $dumpvars(0, uut); + end + + + initial begin + CLK = 0; + forever begin + #5 CLK = !CLK; + end + end + + + initial begin + RST = 0; + memory_awready = 0; + memory_wready = 0; + memory_arready = 0; + memory_rdata = 0; + memory_rlast = 0; + memory_rvalid = 0; + _memory_fsm = _memory_fsm_init; + _write_count = 0; + _write_addr = 0; + _read_count = 0; + _read_addr = 0; + _sleep_count = 0; + _d1__memory_fsm = _memory_fsm_init; + __memory_fsm_cond_100_0_1 = 0; + __memory_fsm_cond_200_1_1 = 0; + __memory_fsm_cond_211_2_1 = 0; + _saxi_awaddr = 0; + _saxi_awvalid = 0; + _saxi_wdata = 0; + _saxi_wstrb = 0; + _saxi_wvalid = 0; + _saxi_araddr = 0; + _saxi_arvalid = 0; + counter = 0; + th_ctrl = th_ctrl_init; + _th_ctrl_i_12 = 0; + _th_ctrl_awaddr_13 = 0; + __saxi_cond_0_1 = 0; + __saxi_cond_1_1 = 0; + _th_ctrl_src_offset_14 = 0; + __saxi_cond_2_1 = 0; + __saxi_cond_3_1 = 0; + _th_ctrl_dst_offset_15 = 0; + __saxi_cond_4_1 = 0; + __saxi_cond_5_1 = 0; + _th_ctrl_start_time_16 = 0; + __saxi_cond_6_1 = 0; + __saxi_cond_7_1 = 0; + _th_ctrl_araddr_17 = 0; + __saxi_cond_8_1 = 0; + _tmp_13 = 0; + _th_ctrl_v_18 = 0; + __saxi_cond_9_1 = 0; + _tmp_14 = 0; + _th_ctrl_end_time_19 = 0; + _th_ctrl_time_20 = 0; + #100; + RST = 1; + #100; + RST = 0; + #1000000; + $finish; + end + + localparam _memory_fsm_200 = 200; + localparam _memory_fsm_201 = 201; + localparam _memory_fsm_202 = 202; + localparam _memory_fsm_203 = 203; + localparam _memory_fsm_204 = 204; + localparam _memory_fsm_205 = 205; + localparam _memory_fsm_206 = 206; + localparam _memory_fsm_207 = 207; + localparam _memory_fsm_208 = 208; + localparam _memory_fsm_209 = 209; + localparam _memory_fsm_210 = 210; + localparam _memory_fsm_211 = 211; + localparam _memory_fsm_100 = 100; + localparam _memory_fsm_101 = 101; + localparam _memory_fsm_102 = 102; + localparam _memory_fsm_103 = 103; + localparam _memory_fsm_104 = 104; + localparam _memory_fsm_105 = 105; + localparam _memory_fsm_106 = 106; + localparam _memory_fsm_107 = 107; + localparam _memory_fsm_108 = 108; + localparam _memory_fsm_109 = 109; + localparam _memory_fsm_110 = 110; + localparam _memory_fsm_111 = 111; + localparam _memory_fsm_112 = 112; + + always @(posedge CLK) begin + if(RST) begin + _memory_fsm <= _memory_fsm_init; + _d1__memory_fsm <= _memory_fsm_init; + memory_awready <= 0; + _write_addr <= 0; + _write_count <= 0; + __memory_fsm_cond_100_0_1 <= 0; + memory_wready <= 0; + memory_arready <= 0; + _read_addr <= 0; + _read_count <= 0; + __memory_fsm_cond_200_1_1 <= 0; + memory_rdata[7:0] <= (0 >> 0) & { 8{ 1'd1 } }; + memory_rdata[15:8] <= (0 >> 8) & { 8{ 1'd1 } }; + memory_rdata[23:16] <= (0 >> 16) & { 8{ 1'd1 } }; + memory_rdata[31:24] <= (0 >> 24) & { 8{ 1'd1 } }; + memory_rvalid <= 0; + memory_rlast <= 0; + __memory_fsm_cond_211_2_1 <= 0; + memory_rdata <= 0; + _sleep_count <= 0; + end else begin + _sleep_count <= _sleep_count + 1; + if(_sleep_count == 3) begin + _sleep_count <= 0; + end + _d1__memory_fsm <= _memory_fsm; + case(_d1__memory_fsm) + _memory_fsm_100: begin + if(__memory_fsm_cond_100_0_1) begin + memory_awready <= 0; + end + end + _memory_fsm_200: begin + if(__memory_fsm_cond_200_1_1) begin + memory_arready <= 0; + end + end + _memory_fsm_211: begin + if(__memory_fsm_cond_211_2_1) begin + memory_rvalid <= 0; + memory_rlast <= 0; + end + end + endcase + case(_memory_fsm) + _memory_fsm_init: begin + if(memory_awvalid) begin + _memory_fsm <= _memory_fsm_100; + end + if(memory_arvalid) begin + _memory_fsm <= _memory_fsm_200; + end + end + _memory_fsm_100: begin + if(memory_awvalid) begin + memory_awready <= 1; + _write_addr <= memory_awaddr; + _write_count <= memory_awlen + 1; + end + __memory_fsm_cond_100_0_1 <= 1; + if(!memory_awvalid) begin + _memory_fsm <= _memory_fsm_init; + end + if(memory_awvalid) begin + _memory_fsm <= _memory_fsm_101; + end + end + _memory_fsm_101: begin + _memory_fsm <= _memory_fsm_102; + end + _memory_fsm_102: begin + _memory_fsm <= _memory_fsm_103; + end + _memory_fsm_103: begin + _memory_fsm <= _memory_fsm_104; + end + _memory_fsm_104: begin + _memory_fsm <= _memory_fsm_105; + end + _memory_fsm_105: begin + _memory_fsm <= _memory_fsm_106; + end + _memory_fsm_106: begin + _memory_fsm <= _memory_fsm_107; + end + _memory_fsm_107: begin + _memory_fsm <= _memory_fsm_108; + end + _memory_fsm_108: begin + _memory_fsm <= _memory_fsm_109; + end + _memory_fsm_109: begin + _memory_fsm <= _memory_fsm_110; + end + _memory_fsm_110: begin + _memory_fsm <= _memory_fsm_111; + end + _memory_fsm_111: begin + memory_wready <= 1; + _memory_fsm <= _memory_fsm_112; + end + _memory_fsm_112: begin + if(memory_wvalid && memory_wstrb[0]) begin + _memory_mem[_write_addr + 0] <= memory_wdata[7:0]; + end + if(memory_wvalid && memory_wstrb[1]) begin + _memory_mem[_write_addr + 1] <= memory_wdata[15:8]; + end + if(memory_wvalid && memory_wstrb[2]) begin + _memory_mem[_write_addr + 2] <= memory_wdata[23:16]; + end + if(memory_wvalid && memory_wstrb[3]) begin + _memory_mem[_write_addr + 3] <= memory_wdata[31:24]; + end + if(memory_wvalid && memory_wready) begin + _write_addr <= _write_addr + 4; + _write_count <= _write_count - 1; + end + if(_sleep_count == 3) begin + memory_wready <= 0; + end else begin + memory_wready <= 1; + end + if(memory_wvalid && memory_wready && (_write_count == 1)) begin + memory_wready <= 0; + end + if(memory_wvalid && memory_wready && (_write_count == 1)) begin + _memory_fsm <= _memory_fsm_init; + end + end + _memory_fsm_200: begin + if(memory_arvalid) begin + memory_arready <= 1; + _read_addr <= memory_araddr; + _read_count <= memory_arlen + 1; + end + __memory_fsm_cond_200_1_1 <= 1; + if(!memory_arvalid) begin + _memory_fsm <= _memory_fsm_init; + end + if(memory_arvalid) begin + _memory_fsm <= _memory_fsm_201; + end + end + _memory_fsm_201: begin + _memory_fsm <= _memory_fsm_202; + end + _memory_fsm_202: begin + _memory_fsm <= _memory_fsm_203; + end + _memory_fsm_203: begin + _memory_fsm <= _memory_fsm_204; + end + _memory_fsm_204: begin + _memory_fsm <= _memory_fsm_205; + end + _memory_fsm_205: begin + _memory_fsm <= _memory_fsm_206; + end + _memory_fsm_206: begin + _memory_fsm <= _memory_fsm_207; + end + _memory_fsm_207: begin + _memory_fsm <= _memory_fsm_208; + end + _memory_fsm_208: begin + _memory_fsm <= _memory_fsm_209; + end + _memory_fsm_209: begin + _memory_fsm <= _memory_fsm_210; + end + _memory_fsm_210: begin + _memory_fsm <= _memory_fsm_211; + end + _memory_fsm_211: begin + if(memory_rready | !memory_rvalid) begin + memory_rdata[7:0] <= _memory_mem[_read_addr + 0]; + end + if(memory_rready | !memory_rvalid) begin + memory_rdata[15:8] <= _memory_mem[_read_addr + 1]; + end + if(memory_rready | !memory_rvalid) begin + memory_rdata[23:16] <= _memory_mem[_read_addr + 2]; + end + if(memory_rready | !memory_rvalid) begin + memory_rdata[31:24] <= _memory_mem[_read_addr + 3]; + end + if((_sleep_count < 3) && (_read_count > 0) && memory_rready | !memory_rvalid) begin + memory_rvalid <= 1; + _read_addr <= _read_addr + 4; + _read_count <= _read_count - 1; + end + if((_sleep_count < 3) && (_read_count == 1) && memory_rready | !memory_rvalid) begin + memory_rlast <= 1; + end + __memory_fsm_cond_211_2_1 <= 1; + if(memory_rvalid && !memory_rready) begin + memory_rvalid <= memory_rvalid; + memory_rdata <= memory_rdata; + memory_rlast <= memory_rlast; + end + if(memory_rvalid && memory_rready && (_read_count == 0)) begin + _memory_fsm <= _memory_fsm_init; + end + end + endcase + end + end + + + always @(posedge CLK) begin + if(RST) begin + _saxi_awaddr <= 0; + _saxi_awvalid <= 0; + __saxi_cond_0_1 <= 0; + _saxi_wdata <= 0; + _saxi_wvalid <= 0; + _saxi_wstrb <= 0; + __saxi_cond_1_1 <= 0; + __saxi_cond_2_1 <= 0; + __saxi_cond_3_1 <= 0; + __saxi_cond_4_1 <= 0; + __saxi_cond_5_1 <= 0; + __saxi_cond_6_1 <= 0; + __saxi_cond_7_1 <= 0; + _saxi_araddr <= 0; + _saxi_arvalid <= 0; + __saxi_cond_8_1 <= 0; + __saxi_cond_9_1 <= 0; + end else begin + if(__saxi_cond_0_1) begin + _saxi_awvalid <= 0; + end + if(__saxi_cond_1_1) begin + _saxi_wvalid <= 0; + end + if(__saxi_cond_2_1) begin + _saxi_awvalid <= 0; + end + if(__saxi_cond_3_1) begin + _saxi_wvalid <= 0; + end + if(__saxi_cond_4_1) begin + _saxi_awvalid <= 0; + end + if(__saxi_cond_5_1) begin + _saxi_wvalid <= 0; + end + if(__saxi_cond_6_1) begin + _saxi_awvalid <= 0; + end + if(__saxi_cond_7_1) begin + _saxi_wvalid <= 0; + end + if(__saxi_cond_8_1) begin + _saxi_arvalid <= 0; + end + if(__saxi_cond_9_1) begin + _saxi_arvalid <= 0; + end + if((th_ctrl == 6) && (_saxi_awready || !_saxi_awvalid)) begin + _saxi_awaddr <= _th_ctrl_awaddr_13; + _saxi_awvalid <= 1; + end + __saxi_cond_0_1 <= 1; + if(_saxi_awvalid && !_saxi_awready) begin + _saxi_awvalid <= _saxi_awvalid; + end + if((th_ctrl == 7) && (_saxi_wready || !_saxi_wvalid)) begin + _saxi_wdata <= 4096; + _saxi_wvalid <= 1; + _saxi_wstrb <= { 4{ 1'd1 } }; + end + __saxi_cond_1_1 <= 1; + if(_saxi_wvalid && !_saxi_wready) begin + _saxi_wvalid <= _saxi_wvalid; + end + if((th_ctrl == 11) && (_saxi_awready || !_saxi_awvalid)) begin + _saxi_awaddr <= _th_ctrl_awaddr_13; + _saxi_awvalid <= 1; + end + __saxi_cond_2_1 <= 1; + if(_saxi_awvalid && !_saxi_awready) begin + _saxi_awvalid <= _saxi_awvalid; + end + if((th_ctrl == 12) && (_saxi_wready || !_saxi_wvalid)) begin + _saxi_wdata <= _th_ctrl_src_offset_14; + _saxi_wvalid <= 1; + _saxi_wstrb <= { 4{ 1'd1 } }; + end + __saxi_cond_3_1 <= 1; + if(_saxi_wvalid && !_saxi_wready) begin + _saxi_wvalid <= _saxi_wvalid; + end + if((th_ctrl == 16) && (_saxi_awready || !_saxi_awvalid)) begin + _saxi_awaddr <= _th_ctrl_awaddr_13; + _saxi_awvalid <= 1; + end + __saxi_cond_4_1 <= 1; + if(_saxi_awvalid && !_saxi_awready) begin + _saxi_awvalid <= _saxi_awvalid; + end + if((th_ctrl == 17) && (_saxi_wready || !_saxi_wvalid)) begin + _saxi_wdata <= _th_ctrl_dst_offset_15; + _saxi_wvalid <= 1; + _saxi_wstrb <= { 4{ 1'd1 } }; + end + __saxi_cond_5_1 <= 1; + if(_saxi_wvalid && !_saxi_wready) begin + _saxi_wvalid <= _saxi_wvalid; + end + if((th_ctrl == 21) && (_saxi_awready || !_saxi_awvalid)) begin + _saxi_awaddr <= _th_ctrl_awaddr_13; + _saxi_awvalid <= 1; + end + __saxi_cond_6_1 <= 1; + if(_saxi_awvalid && !_saxi_awready) begin + _saxi_awvalid <= _saxi_awvalid; + end + if((th_ctrl == 22) && (_saxi_wready || !_saxi_wvalid)) begin + _saxi_wdata <= 1; + _saxi_wvalid <= 1; + _saxi_wstrb <= { 4{ 1'd1 } }; + end + __saxi_cond_7_1 <= 1; + if(_saxi_wvalid && !_saxi_wready) begin + _saxi_wvalid <= _saxi_wvalid; + end + if((th_ctrl == 24) && (_saxi_arready || !_saxi_arvalid)) begin + _saxi_araddr <= _th_ctrl_araddr_17; + _saxi_arvalid <= 1; + end + __saxi_cond_8_1 <= 1; + if(_saxi_arvalid && !_saxi_arready) begin + _saxi_arvalid <= _saxi_arvalid; + end + if((th_ctrl == 28) && (_saxi_arready || !_saxi_arvalid)) begin + _saxi_araddr <= _th_ctrl_araddr_17; + _saxi_arvalid <= 1; + end + __saxi_cond_9_1 <= 1; + if(_saxi_arvalid && !_saxi_arready) begin + _saxi_arvalid <= _saxi_arvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + counter <= 0; + end else begin + counter <= counter + 1; + end + end + + localparam th_ctrl_1 = 1; + localparam th_ctrl_2 = 2; + localparam th_ctrl_3 = 3; + localparam th_ctrl_4 = 4; + localparam th_ctrl_5 = 5; + localparam th_ctrl_6 = 6; + localparam th_ctrl_7 = 7; + localparam th_ctrl_8 = 8; + localparam th_ctrl_9 = 9; + localparam th_ctrl_10 = 10; + localparam th_ctrl_11 = 11; + localparam th_ctrl_12 = 12; + localparam th_ctrl_13 = 13; + localparam th_ctrl_14 = 14; + localparam th_ctrl_15 = 15; + localparam th_ctrl_16 = 16; + localparam th_ctrl_17 = 17; + localparam th_ctrl_18 = 18; + localparam th_ctrl_19 = 19; + localparam th_ctrl_20 = 20; + localparam th_ctrl_21 = 21; + localparam th_ctrl_22 = 22; + localparam th_ctrl_23 = 23; + localparam th_ctrl_24 = 24; + localparam th_ctrl_25 = 25; + localparam th_ctrl_26 = 26; + localparam th_ctrl_27 = 27; + localparam th_ctrl_28 = 28; + localparam th_ctrl_29 = 29; + localparam th_ctrl_30 = 30; + localparam th_ctrl_31 = 31; + localparam th_ctrl_32 = 32; + localparam th_ctrl_33 = 33; + localparam th_ctrl_34 = 34; + localparam th_ctrl_35 = 35; + localparam th_ctrl_36 = 36; + + always @(posedge CLK) begin + if(RST) begin + th_ctrl <= th_ctrl_init; + _th_ctrl_i_12 <= 0; + _th_ctrl_awaddr_13 <= 0; + _th_ctrl_src_offset_14 <= 0; + _th_ctrl_dst_offset_15 <= 0; + _th_ctrl_start_time_16 <= 0; + _th_ctrl_araddr_17 <= 0; + _tmp_13 <= 0; + _th_ctrl_v_18 <= 0; + _tmp_14 <= 0; + _th_ctrl_end_time_19 <= 0; + _th_ctrl_time_20 <= 0; + end else begin + case(th_ctrl) + th_ctrl_init: begin + th_ctrl <= th_ctrl_1; + end + th_ctrl_1: begin + _th_ctrl_i_12 <= 0; + th_ctrl <= th_ctrl_2; + end + th_ctrl_2: begin + if(_th_ctrl_i_12 < 100) begin + th_ctrl <= th_ctrl_3; + end else begin + th_ctrl <= th_ctrl_4; + end + end + th_ctrl_3: begin + _th_ctrl_i_12 <= _th_ctrl_i_12 + 1; + th_ctrl <= th_ctrl_2; + end + th_ctrl_4: begin + _th_ctrl_awaddr_13 <= 4; + th_ctrl <= th_ctrl_5; + end + th_ctrl_5: begin + $display("# copy_bytes = %d", 4096); + th_ctrl <= th_ctrl_6; + end + th_ctrl_6: begin + if(_saxi_awready || !_saxi_awvalid) begin + th_ctrl <= th_ctrl_7; + end + end + th_ctrl_7: begin + if(_saxi_wready || !_saxi_wvalid) begin + th_ctrl <= th_ctrl_8; + end + end + th_ctrl_8: begin + _th_ctrl_awaddr_13 <= 8; + th_ctrl <= th_ctrl_9; + end + th_ctrl_9: begin + _th_ctrl_src_offset_14 <= 0; + th_ctrl <= th_ctrl_10; + end + th_ctrl_10: begin + $display("# src_offset = %d", _th_ctrl_src_offset_14); + th_ctrl <= th_ctrl_11; + end + th_ctrl_11: begin + if(_saxi_awready || !_saxi_awvalid) begin + th_ctrl <= th_ctrl_12; + end + end + th_ctrl_12: begin + if(_saxi_wready || !_saxi_wvalid) begin + th_ctrl <= th_ctrl_13; + end + end + th_ctrl_13: begin + _th_ctrl_awaddr_13 <= 12; + th_ctrl <= th_ctrl_14; + end + th_ctrl_14: begin + _th_ctrl_dst_offset_15 <= 8192; + th_ctrl <= th_ctrl_15; + end + th_ctrl_15: begin + $display("# dst_offset = %d", _th_ctrl_dst_offset_15); + th_ctrl <= th_ctrl_16; + end + th_ctrl_16: begin + if(_saxi_awready || !_saxi_awvalid) begin + th_ctrl <= th_ctrl_17; + end + end + th_ctrl_17: begin + if(_saxi_wready || !_saxi_wvalid) begin + th_ctrl <= th_ctrl_18; + end + end + th_ctrl_18: begin + _th_ctrl_awaddr_13 <= 0; + th_ctrl <= th_ctrl_19; + end + th_ctrl_19: begin + _th_ctrl_start_time_16 <= counter; + th_ctrl <= th_ctrl_20; + end + th_ctrl_20: begin + $display("# start time = %d", _th_ctrl_start_time_16); + th_ctrl <= th_ctrl_21; + end + th_ctrl_21: begin + if(_saxi_awready || !_saxi_awvalid) begin + th_ctrl <= th_ctrl_22; + end + end + th_ctrl_22: begin + if(_saxi_wready || !_saxi_wvalid) begin + th_ctrl <= th_ctrl_23; + end + end + th_ctrl_23: begin + _th_ctrl_araddr_17 <= 16; + th_ctrl <= th_ctrl_24; + end + th_ctrl_24: begin + if(_saxi_arready || !_saxi_arvalid) begin + th_ctrl <= th_ctrl_25; + end + end + th_ctrl_25: begin + if(_saxi_rready && _saxi_rvalid) begin + _tmp_13 <= _saxi_rdata; + end + if(_saxi_rready && _saxi_rvalid) begin + th_ctrl <= th_ctrl_26; + end + end + th_ctrl_26: begin + _th_ctrl_v_18 <= _tmp_13; + th_ctrl <= th_ctrl_27; + end + th_ctrl_27: begin + if(_th_ctrl_v_18 == 0) begin + th_ctrl <= th_ctrl_28; + end else begin + th_ctrl <= th_ctrl_32; + end + end + th_ctrl_28: begin + if(_saxi_arready || !_saxi_arvalid) begin + th_ctrl <= th_ctrl_29; + end + end + th_ctrl_29: begin + if(_saxi_rready && _saxi_rvalid) begin + _tmp_14 <= _saxi_rdata; + end + if(_saxi_rready && _saxi_rvalid) begin + th_ctrl <= th_ctrl_30; + end + end + th_ctrl_30: begin + _th_ctrl_v_18 <= _tmp_14; + th_ctrl <= th_ctrl_31; + end + th_ctrl_31: begin + th_ctrl <= th_ctrl_27; + end + th_ctrl_32: begin + _th_ctrl_end_time_19 <= counter; + th_ctrl <= th_ctrl_33; + end + th_ctrl_33: begin + $display("# end time = %d", _th_ctrl_end_time_19); + th_ctrl <= th_ctrl_34; + end + th_ctrl_34: begin + _th_ctrl_time_20 <= _th_ctrl_end_time_19 - _th_ctrl_start_time_16; + th_ctrl <= th_ctrl_35; + end + th_ctrl_35: begin + $display("# exec time = %d", _th_ctrl_time_20); + th_ctrl <= th_ctrl_36; + end + endcase + end + end + + +endmodule + + + +module blinkled # +( + parameter DATA_WIDTH = 32, + parameter ADDR_WIDTH = 10 +) +( + input CLK, + input RST, + output reg [8-1:0] led, + output reg [32-1:0] maxi_awaddr, + output reg [8-1:0] maxi_awlen, + output reg maxi_awvalid, + input maxi_awready, + output reg [32-1:0] maxi_wdata, + output reg [4-1:0] maxi_wstrb, + output reg maxi_wlast, + output reg maxi_wvalid, + input maxi_wready, + output reg [32-1:0] maxi_araddr, + output reg [8-1:0] maxi_arlen, + output reg maxi_arvalid, + input maxi_arready, + input [32-1:0] maxi_rdata, + input maxi_rlast, + input maxi_rvalid, + output maxi_rready, + input [32-1:0] saxi_awaddr, + input saxi_awvalid, + output saxi_awready, + input [32-1:0] saxi_wdata, + input [4-1:0] saxi_wstrb, + input saxi_wvalid, + output saxi_wready, + input [32-1:0] saxi_araddr, + input saxi_arvalid, + output saxi_arready, + output reg [32-1:0] saxi_rdata, + output reg saxi_rvalid, + input saxi_rready +); + + reg [10-1:0] ram_a_0_addr; + wire [32-1:0] ram_a_0_rdata; + reg [32-1:0] ram_a_0_wdata; + reg ram_a_0_wenable; + reg [10-1:0] ram_a_1_addr; + wire [32-1:0] ram_a_1_rdata; + reg [32-1:0] ram_a_1_wdata; + reg ram_a_1_wenable; + + ram_a + inst_ram_a + ( + .CLK(CLK), + .ram_a_0_addr(ram_a_0_addr), + .ram_a_0_rdata(ram_a_0_rdata), + .ram_a_0_wdata(ram_a_0_wdata), + .ram_a_0_wenable(ram_a_0_wenable), + .ram_a_1_addr(ram_a_1_addr), + .ram_a_1_rdata(ram_a_1_rdata), + .ram_a_1_wdata(ram_a_1_wdata), + .ram_a_1_wenable(ram_a_1_wenable) + ); + + reg [32-1:0] _saxi_register_0; + reg [32-1:0] _saxi_register_1; + reg [32-1:0] _saxi_register_2; + reg [32-1:0] _saxi_register_3; + reg [32-1:0] _saxi_register_4; + reg [32-1:0] _saxi_register_5; + reg [32-1:0] _saxi_register_6; + reg [32-1:0] _saxi_register_7; + reg _saxi_flag_0; + reg _saxi_flag_1; + reg _saxi_flag_2; + reg _saxi_flag_3; + reg _saxi_flag_4; + reg _saxi_flag_5; + reg _saxi_flag_6; + reg _saxi_flag_7; + reg [32-1:0] _saxi_resetval_0; + reg [32-1:0] _saxi_resetval_1; + reg [32-1:0] _saxi_resetval_2; + reg [32-1:0] _saxi_resetval_3; + reg [32-1:0] _saxi_resetval_4; + reg [32-1:0] _saxi_resetval_5; + reg [32-1:0] _saxi_resetval_6; + reg [32-1:0] _saxi_resetval_7; + localparam _saxi_maskwidth = 3; + localparam _saxi_mask = { _saxi_maskwidth{ 1'd1 } }; + localparam _saxi_shift = 2; + reg [32-1:0] _saxi_register_fsm; + localparam _saxi_register_fsm_init = 0; + reg [32-1:0] _tmp_0; + reg _tmp_1; + reg _tmp_2; + reg _tmp_3; + reg _tmp_4; + assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && _tmp_3; + assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4; + reg [_saxi_maskwidth-1:0] _tmp_5; + wire [32-1:0] _tmp_6; + assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 : + (_tmp_5 == 1)? _saxi_register_1 : + (_tmp_5 == 2)? _saxi_register_2 : + (_tmp_5 == 3)? _saxi_register_3 : + (_tmp_5 == 4)? _saxi_register_4 : + (_tmp_5 == 5)? _saxi_register_5 : + (_tmp_5 == 6)? _saxi_register_6 : + (_tmp_5 == 7)? _saxi_register_7 : 'hx; + wire _tmp_7; + assign _tmp_7 = (_tmp_5 == 0)? _saxi_flag_0 : + (_tmp_5 == 1)? _saxi_flag_1 : + (_tmp_5 == 2)? _saxi_flag_2 : + (_tmp_5 == 3)? _saxi_flag_3 : + (_tmp_5 == 4)? _saxi_flag_4 : + (_tmp_5 == 5)? _saxi_flag_5 : + (_tmp_5 == 6)? _saxi_flag_6 : + (_tmp_5 == 7)? _saxi_flag_7 : 'hx; + wire [32-1:0] _tmp_8; + assign _tmp_8 = (_tmp_5 == 0)? _saxi_resetval_0 : + (_tmp_5 == 1)? _saxi_resetval_1 : + (_tmp_5 == 2)? _saxi_resetval_2 : + (_tmp_5 == 3)? _saxi_resetval_3 : + (_tmp_5 == 4)? _saxi_resetval_4 : + (_tmp_5 == 5)? _saxi_resetval_5 : + (_tmp_5 == 6)? _saxi_resetval_6 : + (_tmp_5 == 7)? _saxi_resetval_7 : 'hx; + reg _saxi_cond_0_1; + assign saxi_wready = _saxi_register_fsm == 2; + wire pe_start; + wire pe_busy; + wire [ADDR_WIDTH-1+1-1:0] pe_size; + wire [ADDR_WIDTH-1+1-1:0] pe_addr; + wire [DATA_WIDTH-1+1-1:0] pe_rdata; + wire [DATA_WIDTH-1+1-1:0] pe_wdata; + wire pe_wenable; + + processing_unit + #( + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH) + ) + inst_pe + ( + .CLK(CLK), + .RST(RST), + .start(pe_start), + .busy(pe_busy), + .size(pe_size), + .addr(pe_addr), + .rdata(pe_rdata), + .wdata(pe_wdata), + .wenable(pe_wenable) + ); + + wire [10-1:0] _tmp_9; + assign _tmp_9 = pe_addr; + + always @(*) begin + ram_a_1_addr = _tmp_9; + end + + wire [32-1:0] _tmp_10; + assign _tmp_10 = pe_wdata; + + always @(*) begin + ram_a_1_wdata = _tmp_10; + end + + wire _tmp_11; + assign _tmp_11 = pe_wenable; + + always @(*) begin + ram_a_1_wenable = _tmp_11; + end + + assign pe_rdata = ram_a_1_rdata; + reg start; + wire busy; + reg [ADDR_WIDTH-1:0] size; + assign pe_start = start; + assign pe_size = size; + assign busy = pe_busy; + reg [32-1:0] th_memcpy; + localparam th_memcpy_init = 0; + reg signed [32-1:0] _th_memcpy_copy_bytes_0; + reg signed [32-1:0] _th_memcpy_src_offset_1; + reg signed [32-1:0] _th_memcpy_dst_offset_2; + reg signed [32-1:0] _th_memcpy_copy_bytes_3; + reg signed [32-1:0] _th_memcpy_src_offset_4; + reg signed [32-1:0] _th_memcpy_dst_offset_5; + reg signed [32-1:0] _th_memcpy_rest_words_6; + reg signed [32-1:0] _th_memcpy_src_global_addr_7; + reg signed [32-1:0] _th_memcpy_dst_global_addr_8; + reg signed [32-1:0] _th_memcpy_local_addr_9; + reg signed [32-1:0] _th_memcpy_dma_size_10; + reg [10-1:0] _tmp_12; + reg [32-1:0] _tmp_13; + reg [32-1:0] _tmp_14; + reg [32-1:0] _tmp_fsm_0; + localparam _tmp_fsm_0_init = 0; + reg [32-1:0] _tmp_15; + reg [33-1:0] _tmp_16; + reg [33-1:0] _tmp_17; + reg [32-1:0] _tmp_18; + reg _tmp_19; + reg [33-1:0] _tmp_20; + reg _tmp_21; + wire [32-1:0] __variable_data_22; + wire __variable_valid_22; + wire __variable_ready_22; + assign __variable_ready_22 = (_tmp_20 > 0) && !_tmp_21; + reg _ram_a_cond_0_1; + reg [9-1:0] _tmp_23; + reg _maxi_cond_0_1; + assign maxi_rready = _tmp_fsm_0 == 4; + reg [32-1:0] _d1__tmp_fsm_0; + reg __tmp_fsm_0_cond_4_0_1; + reg _tmp_24; + reg __tmp_fsm_0_cond_5_1_1; + reg signed [32-1:0] _th_memcpy_v_11; + reg [10-1:0] _tmp_25; + reg [32-1:0] _tmp_26; + reg [32-1:0] _tmp_27; + reg [32-1:0] _tmp_fsm_1; + localparam _tmp_fsm_1_init = 0; + reg [32-1:0] _tmp_28; + reg [33-1:0] _tmp_29; + reg [33-1:0] _tmp_30; + reg _tmp_31; + reg _tmp_32; + wire _tmp_33; + wire _tmp_34; + assign _tmp_34 = 1; + localparam _tmp_35 = 1; + wire [_tmp_35-1:0] _tmp_36; + assign _tmp_36 = (_tmp_33 || !_tmp_31) && (_tmp_34 || !_tmp_32); + reg [_tmp_35-1:0] __tmp_36_1; + wire [32-1:0] _tmp_37; + reg [32-1:0] __tmp_37_1; + assign _tmp_37 = (__tmp_36_1)? ram_a_0_rdata : __tmp_37_1; + reg _tmp_38; + reg _tmp_39; + reg _tmp_40; + reg _tmp_41; + reg [33-1:0] _tmp_42; + reg [9-1:0] _tmp_43; + reg _maxi_cond_1_1; + reg _tmp_44; + wire [32-1:0] __variable_data_45; + wire __variable_valid_45; + wire __variable_ready_45; + assign __variable_ready_45 = (_tmp_fsm_1 == 4) && ((_tmp_43 > 0) && (maxi_wready || !maxi_wvalid)); + reg _maxi_cond_2_1; + reg _tmp_46; + reg [32-1:0] _d1__tmp_fsm_1; + reg __tmp_fsm_1_cond_5_0_1; + + always @(posedge CLK) begin + if(RST) begin + ram_a_0_addr <= 0; + _tmp_20 <= 0; + ram_a_0_wdata <= 0; + ram_a_0_wenable <= 0; + _tmp_21 <= 0; + _ram_a_cond_0_1 <= 0; + __tmp_36_1 <= 0; + __tmp_37_1 <= 0; + _tmp_41 <= 0; + _tmp_31 <= 0; + _tmp_32 <= 0; + _tmp_39 <= 0; + _tmp_40 <= 0; + _tmp_38 <= 0; + _tmp_42 <= 0; + end else begin + if(_ram_a_cond_0_1) begin + ram_a_0_wenable <= 0; + _tmp_21 <= 0; + end + if((_tmp_fsm_0 == 1) && (_tmp_20 == 0)) begin + ram_a_0_addr <= _tmp_12 - 1; + _tmp_20 <= _tmp_14; + end + if(__variable_valid_22 && ((_tmp_20 > 0) && !_tmp_21) && (_tmp_20 > 0)) begin + ram_a_0_addr <= ram_a_0_addr + 1; + ram_a_0_wdata <= __variable_data_22; + ram_a_0_wenable <= 1; + _tmp_20 <= _tmp_20 - 1; + end + if(__variable_valid_22 && ((_tmp_20 > 0) && !_tmp_21) && (_tmp_20 == 1)) begin + _tmp_21 <= 1; + end + _ram_a_cond_0_1 <= 1; + __tmp_36_1 <= _tmp_36; + __tmp_37_1 <= _tmp_37; + if((_tmp_33 || !_tmp_31) && (_tmp_34 || !_tmp_32) && _tmp_39) begin + _tmp_41 <= 0; + _tmp_31 <= 0; + _tmp_32 <= 0; + _tmp_39 <= 0; + end + if((_tmp_33 || !_tmp_31) && (_tmp_34 || !_tmp_32) && _tmp_38) begin + _tmp_31 <= 1; + _tmp_32 <= 1; + _tmp_41 <= _tmp_40; + _tmp_40 <= 0; + _tmp_38 <= 0; + _tmp_39 <= 1; + end + if((_tmp_fsm_1 == 1) && (_tmp_42 == 0) && !_tmp_40 && !_tmp_41) begin + ram_a_0_addr <= _tmp_25; + _tmp_42 <= _tmp_27 - 1; + _tmp_38 <= 1; + _tmp_40 <= _tmp_27 == 1; + end + if((_tmp_33 || !_tmp_31) && (_tmp_34 || !_tmp_32) && (_tmp_42 > 0)) begin + ram_a_0_addr <= ram_a_0_addr + 1; + _tmp_42 <= _tmp_42 - 1; + _tmp_38 <= 1; + _tmp_40 <= 0; + end + if((_tmp_33 || !_tmp_31) && (_tmp_34 || !_tmp_32) && (_tmp_42 == 1)) begin + _tmp_40 <= 1; + end + end + end + + assign __variable_data_45 = _tmp_37; + assign __variable_valid_45 = _tmp_31; + assign _tmp_33 = 1 && __variable_ready_45; + + always @(posedge CLK) begin + if(RST) begin + maxi_araddr <= 0; + maxi_arlen <= 0; + maxi_arvalid <= 0; + _tmp_23 <= 0; + _maxi_cond_0_1 <= 0; + maxi_awaddr <= 0; + maxi_awlen <= 0; + maxi_awvalid <= 0; + _tmp_43 <= 0; + _maxi_cond_1_1 <= 0; + maxi_wdata <= 0; + maxi_wvalid <= 0; + maxi_wlast <= 0; + maxi_wstrb <= 0; + _tmp_44 <= 0; + _maxi_cond_2_1 <= 0; + end else begin + if(_maxi_cond_0_1) begin + maxi_arvalid <= 0; + end + if(_maxi_cond_1_1) begin + maxi_awvalid <= 0; + end + if(_maxi_cond_2_1) begin + maxi_wvalid <= 0; + maxi_wlast <= 0; + _tmp_44 <= 0; + end + if((_tmp_fsm_0 == 3) && ((maxi_arready || !maxi_arvalid) && (_tmp_23 == 0))) begin + maxi_araddr <= _tmp_15; + maxi_arlen <= _tmp_16 - 1; + maxi_arvalid <= 1; + _tmp_23 <= _tmp_16; + end + _maxi_cond_0_1 <= 1; + if(maxi_arvalid && !maxi_arready) begin + maxi_arvalid <= maxi_arvalid; + end + if(maxi_rready && maxi_rvalid && (_tmp_23 > 0)) begin + _tmp_23 <= _tmp_23 - 1; + end + if((_tmp_fsm_1 == 3) && ((maxi_awready || !maxi_awvalid) && (_tmp_43 == 0))) begin + maxi_awaddr <= _tmp_28; + maxi_awlen <= _tmp_29 - 1; + maxi_awvalid <= 1; + _tmp_43 <= _tmp_29; + end + if((_tmp_fsm_1 == 3) && ((maxi_awready || !maxi_awvalid) && (_tmp_43 == 0)) && (_tmp_29 == 0)) begin + maxi_awvalid <= 0; + end + _maxi_cond_1_1 <= 1; + if(maxi_awvalid && !maxi_awready) begin + maxi_awvalid <= maxi_awvalid; + end + if(__variable_valid_45 && ((_tmp_fsm_1 == 4) && ((_tmp_43 > 0) && (maxi_wready || !maxi_wvalid))) && ((_tmp_43 > 0) && (maxi_wready || !maxi_wvalid) && (_tmp_43 > 0))) begin + maxi_wdata <= __variable_data_45; + maxi_wvalid <= 1; + maxi_wlast <= 0; + maxi_wstrb <= { 4{ 1'd1 } }; + _tmp_43 <= _tmp_43 - 1; + end + if(__variable_valid_45 && ((_tmp_fsm_1 == 4) && ((_tmp_43 > 0) && (maxi_wready || !maxi_wvalid))) && ((_tmp_43 > 0) && (maxi_wready || !maxi_wvalid) && (_tmp_43 > 0)) && (_tmp_43 == 1)) begin + maxi_wlast <= 1; + _tmp_44 <= 1; + end + _maxi_cond_2_1 <= 1; + if(maxi_wvalid && !maxi_wready) begin + maxi_wvalid <= maxi_wvalid; + maxi_wlast <= maxi_wlast; + _tmp_44 <= _tmp_44; + end + end + end + + assign __variable_data_22 = _tmp_18; + assign __variable_valid_22 = _tmp_19; + + always @(posedge CLK) begin + if(RST) begin + _tmp_3 <= 0; + _tmp_4 <= 0; + _tmp_1 <= 0; + _tmp_2 <= 0; + _tmp_0 <= 0; + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_cond_0_1 <= 0; + _saxi_register_0 <= 0; + _saxi_flag_0 <= 0; + _saxi_register_1 <= 0; + _saxi_flag_1 <= 0; + _saxi_register_2 <= 0; + _saxi_flag_2 <= 0; + _saxi_register_3 <= 0; + _saxi_flag_3 <= 0; + _saxi_register_4 <= 0; + _saxi_flag_4 <= 0; + _saxi_register_5 <= 0; + _saxi_flag_5 <= 0; + _saxi_register_6 <= 0; + _saxi_flag_6 <= 0; + _saxi_register_7 <= 0; + _saxi_flag_7 <= 0; + _saxi_resetval_0 <= 0; + _saxi_resetval_1 <= 0; + _saxi_resetval_2 <= 0; + _saxi_resetval_3 <= 0; + _saxi_resetval_4 <= 0; + _saxi_resetval_5 <= 0; + _saxi_resetval_6 <= 0; + _saxi_resetval_7 <= 0; + end else begin + if(_saxi_cond_0_1) begin + saxi_rvalid <= 0; + end + _tmp_3 <= saxi_awvalid; + _tmp_4 <= saxi_arvalid; + _tmp_1 <= 0; + _tmp_2 <= 0; + if(saxi_awready && saxi_awvalid) begin + _tmp_0 <= saxi_awaddr; + _tmp_1 <= 1; + end else if(saxi_arready && saxi_arvalid) begin + _tmp_0 <= saxi_araddr; + _tmp_2 <= 1; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= _tmp_6; + saxi_rvalid <= 1; + end + _saxi_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 0)) begin + _saxi_register_0 <= _tmp_8; + _saxi_flag_0 <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 1)) begin + _saxi_register_1 <= _tmp_8; + _saxi_flag_1 <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 2)) begin + _saxi_register_2 <= _tmp_8; + _saxi_flag_2 <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 3)) begin + _saxi_register_3 <= _tmp_8; + _saxi_flag_3 <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 4)) begin + _saxi_register_4 <= _tmp_8; + _saxi_flag_4 <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 5)) begin + _saxi_register_5 <= _tmp_8; + _saxi_flag_5 <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 6)) begin + _saxi_register_6 <= _tmp_8; + _saxi_flag_6 <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && _tmp_7 && (_tmp_5 == 7)) begin + _saxi_register_7 <= _tmp_8; + _saxi_flag_7 <= 0; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin + _saxi_register_0 <= saxi_wdata; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin + _saxi_register_1 <= saxi_wdata; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin + _saxi_register_2 <= saxi_wdata; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin + _saxi_register_3 <= saxi_wdata; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin + _saxi_register_4 <= saxi_wdata; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin + _saxi_register_5 <= saxi_wdata; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin + _saxi_register_6 <= saxi_wdata; + end + if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin + _saxi_register_7 <= saxi_wdata; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 0)) begin + _saxi_register_0 <= 0; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 1)) begin + _saxi_register_1 <= 0; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 2)) begin + _saxi_register_2 <= 0; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 3)) begin + _saxi_register_3 <= 0; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 4)) begin + _saxi_register_4 <= 0; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 5)) begin + _saxi_register_5 <= 0; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 6)) begin + _saxi_register_6 <= 0; + end + if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 7)) begin + _saxi_register_7 <= 0; + end + if((th_memcpy == 30) && (4 == 0)) begin + _saxi_register_0 <= 1; + _saxi_flag_0 <= 1; + _saxi_resetval_0 <= 0; + end + if((th_memcpy == 30) && (4 == 1)) begin + _saxi_register_1 <= 1; + _saxi_flag_1 <= 1; + _saxi_resetval_1 <= 0; + end + if((th_memcpy == 30) && (4 == 2)) begin + _saxi_register_2 <= 1; + _saxi_flag_2 <= 1; + _saxi_resetval_2 <= 0; + end + if((th_memcpy == 30) && (4 == 3)) begin + _saxi_register_3 <= 1; + _saxi_flag_3 <= 1; + _saxi_resetval_3 <= 0; + end + if((th_memcpy == 30) && (4 == 4)) begin + _saxi_register_4 <= 1; + _saxi_flag_4 <= 1; + _saxi_resetval_4 <= 0; + end + if((th_memcpy == 30) && (4 == 5)) begin + _saxi_register_5 <= 1; + _saxi_flag_5 <= 1; + _saxi_resetval_5 <= 0; + end + if((th_memcpy == 30) && (4 == 6)) begin + _saxi_register_6 <= 1; + _saxi_flag_6 <= 1; + _saxi_resetval_6 <= 0; + end + if((th_memcpy == 30) && (4 == 7)) begin + _saxi_register_7 <= 1; + _saxi_flag_7 <= 1; + _saxi_resetval_7 <= 0; + end + end + end + + localparam _saxi_register_fsm_1 = 1; + localparam _saxi_register_fsm_2 = 2; + + always @(posedge CLK) begin + if(RST) begin + _saxi_register_fsm <= _saxi_register_fsm_init; + end else begin + case(_saxi_register_fsm) + _saxi_register_fsm_init: begin + if(_tmp_2 || _tmp_1) begin + _tmp_5 <= (_tmp_0 >> _saxi_shift) & _saxi_mask; + end + if(_tmp_2) begin + _saxi_register_fsm <= _saxi_register_fsm_1; + end + if(_tmp_1) begin + _saxi_register_fsm <= _saxi_register_fsm_2; + end + end + _saxi_register_fsm_1: begin + if(saxi_rready || !saxi_rvalid) begin + _saxi_register_fsm <= _saxi_register_fsm_init; + end + end + _saxi_register_fsm_2: begin + _saxi_register_fsm <= _saxi_register_fsm_init; + end + endcase + end + end + + localparam th_memcpy_1 = 1; + localparam th_memcpy_2 = 2; + localparam th_memcpy_3 = 3; + localparam th_memcpy_4 = 4; + localparam th_memcpy_5 = 5; + localparam th_memcpy_6 = 6; + localparam th_memcpy_7 = 7; + localparam th_memcpy_8 = 8; + localparam th_memcpy_9 = 9; + localparam th_memcpy_10 = 10; + localparam th_memcpy_11 = 11; + localparam th_memcpy_12 = 12; + localparam th_memcpy_13 = 13; + localparam th_memcpy_14 = 14; + localparam th_memcpy_15 = 15; + localparam th_memcpy_16 = 16; + localparam th_memcpy_17 = 17; + localparam th_memcpy_18 = 18; + localparam th_memcpy_19 = 19; + localparam th_memcpy_20 = 20; + localparam th_memcpy_21 = 21; + localparam th_memcpy_22 = 22; + localparam th_memcpy_23 = 23; + localparam th_memcpy_24 = 24; + localparam th_memcpy_25 = 25; + localparam th_memcpy_26 = 26; + localparam th_memcpy_27 = 27; + localparam th_memcpy_28 = 28; + localparam th_memcpy_29 = 29; + localparam th_memcpy_30 = 30; + localparam th_memcpy_31 = 31; + localparam th_memcpy_32 = 32; + + always @(posedge CLK) begin + if(RST) begin + th_memcpy <= th_memcpy_init; + _th_memcpy_copy_bytes_0 <= 0; + _th_memcpy_src_offset_1 <= 0; + _th_memcpy_dst_offset_2 <= 0; + _th_memcpy_copy_bytes_3 <= 0; + _th_memcpy_src_offset_4 <= 0; + _th_memcpy_dst_offset_5 <= 0; + _th_memcpy_rest_words_6 <= 0; + _th_memcpy_src_global_addr_7 <= 0; + _th_memcpy_dst_global_addr_8 <= 0; + _th_memcpy_local_addr_9 <= 0; + _th_memcpy_dma_size_10 <= 0; + _tmp_12 <= 0; + _tmp_13 <= 0; + _tmp_14 <= 0; + _th_memcpy_v_11 <= 0; + size <= 0; + start <= 0; + _tmp_25 <= 0; + _tmp_26 <= 0; + _tmp_27 <= 0; + end else begin + case(th_memcpy) + th_memcpy_init: begin + th_memcpy <= th_memcpy_1; + end + th_memcpy_1: begin + if(1) begin + th_memcpy <= th_memcpy_2; + end else begin + th_memcpy <= th_memcpy_32; + end + end + th_memcpy_2: begin + if(_saxi_register_0 == 1) begin + th_memcpy <= th_memcpy_3; + end + end + th_memcpy_3: begin + _th_memcpy_copy_bytes_0 <= _saxi_register_1; + th_memcpy <= th_memcpy_4; + end + th_memcpy_4: begin + _th_memcpy_src_offset_1 <= _saxi_register_2; + th_memcpy <= th_memcpy_5; + end + th_memcpy_5: begin + _th_memcpy_dst_offset_2 <= _saxi_register_3; + th_memcpy <= th_memcpy_6; + end + th_memcpy_6: begin + _th_memcpy_copy_bytes_3 <= _th_memcpy_copy_bytes_0; + _th_memcpy_src_offset_4 <= _th_memcpy_src_offset_1; + _th_memcpy_dst_offset_5 <= _th_memcpy_dst_offset_2; + th_memcpy <= th_memcpy_7; + end + th_memcpy_7: begin + _th_memcpy_rest_words_6 <= _th_memcpy_copy_bytes_3 / (DATA_WIDTH >>> 3); + th_memcpy <= th_memcpy_8; + end + th_memcpy_8: begin + _th_memcpy_src_global_addr_7 <= _th_memcpy_src_offset_4; + th_memcpy <= th_memcpy_9; + end + th_memcpy_9: begin + _th_memcpy_dst_global_addr_8 <= _th_memcpy_dst_offset_5; + th_memcpy <= th_memcpy_10; + end + th_memcpy_10: begin + _th_memcpy_local_addr_9 <= 0; + th_memcpy <= th_memcpy_11; + end + th_memcpy_11: begin + if(_th_memcpy_rest_words_6 > 0) begin + th_memcpy <= th_memcpy_12; + end else begin + th_memcpy <= th_memcpy_30; + end + end + th_memcpy_12: begin + if(_th_memcpy_rest_words_6 > 256) begin + th_memcpy <= th_memcpy_13; + end else begin + th_memcpy <= th_memcpy_15; + end + end + th_memcpy_13: begin + _th_memcpy_dma_size_10 <= 256; + th_memcpy <= th_memcpy_14; + end + th_memcpy_14: begin + th_memcpy <= th_memcpy_16; + end + th_memcpy_15: begin + _th_memcpy_dma_size_10 <= _th_memcpy_rest_words_6; + th_memcpy <= th_memcpy_16; + end + th_memcpy_16: begin + _tmp_12 <= _th_memcpy_local_addr_9; + _tmp_13 <= _th_memcpy_src_global_addr_7; + _tmp_14 <= _th_memcpy_dma_size_10; + th_memcpy <= th_memcpy_17; + end + th_memcpy_17: begin + if(_tmp_24) begin + th_memcpy <= th_memcpy_18; + end + end + th_memcpy_18: begin + _th_memcpy_v_11 <= _th_memcpy_dma_size_10; + th_memcpy <= th_memcpy_19; + end + th_memcpy_19: begin + size <= _th_memcpy_v_11; + th_memcpy <= th_memcpy_20; + end + th_memcpy_20: begin + start <= 1; + th_memcpy <= th_memcpy_21; + end + th_memcpy_21: begin + start <= 0; + th_memcpy <= th_memcpy_22; + end + th_memcpy_22: begin + if(busy) begin + th_memcpy <= th_memcpy_23; + end else begin + th_memcpy <= th_memcpy_24; + end + end + th_memcpy_23: begin + th_memcpy <= th_memcpy_22; + end + th_memcpy_24: begin + _tmp_25 <= _th_memcpy_local_addr_9; + _tmp_26 <= _th_memcpy_dst_global_addr_8; + _tmp_27 <= _th_memcpy_dma_size_10; + th_memcpy <= th_memcpy_25; + end + th_memcpy_25: begin + if(_tmp_46) begin + th_memcpy <= th_memcpy_26; + end + end + th_memcpy_26: begin + _th_memcpy_src_global_addr_7 <= _th_memcpy_src_global_addr_7 + _th_memcpy_dma_size_10 * (DATA_WIDTH >>> 3); + th_memcpy <= th_memcpy_27; + end + th_memcpy_27: begin + _th_memcpy_dst_global_addr_8 <= _th_memcpy_dst_global_addr_8 + _th_memcpy_dma_size_10 * (DATA_WIDTH >>> 3); + th_memcpy <= th_memcpy_28; + end + th_memcpy_28: begin + _th_memcpy_rest_words_6 <= _th_memcpy_rest_words_6 - _th_memcpy_dma_size_10; + th_memcpy <= th_memcpy_29; + end + th_memcpy_29: begin + th_memcpy <= th_memcpy_11; + end + th_memcpy_30: begin + th_memcpy <= th_memcpy_31; + end + th_memcpy_31: begin + th_memcpy <= th_memcpy_1; + end + endcase + end + end + + localparam _tmp_fsm_0_1 = 1; + localparam _tmp_fsm_0_2 = 2; + localparam _tmp_fsm_0_3 = 3; + localparam _tmp_fsm_0_4 = 4; + localparam _tmp_fsm_0_5 = 5; + localparam _tmp_fsm_0_6 = 6; + + always @(posedge CLK) begin + if(RST) begin + _tmp_fsm_0 <= _tmp_fsm_0_init; + _d1__tmp_fsm_0 <= _tmp_fsm_0_init; + _tmp_15 <= 0; + _tmp_17 <= 0; + _tmp_16 <= 0; + __tmp_fsm_0_cond_4_0_1 <= 0; + _tmp_19 <= 0; + _tmp_18 <= 0; + _tmp_24 <= 0; + __tmp_fsm_0_cond_5_1_1 <= 0; + end else begin + _d1__tmp_fsm_0 <= _tmp_fsm_0; + case(_d1__tmp_fsm_0) + _tmp_fsm_0_4: begin + if(__tmp_fsm_0_cond_4_0_1) begin + _tmp_19 <= 0; + end + end + _tmp_fsm_0_5: begin + if(__tmp_fsm_0_cond_5_1_1) begin + _tmp_24 <= 0; + end + end + endcase + case(_tmp_fsm_0) + _tmp_fsm_0_init: begin + if(th_memcpy == 17) begin + _tmp_fsm_0 <= _tmp_fsm_0_1; + end + end + _tmp_fsm_0_1: begin + _tmp_15 <= (_tmp_13 >> 2) << 2; + _tmp_17 <= _tmp_14; + _tmp_fsm_0 <= _tmp_fsm_0_2; + end + _tmp_fsm_0_2: begin + if((_tmp_17 <= 256) && ((_tmp_15 & 4095) + (_tmp_17 << 2) >= 4096)) begin + _tmp_16 <= 4096 - (_tmp_15 & 4095) >> 2; + _tmp_17 <= _tmp_17 - (4096 - (_tmp_15 & 4095) >> 2); + end else if(_tmp_17 <= 256) begin + _tmp_16 <= _tmp_17; + _tmp_17 <= 0; + end else if((_tmp_15 & 4095) + 1024 >= 4096) begin + _tmp_16 <= 4096 - (_tmp_15 & 4095) >> 2; + _tmp_17 <= _tmp_17 - (4096 - (_tmp_15 & 4095) >> 2); + end else begin + _tmp_16 <= 256; + _tmp_17 <= _tmp_17 - 256; + end + _tmp_fsm_0 <= _tmp_fsm_0_3; + end + _tmp_fsm_0_3: begin + if(maxi_arready || !maxi_arvalid) begin + _tmp_fsm_0 <= _tmp_fsm_0_4; + end + end + _tmp_fsm_0_4: begin + __tmp_fsm_0_cond_4_0_1 <= 1; + if(maxi_rready && maxi_rvalid) begin + _tmp_18 <= maxi_rdata; + _tmp_19 <= 1; + end + if(maxi_rready && maxi_rvalid && maxi_rlast) begin + _tmp_15 <= _tmp_15 + (_tmp_16 << 2); + end + if(maxi_rready && maxi_rvalid && maxi_rlast && (_tmp_17 > 0)) begin + _tmp_fsm_0 <= _tmp_fsm_0_2; + end + if(maxi_rready && maxi_rvalid && maxi_rlast && (_tmp_17 == 0)) begin + _tmp_fsm_0 <= _tmp_fsm_0_5; + end + end + _tmp_fsm_0_5: begin + _tmp_24 <= 1; + __tmp_fsm_0_cond_5_1_1 <= 1; + _tmp_fsm_0 <= _tmp_fsm_0_6; + end + _tmp_fsm_0_6: begin + _tmp_fsm_0 <= _tmp_fsm_0_init; + end + endcase + end + end + + localparam _tmp_fsm_1_1 = 1; + localparam _tmp_fsm_1_2 = 2; + localparam _tmp_fsm_1_3 = 3; + localparam _tmp_fsm_1_4 = 4; + localparam _tmp_fsm_1_5 = 5; + localparam _tmp_fsm_1_6 = 6; + + always @(posedge CLK) begin + if(RST) begin + _tmp_fsm_1 <= _tmp_fsm_1_init; + _d1__tmp_fsm_1 <= _tmp_fsm_1_init; + _tmp_28 <= 0; + _tmp_30 <= 0; + _tmp_29 <= 0; + _tmp_46 <= 0; + __tmp_fsm_1_cond_5_0_1 <= 0; + end else begin + _d1__tmp_fsm_1 <= _tmp_fsm_1; + case(_d1__tmp_fsm_1) + _tmp_fsm_1_5: begin + if(__tmp_fsm_1_cond_5_0_1) begin + _tmp_46 <= 0; + end + end + endcase + case(_tmp_fsm_1) + _tmp_fsm_1_init: begin + if(th_memcpy == 25) begin + _tmp_fsm_1 <= _tmp_fsm_1_1; + end + end + _tmp_fsm_1_1: begin + _tmp_28 <= (_tmp_26 >> 2) << 2; + _tmp_30 <= _tmp_27; + _tmp_fsm_1 <= _tmp_fsm_1_2; + end + _tmp_fsm_1_2: begin + if((_tmp_30 <= 256) && ((_tmp_28 & 4095) + (_tmp_30 << 2) >= 4096)) begin + _tmp_29 <= 4096 - (_tmp_28 & 4095) >> 2; + _tmp_30 <= _tmp_30 - (4096 - (_tmp_28 & 4095) >> 2); + end else if(_tmp_30 <= 256) begin + _tmp_29 <= _tmp_30; + _tmp_30 <= 0; + end else if((_tmp_28 & 4095) + 1024 >= 4096) begin + _tmp_29 <= 4096 - (_tmp_28 & 4095) >> 2; + _tmp_30 <= _tmp_30 - (4096 - (_tmp_28 & 4095) >> 2); + end else begin + _tmp_29 <= 256; + _tmp_30 <= _tmp_30 - 256; + end + _tmp_fsm_1 <= _tmp_fsm_1_3; + end + _tmp_fsm_1_3: begin + if(maxi_awready || !maxi_awvalid) begin + _tmp_fsm_1 <= _tmp_fsm_1_4; + end + end + _tmp_fsm_1_4: begin + if(_tmp_44 && maxi_wvalid && maxi_wready) begin + _tmp_28 <= _tmp_28 + (_tmp_29 << 2); + end + if(_tmp_44 && maxi_wvalid && maxi_wready && (_tmp_30 > 0)) begin + _tmp_fsm_1 <= _tmp_fsm_1_2; + end + if(_tmp_44 && maxi_wvalid && maxi_wready && (_tmp_30 == 0)) begin + _tmp_fsm_1 <= _tmp_fsm_1_5; + end + end + _tmp_fsm_1_5: begin + _tmp_46 <= 1; + __tmp_fsm_1_cond_5_0_1 <= 1; + _tmp_fsm_1 <= _tmp_fsm_1_6; + end + _tmp_fsm_1_6: begin + _tmp_fsm_1 <= _tmp_fsm_1_init; + end + endcase + end + end + + +endmodule + + + +module ram_a +( + input CLK, + input [10-1:0] ram_a_0_addr, + output [32-1:0] ram_a_0_rdata, + input [32-1:0] ram_a_0_wdata, + input ram_a_0_wenable, + input [10-1:0] ram_a_1_addr, + output [32-1:0] ram_a_1_rdata, + input [32-1:0] ram_a_1_wdata, + input ram_a_1_wenable +); + + reg [10-1:0] ram_a_0_daddr; + reg [10-1:0] ram_a_1_daddr; + reg [32-1:0] mem [0:1024-1]; + + always @(posedge CLK) begin + if(ram_a_0_wenable) begin + mem[ram_a_0_addr] <= ram_a_0_wdata; + end + ram_a_0_daddr <= ram_a_0_addr; + end + + assign ram_a_0_rdata = mem[ram_a_0_daddr]; + + always @(posedge CLK) begin + if(ram_a_1_wenable) begin + mem[ram_a_1_addr] <= ram_a_1_wdata; + end + ram_a_1_daddr <= ram_a_1_addr; + end + + assign ram_a_1_rdata = mem[ram_a_1_daddr]; + +endmodule + + + +module processing_unit # +( + parameter ADDR_WIDTH = 10, + parameter DATA_WIDTH = 32 +) +( + input CLK, + input RST, + input start, + output reg busy, + input [ADDR_WIDTH-1:0] size, + output reg [ADDR_WIDTH-1:0] addr, + input [DATA_WIDTH-1:0] rdata, + output reg [DATA_WIDTH-1:0] wdata, + output reg wenable +); + + reg [ADDR_WIDTH-1:0] count; + reg [DATA_WIDTH-1:0] rdata_buf; + reg [32-1:0] fsm; + localparam fsm_init = 0; + localparam fsm_1 = 1; + localparam fsm_2 = 2; + localparam fsm_3 = 3; + localparam fsm_4 = 4; + localparam fsm_5 = 5; + + always @(posedge CLK) begin + if(RST) begin + fsm <= fsm_init; + addr <= 0; + count <= 0; + busy <= 0; + rdata_buf <= 0; + wdata <= 0; + wenable <= 0; + end else begin + case(fsm) + fsm_init: begin + if(start) begin + addr <= 0; + count <= size; + busy <= 1; + end + if(start) begin + fsm <= fsm_1; + end + end + fsm_1: begin + fsm <= fsm_2; + end + fsm_2: begin + rdata_buf <= rdata; + fsm <= fsm_3; + end + fsm_3: begin + wdata <= rdata_buf + 100; + wenable <= 1; + fsm <= fsm_4; + end + fsm_4: begin + wenable <= 0; + addr <= addr + 1; + count <= count - 1; + if(count > 1) begin + fsm <= fsm_1; + end + if(count <= 1) begin + fsm <= fsm_5; + end + end + fsm_5: begin + busy <= 0; + fsm <= fsm_init; + end + endcase + end + end + + +endmodule +""" + + +def test(): + veriloggen.reset() + test_module = thread_myverilog_ipcore.mkTest() + code = test_module.to_verilog() + + from pyverilog.vparser.parser import VerilogParser + from pyverilog.ast_code_generator.codegen import ASTCodeGenerator + parser = VerilogParser() + expected_ast = parser.parse(expected_verilog) + codegen = ASTCodeGenerator() + expected_code = codegen.visit(expected_ast) + + assert(expected_code == code) diff --git a/examples/thread_myverilog_ipcore/thread_myverilog_ipcore.py b/examples/thread_myverilog_ipcore/thread_myverilog_ipcore.py new file mode 100644 index 00000000..434ff2b3 --- /dev/null +++ b/examples/thread_myverilog_ipcore/thread_myverilog_ipcore.py @@ -0,0 +1,322 @@ +from __future__ import absolute_import +from __future__ import print_function +import sys +import os + +# the next line can be removed after installation +sys.path.insert(0, os.path.dirname(os.path.dirname( + os.path.dirname(os.path.abspath(__file__))))) + +from veriloggen import * +import veriloggen.thread as vthread +import veriloggen.types.axi as axi +import veriloggen.types.ipcore as ipcore + +pe_verilog_code = """ +module processing_unit # +( + parameter ADDR_WIDTH = 10, + parameter DATA_WIDTH = 32 +) +( + input CLK, + input RST, + input start, + output reg busy, + input [ADDR_WIDTH-1:0] size, + output reg [ADDR_WIDTH-1:0] addr, + input [DATA_WIDTH-1:0] rdata, + output reg [DATA_WIDTH-1:0] wdata, + output reg wenable +); + + reg [ADDR_WIDTH-1:0] count; + reg [DATA_WIDTH-1:0] rdata_buf; + reg [32-1:0] fsm; + localparam fsm_init = 0; + localparam fsm_1 = 1; + localparam fsm_2 = 2; + localparam fsm_3 = 3; + localparam fsm_4 = 4; + localparam fsm_5 = 5; + + always @(posedge CLK) begin + if(RST) begin + fsm <= fsm_init; + addr <= 0; + count <= 0; + busy <= 0; + rdata_buf <= 0; + wdata <= 0; + wenable <= 0; + end else begin + case(fsm) + fsm_init: begin + if(start) begin + addr <= 0; + count <= size; + busy <= 1; + end + if(start) begin + fsm <= fsm_1; + end + end + fsm_1: begin + fsm <= fsm_2; + end + fsm_2: begin + rdata_buf <= rdata; + fsm <= fsm_3; + end + fsm_3: begin + wdata <= rdata_buf + 100; + wenable <= 1; + fsm <= fsm_4; + end + fsm_4: begin + wenable <= 0; + addr <= addr + 1; + count <= count - 1; + if(count > 1) begin + fsm <= fsm_1; + end + if(count <= 1) begin + fsm <= fsm_5; + end + end + fsm_5: begin + busy <= 0; + fsm <= fsm_init; + end + endcase + end + end + + +endmodule +""" + + +def mkMemcpy(): + m = Module('blinkled') + clk = m.Input('CLK') + rst = m.Input('RST') + led = m.OutputReg('led', 8, initval=0) + + datawidth = 32 + addrwidth = 10 + ram_words = (2 ** addrwidth) // (datawidth // 8) + + ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth, numports=2) + maxi = vthread.AXIM(m, 'maxi', clk, rst, datawidth) + saxi = vthread.AXISLiteRegister(m, 'saxi', clk, rst, datawidth, length=8) + + datawidth = m.Parameter('DATA_WIDTH', datawidth) + addrwidth = m.Parameter('ADDR_WIDTH', addrwidth) + + # import verilog submodule + sub = Submodule(m, pe_verilog_code, 'inst_pe', prefix='pe_', + arg_params=(('ADDR_WIDTH', addrwidth), + ('DATA_WIDTH', datawidth)), + arg_ports=(('CLK', clk), ('RST', rst)), + as_wire=('start', 'busy', 'size', + 'addr', 'rdata', 'wdata', 'wenable')) + + # connect ports to RAM + ram_a.connect_rtl(1, sub['addr'], sub['wdata'], + sub['wenable'], sub['rdata']) + + # control ports of submodule + start = m.Reg('start', initval=0) + busy = m.Wire('busy') + size = m.Reg('size', addrwidth, initval=0) + + sub['start'].assign(start) + sub['size'].assign(size) + busy.assign(sub['busy']) + + def control_processing_unit(v): + size.value = v + start.value = 1 + start.value = 0 + while busy: + pass + + def memcpy(): + while True: + saxi.wait_flag(0, value=1, resetvalue=0) + + copy_bytes = saxi.read(1) + src_offset = saxi.read(2) + dst_offset = saxi.read(3) + + copy(copy_bytes, src_offset, dst_offset) + + saxi.write_flag(4, 1, resetvalue=0) + + def copy(copy_bytes, src_offset, dst_offset): + rest_words = copy_bytes // (datawidth // 8) + src_global_addr = src_offset + dst_global_addr = dst_offset + local_addr = 0 + + while rest_words > 0: + if rest_words > ram_words: + dma_size = ram_words + else: + dma_size = rest_words + + maxi.dma_read(ram_a, local_addr, src_global_addr, dma_size) + control_processing_unit(dma_size) + maxi.dma_write(ram_a, local_addr, dst_global_addr, dma_size) + + src_global_addr += dma_size * (datawidth // 8) + dst_global_addr += dma_size * (datawidth // 8) + rest_words -= dma_size + + th = vthread.Thread(m, 'th_memcpy', clk, rst, memcpy) + fsm = th.start() + + return m + + +def mkTest(): + m = Module('test') + + copy_bytes = 1024 * 4 + + # target instance + memcpy = mkMemcpy() + + uut = Submodule(m, memcpy, name='uut') + clk = uut['CLK'] + rst = uut['RST'] + + memory = axi.AxiMemoryModel(m, 'memory', clk, rst) + memory.connect(uut.get_inst_ports(), 'maxi') + + # AXI-Slave controller + _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True) + _saxi.connect(uut.get_inst_ports(), 'saxi') + + # Timer + counter = m.Reg('counter', 32, initval=0) + seq = Seq(m, 'seq', clk, rst) + seq( + counter.inc() + ) + + def ctrl(): + for i in range(100): + pass + + awaddr = 4 * 1 + print('# copy_bytes = %d' % copy_bytes) + _saxi.write(awaddr, copy_bytes) + + awaddr = 4 * 2 + src_offset = 0 + print('# src_offset = %d' % src_offset) + _saxi.write(awaddr, src_offset) + + awaddr = 4 * 3 + dst_offset = 1024 * 8 + print('# dst_offset = %d' % dst_offset) + _saxi.write(awaddr, dst_offset) + + awaddr = 4 * 0 + start_time = counter + print('# start time = %d' % start_time) + _saxi.write(awaddr, 1) + + araddr = 4 * 4 + v = _saxi.read(araddr) + while v == 0: + v = _saxi.read(araddr) + + end_time = counter + print('# end time = %d' % end_time) + time = end_time - start_time + print('# exec time = %d' % time) + + th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl) + fsm = th.start() + + simulation.setup_waveform(m, uut) + simulation.setup_clock(m, clk, hperiod=5) + init = simulation.setup_reset(m, rst, m.make_reset(), period=100) + + init.add( + Delay(1000000), + Systask('finish'), + ) + + return m + + +if __name__ == '__main__': + test = mkTest() + verilog = test.to_verilog('tmp.v') + print(verilog) + + sim = simulation.Simulator(test) + rslt = sim.run() + print(rslt) + + simcode = """ +reg [31:0] counter; +always @(posedge sim_clk) begin + if(!sim_resetn) begin + counter <= 0; + end else begin + counter <= counter + 1; + end +end + +reg [31:0] _start_time; +reg [31:0] _end_time; +reg [31:0] _time; + +reg [31:0] _addr; +reg [31:0] _data; +initial begin + #1000; + _addr = 4; + _data = 1024 * 4; + $display("# copy_bytes = %d", _data); + slave_write_ipgen_slave_lite_memory_saxi_1(_data, _addr); + + _addr = 8; + _data = 0; + $display("# src_offset = %d", _data); + slave_write_ipgen_slave_lite_memory_saxi_1(_data, _addr); + + _addr = 12; + _data = 1024 * 8; + $display("# dst_offset = %d", _data); + slave_write_ipgen_slave_lite_memory_saxi_1(_data, _addr); + + _addr = 0; + _data = 1; + _start_time = counter; + $display("# start time = %d", _start_time); + slave_write_ipgen_slave_lite_memory_saxi_1(_data, _addr); + + _addr = 16; + _data = 0; + while(_data == 0) begin + slave_read_ipgen_slave_lite_memory_saxi_1(_data, _addr); + nclk(); + end + _end_time = counter; + $display("# end time = %d", _end_time); + _time = _end_time - _start_time; + $display("# exec time = %d", _time); + + #10000; + $finish; +end +""" + + m = mkMemcpy() + ipcore.to_ipcore(m, 'myipcore', simcode=simcode, iftype='axi') diff --git a/examples/thread_stream_matmul/test_thread_stream_matmul.py b/examples/thread_stream_matmul/test_thread_stream_matmul.py index cbb2f94f..ea8c92a4 100644 --- a/examples/thread_stream_matmul/test_thread_stream_matmul.py +++ b/examples/thread_stream_matmul/test_thread_stream_matmul.py @@ -602,7 +602,7 @@ reg [2-1:0] _tmp_50; reg _tmp_51; wire _tmp_all_valid_52; - wire [32-1:0] _reduceadd_data_53; + wire signed [32-1:0] _reduceadd_data_53; wire _reduceadd_valid_53; wire _reduceadd_ready_53; assign _reduceadd_ready_53 = (_tmp_50 > 0) && !_tmp_51 && _tmp_all_valid_52; @@ -1070,11 +1070,11 @@ assign __variable_valid_23 = _tmp_20; assign __variable_data_87 = _tmp_83; assign __variable_valid_87 = _tmp_84; - wire [32-1:0] _times_data_92; + wire signed [32-1:0] _times_data_92; wire _times_valid_92; wire _times_ready_92; - wire [64-1:0] _times_odata_92; - reg [64-1:0] _times_data_reg_92; + wire signed [64-1:0] _times_odata_92; + reg signed [64-1:0] _times_data_reg_92; assign _times_data_92 = _times_data_reg_92; wire _times_ovalid_92; reg _times_valid_reg_92; @@ -1099,7 +1099,7 @@ assign _tmp_28 = 1 && ((_times_ready_92 || !_times_valid_92) && (_tmp_26 && _tmp_38)); assign _tmp_40 = 1 && ((_times_ready_92 || !_times_valid_92) && (_tmp_26 && _tmp_38)); - reg [32-1:0] _reduceadd_data_93; + reg signed [32-1:0] _reduceadd_data_93; reg _reduceadd_valid_93; wire _reduceadd_ready_93; reg [33-1:0] _reduceadd_count_93; @@ -2179,15 +2179,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/dataflow_/_iter/dataflow__iter.py b/tests/extension/dataflow_/_iter/dataflow__iter.py index 38db4633..3bbe7189 100644 --- a/tests/extension/dataflow_/_iter/dataflow__iter.py +++ b/tests/extension/dataflow_/_iter/dataflow__iter.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready', width=8) - y = dataflow.Variable('ydata', valid='yvalid', ready='yready', width=8) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', width=8, signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', width=8, signed=False) # dataflow definition bits = [] diff --git a/tests/extension/dataflow_/_slice/dataflow__slice.py b/tests/extension/dataflow_/_slice/dataflow__slice.py index 32924db5..e4216a76 100644 --- a/tests/extension/dataflow_/_slice/dataflow__slice.py +++ b/tests/extension/dataflow_/_slice/dataflow__slice.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/add/dataflow_add.py b/tests/extension/dataflow_/add/dataflow_add.py index 4c1a9616..ed7162fd 100644 --- a/tests/extension/dataflow_/add/dataflow_add.py +++ b/tests/extension/dataflow_/add/dataflow_add.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/add_nocontrol/dataflow_add_nocontrol.py b/tests/extension/dataflow_/add_nocontrol/dataflow_add_nocontrol.py index e843fe97..9312aae0 100644 --- a/tests/extension/dataflow_/add_nocontrol/dataflow_add_nocontrol.py +++ b/tests/extension/dataflow_/add_nocontrol/dataflow_add_nocontrol.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata') - y = dataflow.Variable('ydata') + x = dataflow.Variable('xdata', signed=False) + y = dataflow.Variable('ydata', signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/add_nostall/dataflow_add_nostall.py b/tests/extension/dataflow_/add_nostall/dataflow_add_nostall.py index 6232436a..81d2cd46 100644 --- a/tests/extension/dataflow_/add_nostall/dataflow_add_nostall.py +++ b/tests/extension/dataflow_/add_nostall/dataflow_add_nostall.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/alias/dataflow_alias.py b/tests/extension/dataflow_/alias/dataflow_alias.py index 0f49de1f..72c7e468 100644 --- a/tests/extension/dataflow_/alias/dataflow_alias.py +++ b/tests/extension/dataflow_/alias/dataflow_alias.py @@ -19,7 +19,7 @@ def mkMain(n=128, datawidth=32, numports=2): rst = m.Input('RST') # original variable - xorig = dataflow.Variable('xdata', 'xvalid', 'xready') + xorig = dataflow.Variable('xdata', 'xvalid', 'xready', signed=False) # connect an exising variable xorig = dataflow.Variable(xorig) x = dataflow.Variable(xorig) diff --git a/tests/extension/dataflow_/average/dataflow_average.py b/tests/extension/dataflow_/average/dataflow_average.py index 8dde7fc3..0b924657 100644 --- a/tests/extension/dataflow_/average/dataflow_average.py +++ b/tests/extension/dataflow_/average/dataflow_average.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition v = x + y diff --git a/tests/extension/dataflow_/connect/dataflow_connect.py b/tests/extension/dataflow_/connect/dataflow_connect.py index fb9d9fa8..266c334f 100644 --- a/tests/extension/dataflow_/connect/dataflow_connect.py +++ b/tests/extension/dataflow_/connect/dataflow_connect.py @@ -18,7 +18,7 @@ def mkMain(n=128, datawidth=32, numports=2): clk = m.Input('CLK') rst = m.Input('RST') - x = dataflow.Variable() + x = dataflow.Variable(signed=False) y = x + 1 z = y + 1 @@ -26,7 +26,7 @@ def mkMain(n=128, datawidth=32, numports=2): z.output('zdata', 'zvalid', 'zready') # source variable - xsrc = dataflow.Variable('xdata', 'xvalid', 'xready') + xsrc = dataflow.Variable('xdata', 'xvalid', 'xready', signed=False) # connect a variable to the variable that has no input_data x.connect(xsrc) diff --git a/tests/extension/dataflow_/custom/dataflow_custom.py b/tests/extension/dataflow_/custom/dataflow_custom.py index 7ee48fbd..b74d79d3 100644 --- a/tests/extension/dataflow_/custom/dataflow_custom.py +++ b/tests/extension/dataflow_/custom/dataflow_custom.py @@ -17,8 +17,8 @@ def add(left, right): def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = dataflow.CustomOp(add, x, y) diff --git a/tests/extension/dataflow_/div/dataflow_div.py b/tests/extension/dataflow_/div/dataflow_div.py index d98041d9..53a52f5d 100644 --- a/tests/extension/dataflow_/div/dataflow_div.py +++ b/tests/extension/dataflow_/div/dataflow_div.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x // 2 + y diff --git a/tests/extension/dataflow_/div_signed/dataflow_div_signed.py b/tests/extension/dataflow_/div_signed/dataflow_div_signed.py index 7cdfa464..dd3196aa 100644 --- a/tests/extension/dataflow_/div_signed/dataflow_div_signed.py +++ b/tests/extension/dataflow_/div_signed/dataflow_div_signed.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=True) - y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=True) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + y = dataflow.Variable('ydata', valid='yvalid', ready='yready') # dataflow definition z = x // 2 + y diff --git a/tests/extension/dataflow_/fixed_add/dataflow_fixed_add.py b/tests/extension/dataflow_/fixed_add/dataflow_fixed_add.py index 84f16fee..4d2cc62e 100644 --- a/tests/extension/dataflow_/fixed_add/dataflow_fixed_add.py +++ b/tests/extension/dataflow_/fixed_add/dataflow_fixed_add.py @@ -14,8 +14,8 @@ def mkMain(point=8): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=point) - y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=point) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=point, signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=point, signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/fixed_add_shift/dataflow_fixed_add_shift.py b/tests/extension/dataflow_/fixed_add_shift/dataflow_fixed_add_shift.py index f286b8f1..0de3586a 100644 --- a/tests/extension/dataflow_/fixed_add_shift/dataflow_fixed_add_shift.py +++ b/tests/extension/dataflow_/fixed_add_shift/dataflow_fixed_add_shift.py @@ -14,8 +14,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=8) - y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=4) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=8, signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=4, signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/fixed_add_shift_signed/dataflow_fixed_add_shift_signed.py b/tests/extension/dataflow_/fixed_add_shift_signed/dataflow_fixed_add_shift_signed.py index fde6f5bc..8522004c 100644 --- a/tests/extension/dataflow_/fixed_add_shift_signed/dataflow_fixed_add_shift_signed.py +++ b/tests/extension/dataflow_/fixed_add_shift_signed/dataflow_fixed_add_shift_signed.py @@ -14,10 +14,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', - ready='xready', point=8, signed=True) - y = dataflow.Variable('ydata', valid='yvalid', - ready='yready', point=4, signed=True) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=8) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=4) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/fixed_mul/dataflow_fixed_mul.py b/tests/extension/dataflow_/fixed_mul/dataflow_fixed_mul.py index 3d2c78de..59fa29dc 100644 --- a/tests/extension/dataflow_/fixed_mul/dataflow_fixed_mul.py +++ b/tests/extension/dataflow_/fixed_mul/dataflow_fixed_mul.py @@ -14,8 +14,8 @@ def mkMain(point=8): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=point) - y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=point) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=point, signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=point, signed=False) # dataflow definition z = x * y diff --git a/tests/extension/dataflow_/fixed_mul_shift/dataflow_fixed_mul_shift.py b/tests/extension/dataflow_/fixed_mul_shift/dataflow_fixed_mul_shift.py index 364790f2..e4341b15 100644 --- a/tests/extension/dataflow_/fixed_mul_shift/dataflow_fixed_mul_shift.py +++ b/tests/extension/dataflow_/fixed_mul_shift/dataflow_fixed_mul_shift.py @@ -14,8 +14,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=8) - y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=4) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=8, signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=4, signed=False) # dataflow definition z = x * y diff --git a/tests/extension/dataflow_/fixed_mul_shift_signed/dataflow_fixed_mul_shift_signed.py b/tests/extension/dataflow_/fixed_mul_shift_signed/dataflow_fixed_mul_shift_signed.py index 590cca31..ff9f1f3b 100644 --- a/tests/extension/dataflow_/fixed_mul_shift_signed/dataflow_fixed_mul_shift_signed.py +++ b/tests/extension/dataflow_/fixed_mul_shift_signed/dataflow_fixed_mul_shift_signed.py @@ -14,10 +14,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', - ready='xready', point=8, signed=True) - y = dataflow.Variable('ydata', valid='yvalid', - ready='yready', point=4, signed=True) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', point=8) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', point=4) # dataflow definition z = x * y diff --git a/tests/extension/dataflow_/getio/dataflow_getio.py b/tests/extension/dataflow_/getio/dataflow_getio.py index 480dc002..087caa73 100644 --- a/tests/extension/dataflow_/getio/dataflow_getio.py +++ b/tests/extension/dataflow_/getio/dataflow_getio.py @@ -19,8 +19,8 @@ def mkMain(n=128, datawidth=32, numports=2): rst = m.Input('RST') # variables - x = dataflow.Variable('xdata', 'xvalid', 'xready') - y = dataflow.Variable('ydata', 'yvalid', 'yready') + x = dataflow.Variable('xdata', 'xvalid', 'xready', signed=False) + y = dataflow.Variable('ydata', 'yvalid', 'yready', signed=False) z = x + y z.output('zdata', 'zvalid', 'zready') diff --git a/tests/extension/dataflow_/graph_add/dataflow_graph_add.py b/tests/extension/dataflow_/graph_add/dataflow_graph_add.py index b8f1b485..c4709112 100644 --- a/tests/extension/dataflow_/graph_add/dataflow_graph_add.py +++ b/tests/extension/dataflow_/graph_add/dataflow_graph_add.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/graph_average/dataflow_graph_average.py b/tests/extension/dataflow_/graph_average/dataflow_graph_average.py index c05b97ed..3ee811fd 100644 --- a/tests/extension/dataflow_/graph_average/dataflow_graph_average.py +++ b/tests/extension/dataflow_/graph_average/dataflow_graph_average.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition v = x + y diff --git a/tests/extension/dataflow_/graph_pass/dataflow_graph_pass.py b/tests/extension/dataflow_/graph_pass/dataflow_graph_pass.py index c2167c38..9bdd74b4 100644 --- a/tests/extension/dataflow_/graph_pass/dataflow_graph_pass.py +++ b/tests/extension/dataflow_/graph_pass/dataflow_graph_pass.py @@ -13,7 +13,7 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition z = x diff --git a/tests/extension/dataflow_/implement_add/dataflow_implement_add.py b/tests/extension/dataflow_/implement_add/dataflow_implement_add.py index 5a6283e4..69b7ed64 100644 --- a/tests/extension/dataflow_/implement_add/dataflow_implement_add.py +++ b/tests/extension/dataflow_/implement_add/dataflow_implement_add.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/implement_embedded/dataflow_implement_embedded.py b/tests/extension/dataflow_/implement_embedded/dataflow_implement_embedded.py index 57d13ed0..e81c20ec 100644 --- a/tests/extension/dataflow_/implement_embedded/dataflow_implement_embedded.py +++ b/tests/extension/dataflow_/implement_embedded/dataflow_implement_embedded.py @@ -30,8 +30,8 @@ def mkMain(): zvalid = m.Output('zvalid') zready = m.Input('zready') - x = dataflow.Variable(xdata, valid=xvalid, ready=xready) - y = dataflow.Variable(ydata, valid=yvalid, ready=yready) + x = dataflow.Variable(xdata, valid=xvalid, ready=xready, signed=False) + y = dataflow.Variable(ydata, valid=yvalid, ready=yready, signed=False) # dataflow definition z = x + y diff --git a/tests/extension/dataflow_/inc/dataflow_inc.py b/tests/extension/dataflow_/inc/dataflow_inc.py index 3aa6b799..515b0489 100644 --- a/tests/extension/dataflow_/inc/dataflow_inc.py +++ b/tests/extension/dataflow_/inc/dataflow_inc.py @@ -13,7 +13,7 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition z = x + 1 diff --git a/tests/extension/dataflow_/loop/dataflow_loop.py b/tests/extension/dataflow_/loop/dataflow_loop.py index a6785b5b..3d8e8c35 100644 --- a/tests/extension/dataflow_/loop/dataflow_loop.py +++ b/tests/extension/dataflow_/loop/dataflow_loop.py @@ -18,8 +18,8 @@ def mkMain(n=128, datawidth=32, numports=2): clk = m.Input('CLK') rst = m.Input('RST') - x = dataflow.Variable('xdata') - y = dataflow.Variable() + x = dataflow.Variable('xdata', signed=False) + y = dataflow.Variable(signed=False) z = x + y y.connect(z) # y <- z <- y loop diff --git a/tests/extension/dataflow_/lut/dataflow_lut.py b/tests/extension/dataflow_/lut/dataflow_lut.py index bbf07b76..2cdfb166 100644 --- a/tests/extension/dataflow_/lut/dataflow_lut.py +++ b/tests/extension/dataflow_/lut/dataflow_lut.py @@ -17,12 +17,12 @@ def add(left, right): def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition patterns = tuple([i * i for i in range(256)]) - lut = dataflow.LUT(x, patterns) + lut = dataflow.LUT(x, patterns, signed=False) z = lut + y # set output attribute diff --git a/tests/extension/dataflow_/madd/dataflow_madd.py b/tests/extension/dataflow_/madd/dataflow_madd.py index 27373dac..d413bc5d 100644 --- a/tests/extension/dataflow_/madd/dataflow_madd.py +++ b/tests/extension/dataflow_/madd/dataflow_madd.py @@ -15,8 +15,7 @@ def mkMain(): # input variiable x = dataflow.Variable('xdata', valid='xvalid', ready='xready') y = dataflow.Variable('ydata', valid='yvalid', ready='yready') - reset = dataflow.Variable( - 'resetdata', valid='resetvalid', ready='resetready') + reset = dataflow.Variable('resetdata', valid='resetvalid', ready='resetready') # dataflow definition v = x * y diff --git a/tests/extension/dataflow_/madd/test_dataflow_madd.py b/tests/extension/dataflow_/madd/test_dataflow_madd.py index 44f3ecde..45911c21 100644 --- a/tests/extension/dataflow_/madd/test_dataflow_madd.py +++ b/tests/extension/dataflow_/madd/test_dataflow_madd.py @@ -8,16 +8,16 @@ reg CLK; reg RST; - reg [32-1:0] xdata; + reg signed [32-1:0] xdata; reg xvalid; wire xready; - reg [32-1:0] ydata; + reg signed [32-1:0] ydata; reg yvalid; wire yready; - reg [32-1:0] resetdata; + reg signed [32-1:0] resetdata; reg resetvalid; wire resetready; - wire [32-1:0] zdata; + wire signed [32-1:0] zdata; wire zvalid; reg zready; @@ -781,25 +781,25 @@ ( input CLK, input RST, - input [32-1:0] xdata, + input signed [32-1:0] xdata, input xvalid, output xready, - input [32-1:0] ydata, + input signed [32-1:0] ydata, input yvalid, output yready, - input [32-1:0] resetdata, + input signed [32-1:0] resetdata, input resetvalid, output resetready, - output [32-1:0] zdata, + output signed [32-1:0] zdata, output zvalid, input zready ); - wire [32-1:0] _times_data_0; + wire signed [32-1:0] _times_data_0; wire _times_valid_0; wire _times_ready_0; - wire [64-1:0] _times_odata_0; - reg [64-1:0] _times_data_reg_0; + wire signed [64-1:0] _times_odata_0; + reg signed [64-1:0] _times_data_reg_0; assign _times_data_0 = _times_data_reg_0; wire _times_ovalid_0; reg _times_valid_reg_0; @@ -824,35 +824,35 @@ assign xready = (_times_ready_0 || !_times_valid_0) && (xvalid && yvalid); assign yready = (_times_ready_0 || !_times_valid_0) && (xvalid && yvalid); - reg [32-1:0] __delay_data_1; + reg signed [32-1:0] __delay_data_1; reg __delay_valid_1; wire __delay_ready_1; assign resetready = (__delay_ready_1 || !__delay_valid_1) && resetvalid; - reg [32-1:0] __delay_data_2; + reg signed [32-1:0] __delay_data_2; reg __delay_valid_2; wire __delay_ready_2; assign __delay_ready_1 = (__delay_ready_2 || !__delay_valid_2) && __delay_valid_1; - reg [32-1:0] __delay_data_3; + reg signed [32-1:0] __delay_data_3; reg __delay_valid_3; wire __delay_ready_3; assign __delay_ready_2 = (__delay_ready_3 || !__delay_valid_3) && __delay_valid_2; - reg [32-1:0] __delay_data_4; + reg signed [32-1:0] __delay_data_4; reg __delay_valid_4; wire __delay_ready_4; assign __delay_ready_3 = (__delay_ready_4 || !__delay_valid_4) && __delay_valid_3; - reg [32-1:0] __delay_data_5; + reg signed [32-1:0] __delay_data_5; reg __delay_valid_5; wire __delay_ready_5; assign __delay_ready_4 = (__delay_ready_5 || !__delay_valid_5) && __delay_valid_4; - reg [32-1:0] __delay_data_6; + reg signed [32-1:0] __delay_data_6; reg __delay_valid_6; wire __delay_ready_6; assign __delay_ready_5 = (__delay_ready_6 || !__delay_valid_6) && __delay_valid_5; - reg [32-1:0] __delay_data_7; + reg signed [32-1:0] __delay_data_7; reg __delay_valid_7; wire __delay_ready_7; assign __delay_ready_6 = (__delay_ready_7 || !__delay_valid_7) && __delay_valid_6; - reg [32-1:0] _reduceadd_data_8; + reg signed [32-1:0] _reduceadd_data_8; reg _reduceadd_valid_8; wire _reduceadd_ready_8; assign _times_ready_0 = (_reduceadd_ready_8 || !_reduceadd_valid_8) && (_times_valid_0 && __delay_valid_7); @@ -1036,15 +1036,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py b/tests/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py index e46b3828..6d7d0949 100644 --- a/tests/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py +++ b/tests/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py @@ -25,10 +25,10 @@ def mkMain(n=128, datawidth=32, numports=2): xdata = m.Reg('xdata', 32, initval=0) xvalid = m.Reg('xvalid', initval=0) xready = m.Wire('xready') - x = df.Variable(xdata, xvalid, xready) + x = df.Variable(xdata, xvalid, xready, signed=False) # input with name - y = df.Variable('ydata', 'yvalid', 'yready') + y = df.Variable('ydata', 'yvalid', 'yready', signed=False) # output a = x + y + 1 diff --git a/tests/extension/dataflow_/mod/dataflow_mod.py b/tests/extension/dataflow_/mod/dataflow_mod.py index 981081bf..b84f5161 100644 --- a/tests/extension/dataflow_/mod/dataflow_mod.py +++ b/tests/extension/dataflow_/mod/dataflow_mod.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x % 4 + y diff --git a/tests/extension/dataflow_/mul/dataflow_mul.py b/tests/extension/dataflow_/mul/dataflow_mul.py index c02c6578..a429062d 100644 --- a/tests/extension/dataflow_/mul/dataflow_mul.py +++ b/tests/extension/dataflow_/mul/dataflow_mul.py @@ -11,8 +11,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = x * y diff --git a/tests/extension/dataflow_/muladd/dataflow_muladd.py b/tests/extension/dataflow_/muladd/dataflow_muladd.py index f63b01b5..1ca688db 100644 --- a/tests/extension/dataflow_/muladd/dataflow_muladd.py +++ b/tests/extension/dataflow_/muladd/dataflow_muladd.py @@ -13,9 +13,9 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') - c = dataflow.Variable('cdata', valid='cvalid', ready='cready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) + c = dataflow.Variable('cdata', valid='cvalid', ready='cready', signed=False) # dataflow definition z = x * y + c diff --git a/tests/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py b/tests/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py index 9a714c7a..54812605 100644 --- a/tests/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py +++ b/tests/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py @@ -19,8 +19,8 @@ def mkMain(n=128, datawidth=32, numports=2): rst = m.Input('RST') # variables - x = dataflow.Variable('xdata', 'xvalid', 'xready') - y = dataflow.Variable('ydata', 'yvalid', 'yready') + x = dataflow.Variable('xdata', 'xvalid', 'xready', signed=False) + y = dataflow.Variable('ydata', 'yvalid', 'yready', signed=False) z = x + y z.output('zdata', 'zvalid', 'zready') diff --git a/tests/extension/dataflow_/mux/dataflow_mux.py b/tests/extension/dataflow_/mux/dataflow_mux.py index 3684ba1f..67cc2542 100644 --- a/tests/extension/dataflow_/mux/dataflow_mux.py +++ b/tests/extension/dataflow_/mux/dataflow_mux.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z = dataflow.Mux(x < y, x, y) diff --git a/tests/extension/dataflow_/mux_const/dataflow_mux_const.py b/tests/extension/dataflow_/mux_const/dataflow_mux_const.py index b80bfdbc..cd3d42b5 100644 --- a/tests/extension/dataflow_/mux_const/dataflow_mux_const.py +++ b/tests/extension/dataflow_/mux_const/dataflow_mux_const.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # Mux with constant condition: only true_value is selected z = dataflow.Mux(1, x + y, x - y) diff --git a/tests/extension/dataflow_/parameter/test_dataflow_parameter.py b/tests/extension/dataflow_/parameter/test_dataflow_parameter.py index f8224b87..794e4e85 100644 --- a/tests/extension/dataflow_/parameter/test_dataflow_parameter.py +++ b/tests/extension/dataflow_/parameter/test_dataflow_parameter.py @@ -7,8 +7,11 @@ module test # ( parameter xparam = 100, - parameter [32-1:0] aparam = 10 - ); + parameter signed [32-1:0] aparam = 10 +) +( + +); reg CLK; reg RST; @@ -57,7 +60,7 @@ module main # ( parameter xparam = 100, - parameter [32-1:0] aparam = 10 + parameter signed [32-1:0] aparam = 10 ) ( input CLK, @@ -65,61 +68,61 @@ ); reg [32-1:0] yparam; - wire [32-1:0] bparam; - wire [32-1:0] vdata; - wire [32-1:0] wdata; - reg [32-1:0] _plus_data_0; + wire signed [32-1:0] bparam; + wire signed [32-1:0] vdata; + wire signed [32-1:0] wdata; + reg signed [32-1:0] _plus_data_0; reg _plus_valid_0; wire _plus_ready_0; - reg [32-1:0] __delay_data_1; + reg signed [32-1:0] __delay_data_1; reg __delay_valid_1; wire __delay_ready_1; - reg [32-1:0] _plus_data_2; + reg signed [32-1:0] _plus_data_2; reg _plus_valid_2; wire _plus_ready_2; assign _plus_ready_0 = (_plus_ready_2 || !_plus_valid_2) && _plus_valid_0; - reg [32-1:0] __delay_data_3; + reg signed [32-1:0] __delay_data_3; reg __delay_valid_3; wire __delay_ready_3; assign __delay_ready_1 = (__delay_ready_3 || !__delay_valid_3) && __delay_valid_1; - reg [32-1:0] _plus_data_4; + reg signed [32-1:0] _plus_data_4; reg _plus_valid_4; wire _plus_ready_4; assign _plus_ready_2 = (_plus_ready_4 || !_plus_valid_4) && _plus_valid_2; - reg [32-1:0] __delay_data_5; + reg signed [32-1:0] __delay_data_5; reg __delay_valid_5; wire __delay_ready_5; assign __delay_ready_3 = (__delay_ready_5 || !__delay_valid_5) && __delay_valid_3; - reg [32-1:0] _plus_data_6; + reg signed [32-1:0] _plus_data_6; reg _plus_valid_6; wire _plus_ready_6; assign _plus_ready_4 = (_plus_ready_6 || !_plus_valid_6) && _plus_valid_4; - reg [32-1:0] __delay_data_7; + reg signed [32-1:0] __delay_data_7; reg __delay_valid_7; wire __delay_ready_7; assign __delay_ready_5 = (__delay_ready_7 || !__delay_valid_7) && __delay_valid_5; - reg [32-1:0] _plus_data_8; + reg signed [32-1:0] _plus_data_8; reg _plus_valid_8; wire _plus_ready_8; assign _plus_ready_6 = (_plus_ready_8 || !_plus_valid_8) && _plus_valid_6; - reg [32-1:0] __delay_data_9; + reg signed [32-1:0] __delay_data_9; reg __delay_valid_9; wire __delay_ready_9; assign __delay_ready_7 = (__delay_ready_9 || !__delay_valid_9) && __delay_valid_7; - reg [32-1:0] _plus_data_10; + reg signed [32-1:0] _plus_data_10; reg _plus_valid_10; wire _plus_ready_10; assign _plus_ready_8 = (_plus_ready_10 || !_plus_valid_10) && _plus_valid_8; - reg [32-1:0] __delay_data_11; + reg signed [32-1:0] __delay_data_11; reg __delay_valid_11; wire __delay_ready_11; assign __delay_ready_9 = (__delay_ready_11 || !__delay_valid_11) && __delay_valid_9; - reg [32-1:0] _plus_data_12; + reg signed [32-1:0] _plus_data_12; reg _plus_valid_12; wire _plus_ready_12; assign _plus_ready_10 = (_plus_ready_12 || !_plus_valid_12) && (_plus_valid_10 && __delay_valid_11); assign __delay_ready_11 = (_plus_ready_12 || !_plus_valid_12) && (_plus_valid_10 && __delay_valid_11); - wire [32-1:0] cdata; + wire signed [32-1:0] cdata; wire cvalid; assign cdata = _plus_data_12; assign cvalid = _plus_valid_12; diff --git a/tests/extension/dataflow_/pass/dataflow_pass.py b/tests/extension/dataflow_/pass/dataflow_pass.py index b9d2e9d9..3842f1b7 100644 --- a/tests/extension/dataflow_/pass/dataflow_pass.py +++ b/tests/extension/dataflow_/pass/dataflow_pass.py @@ -13,7 +13,7 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition z = x diff --git a/tests/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py b/tests/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py index 44726a2e..03cfb234 100644 --- a/tests/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py +++ b/tests/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py @@ -11,7 +11,7 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata') + x = dataflow.Variable('xdata', signed=False) # dataflow definition z = x diff --git a/tests/extension/dataflow_/prev/dataflow_prev.py b/tests/extension/dataflow_/prev/dataflow_prev.py index 8df7f2b9..303449b9 100644 --- a/tests/extension/dataflow_/prev/dataflow_prev.py +++ b/tests/extension/dataflow_/prev/dataflow_prev.py @@ -13,7 +13,7 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition z = x + x.prev(1) + x.prev(2) diff --git a/tests/extension/dataflow_/readwrite/dataflow_readwrite.py b/tests/extension/dataflow_/readwrite/dataflow_readwrite.py index f275ed74..a8279b18 100644 --- a/tests/extension/dataflow_/readwrite/dataflow_readwrite.py +++ b/tests/extension/dataflow_/readwrite/dataflow_readwrite.py @@ -22,10 +22,10 @@ def mkMain(n=128, datawidth=32, numports=2): xdata = m.Reg('xdata', 32, initval=0) xvalid = m.Reg('xvalid', initval=0) xready = m.Wire('xready') - x = dataflow.Variable(xdata, xvalid, xready) + x = dataflow.Variable(xdata, xvalid, xready, signed=False) # default type - y = dataflow.Variable('ydata', 'yvalid', 'yready') + y = dataflow.Variable('ydata', 'yvalid', 'yready', signed=False) z = x + y z.output('zdata', 'zvalid', 'zready') diff --git a/tests/extension/dataflow_/reduceadd/dataflow_reduceadd.py b/tests/extension/dataflow_/reduceadd/dataflow_reduceadd.py index c8607e71..009e5778 100644 --- a/tests/extension/dataflow_/reduceadd/dataflow_reduceadd.py +++ b/tests/extension/dataflow_/reduceadd/dataflow_reduceadd.py @@ -13,10 +13,10 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition - z = dataflow.ReduceAdd(x, initval=0) + z = dataflow.ReduceAdd(x, initval=0, signed=False) # set output attribute z.output('zdata', valid='zvalid', ready='zready') diff --git a/tests/extension/dataflow_/reduceadd_enable/dataflow_reduceadd_enable.py b/tests/extension/dataflow_/reduceadd_enable/dataflow_reduceadd_enable.py index 3fdfb73e..09681d56 100644 --- a/tests/extension/dataflow_/reduceadd_enable/dataflow_reduceadd_enable.py +++ b/tests/extension/dataflow_/reduceadd_enable/dataflow_reduceadd_enable.py @@ -13,14 +13,14 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) reset = dataflow.Variable( - 'resetdata', valid='resetvalid', ready='resetready', width=1) + 'resetdata', valid='resetvalid', ready='resetready', width=1, signed=False) enable = dataflow.Variable( - 'enabledata', valid='enablevalid', ready='enableready', width=1) + 'enabledata', valid='enablevalid', ready='enableready', width=1, signed=False) # dataflow definition - z = dataflow.ReduceAdd(x, initval=0, enable=enable, reset=reset) + z = dataflow.ReduceAdd(x, initval=0, enable=enable, reset=reset, signed=False) # set output attribute z.output('zdata', valid='zvalid', ready='zready') diff --git a/tests/extension/dataflow_/reduceadd_reset/dataflow_reduceadd_reset.py b/tests/extension/dataflow_/reduceadd_reset/dataflow_reduceadd_reset.py index 4a4440d6..ce498c5c 100644 --- a/tests/extension/dataflow_/reduceadd_reset/dataflow_reduceadd_reset.py +++ b/tests/extension/dataflow_/reduceadd_reset/dataflow_reduceadd_reset.py @@ -13,12 +13,12 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) reset = dataflow.Variable( - 'resetdata', valid='resetvalid', ready='resetready', width=1) + 'resetdata', valid='resetvalid', ready='resetready', width=1, signed=False) # dataflow definition - z = dataflow.ReduceAdd(x, initval=0, reset=reset) + z = dataflow.ReduceAdd(x, initval=0, reset=reset, signed=False) # set output attribute z.output('zdata', valid='zvalid', ready='zready') diff --git a/tests/extension/dataflow_/reduceadd_valid/dataflow_reduceadd_valid.py b/tests/extension/dataflow_/reduceadd_valid/dataflow_reduceadd_valid.py index e698713e..bbd6745f 100644 --- a/tests/extension/dataflow_/reduceadd_valid/dataflow_reduceadd_valid.py +++ b/tests/extension/dataflow_/reduceadd_valid/dataflow_reduceadd_valid.py @@ -13,10 +13,10 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition - z, v = dataflow.ReduceAddValid(x * x, size=4, initval=0) + z, v = dataflow.ReduceAddValid(x * x, size=4, initval=0, signed=False) # set output attribute z.output('zdata', valid='zvalid', ready='zready') diff --git a/tests/extension/dataflow_/reduceadd_valid_enable/dataflow_reduceadd_valid_enable.py b/tests/extension/dataflow_/reduceadd_valid_enable/dataflow_reduceadd_valid_enable.py index 2ee91cc4..4c9445e6 100644 --- a/tests/extension/dataflow_/reduceadd_valid_enable/dataflow_reduceadd_valid_enable.py +++ b/tests/extension/dataflow_/reduceadd_valid_enable/dataflow_reduceadd_valid_enable.py @@ -13,15 +13,15 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) reset = dataflow.Variable( - 'resetdata', valid='resetvalid', ready='resetready', width=1) + 'resetdata', valid='resetvalid', ready='resetready', width=1, signed=False) enable = dataflow.Variable( - 'enabledata', valid='enablevalid', ready='enableready', width=1) + 'enabledata', valid='enablevalid', ready='enableready', width=1, signed=False) # dataflow definition z, v = dataflow.ReduceAddValid(x * x, size=4, initval=0, - enable=enable, reset=reset) + enable=enable, reset=reset, signed=False) # set output attribute z.output('zdata', valid='zvalid', ready='zready') diff --git a/tests/extension/dataflow_/reducecustom/dataflow_reducecustom.py b/tests/extension/dataflow_/reducecustom/dataflow_reducecustom.py index 97f8f8d0..47bece5b 100644 --- a/tests/extension/dataflow_/reducecustom/dataflow_reducecustom.py +++ b/tests/extension/dataflow_/reducecustom/dataflow_reducecustom.py @@ -17,10 +17,10 @@ def func_add(left, right): def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition - z = dataflow.ReduceCustom(func_add, x, initval=0) + z = dataflow.ReduceCustom(func_add, x, initval=0, signed=False) # set output attribute z.output('zdata', valid='zvalid', ready='zready') diff --git a/tests/extension/dataflow_/reducemul/dataflow_reducemul.py b/tests/extension/dataflow_/reducemul/dataflow_reducemul.py index 37417d34..a6819f24 100644 --- a/tests/extension/dataflow_/reducemul/dataflow_reducemul.py +++ b/tests/extension/dataflow_/reducemul/dataflow_reducemul.py @@ -13,10 +13,10 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) # dataflow definition - z = dataflow.ReduceMul(x, initval=1) + z = dataflow.ReduceMul(x, initval=1, signed=False) # set output attribute z.output('zdata', valid='zvalid', ready='zready') diff --git a/tests/extension/dataflow_/sign/dataflow_sign.py b/tests/extension/dataflow_/sign/dataflow_sign.py index 66f63d63..8a26e2d9 100644 --- a/tests/extension/dataflow_/sign/dataflow_sign.py +++ b/tests/extension/dataflow_/sign/dataflow_sign.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=True) - y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=True) + x = dataflow.Variable('xdata', valid='xvalid', ready='xready') + y = dataflow.Variable('ydata', valid='yvalid', ready='yready') # dataflow definition z = x - y + dataflow.Constant(5) diff --git a/tests/extension/dataflow_/two_outputs_addsub/dataflow_two_outputs_addsub.py b/tests/extension/dataflow_/two_outputs_addsub/dataflow_two_outputs_addsub.py index 1687a440..cb217110 100644 --- a/tests/extension/dataflow_/two_outputs_addsub/dataflow_two_outputs_addsub.py +++ b/tests/extension/dataflow_/two_outputs_addsub/dataflow_two_outputs_addsub.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z1 = x + y diff --git a/tests/extension/dataflow_/two_outputs_mul/dataflow_two_outputs_mul.py b/tests/extension/dataflow_/two_outputs_mul/dataflow_two_outputs_mul.py index db69878e..193bd117 100644 --- a/tests/extension/dataflow_/two_outputs_mul/dataflow_two_outputs_mul.py +++ b/tests/extension/dataflow_/two_outputs_mul/dataflow_two_outputs_mul.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z1 = x * y diff --git a/tests/extension/dataflow_/unbalanced_outputs/dataflow_unbalanced_outputs.py b/tests/extension/dataflow_/unbalanced_outputs/dataflow_unbalanced_outputs.py index 8e45c024..66e6beaa 100644 --- a/tests/extension/dataflow_/unbalanced_outputs/dataflow_unbalanced_outputs.py +++ b/tests/extension/dataflow_/unbalanced_outputs/dataflow_unbalanced_outputs.py @@ -13,8 +13,8 @@ def mkMain(): # input variiable - x = dataflow.Variable('xdata', valid='xvalid', ready='xready') - y = dataflow.Variable('ydata', valid='yvalid', ready='yready') + x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) + y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=False) # dataflow definition z1 = x + y diff --git a/tests/extension/stream_/add/test_stream_add.py b/tests/extension/stream_/add/test_stream_add.py index a4a74305..67234b94 100644 --- a/tests/extension/stream_/add/test_stream_add.py +++ b/tests/extension/stream_/add/test_stream_add.py @@ -8,9 +8,9 @@ reg CLK; reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; - wire [32-1:0] zdata; + reg signed [32-1:0] xdata; + reg signed [32-1:0] ydata; + wire signed [32-1:0] zdata; main uut @@ -123,12 +123,12 @@ ( input CLK, input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, - output [32-1:0] zdata + input signed [32-1:0] xdata, + input signed [32-1:0] ydata, + output signed [32-1:0] zdata ); - reg [32-1:0] _data_2; + reg signed [32-1:0] _data_2; assign zdata = _data_2; always @(posedge CLK) begin diff --git a/tests/extension/stream_/add_validready/test_stream_add_validready.py b/tests/extension/stream_/add_validready/test_stream_add_validready.py index 950b745f..7fc9ef3b 100644 --- a/tests/extension/stream_/add_validready/test_stream_add_validready.py +++ b/tests/extension/stream_/add_validready/test_stream_add_validready.py @@ -8,13 +8,13 @@ reg CLK; reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; + reg signed [32-1:0] xdata; + reg signed [32-1:0] ydata; reg ivalid; wire iready; wire ovalid; reg oready; - wire [32-1:0] zdata; + wire signed [32-1:0] zdata; main uut @@ -167,13 +167,13 @@ ( input CLK, input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, + input signed [32-1:0] xdata, + input signed [32-1:0] ydata, input ivalid, output iready, output ovalid, input oready, - output [32-1:0] zdata + output signed [32-1:0] zdata ); wire _tmp_0; @@ -181,7 +181,7 @@ reg _ivalid_0; assign ovalid = _ivalid_0; assign iready = _tmp_0; - reg [32-1:0] _data_2; + reg signed [32-1:0] _data_2; assign zdata = _data_2; always @(posedge CLK) begin diff --git a/tests/extension/stream_/iadd/stream_iadd.py b/tests/extension/stream_/iadd/stream_iadd.py deleted file mode 100644 index 7aae814d..00000000 --- a/tests/extension/stream_/iadd/stream_iadd.py +++ /dev/null @@ -1,109 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import sys -import os - -# the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( - os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) - -from veriloggen import * -import veriloggen.stream as stream - - -def mkMain(): - # input variiable - x = stream.Variable('xdata') - y = stream.Variable('ydata') - - # stream definition - z = x + y - z = stream.Iadd(z) - - # set output attribute - z.output('zdata') - - st = stream.Stream(z) - m = st.to_module('main') - - return m - - -def mkTest(numports=8): - m = Module('test') - - # target instance - main = mkMain() - - params = m.copy_params(main) - ports = m.copy_sim_ports(main) - - clk = ports['CLK'] - rst = ports['RST'] - - xdata = ports['xdata'] - ydata = ports['ydata'] - zdata = ports['zdata'] - - uut = m.Instance(main, 'uut', - params=m.connect_params(main), - ports=m.connect_ports(main)) - - reset_done = m.Reg('reset_done', initval=0) - reset_stmt = [] - reset_stmt.append(reset_done(0)) - reset_stmt.append(xdata(0)) - reset_stmt.append(ydata(0)) - - simulation.setup_waveform(m, uut) - simulation.setup_clock(m, clk, hperiod=5) - init = simulation.setup_reset(m, rst, reset_stmt, period=100) - - nclk = simulation.next_clock - - init.add( - Delay(1000), - reset_done(1), - nclk(clk), - Delay(10000), - Systask('finish'), - ) - - send_fsm = FSM(m, 'send_fsm', clk, rst) - send_count = m.Reg('send_count', 32, initval=0) - send_fsm.If(reset_done).goto_next() - send_fsm( - xdata(xdata + 1), - ydata(ydata + 2), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), - send_count.inc() - ) - send_fsm.If(send_count == 20).goto_next() - - recv_fsm = FSM(m, 'recv_fsm', clk, rst) - recv_count = m.Reg('recv_count', 32, initval=0) - recv_fsm.If(reset_done).goto_next() - recv_fsm( - Display('zdata=%d', zdata), - recv_count.inc() - ) - recv_fsm.If(recv_count == 20 + 10).goto_next() - - return m - - -if __name__ == '__main__': - test = mkTest() - verilog = test.to_verilog('tmp.v') - print(verilog) - - # run simulator (Icarus Verilog) - sim = simulation.Simulator(test) - rslt = sim.run() # display=False - #rslt = sim.run(display=True) - print(rslt) - - # launch waveform viewer (GTKwave) - # sim.view_waveform() # background=False - # sim.view_waveform(background=True) diff --git a/tests/extension/stream_/iadd/test_stream_iadd.py b/tests/extension/stream_/iadd/test_stream_iadd.py deleted file mode 100644 index b3bda774..00000000 --- a/tests/extension/stream_/iadd/test_stream_iadd.py +++ /dev/null @@ -1,162 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import veriloggen -import stream_iadd - -expected_verilog = """ -module test; - - reg CLK; - reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; - wire [32-1:0] zdata; - - main - uut - ( - .CLK(CLK), - .RST(RST), - .xdata(xdata), - .ydata(ydata), - .zdata(zdata) - ); - - reg reset_done; - - initial begin - $dumpfile("uut.vcd"); - $dumpvars(0, uut); - end - - - initial begin - CLK = 0; - forever begin - #5 CLK = !CLK; - end - end - - - initial begin - RST = 0; - reset_done = 0; - xdata = 0; - ydata = 0; - #100; - RST = 1; - #100; - RST = 0; - #1000; - reset_done = 1; - @(posedge CLK); - #1; - #10000; - $finish; - end - - reg [32-1:0] send_fsm; - localparam send_fsm_init = 0; - reg [32-1:0] send_count; - reg [32-1:0] recv_fsm; - localparam recv_fsm_init = 0; - reg [32-1:0] recv_count; - localparam send_fsm_1 = 1; - localparam send_fsm_2 = 2; - - always @(posedge CLK) begin - if(RST) begin - send_fsm <= send_fsm_init; - send_count <= 0; - end else begin - case(send_fsm) - send_fsm_init: begin - if(reset_done) begin - send_fsm <= send_fsm_1; - end - end - send_fsm_1: begin - xdata <= xdata + 1; - ydata <= ydata + 2; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); - send_count <= send_count + 1; - if(send_count == 20) begin - send_fsm <= send_fsm_2; - end - end - endcase - end - end - - localparam recv_fsm_1 = 1; - localparam recv_fsm_2 = 2; - - always @(posedge CLK) begin - if(RST) begin - recv_fsm <= recv_fsm_init; - recv_count <= 0; - end else begin - case(recv_fsm) - recv_fsm_init: begin - if(reset_done) begin - recv_fsm <= recv_fsm_1; - end - end - recv_fsm_1: begin - $display("zdata=%d", zdata); - recv_count <= recv_count + 1; - if(recv_count == 30) begin - recv_fsm <= recv_fsm_2; - end - end - endcase - end - end - - -endmodule - - - -module main -( - input CLK, - input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, - output [32-1:0] zdata -); - - reg [32-1:0] _data_2; - reg [32-1:0] _data_4; - assign zdata = _data_4; - - always @(posedge CLK) begin - if(RST) begin - _data_2 <= 0; - _data_4 <= 1'd0; - end else begin - _data_2 <= xdata + ydata; - _data_4 <= _data_4 + _data_2; - end - end - - -endmodule -""" - - -def test(): - veriloggen.reset() - test_module = stream_iadd.mkTest() - code = test_module.to_verilog() - - from pyverilog.vparser.parser import VerilogParser - from pyverilog.ast_code_generator.codegen import ASTCodeGenerator - parser = VerilogParser() - expected_ast = parser.parse(expected_verilog) - codegen = ASTCodeGenerator() - expected_code = codegen.visit(expected_ast) - - assert(expected_code == code) diff --git a/tests/extension/stream_/iadd_ready/stream_iadd_ready.py b/tests/extension/stream_/iadd_ready/stream_iadd_ready.py deleted file mode 100644 index 85edb987..00000000 --- a/tests/extension/stream_/iadd_ready/stream_iadd_ready.py +++ /dev/null @@ -1,131 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import sys -import os - -# the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( - os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) - -from veriloggen import * -import veriloggen.stream as stream - - -def mkMain(): - # input variiable - x = stream.Variable('xdata') - y = stream.Variable('ydata') - - # stream definition - z = x + y - z = stream.Iadd(z) - - # set output attribute - z.output('zdata') - - st = stream.Stream(z, - iready='iready', oready='oready') - m = st.to_module('main') - - return m - - -def mkTest(numports=8): - m = Module('test') - - # target instance - main = mkMain() - - params = m.copy_params(main) - ports = m.copy_sim_ports(main) - - clk = ports['CLK'] - rst = ports['RST'] - - xdata = ports['xdata'] - ydata = ports['ydata'] - zdata = ports['zdata'] - - iready = ports['iready'] - oready = ports['oready'] - - uut = m.Instance(main, 'uut', - params=m.connect_params(main), - ports=m.connect_ports(main)) - - reset_done = m.Reg('reset_done', initval=0) - reset_stmt = [] - reset_stmt.append(reset_done(0)) - reset_stmt.append(xdata(0)) - reset_stmt.append(ydata(0)) - reset_stmt.append(oready(0)) - - simulation.setup_waveform(m, uut) - simulation.setup_clock(m, clk, hperiod=5) - init = simulation.setup_reset(m, rst, reset_stmt, period=100) - - nclk = simulation.next_clock - - init.add( - Delay(1000), - reset_done(1), - nclk(clk), - Delay(10000), - Systask('finish'), - ) - - send_fsm = FSM(m, 'send_fsm', clk, rst) - send_count = m.Reg('send_count', 32, initval=0) - send_fsm.If(reset_done).goto_next() - - send_fsm.If(iready)( - xdata(xdata + 1), - ydata(ydata + 2), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), - send_count.inc() - ) - send_fsm.If(send_count == 20).goto_next() - - recv_fsm = FSM(m, 'recv_fsm', clk, rst) - recv_count = m.Reg('recv_count', 32, initval=0) - recv_fsm.If(reset_done).goto_next() - - recv_fsm( - recv_count.inc() - ) - recv_fsm.If(recv_count == 20)( - recv_count(0) - ) - recv_fsm.If(recv_count == 20).goto_next() - - recv_fsm( - oready(Not(oready)) - ) - - recv_fsm.If(oready)( - Display('zdata=%d', zdata), - recv_count.inc() - ) - recv_fsm.If(recv_count == 20)( - oready(0) - ) - recv_fsm.If(recv_count == 20).goto_next() - - return m - - -if __name__ == '__main__': - test = mkTest() - verilog = test.to_verilog('tmp.v') - print(verilog) - - # run simulator (Icarus Verilog) - sim = simulation.Simulator(test) - rslt = sim.run() # display=False - #rslt = sim.run(display=True) - print(rslt) - - # launch waveform viewer (GTKwave) - # sim.view_waveform() # background=False - # sim.view_waveform(background=True) diff --git a/tests/extension/stream_/iadd_ready/test_stream_iadd_ready.py b/tests/extension/stream_/iadd_ready/test_stream_iadd_ready.py deleted file mode 100644 index b6923477..00000000 --- a/tests/extension/stream_/iadd_ready/test_stream_iadd_ready.py +++ /dev/null @@ -1,192 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import veriloggen -import stream_iadd_ready - -expected_verilog = """ -module test; - - reg CLK; - reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; - wire iready; - reg oready; - wire [32-1:0] zdata; - - main - uut - ( - .CLK(CLK), - .RST(RST), - .xdata(xdata), - .ydata(ydata), - .iready(iready), - .oready(oready), - .zdata(zdata) - ); - - reg reset_done; - - initial begin - $dumpfile("uut.vcd"); - $dumpvars(0, uut); - end - - - initial begin - CLK = 0; - forever begin - #5 CLK = !CLK; - end - end - - - initial begin - RST = 0; - reset_done = 0; - xdata = 0; - ydata = 0; - oready = 0; - #100; - RST = 1; - #100; - RST = 0; - #1000; - reset_done = 1; - @(posedge CLK); - #1; - #10000; - $finish; - end - - reg [32-1:0] send_fsm; - localparam send_fsm_init = 0; - reg [32-1:0] send_count; - reg [32-1:0] recv_fsm; - localparam recv_fsm_init = 0; - reg [32-1:0] recv_count; - localparam send_fsm_1 = 1; - localparam send_fsm_2 = 2; - - always @(posedge CLK) begin - if(RST) begin - send_fsm <= send_fsm_init; - send_count <= 0; - end else begin - case(send_fsm) - send_fsm_init: begin - if(reset_done) begin - send_fsm <= send_fsm_1; - end - end - send_fsm_1: begin - if(iready) begin - xdata <= xdata + 1; - ydata <= ydata + 2; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); - send_count <= send_count + 1; - end - if(send_count == 20) begin - send_fsm <= send_fsm_2; - end - end - endcase - end - end - - localparam recv_fsm_1 = 1; - localparam recv_fsm_2 = 2; - localparam recv_fsm_3 = 3; - - always @(posedge CLK) begin - if(RST) begin - recv_fsm <= recv_fsm_init; - recv_count <= 0; - end else begin - case(recv_fsm) - recv_fsm_init: begin - if(reset_done) begin - recv_fsm <= recv_fsm_1; - end - end - recv_fsm_1: begin - recv_count <= recv_count + 1; - if(recv_count == 20) begin - recv_count <= 0; - end - if(recv_count == 20) begin - recv_fsm <= recv_fsm_2; - end - end - recv_fsm_2: begin - oready <= !oready; - if(oready) begin - $display("zdata=%d", zdata); - recv_count <= recv_count + 1; - end - if(recv_count == 20) begin - oready <= 0; - end - if(recv_count == 20) begin - recv_fsm <= recv_fsm_3; - end - end - endcase - end - end - - -endmodule - - - -module main -( - input CLK, - input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, - output iready, - input oready, - output [32-1:0] zdata -); - - assign iready = oready; - reg [32-1:0] _data_2; - reg [32-1:0] _data_4; - assign zdata = _data_4; - - always @(posedge CLK) begin - if(RST) begin - _data_2 <= 0; - _data_4 <= 1'd0; - end else begin - if(oready) begin - _data_2 <= xdata + ydata; - end - if(oready) begin - _data_4 <= _data_4 + _data_2; - end - end - end - - -endmodule -""" - - -def test(): - veriloggen.reset() - test_module = stream_iadd_ready.mkTest() - code = test_module.to_verilog() - - from pyverilog.vparser.parser import VerilogParser - from pyverilog.ast_code_generator.codegen import ASTCodeGenerator - parser = VerilogParser() - expected_ast = parser.parse(expected_verilog) - codegen = ASTCodeGenerator() - expected_code = codegen.visit(expected_ast) - - assert(expected_code == code) diff --git a/tests/extension/stream_/iadd_valid/stream_iadd_valid.py b/tests/extension/stream_/iadd_valid/stream_iadd_valid.py deleted file mode 100644 index 942e8e9c..00000000 --- a/tests/extension/stream_/iadd_valid/stream_iadd_valid.py +++ /dev/null @@ -1,129 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import sys -import os - -# the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( - os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) - -from veriloggen import * -import veriloggen.stream as stream - - -def mkMain(): - # input variiable - x = stream.Variable('xdata') - y = stream.Variable('ydata') - - # stream definition - z = x + y - z = stream.Iadd(z) - - # set output attribute - z.output('zdata') - - st = stream.Stream(z, - ivalid='ivalid', ovalid='ovalid') - m = st.to_module('main') - - return m - - -def mkTest(numports=8): - m = Module('test') - - # target instance - main = mkMain() - - params = m.copy_params(main) - ports = m.copy_sim_ports(main) - - clk = ports['CLK'] - rst = ports['RST'] - - xdata = ports['xdata'] - ydata = ports['ydata'] - zdata = ports['zdata'] - - ivalid = ports['ivalid'] - ovalid = ports['ovalid'] - - uut = m.Instance(main, 'uut', - params=m.connect_params(main), - ports=m.connect_ports(main)) - - reset_done = m.Reg('reset_done', initval=0) - reset_stmt = [] - reset_stmt.append(reset_done(0)) - reset_stmt.append(xdata(0)) - reset_stmt.append(ydata(0)) - reset_stmt.append(ivalid(0)) - - simulation.setup_waveform(m, uut) - simulation.setup_clock(m, clk, hperiod=5) - init = simulation.setup_reset(m, rst, reset_stmt, period=100) - - nclk = simulation.next_clock - - init.add( - Delay(1000), - reset_done(1), - nclk(clk), - Delay(10000), - Systask('finish'), - ) - - send_fsm = FSM(m, 'send_fsm', clk, rst) - send_count = m.Reg('send_count', 32, initval=0) - send_fsm.If(reset_done).goto_next() - - send_fsm( - ivalid(0), - send_count.inc() - ) - send_fsm.If(send_count == 20)( - ivalid(1), - send_count(0) - ) - send_fsm.If(send_count == 20).goto_next() - - send_fsm( - ivalid(1), - xdata(xdata + 1), - ydata(ydata + 2), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), - send_count.inc() - ) - send_fsm.If(send_count == 20).goto_next() - - send_fsm( - ivalid(0) - ) - - recv_fsm = FSM(m, 'recv_fsm', clk, rst) - recv_count = m.Reg('recv_count', 32, initval=0) - recv_fsm.If(reset_done).goto_next() - recv_fsm.If(ovalid)( - Display('zdata=%d', zdata), - recv_count.inc() - ) - - return m - - -if __name__ == '__main__': - test = mkTest() - verilog = test.to_verilog('tmp.v') - print(verilog) - - # run simulator (Icarus Verilog) - sim = simulation.Simulator(test) - rslt = sim.run() # display=False - #rslt = sim.run(display=True) - print(rslt) - - # launch waveform viewer (GTKwave) - # sim.view_waveform() # background=False - # sim.view_waveform(background=True) diff --git a/tests/extension/stream_/iadd_valid/test_stream_iadd_valid.py b/tests/extension/stream_/iadd_valid/test_stream_iadd_valid.py deleted file mode 100644 index 03ce093d..00000000 --- a/tests/extension/stream_/iadd_valid/test_stream_iadd_valid.py +++ /dev/null @@ -1,192 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import veriloggen -import stream_iadd_valid - -expected_verilog = """ -module test; - - reg CLK; - reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; - reg ivalid; - wire ovalid; - wire [32-1:0] zdata; - - main - uut - ( - .CLK(CLK), - .RST(RST), - .xdata(xdata), - .ydata(ydata), - .ivalid(ivalid), - .ovalid(ovalid), - .zdata(zdata) - ); - - reg reset_done; - - initial begin - $dumpfile("uut.vcd"); - $dumpvars(0, uut); - end - - - initial begin - CLK = 0; - forever begin - #5 CLK = !CLK; - end - end - - - initial begin - RST = 0; - reset_done = 0; - xdata = 0; - ydata = 0; - ivalid = 0; - #100; - RST = 1; - #100; - RST = 0; - #1000; - reset_done = 1; - @(posedge CLK); - #1; - #10000; - $finish; - end - - reg [32-1:0] send_fsm; - localparam send_fsm_init = 0; - reg [32-1:0] send_count; - reg [32-1:0] recv_fsm; - localparam recv_fsm_init = 0; - reg [32-1:0] recv_count; - localparam send_fsm_1 = 1; - localparam send_fsm_2 = 2; - localparam send_fsm_3 = 3; - - always @(posedge CLK) begin - if(RST) begin - send_fsm <= send_fsm_init; - send_count <= 0; - end else begin - case(send_fsm) - send_fsm_init: begin - if(reset_done) begin - send_fsm <= send_fsm_1; - end - end - send_fsm_1: begin - ivalid <= 0; - send_count <= send_count + 1; - if(send_count == 20) begin - ivalid <= 1; - send_count <= 0; - end - if(send_count == 20) begin - send_fsm <= send_fsm_2; - end - end - send_fsm_2: begin - ivalid <= 1; - xdata <= xdata + 1; - ydata <= ydata + 2; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); - send_count <= send_count + 1; - if(send_count == 20) begin - send_fsm <= send_fsm_3; - end - end - send_fsm_3: begin - ivalid <= 0; - end - endcase - end - end - - localparam recv_fsm_1 = 1; - - always @(posedge CLK) begin - if(RST) begin - recv_fsm <= recv_fsm_init; - recv_count <= 0; - end else begin - case(recv_fsm) - recv_fsm_init: begin - if(reset_done) begin - recv_fsm <= recv_fsm_1; - end - end - recv_fsm_1: begin - if(ovalid) begin - $display("zdata=%d", zdata); - recv_count <= recv_count + 1; - end - end - endcase - end - end - - -endmodule - - - -module main -( - input CLK, - input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, - input ivalid, - output ovalid, - output [32-1:0] zdata -); - - reg _ivalid_0; - reg _ivalid_1; - assign ovalid = _ivalid_1; - reg [32-1:0] _data_2; - reg [32-1:0] _data_4; - assign zdata = _data_4; - - always @(posedge CLK) begin - if(RST) begin - _ivalid_0 <= 0; - _ivalid_1 <= 0; - _data_2 <= 0; - _data_4 <= 1'd0; - end else begin - _ivalid_0 <= ivalid; - _ivalid_1 <= _ivalid_0; - _data_2 <= xdata + ydata; - if(_ivalid_0) begin - _data_4 <= _data_4 + _data_2; - end - end - end - - -endmodule -""" - - -def test(): - veriloggen.reset() - test_module = stream_iadd_valid.mkTest() - code = test_module.to_verilog() - - from pyverilog.vparser.parser import VerilogParser - from pyverilog.ast_code_generator.codegen import ASTCodeGenerator - parser = VerilogParser() - expected_ast = parser.parse(expected_verilog) - codegen = ASTCodeGenerator() - expected_code = codegen.visit(expected_ast) - - assert(expected_code == code) diff --git a/tests/extension/stream_/iadd_validready/stream_iadd_validready.py b/tests/extension/stream_/iadd_validready/stream_iadd_validready.py deleted file mode 100644 index bb46dbc4..00000000 --- a/tests/extension/stream_/iadd_validready/stream_iadd_validready.py +++ /dev/null @@ -1,153 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import sys -import os - -# the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( - os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) - -from veriloggen import * -import veriloggen.stream as stream - - -def mkMain(): - # input variiable - x = stream.Variable('xdata') - y = stream.Variable('ydata') - - # stream definition - z = x + y - z = stream.Iadd(z) - - # set output attribute - z.output('zdata') - - st = stream.Stream(z, - ivalid='ivalid', ovalid='ovalid', - iready='iready', oready='oready') - m = st.to_module('main') - - return m - - -def mkTest(numports=8): - m = Module('test') - - # target instance - main = mkMain() - - params = m.copy_params(main) - ports = m.copy_sim_ports(main) - - clk = ports['CLK'] - rst = ports['RST'] - - xdata = ports['xdata'] - ydata = ports['ydata'] - zdata = ports['zdata'] - - ivalid = ports['ivalid'] - ovalid = ports['ovalid'] - iready = ports['iready'] - oready = ports['oready'] - - uut = m.Instance(main, 'uut', - params=m.connect_params(main), - ports=m.connect_ports(main)) - - reset_done = m.Reg('reset_done', initval=0) - reset_stmt = [] - reset_stmt.append(reset_done(0)) - reset_stmt.append(xdata(0)) - reset_stmt.append(ydata(0)) - reset_stmt.append(ivalid(0)) - reset_stmt.append(oready(0)) - - simulation.setup_waveform(m, uut) - simulation.setup_clock(m, clk, hperiod=5) - init = simulation.setup_reset(m, rst, reset_stmt, period=100) - - nclk = simulation.next_clock - - init.add( - Delay(1000), - reset_done(1), - nclk(clk), - Delay(10000), - Systask('finish'), - ) - - send_fsm = FSM(m, 'send_fsm', clk, rst) - send_count = m.Reg('send_count', 32, initval=0) - send_fsm.If(reset_done).goto_next() - - send_fsm( - ivalid(0), - send_count.inc() - ) - - send_fsm.If(send_count == 10)( - send_count(0) - ) - send_fsm.If(send_count == 10).goto_next() - - send_fsm( - xdata(0), - ydata(0), - ivalid(1), - send_count.inc() - ) - send_fsm.goto_next() - - send_fsm.If(iready)( - xdata(xdata + 1), - ydata(ydata + 2), - ivalid(1), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), - send_count.inc() - ) - send_fsm.If(iready, send_count == 20)( - ivalid(0) - ) - send_fsm.If(iready, send_count == 20).goto_next() - - recv_fsm = FSM(m, 'recv_fsm', clk, rst) - recv_count = m.Reg('recv_count', 32, initval=0) - recv_fsm.If(reset_done).goto_next() - - recv_fsm( - recv_count.inc() - ) - recv_fsm.If(recv_count == 20)( - recv_count(0) - ) - recv_fsm.If(recv_count == 20).goto_next() - - recv_fsm( - oready(Not(oready)) - ) - - recv_fsm.If(ovalid, oready)( - Display('zdata=%d', zdata), - recv_count.inc() - ) - - return m - - -if __name__ == '__main__': - test = mkTest() - verilog = test.to_verilog('tmp.v') - print(verilog) - - # run simulator (Icarus Verilog) - sim = simulation.Simulator(test) - rslt = sim.run() # display=False - #rslt = sim.run(display=True) - print(rslt) - - # launch waveform viewer (GTKwave) - # sim.view_waveform() # background=False - # sim.view_waveform(background=True) diff --git a/tests/extension/stream_/iadd_validready/test_stream_iadd_validready.py b/tests/extension/stream_/iadd_validready/test_stream_iadd_validready.py deleted file mode 100644 index 63239c00..00000000 --- a/tests/extension/stream_/iadd_validready/test_stream_iadd_validready.py +++ /dev/null @@ -1,227 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function -import veriloggen -import stream_iadd_validready - -expected_verilog = """ -module test; - - reg CLK; - reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; - reg ivalid; - wire iready; - wire ovalid; - reg oready; - wire [32-1:0] zdata; - - main - uut - ( - .CLK(CLK), - .RST(RST), - .xdata(xdata), - .ydata(ydata), - .ivalid(ivalid), - .iready(iready), - .ovalid(ovalid), - .oready(oready), - .zdata(zdata) - ); - - reg reset_done; - - initial begin - $dumpfile("uut.vcd"); - $dumpvars(0, uut); - end - - - initial begin - CLK = 0; - forever begin - #5 CLK = !CLK; - end - end - - - initial begin - RST = 0; - reset_done = 0; - xdata = 0; - ydata = 0; - ivalid = 0; - oready = 0; - #100; - RST = 1; - #100; - RST = 0; - #1000; - reset_done = 1; - @(posedge CLK); - #1; - #10000; - $finish; - end - - reg [32-1:0] send_fsm; - localparam send_fsm_init = 0; - reg [32-1:0] send_count; - reg [32-1:0] recv_fsm; - localparam recv_fsm_init = 0; - reg [32-1:0] recv_count; - localparam send_fsm_1 = 1; - localparam send_fsm_2 = 2; - localparam send_fsm_3 = 3; - localparam send_fsm_4 = 4; - - always @(posedge CLK) begin - if(RST) begin - send_fsm <= send_fsm_init; - send_count <= 0; - end else begin - case(send_fsm) - send_fsm_init: begin - if(reset_done) begin - send_fsm <= send_fsm_1; - end - end - send_fsm_1: begin - ivalid <= 0; - send_count <= send_count + 1; - if(send_count == 10) begin - send_count <= 0; - end - if(send_count == 10) begin - send_fsm <= send_fsm_2; - end - end - send_fsm_2: begin - xdata <= 0; - ydata <= 0; - ivalid <= 1; - send_count <= send_count + 1; - send_fsm <= send_fsm_3; - end - send_fsm_3: begin - if(iready) begin - xdata <= xdata + 1; - ydata <= ydata + 2; - ivalid <= 1; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); - send_count <= send_count + 1; - end - if(iready && (send_count == 20)) begin - ivalid <= 0; - end - if(iready && (send_count == 20)) begin - send_fsm <= send_fsm_4; - end - end - endcase - end - end - - localparam recv_fsm_1 = 1; - localparam recv_fsm_2 = 2; - - always @(posedge CLK) begin - if(RST) begin - recv_fsm <= recv_fsm_init; - recv_count <= 0; - end else begin - case(recv_fsm) - recv_fsm_init: begin - if(reset_done) begin - recv_fsm <= recv_fsm_1; - end - end - recv_fsm_1: begin - recv_count <= recv_count + 1; - if(recv_count == 20) begin - recv_count <= 0; - end - if(recv_count == 20) begin - recv_fsm <= recv_fsm_2; - end - end - recv_fsm_2: begin - oready <= !oready; - if(ovalid && oready) begin - $display("zdata=%d", zdata); - recv_count <= recv_count + 1; - end - end - endcase - end - end - - -endmodule - - - -module main -( - input CLK, - input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, - input ivalid, - output iready, - output ovalid, - input oready, - output [32-1:0] zdata -); - - wire _tmp_0; - assign _tmp_0 = !ovalid || oready; - reg _ivalid_0; - reg _ivalid_1; - assign ovalid = _ivalid_1; - assign iready = _tmp_0; - reg [32-1:0] _data_2; - reg [32-1:0] _data_4; - assign zdata = _data_4; - - always @(posedge CLK) begin - if(RST) begin - _ivalid_0 <= 0; - _ivalid_1 <= 0; - _data_2 <= 0; - _data_4 <= 1'd0; - end else begin - if(_tmp_0) begin - _ivalid_0 <= ivalid; - end - if(_tmp_0) begin - _ivalid_1 <= _ivalid_0; - end - if(_tmp_0) begin - _data_2 <= xdata + ydata; - end - if(_ivalid_0 && _tmp_0) begin - _data_4 <= _data_4 + _data_2; - end - end - end - - -endmodule -""" - -def test(): - veriloggen.reset() - test_module = stream_iadd_validready.mkTest() - code = test_module.to_verilog() - - from pyverilog.vparser.parser import VerilogParser - from pyverilog.ast_code_generator.codegen import ASTCodeGenerator - parser = VerilogParser() - expected_ast = parser.parse(expected_verilog) - codegen = ASTCodeGenerator() - expected_code = codegen.visit(expected_ast) - - assert(expected_code == code) diff --git a/tests/extension/stream_/iadd/Makefile b/tests/extension/stream_/reduceadd/Makefile similarity index 100% rename from tests/extension/stream_/iadd/Makefile rename to tests/extension/stream_/reduceadd/Makefile diff --git a/tests/extension/stream_/regionadd/stream_regionadd.py b/tests/extension/stream_/reduceadd/stream_reduceadd.py similarity index 94% rename from tests/extension/stream_/regionadd/stream_regionadd.py rename to tests/extension/stream_/reduceadd/stream_reduceadd.py index 684b225e..585138af 100644 --- a/tests/extension/stream_/regionadd/stream_regionadd.py +++ b/tests/extension/stream_/reduceadd/stream_reduceadd.py @@ -19,7 +19,7 @@ def mkMain(): # stream definition z = x + y - z, v = stream.RegionAdd(z, 8, enable=e) + z, v = stream.ReduceAddValid(z, 8, enable=e) # set output attribute z.output('zdata') @@ -82,20 +82,24 @@ def mkTest(numports=8): xdata(0), ydata(0), edata(1), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), send_count.inc() ) + send_fsm.Delay(1)( + Display('xdata=%d', xdata), + Display('ydata=%d', ydata) + ) send_fsm.goto_next() send_fsm( xdata(xdata + 1), ydata(ydata + 2), edata(1), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), send_count.inc() ) + send_fsm.Delay(1)( + Display('xdata=%d', xdata), + Display('ydata=%d', ydata) + ) send_fsm.If(send_count == 64).goto_next() send_fsm( diff --git a/tests/extension/stream_/regionadd/test_stream_regionadd.py b/tests/extension/stream_/reduceadd/test_stream_reduceadd.py similarity index 63% rename from tests/extension/stream_/regionadd/test_stream_regionadd.py rename to tests/extension/stream_/reduceadd/test_stream_reduceadd.py index 76add36d..a48d34c1 100644 --- a/tests/extension/stream_/regionadd/test_stream_regionadd.py +++ b/tests/extension/stream_/reduceadd/test_stream_reduceadd.py @@ -1,18 +1,18 @@ from __future__ import absolute_import from __future__ import print_function import veriloggen -import stream_regionadd +import stream_reduceadd expected_verilog = """ module test; reg CLK; reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; - reg [32-1:0] edata; - wire [32-1:0] zdata; - wire [32-1:0] vdata; + reg signed [32-1:0] xdata; + reg signed [32-1:0] ydata; + reg signed [32-1:0] edata; + wire signed [32-1:0] zdata; + wire [1-1:0] vdata; main uut @@ -63,6 +63,9 @@ reg [32-1:0] send_fsm; localparam send_fsm_init = 0; reg [32-1:0] send_count; + reg [32-1:0] _d1_send_fsm; + reg _send_fsm_cond_1_0_1; + reg _send_fsm_cond_2_1_1; reg [32-1:0] recv_fsm; localparam recv_fsm_init = 0; reg [32-1:0] recv_count; @@ -73,8 +76,26 @@ always @(posedge CLK) begin if(RST) begin send_fsm <= send_fsm_init; + _d1_send_fsm <= send_fsm_init; send_count <= 0; + _send_fsm_cond_1_0_1 <= 0; + _send_fsm_cond_2_1_1 <= 0; end else begin + _d1_send_fsm <= send_fsm; + case(_d1_send_fsm) + send_fsm_1: begin + if(_send_fsm_cond_1_0_1) begin + $display("xdata=%d", xdata); + $display("ydata=%d", ydata); + end + end + send_fsm_2: begin + if(_send_fsm_cond_2_1_1) begin + $display("xdata=%d", xdata); + $display("ydata=%d", ydata); + end + end + endcase case(send_fsm) send_fsm_init: begin if(reset_done) begin @@ -85,18 +106,16 @@ xdata <= 0; ydata <= 0; edata <= 1; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); send_count <= send_count + 1; + _send_fsm_cond_1_0_1 <= 1; send_fsm <= send_fsm_2; end send_fsm_2: begin xdata <= xdata + 1; ydata <= ydata + 2; edata <= 1; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); send_count <= send_count + 1; + _send_fsm_cond_2_1_1 <= 1; if(send_count == 64) begin send_fsm <= send_fsm_3; end @@ -144,68 +163,51 @@ ( input CLK, input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, - input [32-1:0] edata, - output [32-1:0] zdata, - output [32-1:0] vdata + input signed [32-1:0] xdata, + input signed [32-1:0] ydata, + input signed [32-1:0] edata, + output signed [32-1:0] zdata, + output [1-1:0] vdata ); - reg [32-1:0] _data_3; - reg [32-1:0] _data_6; - reg [32-1:0] _data_14; - reg [1-1:0] _data_7; - reg [32-1:0] _data_15; - reg [32-1:0] _data_16; + reg signed [32-1:0] _data_3; + reg signed [32-1:0] _data_10; + reg signed [32-1:0] _data_6; + reg [5-1:0] _count_6; reg [1-1:0] _data_9; - reg [32-1:0] _data_10; - reg [32-1:0] _data_17; - reg [32-1:0] _data_18; - reg [32-1:0] _data_11; - reg [32-1:0] _data_13; - reg [32-1:0] _data_19; - assign zdata = _data_13; - assign vdata = _data_19; + reg [5-1:0] _count_9; + assign zdata = _data_6; + assign vdata = _data_9; always @(posedge CLK) begin if(RST) begin _data_3 <= 0; - _data_6 <= 1'd0; - _data_14 <= 0; - _data_7 <= 0; - _data_15 <= 0; - _data_16 <= 0; - _data_9 <= 0; _data_10 <= 0; - _data_17 <= 0; - _data_18 <= 0; - _data_11 <= 0; - _data_13 <= 1'd0; - _data_19 <= 0; + _data_6 <= 1'd0; + _count_6 <= 0; + _data_9 <= 1'd0; + _count_9 <= 0; end else begin _data_3 <= xdata + ydata; - if(edata) begin - _data_6 <= (_data_6 >= 7)? 0 : _data_6 + 2'd1; + _data_10 <= edata; + if(_data_10) begin + _data_6 <= _data_6 + _data_3; + end + if(_data_10) begin + _count_6 <= (_count_6 == 7)? 0 : _count_6 + 1; + end + if(_data_10 && (_count_6 == 0)) begin + _data_6 <= 1'd0 + _data_3; end - _data_14 <= edata; - _data_7 <= _data_6 == 4'd7; - _data_15 <= _data_14; - _data_16 <= _data_3; - _data_9 <= _data_7; - _data_10 <= _data_9 && _data_15; - _data_17 <= _data_16; - _data_18 <= _data_15; - _data_11 <= _data_10; - if(_data_18) begin - _data_13 <= _data_13 + _data_17; + if(_data_10) begin + _data_9 <= _count_9 == 7; end - if(_data_11) begin - _data_13 <= 1'd0; + if(_data_10) begin + _count_9 <= (_count_9 == 7)? 0 : _count_9 + 1; end - if(_data_18 && _data_11) begin - _data_13 <= 1'd0 + _data_17; + if(_data_10 && (_count_9 == 0)) begin + _data_9 <= _count_9 == 7; end - _data_19 <= _data_10; end end @@ -216,7 +218,7 @@ def test(): veriloggen.reset() - test_module = stream_regionadd.mkTest() + test_module = stream_reduceadd.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser diff --git a/tests/extension/stream_/iadd_ready/Makefile b/tests/extension/stream_/reduceadd_valid/Makefile similarity index 100% rename from tests/extension/stream_/iadd_ready/Makefile rename to tests/extension/stream_/reduceadd_valid/Makefile diff --git a/tests/extension/stream_/regionadd_valid/stream_regionadd_valid.py b/tests/extension/stream_/reduceadd_valid/stream_reduceadd_valid.py similarity index 93% rename from tests/extension/stream_/regionadd_valid/stream_regionadd_valid.py rename to tests/extension/stream_/reduceadd_valid/stream_reduceadd_valid.py index 557f0800..cb669549 100644 --- a/tests/extension/stream_/regionadd_valid/stream_regionadd_valid.py +++ b/tests/extension/stream_/reduceadd_valid/stream_reduceadd_valid.py @@ -18,7 +18,7 @@ def mkMain(): # stream definition z = x + y - z, v = stream.RegionAdd(z, 8) + z, v = stream.ReduceAddValid(z, 8) # set output attribute z.output('zdata') @@ -96,16 +96,22 @@ def mkTest(numports=8): ivalid(1), send_count.inc() ) + send_fsm.Delay(1)( + Display('xdata=%d', xdata), + Display('ydata=%d', ydata) + ) send_fsm.goto_next() send_fsm( xdata(xdata + 1), ydata(ydata + 2), ivalid(1), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), send_count.inc() ) + send_fsm.Delay(1)( + Display('xdata=%d', xdata), + Display('ydata=%d', ydata) + ) send_fsm.If(send_count == 65)( ivalid(0) ) diff --git a/tests/extension/stream_/regionadd_valid/test_stream_regionadd_valid.py b/tests/extension/stream_/reduceadd_valid/test_stream_reduceadd_valid.py similarity index 68% rename from tests/extension/stream_/regionadd_valid/test_stream_regionadd_valid.py rename to tests/extension/stream_/reduceadd_valid/test_stream_reduceadd_valid.py index 4dc9401a..b12bcc8a 100644 --- a/tests/extension/stream_/regionadd_valid/test_stream_regionadd_valid.py +++ b/tests/extension/stream_/reduceadd_valid/test_stream_reduceadd_valid.py @@ -1,18 +1,18 @@ from __future__ import absolute_import from __future__ import print_function import veriloggen -import stream_regionadd_valid +import stream_reduceadd_valid expected_verilog = """ module test; reg CLK; reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; + reg signed [32-1:0] xdata; + reg signed [32-1:0] ydata; reg ivalid; wire ovalid; - wire [32-1:0] zdata; + wire signed [32-1:0] zdata; wire [1-1:0] vdata; main @@ -65,6 +65,9 @@ reg [32-1:0] send_fsm; localparam send_fsm_init = 0; reg [32-1:0] send_count; + reg [32-1:0] _d1_send_fsm; + reg _send_fsm_cond_2_0_1; + reg _send_fsm_cond_3_1_1; reg [32-1:0] recv_fsm; localparam recv_fsm_init = 0; reg [32-1:0] recv_count; @@ -76,8 +79,26 @@ always @(posedge CLK) begin if(RST) begin send_fsm <= send_fsm_init; + _d1_send_fsm <= send_fsm_init; send_count <= 0; + _send_fsm_cond_2_0_1 <= 0; + _send_fsm_cond_3_1_1 <= 0; end else begin + _d1_send_fsm <= send_fsm; + case(_d1_send_fsm) + send_fsm_2: begin + if(_send_fsm_cond_2_0_1) begin + $display("xdata=%d", xdata); + $display("ydata=%d", ydata); + end + end + send_fsm_3: begin + if(_send_fsm_cond_3_1_1) begin + $display("xdata=%d", xdata); + $display("ydata=%d", ydata); + end + end + endcase case(send_fsm) send_fsm_init: begin if(reset_done) begin @@ -99,15 +120,15 @@ ydata <= 0; ivalid <= 1; send_count <= send_count + 1; + _send_fsm_cond_2_0_1 <= 1; send_fsm <= send_fsm_3; end send_fsm_3: begin xdata <= xdata + 1; ydata <= ydata + 2; ivalid <= 1; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); send_count <= send_count + 1; + _send_fsm_cond_3_1_1 <= 1; if(send_count == 65) begin ivalid <= 0; end @@ -151,53 +172,56 @@ ( input CLK, input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, + input signed [32-1:0] xdata, + input signed [32-1:0] ydata, input ivalid, output ovalid, - output [32-1:0] zdata, + output signed [32-1:0] zdata, output [1-1:0] vdata ); reg _ivalid_0; reg _ivalid_1; assign ovalid = _ivalid_1; - reg [32-1:0] _data_5; - reg [32-1:0] _data_2; - reg [1-1:0] _data_6; + reg signed [32-1:0] _data_2; + reg signed [32-1:0] _data_5; + reg [5-1:0] _count_5; reg [1-1:0] _data_8; - reg [1-1:0] _data_9; - reg [32-1:0] _data_11; - reg [1-1:0] _data_12; - assign zdata = _data_11; - assign vdata = _data_12; + reg [5-1:0] _count_8; + assign zdata = _data_5; + assign vdata = _data_8; always @(posedge CLK) begin if(RST) begin _ivalid_0 <= 0; _ivalid_1 <= 0; - _data_5 <= 1'd0; _data_2 <= 0; - _data_6 <= 0; - _data_8 <= 0; - _data_9 <= 0; - _data_11 <= 1'd0; - _data_12 <= 0; + _data_5 <= 1'd0; + _count_5 <= 0; + _data_8 <= 1'd0; + _count_8 <= 0; end else begin _ivalid_0 <= ivalid; _ivalid_1 <= _ivalid_0; - _data_5 <= (_data_5 >= 7)? 0 : _data_5 + 2'd1; _data_2 <= xdata + ydata; - _data_6 <= _data_5 == 4'd7; - _data_8 <= _data_6; - _data_9 <= _data_8; if(_ivalid_0) begin - _data_11 <= _data_11 + _data_2; + _data_5 <= _data_5 + _data_2; + end + if(_ivalid_0) begin + _count_5 <= (_count_5 == 7)? 0 : _count_5 + 1; + end + if(_ivalid_0 && (_count_5 == 0)) begin + _data_5 <= 1'd0 + _data_2; + end + if(_ivalid_0) begin + _data_8 <= _count_8 == 7; + end + if(_ivalid_0) begin + _count_8 <= (_count_8 == 7)? 0 : _count_8 + 1; end - if(_ivalid_0 && _data_9) begin - _data_11 <= 1'd0 + _data_2; + if(_ivalid_0 && (_count_8 == 0)) begin + _data_8 <= _count_8 == 7; end - _data_12 <= _data_8; end end @@ -208,7 +232,7 @@ def test(): veriloggen.reset() - test_module = stream_regionadd_valid.mkTest() + test_module = stream_reduceadd_valid.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser diff --git a/tests/extension/stream_/iadd_valid/Makefile b/tests/extension/stream_/reduceadd_validready/Makefile similarity index 100% rename from tests/extension/stream_/iadd_valid/Makefile rename to tests/extension/stream_/reduceadd_validready/Makefile diff --git a/tests/extension/stream_/regionadd_validready/stream_regionadd_validready.py b/tests/extension/stream_/reduceadd_validready/stream_reduceadd_validready.py similarity index 94% rename from tests/extension/stream_/regionadd_validready/stream_regionadd_validready.py rename to tests/extension/stream_/reduceadd_validready/stream_reduceadd_validready.py index 4847c9a2..6ce79972 100644 --- a/tests/extension/stream_/regionadd_validready/stream_regionadd_validready.py +++ b/tests/extension/stream_/reduceadd_validready/stream_reduceadd_validready.py @@ -18,7 +18,7 @@ def mkMain(): # stream definition z = x + y - z, v = stream.RegionAdd(z, 8) + z, v = stream.ReduceAddValid(z, 8) # set output attribute z.output('zdata') @@ -100,16 +100,22 @@ def mkTest(numports=8): ivalid(1), send_count.inc() ) + send_fsm.Delay(1)( + Display('xdata=%d', xdata), + Display('ydata=%d', ydata) + ) send_fsm.goto_next() send_fsm.If(iready)( xdata(xdata + 1), ydata(ydata + 2), ivalid(1), - Display('xdata=%d', xdata), - Display('ydata=%d', ydata), send_count.inc() ) + send_fsm.Delay(1)( + Display('xdata=%d', xdata), + Display('ydata=%d', ydata) + ) send_fsm.If(iready, send_count == 65)( ivalid(0) ) diff --git a/tests/extension/stream_/regionadd_validready/test_stream_regionadd_validready.py b/tests/extension/stream_/reduceadd_validready/test_stream_reduceadd_validready.py similarity index 73% rename from tests/extension/stream_/regionadd_validready/test_stream_regionadd_validready.py rename to tests/extension/stream_/reduceadd_validready/test_stream_reduceadd_validready.py index 3202aa69..2dcf9f43 100644 --- a/tests/extension/stream_/regionadd_validready/test_stream_regionadd_validready.py +++ b/tests/extension/stream_/reduceadd_validready/test_stream_reduceadd_validready.py @@ -1,20 +1,20 @@ from __future__ import absolute_import from __future__ import print_function import veriloggen -import stream_regionadd_validready +import stream_reduceadd_validready expected_verilog = """ module test; reg CLK; reg RST; - reg [32-1:0] xdata; - reg [32-1:0] ydata; + reg signed [32-1:0] xdata; + reg signed [32-1:0] ydata; reg ivalid; wire iready; wire ovalid; reg oready; - wire [32-1:0] zdata; + wire signed [32-1:0] zdata; wire [1-1:0] vdata; main @@ -70,6 +70,9 @@ reg [32-1:0] send_fsm; localparam send_fsm_init = 0; reg [32-1:0] send_count; + reg [32-1:0] _d1_send_fsm; + reg _send_fsm_cond_2_0_1; + reg _send_fsm_cond_3_1_1; reg [32-1:0] recv_fsm; localparam recv_fsm_init = 0; reg [32-1:0] recv_count; @@ -81,8 +84,26 @@ always @(posedge CLK) begin if(RST) begin send_fsm <= send_fsm_init; + _d1_send_fsm <= send_fsm_init; send_count <= 0; + _send_fsm_cond_2_0_1 <= 0; + _send_fsm_cond_3_1_1 <= 0; end else begin + _d1_send_fsm <= send_fsm; + case(_d1_send_fsm) + send_fsm_2: begin + if(_send_fsm_cond_2_0_1) begin + $display("xdata=%d", xdata); + $display("ydata=%d", ydata); + end + end + send_fsm_3: begin + if(_send_fsm_cond_3_1_1) begin + $display("xdata=%d", xdata); + $display("ydata=%d", ydata); + end + end + endcase case(send_fsm) send_fsm_init: begin if(reset_done) begin @@ -104,6 +125,7 @@ ydata <= 0; ivalid <= 1; send_count <= send_count + 1; + _send_fsm_cond_2_0_1 <= 1; send_fsm <= send_fsm_3; end send_fsm_3: begin @@ -111,10 +133,9 @@ xdata <= xdata + 1; ydata <= ydata + 2; ivalid <= 1; - $display("xdata=%d", xdata); - $display("ydata=%d", ydata); send_count <= send_count + 1; end + _send_fsm_cond_3_1_1 <= 1; if(iready && (send_count == 65)) begin ivalid <= 0; end @@ -169,13 +190,13 @@ ( input CLK, input RST, - input [32-1:0] xdata, - input [32-1:0] ydata, + input signed [32-1:0] xdata, + input signed [32-1:0] ydata, input ivalid, output iready, output ovalid, input oready, - output [32-1:0] zdata, + output signed [32-1:0] zdata, output [1-1:0] vdata ); @@ -185,27 +206,23 @@ reg _ivalid_1; assign ovalid = _ivalid_1; assign iready = _tmp_0; - reg [32-1:0] _data_5; - reg [32-1:0] _data_2; - reg [1-1:0] _data_6; + reg signed [32-1:0] _data_2; + reg signed [32-1:0] _data_5; + reg [5-1:0] _count_5; reg [1-1:0] _data_8; - reg [1-1:0] _data_9; - reg [32-1:0] _data_11; - reg [1-1:0] _data_12; - assign zdata = _data_11; - assign vdata = _data_12; + reg [5-1:0] _count_8; + assign zdata = _data_5; + assign vdata = _data_8; always @(posedge CLK) begin if(RST) begin _ivalid_0 <= 0; _ivalid_1 <= 0; - _data_5 <= 1'd0; _data_2 <= 0; - _data_6 <= 0; - _data_8 <= 0; - _data_9 <= 0; - _data_11 <= 1'd0; - _data_12 <= 0; + _data_5 <= 1'd0; + _count_5 <= 0; + _data_8 <= 1'd0; + _count_8 <= 0; end else begin if(_tmp_0) begin _ivalid_0 <= ivalid; @@ -213,29 +230,26 @@ if(_tmp_0) begin _ivalid_1 <= _ivalid_0; end - if(_tmp_0) begin - _data_5 <= (_data_5 >= 7)? 0 : _data_5 + 2'd1; - end if(_tmp_0) begin _data_2 <= xdata + ydata; end - if(_tmp_0) begin - _data_6 <= _data_5 == 4'd7; + if(_ivalid_0 && _tmp_0) begin + _data_5 <= _data_5 + _data_2; end - if(_tmp_0) begin - _data_8 <= _data_6; + if(_ivalid_0 && _tmp_0) begin + _count_5 <= (_count_5 == 7)? 0 : _count_5 + 1; end - if(_tmp_0) begin - _data_9 <= _data_8; + if(_ivalid_0 && _tmp_0 && (_count_5 == 0)) begin + _data_5 <= 1'd0 + _data_2; end if(_ivalid_0 && _tmp_0) begin - _data_11 <= _data_11 + _data_2; + _data_8 <= _count_8 == 7; end - if(_ivalid_0 && _tmp_0 && _data_9) begin - _data_11 <= 1'd0 + _data_2; + if(_ivalid_0 && _tmp_0) begin + _count_8 <= (_count_8 == 7)? 0 : _count_8 + 1; end - if(_tmp_0) begin - _data_12 <= _data_8; + if(_ivalid_0 && _tmp_0 && (_count_8 == 0)) begin + _data_8 <= _count_8 == 7; end end end @@ -247,7 +261,7 @@ def test(): veriloggen.reset() - test_module = stream_regionadd_validready.mkTest() + test_module = stream_reduceadd_validready.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser diff --git a/tests/extension/stream_/regionadd/Makefile b/tests/extension/stream_/regionadd/Makefile deleted file mode 100644 index 499ae3b1..00000000 --- a/tests/extension/stream_/regionadd/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) -ARGS= - -PYTHON=python3 -#PYTHON=python -#OPT=-m pdb -#OPT=-m cProfile -s time -#OPT=-m cProfile -o profile.rslt - -.PHONY: all -all: test - -.PHONY: run -run: - $(PYTHON) $(OPT) $(TARGET) $(ARGS) - -.PHONY: test -test: - $(PYTHON) -m pytest -vv - -.PHONY: check -check: - $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v - iverilog -tnull -Wall tmp.v - rm -f tmp.v - -.PHONY: clean -clean: - rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd diff --git a/tests/extension/stream_/regionadd_valid/Makefile b/tests/extension/stream_/regionadd_valid/Makefile deleted file mode 100644 index 499ae3b1..00000000 --- a/tests/extension/stream_/regionadd_valid/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) -ARGS= - -PYTHON=python3 -#PYTHON=python -#OPT=-m pdb -#OPT=-m cProfile -s time -#OPT=-m cProfile -o profile.rslt - -.PHONY: all -all: test - -.PHONY: run -run: - $(PYTHON) $(OPT) $(TARGET) $(ARGS) - -.PHONY: test -test: - $(PYTHON) -m pytest -vv - -.PHONY: check -check: - $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v - iverilog -tnull -Wall tmp.v - rm -f tmp.v - -.PHONY: clean -clean: - rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd diff --git a/tests/extension/stream_/regionadd_validready/Makefile b/tests/extension/stream_/regionadd_validready/Makefile deleted file mode 100644 index 499ae3b1..00000000 --- a/tests/extension/stream_/regionadd_validready/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) -ARGS= - -PYTHON=python3 -#PYTHON=python -#OPT=-m pdb -#OPT=-m cProfile -s time -#OPT=-m cProfile -o profile.rslt - -.PHONY: all -all: test - -.PHONY: run -run: - $(PYTHON) $(OPT) $(TARGET) $(ARGS) - -.PHONY: test -test: - $(PYTHON) -m pytest -vv - -.PHONY: check -check: - $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v - iverilog -tnull -Wall tmp.v - rm -f tmp.v - -.PHONY: clean -clean: - rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd diff --git a/tests/extension/thread_/stream/test_thread_stream.py b/tests/extension/thread_/stream/test_thread_stream.py index 51e1e78b..894d68eb 100644 --- a/tests/extension/thread_/stream/test_thread_stream.py +++ b/tests/extension/thread_/stream/test_thread_stream.py @@ -588,7 +588,7 @@ localparam _mystream_fsm_9_init = 0; reg [33-1:0] _tmp_50; reg _tmp_51; - wire [32-1:0] _plus_data_52; + wire signed [32-1:0] _plus_data_52; wire _plus_valid_52; wire _plus_ready_52; assign _plus_ready_52 = (_tmp_50 > 0) && !_tmp_51; @@ -1041,7 +1041,7 @@ end end - reg [32-1:0] _plus_data_131; + reg signed [32-1:0] _plus_data_131; reg _plus_valid_131; wire _plus_ready_131; assign _tmp_28 = 1 && ((_plus_ready_131 || !_plus_valid_131) && (_tmp_26 && _tmp_38)); diff --git a/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py b/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py index d9241c77..ae1165ea 100644 --- a/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py +++ b/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py @@ -582,7 +582,7 @@ reg [5-1:0] _tmp_47; reg _tmp_48; wire _tmp_all_valid_49; - wire [32-1:0] _reduceadd_data_50; + wire signed [32-1:0] _reduceadd_data_50; wire _reduceadd_valid_50; wire _reduceadd_ready_50; assign _reduceadd_ready_50 = (_tmp_47 > 0) && !_tmp_48 && _tmp_all_valid_49; @@ -1270,11 +1270,11 @@ assign __variable_data_111 = _tmp_103; assign __variable_valid_111 = _tmp_97; assign _tmp_99 = 1 && __variable_ready_111; - wire [32-1:0] _times_data_117; + wire signed [32-1:0] _times_data_117; wire _times_valid_117; wire _times_ready_117; - wire [64-1:0] _times_odata_117; - reg [64-1:0] _times_data_reg_117; + wire signed [64-1:0] _times_odata_117; + reg signed [64-1:0] _times_data_reg_117; assign _times_data_117 = _times_data_reg_117; wire _times_ovalid_117; reg _times_valid_reg_117; @@ -1299,7 +1299,7 @@ assign _tmp_15 = 1 && ((_times_ready_117 || !_times_valid_117) && (_tmp_13 && _tmp_30)); assign _tmp_32 = 1 && ((_times_ready_117 || !_times_valid_117) && (_tmp_13 && _tmp_30)); - reg [32-1:0] _reduceadd_data_118; + reg signed [32-1:0] _reduceadd_data_118; reg _reduceadd_valid_118; wire _reduceadd_ready_118; reg [4-1:0] _reduceadd_count_118; @@ -2391,15 +2391,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/thread_/stream_len1/test_thread_stream_len1.py b/tests/extension/thread_/stream_len1/test_thread_stream_len1.py index c9db1f2e..4c1439cd 100644 --- a/tests/extension/thread_/stream_len1/test_thread_stream_len1.py +++ b/tests/extension/thread_/stream_len1/test_thread_stream_len1.py @@ -588,7 +588,7 @@ localparam _mystream_fsm_9_init = 0; reg [33-1:0] _tmp_50; reg _tmp_51; - wire [32-1:0] _plus_data_52; + wire signed [32-1:0] _plus_data_52; wire _plus_valid_52; wire _plus_ready_52; assign _plus_ready_52 = (_tmp_50 > 0) && !_tmp_51; @@ -1041,7 +1041,7 @@ end end - reg [32-1:0] _plus_data_131; + reg signed [32-1:0] _plus_data_131; reg _plus_valid_131; wire _plus_ready_131; assign _tmp_28 = 1 && ((_plus_ready_131 || !_plus_valid_131) && (_tmp_26 && _tmp_38)); diff --git a/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py b/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py index 2a6dc597..d471dddb 100644 --- a/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py +++ b/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py @@ -588,7 +588,7 @@ localparam _mystream_fsm_9_init = 0; reg [33-1:0] _tmp_50; reg _tmp_51; - wire [32-1:0] _times_data_52; + wire signed [32-1:0] _times_data_52; wire _times_valid_52; wire _times_ready_52; assign _times_ready_52 = (_tmp_50 > 0) && !_tmp_51; @@ -1596,19 +1596,19 @@ end end - reg [32-1:0] _plus_data_275; + reg signed [32-1:0] _plus_data_275; reg _plus_valid_275; wire _plus_ready_275; assign _tmp_28 = 1 && ((_plus_ready_275 || !_plus_valid_275) && _tmp_26); - reg [32-1:0] _plus_data_276; + reg signed [32-1:0] _plus_data_276; reg _plus_valid_276; wire _plus_ready_276; assign _tmp_40 = 1 && ((_plus_ready_276 || !_plus_valid_276) && _tmp_38); - wire [32-1:0] _times_data_277; + wire signed [32-1:0] _times_data_277; wire _times_valid_277; wire _times_ready_277; - wire [64-1:0] _times_odata_277; - reg [64-1:0] _times_data_reg_277; + wire signed [64-1:0] _times_odata_277; + reg signed [64-1:0] _times_data_reg_277; assign _times_data_277 = _times_data_reg_277; wire _times_ovalid_277; reg _times_valid_reg_277; @@ -4393,15 +4393,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py b/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py index 568e7171..d33f508d 100644 --- a/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py +++ b/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py @@ -780,7 +780,7 @@ localparam _mystream_fsm_12_init = 0; reg [33-1:0] _tmp_78; reg _tmp_79; - wire [32-1:0] _plus_data_80; + wire signed [32-1:0] _plus_data_80; wire _plus_valid_80; wire _plus_ready_80; assign _plus_ready_80 = (_tmp_78 > 0) && !_tmp_79; @@ -1554,7 +1554,7 @@ end end - reg [32-1:0] _plus_data_229; + reg signed [32-1:0] _plus_data_229; reg _plus_valid_229; wire _plus_ready_229; assign _tmp_40 = 1 && ((_plus_ready_229 || !_plus_valid_229) && (_tmp_38 && _tmp_58)); diff --git a/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py b/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py index 980296b1..e97d8e77 100644 --- a/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py +++ b/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py @@ -589,7 +589,7 @@ localparam _mystream_fsm_10_init = 0; reg [33-1:0] _tmp_50; reg _tmp_51; - wire [32-1:0] _times_data_52; + wire signed [32-1:0] _times_data_52; wire _times_valid_52; wire _times_ready_52; assign _times_ready_52 = (_tmp_50 > 0) && !_tmp_51; @@ -1412,11 +1412,11 @@ end end - wire [32-1:0] _times_data_227; + wire signed [32-1:0] _times_data_227; wire _times_valid_227; wire _times_ready_227; - wire [64-1:0] _times_odata_227; - reg [64-1:0] _times_data_reg_227; + wire signed [64-1:0] _times_odata_227; + reg signed [64-1:0] _times_data_reg_227; assign _times_data_227 = _times_data_reg_227; wire _times_ovalid_227; reg _times_valid_reg_227; @@ -3769,15 +3769,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py b/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py index d690077d..7f9d0c11 100644 --- a/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py +++ b/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py @@ -605,7 +605,7 @@ reg [2-1:0] _tmp_64; reg _tmp_65; wire _tmp_all_valid_66; - wire [32-1:0] _reduceadd_data_67; + wire signed [32-1:0] _reduceadd_data_67; wire _reduceadd_valid_67; wire _reduceadd_ready_67; assign _reduceadd_ready_67 = (_tmp_64 > 0) && !_tmp_65 && _tmp_all_valid_66; @@ -1424,11 +1424,11 @@ assign __variable_data_141 = _tmp_133; assign __variable_valid_141 = _tmp_127; assign _tmp_129 = 1 && __variable_ready_141; - wire [32-1:0] _times_data_147; + wire signed [32-1:0] _times_data_147; wire _times_valid_147; wire _times_ready_147; - wire [64-1:0] _times_odata_147; - reg [64-1:0] _times_data_reg_147; + wire signed [64-1:0] _times_odata_147; + reg signed [64-1:0] _times_data_reg_147; assign _times_data_147 = _times_data_reg_147; wire _times_ovalid_147; reg _times_valid_reg_147; @@ -1453,7 +1453,7 @@ assign _tmp_28 = 1 && ((_times_ready_147 || !_times_valid_147) && (_tmp_26 && _tmp_45)); assign _tmp_47 = 1 && ((_times_ready_147 || !_times_valid_147) && (_tmp_26 && _tmp_45)); - reg [32-1:0] _reduceadd_data_148; + reg signed [32-1:0] _reduceadd_data_148; reg _reduceadd_valid_148; wire _reduceadd_ready_148; reg [12-1:0] _reduceadd_count_148; @@ -2681,15 +2681,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/thread_/stream_parameter_variable/test_thread_stream_parameter_variable.py b/tests/extension/thread_/stream_parameter_variable/test_thread_stream_parameter_variable.py index 05d4bfda..baf99002 100644 --- a/tests/extension/thread_/stream_parameter_variable/test_thread_stream_parameter_variable.py +++ b/tests/extension/thread_/stream_parameter_variable/test_thread_stream_parameter_variable.py @@ -590,7 +590,7 @@ localparam _mystream_fsm_11_init = 0; reg [33-1:0] _tmp_50; reg _tmp_51; - wire [32-1:0] _plus_data_52; + wire signed [32-1:0] _plus_data_52; wire _plus_valid_52; wire _plus_ready_52; assign _plus_ready_52 = (_tmp_50 > 0) && !_tmp_51; @@ -1045,12 +1045,12 @@ end end - reg [32-1:0] _plus_data_131; + reg signed [32-1:0] _plus_data_131; reg _plus_valid_131; wire _plus_ready_131; assign _tmp_28 = 1 && ((_plus_ready_131 || !_plus_valid_131) && (_tmp_26 && _tmp_38)); assign _tmp_40 = 1 && ((_plus_ready_131 || !_plus_valid_131) && (_tmp_26 && _tmp_38)); - reg [32-1:0] _plus_data_132; + reg signed [32-1:0] _plus_data_132; reg _plus_valid_132; wire _plus_ready_132; assign _plus_ready_131 = (_plus_ready_132 || !_plus_valid_132) && _plus_valid_131; diff --git a/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py b/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py index 73516a26..ee818803 100644 --- a/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py +++ b/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py @@ -604,7 +604,7 @@ localparam _mystream_fsm_7_init = 0; reg _tmp_64; reg _tmp_65; - wire [32-1:0] _plus_data_66; + wire signed [32-1:0] _plus_data_66; wire _plus_valid_66; wire _plus_ready_66; assign _plus_ready_66 = _tmp_65 && !_tmp_64; @@ -1110,7 +1110,7 @@ end end - reg [32-1:0] _plus_data_152; + reg signed [32-1:0] _plus_data_152; reg _plus_valid_152; wire _plus_ready_152; assign _tmp_28 = 1 && ((_plus_ready_152 || !_plus_valid_152) && (_tmp_26 && _tmp_45)); diff --git a/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py b/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py index fa0dd369..45e50edd 100644 --- a/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py +++ b/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py @@ -604,7 +604,7 @@ localparam _mystream_fsm_7_init = 0; reg _tmp_64; reg _tmp_65; - wire [32-1:0] _plus_data_66; + wire signed [32-1:0] _plus_data_66; wire _plus_valid_66; wire _plus_ready_66; assign _plus_ready_66 = _tmp_65 && !_tmp_64; @@ -1110,7 +1110,7 @@ end end - reg [32-1:0] _plus_data_152; + reg signed [32-1:0] _plus_data_152; reg _plus_valid_152; wire _plus_ready_152; assign _tmp_28 = 1 && ((_plus_ready_152 || !_plus_valid_152) && (_tmp_26 && _tmp_45)); diff --git a/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py b/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py index 47f66f4e..be7b27b9 100644 --- a/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py +++ b/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py @@ -531,7 +531,7 @@ reg [2-1:0] _tmp_25; reg _tmp_26; wire _tmp_all_valid_27; - wire [32-1:0] _reduceadd_data_28; + wire signed [32-1:0] _reduceadd_data_28; wire _reduceadd_valid_28; wire _reduceadd_ready_28; assign _reduceadd_ready_28 = (_tmp_25 > 0) && !_tmp_26 && _tmp_all_valid_27; @@ -1079,7 +1079,7 @@ assign __variable_data_87 = _tmp_79; assign __variable_valid_87 = _tmp_73; assign _tmp_75 = 1 && __variable_ready_87; - reg [32-1:0] _reduceadd_data_93; + reg signed [32-1:0] _reduceadd_data_93; reg _reduceadd_valid_93; wire _reduceadd_ready_93; reg [33-1:0] _reduceadd_count_93; diff --git a/tests/extension/thread_/stream_reuse/test_thread_stream_reuse.py b/tests/extension/thread_/stream_reuse/test_thread_stream_reuse.py index e0a93994..d1785efc 100644 --- a/tests/extension/thread_/stream_reuse/test_thread_stream_reuse.py +++ b/tests/extension/thread_/stream_reuse/test_thread_stream_reuse.py @@ -616,7 +616,7 @@ localparam _mystream_fsm_11_init = 0; reg [36-1:0] _tmp_56; reg _tmp_57; - wire [32-1:0] _plus_data_58; + wire signed [32-1:0] _plus_data_58; wire _plus_valid_58; wire _plus_ready_58; assign _plus_ready_58 = (_tmp_56 > 0) && !_tmp_57; @@ -1085,29 +1085,29 @@ end end - reg [32-1:0] _plus_data_141; + reg signed [32-1:0] _plus_data_141; reg _plus_valid_141; wire _plus_ready_141; assign _tmp_29 = 1 && ((_plus_ready_141 || !_plus_valid_141) && (_tmp_26 && _tmp_27)); assign _tmp_30 = 1 && ((_plus_ready_141 || !_plus_valid_141) && (_tmp_26 && _tmp_27)); - reg [32-1:0] __delay_data_142; + reg signed [32-1:0] __delay_data_142; reg __delay_valid_142; wire __delay_ready_142; assign _tmp_44 = 1 && ((__delay_ready_142 || !__delay_valid_142) && _tmp_41); - reg [32-1:0] __delay_data_143; + reg signed [32-1:0] __delay_data_143; reg __delay_valid_143; wire __delay_ready_143; assign _tmp_45 = 1 && ((__delay_ready_143 || !__delay_valid_143) && _tmp_42); - reg [32-1:0] _plus_data_144; + reg signed [32-1:0] _plus_data_144; reg _plus_valid_144; wire _plus_ready_144; assign _plus_ready_141 = (_plus_ready_144 || !_plus_valid_144) && (_plus_valid_141 && __delay_valid_142); assign __delay_ready_142 = (_plus_ready_144 || !_plus_valid_144) && (_plus_valid_141 && __delay_valid_142); - reg [32-1:0] __delay_data_145; + reg signed [32-1:0] __delay_data_145; reg __delay_valid_145; wire __delay_ready_145; assign __delay_ready_143 = (__delay_ready_145 || !__delay_valid_145) && __delay_valid_143; - reg [32-1:0] _plus_data_146; + reg signed [32-1:0] _plus_data_146; reg _plus_valid_146; wire _plus_ready_146; assign _plus_ready_144 = (_plus_ready_146 || !_plus_valid_146) && (_plus_valid_144 && __delay_valid_145); diff --git a/tests/extension/thread_/stream_reuse_pattern/test_thread_stream_reuse_pattern.py b/tests/extension/thread_/stream_reuse_pattern/test_thread_stream_reuse_pattern.py index c65bfd55..74746baa 100644 --- a/tests/extension/thread_/stream_reuse_pattern/test_thread_stream_reuse_pattern.py +++ b/tests/extension/thread_/stream_reuse_pattern/test_thread_stream_reuse_pattern.py @@ -632,7 +632,7 @@ localparam _mystream_fsm_9_init = 0; reg [10-1:0] _tmp_62; reg _tmp_63; - wire [32-1:0] _plus_data_64; + wire signed [32-1:0] _plus_data_64; wire _plus_valid_64; wire _plus_ready_64; assign _plus_ready_64 = (_tmp_62 > 0) && !_tmp_63; @@ -1071,7 +1071,7 @@ end end - reg [32-1:0] _plus_data_143; + reg signed [32-1:0] _plus_data_143; reg _plus_valid_143; wire _plus_ready_143; assign _tmp_28 = 1 && ((_plus_ready_143 || !_plus_valid_143) && (_tmp_26 && _tmp_44)); diff --git a/tests/extension/thread_/stream_stride/test_thread_stream_stride.py b/tests/extension/thread_/stream_stride/test_thread_stream_stride.py index 81c065de..f1f6a829 100644 --- a/tests/extension/thread_/stream_stride/test_thread_stream_stride.py +++ b/tests/extension/thread_/stream_stride/test_thread_stream_stride.py @@ -593,7 +593,7 @@ reg [2-1:0] _tmp_52; reg _tmp_53; wire _tmp_all_valid_54; - wire [32-1:0] _reduceadd_data_55; + wire signed [32-1:0] _reduceadd_data_55; wire _reduceadd_valid_55; wire _reduceadd_ready_55; assign _reduceadd_ready_55 = (_tmp_52 > 0) && !_tmp_53 && _tmp_all_valid_54; @@ -1321,11 +1321,11 @@ assign __variable_data_131 = _tmp_123; assign __variable_valid_131 = _tmp_117; assign _tmp_119 = 1 && __variable_ready_131; - wire [32-1:0] _times_data_137; + wire signed [32-1:0] _times_data_137; wire _times_valid_137; wire _times_ready_137; - wire [64-1:0] _times_odata_137; - reg [64-1:0] _times_data_reg_137; + wire signed [64-1:0] _times_odata_137; + reg signed [64-1:0] _times_data_reg_137; assign _times_data_137 = _times_data_reg_137; wire _times_ovalid_137; reg _times_valid_reg_137; @@ -1350,7 +1350,7 @@ assign _tmp_30 = 1 && ((_times_ready_137 || !_times_valid_137) && (_tmp_28 && _tmp_40)); assign _tmp_42 = 1 && ((_times_ready_137 || !_times_valid_137) && (_tmp_28 && _tmp_40)); - reg [32-1:0] _reduceadd_data_138; + reg signed [32-1:0] _reduceadd_data_138; reg _reduceadd_valid_138; wire _reduceadd_ready_138; reg [33-1:0] _reduceadd_count_138; @@ -2616,15 +2616,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py b/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py index ff7eda5e..91940a56 100644 --- a/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py +++ b/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py @@ -552,7 +552,7 @@ localparam _mystream_fsm_5_init = 0; reg _tmp_32; reg _tmp_33; - wire [32-1:0] __variable_data_34; + wire signed [32-1:0] __variable_data_34; wire __variable_valid_34; wire __variable_ready_34; assign __variable_ready_34 = _tmp_33 && !_tmp_32; diff --git a/tests/extension/thread_/stream_when/test_thread_stream_when.py b/tests/extension/thread_/stream_when/test_thread_stream_when.py index de98ce1f..7930c42b 100644 --- a/tests/extension/thread_/stream_when/test_thread_stream_when.py +++ b/tests/extension/thread_/stream_when/test_thread_stream_when.py @@ -589,7 +589,7 @@ reg [2-1:0] _tmp_50; reg _tmp_51; wire _tmp_all_valid_52; - wire [32-1:0] _reduceadd_data_53; + wire signed [32-1:0] _reduceadd_data_53; wire _reduceadd_valid_53; wire _reduceadd_ready_53; assign _reduceadd_ready_53 = (_tmp_50 > 0) && !_tmp_51 && _tmp_all_valid_52; @@ -1313,11 +1313,11 @@ assign __variable_data_127 = _tmp_119; assign __variable_valid_127 = _tmp_113; assign _tmp_115 = 1 && __variable_ready_127; - wire [32-1:0] _times_data_133; + wire signed [32-1:0] _times_data_133; wire _times_valid_133; wire _times_ready_133; - wire [64-1:0] _times_odata_133; - reg [64-1:0] _times_data_reg_133; + wire signed [64-1:0] _times_odata_133; + reg signed [64-1:0] _times_data_reg_133; assign _times_data_133 = _times_data_reg_133; wire _times_ovalid_133; reg _times_valid_reg_133; @@ -1342,7 +1342,7 @@ assign _tmp_28 = 1 && ((_times_ready_133 || !_times_valid_133) && (_tmp_26 && _tmp_38)); assign _tmp_40 = 1 && ((_times_ready_133 || !_times_valid_133) && (_tmp_26 && _tmp_38)); - reg [32-1:0] _reduceadd_data_134; + reg signed [32-1:0] _reduceadd_data_134; reg _reduceadd_valid_134; wire _reduceadd_ready_134; reg [33-1:0] _reduceadd_count_134; @@ -2584,15 +2584,15 @@ output [64-1:0] c ); - reg [32-1:0] _a; - reg [32-1:0] _b; + reg signed [32-1:0] _a; + reg signed [32-1:0] _b; reg signed [64-1:0] _tmpval0; reg signed [64-1:0] _tmpval1; reg signed [64-1:0] _tmpval2; reg signed [64-1:0] _tmpval3; reg signed [64-1:0] _tmpval4; wire signed [64-1:0] rslt; - assign rslt = $signed({ 1'd0, _a }) * $signed({ 1'd0, _b }); + assign rslt = _a * _b; assign c = _tmpval4; always @(posedge CLK) begin diff --git a/tests/extension/types_/axi_/axi_to_ram/test_types_axi_axi_to_ram.py b/tests/extension/types_/axi_/axi_to_ram/test_types_axi_axi_to_ram.py index 792b21b2..bf3906b5 100644 --- a/tests/extension/types_/axi_/axi_to_ram/test_types_axi_axi_to_ram.py +++ b/tests/extension/types_/axi_/axi_to_ram/test_types_axi_axi_to_ram.py @@ -248,7 +248,7 @@ assign myaxi_rready = _tmp_1 && _tmp_2; reg [8-1:0] _tmp_3; reg _tmp_4; - wire [32-1:0] _reduceadd_data_5; + wire signed [32-1:0] _reduceadd_data_5; wire _reduceadd_valid_5; wire _reduceadd_ready_5; assign _reduceadd_ready_5 = (_tmp_3 > 0) && !_tmp_4; @@ -269,7 +269,7 @@ reg _tmp_15; reg _tmp_16; reg [8-1:0] _tmp_17; - wire [32-1:0] __variable_data_18; + wire signed [32-1:0] __variable_data_18; wire __variable_valid_18; wire __variable_ready_18; assign __variable_ready_18 = 1; @@ -399,7 +399,7 @@ assign __variable_valid_19 = _tmp_7; assign _tmp_9 = 1 && __variable_ready_19; reg [1-1:0] __prev_data_20; - reg [32-1:0] _reduceadd_data_21; + reg signed [32-1:0] _reduceadd_data_21; reg _reduceadd_valid_21; wire _reduceadd_ready_21; assign _tmp_1 = 1 && ((_reduceadd_ready_21 || !_reduceadd_valid_21) && (myaxi_rvalid && myaxi_rvalid)); diff --git a/tests/extension/types_/axi_/ram_to_axi/test_types_axi_ram_to_axi.py b/tests/extension/types_/axi_/ram_to_axi/test_types_axi_ram_to_axi.py index 9d2c660f..6a219402 100644 --- a/tests/extension/types_/axi_/ram_to_axi/test_types_axi_ram_to_axi.py +++ b/tests/extension/types_/axi_/ram_to_axi/test_types_axi_ram_to_axi.py @@ -306,7 +306,7 @@ assign myaxi_rready = _tmp_1 && _tmp_2; reg [8-1:0] _tmp_3; reg _tmp_4; - wire [32-1:0] _reduceadd_data_5; + wire signed [32-1:0] _reduceadd_data_5; wire _reduceadd_valid_5; wire _reduceadd_ready_5; assign _reduceadd_ready_5 = (_tmp_3 > 0) && !_tmp_4; @@ -331,7 +331,7 @@ reg _tmp_17; reg [8-1:0] _tmp_18; reg _tmp_19; - wire [32-1:0] __variable_data_20; + wire signed [32-1:0] __variable_data_20; wire __variable_valid_20; wire __variable_ready_20; assign __variable_ready_20 = (_tmp_6 > 0) && (myaxi_wready || !myaxi_wvalid); @@ -490,7 +490,7 @@ assign __variable_valid_20 = _tmp_7; assign _tmp_9 = 1 && __variable_ready_20; reg [1-1:0] __prev_data_21; - reg [32-1:0] _reduceadd_data_22; + reg signed [32-1:0] _reduceadd_data_22; reg _reduceadd_valid_22; wire _reduceadd_ready_22; assign _tmp_1 = 1 && ((_reduceadd_ready_22 || !_reduceadd_valid_22) && (myaxi_rvalid && myaxi_rvalid)); diff --git a/tests/extension/types_/axi_/read_dataflow/test_types_axi_read_dataflow.py b/tests/extension/types_/axi_/read_dataflow/test_types_axi_read_dataflow.py index 3b973ec1..502cd058 100644 --- a/tests/extension/types_/axi_/read_dataflow/test_types_axi_read_dataflow.py +++ b/tests/extension/types_/axi_/read_dataflow/test_types_axi_read_dataflow.py @@ -206,7 +206,7 @@ wire _tmp_1; wire _tmp_2; assign myaxi_rready = _tmp_1 && _tmp_2; - wire [32-1:0] _reduceadd_data_3; + wire signed [32-1:0] _reduceadd_data_3; wire _reduceadd_valid_3; wire _reduceadd_ready_3; assign _reduceadd_ready_3 = 1; @@ -260,7 +260,7 @@ assign __variable_data_4 = myaxi_rlast; assign __variable_valid_4 = myaxi_rvalid; reg [1-1:0] __prev_data_5; - reg [32-1:0] _reduceadd_data_6; + reg signed [32-1:0] _reduceadd_data_6; reg _reduceadd_valid_6; wire _reduceadd_ready_6; assign _tmp_1 = 1 && ((_reduceadd_ready_6 || !_reduceadd_valid_6) && (myaxi_rvalid && myaxi_rvalid)); diff --git a/tests/extension/types_/ram_manager_/read_dataflow/test_types_ram_manager_read_dataflow.py b/tests/extension/types_/ram_manager_/read_dataflow/test_types_ram_manager_read_dataflow.py index 65223fe3..bae05820 100644 --- a/tests/extension/types_/ram_manager_/read_dataflow/test_types_ram_manager_read_dataflow.py +++ b/tests/extension/types_/ram_manager_/read_dataflow/test_types_ram_manager_read_dataflow.py @@ -5,7 +5,7 @@ expected_verilog = """ module test; - + reg CLK; reg RST; @@ -100,7 +100,7 @@ reg _tmp_12; reg _tmp_13; reg [7-1:0] _tmp_14; - wire [32-1:0] __variable_data_15; + wire signed [32-1:0] __variable_data_15; wire __variable_valid_15; wire __variable_ready_15; assign __variable_ready_15 = 1; diff --git a/tests/extension/types_/ram_manager_/read_dataflow_reuse/test_types_ram_manager_read_dataflow_reuse.py b/tests/extension/types_/ram_manager_/read_dataflow_reuse/test_types_ram_manager_read_dataflow_reuse.py index 8b55a1d5..ade525da 100644 --- a/tests/extension/types_/ram_manager_/read_dataflow_reuse/test_types_ram_manager_read_dataflow_reuse.py +++ b/tests/extension/types_/ram_manager_/read_dataflow_reuse/test_types_ram_manager_read_dataflow_reuse.py @@ -113,11 +113,11 @@ reg __tmp_fsm_0_cond_7_4_1; reg __tmp_fsm_0_cond_7_4_2; reg __tmp_fsm_0_cond_10_5_1; - wire [32-1:0] __variable_data_18; + wire signed [32-1:0] __variable_data_18; wire __variable_valid_18; wire __variable_ready_18; assign __variable_ready_18 = 1; - wire [32-1:0] __variable_data_19; + wire signed [32-1:0] __variable_data_19; wire __variable_valid_19; wire __variable_ready_19; assign __variable_ready_19 = 1; diff --git a/tests/extension/types_/ram_manager_/rtl_dataflow/test_types_ram_manager_rtl_dataflow.py b/tests/extension/types_/ram_manager_/rtl_dataflow/test_types_ram_manager_rtl_dataflow.py index 8311b639..ea769661 100644 --- a/tests/extension/types_/ram_manager_/rtl_dataflow/test_types_ram_manager_rtl_dataflow.py +++ b/tests/extension/types_/ram_manager_/rtl_dataflow/test_types_ram_manager_rtl_dataflow.py @@ -79,14 +79,14 @@ localparam xfsm_init = 0; reg [32-1:0] xaddr; reg [32-1:0] xcount; - wire [32-1:0] xdata; + wire signed [32-1:0] xdata; wire xvalid; wire xready; - reg [32-1:0] _plus_data_0; + reg signed [32-1:0] _plus_data_0; reg _plus_valid_0; wire _plus_ready_0; assign xready = (_plus_ready_0 || !_plus_valid_0) && xvalid; - wire [32-1:0] ydata; + wire signed [32-1:0] ydata; wire yvalid; wire yread; assign ydata = _plus_data_0; diff --git a/veriloggen/dataflow/dtypes.py b/veriloggen/dataflow/dtypes.py index c0b7590e..2e89a4fc 100644 --- a/veriloggen/dataflow/dtypes.py +++ b/veriloggen/dataflow/dtypes.py @@ -38,18 +38,18 @@ def Constant(value, fixed=True, point=0): raise TypeError("Unsupported type for Constant '%s'" % str(type(value))) -def Variable(data=None, valid=None, ready=None, width=32, point=0, signed=False): +def Variable(data=None, valid=None, ready=None, width=32, point=0, signed=True): return _Variable(data, valid, ready, width, point, signed) -def Parameter(name, value, width=32, point=0, signed=False): +def Parameter(name, value, width=32, point=0, signed=True): """ parameter with an immediate value """ if not isinstance(name, str): raise TypeError("'name' must be str, not '%s'" % str(type(name))) return _ParameterVariable(name, width, point, signed, value=value) -def ParameterVariable(data, width=32, point=0, signed=False): +def ParameterVariable(data, width=32, point=0, signed=True): """ parameter with an existing object """ if isinstance(data, float): return Constant(data, point=point) @@ -1852,7 +1852,7 @@ def eval(self): class LUT(_SpecialOperator): latency = 1 - def __init__(self, address, patterns, width=32, point=0, signed=False): + def __init__(self, address, patterns, width=32, point=0, signed=True): _SpecialOperator.__init__(self, address) self.op = None self.width = width @@ -2058,7 +2058,7 @@ def _implement(self, m, seq): class _Variable(_Numeric): - def __init__(self, data=None, valid=None, ready=None, width=32, point=0, signed=False): + def __init__(self, data=None, valid=None, ready=None, width=32, point=0, signed=True): _Numeric.__init__(self) self.input_data = data self.input_valid = valid @@ -2247,7 +2247,7 @@ def __getattribute__(self, attr): class _ParameterVariable(_Variable): - def __init__(self, data, width=32, point=0, signed=False, value=None): + def __init__(self, data, width=32, point=0, signed=True, value=None): if isinstance(data, _Numeric): raise TypeError( "_ParameterVariable cannot receive type '%s'" % str(type(data))) @@ -2291,7 +2291,7 @@ class _Accumulator(_UnaryOperator): ops = (vtypes.Plus, ) def __init__(self, right, size=None, initval=None, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): self.size = _to_constant(size) if size is not None else None @@ -2489,7 +2489,7 @@ class ReduceAdd(_Accumulator): ops = (vtypes.Plus, ) def __init__(self, right, size=None, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) @@ -2498,7 +2498,7 @@ class ReduceSub(_Accumulator): ops = (vtypes.Minus, ) def __init__(self, right, size=None, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) @@ -2508,7 +2508,7 @@ class ReduceMul(_Accumulator): ops = (vtypes.Times, ) def __init__(self, right, size=None, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) @@ -2518,7 +2518,7 @@ class ReduceDiv(_Accumulator): ops = () def __init__(self, right, size=None, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): raise NotImplementedError() _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) @@ -2527,7 +2527,7 @@ def __init__(self, right, size=None, initval=0, class ReduceCustom(_Accumulator): def __init__(self, ops, right, size=None, initval=0, - enable=None, reset=None, width=32, signed=False, label=None): + enable=None, reset=None, width=32, signed=True, label=None): _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) if not isinstance(ops, (tuple, list)): @@ -2572,7 +2572,7 @@ def __init__(self, size, control=None, enable=None, reset=None): def _ReduceValid(cls, right, size, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): data = cls(right, size, initval, enable, reset, width, signed) @@ -2582,7 +2582,7 @@ def _ReduceValid(cls, right, size, initval=0, def ReduceAddValid(right, size, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): cls = ReduceAdd return _ReduceValid(cls, right, size, initval, @@ -2590,7 +2590,7 @@ def ReduceAddValid(right, size, initval=0, def ReduceSubValid(right, size, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): cls = ReduceSub return _ReduceValid(cls, right, size, initval, @@ -2598,7 +2598,7 @@ def ReduceSubValid(right, size, initval=0, def ReduceMulValid(right, size, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): cls = ReduceMul return _ReduceValid(cls, right, size, initval, @@ -2606,7 +2606,7 @@ def ReduceMulValid(right, size, initval=0, def ReduceDivValid(right, size, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): cls = ReduceDiv return _ReduceValid(cls, right, size, initval, @@ -2614,7 +2614,7 @@ def ReduceDivValid(right, size, initval=0, def ReduceCustomValid(ops, right, size, initval=0, - enable=None, reset=None, width=32, signed=False): + enable=None, reset=None, width=32, signed=True): data = ReduceCustom(ops, right, size, initval, enable, reset, width, signed) diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index 4a737508..51f08c26 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -4,10 +4,12 @@ from functools import partial from collections import OrderedDict from math import log + import veriloggen.core.vtypes as vtypes import veriloggen.types.fixed as fx import veriloggen.types.rom as rom from veriloggen.seq.seq import make_condition as _make_condition + from . import mul from . import div @@ -36,18 +38,18 @@ def Constant(value, fixed=True, point=0): raise TypeError("Unsupported type for Constant '%s'" % str(type(value))) -def Variable(data=None, width=32, point=0, signed=False): +def Variable(data=None, width=32, point=0, signed=True): return _Variable(data, width, point, signed) -def Parameter(name, value, width=32, point=0, signed=False): +def Parameter(name, value, width=32, point=0, signed=True): """ parameter with an immediate value """ if not isinstance(name, str): raise TypeError("'name' must be str, not '%s'" % str(tyep(name))) return _ParameterVariable(name, width, point, signed, value=value) -def ParameterVariable(data, width=32, point=0, signed=False): +def ParameterVariable(data, width=32, point=0, signed=True): """ parameter with an existing object """ if isinstance(data, float): return Constant(data, point=point) @@ -1184,6 +1186,7 @@ def OrList(*args): left = Lor(left, right) return left + Ands = AndList Ors = OrList @@ -1462,7 +1465,7 @@ def eval(self): class LUT(_SpecialOperator): latency = 1 - def __init__(self, address, patterns, width=32, point=0, signed=False): + def __init__(self, address, patterns, width=32, point=0, signed=True): _SpecialOperator.__init__(self, address) self.op = None self.width = width @@ -1601,7 +1604,7 @@ def _implement(self, m, seq, svalid=None, senable=None): class _Variable(_Numeric): - def __init__(self, data=None, width=32, point=0, signed=False): + def __init__(self, data=None, width=32, point=0, signed=True): _Numeric.__init__(self) self.input_data = data if isinstance(self.input_data, _Numeric): @@ -1727,7 +1730,7 @@ def __getattribute__(self, attr): class _ParameterVariable(_Variable): - def __init__(self, data, width=32, point=0, signed=False, value=None): + def __init__(self, data, width=32, point=0, signed=True, value=None): if isinstance(data, _Numeric): raise TypeError( "_ParameterVariable cannot receive type '%s'" % str(type(data))) @@ -1767,18 +1770,32 @@ class _Accumulator(_UnaryOperator): latency = 1 ops = (vtypes.Plus, ) - def __init__(self, right, initval=None, enable=None, reset=None, width=32, signed=False): - self.initval = _to_constant( - initval) if initval is not None else _to_constant(0) + def __init__(self, right, size=None, initval=None, + enable=None, reset=None, width=32, signed=True): + + self.size = _to_constant(size) if size is not None else None + + if (self.size is not None and + not isinstance(self.size, _Constant) and + not isinstance(self.size, _ParameterVariable)): + raise TypeError("size must be _Constant or _ParameterVariable, not '%s'" % + str(type(self.size))) + + self.initval = (_to_constant(initval) + if initval is not None else _to_constant(0)) + + if not isinstance(self.initval, _Constant): + raise TypeError("initval must be Constant, not '%s'" % + str(type(self.initval))) + self.enable = _to_constant(enable) if self.enable is not None: self.enable._add_sink(self) + self.reset = _to_constant(reset) if self.reset is not None: self.reset._add_sink(self) - if not isinstance(self.initval, _Constant): - raise TypeError("initval must be Constant, not '%s'" % - str(type(self.initval))) + _UnaryOperator.__init__(self, right) self.width = width self.signed = signed @@ -1801,19 +1818,32 @@ def _implement(self, m, seq, svalid=None, senable=None): raise ValueError("Latency mismatch '%d' vs '%s'" % (self.latency, 1)) + size_data = self.size.sig_data if self.size is not None else None initval_data = self.initval.sig_data width = self.bit_length() signed = self.get_signed() - rdata = self.right.sig_data - enabledata = self.enable.sig_data if self.enable is not None else None - resetdata = self.reset.sig_data if self.reset is not None else None + # for Pulse + if not self.ops and self.size is not None: + width = 1 data = m.Reg(self.name('data'), width, initval=initval_data, signed=signed) + + if self.size is not None: + count = m.Reg(self.name('count'), + size_data.bit_length() + 1, initval=0) + next_count_value = vtypes.Mux(count == size_data - 1, + 0, count + 1) + count_zero = (count == 0) + self.sig_data = data + rdata = self.right.sig_data + enabledata = self.enable.sig_data if self.enable is not None else None + resetdata = self.reset.sig_data if self.reset is not None else None + value = data for op in self.ops: if not isinstance(op, type): @@ -1827,11 +1857,11 @@ def _implement(self, m, seq, svalid=None, senable=None): raise TypeError("Operator '%s' returns unsupported object type '%s'." % (str(op), str(type(value)))) - # for Ireg - if not self.ops: - value = rdata + # for Pulse + if not self.ops and self.size is not None: + value = (count == (size_data - 1)) - if self.reset is not None: + if self.reset is not None or self.size is not None: reset_value = initval_data for op in self.ops: if not isinstance(op, type): @@ -1845,75 +1875,101 @@ def _implement(self, m, seq, svalid=None, senable=None): raise TypeError("Operator '%s' returns unsupported object type '%s'." % (str(op), str(type(reset_value)))) + if not self.ops and self.size is not None: + reset_value = (count == (size_data - 1)) + if self.enable is not None: enable_cond = _and_vars(svalid, senable, enabledata) seq(data(value), cond=enable_cond) + + if self.size is not None: + seq(count(next_count_value), cond=enable_cond) + else: enable_cond = _and_vars(svalid, senable) seq(data(value), cond=enable_cond) + if self.size is not None: + seq(count(next_count_value), cond=enable_cond) + if self.reset is not None: if self.enable is None: reset_cond = _and_vars(svalid, senable, resetdata) seq(data(reset_value), cond=reset_cond) + + if self.size is not None: + seq(count(0), cond=reset_cond) + reset_cond = _and_vars(svalid, senable, count_zero) + seq(data(reset_value), cond=reset_cond) + else: reset_cond = _and_vars(svalid, senable, resetdata) seq(data(initval_data), cond=reset_cond) + reset_enable_cond = _and_vars( svalid, senable, enabledata, resetdata) seq(data(reset_value), cond=reset_enable_cond) + if self.size is not None: + seq(count(0), cond=reset_enable_cond) + reset_enable_cond = _and_vars( + svalid, senable, enabledata, count_zero) + seq(data(reset_value), cond=reset_enable_cond) -class Ireg(_Accumulator): - ops = () - - def __init__(self, right, initval=0, enable=None, reset=None, width=32, signed=False): - _Accumulator.__init__(self, right, initval, - enable, reset, width, signed) - self.label = 'reg' + elif self.size is not None: + if self.enable is not None: + reset_enable_cond = _and_vars( + svalid, senable, enabledata, count_zero) + seq(data(reset_value), cond=reset_enable_cond) + else: + reset_cond = _and_vars(svalid, senable, count_zero) + seq(data(reset_value), cond=reset_cond) -class Iadd(_Accumulator): +class ReduceAdd(_Accumulator): ops = (vtypes.Plus, ) - def __init__(self, right, initval=0, enable=None, reset=None, width=32, signed=False): - _Accumulator.__init__(self, right, initval, + def __init__(self, right, size=None, initval=0, + enable=None, reset=None, width=32, signed=True): + _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) -class Isub(_Accumulator): +class ReduceSub(_Accumulator): ops = (vtypes.Minus, ) - def __init__(self, right, initval=0, enable=None, reset=None, width=32, signed=False): - _Accumulator.__init__(self, right, initval, + def __init__(self, right, size=None, initval=0, + enable=None, reset=None, width=32, signed=True): + _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) -class Imul(_Accumulator): - #latency = 6 +class ReduceMul(_Accumulator): latency = 1 ops = (vtypes.Times, ) - def __init__(self, right, initval=1, enable=None, reset=None, width=32, signed=False): - _Accumulator.__init__(self, right, initval, + def __init__(self, right, size=None, initval=0, + enable=None, reset=None, width=32, signed=True): + _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) -class Idiv(_Accumulator): +class ReduceDiv(_Accumulator): latency = 32 - op = () + ops = () - def __init__(self, right, initval=1, enable=None, reset=None, width=32, signed=False): + def __init__(self, right, size=None, initval=0, + enable=None, reset=None, width=32, signed=True): raise NotImplementedError() - _Accumulator.__init__(self, right, initval, + _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) -class Icustom(_Accumulator): +class ReduceCustom(_Accumulator): - def __init__(self, ops, right, initval=0, enable=None, reset=None, - width=32, signed=False, label=None): - _Accumulator.__init__(self, right, initval, + def __init__(self, ops, right, size=None, initval=0, + enable=None, reset=None, width=32, signed=True, label=None): + _Accumulator.__init__(self, right, size, initval, enable, reset, width, signed) if not isinstance(ops, (tuple, list)): ops = tuple([ops]) @@ -1921,6 +1977,93 @@ def __init__(self, ops, right, initval=0, enable=None, reset=None, self.label = label +class Counter(_Accumulator): + + def __init__(self, step=1, size=None, initval=0, + control=None, enable=None, reset=None, width=32, signed=False): + + self.ops = (lambda x, y: x + step, ) + + if control is None: + control = 0 + + initval -= step + + _Accumulator.__init__(self, control, size, initval, + enable, reset, width, signed) + self.label = 'Counter' + + +class Pulse(_Accumulator): + ops = () + + def __init__(self, size, control=None, enable=None, reset=None): + + if control is None: + control = 0 + + step = 1 + initval = 0 + width = 1 + signed = False + + _Accumulator.__init__(self, control, size, initval, + enable, reset, width, signed) + self.label = 'Pulse' + + +def _ReduceValid(cls, right, size, initval=0, + enable=None, reset=None, width=32, signed=True): + + data = cls(right, size, initval, + enable, reset, width, signed) + valid = Pulse(size, right, enable, reset) + + return data, valid + + +def ReduceAddValid(right, size, initval=0, + enable=None, reset=None, width=32, signed=True): + + cls = ReduceAdd + return _ReduceValid(cls, right, size, initval, + enable, reset, width, signed) + + +def ReduceSubValid(right, size, initval=0, + enable=None, reset=None, width=32, signed=True): + + cls = ReduceSub + return _ReduceValid(cls, right, size, initval, + enable, reset, width, signed) + + +def ReduceMulValid(right, size, initval=0, + enable=None, reset=None, width=32, signed=True): + + cls = ReduceMul + return _ReduceValid(cls, right, size, initval, + enable, reset, width, signed) + + +def ReduceDivValid(right, size, initval=0, + enable=None, reset=None, width=32, signed=True): + + cls = ReduceDiv + return _ReduceValid(cls, right, size, initval, + enable, reset, width, signed) + + +def ReduceCustomValid(ops, right, size, initval=0, + enable=None, reset=None, width=32, signed=True): + + data = ReduceCustom(ops, right, size, initval, + enable, reset, width, signed) + valid = Pulse(size, right, enable, reset) + + return data, valid + + class Int(_Constant): def __init__(self, value, signed=True): @@ -1968,101 +2111,6 @@ def _set_attributes(self): self.signed = False -def _RegionAcc(op, right, size, initval=0, enable=None, reset=None, - width=32, signed=False, filter=False, filter_value=0): - - counter = Counter(1, maxval=size, initval=0, enable=enable, reset=reset) - - valid = (counter == size - 1).prev(1) - - if enable is not None: - valid = Land(valid, enable) - - if reset is None: - reset = valid.prev(1) - else: - reset = Lor(reset, valid.prev(1)) - - comp = op(right, initval=initval, enable=enable, - reset=reset, width=width, signed=signed) - if filter: - comp = Mux(valid, comp, filter_value) - - return comp, valid - - -def RegionReg(right, size, initval=0, enable=None, reset=None, - width=32, signed=False, filter=False, filter_value=0): - return _RegionAcc(Ireg, right, size, initval, enable, reset, - width, signed, filter, filter_value) - - -def RegionAdd(right, size, initval=0, enable=None, reset=None, - width=32, signed=False, filter=False, filter_value=0): - return _RegionAcc(Iadd, right, size, initval, enable, reset, - width, signed, filter, filter_value) - - -def RegionSub(right, size, initval=0, enable=None, reset=None, - width=32, signed=False, filter=False, filter_value=0): - return _RegionAcc(Isub, right, size, initval, enable, reset, - width, signed, filter, filter_value) - - -def RegionMul(right, size, initval=0, enable=None, reset=None, - width=32, signed=False, filter=False, filter_value=0): - return _RegionAcc(Imul, right, size, initval, enable, reset, - width, signed, filter, filter_value) - - -def RegionDiv(right, size, initval=0, enable=None, reset=None, - width=32, signed=False, filter=False, filter_value=0): - return _RegionAcc(Idiv, right, size, initval, enable, reset, - width, signed, filter, filter_value) - - -def RegionCustom(ops, right, size, initval=0, enable=None, reset=None, - width=32, signed=False, filter=False, filter_value=0): - op = partial(Icustom, ops) - return _RegionAcc(op, right, size, initval, enable, reset, - width, signed, filter, filter_value) - - -def Counter(step=None, maxval=None, initval=0, enable=None, reset=None, width=32, signed=False): - if step is None: - step = 1 - - step = _to_constant(step) - if not isinstance(step, _Constant): - raise TypeError("'step' must be constant") - raw_step = step.value - - initval = _to_constant(initval) - if not isinstance(initval, _Constant): - raise TypeError("'initval' must be constant") - raw_initval = initval.value - - if maxval is None: - return Icustom(lambda a, b: a + b, - step, initval=initval, enable=enable, reset=reset, - width=width, signed=signed, - label='Counter') - - #maxval = _to_constant(maxval) - # if not isinstance(maxval, _Constant): - # raise TypeError("'maxval' must be constant") - #raw_maxval = maxval.value - - # return Icustom(lambda a, b: vtypes.Mux(a >= raw_maxval - raw_step, raw_initval, a + b), - # step, initval=initval, enable=enable, reset=reset, - # width=width, signed=signed, - # label='Counter') - return Icustom(lambda a, b: vtypes.Mux(a >= maxval - raw_step, raw_initval, a + b), - step, initval=initval, enable=enable, reset=reset, - width=width, signed=signed, - label='Counter') - - def make_condition(*cond, **kwargs): ready = kwargs['ready'] if 'ready' in kwargs else None @@ -2165,6 +2213,6 @@ def _from_vtypes_value(value): return Str(value.value) if isinstance(value, vtypes._Numeric): - return Variable(value) + return ParameterVariable(value) raise TypeError("Unsupported type '%s'" % str(type(value))) diff --git a/veriloggen/thread/fixed.py b/veriloggen/thread/fixed.py index 6388745d..16366322 100644 --- a/veriloggen/thread/fixed.py +++ b/veriloggen/thread/fixed.py @@ -18,11 +18,11 @@ def as_fixed(fsm, value, point, signed=True): return fixed.as_fixed(value, point, signed) -def to_fixed(fsm, value, point, signed=False): +def to_fixed(fsm, value, point, signed=True): return fixed.to_fixed(value, point, signed) -def fixed_to_int(fsm, value, point, signed=False): +def fixed_to_int(fsm, value, point, signed=True): return fixed.fixed_to_int(value, point, signed) @@ -30,5 +30,5 @@ def fixed_to_int_low(fsm, value, point): return fixed.fixed_to_int_low(value, point) -def fixed_to_real(fsm, value, point, signed=False): +def fixed_to_real(fsm, value, point, signed=True): return fixed.fixed_to_real(value, point, signed) diff --git a/veriloggen/thread/stream.py b/veriloggen/thread/stream.py index c83b2a42..7d9f4de9 100644 --- a/veriloggen/thread/stream.py +++ b/veriloggen/thread/stream.py @@ -293,7 +293,7 @@ def _synthesize_run_fsm(self, parent_fsm, args, kwargs, cond=None): # stream control methods def read(self, obj, addr, size, - stride=1, point=0, signed=False, port=0, with_last=False): + stride=1, point=0, signed=True, port=0, with_last=False): done_flag = self.m.Reg(compiler._tmp_name('_'.join(['', self.name, 'done_flag'])), initval=0) @@ -332,7 +332,7 @@ def read(self, obj, addr, size, return rdata def read_pattern(self, obj, addr, pattern, - point=0, signed=False, port=0, with_last=False): + point=0, signed=True, port=0, with_last=False): done_flag = self.m.Reg(compiler._tmp_name('_'.join(['', self.name, 'done_flag'])), initval=0) @@ -369,7 +369,7 @@ def read_pattern(self, obj, addr, pattern, return rdata def read_multidim(self, obj, addr, shape, order=None, - point=0, signed=False, port=0, with_last=False): + point=0, signed=True, port=0, with_last=False): done_flag = self.m.Reg(compiler._tmp_name('_'.join(['', self.name, 'done_flag'])), initval=0) @@ -409,7 +409,7 @@ def read_multidim(self, obj, addr, shape, order=None, def read_reuse(self, obj, addr, size, reuse_size=1, num_outputs=1, - stride=1, point=0, signed=False, port=0, with_last=False): + stride=1, point=0, signed=True, port=0, with_last=False): done_flag = self.m.Reg(compiler._tmp_name('_'.join(['', self.name, 'done_flag'])), initval=0) @@ -458,7 +458,7 @@ def read_reuse(self, obj, addr, size, def read_reuse_pattern(self, obj, addr, pattern, reuse_size=1, num_outputs=1, - point=0, signed=False, port=0, with_last=False): + point=0, signed=True, port=0, with_last=False): done_flag = self.m.Reg(compiler._tmp_name('_'.join(['', self.name, 'done_flag'])), initval=0) @@ -507,7 +507,7 @@ def read_reuse_pattern(self, obj, addr, pattern, def read_reuse_multidim(self, obj, addr, shape, order=None, reuse_size=1, num_outputs=1, - point=0, signed=False, port=0, with_last=False): + point=0, signed=True, port=0, with_last=False): done_flag = self.m.Reg(compiler._tmp_name('_'.join(['', self.name, 'done_flag'])), initval=0) diff --git a/veriloggen/thread/ttypes.py b/veriloggen/thread/ttypes.py index 4f7fcb13..1ef7efb9 100644 --- a/veriloggen/thread/ttypes.py +++ b/veriloggen/thread/ttypes.py @@ -608,7 +608,7 @@ def dma_write_bank(self, fsm, bank, bus, local_addr, global_addr, size, return 0 def read_dataflow(self, port, addr, length=1, - stride=1, cond=None, point=0, signed=False): + stride=1, cond=None, point=0, signed=True): """ @return data, last, done """ @@ -630,7 +630,7 @@ def read_dataflow(self, port, addr, length=1, return merged_data, merged_last, merged_done def read_dataflow_interleave(self, port, addr, length=1, - stride=1, cond=None, point=0, signed=False): + stride=1, cond=None, point=0, signed=True): """ @return data, last, done """ @@ -751,7 +751,7 @@ def read_dataflow_interleave(self, port, addr, length=1, return df_data, df_last, done def read_dataflow_pattern_interleave(self, port, addr, pattern, - cond=None, point=0, signed=False): + cond=None, point=0, signed=True): """ @return data, last, done """ @@ -959,7 +959,7 @@ def read_dataflow_pattern_interleave(self, port, addr, pattern, return df_data, df_last, done def read_dataflow_multidim_interleave(self, port, addr, shape, order=None, - cond=None, point=0, signed=False): + cond=None, point=0, signed=True): """ @return data, last, done """ diff --git a/veriloggen/types/axi.py b/veriloggen/types/axi.py index ceb18d45..5e79a609 100644 --- a/veriloggen/types/axi.py +++ b/veriloggen/types/axi.py @@ -611,7 +611,7 @@ def _read_data_full(self, counter=None, cond=None): return data, valid, last - def read_dataflow(self, counter=None, cond=None, point=0, signed=False): + def read_dataflow(self, counter=None, cond=None, point=0, signed=True): """ @return data, last, done """ @@ -657,7 +657,7 @@ def read_dataflow(self, counter=None, cond=None, point=0, signed=False): df_data = df.Variable(data, valid, data_ready, point=point, signed=signed) - df_last = df.Variable(last, valid, last_ready, width=1) + df_last = df.Variable(last, valid, last_ready, width=1, signed=False) done = vtypes.Ands(last, self.rdata.rvalid, self.rdata.rready) return df_data, df_last, done @@ -701,7 +701,8 @@ def _dma_read_same(self, ram, bus_addr, ram_addr, length, wdata = self.m.TmpReg(ram.datawidth, initval=0) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow( ram_port, ram_addr, df_data, length, @@ -790,7 +791,8 @@ def _dma_read_narrow(self, ram, bus_addr, ram_addr, length, wdata = self.m.TmpReg(ram.datawidth, initval=0) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow( ram_port, ram_addr, df_data, length, @@ -888,7 +890,8 @@ def _dma_read_wide(self, ram, bus_addr, ram_addr, length, wdata_ram = self.m.TmpWire(ram.datawidth) wdata_ram.assign(wdata) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata_ram, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata_ram, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow( ram_port, ram_addr, df_data, length, @@ -1016,7 +1019,8 @@ def _dma_read_pattern_same(self, ram, bus_addr, ram_addr, pattern, wdata = self.m.TmpReg(ram.datawidth, initval=0) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow_pattern(ram_port, ram_addr, df_data, pattern, cond=fsm) @@ -1129,7 +1133,8 @@ def _dma_read_pattern_narrow(self, ram, bus_addr, ram_addr, pattern, wdata = self.m.TmpReg(ram.datawidth, initval=0) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow_pattern(ram_port, ram_addr, df_data, pattern, cond=fsm) @@ -1251,7 +1256,8 @@ def _dma_read_pattern_wide(self, ram, bus_addr, ram_addr, pattern, wdata_ram = self.m.TmpWire(ram.datawidth) wdata_ram.assign(wdata) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata_ram, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata_ram, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow_pattern(ram_port, ram_addr, df_data, pattern, cond=fsm) @@ -1402,7 +1408,8 @@ def _dma_read_unsafe_same(self, ram, bus_addr, ram_addr, length, wdata = self.m.TmpReg(ram.datawidth, initval=0) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow( ram_port, ram_addr, df_data, length, @@ -1446,7 +1453,8 @@ def _dma_read_unsafe_narrow(self, ram, bus_addr, ram_addr, length, wdata = self.m.TmpReg(ram.datawidth, initval=0) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow( ram_port, ram_addr, df_data, length, @@ -1499,7 +1507,8 @@ def _dma_read_unsafe_wide(self, ram, bus_addr, ram_addr, length, wdata_ram = self.m.TmpWire(ram.datawidth) wdata_ram.assign(wdata) wvalid = self.m.TmpReg(initval=0) - df_data = self.df.Variable(wdata_ram, wvalid, width=ram.datawidth) + df_data = self.df.Variable( + wdata_ram, wvalid, width=ram.datawidth, signed=False) done = ram.write_dataflow( ram_port, ram_addr, df_data, length, @@ -1569,7 +1578,7 @@ def _dma_write_same(self, ram, bus_addr, ram_addr, length, ) data, last, done = ram.read_dataflow( - ram_port, ram_addr, length, stride=stride, cond=fsm) + ram_port, ram_addr, length, stride=stride, cond=fsm, signed=False) fsm.goto_next() check_state = fsm.current @@ -1645,7 +1654,7 @@ def _dma_write_narrow(self, ram, bus_addr, ram_addr, length, ) data, last, done = ram.read_dataflow( - ram_port, ram_addr, length, stride=stride, cond=fsm) + ram_port, ram_addr, length, stride=stride, cond=fsm, signed=False) fsm.goto_next() check_state = fsm.current @@ -1701,7 +1710,8 @@ def _dma_write_narrow(self, ram, bus_addr, ram_addr, length, pack_count(0) ) - df_data = self.df.Variable(wdata, wvalid, wready, width=self.datawidth) + df_data = self.df.Variable( + wdata, wvalid, wready, width=self.datawidth, signed=False) done = self.write_dataflow(df_data, counter, cond=fsm) @@ -1752,7 +1762,7 @@ def _dma_write_wide(self, ram, bus_addr, ram_addr, length, ) data, last, done = ram.read_dataflow( - ram_port, ram_addr, length, stride=stride, cond=fsm) + ram_port, ram_addr, length, stride=stride, cond=fsm, signed=False) fsm.goto_next() check_state = fsm.current @@ -1803,7 +1813,8 @@ def _dma_write_wide(self, ram, bus_addr, ram_addr, length, pack_count(0) ) - df_data = self.df.Variable(wdata, wvalid, wready, width=self.datawidth) + df_data = self.df.Variable( + wdata, wvalid, wready, width=self.datawidth, signed=False) done = self.write_dataflow(df_data, counter, cond=fsm) @@ -1871,8 +1882,8 @@ def _dma_write_pattern_same(self, ram, bus_addr, ram_addr, pattern, count(size - 1) ) - data, last, done = ram.read_dataflow_pattern(ram_port, ram_addr, pattern, - cond=fsm) + data, last, done = ram.read_dataflow_pattern( + ram_port, ram_addr, pattern, cond=fsm, signed=False) fsm.goto_next() check_state = fsm.current @@ -1972,8 +1983,8 @@ def _dma_write_pattern_narrow(self, ram, bus_addr, ram_addr, pattern, count(size - 1) ) - data, last, done = ram.read_dataflow_pattern(ram_port, ram_addr, pattern, - cond=fsm) + data, last, done = ram.read_dataflow_pattern( + ram_port, ram_addr, pattern, cond=fsm, signed=False) fsm.goto_next() check_state = fsm.current @@ -2029,7 +2040,8 @@ def _dma_write_pattern_narrow(self, ram, bus_addr, ram_addr, pattern, pack_count(0) ) - df_data = self.df.Variable(wdata, wvalid, wready, width=self.datawidth) + df_data = self.df.Variable( + wdata, wvalid, wready, width=self.datawidth, signed=False) done = self.write_dataflow(df_data, counter, cond=fsm) @@ -2104,8 +2116,8 @@ def _dma_write_pattern_wide(self, ram, bus_addr, ram_addr, pattern, count(size - 1) ) - data, last, done = ram.read_dataflow_pattern(ram_port, ram_addr, pattern, - cond=fsm) + data, last, done = ram.read_dataflow_pattern( + ram_port, ram_addr, pattern, cond=fsm, signed=False) fsm.goto_next() check_state = fsm.current @@ -2156,7 +2168,8 @@ def _dma_write_pattern_wide(self, ram, bus_addr, ram_addr, pattern, pack_count(0) ) - df_data = self.df.Variable(wdata, wvalid, wready, width=self.datawidth) + df_data = self.df.Variable( + wdata, wvalid, wready, width=self.datawidth, signed=False) done = self.write_dataflow(df_data, counter, cond=fsm) @@ -2235,7 +2248,7 @@ def _dma_write_unsafe_same(self, ram, bus_addr, ram_addr, length, fsm.If(ack).goto_next() data, last, done = ram.read_dataflow( - ram_port, ram_addr, length, stride=stride, cond=fsm) + ram_port, ram_addr, length, stride=stride, cond=fsm, signed=False) fsm.goto_next() done = self.write_dataflow(data, counter, cond=fsm) @@ -2265,7 +2278,7 @@ def _dma_write_unsafe_narrow(self, ram, bus_addr, ram_addr, length, fsm.If(ack).goto_next() data, last, done = ram.read_dataflow( - ram_port, ram_addr, length, stride=stride, cond=fsm) + ram_port, ram_addr, length, stride=stride, cond=fsm, signed=False) fsm.goto_next() wdata = self.m.TmpReg(ram.datawidth, initval=0) @@ -2297,7 +2310,8 @@ def _dma_write_unsafe_narrow(self, ram, bus_addr, ram_addr, length, pack_count(0) ) - df_data = self.df.Variable(wdata, wvalid, wready, width=self.datawidth) + df_data = self.df.Variable( + wdata, wvalid, wready, width=self.datawidth, signed=False) done = self.write_dataflow(df_data, counter, cond=fsm) fsm.If(done).goto_init() @@ -2326,7 +2340,7 @@ def _dma_write_unsafe_wide(self, ram, bus_addr, ram_addr, length, fsm.If(ack).goto_next() data, last, done = ram.read_dataflow( - ram_port, ram_addr, length, stride=stride, cond=fsm) + ram_port, ram_addr, length, stride=stride, cond=fsm, signed=False) fsm.goto_next() wdata = self.m.TmpReg(self.datawidth, initval=0) @@ -2353,7 +2367,8 @@ def _dma_write_unsafe_wide(self, ram, bus_addr, ram_addr, length, pack_count(0) ) - df_data = self.df.Variable(wdata, wvalid, wready, width=self.datawidth) + df_data = self.df.Variable( + wdata, wvalid, wready, width=self.datawidth, signed=False) done = self.write_dataflow(df_data, counter, cond=fsm) fsm.If(done).goto_init() @@ -2778,10 +2793,10 @@ def pull_write_dataflow(self, counter=None, cond=None): df = self.df if self.df is not None else _df - df_data = df.Variable(data, valid, data_ready) + df_data = df.Variable(data, valid, data_ready, signed=False) df_mask = df.Variable(mask, valid, mask_ready, - width=self.datawidth // 4) - df_last = df.Variable(last, valid, last_ready, width=1) + width=self.datawidth // 4, signed=False) + df_last = df.Variable(last, valid, last_ready, width=1, signed=False) done = vtypes.Ands(last, self.wdata.wvalid, self.wdata.wready) return df_data, df_mask, df_last, done diff --git a/veriloggen/types/ram.py b/veriloggen/types/ram.py index f5b6e582..2fd8118b 100644 --- a/veriloggen/types/ram.py +++ b/veriloggen/types/ram.py @@ -254,7 +254,7 @@ def read_data(self, port, addr, cond=None): return rdata, rvalid def read_dataflow(self, port, addr, length=1, - stride=1, cond=None, point=0, signed=False): + stride=1, cond=None, point=0, signed=True): """ @return data, last, done """ @@ -326,13 +326,13 @@ def read_dataflow(self, port, addr, length=1, df_data = df.Variable(data, data_valid, data_ready, width=self.datawidth, point=point, signed=signed) - df_last = df.Variable(last, last_valid, last_ready, width=1) + df_last = df.Variable(last, last_valid, last_ready, width=1, signed=False) done = last return df_data, df_last, done def read_dataflow_pattern(self, port, addr, pattern, - cond=None, point=0, signed=False): + cond=None, point=0, signed=True): """ @return data, last, done """ @@ -492,13 +492,13 @@ def read_dataflow_pattern(self, port, addr, pattern, df_data = df.Variable(data, data_valid, data_ready, width=self.datawidth, point=point, signed=signed) - df_last = df.Variable(last, last_valid, last_ready, width=1) + df_last = df.Variable(last, last_valid, last_ready, width=1, signed=False) done = last return df_data, df_last, done def read_dataflow_multidim(self, port, addr, shape, order=None, - cond=None, point=0, signed=False): + cond=None, point=0, signed=True): """ @return data, last, done """ @@ -513,7 +513,7 @@ def read_dataflow_multidim(self, port, addr, shape, order=None, def read_dataflow_reuse(self, port, addr, length=1, stride=1, reuse_size=1, num_outputs=1, - cond=None, point=0, signed=False): + cond=None, point=0, signed=True): """ @return data, last, done """ @@ -649,7 +649,7 @@ def read_dataflow_reuse(self, port, addr, length=1, df = self.df if self.df is not None else dataflow - df_last = df.Variable(last, last_valid, last_ready, width=1) + df_last = df.Variable(last, last_valid, last_ready, width=1, signed=False) done = last df_reuse_data = [df.Variable(d, v, r, @@ -660,7 +660,7 @@ def read_dataflow_reuse(self, port, addr, length=1, def read_dataflow_reuse_pattern(self, port, addr, pattern, reuse_size=1, num_outputs=1, - cond=None, point=0, signed=False): + cond=None, point=0, signed=True): """ @return data, last, done """ @@ -944,7 +944,7 @@ def read_dataflow_reuse_pattern(self, port, addr, pattern, df = self.df if self.df is not None else dataflow - df_last = df.Variable(last, last_valid, last_ready, width=1) + df_last = df.Variable(last, last_valid, last_ready, width=1, signed=False) done = last df_reuse_data = [df.Variable(d, v, r, @@ -955,7 +955,7 @@ def read_dataflow_reuse_pattern(self, port, addr, pattern, def read_dataflow_reuse_multidim(self, port, addr, shape, order=None, reuse_size=1, num_outputs=1, - cond=None, point=0, signed=False): + cond=None, point=0, signed=True): """ @return data, last, done """