diff --git a/boards/common/iotlab/Kconfig b/boards/common/iotlab/Kconfig index 6a5831c0926b..f346823360fb 100644 --- a/boards/common/iotlab/Kconfig +++ b/boards/common/iotlab/Kconfig @@ -27,6 +27,9 @@ config BOARD_COMMON_IOTLAB select HAVE_L3G4200D select HAVE_LSM303DLHC +config CLOCK_HSE + default 16000000 + config MODULE_BOARDS_COMMON_IOTLAB bool depends on TEST_KCONFIG diff --git a/boards/common/iotlab/Makefile.features b/boards/common/iotlab/Makefile.features index ba0bff2db2f0..455b73500d7b 100644 --- a/boards/common/iotlab/Makefile.features +++ b/boards/common/iotlab/Makefile.features @@ -11,6 +11,3 @@ FEATURES_PROVIDED += periph_uart # Put other features for this board (in alphabetical order) FEATURES_PROVIDED += riotboot - -# iotlab boards provide a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/common/iotlab/clock.config diff --git a/boards/common/iotlab/clock.config b/boards/common/iotlab/clock.config deleted file mode 100644 index a2c08246e3a9..000000000000 --- a/boards/common/iotlab/clock.config +++ /dev/null @@ -1,4 +0,0 @@ -# iotlab based boards provide a 16MHz HSE so they need a predivider of 2 -# to remain with a 72MHz sysclk by default. -CONFIG_CUSTOM_PLL_PARAMS=y -CONFIG_CLOCK_PLL_PREDIV=2 diff --git a/boards/common/iotlab/include/periph_conf_common.h b/boards/common/iotlab/include/periph_conf_common.h index 7cce184d3688..a4bd239775f1 100644 --- a/boards/common/iotlab/include/periph_conf_common.h +++ b/boards/common/iotlab/include/periph_conf_common.h @@ -29,7 +29,10 @@ #ifndef CONFIG_BOARD_HAS_HSE #define CONFIG_BOARD_HAS_HSE 1 #endif -#define CLOCK_HSE MHZ(16) + +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(16) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/common/weact-f4x1cx/Kconfig b/boards/common/weact-f4x1cx/Kconfig index 77fd5fca62cd..9905647f18dd 100644 --- a/boards/common/weact-f4x1cx/Kconfig +++ b/boards/common/weact-f4x1cx/Kconfig @@ -28,6 +28,9 @@ config BOARD_COMMON_WEACT_F4X1CX select HAVE_SAUL_GPIO select HAVE_MTD_SPI_NOR +config CLOCK_HSE + default 25000000 + config MODULE_BOARDS_COMMON_WEACT-F4X1CX bool depends on TEST_KCONFIG diff --git a/boards/common/weact-f4x1cx/Makefile.features b/boards/common/weact-f4x1cx/Makefile.features index 6a2f08acdaed..5bb974e4cd93 100644 --- a/boards/common/weact-f4x1cx/Makefile.features +++ b/boards/common/weact-f4x1cx/Makefile.features @@ -14,8 +14,6 @@ FEATURES_PROVIDED += periph_usbdev FEATURES_PROVIDED += highlevel_stdio FEATURES_PROVIDED += tinyusb_device -# weact-f4x1cx boards provide a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/common/weact-f4x1cx/clock.config # This configuration enables modules that are only available when using Kconfig # module modelling diff --git a/boards/common/weact-f4x1cx/clock.config b/boards/common/weact-f4x1cx/clock.config deleted file mode 100644 index 945b9e4add1b..000000000000 --- a/boards/common/weact-f4x1cx/clock.config +++ /dev/null @@ -1,4 +0,0 @@ -# weact-f4x1cx based boards provide a 25MHz HSE so they need a custom PLL config -# to output a 48MHz clock for USB. -CONFIG_CUSTOM_PLL_PARAMS=y -CONFIG_CLOCK_PLL_M=25 diff --git a/boards/common/weact-f4x1cx/include/periph_conf.h b/boards/common/weact-f4x1cx/include/periph_conf.h index 7f10229e3644..78ab979554ce 100644 --- a/boards/common/weact-f4x1cx/include/periph_conf.h +++ b/boards/common/weact-f4x1cx/include/periph_conf.h @@ -33,7 +33,9 @@ #endif /* The HSE provides a 25MHz clock */ -#define CLOCK_HSE MHZ(25) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(25) +#endif #include "clk_conf.h" #include "cfg_i2c1_pb8_pb9.h" diff --git a/boards/f4vi1/Kconfig b/boards/f4vi1/Kconfig index 0fd48939ffd7..24d4655762d5 100644 --- a/boards/f4vi1/Kconfig +++ b/boards/f4vi1/Kconfig @@ -21,6 +21,9 @@ config BOARD_F4VI1 select BOARD_HAS_HSE select BOARD_HAS_LSE +config CLOCK_HSE + default 16000000 + config CLOCK_PLL_M default 16 diff --git a/boards/f4vi1/include/periph_conf.h b/boards/f4vi1/include/periph_conf.h index 4c30e43ed231..5b1dcc3a0d08 100644 --- a/boards/f4vi1/include/periph_conf.h +++ b/boards/f4vi1/include/periph_conf.h @@ -27,7 +27,9 @@ #endif /* The HSE provides a 16MHz clock */ -#define CLOCK_HSE MHZ(16) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(16) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/im880b/Kconfig b/boards/im880b/Kconfig index e67d535aaeec..b653be069b0e 100644 --- a/boards/im880b/Kconfig +++ b/boards/im880b/Kconfig @@ -22,6 +22,10 @@ config BOARD_IM880B select HAS_PERIPH_UART # Clock configuration + select BOARD_HAS_HSE select BOARD_HAS_LSE +config CLOCK_HSE + default 16000000 + source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/im880b/include/periph_conf.h b/boards/im880b/include/periph_conf.h index 69bbcb99b3d1..31fddb1f14e6 100644 --- a/boards/im880b/include/periph_conf.h +++ b/boards/im880b/include/periph_conf.h @@ -36,7 +36,9 @@ /** * @brief Speed of the HSE clock in Hz */ -#define CLOCK_HSE MHZ(16) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(16) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/lora-e5-dev/Kconfig b/boards/lora-e5-dev/Kconfig index 95e962b90e7c..ae10e390c372 100644 --- a/boards/lora-e5-dev/Kconfig +++ b/boards/lora-e5-dev/Kconfig @@ -33,6 +33,9 @@ config BOARD_LORA_E5_DEV select HAVE_SAUL_GPIO select HAVE_LM75A +config CLOCK_HSE + default 32000000 + config LORA_E5_DEV_ENABLE_3P3V bool "LoRa-E5 Development Kit - Enable 3.3V output" default y diff --git a/boards/lora-e5-dev/include/periph_conf.h b/boards/lora-e5-dev/include/periph_conf.h index e123e92d9c19..599b02ffe2bb 100644 --- a/boards/lora-e5-dev/include/periph_conf.h +++ b/boards/lora-e5-dev/include/periph_conf.h @@ -30,7 +30,9 @@ #define CONFIG_BOARD_HAS_HSE 1 #endif -#define CLOCK_HSE MHZ(32) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(32) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/msbiot/Kconfig b/boards/msbiot/Kconfig index 4eba4726cd30..c25a03b59296 100644 --- a/boards/msbiot/Kconfig +++ b/boards/msbiot/Kconfig @@ -30,6 +30,9 @@ config BOARD_MSBIOT select HAVE_MPU9150 select HAVE_SAUL_GPIO +config CLOCK_HSE + default 16000000 + config CLOCK_PLL_M default 16 diff --git a/boards/msbiot/include/periph_conf.h b/boards/msbiot/include/periph_conf.h index 5f3f01632385..ddce99602f02 100644 --- a/boards/msbiot/include/periph_conf.h +++ b/boards/msbiot/include/periph_conf.h @@ -25,7 +25,9 @@ #endif /* The HSE provides a 16MHz clock */ -#define CLOCK_HSE MHZ(16) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(16) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/nucleo-wl55jc/Kconfig b/boards/nucleo-wl55jc/Kconfig index 63e9438de4a6..cc7ba278813e 100644 --- a/boards/nucleo-wl55jc/Kconfig +++ b/boards/nucleo-wl55jc/Kconfig @@ -28,4 +28,7 @@ config BOARD_NUCLEO_WL55JC select MODULE_PERIPH_LPUART if MODULE_STDIO_UART && HAS_PERIPH_LPUART +config CLOCK_HSE + default 32000000 + source "$(RIOTBOARD)/common/nucleo64/Kconfig" diff --git a/boards/nucleo-wl55jc/include/periph_conf.h b/boards/nucleo-wl55jc/include/periph_conf.h index d8f7dbbca052..37a2e709e7b8 100644 --- a/boards/nucleo-wl55jc/include/periph_conf.h +++ b/boards/nucleo-wl55jc/include/periph_conf.h @@ -31,7 +31,9 @@ #define CONFIG_BOARD_HAS_HSE 1 #endif -#define CLOCK_HSE MHZ(32) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(32) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/p-nucleo-wb55/Kconfig b/boards/p-nucleo-wb55/Kconfig index 84381aec9de4..1351bf5d2ca3 100644 --- a/boards/p-nucleo-wb55/Kconfig +++ b/boards/p-nucleo-wb55/Kconfig @@ -33,4 +33,7 @@ config BOARD_P_NUCLEO_WB55 select BOARD_HAS_HSE select BOARD_HAS_LSE +config CLOCK_HSE + default 32000000 + source "$(RIOTBOARD)/common/nucleo/Kconfig" diff --git a/boards/p-nucleo-wb55/include/periph_conf.h b/boards/p-nucleo-wb55/include/periph_conf.h index f1818527952a..80e201ea2150 100644 --- a/boards/p-nucleo-wb55/include/periph_conf.h +++ b/boards/p-nucleo-wb55/include/periph_conf.h @@ -28,7 +28,9 @@ #define CONFIG_BOARD_HAS_HSE 1 #endif -#define CLOCK_HSE MHZ(32) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(32) +#endif /* EXTAHB (HCLK2) max freq 32 Mhz*/ #define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3 diff --git a/boards/pyboard/Kconfig b/boards/pyboard/Kconfig index a2b900d1bb32..c189d3488200 100644 --- a/boards/pyboard/Kconfig +++ b/boards/pyboard/Kconfig @@ -31,6 +31,9 @@ config BOARD_PYBOARD select HAVE_SAUL_GPIO +config CLOCK_HSE + default 12000000 + config CLOCK_PLL_M default 12 diff --git a/boards/pyboard/include/periph_conf.h b/boards/pyboard/include/periph_conf.h index ec4cbc447f28..16c3a37bf7fa 100644 --- a/boards/pyboard/include/periph_conf.h +++ b/boards/pyboard/include/periph_conf.h @@ -32,7 +32,9 @@ #endif /* The HSE provides a 12MHz clock */ -#define CLOCK_HSE MHZ(12) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(12) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/stm32f469i-disco/Kconfig b/boards/stm32f469i-disco/Kconfig index 0f1197435eef..9cc6e019b49a 100644 --- a/boards/stm32f469i-disco/Kconfig +++ b/boards/stm32f469i-disco/Kconfig @@ -27,4 +27,7 @@ config BOARD_STM32F469I_DISCO select HAVE_SAUL_GPIO +config CLOCK_HSE + default 8000000 + source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/stm32f469i-disco/include/periph_conf.h b/boards/stm32f469i-disco/include/periph_conf.h index cda8c0e3192e..4ba53d5aef34 100644 --- a/boards/stm32f469i-disco/include/periph_conf.h +++ b/boards/stm32f469i-disco/include/periph_conf.h @@ -28,7 +28,9 @@ #endif /* The HSE provides a 8MHz clock */ -#define CLOCK_HSE MHZ(8) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(8) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/stm32f723e-disco/Kconfig b/boards/stm32f723e-disco/Kconfig index b987eff9de68..86b6923c01d5 100644 --- a/boards/stm32f723e-disco/Kconfig +++ b/boards/stm32f723e-disco/Kconfig @@ -37,6 +37,9 @@ config BOARD_STM32F723E_DISCO # Workaround due to stdout only working with stdin enabled select MODULE_STDIN if TEST_KCONFIG +config CLOCK_HSE + default 25000000 + config MODULE_PERIPH_INIT_LED0 default n if MODULE_PERIPH_SPI diff --git a/boards/stm32f723e-disco/Makefile.features b/boards/stm32f723e-disco/Makefile.features index 983f775e2b11..45efd116eca4 100644 --- a/boards/stm32f723e-disco/Makefile.features +++ b/boards/stm32f723e-disco/Makefile.features @@ -15,6 +15,3 @@ FEATURES_PROVIDED += periph_usbdev_hs_utmi # Put other features for this board (in alphabetical order) FEATURES_PROVIDED += tinyusb_device - -# stm32f723e-disco provides a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/stm32f723e-disco/clock.config diff --git a/boards/stm32f723e-disco/clock.config b/boards/stm32f723e-disco/clock.config deleted file mode 100644 index 607e0576f6d2..000000000000 --- a/boards/stm32f723e-disco/clock.config +++ /dev/null @@ -1,5 +0,0 @@ -# stm32f723e-disco provides a 25MHz HSE so they need a custom PLL config -# to remain in 216MHz max clock. -CONFIG_CUSTOM_PLL_PARAMS=y -CONFIG_CLOCK_PLL_M=25 -CONFIG_CLOCK_PLL_N=432 diff --git a/boards/stm32f723e-disco/include/periph_conf.h b/boards/stm32f723e-disco/include/periph_conf.h index 7a2213b8c128..5081f8b73243 100644 --- a/boards/stm32f723e-disco/include/periph_conf.h +++ b/boards/stm32f723e-disco/include/periph_conf.h @@ -30,7 +30,9 @@ #endif /* The HSE provides a 25MHz clock */ -#define CLOCK_HSE MHZ(25) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(25) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/stm32f746g-disco/Kconfig b/boards/stm32f746g-disco/Kconfig index d0f3356462bd..18fbf0842ff9 100644 --- a/boards/stm32f746g-disco/Kconfig +++ b/boards/stm32f746g-disco/Kconfig @@ -34,4 +34,9 @@ config BOARD_STM32F746G_DISCO select HAVE_STM32_ETH select HAVE_FT5X06 + +config CLOCK_HSE + default 25000000 + + source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/stm32f746g-disco/clock.config b/boards/stm32f746g-disco/clock.config deleted file mode 100644 index cb4034b254a6..000000000000 --- a/boards/stm32f746g-disco/clock.config +++ /dev/null @@ -1,5 +0,0 @@ -# stm32f746g-disco provides a 25MHz HSE so they need a custom PLL config -# to remain in 216MHz max clock. -CONFIG_CUSTOM_PLL_PARAMS=y -CONFIG_CLOCK_PLL_M=25 -CONFIG_CLOCK_PLL_N=432 diff --git a/boards/stm32f746g-disco/features-shared.mk b/boards/stm32f746g-disco/features-shared.mk index 2e2d5ecb416e..ad20ec6fe562 100644 --- a/boards/stm32f746g-disco/features-shared.mk +++ b/boards/stm32f746g-disco/features-shared.mk @@ -11,6 +11,3 @@ FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_usbdev FEATURES_PROVIDED += periph_usbdev_hs_ulpi FEATURES_PROVIDED += tinyusb_device - -# stm32f746g-disco provides a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/stm32f746g-disco/clock.config diff --git a/boards/stm32f746g-disco/include/periph_conf.h b/boards/stm32f746g-disco/include/periph_conf.h index 4cfded763793..9ad0453e91f6 100644 --- a/boards/stm32f746g-disco/include/periph_conf.h +++ b/boards/stm32f746g-disco/include/periph_conf.h @@ -30,7 +30,9 @@ #endif /* The HSE provides a 25MHz clock */ -#define CLOCK_HSE MHZ(25) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(25) +#endif #include diff --git a/boards/stm32f7508-dk/Kconfig b/boards/stm32f7508-dk/Kconfig index e37295848b54..5573789d533f 100644 --- a/boards/stm32f7508-dk/Kconfig +++ b/boards/stm32f7508-dk/Kconfig @@ -31,6 +31,10 @@ config BOARD_STM32F7508_DK select BOARD_HAS_LSE select HAVE_SAUL_GPIO + select HAVE_STM32_ETH select HAVE_FT5X06 +config CLOCK_HSE + default 25000000 + source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/stm32f769i-disco/Kconfig b/boards/stm32f769i-disco/Kconfig index 94671967f5fc..aef5b3603354 100644 --- a/boards/stm32f769i-disco/Kconfig +++ b/boards/stm32f769i-disco/Kconfig @@ -29,4 +29,9 @@ config BOARD_STM32F769I_DISCO select HAVE_SAUL_GPIO + +config CLOCK_HSE + default 25000000 + + source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/stm32f769i-disco/Makefile.features b/boards/stm32f769i-disco/Makefile.features index 7577140b5eda..17c78c609894 100644 --- a/boards/stm32f769i-disco/Makefile.features +++ b/boards/stm32f769i-disco/Makefile.features @@ -10,6 +10,3 @@ FEATURES_PROVIDED += periph_usbdev # Put other features for this board (in alphabetical order) FEATURES_PROVIDED += tinyusb_device - -# stm32f769i-disco provides a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/stm32f769i-disco/clock.config diff --git a/boards/stm32f769i-disco/clock.config b/boards/stm32f769i-disco/clock.config deleted file mode 100644 index ea639c8bd1f2..000000000000 --- a/boards/stm32f769i-disco/clock.config +++ /dev/null @@ -1,5 +0,0 @@ -# stm32f769i-disco provides a 25MHz HSE so they need a custom PLL config -# to remain in 216MHz max clock. -CONFIG_CUSTOM_PLL_PARAMS=y -CONFIG_CLOCK_PLL_M=25 -CONFIG_CLOCK_PLL_N=432 diff --git a/boards/stm32f769i-disco/include/periph_conf.h b/boards/stm32f769i-disco/include/periph_conf.h index dc77edb2dbcc..0e504e84c608 100644 --- a/boards/stm32f769i-disco/include/periph_conf.h +++ b/boards/stm32f769i-disco/include/periph_conf.h @@ -30,7 +30,9 @@ #endif /* The HSE provides a 25MHz clock */ -#define CLOCK_HSE MHZ(25) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(25) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/ublox-c030-u201/Kconfig b/boards/ublox-c030-u201/Kconfig index d35cd38e1cde..fc73c1fa7b6b 100644 --- a/boards/ublox-c030-u201/Kconfig +++ b/boards/ublox-c030-u201/Kconfig @@ -30,4 +30,7 @@ config BOARD_UBLOX_C030_U201 select HAVE_SAUL_GPIO select MODULE_PERIPH_UART_HW_FC if TEST_KCONFIG && HAS_PERIPH_UART_HW_FC +config CLOCK_HSE + default 12000000 + source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/ublox-c030-u201/Makefile.features b/boards/ublox-c030-u201/Makefile.features index d25489c730e2..3643e1c2db90 100644 --- a/boards/ublox-c030-u201/Makefile.features +++ b/boards/ublox-c030-u201/Makefile.features @@ -10,6 +10,3 @@ FEATURES_PROVIDED += periph_spi FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_uart_hw_fc - -# ublox-c030-u201 provides a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/ublox-c030-u201/clock.config diff --git a/boards/ublox-c030-u201/clock.config b/boards/ublox-c030-u201/clock.config deleted file mode 100644 index 778fb18fa254..000000000000 --- a/boards/ublox-c030-u201/clock.config +++ /dev/null @@ -1,5 +0,0 @@ -# ublox-c030-u201 provides a 12MHz HSE so its needs a custom PLL config to -# output a 180MHz clock. -CONFIG_CUSTOM_PLL_PARAMS=y -CONFIG_CLOCK_PLL_M=12 -CONFIG_CLOCK_PLL_N=360 diff --git a/boards/ublox-c030-u201/include/periph_conf.h b/boards/ublox-c030-u201/include/periph_conf.h index be595740786e..1f98b1a4af9a 100644 --- a/boards/ublox-c030-u201/include/periph_conf.h +++ b/boards/ublox-c030-u201/include/periph_conf.h @@ -30,7 +30,9 @@ #endif /* The HSE provides a 12MHz clock */ -#define CLOCK_HSE MHZ(12) +#ifndef CONFIG_CLOCK_HSE +#define CONFIG_CLOCK_HSE MHZ(12) +#endif #include "periph_cpu.h" #include "clk_conf.h" diff --git a/boards/weact-f401cc/Makefile.features b/boards/weact-f401cc/Makefile.features index fa1a35efbf0c..49c258a11a81 100644 --- a/boards/weact-f401cc/Makefile.features +++ b/boards/weact-f401cc/Makefile.features @@ -1,6 +1,3 @@ CPU_MODEL = stm32f401cc include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features - -# weact-f401cc provides a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/weact-f401cc/clock.config diff --git a/boards/weact-f401cc/clock.config b/boards/weact-f401cc/clock.config deleted file mode 100644 index b6a5c5f93857..000000000000 --- a/boards/weact-f401cc/clock.config +++ /dev/null @@ -1 +0,0 @@ -CONFIG_CLOCK_PLL_N=336 diff --git a/boards/weact-f401ce/Makefile.features b/boards/weact-f401ce/Makefile.features index 6921886adc27..1417cb4e9d02 100644 --- a/boards/weact-f401ce/Makefile.features +++ b/boards/weact-f401ce/Makefile.features @@ -1,6 +1,3 @@ CPU_MODEL = stm32f401ce include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features - -# weact-f401ce provides a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/weact-f401ce/clock.config diff --git a/boards/weact-f401ce/clock.config b/boards/weact-f401ce/clock.config deleted file mode 100644 index b6a5c5f93857..000000000000 --- a/boards/weact-f401ce/clock.config +++ /dev/null @@ -1 +0,0 @@ -CONFIG_CLOCK_PLL_N=336 diff --git a/boards/weact-f411ce/Makefile.features b/boards/weact-f411ce/Makefile.features index 8f3a504e1680..464bf16c20f1 100644 --- a/boards/weact-f411ce/Makefile.features +++ b/boards/weact-f411ce/Makefile.features @@ -1,6 +1,3 @@ CPU_MODEL = stm32f411ce include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features - -# weact-f411ce provides a custom default Kconfig clock configuration -KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/weact-f411ce/clock.config diff --git a/boards/weact-f411ce/clock.config b/boards/weact-f411ce/clock.config deleted file mode 100644 index 2328d09ebee5..000000000000 --- a/boards/weact-f411ce/clock.config +++ /dev/null @@ -1 +0,0 @@ -CONFIG_CLOCK_PLL_N=192 diff --git a/cpu/stm32/Kconfig b/cpu/stm32/Kconfig index 605dd7cfe3d0..07a920dc459a 100644 --- a/cpu/stm32/Kconfig +++ b/cpu/stm32/Kconfig @@ -19,6 +19,8 @@ config CPU_STM32 # This CPU requires periph_rtc when periph_rtc_mem select MODULE_PERIPH_RTC if MODULE_PERIPH_RTC_MEM && HAS_PERIPH_RTC +menu "STM32 configuration" + # Common CPU symbol config CPU default "stm32" if CPU_STM32 @@ -39,22 +41,30 @@ config MODULE_BOOTLOADER_STM32 depends on HAS_BOOTLOADER_STM32 depends on TEST_KCONFIG -orsource "kconfigs/Kconfig.clk" -orsource "kconfigs/*/Kconfig" -orsource "kconfigs/*/Kconfig.lines" -orsource "kconfigs/*/Kconfig.models" + +menu "STM32 clock configuration" + depends on CPU_STM32 + +rsource "kconfigs/Kconfig.clk" +rsource "kconfigs/$(CPU_FAM)/Kconfig.clk" + +endmenu + +rsource "kconfigs/$(CPU_FAM)/Kconfig" +rsource "kconfigs/$(CPU_FAM)/Kconfig.lines" +rsource "kconfigs/$(CPU_FAM)/Kconfig.models" choice prompt "ReaDout Protection level" default RDP0 help - Set minimum running RDP level. - RDP0 is full debug permissions, RDP1 disables read from Flash but - otherwise leaves debug enabled, RDP2 disables JTAG completely. If - there is a mismatch between desired RDP level here and RDP level - set on the chip, early cpu init will hang. This ensures production - devices with the wrong RDP level, by fault or malace intent, will - not run. See cpu manual for further details on RDP. + Set minimum running RDP level. + RDP0 is full debug permissions, RDP1 disables read from Flash but + otherwise leaves debug enabled, RDP2 disables JTAG completely. If + there is a mismatch between desired RDP level here and RDP level + set on the chip, early cpu init will hang. This ensures production + devices with the wrong RDP level, by fault or malace intent, will + not run. See cpu manual for further details on RDP. depends on (CPU_FAM_F1 || CPU_FAM_F2 || CPU_FAM_F3 || CPU_FAM_F4 || CPU_FAM_F7) config RDP0 bool "RDP0" @@ -72,4 +82,6 @@ rsource "vectors/Kconfig" endif # TEST_KCONFIG +endmenu + source "$(RIOTCPU)/cortexm_common/Kconfig" diff --git a/cpu/stm32/dist/clk_conf/clk_conf.c b/cpu/stm32/dist/clk_conf/clk_conf.c index d6ba46fb61c8..14911c10b0e4 100644 --- a/cpu/stm32/dist/clk_conf/clk_conf.c +++ b/cpu/stm32/dist/clk_conf/clk_conf.c @@ -454,7 +454,9 @@ int main(int argc, char **argv) printf("#define CLOCK_CORECLOCK (%uU)\n", coreclock); printf("/* 0: no external high speed crystal available\n" " * else: actual crystal frequency [in Hz] */\n" - "#define CLOCK_HSE (%uU)\n", pll_src ? pll_in : 0); + "#ifndef CONFIG_CLOCK_HSE\n" + "#define CONFIG_CLOCK_HSE (%uU)\n", pll_src ? pll_in : 0); + printf("#endif\n"); printf("/* 0: no external low speed crystal available,\n" " * 1: external crystal available (always 32.768kHz) */\n" "#define CLOCK_LSE (%uU)\n", is_lse); diff --git a/cpu/stm32/doc.txt b/cpu/stm32/doc.txt index cfd065f3e1e1..88f5fee8154b 100644 --- a/cpu/stm32/doc.txt +++ b/cpu/stm32/doc.txt @@ -21,7 +21,7 @@ system clock (but only one can be used at a time): - HSE (High Speed External): HSE depends on the board configuration and its presence is specified by the `CONFIG_BOARD_HAS_HSE` constant at board level. - The `CLOCK_HSE` constant specifies the frequency of the external oscillator + The `CONFIG_CLOCK_HSE` constant specifies the frequency of the external oscillator in Hz. To use HSE as system clock (SYSCLK), set `CONFIG_USE_CLOCK_HSE` constant to 1; diff --git a/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h b/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h index 119b46b6fcc8..f6b2aaf4f262 100644 --- a/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h +++ b/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h @@ -55,22 +55,24 @@ extern "C" { #error "Cannot use HSI as clock source with other clock configurations" #endif -#ifndef CLOCK_HSE +#ifndef CONFIG_CLOCK_HSE #if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \ defined(CPU_FAM_STM32MP1) -#define CLOCK_HSE MHZ(24) +#define CONFIG_CLOCK_HSE MHZ(24) #else -#define CLOCK_HSE MHZ(8) +#define CONFIG_CLOCK_HSE MHZ(8) #endif #endif +#ifndef CONFIG_CLOCK_HSI #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \ defined(CPU_FAM_STM32F3) -#define CLOCK_HSI MHZ(8) +#define CONFIG_CLOCK_HSI MHZ(8) #elif defined(CPU_FAM_STM32MP1) -#define CLOCK_HSI MHZ(64) +#define CONFIG_CLOCK_HSI MHZ(64) #else -#define CLOCK_HSI MHZ(16) +#define CONFIG_CLOCK_HSI MHZ(16) +#endif #endif /** @} */ diff --git a/cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx.h b/cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx.h index 9a7a6ae9df6f..0703081a228e 100644 --- a/cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx.h +++ b/cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx.h @@ -66,15 +66,17 @@ extern "C" { #error "Cannot use HSI as clock source with other clock configurations" #endif -#ifndef CLOCK_HSE +#ifndef CONFIG_CLOCK_HSE #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) -#define CLOCK_HSE MHZ(24) +#define CONFIG_CLOCK_HSE MHZ(24) #else -#define CLOCK_HSE MHZ(8) +#define CONFIG_CLOCK_HSE MHZ(8) #endif #endif -#define CLOCK_HSI MHZ(16) +#ifndef CONFIG_CLOCK_HSI +#define CONFIG_CLOCK_HSI MHZ(16) +#endif #ifndef CONFIG_CLOCK_MSI #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) diff --git a/cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h b/cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h index 072cecd73ff4..180dff371981 100644 --- a/cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h +++ b/cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h @@ -34,7 +34,7 @@ extern "C" { * @name F0/F1/F3 clock settings * @{ */ -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(32)) #error "HSE clock frequency must be between 4MHz and 32MHz" #endif @@ -50,7 +50,7 @@ extern "C" { PLL_MUL to 16, so system clock = (HSI8 / 2) * 16 = 64MHz */ #ifndef CONFIG_CLOCK_PLL_PREDIV -#if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))) || \ +#if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(16))) || \ defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \ defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \ defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) || \ @@ -68,7 +68,9 @@ extern "C" { #define CONFIG_CLOCK_PLL_MUL (6) #endif #else /* CPU_FAM_F1 || CPU_FAM_F3 */ -#if defined(CPU_LINE_STM32F303x8) +#if defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \ + defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \ + defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) #define CONFIG_CLOCK_PLL_MUL (16) #else #define CONFIG_CLOCK_PLL_MUL (9) @@ -77,19 +79,19 @@ extern "C" { #endif /* CONFIG_CLOCK_PLL_MUL */ #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI) #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #error "The board doesn't provide an HSE oscillator" #endif -#define CLOCK_CORECLOCK (CLOCK_HSE) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE) #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE) +#else /* CONFIG_CLOCK_HSI */ +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) #endif /* PLL configuration: make sure your values are legit! * diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h index ae87d7f527a6..46d6c81fef3d 100644 --- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h +++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h @@ -51,19 +51,19 @@ * @{ */ #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE) +#else /* CONFIG_CLOCK_HSI */ +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) #endif #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI) #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #error "The board doesn't provide an HSE oscillator" #endif -#define CLOCK_CORECLOCK (CLOCK_HSE) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE) #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P) diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h index 6187b671e7c9..400b37fa29b5 100644 --- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h +++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h @@ -37,7 +37,7 @@ extern "C" { decreased to 96MHZ so the PLLQ can output 48MHz. */ #ifndef CONFIG_CLOCK_PLL_M -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25)) #define CONFIG_CLOCK_PLL_M (25) #else #define CONFIG_CLOCK_PLL_M (4) @@ -45,17 +45,17 @@ extern "C" { #endif #ifndef CONFIG_CLOCK_PLL_N #if IS_USED(MODULE_PERIPH_USBDEV_CLK) && defined(CPU_LINE_STM32F411xE) -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (96) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25)) #define CONFIG_CLOCK_PLL_N (192) #else #define CONFIG_CLOCK_PLL_N (48) #endif #else -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (100) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25)) #define CONFIG_CLOCK_PLL_N (200) #else #define CONFIG_CLOCK_PLL_N (50) diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h index 74b96a87cce2..6e5a0a8e8212 100644 --- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h +++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h @@ -37,7 +37,7 @@ extern "C" { #define CONFIG_CLOCK_PLL_M (4) #endif #ifndef CONFIG_CLOCK_PLL_N -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (120) #else #define CONFIG_CLOCK_PLL_N (60) diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h index cc6f13724526..de4bec1e1936 100644 --- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h +++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h @@ -37,9 +37,9 @@ extern "C" { decreased to 168MHZ so the PLLQ can output 48MHz. */ #ifndef CONFIG_CLOCK_PLL_M -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12)) #define CONFIG_CLOCK_PLL_M (12) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16)) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(16)) #define CONFIG_CLOCK_PLL_M (16) #else #define CONFIG_CLOCK_PLL_M (4) @@ -51,19 +51,19 @@ extern "C" { defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \ defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \ defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx)) -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (168) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12) || \ - (CLOCK_HSE == MHZ(16))) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \ + (CONFIG_CLOCK_HSE == MHZ(16))) #define CONFIG_CLOCK_PLL_N (336) #else #define CONFIG_CLOCK_PLL_N (84) #endif #else -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (180) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12) || \ - (CLOCK_HSE == MHZ(16))) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \ + (CONFIG_CLOCK_HSE == MHZ(16))) #define CONFIG_CLOCK_PLL_N (360) #else #define CONFIG_CLOCK_PLL_N (90) diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h index 55e3bf338e7a..022ed32fab65 100644 --- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h +++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h @@ -34,16 +34,16 @@ extern "C" { /* The following parameters configure a 216MHz system clock with HSE (8MHz, 16MHz or 25MHz) or HSI (16MHz) as PLL input clock */ #ifndef CONFIG_CLOCK_PLL_M -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25)) #define CONFIG_CLOCK_PLL_M (25) #else #define CONFIG_CLOCK_PLL_M (4) #endif #endif #ifndef CONFIG_CLOCK_PLL_N -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25)) #define CONFIG_CLOCK_PLL_N (432) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (216) #else #define CONFIG_CLOCK_PLL_N (108) diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h index 66137a3bcdc5..eb03e49e7e66 100644 --- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h +++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h @@ -34,16 +34,16 @@ extern "C" { /* The following parameters configure a 84MHz system clock with HSE (8MHz, 16MHz or 25MHz) or HSI (16MHz) as PLL input clock */ #ifndef CONFIG_CLOCK_PLL_M -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25)) #define CONFIG_CLOCK_PLL_M (25) #else #define CONFIG_CLOCK_PLL_M (4) #endif #endif #ifndef CONFIG_CLOCK_PLL_N -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_N (168) -#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25)) +#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25)) #define CONFIG_CLOCK_PLL_N (336) #else #define CONFIG_CLOCK_PLL_N (84) diff --git a/cpu/stm32/include/clk/g0g4/cfg_clock_default.h b/cpu/stm32/include/clk/g0g4/cfg_clock_default.h index 07c22fcf05b4..7facc82ebb1c 100644 --- a/cpu/stm32/include/clk/g0g4/cfg_clock_default.h +++ b/cpu/stm32/include/clk/g0g4/cfg_clock_default.h @@ -32,7 +32,7 @@ extern "C" { * * @{ */ -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48)) #error "HSE clock frequency must be between 4MHz and 48MHz" #endif @@ -43,9 +43,9 @@ extern "C" { #endif #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE) +#else /* CONFIG_CLOCK_HSI */ +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) #endif /* The following parameters configure a 64MHz system clock with HSI as input clock */ @@ -73,16 +73,16 @@ extern "C" { #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) #ifdef CPU_FAM_STM32G0 -#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV) #else -#define CLOCK_CORECLOCK (CLOCK_HSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI) #endif #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #error "The board doesn't provide an HSE oscillator" #endif -#define CLOCK_CORECLOCK (CLOCK_HSE) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE) #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #define CLOCK_CORECLOCK \ diff --git a/cpu/stm32/include/clk/l0l1/cfg_clock_default.h b/cpu/stm32/include/clk/l0l1/cfg_clock_default.h index f60062972b8c..bdb0c092c8d7 100644 --- a/cpu/stm32/include/clk/l0l1/cfg_clock_default.h +++ b/cpu/stm32/include/clk/l0l1/cfg_clock_default.h @@ -29,7 +29,7 @@ extern "C" { * @name L0/L1 clock system configuration * @{ */ -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(1) || CONFIG_CLOCK_HSE > MHZ(24)) #error "HSE clock frequency must be between 1MHz and 24MHz" #endif @@ -42,25 +42,25 @@ extern "C" { #endif #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI) #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #error "The board doesn't provide an HSE oscillator" #endif -#define CLOCK_CORECLOCK (CLOCK_HSE) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE) #elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI) #define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#if CLOCK_HSE < MHZ(2) +#if CONFIG_CLOCK_HSE < MHZ(2) #error "HSE must be greater than 2MHz when used as PLL input clock" #endif -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE) +#else /* CONFIG_CLOCK_HSI */ +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) #endif /* CONFIG_BOARD_HAS_HSE */ /* PLL configuration: make sure your values are legit! * diff --git a/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h b/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h index 658d7d9394b7..89eb43735ee4 100644 --- a/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h +++ b/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h @@ -29,7 +29,7 @@ extern "C" { * @name L4/L5/WB clock system configuration * @{ */ -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48)) #error "HSE clock frequency must be between 4MHz and 48MHz" #endif @@ -56,23 +56,23 @@ extern "C" { #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI) #define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI) #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE) #else /* CONFIG_CLOCK_PLL_SRC_ */ -#define CLOCK_PLL_SRC (CLOCK_HSI) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) #endif #ifndef CONFIG_CLOCK_PLL_M #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI) #define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */ -#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(8)) +#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(8)) #define CONFIG_CLOCK_PLL_M (1) /* HSE at 8MHz */ -#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(32)) +#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32)) #define CONFIG_CLOCK_PLL_M (4) /* HSE at 32MHz */ #else #define CONFIG_CLOCK_PLL_M (2) /* HSI at 16MHz */ #endif #endif #ifndef CONFIG_CLOCK_PLL_N -#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(32)) +#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32)) /* For STM32WL, VCO output frequency ((PLL input clock frequency / PLLM ) x PLLN ) must be between 96 and 344 MHz. PLLN can have values <=127 & >=6 */ #if IS_ACTIVE(CPU_FAM_STM32WL) @@ -81,7 +81,7 @@ extern "C" { #define CONFIG_CLOCK_PLL_N (16) #endif /* CPU_FAM_STM32WL */ #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \ - (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(16))) + (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(16))) #define CONFIG_CLOCK_PLL_N (32) #else #if defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \ @@ -105,10 +105,10 @@ extern "C" { #endif #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI) #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) -#define CLOCK_CORECLOCK (CLOCK_HSE) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE) #elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI) #define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_default.h b/cpu/stm32/include/clk/mp1/cfg_clock_default.h index 8dd698cb1f87..8d6ba8f93ee3 100644 --- a/cpu/stm32/include/clk/mp1/cfg_clock_default.h +++ b/cpu/stm32/include/clk/mp1/cfg_clock_default.h @@ -28,7 +28,7 @@ #ifndef CONFIG_CLOCK_PLL_M #define CONFIG_CLOCK_PLL_M (2) #endif -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(24)) #ifndef CONFIG_CLOCK_PLL_N #define CONFIG_CLOCK_PLL_N (52) #endif @@ -75,19 +75,19 @@ * @{ */ #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE) +#else /* CONFIG_CLOCK_HSI */ +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) #endif #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI) #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #error "The board doesn't provide an HSE oscillator" #endif -#define CLOCK_CORECLOCK (CLOCK_HSE) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE) #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \ diff --git a/cpu/stm32/include/clk/u5/cfg_clock_default.h b/cpu/stm32/include/clk/u5/cfg_clock_default.h index 87494ae205f8..6f29345a83c9 100644 --- a/cpu/stm32/include/clk/u5/cfg_clock_default.h +++ b/cpu/stm32/include/clk/u5/cfg_clock_default.h @@ -27,7 +27,7 @@ extern "C" { * @name U5 clock system configuration * @{ */ -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48)) #error "HSE clock frequency must be between 4MHz and 48MHz" #endif @@ -54,9 +54,9 @@ extern "C" { #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI) #define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI) #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE) #else /* CONFIG_CLOCK_PLL_SRC_ */ -#define CLOCK_PLL_SRC (CLOCK_HSI) +#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) #endif #ifndef CONFIG_CLOCK_PLL_M #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI) @@ -76,10 +76,10 @@ extern "C" { #endif #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI) #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) -#define CLOCK_CORECLOCK (CLOCK_HSE) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE) #elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI) #define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) diff --git a/cpu/stm32/include/tinyusb_hw_defaults.h b/cpu/stm32/include/tinyusb_hw_defaults.h index 02b20095e8b6..412822755258 100644 --- a/cpu/stm32/include/tinyusb_hw_defaults.h +++ b/cpu/stm32/include/tinyusb_hw_defaults.h @@ -117,7 +117,7 @@ extern "C" { * If the CMSIS defines that the internal UTMI HS PHY is used, the Synopsys DWC2 * driver needs the definition of the HSE clock value. */ -#define HSE_VALUE CLOCK_HSE +#define HSE_VALUE CONFIG_CLOCK_HSE #endif #ifdef __cplusplus diff --git a/cpu/stm32/kconfigs/Kconfig.clk b/cpu/stm32/kconfigs/Kconfig.clk index 18554d36bc21..1a898ef00bfd 100644 --- a/cpu/stm32/kconfigs/Kconfig.clk +++ b/cpu/stm32/kconfigs/Kconfig.clk @@ -10,8 +10,6 @@ config CLOCK_HAS_NO_MCO_PRE help Indicates that the CPU has no MCO prescaler -menu "STM32 clock configuration" - depends on CPU_STM32 choice bool "Clock source selection" @@ -20,10 +18,6 @@ default USE_CLOCK_PLL config USE_CLOCK_PLL bool "PLL" -config USE_CLOCK_MSI - bool "Use direct multi-speed frequency internal oscillator (MSI)" - depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - config USE_CLOCK_HSE bool "Direct High frequency external oscillator (HSE)" depends on BOARD_HAS_HSE @@ -33,345 +27,16 @@ config USE_CLOCK_HSI endchoice -if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL -choice -bool "Source clock for PLL" if USE_CLOCK_PLL -default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE -default CLOCK_PLL_SRC_MSI - -config CLOCK_PLL_SRC_MSI - bool "Use MSI source clock" - -config CLOCK_PLL_SRC_HSE - bool "Use HSE source clock" +config CLOCK_HSE + int depends on BOARD_HAS_HSE - -config CLOCK_PLL_SRC_HSI - bool "Use HSI16 source clock" -endchoice - -endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL + default 24000000 if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_MP1 + default 8000000 config CUSTOM_PLL_PARAMS bool "Configure PLL parameters" depends on USE_CLOCK_PLL -if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_MP1 -config CLOCK_PLL_M - int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS - default 4 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 - default 1 if CPU_FAM_G0 - default 6 if CPU_FAM_G4 && BOARD_HAS_HSE - default 4 if CPU_FAM_G4 - default 6 if (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) && CLOCK_PLL_SRC_MSI - default 4 if (CPU_FAM_WB || CPU_FAM_WL) && CLOCK_PLL_SRC_HSE - default 2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 - range 1 8 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - range 1 16 if CPU_FAM_G4 - -config CLOCK_PLL_N - int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS - default 120 if BOARD_HAS_HSE && CPU_FAM_F2 - default 60 if CPU_FAM_F2 - default 168 if CPU_FAM_F4 && CLOCK_MAX_84MHZ && BOARD_HAS_HSE - default 84 if CPU_FAM_F4 && CLOCK_MAX_84MHZ - default 96 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 48 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 100 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE - default 50 if CPU_FAM_F4 && CLOCK_MAX_100MHZ - default 168 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 84 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 180 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE - default 90 if CPU_FAM_F4 && CLOCK_MAX_180MHZ - default 216 if CPU_FAM_F7 && BOARD_HAS_HSE - default 108 if CPU_FAM_F7 - default 12 if CPU_FAM_WL - default 16 if CPU_FAM_WB - default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX - default 27 if CPU_FAM_L5 - default 20 if CPU_FAM_G0 || CPU_FAM_L4 - default 85 if CPU_FAM_G4 - default 52 if CPU_FAM_MP1 && BOARD_HAS_HSE - default 78 if CPU_FAM_MP1 - range 8 86 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 - range 50 432 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 - range 8 127 if CPU_FAM_G4 - range 6 127 if CPU_FAM_WB || CPU_FAM_WL - range 4 512 if CPU_FAM_MP1 - -if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 -choice -bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS -default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ -default PLL_P_DIV_2 - -config PLL_P_DIV_2 - bool "Divide by 2" - -config PLL_P_DIV_4 - bool "Divide by 4" - -config PLL_P_DIV_6 - bool "Divide by 6" - -config PLL_P_DIV_8 - bool "Divide by 8" - -endchoice - -config CLOCK_PLL_P - int - default 3 if CPU_FAM_MP1 - default 2 if PLL_P_DIV_2 - default 4 if PLL_P_DIV_4 - default 6 if PLL_P_DIV_6 - default 8 if PLL_P_DIV_8 - -config CLOCK_PLL_Q - int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS - default 5 if CPU_FAM_F2 - default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ - default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ - default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) - default 9 if CPU_FAM_F7 - default 13 if CPU_FAM_MP1 - default 8 - range 2 15 -endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 - -if CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 -config CLOCK_PLL_R - int "Q: VCO division factor" if CUSTOM_PLL_PARAMS - default 2 if CPU_FAM_WB || CPU_FAM_WL - default 3 if CPU_FAM_MP1 - default 6 if BOARD_HAS_HSE - default 5 - range 2 8 -endif # CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 - -if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 -choice -bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS -default PLL_R_DIV_2 - -config PLL_R_DIV_2 - bool "Divide by 2" - -config PLL_R_DIV_4 - bool "Divide by 4" - -config PLL_R_DIV_6 - bool "Divide by 6" - -config PLL_R_DIV_8 - bool "Divide by 8" - -endchoice - -config CLOCK_PLL_R - int - default 2 if PLL_R_DIV_2 - default 4 if PLL_R_DIV_4 - default 6 if PLL_R_DIV_6 - default 8 if PLL_R_DIV_8 -endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 - -endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 - -if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 -config CLOCK_PLL_PREDIV - int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 && !CPU_LINE_STM32F303X8 - default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 || CPU_LINE_STM32F303X8 || CPU_LINE_STM32F303XC - default 1 - range 1 16 - -config CLOCK_PLL_MUL - int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS - default 16 if CPU_LINE_STM32F303X8 - default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 - default 9 if CPU_FAM_F1 || CPU_FAM_F3 - default 6 if CPU_FAM_F0 - range 2 16 -endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 - -if CPU_FAM_L0 || CPU_FAM_L1 -config CLOCK_PLL_DIV - int "Main PLL division factor" if CUSTOM_PLL_PARAMS - default 2 - range 2 4 - -choice -bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS -default PLL_MUL_4 - -config PLL_MUL_3 - bool "Multiply by 3" - -config PLL_MUL_4 - bool "Multiply by 4" - -config PLL_MUL_6 - bool "Multiply by 6" - -config PLL_MUL_8 - bool "Multiply by 8" - -config PLL_MUL_12 - bool "Multiply by 12" - -config PLL_MUL_16 - bool "Multiply by 16" - -config PLL_MUL_24 - bool "Multiply by 24" - -config PLL_MUL_32 - bool "Multiply by 32" - -config PLL_MUL_48 - bool "Multiply by 48" - -endchoice - -config CLOCK_PLL_MUL - int - default 3 if PLL_MUL_3 - default 4 if PLL_MUL_4 - default 6 if PLL_MUL_6 - default 8 if PLL_MUL_8 - default 12 if PLL_MUL_12 - default 16 if PLL_MUL_16 - default 24 if PLL_MUL_24 - default 32 if PLL_MUL_32 - default 48 if PLL_MUL_48 -endif # CPU_FAM_L0 || CPU_FAM_L1 - -if CPU_FAM_G0 -choice -bool "HSISYS division factor" if USE_CLOCK_HSI -default CLOCK_HSISYS_DIV_1 - -config CLOCK_HSISYS_DIV_1 - bool "Divide HSISYS by 1" - -config CLOCK_HSISYS_DIV_2 - bool "Divide HSISYS by 2" - -config CLOCK_HSISYS_DIV_4 - bool "Divide HSISYS by 4" - -config CLOCK_HSISYS_DIV_8 - bool "Divide HSISYS by 8" - -config CLOCK_HSISYS_DIV_16 - bool "Divide HSISYS by 16" - -config CLOCK_HSISYS_DIV_32 - bool "Divide HSISYS by 32" - -config CLOCK_HSISYS_DIV_64 - bool "Divide HSISYS by 64" - -config CLOCK_HSISYS_DIV_128 - bool "Divide HSISYS by 128" - -endchoice - -config CLOCK_HSISYS_DIV - int - default 1 if CLOCK_HSISYS_DIV_1 - default 2 if CLOCK_HSISYS_DIV_2 - default 4 if CLOCK_HSISYS_DIV_4 - default 8 if CLOCK_HSISYS_DIV_8 - default 16 if CLOCK_HSISYS_DIV_16 - default 32 if CLOCK_HSISYS_DIV_32 - default 64 if CLOCK_HSISYS_DIV_64 - default 128 if CLOCK_HSISYS_DIV_128 -endif # CPU_FAM_G0 - -if CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL -choice -bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI) -default CLOCK_MSI_48MHZ if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL -default CLOCK_MSI_4MHZ - -config CLOCK_MSI_65KHZ - bool "65.536kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_100KHZ - bool "100kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_130KHZ - bool "131.072kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_200KHZ - bool "200kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_260KHZ - bool "262.144kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_400KHZ - bool "400kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_520KHZ - bool "524.288kHz" if CPU_FAM_L0 || CPU_FAM_L1 - -config CLOCK_MSI_800KHZ - bool "800kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_1MHZ - bool - prompt "1MHz" - -config CLOCK_MSI_2MHZ - bool - prompt "2MHz" - -config CLOCK_MSI_4MHZ - bool - prompt "4MHz" - -config CLOCK_MSI_8MHZ - bool "8MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_16MHZ - bool "16MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_24MHZ - bool "24MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_32MHZ - bool "32MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MSI_48MHZ - bool "48MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - -endchoice - -config CLOCK_MSI - int - default 65536 if CLOCK_MSI_65KHZ - default 131072 if CLOCK_MSI_130KHZ - default 262144 if CLOCK_MSI_260KHZ - default 524288 if CLOCK_MSI_520KHZ - default 100000 if CLOCK_MSI_100KHZ - default 200000 if CLOCK_MSI_200KHZ - default 400000 if CLOCK_MSI_400KHZ - default 800000 if CLOCK_MSI_800KHZ - default 1000000 if CLOCK_MSI_1MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) - default 1048000 if CLOCK_MSI_1MHZ && (CPU_FAM_L0 || CPU_FAM_L1) - default 2000000 if CLOCK_MSI_2MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) - default 2097000 if CLOCK_MSI_2MHZ && (CPU_FAM_L0 || CPU_FAM_L1) - default 4000000 if CLOCK_MSI_4MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) - default 4194000 if CLOCK_MSI_4MHZ && (CPU_FAM_L0 || CPU_FAM_L1) - default 8000000 if CLOCK_MSI_8MHZ - default 16000000 if CLOCK_MSI_16MHZ - default 24000000 if CLOCK_MSI_24MHZ - default 32000000 if CLOCK_MSI_32MHZ - default 48000000 if CLOCK_MSI_48MHZ - -endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL - choice bool "APB1 prescaler (division factor of HCLK to produce PCLK1)" default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB || CPU_FAM_WL @@ -433,87 +98,3 @@ config CLOCK_APB2_DIV default 4 if CLOCK_APB2_DIV_4 default 8 if CLOCK_APB2_DIV_8 default 16 if CLOCK_APB2_DIV_16 - -if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL -config CLOCK_ENABLE_MCO - bool "Enable MCU Clock Output (MCO) on PA8" - -choice -bool "MCO source" -depends on CLOCK_ENABLE_MCO -default CLOCK_MCO_USE_PLLCLK - -config CLOCK_MCO_USE_PLLCLK - bool "Use PLLCLK as MCO source" - -config CLOCK_MCO_USE_HSE - bool "Use HSE as MCO source" - -config CLOCK_MCO_USE_HSI - bool "Use HSI as MCO source" - -config CLOCK_MCO_USE_LSE - bool "Use LSE as MCO source" - depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MCO_USE_LSI - bool "Use LSI as MCO source" - depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MCO_USE_MSI - bool "Use MSI as MCO source" - depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -config CLOCK_MCO_USE_SYSCLK - bool "Use SYSCLK as MCO source" - -endchoice - -choice -bool "MCO prescaler" -depends on !CLOCK_HAS_NO_MCO_PRE && CLOCK_ENABLE_MCO -default CLOCK_MCO_PRE_1 - -config CLOCK_MCO_PRE_1 - bool "Divide MCO by 1" - -config CLOCK_MCO_PRE_2 - bool "Divide MCO by 2" - -config CLOCK_MCO_PRE_4 - bool "Divide MCO by 4" - -config CLOCK_MCO_PRE_8 - bool "Divide MCO by 8" - -config CLOCK_MCO_PRE_16 - bool "Divide MCO by 16" - -config CLOCK_MCO_PRE_32 - bool "Divide MCO by 32" - depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL - -config CLOCK_MCO_PRE_64 - bool "Divide MCO by 64" - depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL - -config CLOCK_MCO_PRE_128 - bool "Divide MCO by 128" - depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL - -endchoice - -config CLOCK_MCO_PRE - int - default 2 if CLOCK_MCO_PRE_2 - default 4 if CLOCK_MCO_PRE_4 - default 8 if CLOCK_MCO_PRE_8 - default 16 if CLOCK_MCO_PRE_16 - default 32 if CLOCK_MCO_PRE_32 - default 64 if CLOCK_MCO_PRE_64 - default 128 if CLOCK_MCO_PRE_128 - default 1 - -endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL - -endmenu diff --git a/cpu/stm32/kconfigs/f0/Kconfig.clk b/cpu/stm32/kconfigs/f0/Kconfig.clk new file mode 100644 index 000000000000..d4c08b1aa6f8 --- /dev/null +++ b/cpu/stm32/kconfigs/f0/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f0f1f3/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/f0/Kconfig.lines b/cpu/stm32/kconfigs/f0/Kconfig.lines index e52ba029c1a7..28226e48813e 100644 --- a/cpu/stm32/kconfigs/f0/Kconfig.lines +++ b/cpu/stm32/kconfigs/f0/Kconfig.lines @@ -28,6 +28,7 @@ config CPU_LINE_STM32F031X6 select CPU_FAM_F0 select HAS_PERIPH_RTC_MEM select HAS_PERIPH_VBAT + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F038XX bool @@ -40,6 +41,7 @@ config CPU_LINE_STM32F042X6 select CPU_FAM_F0 select HAS_PERIPH_RTC_MEM select HAS_PERIPH_VBAT + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F048XX bool diff --git a/cpu/stm32/kconfigs/f0f1f3/Kconfig.clk b/cpu/stm32/kconfigs/f0f1f3/Kconfig.clk new file mode 100644 index 000000000000..21ef7de8b9a8 --- /dev/null +++ b/cpu/stm32/kconfigs/f0f1f3/Kconfig.clk @@ -0,0 +1,31 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 + +config CLOCK_PLL_PREDIV + int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + default 2 if HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 || CLOCK_HSE = 16000000 + default 1 + range 1 16 + +config CLOCK_PLL_MUL + int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 12 if CPU_FAM_F0 && HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + default 6 if CPU_FAM_F0 + default 16 if CPU_FAM_F3 && HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + default 9 if CPU_FAM_F1 || CPU_FAM_F3 + + range 2 16 + +config HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + bool + help + Indicated that this CPU Line has the prediv hardwired to 2, making it + unable to change. + +endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 diff --git a/cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk b/cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk new file mode 100644 index 000000000000..b08de4271971 --- /dev/null +++ b/cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk @@ -0,0 +1,89 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_ENABLE_MCO + bool "Enable MCU Clock Output (MCO) on PA8" + +choice +bool "MCO source" +depends on CLOCK_ENABLE_MCO +default CLOCK_MCO_USE_PLLCLK + +config CLOCK_MCO_USE_PLLCLK + bool "Use PLLCLK as MCO source" + +config CLOCK_MCO_USE_HSE + bool "Use HSE as MCO source" + +config CLOCK_MCO_USE_HSI + bool "Use HSI as MCO source" + +config CLOCK_MCO_USE_LSE + bool "Use LSE as MCO source" + depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_MCO_USE_LSI + bool "Use LSI as MCO source" + depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_MCO_USE_MSI + bool "Use MSI as MCO source" + depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL + +config CLOCK_MCO_USE_SYSCLK + bool "Use SYSCLK as MCO source" + +endchoice + +choice +bool "MCO prescaler" +depends on !CLOCK_HAS_NO_MCO_PRE && CLOCK_ENABLE_MCO +default CLOCK_MCO_PRE_1 + +config CLOCK_MCO_PRE_1 + bool "Divide MCO by 1" + +config CLOCK_MCO_PRE_2 + bool "Divide MCO by 2" + +config CLOCK_MCO_PRE_4 + bool "Divide MCO by 4" + +config CLOCK_MCO_PRE_8 + bool "Divide MCO by 8" + +config CLOCK_MCO_PRE_16 + bool "Divide MCO by 16" + +config CLOCK_MCO_PRE_32 + bool "Divide MCO by 32" + depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 + +config CLOCK_MCO_PRE_64 + bool "Divide MCO by 64" + depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 + +config CLOCK_MCO_PRE_128 + bool "Divide MCO by 128" + depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 + +endchoice + +config CLOCK_MCO_PRE + int + default 2 if CLOCK_MCO_PRE_2 + default 4 if CLOCK_MCO_PRE_4 + default 8 if CLOCK_MCO_PRE_8 + default 16 if CLOCK_MCO_PRE_16 + default 32 if CLOCK_MCO_PRE_32 + default 64 if CLOCK_MCO_PRE_64 + default 128 if CLOCK_MCO_PRE_128 + default 1 + +endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL diff --git a/cpu/stm32/kconfigs/f1/Kconfig.clk b/cpu/stm32/kconfigs/f1/Kconfig.clk new file mode 100644 index 000000000000..d4c08b1aa6f8 --- /dev/null +++ b/cpu/stm32/kconfigs/f1/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f0f1f3/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/f2/Kconfig.clk b/cpu/stm32/kconfigs/f2/Kconfig.clk new file mode 100644 index 000000000000..bea4721017ef --- /dev/null +++ b/cpu/stm32/kconfigs/f2/Kconfig.clk @@ -0,0 +1,22 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' + +if CPU_FAM_F2 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 4 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 120 if CLOCK_HSE = 8000000 + default 60 + range 50 432 + +endif # CPU_FAM_F2 diff --git a/cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk b/cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk new file mode 100644 index 000000000000..5900f0247eb4 --- /dev/null +++ b/cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk @@ -0,0 +1,54 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 + +choice +bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS +default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ +default PLL_P_DIV_2 + +config PLL_P_DIV_2 + bool "Divide by 2" + +config PLL_P_DIV_4 + bool "Divide by 4" + +config PLL_P_DIV_6 + bool "Divide by 6" + +config PLL_P_DIV_8 + bool "Divide by 8" + +endchoice + +config CLOCK_PLL_P + int + default 3 if CPU_FAM_MP1 + default 2 if PLL_P_DIV_2 + default 4 if PLL_P_DIV_4 + default 6 if PLL_P_DIV_6 + default 8 if PLL_P_DIV_8 + +config CLOCK_PLL_Q + int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS + default 5 if CPU_FAM_F2 + default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ + default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ + default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 9 if CPU_FAM_F7 + default 13 if CPU_FAM_MP1 + default 8 + range 2 15 + +config HAVE_CLOCK_ALT_48MHZ + bool + help + Indicates this CPU has an alternate clock source that can be used to + provide 48 MHz for the USB peripheral. + +endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1 diff --git a/cpu/stm32/kconfigs/f3/Kconfig.clk b/cpu/stm32/kconfigs/f3/Kconfig.clk new file mode 100644 index 000000000000..d4c08b1aa6f8 --- /dev/null +++ b/cpu/stm32/kconfigs/f3/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f0f1f3/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/f3/Kconfig.lines b/cpu/stm32/kconfigs/f3/Kconfig.lines index 8a07aaf22fdb..f964c3a9777a 100644 --- a/cpu/stm32/kconfigs/f3/Kconfig.lines +++ b/cpu/stm32/kconfigs/f3/Kconfig.lines @@ -27,15 +27,27 @@ config CPU_LINE_STM32F302XE bool select CPU_FAM_F3 +config CPU_LINE_STM32F303X6 + bool + select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + config CPU_LINE_STM32F303X8 bool select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 + +config CPU_LINE_STM32F303XB + bool + select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F303XC bool select CPU_FAM_F3 select HAS_CORTEXM_MPU select CLOCK_HAS_NO_MCO_PRE + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F303XE bool @@ -49,6 +61,7 @@ config CPU_LINE_STM32F318XX config CPU_LINE_STM32F328XX bool select CPU_FAM_F3 + select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 config CPU_LINE_STM32F334X8 bool diff --git a/cpu/stm32/kconfigs/f4/Kconfig.clk b/cpu/stm32/kconfigs/f4/Kconfig.clk new file mode 100644 index 000000000000..88f7037dafda --- /dev/null +++ b/cpu/stm32/kconfigs/f4/Kconfig.clk @@ -0,0 +1,43 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' + +if CPU_FAM_F4 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 25 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000 + default 25 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 + default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 + default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 + default 4 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 168 if CLOCK_MAX_84MHZ && CLOCK_HSE = 8000000 + default 336 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000 + default 84 if CLOCK_MAX_84MHZ + + default 96 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 100 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000 + default 192 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 200 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 + default 48 if CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) + default 50 if CLOCK_MAX_100MHZ + + default 168 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 180 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000 + default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 + default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 + default 84 if CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ + default 90 if CLOCK_MAX_180MHZ + range 50 432 + +endif # CPU_FAM_F4 diff --git a/cpu/stm32/kconfigs/f4/Kconfig.lines b/cpu/stm32/kconfigs/f4/Kconfig.lines index 21938fec4d7c..40491548da83 100644 --- a/cpu/stm32/kconfigs/f4/Kconfig.lines +++ b/cpu/stm32/kconfigs/f4/Kconfig.lines @@ -59,28 +59,33 @@ config CPU_LINE_STM32F412CX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F412RX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F412VX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F412ZX bool select CPU_FAM_F4 select HAS_PERIPH_HWRNG select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F413XX bool select CPU_FAM_F4 select HAS_PERIPH_HWRNG select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F415XX bool @@ -99,6 +104,7 @@ config CPU_LINE_STM32F423XX bool select CPU_FAM_F4 select CLOCK_MAX_100MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F427XX bool @@ -132,6 +138,7 @@ config CPU_LINE_STM32F446XX select CPU_FAM_F4 select HAS_BACKUP_RAM select CLOCK_MAX_180MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F469XX bool @@ -139,9 +146,11 @@ config CPU_LINE_STM32F469XX select HAS_BACKUP_RAM select HAS_PERIPH_HWRNG select CLOCK_MAX_180MHZ + select HAVE_CLOCK_ALT_48MHZ config CPU_LINE_STM32F479XX bool select CPU_FAM_F4 select HAS_BACKUP_RAM select CLOCK_MAX_180MHZ + select HAVE_CLOCK_ALT_48MHZ diff --git a/cpu/stm32/kconfigs/f7/Kconfig b/cpu/stm32/kconfigs/f7/Kconfig index 79bfb37d6af2..8b07ec2ecae4 100644 --- a/cpu/stm32/kconfigs/f7/Kconfig +++ b/cpu/stm32/kconfigs/f7/Kconfig @@ -22,6 +22,7 @@ config CPU_FAM_F7 select HAS_PERIPH_VBAT select HAS_PERIPH_WDT select HAS_BOOTLOADER_STM32 + select HAVE_CLOCK_ALT_48MHZ config CPU_FAM default "f7" if CPU_FAM_F7 diff --git a/cpu/stm32/kconfigs/f7/Kconfig.clk b/cpu/stm32/kconfigs/f7/Kconfig.clk new file mode 100644 index 000000000000..25a8096abeb0 --- /dev/null +++ b/cpu/stm32/kconfigs/f7/Kconfig.clk @@ -0,0 +1,24 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' + +if CPU_FAM_F7 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 25 if CLOCK_HSE = 25000000 + default 4 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 216 if CLOCK_HSE = 8000000 + default 432 if CLOCK_HSE = 25000000 + default 108 + range 50 432 + +endif # CPU_FAM_F7 diff --git a/cpu/stm32/kconfigs/g0/Kconfig.clk b/cpu/stm32/kconfigs/g0/Kconfig.clk new file mode 100644 index 000000000000..6a304bedce65 --- /dev/null +++ b/cpu/stm32/kconfigs/g0/Kconfig.clk @@ -0,0 +1,63 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_G0 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 1 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 20 + range 8 86 + +choice +bool "HSISYS division factor" if USE_CLOCK_HSI +default CLOCK_HSISYS_DIV_1 + +config CLOCK_HSISYS_DIV_1 + bool "Divide HSISYS by 1" + +config CLOCK_HSISYS_DIV_2 + bool "Divide HSISYS by 2" + +config CLOCK_HSISYS_DIV_4 + bool "Divide HSISYS by 4" + +config CLOCK_HSISYS_DIV_8 + bool "Divide HSISYS by 8" + +config CLOCK_HSISYS_DIV_16 + bool "Divide HSISYS by 16" + +config CLOCK_HSISYS_DIV_32 + bool "Divide HSISYS by 32" + +config CLOCK_HSISYS_DIV_64 + bool "Divide HSISYS by 64" + +config CLOCK_HSISYS_DIV_128 + bool "Divide HSISYS by 128" + +endchoice + +config CLOCK_HSISYS_DIV + int + default 1 if CLOCK_HSISYS_DIV_1 + default 2 if CLOCK_HSISYS_DIV_2 + default 4 if CLOCK_HSISYS_DIV_4 + default 8 if CLOCK_HSISYS_DIV_8 + default 16 if CLOCK_HSISYS_DIV_16 + default 32 if CLOCK_HSISYS_DIV_32 + default 64 if CLOCK_HSISYS_DIV_64 + default 128 if CLOCK_HSISYS_DIV_128 + +endif # CPU_FAM_G0 diff --git a/cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk b/cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk new file mode 100644 index 000000000000..b0092c6156b4 --- /dev/null +++ b/cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk @@ -0,0 +1,18 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 + +config CLOCK_PLL_R + int "Q: VCO division factor" if CUSTOM_PLL_PARAMS + default 2 if CPU_FAM_WB || CPU_FAM_WL + default 3 if CPU_FAM_MP1 + default 6 if BOARD_HAS_HSE + default 5 + range 2 8 + +endif # CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1 diff --git a/cpu/stm32/kconfigs/g4/Kconfig.clk b/cpu/stm32/kconfigs/g4/Kconfig.clk new file mode 100644 index 000000000000..5253a6518e51 --- /dev/null +++ b/cpu/stm32/kconfigs/g4/Kconfig.clk @@ -0,0 +1,23 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g4l4l5/Kconfig.clk' + +if CPU_FAM_G4 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if BOARD_HAS_HSE + default 4 + range 1 16 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 85 + range 8 127 + +endif # CPU_FAM_G4 diff --git a/cpu/stm32/kconfigs/g4l4l5/Kconfig.clk b/cpu/stm32/kconfigs/g4l4l5/Kconfig.clk new file mode 100644 index 000000000000..313c4284fae4 --- /dev/null +++ b/cpu/stm32/kconfigs/g4l4l5/Kconfig.clk @@ -0,0 +1,35 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 + +choice +bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS +default PLL_R_DIV_2 + +config PLL_R_DIV_2 + bool "Divide by 2" + +config PLL_R_DIV_4 + bool "Divide by 4" + +config PLL_R_DIV_6 + bool "Divide by 6" + +config PLL_R_DIV_8 + bool "Divide by 8" + +endchoice + +config CLOCK_PLL_R + int + default 2 if PLL_R_DIV_2 + default 4 if PLL_R_DIV_4 + default 6 if PLL_R_DIV_6 + default 8 if PLL_R_DIV_8 + +endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 diff --git a/cpu/stm32/kconfigs/l0/Kconfig.clk b/cpu/stm32/kconfigs/l0/Kconfig.clk new file mode 100644 index 000000000000..cab42844c3c5 --- /dev/null +++ b/cpu/stm32/kconfigs/l0/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l0l1/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/l0l1/Kconfig.clk b/cpu/stm32/kconfigs/l0l1/Kconfig.clk new file mode 100644 index 000000000000..eb4bd7d3e106 --- /dev/null +++ b/cpu/stm32/kconfigs/l0l1/Kconfig.clk @@ -0,0 +1,112 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_L0 || CPU_FAM_L1 + +config CLOCK_PLL_DIV + int "Main PLL division factor" if CUSTOM_PLL_PARAMS + default 2 + range 2 4 + +choice +bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS +default PLL_MUL_4 + +config PLL_MUL_3 + bool "Multiply by 3" + +config PLL_MUL_4 + bool "Multiply by 4" + +config PLL_MUL_6 + bool "Multiply by 6" + +config PLL_MUL_8 + bool "Multiply by 8" + +config PLL_MUL_12 + bool "Multiply by 12" + +config PLL_MUL_16 + bool "Multiply by 16" + +config PLL_MUL_24 + bool "Multiply by 24" + +config PLL_MUL_32 + bool "Multiply by 32" + +config PLL_MUL_48 + bool "Multiply by 48" + +endchoice + +config CLOCK_PLL_MUL + int + default 3 if PLL_MUL_3 + default 4 if PLL_MUL_4 + default 6 if PLL_MUL_6 + default 8 if PLL_MUL_8 + default 12 if PLL_MUL_12 + default 16 if PLL_MUL_16 + default 24 if PLL_MUL_24 + default 32 if PLL_MUL_32 + default 48 if PLL_MUL_48 + +config USE_CLOCK_MSI + bool "Use direct multi-speed frequency internal oscillator (MSI)" + +choice +bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI) +default CLOCK_MSI_4MHZ + +config CLOCK_MSI_65KHZ + bool "65.536kHz" + +config CLOCK_MSI_130KHZ + bool "131.072kHz" + +config CLOCK_MSI_260KHZ + bool "262.144kHz" + +config CLOCK_MSI_520KHZ + bool "524.288kHz" + +config CLOCK_MSI_1MHZ + bool + prompt "1MHz" + +config CLOCK_MSI_2MHZ + bool + prompt "2MHz" + +config CLOCK_MSI_4MHZ + bool + prompt "4MHz" + +endchoice + +config CLOCK_MSI + int + default 65536 if CLOCK_MSI_65KHZ + default 131072 if CLOCK_MSI_130KHZ + default 262144 if CLOCK_MSI_260KHZ + default 524288 if CLOCK_MSI_520KHZ + default 100000 if CLOCK_MSI_100KHZ + default 200000 if CLOCK_MSI_200KHZ + default 400000 if CLOCK_MSI_400KHZ + default 800000 if CLOCK_MSI_800KHZ + default 1048000 if CLOCK_MSI_1MHZ + default 2097000 if CLOCK_MSI_2MHZ + default 4194000 if CLOCK_MSI_4MHZ + default 8000000 if CLOCK_MSI_8MHZ + default 16000000 if CLOCK_MSI_16MHZ + default 24000000 if CLOCK_MSI_24MHZ + default 32000000 if CLOCK_MSI_32MHZ + default 48000000 if CLOCK_MSI_48MHZ + +endif # CPU_FAM_L0 || CPU_FAM_L1 diff --git a/cpu/stm32/kconfigs/l1/Kconfig.clk b/cpu/stm32/kconfigs/l1/Kconfig.clk new file mode 100644 index 000000000000..cab42844c3c5 --- /dev/null +++ b/cpu/stm32/kconfigs/l1/Kconfig.clk @@ -0,0 +1,8 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l0l1/Kconfig.clk' diff --git a/cpu/stm32/kconfigs/l4/Kconfig.clk b/cpu/stm32/kconfigs/l4/Kconfig.clk new file mode 100644 index 000000000000..263f0baaae46 --- /dev/null +++ b/cpu/stm32/kconfigs/l4/Kconfig.clk @@ -0,0 +1,25 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g4l4l5/Kconfig.clk' +rsource '../l4l5wx/Kconfig.clk' + +if CPU_FAM_L4 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX + default 20 + range 8 86 + +endif # CPU_FAM_L4 diff --git a/cpu/stm32/kconfigs/l4l5wx/Kconfig.clk b/cpu/stm32/kconfigs/l4l5wx/Kconfig.clk new file mode 100644 index 000000000000..2d76c04c576f --- /dev/null +++ b/cpu/stm32/kconfigs/l4l5wx/Kconfig.clk @@ -0,0 +1,94 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL + +config USE_CLOCK_MSI + bool "Use direct multi-speed frequency internal oscillator (MSI)" + +choice +bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI) +default CLOCK_MSI_48MHZ + +config CLOCK_MSI_100KHZ + bool "100kHz" + +config CLOCK_MSI_200KHZ + bool "200kHz" + +config CLOCK_MSI_400KHZ + bool "400kHz" + +config CLOCK_MSI_800KHZ + bool "800kHz" + +config CLOCK_MSI_1MHZ + bool + prompt "1MHz" + +config CLOCK_MSI_2MHZ + bool + prompt "2MHz" + +config CLOCK_MSI_4MHZ + bool + prompt "4MHz" + +config CLOCK_MSI_8MHZ + bool "8MHz" + +config CLOCK_MSI_16MHZ + bool "16MHz" + +config CLOCK_MSI_24MHZ + bool "24MHz" + +config CLOCK_MSI_32MHZ + bool "32MHz" + +config CLOCK_MSI_48MHZ + bool "48MHz" + +endchoice + +config CLOCK_MSI + int + default 65536 if CLOCK_MSI_65KHZ + default 131072 if CLOCK_MSI_130KHZ + default 262144 if CLOCK_MSI_260KHZ + default 524288 if CLOCK_MSI_520KHZ + default 100000 if CLOCK_MSI_100KHZ + default 200000 if CLOCK_MSI_200KHZ + default 400000 if CLOCK_MSI_400KHZ + default 800000 if CLOCK_MSI_800KHZ + default 1000000 if CLOCK_MSI_1MHZ + default 2000000 if CLOCK_MSI_2MHZ + default 4000000 if CLOCK_MSI_4MHZ + default 8000000 if CLOCK_MSI_8MHZ + default 16000000 if CLOCK_MSI_16MHZ + default 24000000 if CLOCK_MSI_24MHZ + default 32000000 if CLOCK_MSI_32MHZ + default 48000000 if CLOCK_MSI_48MHZ + + +choice +bool "Source clock for PLL" if USE_CLOCK_PLL +default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE +default CLOCK_PLL_SRC_MSI + +config CLOCK_PLL_SRC_MSI + bool "Use MSI source clock" + +config CLOCK_PLL_SRC_HSE + bool "Use HSE source clock" + depends on BOARD_HAS_HSE + +config CLOCK_PLL_SRC_HSI + bool "Use HSI16 source clock" +endchoice + +endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL diff --git a/cpu/stm32/kconfigs/l5/Kconfig.clk b/cpu/stm32/kconfigs/l5/Kconfig.clk new file mode 100644 index 000000000000..d7777cdf326c --- /dev/null +++ b/cpu/stm32/kconfigs/l5/Kconfig.clk @@ -0,0 +1,24 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../g4l4l5/Kconfig.clk' +rsource '../l4l5wx/Kconfig.clk' + +if CPU_FAM_L5 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 27 if CPU_FAM_L5 + range 8 86 + +endif # CPU_FAM_L5 diff --git a/cpu/stm32/kconfigs/mp1/Kconfig.clk b/cpu/stm32/kconfigs/mp1/Kconfig.clk new file mode 100644 index 000000000000..ec5c3bf9bc45 --- /dev/null +++ b/cpu/stm32/kconfigs/mp1/Kconfig.clk @@ -0,0 +1,24 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../f2f4f7mp1/Kconfig.clk' +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_MP1 + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 2 + range 1 64 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 52 if BOARD_HAS_HSE + default 78 + range 4 512 + +endif # CPU_FAM_MP1 diff --git a/cpu/stm32/kconfigs/u5/Kconfig.clk b/cpu/stm32/kconfigs/u5/Kconfig.clk new file mode 100644 index 000000000000..7062ae4ea72a --- /dev/null +++ b/cpu/stm32/kconfigs/u5/Kconfig.clk @@ -0,0 +1,6 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# diff --git a/cpu/stm32/kconfigs/wb/Kconfig.clk b/cpu/stm32/kconfigs/wb/Kconfig.clk new file mode 100644 index 000000000000..943c70f3908d --- /dev/null +++ b/cpu/stm32/kconfigs/wb/Kconfig.clk @@ -0,0 +1,25 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l4l5wx/Kconfig.clk' +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_WB + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 4 if CLOCK_PLL_SRC_HSE + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 16 + range 6 127 + +endif # CPU_FAM_WB diff --git a/cpu/stm32/kconfigs/wl/Kconfig.clk b/cpu/stm32/kconfigs/wl/Kconfig.clk new file mode 100644 index 000000000000..881c890dfb94 --- /dev/null +++ b/cpu/stm32/kconfigs/wl/Kconfig.clk @@ -0,0 +1,25 @@ +# Copyright (c) 2022 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +rsource '../l4l5wx/Kconfig.clk' +rsource '../g0wxmp1/Kconfig.clk' + +if CPU_FAM_WL + +config CLOCK_PLL_M + int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS + default 6 if CLOCK_PLL_SRC_MSI + default 4 if CLOCK_PLL_SRC_HSE + default 2 + range 1 8 + +config CLOCK_PLL_N + int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS + default 12 + range 6 127 + +endif # CPU_FAM_WL diff --git a/cpu/stm32/periph/uart.c b/cpu/stm32/periph/uart.c index b18c8c3921c6..09484842b8c3 100644 --- a/cpu/stm32/periph/uart.c +++ b/cpu/stm32/periph/uart.c @@ -306,10 +306,10 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate) switch (uart_config[uart].clk_src) { case RCC_UART35CKSELR_UART35SRC_2: /* HSI */ - clk = CLOCK_HSI; + clk = CONFIG_CLOCK_HSI; break; case RCC_UART35CKSELR_UART35SRC_4: /* HSE */ - clk = CLOCK_HSE; + clk = CONFIG_CLOCK_HSE; break; default: /* return */ return; diff --git a/cpu/stm32/stmclk/stmclk_gx.c b/cpu/stm32/stmclk/stmclk_gx.c index ded9a44a0fd8..9bbd6f803fba 100644 --- a/cpu/stm32/stmclk/stmclk_gx.c +++ b/cpu/stm32/stmclk/stmclk_gx.c @@ -59,10 +59,10 @@ #endif #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#define PLL_IN CLOCK_HSE +#define PLL_IN CONFIG_CLOCK_HSE #define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE #else -#define PLL_IN CLOCK_HSI +#define PLL_IN CONFIG_CLOCK_HSI #define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI #endif diff --git a/dist/tools/doccheck/exclude_patterns b/dist/tools/doccheck/exclude_patterns index d2846b94fceb..2e80927eab5c 100644 --- a/dist/tools/doccheck/exclude_patterns +++ b/dist/tools/doccheck/exclude_patterns @@ -795,7 +795,7 @@ boards/common/iotlab/include/openwsn_defs\.h:[0-9]+: warning: Member PORT_maxRxD boards/common/iotlab/include/openwsn_defs\.h:[0-9]+: warning: Member PORT_maxTxAckPrepare \(macro definition\) of file openwsn_defs\.h is not documented\. boards/common/iotlab/include/openwsn_defs\.h:[0-9]+: warning: Member PORT_maxTxDataPrepare \(macro definition\) of file openwsn_defs\.h is not documented\. boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf_common\.h is not documented\. -boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf_common\.h is not documented\. +boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf_common\.h is not documented\. boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf_common\.h is not documented\. boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf_common\.h is not documented\. boards/common/iotlab/include/periph_conf_common\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf_common\.h is not documented\. @@ -1263,7 +1263,7 @@ boards/common/weact\-f4x1cx/include/board\.h:[0-9]+: warning: Member XTIMER_BACK boards/common/weact\-f4x1cx/include/board\.h:[0-9]+: warning: Member XTIMER_OVERHEAD \(macro definition\) of file board\.h is not documented\. boards/common/weact\-f4x1cx/include/board\.h:[0-9]+: warning: Member mtd0 \(variable\) of file board\.h is not documented\. boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. -boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/common/weact\-f4x1cx/include/periph_conf\.h:[0-9]+: warning: Member PWM_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. @@ -1389,7 +1389,7 @@ boards/esp32\-wrover\-kit/include/board\.h:[0-9]+: warning: Member LCD_CS \(macr boards/esp32\-wrover\-kit/include/board\.h:[0-9]+: warning: Member LCD_DC \(macro definition\) of file board\.h is not documented\. boards/esp32\-wrover\-kit/include/board\.h:[0-9]+: warning: Member LCD_RST \(macro definition\) of file board\.h is not documented\. boards/f4vi1/include/board\.h:[0-9]+: warning: Member LED_PORT \(macro definition\) of file board\.h is not documented\. -boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member TIMER_0_ISR \(macro definition\) of file periph_conf\.h is not documented\. boards/f4vi1/include/periph_conf\.h:[0-9]+: warning: Member TIMER_1_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -1797,7 +1797,7 @@ boards/lobaro\-lorabox/include/periph_conf\.h:[0-9]+: warning: Member uart_confi boards/lora\-e5\-dev/include/board\.h:[0-9]+: warning: Member FE_CTRL1 \(macro definition\) of file board\.h is not documented\. boards/lora\-e5\-dev/include/board\.h:[0-9]+: warning: Member FE_CTRL2 \(macro definition\) of file board\.h is not documented\. boards/lora\-e5\-dev/include/board\.h:[0-9]+: warning: Member SX126X_PARAM_SPI \(macro definition\) of file board\.h is not documented\. -boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/lora\-e5\-dev/include/periph_conf\.h:[0-9]+: warning: Member I2C_1_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -2068,7 +2068,7 @@ boards/msba2/include/periph_conf\.h:[0-9]+: warning: Member i2c_config\[\] \(var boards/msba2/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/msba2/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. -boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member DAC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. boards/msbiot/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -2887,7 +2887,7 @@ boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member FE_CTRL1 \(macro boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member FE_CTRL2 \(macro definition\) of file board\.h is not documented\. boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member FE_CTRL3 \(macro definition\) of file board\.h is not documented\. boards/nucleo\-wl55jc/include/board\.h:[0-9]+: warning: Member SX126X_PARAM_SPI \(macro definition\) of file board\.h is not documented\. -boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/nucleo\-wl55jc/include/periph_conf\.h:[0-9]+: warning: Member I2C_1_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -3125,7 +3125,7 @@ boards/p\-nucleo\-wb55/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO boards/p\-nucleo\-wb55/include/arduino_pinmap\.h:[0-9]+: warning: Member ARDUINO_PIN_A5 \(macro definition\) of file arduino_pinmap\.h is not documented\. boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_EXTAHB \(macro definition\) of file periph_conf\.h is not documented\. boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_EXTAHB_DIV \(macro definition\) of file periph_conf\.h is not documented\. -boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/p\-nucleo\-wb55/include/periph_conf\.h:[0-9]+: warning: Member SPI_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. @@ -3253,7 +3253,7 @@ boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member I2C_NUMOF \(macro boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member SPI_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member i2c_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/pinetime/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\. -boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/pyboard/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -4513,7 +4513,7 @@ boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member pwm_confi boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member timer_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/stm32f4discovery/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\. -boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member I2C_0_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -4531,7 +4531,7 @@ boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member i2c_conf boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member timer_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/stm32f723e\-disco/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\. -boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f769i\-disco/include/periph_conf\.h:[0-9]+: warning: Member UART_0_DMA_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -4678,7 +4678,7 @@ boards/ublox\-c030\-u201/include/board\.h:[0-9]+: warning: Member SI70XX_SAUL_IN boards/ublox\-c030\-u201/include/board\.h:[0-9]+: warning: Member UB_M_RST_PIN \(macro definition\) of group boards_ublox\-c030\-u201 is not documented\. boards/ublox\-c030\-u201/include/board\.h:[0-9]+: warning: Member UB_PWRON_PIN \(macro definition\) of group boards_ublox\-c030\-u201 is not documented\. boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. -boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/ublox\-c030\-u201/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -6343,11 +6343,11 @@ cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_RX0 \(macro d cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_RX1 \(macro definition\) of file candev_stm32\.h is not documented\. cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_SCE \(macro definition\) of file candev_stm32\.h is not documented\. cpu/stm32/include/candev_stm32\.h:[0-9]+: warning: Member ISR_CAN3_TX \(macro definition\) of file candev_stm32\.h is not documented\. -cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\. -cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CLOCK_HSI \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\. +cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\. +cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSI \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\. cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1\.h:[0-9]+: warning: Member CONFIG_USE_CLOCK_PLL \(macro definition\) of file cfg_clock_common_fx_gx_mp1\.h is not documented\. -cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\. -cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\. +cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\. +cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\. cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_MSI \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\. cpu/stm32/include/clk/cfg_clock_common_lx_wx\.h:[0-9]+: warning: Member CONFIG_USE_CLOCK_PLL \(macro definition\) of file cfg_clock_common_lx_wx\.h is not documented\. cpu/stm32/include/clk/f0f1f3/cfg_clock_default\.h:[0-9]+: warning: Member CLOCK_AHB \(macro definition\) of file cfg_clock_default\.h is not documented\. @@ -12530,7 +12530,7 @@ boards/nucleo\-g431rb/include/periph_conf\.h:[0-9]+: warning: Member PWM_NUMOF \ boards/nucleo\-g431rb/include/periph_conf\.h:[0-9]+: warning: Member pwm_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. -boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_1_ISR \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_NUMOF \(macro definition\) of file periph_conf\.h is not documented\. @@ -12551,7 +12551,7 @@ boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member ADC_NUMO boards/stm32f469i\-disco/include/periph_conf\.h:[0-9]+: warning: Member adc_config\[\] \(variable\) of file periph_conf\.h is not documented\. boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_LSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_BOARD_HAS_HSE \(macro definition\) of file periph_conf\.h is not documented\. -boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. +boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_0_ISR \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_1_ISR \(macro definition\) of file periph_conf\.h is not documented\. boards/stm32f746g\-disco/include/periph_conf\.h:[0-9]+: warning: Member DMA_2_ISR \(macro definition\) of file periph_conf\.h is not documented\. @@ -12617,8 +12617,8 @@ cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CONFIG_CLO cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CLOCK_APB1 \(macro definition\) of file cfg_clock_default\.h is not documented\. cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CONFIG_CLOCK_APB2_DIV \(macro definition\) of file cfg_clock_default\.h is not documented\. cpu/stm32/include/clk/u5/cfg_clock_default\.h:[0-9]+: warning: Member CLOCK_APB2 \(macro definition\) of file cfg_clock_default\.h is not documented\. -cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\. -cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\. +cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSE \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\. +cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_HSI \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\. cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_CLOCK_MSI \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\. cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx\.h:[0-9]+: warning: Member CONFIG_USE_CLOCK_PLL \(macro definition\) of file cfg_clock_common_lx_u5_wx\.h is not documented\. drivers/ft5x06/include/ft5x06_params\.h:[0-9]+: warning: Member FT5X06_PARAM_I2C_DEV \(macro definition\) of file ft5x06_params\.h is not documented\. diff --git a/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c index 92a8220708e9..cc54be288127 100644 --- a/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c +++ b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c @@ -768,7 +768,7 @@ static void _usbdev_init(usbdev_t *dev) _global_regs(usbdev->config)->GCCFG |= USB_OTG_GCCFG_PHYHSEN; /* determine the PLL input clock of the USB HS PHY from HSE clock */ - switch (CLOCK_HSE) { + switch (CONFIG_CLOCK_HSE) { case 12000000: USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL1_PLLSEL_12MHZ; break;