diff --git a/cpu/gd32v/include/periph_cpu.h b/cpu/gd32v/include/periph_cpu.h
index 449e46ffe8c70..b6e85c13e4692 100644
--- a/cpu/gd32v/include/periph_cpu.h
+++ b/cpu/gd32v/include/periph_cpu.h
@@ -40,6 +40,19 @@ extern "C" {
 
 /**
  * @brief   Power modes
+ *
+ * The GD32V has three power modes (terminology as defined by GigaDevice).
+ * - Sleep:      Only the clock of the RISC-V core is switched off.
+ * - Deep sleep: The RISC-V core including all AHB and APB peripheralsa and all
+ *               high speed clocks are off. The LDO is in operation and the
+ *               SRAM is retained.
+ *               The MCU can be woken up by external interrupts or events
+ *               without restart.
+ * - Standby:    The RISC-V core including all AHB and APB peripherals, all
+ *               high-speed clocks, and the LDO are off. The SRAM is not
+ *               retained.
+ *               The MCU can be woken up by WKUP or the NRST pin, watchdog
+ *               reset and RTC alarms with restart.
  */
 enum {
     GD32V_PM_STANDBY = 0,       /**< STANDBY mode,  */