diff --git a/boards/frdm-kw41z/Makefile.dep b/boards/frdm-kw41z/Makefile.dep
index 9290d7a8d2773..82ce32f23ea01 100644
--- a/boards/frdm-kw41z/Makefile.dep
+++ b/boards/frdm-kw41z/Makefile.dep
@@ -5,3 +5,7 @@ ifneq (,$(filter saul_default,$(USEMODULE)))
 #   USEMODULE += saul_gpio
   USEMODULE += saul_adc
 endif
+
+ifneq (,$(filter netdev_default gnrc_netdev_default,$(USEMODULE)))
+  USEMODULE += kw41zrf
+endif
diff --git a/cpu/k60/include/vendor/MK60D10.h b/cpu/k60/include/vendor/MK60D10.h
index 0500f52ba8701..997a76dc1c1b5 100644
--- a/cpu/k60/include/vendor/MK60D10.h
+++ b/cpu/k60/include/vendor/MK60D10.h
@@ -1,21 +1,33 @@
 /*
 ** ###################################################################
+**     Processors:          MK60DN256VLL10
+**                          MK60DN256VLQ10
+**                          MK60DN256VMC10
+**                          MK60DN256VMD10
+**                          MK60DN512VLL10
+**                          MK60DN512VLQ10
+**                          MK60DN512VMC10
+**                          MK60DN512VMD10
+**                          MK60DX256VLL10
+**                          MK60DX256VLQ10
+**                          MK60DX256VMC10
+**                          MK60DX256VMD10
+**
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
-**                          GNU C Compiler - CodeSourcery Sourcery G++
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    K60P144M100SF2V2RM Rev. 2, Jun 2012
-**     Version:             rev. 1.8, 2014-10-14
-**     Build:               b141015
+**     Version:             rev. 1.9, 2015-07-29
+**     Build:               b170112
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MK60D10
 **
-**     Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -26,7 +38,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -41,8 +53,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2012-01-03)
@@ -68,48 +80,29 @@
 **         Update of startup files - possibility to override DefaultISR added.
 **     - rev. 1.8 (2014-10-14)
 **         Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0
-**     - rev. 1.8-jg (2015-05-18)
-**         Removed BITBAND_REG macro.
+**     - rev. 1.9 (2015-07-29)
+**         Correction of backward compatibility.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MK60D10.h
- * @version 1.8-jg
- * @date 2015-05-18
+ * @version 1.9
+ * @date 2015-07-29
  * @brief CMSIS Peripheral Access Layer for MK60D10
  *
  * CMSIS Peripheral Access Layer for MK60D10
  */
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* ----------------------------------------------------------------------------
-   -- MCU activation
-   ---------------------------------------------------------------------------- */
-
-/* Prevention from multiple including the same memory map */
-#if !defined(MK60D10_H_)  /* Check if memory map has not been already included */
-#define MK60D10_H_
-#define MCU_MK60D10
-
-/* Check if another memory map has not been also included */
-#if (defined(MCU_ACTIVE))
-  #error MK60D10 memory map: There is already included another memory map. Only one memory map can be included.
-#endif /* (defined(MCU_ACTIVE)) */
-#define MCU_ACTIVE
-
-#include <stdint.h>
+#ifndef _MK60D10_H_
+#define _MK60D10_H_                              /**< Symbol preventing repeated inclusion */
 
 /** Memory map major version (memory maps with equal major version number are
  * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
+#define MCU_MEM_MAP_VERSION 0x0100U
 /** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+#define MCU_MEM_MAP_VERSION_MINOR 0x0009U
 
 /**
  * @brief Macro to calculate address of an aliased word in the peripheral
@@ -128,7 +121,8 @@ extern "C"
  * @param Bit Bit number to access.
  * @return Value of the targeted bit in the bit band region.
  */
-#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
 /**
  * @brief Macro to access a single bit of a peripheral register (bit band region
  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -137,7 +131,7 @@ extern "C"
  * @param Bit Bit number to access.
  * @return Value of the targeted bit in the bit band region.
  */
-#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
 /**
  * @brief Macro to access a single bit of a peripheral register (bit band region
  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -146,7 +140,7 @@ extern "C"
  * @param Bit Bit number to access.
  * @return Value of the targeted bit in the bit band region.
  */
-#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
 
 /* ----------------------------------------------------------------------------
    -- Interrupt vector numbers
@@ -197,7 +191,7 @@ typedef enum IRQn {
   FTFL_IRQn                    = 18,               /**< FTFL command complete */
   Read_Collision_IRQn          = 19,               /**< FTFL read collision */
   LVD_LVW_IRQn                 = 20,               /**< PMC controller low-voltage detect, low-voltage warning */
-  LLW_IRQn                     = 21,               /**< Low leakage wakeup */
+  LLWU_IRQn                    = 21,               /**< Low leakage wakeup */
   WDOG_EWM_IRQn                = 22,               /**< Single interrupt vector for  WDOG and EWM */
   RNG_IRQn                     = 23,               /**< Randon number generator */
   I2C0_IRQn                    = 24,               /**< Inter-integrated circuit 0 */
@@ -308,6 +302,108 @@ typedef enum IRQn {
  */ /* end of group Cortex_Core_Configuration */
 
 
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< Disable */
+    kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
+    kDmaRequestMux0UART0Rx          = 2|0x100U,    /**< UART0 receive complete */
+    kDmaRequestMux0UART0Tx          = 3|0x100U,    /**< UART0 transmit complete */
+    kDmaRequestMux0UART1Rx          = 4|0x100U,    /**< UART1 receive complete */
+    kDmaRequestMux0UART1Tx          = 5|0x100U,    /**< UART1 transmit complete */
+    kDmaRequestMux0UART2Rx          = 6|0x100U,    /**< UART2 receive complete */
+    kDmaRequestMux0UART2Tx          = 7|0x100U,    /**< UART2 transmit complete */
+    kDmaRequestMux0UART3Rx          = 8|0x100U,    /**< UART3 receive complete */
+    kDmaRequestMux0UART3Tx          = 9|0x100U,    /**< UART3 transmit complete */
+    kDmaRequestMux0UART4Rx          = 10|0x100U,   /**< UART4 receive complete */
+    kDmaRequestMux0UART4Tx          = 11|0x100U,   /**< UART4 transmit complete */
+    kDmaRequestMux0UART5Rx          = 12|0x100U,   /**< UART5 receive complete */
+    kDmaRequestMux0UART5Tx          = 13|0x100U,   /**< UART5 transmit complete */
+    kDmaRequestMux0I2S0Rx           = 14|0x100U,   /**< I2S0 receive complete */
+    kDmaRequestMux0I2S0Tx           = 15|0x100U,   /**< I2S0 transmit complete */
+    kDmaRequestMux0SPI0Rx           = 16|0x100U,   /**< SPI0 receive complete */
+    kDmaRequestMux0SPI0Tx           = 17|0x100U,   /**< SPI0 transmit complete */
+    kDmaRequestMux0SPI1Rx           = 18|0x100U,   /**< SPI1 receive complete */
+    kDmaRequestMux0SPI1Tx           = 19|0x100U,   /**< SPI1 transmit complete */
+    kDmaRequestMux0SPI2Rx           = 20|0x100U,   /**< SPI2 receive complete */
+    kDmaRequestMux0SPI2Tx           = 21|0x100U,   /**< SPI2 transmit complete */
+    kDmaRequestMux0I2C0             = 22|0x100U,   /**< I2C0 transmission complete */
+    kDmaRequestMux0I2C1             = 23|0x100U,   /**< I2C1 transmission complete */
+    kDmaRequestMux0FTM0Channel0     = 24|0x100U,   /**< FTM0 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel1     = 25|0x100U,   /**< FTM0 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel2     = 26|0x100U,   /**< FTM0 channel 2 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel3     = 27|0x100U,   /**< FTM0 channel 3 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel4     = 28|0x100U,   /**< FTM0 channel 4 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel5     = 29|0x100U,   /**< FTM0 channel 5 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel6     = 30|0x100U,   /**< FTM0 channel 6 event (CMP or CAP) */
+    kDmaRequestMux0FTM0Channel7     = 31|0x100U,   /**< FTM0 channel 7 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel0     = 32|0x100U,   /**< FTM1 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM1Channel1     = 33|0x100U,   /**< FTM1 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel0     = 34|0x100U,   /**< FTM2 channel 0 event (CMP or CAP) */
+    kDmaRequestMux0FTM2Channel1     = 35|0x100U,   /**< FTM2 channel 1 event (CMP or CAP) */
+    kDmaRequestMux0IEEE1588Timer0   = 36|0x100U,   /**< Ethernet IEEE 1588 timer 0 */
+    kDmaRequestMux0IEEE1588Timer1   = 37|0x100U,   /**< Ethernet IEEE 1588 timer 1 */
+    kDmaRequestMux0IEEE1588Timer2   = 38|0x100U,   /**< Ethernet IEEE 1588 timer 2 */
+    kDmaRequestMux0IEEE1588Timer3   = 39|0x100U,   /**< Ethernet IEEE 1588 timer 3 */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0 conversion complete */
+    kDmaRequestMux0ADC1             = 41|0x100U,   /**< ADC1 conversion complete */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0 Output */
+    kDmaRequestMux0CMP1             = 43|0x100U,   /**< CMP1 Output */
+    kDmaRequestMux0CMP2             = 44|0x100U,   /**< CMP2 Output */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0DAC1             = 46|0x100U,   /**< DAC1 buffer pointer reaches upper or lower limit */
+    kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT end of modulation cycle event */
+    kDmaRequestMux0PDB0             = 48|0x100U,   /**< PDB0 programmable interrupt delay event */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< PORTA rising, falling or both edges */
+    kDmaRequestMux0PortB            = 50|0x100U,   /**< PORTB rising, falling or both edges */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< PORTC rising, falling or both edges */
+    kDmaRequestMux0PortD            = 52|0x100U,   /**< PORTD rising, falling or both edges */
+    kDmaRequestMux0PortE            = 53|0x100U,   /**< PORTE rising, falling or both edges */
+    kDmaRequestMux0AlwaysOn54       = 54|0x100U,   /**< Always enabled 54 */
+    kDmaRequestMux0AlwaysOn55       = 55|0x100U,   /**< Always enabled 55 */
+    kDmaRequestMux0AlwaysOn56       = 56|0x100U,   /**< Always enabled 56 */
+    kDmaRequestMux0AlwaysOn57       = 57|0x100U,   /**< Always enabled 57 */
+    kDmaRequestMux0AlwaysOn58       = 58|0x100U,   /**< Always enabled 58 */
+    kDmaRequestMux0AlwaysOn59       = 59|0x100U,   /**< Always enabled 59 */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< Always enabled 60 */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< Always enabled 61 */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< Always enabled 62 */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< Always enabled 63 */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
 /* ----------------------------------------------------------------------------
    -- Device Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -373,50 +469,7 @@ typedef struct {
   __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
   __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
   __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type, *ADC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- ADC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register accessors */
-#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
-#define ADC_CFG1_REG(base)                       ((base)->CFG1)
-#define ADC_CFG2_REG(base)                       ((base)->CFG2)
-#define ADC_R_REG(base,index)                    ((base)->R[index])
-#define ADC_CV1_REG(base)                        ((base)->CV1)
-#define ADC_CV2_REG(base)                        ((base)->CV2)
-#define ADC_SC2_REG(base)                        ((base)->SC2)
-#define ADC_SC3_REG(base)                        ((base)->SC3)
-#define ADC_OFS_REG(base)                        ((base)->OFS)
-#define ADC_PG_REG(base)                         ((base)->PG)
-#define ADC_MG_REG(base)                         ((base)->MG)
-#define ADC_CLPD_REG(base)                       ((base)->CLPD)
-#define ADC_CLPS_REG(base)                       ((base)->CLPS)
-#define ADC_CLP4_REG(base)                       ((base)->CLP4)
-#define ADC_CLP3_REG(base)                       ((base)->CLP3)
-#define ADC_CLP2_REG(base)                       ((base)->CLP2)
-#define ADC_CLP1_REG(base)                       ((base)->CLP1)
-#define ADC_CLP0_REG(base)                       ((base)->CLP0)
-#define ADC_PGA_REG(base)                        ((base)->PGA)
-#define ADC_CLMD_REG(base)                       ((base)->CLMD)
-#define ADC_CLMS_REG(base)                       ((base)->CLMS)
-#define ADC_CLM4_REG(base)                       ((base)->CLM4)
-#define ADC_CLM3_REG(base)                       ((base)->CLM3)
-#define ADC_CLM2_REG(base)                       ((base)->CLM2)
-#define ADC_CLM1_REG(base)                       ((base)->CLM1)
-#define ADC_CLM0_REG(base)                       ((base)->CLM0)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
+} ADC_Type;
 
 /* ----------------------------------------------------------------------------
    -- ADC Register Masks
@@ -427,156 +480,208 @@ typedef struct {
  * @{
  */
 
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK                        0x1Fu
-#define ADC_SC1_ADCH_SHIFT                       0
-#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK                        0x20u
-#define ADC_SC1_DIFF_SHIFT                       5
-#define ADC_SC1_AIEN_MASK                        0x40u
-#define ADC_SC1_AIEN_SHIFT                       6
-#define ADC_SC1_COCO_MASK                        0x80u
-#define ADC_SC1_COCO_SHIFT                       7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK                     0x3u
-#define ADC_CFG1_ADICLK_SHIFT                    0
-#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK                       0xCu
-#define ADC_CFG1_MODE_SHIFT                      2
-#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK                     0x10u
-#define ADC_CFG1_ADLSMP_SHIFT                    4
-#define ADC_CFG1_ADIV_MASK                       0x60u
-#define ADC_CFG1_ADIV_SHIFT                      5
-#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK                      0x80u
-#define ADC_CFG1_ADLPC_SHIFT                     7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK                     0x3u
-#define ADC_CFG2_ADLSTS_SHIFT                    0
-#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK                      0x4u
-#define ADC_CFG2_ADHSC_SHIFT                     2
-#define ADC_CFG2_ADACKEN_MASK                    0x8u
-#define ADC_CFG2_ADACKEN_SHIFT                   3
-#define ADC_CFG2_MUXSEL_MASK                     0x10u
-#define ADC_CFG2_MUXSEL_SHIFT                    4
-/* R Bit Fields */
-#define ADC_R_D_MASK                             0xFFFFu
-#define ADC_R_D_SHIFT                            0
-#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK                          0xFFFFu
-#define ADC_CV1_CV_SHIFT                         0
-#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK                          0xFFFFu
-#define ADC_CV2_CV_SHIFT                         0
-#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK                      0x3u
-#define ADC_SC2_REFSEL_SHIFT                     0
-#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK                       0x4u
-#define ADC_SC2_DMAEN_SHIFT                      2
-#define ADC_SC2_ACREN_MASK                       0x8u
-#define ADC_SC2_ACREN_SHIFT                      3
-#define ADC_SC2_ACFGT_MASK                       0x10u
-#define ADC_SC2_ACFGT_SHIFT                      4
-#define ADC_SC2_ACFE_MASK                        0x20u
-#define ADC_SC2_ACFE_SHIFT                       5
-#define ADC_SC2_ADTRG_MASK                       0x40u
-#define ADC_SC2_ADTRG_SHIFT                      6
-#define ADC_SC2_ADACT_MASK                       0x80u
-#define ADC_SC2_ADACT_SHIFT                      7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK                        0x3u
-#define ADC_SC3_AVGS_SHIFT                       0
-#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK                        0x4u
-#define ADC_SC3_AVGE_SHIFT                       2
-#define ADC_SC3_ADCO_MASK                        0x8u
-#define ADC_SC3_ADCO_SHIFT                       3
-#define ADC_SC3_CALF_MASK                        0x40u
-#define ADC_SC3_CALF_SHIFT                       6
-#define ADC_SC3_CAL_MASK                         0x80u
-#define ADC_SC3_CAL_SHIFT                        7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK                         0xFFFFu
-#define ADC_OFS_OFS_SHIFT                        0
-#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK                           0xFFFFu
-#define ADC_PG_PG_SHIFT                          0
-#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK                           0xFFFFu
-#define ADC_MG_MG_SHIFT                          0
-#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK                       0x3Fu
-#define ADC_CLPD_CLPD_SHIFT                      0
-#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK                       0x3Fu
-#define ADC_CLPS_CLPS_SHIFT                      0
-#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK                       0x3FFu
-#define ADC_CLP4_CLP4_SHIFT                      0
-#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK                       0x1FFu
-#define ADC_CLP3_CLP3_SHIFT                      0
-#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK                       0xFFu
-#define ADC_CLP2_CLP2_SHIFT                      0
-#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK                       0x7Fu
-#define ADC_CLP1_CLP1_SHIFT                      0
-#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK                       0x3Fu
-#define ADC_CLP0_CLP0_SHIFT                      0
-#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* PGA Bit Fields */
-#define ADC_PGA_PGAG_MASK                        0xF0000u
-#define ADC_PGA_PGAG_SHIFT                       16
-#define ADC_PGA_PGAG(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
-#define ADC_PGA_PGALPb_MASK                      0x100000u
-#define ADC_PGA_PGALPb_SHIFT                     20
-#define ADC_PGA_PGAEN_MASK                       0x800000u
-#define ADC_PGA_PGAEN_SHIFT                      23
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK                       0x3Fu
-#define ADC_CLMD_CLMD_SHIFT                      0
-#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK                       0x3Fu
-#define ADC_CLMS_CLMS_SHIFT                      0
-#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK                       0x3FFu
-#define ADC_CLM4_CLM4_SHIFT                      0
-#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK                       0x1FFu
-#define ADC_CLM3_CLM3_SHIFT                      0
-#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK                       0xFFu
-#define ADC_CLM2_CLM2_SHIFT                      0
-#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK                       0x7Fu
-#define ADC_CLM1_CLM1_SHIFT                      0
-#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK                       0x3Fu
-#define ADC_CLM0_CLM0_SHIFT                      0
-#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK                        (0x1FU)
+#define ADC_SC1_ADCH_SHIFT                       (0U)
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        (0x20U)
+#define ADC_SC1_DIFF_SHIFT                       (5U)
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        (0x40U)
+#define ADC_SC1_AIEN_SHIFT                       (6U)
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        (0x80U)
+#define ADC_SC1_COCO_SHIFT                       (7U)
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT                            (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK                     (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT                    (0U)
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       (0xCU)
+#define ADC_CFG1_MODE_SHIFT                      (2U)
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT                    (4U)
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       (0x60U)
+#define ADC_CFG1_ADIV_SHIFT                      (5U)
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT                     (7U)
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK                     (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT                    (0U)
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT                     (2U)
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT                   (3U)
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT                    (4U)
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK                             (0xFFFFU)
+#define ADC_R_D_SHIFT                            (0U)
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT                              (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK                          (0xFFFFU)
+#define ADC_CV1_CV_SHIFT                         (0U)
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK                          (0xFFFFU)
+#define ADC_CV2_CV_SHIFT                         (0U)
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK                      (0x3U)
+#define ADC_SC2_REFSEL_SHIFT                     (0U)
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       (0x4U)
+#define ADC_SC2_DMAEN_SHIFT                      (2U)
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       (0x8U)
+#define ADC_SC2_ACREN_SHIFT                      (3U)
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       (0x10U)
+#define ADC_SC2_ACFGT_SHIFT                      (4U)
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        (0x20U)
+#define ADC_SC2_ACFE_SHIFT                       (5U)
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       (0x40U)
+#define ADC_SC2_ADTRG_SHIFT                      (6U)
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       (0x80U)
+#define ADC_SC2_ADACT_SHIFT                      (7U)
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK                        (0x3U)
+#define ADC_SC3_AVGS_SHIFT                       (0U)
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        (0x4U)
+#define ADC_SC3_AVGE_SHIFT                       (2U)
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        (0x8U)
+#define ADC_SC3_ADCO_SHIFT                       (3U)
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        (0x40U)
+#define ADC_SC3_CALF_SHIFT                       (6U)
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         (0x80U)
+#define ADC_SC3_CAL_SHIFT                        (7U)
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK                         (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT                        (0U)
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK                           (0xFFFFU)
+#define ADC_PG_PG_SHIFT                          (0U)
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK                           (0xFFFFU)
+#define ADC_MG_MG_SHIFT                          (0U)
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK                       (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT                      (0U)
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK                       (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT                      (0U)
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK                       (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT                      (0U)
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK                       (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT                      (0U)
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK                       (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT                      (0U)
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK                       (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT                      (0U)
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK                       (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT                      (0U)
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name PGA - ADC PGA Register */
+#define ADC_PGA_PGAG_MASK                        (0xF0000U)
+#define ADC_PGA_PGAG_SHIFT                       (16U)
+#define ADC_PGA_PGAG(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGAG_SHIFT)) & ADC_PGA_PGAG_MASK)
+#define ADC_PGA_PGALPb_MASK                      (0x100000U)
+#define ADC_PGA_PGALPb_SHIFT                     (20U)
+#define ADC_PGA_PGALPb(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGALPb_SHIFT)) & ADC_PGA_PGALPb_MASK)
+#define ADC_PGA_PGAEN_MASK                       (0x800000U)
+#define ADC_PGA_PGAEN_SHIFT                      (23U)
+#define ADC_PGA_PGAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGAEN_SHIFT)) & ADC_PGA_PGAEN_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK                       (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT                      (0U)
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK                       (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT                      (0U)
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK                       (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT                      (0U)
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK                       (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT                      (0U)
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK                       (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT                      (0U)
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK                       (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT                      (0U)
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK                       (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT                      (0U)
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
 
 /*!
  * @}
@@ -588,12 +693,10 @@ typedef struct {
 #define ADC0_BASE                                (0x4003B000u)
 /** Peripheral ADC0 base pointer */
 #define ADC0                                     ((ADC_Type *)ADC0_BASE)
-#define ADC0_BASE_PTR                            (ADC0)
 /** Peripheral ADC1 base address */
 #define ADC1_BASE                                (0x400BB000u)
 /** Peripheral ADC1 base pointer */
 #define ADC1                                     ((ADC_Type *)ADC1_BASE)
-#define ADC1_BASE_PTR                            (ADC1)
 /** Array initializer of ADC peripheral base addresses */
 #define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
 /** Array initializer of ADC peripheral base pointers */
@@ -601,87 +704,6 @@ typedef struct {
 /** Interrupt vectors for the ADC peripheral type */
 #define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- ADC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register instance definitions */
-/* ADC0 */
-#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
-#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
-#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
-#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
-#define ADC0_RA                                  ADC_R_REG(ADC0,0)
-#define ADC0_RB                                  ADC_R_REG(ADC0,1)
-#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
-#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
-#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
-#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
-#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
-#define ADC0_PG                                  ADC_PG_REG(ADC0)
-#define ADC0_MG                                  ADC_MG_REG(ADC0)
-#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
-#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
-#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
-#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
-#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
-#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
-#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
-#define ADC0_PGA                                 ADC_PGA_REG(ADC0)
-#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
-#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
-#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
-#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
-#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
-#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
-#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
-/* ADC1 */
-#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
-#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
-#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
-#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
-#define ADC1_RA                                  ADC_R_REG(ADC1,0)
-#define ADC1_RB                                  ADC_R_REG(ADC1,1)
-#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
-#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
-#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
-#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
-#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
-#define ADC1_PG                                  ADC_PG_REG(ADC1)
-#define ADC1_MG                                  ADC_MG_REG(ADC1)
-#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
-#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
-#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
-#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
-#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
-#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
-#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
-#define ADC1_PGA                                 ADC_PGA_REG(ADC1)
-#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
-#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
-#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
-#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
-#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
-#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
-#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
-
-/* ADC - Register array accessors */
-#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
-#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
-#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
-#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group ADC_Peripheral_Access_Layer */
@@ -717,41 +739,7 @@ typedef struct {
   __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
   __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
   __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
-} AIPS_Type, *AIPS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- AIPS - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
- * @{
- */
-
-
-/* AIPS - Register accessors */
-#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
-#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
-#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
-#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
-#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
-#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
-#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
-#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
-#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
-#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
-#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
-#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
-#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
-#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
-#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
-#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
-#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
-
-/*!
- * @}
- */ /* end of group AIPS_Register_Accessor_Macros */
-
+} AIPS_Type;
 
 /* ----------------------------------------------------------------------------
    -- AIPS Register Masks
@@ -762,827 +750,1246 @@ typedef struct {
  * @{
  */
 
-/* MPRA Bit Fields */
-#define AIPS_MPRA_MPL5_MASK                      0x100u
-#define AIPS_MPRA_MPL5_SHIFT                     8
-#define AIPS_MPRA_MTW5_MASK                      0x200u
-#define AIPS_MPRA_MTW5_SHIFT                     9
-#define AIPS_MPRA_MTR5_MASK                      0x400u
-#define AIPS_MPRA_MTR5_SHIFT                     10
-#define AIPS_MPRA_MPL4_MASK                      0x1000u
-#define AIPS_MPRA_MPL4_SHIFT                     12
-#define AIPS_MPRA_MTW4_MASK                      0x2000u
-#define AIPS_MPRA_MTW4_SHIFT                     13
-#define AIPS_MPRA_MTR4_MASK                      0x4000u
-#define AIPS_MPRA_MTR4_SHIFT                     14
-#define AIPS_MPRA_MPL3_MASK                      0x10000u
-#define AIPS_MPRA_MPL3_SHIFT                     16
-#define AIPS_MPRA_MTW3_MASK                      0x20000u
-#define AIPS_MPRA_MTW3_SHIFT                     17
-#define AIPS_MPRA_MTR3_MASK                      0x40000u
-#define AIPS_MPRA_MTR3_SHIFT                     18
-#define AIPS_MPRA_MPL2_MASK                      0x100000u
-#define AIPS_MPRA_MPL2_SHIFT                     20
-#define AIPS_MPRA_MTW2_MASK                      0x200000u
-#define AIPS_MPRA_MTW2_SHIFT                     21
-#define AIPS_MPRA_MTR2_MASK                      0x400000u
-#define AIPS_MPRA_MTR2_SHIFT                     22
-#define AIPS_MPRA_MPL1_MASK                      0x1000000u
-#define AIPS_MPRA_MPL1_SHIFT                     24
-#define AIPS_MPRA_MTW1_MASK                      0x2000000u
-#define AIPS_MPRA_MTW1_SHIFT                     25
-#define AIPS_MPRA_MTR1_MASK                      0x4000000u
-#define AIPS_MPRA_MTR1_SHIFT                     26
-#define AIPS_MPRA_MPL0_MASK                      0x10000000u
-#define AIPS_MPRA_MPL0_SHIFT                     28
-#define AIPS_MPRA_MTW0_MASK                      0x20000000u
-#define AIPS_MPRA_MTW0_SHIFT                     29
-#define AIPS_MPRA_MTR0_MASK                      0x40000000u
-#define AIPS_MPRA_MTR0_SHIFT                     30
-/* PACRA Bit Fields */
-#define AIPS_PACRA_TP7_MASK                      0x1u
-#define AIPS_PACRA_TP7_SHIFT                     0
-#define AIPS_PACRA_WP7_MASK                      0x2u
-#define AIPS_PACRA_WP7_SHIFT                     1
-#define AIPS_PACRA_SP7_MASK                      0x4u
-#define AIPS_PACRA_SP7_SHIFT                     2
-#define AIPS_PACRA_TP6_MASK                      0x10u
-#define AIPS_PACRA_TP6_SHIFT                     4
-#define AIPS_PACRA_WP6_MASK                      0x20u
-#define AIPS_PACRA_WP6_SHIFT                     5
-#define AIPS_PACRA_SP6_MASK                      0x40u
-#define AIPS_PACRA_SP6_SHIFT                     6
-#define AIPS_PACRA_TP5_MASK                      0x100u
-#define AIPS_PACRA_TP5_SHIFT                     8
-#define AIPS_PACRA_WP5_MASK                      0x200u
-#define AIPS_PACRA_WP5_SHIFT                     9
-#define AIPS_PACRA_SP5_MASK                      0x400u
-#define AIPS_PACRA_SP5_SHIFT                     10
-#define AIPS_PACRA_TP4_MASK                      0x1000u
-#define AIPS_PACRA_TP4_SHIFT                     12
-#define AIPS_PACRA_WP4_MASK                      0x2000u
-#define AIPS_PACRA_WP4_SHIFT                     13
-#define AIPS_PACRA_SP4_MASK                      0x4000u
-#define AIPS_PACRA_SP4_SHIFT                     14
-#define AIPS_PACRA_TP3_MASK                      0x10000u
-#define AIPS_PACRA_TP3_SHIFT                     16
-#define AIPS_PACRA_WP3_MASK                      0x20000u
-#define AIPS_PACRA_WP3_SHIFT                     17
-#define AIPS_PACRA_SP3_MASK                      0x40000u
-#define AIPS_PACRA_SP3_SHIFT                     18
-#define AIPS_PACRA_TP2_MASK                      0x100000u
-#define AIPS_PACRA_TP2_SHIFT                     20
-#define AIPS_PACRA_WP2_MASK                      0x200000u
-#define AIPS_PACRA_WP2_SHIFT                     21
-#define AIPS_PACRA_SP2_MASK                      0x400000u
-#define AIPS_PACRA_SP2_SHIFT                     22
-#define AIPS_PACRA_TP1_MASK                      0x1000000u
-#define AIPS_PACRA_TP1_SHIFT                     24
-#define AIPS_PACRA_WP1_MASK                      0x2000000u
-#define AIPS_PACRA_WP1_SHIFT                     25
-#define AIPS_PACRA_SP1_MASK                      0x4000000u
-#define AIPS_PACRA_SP1_SHIFT                     26
-#define AIPS_PACRA_TP0_MASK                      0x10000000u
-#define AIPS_PACRA_TP0_SHIFT                     28
-#define AIPS_PACRA_WP0_MASK                      0x20000000u
-#define AIPS_PACRA_WP0_SHIFT                     29
-#define AIPS_PACRA_SP0_MASK                      0x40000000u
-#define AIPS_PACRA_SP0_SHIFT                     30
-/* PACRB Bit Fields */
-#define AIPS_PACRB_TP7_MASK                      0x1u
-#define AIPS_PACRB_TP7_SHIFT                     0
-#define AIPS_PACRB_WP7_MASK                      0x2u
-#define AIPS_PACRB_WP7_SHIFT                     1
-#define AIPS_PACRB_SP7_MASK                      0x4u
-#define AIPS_PACRB_SP7_SHIFT                     2
-#define AIPS_PACRB_TP6_MASK                      0x10u
-#define AIPS_PACRB_TP6_SHIFT                     4
-#define AIPS_PACRB_WP6_MASK                      0x20u
-#define AIPS_PACRB_WP6_SHIFT                     5
-#define AIPS_PACRB_SP6_MASK                      0x40u
-#define AIPS_PACRB_SP6_SHIFT                     6
-#define AIPS_PACRB_TP5_MASK                      0x100u
-#define AIPS_PACRB_TP5_SHIFT                     8
-#define AIPS_PACRB_WP5_MASK                      0x200u
-#define AIPS_PACRB_WP5_SHIFT                     9
-#define AIPS_PACRB_SP5_MASK                      0x400u
-#define AIPS_PACRB_SP5_SHIFT                     10
-#define AIPS_PACRB_TP4_MASK                      0x1000u
-#define AIPS_PACRB_TP4_SHIFT                     12
-#define AIPS_PACRB_WP4_MASK                      0x2000u
-#define AIPS_PACRB_WP4_SHIFT                     13
-#define AIPS_PACRB_SP4_MASK                      0x4000u
-#define AIPS_PACRB_SP4_SHIFT                     14
-#define AIPS_PACRB_TP3_MASK                      0x10000u
-#define AIPS_PACRB_TP3_SHIFT                     16
-#define AIPS_PACRB_WP3_MASK                      0x20000u
-#define AIPS_PACRB_WP3_SHIFT                     17
-#define AIPS_PACRB_SP3_MASK                      0x40000u
-#define AIPS_PACRB_SP3_SHIFT                     18
-#define AIPS_PACRB_TP2_MASK                      0x100000u
-#define AIPS_PACRB_TP2_SHIFT                     20
-#define AIPS_PACRB_WP2_MASK                      0x200000u
-#define AIPS_PACRB_WP2_SHIFT                     21
-#define AIPS_PACRB_SP2_MASK                      0x400000u
-#define AIPS_PACRB_SP2_SHIFT                     22
-#define AIPS_PACRB_TP1_MASK                      0x1000000u
-#define AIPS_PACRB_TP1_SHIFT                     24
-#define AIPS_PACRB_WP1_MASK                      0x2000000u
-#define AIPS_PACRB_WP1_SHIFT                     25
-#define AIPS_PACRB_SP1_MASK                      0x4000000u
-#define AIPS_PACRB_SP1_SHIFT                     26
-#define AIPS_PACRB_TP0_MASK                      0x10000000u
-#define AIPS_PACRB_TP0_SHIFT                     28
-#define AIPS_PACRB_WP0_MASK                      0x20000000u
-#define AIPS_PACRB_WP0_SHIFT                     29
-#define AIPS_PACRB_SP0_MASK                      0x40000000u
-#define AIPS_PACRB_SP0_SHIFT                     30
-/* PACRC Bit Fields */
-#define AIPS_PACRC_TP7_MASK                      0x1u
-#define AIPS_PACRC_TP7_SHIFT                     0
-#define AIPS_PACRC_WP7_MASK                      0x2u
-#define AIPS_PACRC_WP7_SHIFT                     1
-#define AIPS_PACRC_SP7_MASK                      0x4u
-#define AIPS_PACRC_SP7_SHIFT                     2
-#define AIPS_PACRC_TP6_MASK                      0x10u
-#define AIPS_PACRC_TP6_SHIFT                     4
-#define AIPS_PACRC_WP6_MASK                      0x20u
-#define AIPS_PACRC_WP6_SHIFT                     5
-#define AIPS_PACRC_SP6_MASK                      0x40u
-#define AIPS_PACRC_SP6_SHIFT                     6
-#define AIPS_PACRC_TP5_MASK                      0x100u
-#define AIPS_PACRC_TP5_SHIFT                     8
-#define AIPS_PACRC_WP5_MASK                      0x200u
-#define AIPS_PACRC_WP5_SHIFT                     9
-#define AIPS_PACRC_SP5_MASK                      0x400u
-#define AIPS_PACRC_SP5_SHIFT                     10
-#define AIPS_PACRC_TP4_MASK                      0x1000u
-#define AIPS_PACRC_TP4_SHIFT                     12
-#define AIPS_PACRC_WP4_MASK                      0x2000u
-#define AIPS_PACRC_WP4_SHIFT                     13
-#define AIPS_PACRC_SP4_MASK                      0x4000u
-#define AIPS_PACRC_SP4_SHIFT                     14
-#define AIPS_PACRC_TP3_MASK                      0x10000u
-#define AIPS_PACRC_TP3_SHIFT                     16
-#define AIPS_PACRC_WP3_MASK                      0x20000u
-#define AIPS_PACRC_WP3_SHIFT                     17
-#define AIPS_PACRC_SP3_MASK                      0x40000u
-#define AIPS_PACRC_SP3_SHIFT                     18
-#define AIPS_PACRC_TP2_MASK                      0x100000u
-#define AIPS_PACRC_TP2_SHIFT                     20
-#define AIPS_PACRC_WP2_MASK                      0x200000u
-#define AIPS_PACRC_WP2_SHIFT                     21
-#define AIPS_PACRC_SP2_MASK                      0x400000u
-#define AIPS_PACRC_SP2_SHIFT                     22
-#define AIPS_PACRC_TP1_MASK                      0x1000000u
-#define AIPS_PACRC_TP1_SHIFT                     24
-#define AIPS_PACRC_WP1_MASK                      0x2000000u
-#define AIPS_PACRC_WP1_SHIFT                     25
-#define AIPS_PACRC_SP1_MASK                      0x4000000u
-#define AIPS_PACRC_SP1_SHIFT                     26
-#define AIPS_PACRC_TP0_MASK                      0x10000000u
-#define AIPS_PACRC_TP0_SHIFT                     28
-#define AIPS_PACRC_WP0_MASK                      0x20000000u
-#define AIPS_PACRC_WP0_SHIFT                     29
-#define AIPS_PACRC_SP0_MASK                      0x40000000u
-#define AIPS_PACRC_SP0_SHIFT                     30
-/* PACRD Bit Fields */
-#define AIPS_PACRD_TP7_MASK                      0x1u
-#define AIPS_PACRD_TP7_SHIFT                     0
-#define AIPS_PACRD_WP7_MASK                      0x2u
-#define AIPS_PACRD_WP7_SHIFT                     1
-#define AIPS_PACRD_SP7_MASK                      0x4u
-#define AIPS_PACRD_SP7_SHIFT                     2
-#define AIPS_PACRD_TP6_MASK                      0x10u
-#define AIPS_PACRD_TP6_SHIFT                     4
-#define AIPS_PACRD_WP6_MASK                      0x20u
-#define AIPS_PACRD_WP6_SHIFT                     5
-#define AIPS_PACRD_SP6_MASK                      0x40u
-#define AIPS_PACRD_SP6_SHIFT                     6
-#define AIPS_PACRD_TP5_MASK                      0x100u
-#define AIPS_PACRD_TP5_SHIFT                     8
-#define AIPS_PACRD_WP5_MASK                      0x200u
-#define AIPS_PACRD_WP5_SHIFT                     9
-#define AIPS_PACRD_SP5_MASK                      0x400u
-#define AIPS_PACRD_SP5_SHIFT                     10
-#define AIPS_PACRD_TP4_MASK                      0x1000u
-#define AIPS_PACRD_TP4_SHIFT                     12
-#define AIPS_PACRD_WP4_MASK                      0x2000u
-#define AIPS_PACRD_WP4_SHIFT                     13
-#define AIPS_PACRD_SP4_MASK                      0x4000u
-#define AIPS_PACRD_SP4_SHIFT                     14
-#define AIPS_PACRD_TP3_MASK                      0x10000u
-#define AIPS_PACRD_TP3_SHIFT                     16
-#define AIPS_PACRD_WP3_MASK                      0x20000u
-#define AIPS_PACRD_WP3_SHIFT                     17
-#define AIPS_PACRD_SP3_MASK                      0x40000u
-#define AIPS_PACRD_SP3_SHIFT                     18
-#define AIPS_PACRD_TP2_MASK                      0x100000u
-#define AIPS_PACRD_TP2_SHIFT                     20
-#define AIPS_PACRD_WP2_MASK                      0x200000u
-#define AIPS_PACRD_WP2_SHIFT                     21
-#define AIPS_PACRD_SP2_MASK                      0x400000u
-#define AIPS_PACRD_SP2_SHIFT                     22
-#define AIPS_PACRD_TP1_MASK                      0x1000000u
-#define AIPS_PACRD_TP1_SHIFT                     24
-#define AIPS_PACRD_WP1_MASK                      0x2000000u
-#define AIPS_PACRD_WP1_SHIFT                     25
-#define AIPS_PACRD_SP1_MASK                      0x4000000u
-#define AIPS_PACRD_SP1_SHIFT                     26
-#define AIPS_PACRD_TP0_MASK                      0x10000000u
-#define AIPS_PACRD_TP0_SHIFT                     28
-#define AIPS_PACRD_WP0_MASK                      0x20000000u
-#define AIPS_PACRD_WP0_SHIFT                     29
-#define AIPS_PACRD_SP0_MASK                      0x40000000u
-#define AIPS_PACRD_SP0_SHIFT                     30
-/* PACRE Bit Fields */
-#define AIPS_PACRE_TP7_MASK                      0x1u
-#define AIPS_PACRE_TP7_SHIFT                     0
-#define AIPS_PACRE_WP7_MASK                      0x2u
-#define AIPS_PACRE_WP7_SHIFT                     1
-#define AIPS_PACRE_SP7_MASK                      0x4u
-#define AIPS_PACRE_SP7_SHIFT                     2
-#define AIPS_PACRE_TP6_MASK                      0x10u
-#define AIPS_PACRE_TP6_SHIFT                     4
-#define AIPS_PACRE_WP6_MASK                      0x20u
-#define AIPS_PACRE_WP6_SHIFT                     5
-#define AIPS_PACRE_SP6_MASK                      0x40u
-#define AIPS_PACRE_SP6_SHIFT                     6
-#define AIPS_PACRE_TP5_MASK                      0x100u
-#define AIPS_PACRE_TP5_SHIFT                     8
-#define AIPS_PACRE_WP5_MASK                      0x200u
-#define AIPS_PACRE_WP5_SHIFT                     9
-#define AIPS_PACRE_SP5_MASK                      0x400u
-#define AIPS_PACRE_SP5_SHIFT                     10
-#define AIPS_PACRE_TP4_MASK                      0x1000u
-#define AIPS_PACRE_TP4_SHIFT                     12
-#define AIPS_PACRE_WP4_MASK                      0x2000u
-#define AIPS_PACRE_WP4_SHIFT                     13
-#define AIPS_PACRE_SP4_MASK                      0x4000u
-#define AIPS_PACRE_SP4_SHIFT                     14
-#define AIPS_PACRE_TP3_MASK                      0x10000u
-#define AIPS_PACRE_TP3_SHIFT                     16
-#define AIPS_PACRE_WP3_MASK                      0x20000u
-#define AIPS_PACRE_WP3_SHIFT                     17
-#define AIPS_PACRE_SP3_MASK                      0x40000u
-#define AIPS_PACRE_SP3_SHIFT                     18
-#define AIPS_PACRE_TP2_MASK                      0x100000u
-#define AIPS_PACRE_TP2_SHIFT                     20
-#define AIPS_PACRE_WP2_MASK                      0x200000u
-#define AIPS_PACRE_WP2_SHIFT                     21
-#define AIPS_PACRE_SP2_MASK                      0x400000u
-#define AIPS_PACRE_SP2_SHIFT                     22
-#define AIPS_PACRE_TP1_MASK                      0x1000000u
-#define AIPS_PACRE_TP1_SHIFT                     24
-#define AIPS_PACRE_WP1_MASK                      0x2000000u
-#define AIPS_PACRE_WP1_SHIFT                     25
-#define AIPS_PACRE_SP1_MASK                      0x4000000u
-#define AIPS_PACRE_SP1_SHIFT                     26
-#define AIPS_PACRE_TP0_MASK                      0x10000000u
-#define AIPS_PACRE_TP0_SHIFT                     28
-#define AIPS_PACRE_WP0_MASK                      0x20000000u
-#define AIPS_PACRE_WP0_SHIFT                     29
-#define AIPS_PACRE_SP0_MASK                      0x40000000u
-#define AIPS_PACRE_SP0_SHIFT                     30
-/* PACRF Bit Fields */
-#define AIPS_PACRF_TP7_MASK                      0x1u
-#define AIPS_PACRF_TP7_SHIFT                     0
-#define AIPS_PACRF_WP7_MASK                      0x2u
-#define AIPS_PACRF_WP7_SHIFT                     1
-#define AIPS_PACRF_SP7_MASK                      0x4u
-#define AIPS_PACRF_SP7_SHIFT                     2
-#define AIPS_PACRF_TP6_MASK                      0x10u
-#define AIPS_PACRF_TP6_SHIFT                     4
-#define AIPS_PACRF_WP6_MASK                      0x20u
-#define AIPS_PACRF_WP6_SHIFT                     5
-#define AIPS_PACRF_SP6_MASK                      0x40u
-#define AIPS_PACRF_SP6_SHIFT                     6
-#define AIPS_PACRF_TP5_MASK                      0x100u
-#define AIPS_PACRF_TP5_SHIFT                     8
-#define AIPS_PACRF_WP5_MASK                      0x200u
-#define AIPS_PACRF_WP5_SHIFT                     9
-#define AIPS_PACRF_SP5_MASK                      0x400u
-#define AIPS_PACRF_SP5_SHIFT                     10
-#define AIPS_PACRF_TP4_MASK                      0x1000u
-#define AIPS_PACRF_TP4_SHIFT                     12
-#define AIPS_PACRF_WP4_MASK                      0x2000u
-#define AIPS_PACRF_WP4_SHIFT                     13
-#define AIPS_PACRF_SP4_MASK                      0x4000u
-#define AIPS_PACRF_SP4_SHIFT                     14
-#define AIPS_PACRF_TP3_MASK                      0x10000u
-#define AIPS_PACRF_TP3_SHIFT                     16
-#define AIPS_PACRF_WP3_MASK                      0x20000u
-#define AIPS_PACRF_WP3_SHIFT                     17
-#define AIPS_PACRF_SP3_MASK                      0x40000u
-#define AIPS_PACRF_SP3_SHIFT                     18
-#define AIPS_PACRF_TP2_MASK                      0x100000u
-#define AIPS_PACRF_TP2_SHIFT                     20
-#define AIPS_PACRF_WP2_MASK                      0x200000u
-#define AIPS_PACRF_WP2_SHIFT                     21
-#define AIPS_PACRF_SP2_MASK                      0x400000u
-#define AIPS_PACRF_SP2_SHIFT                     22
-#define AIPS_PACRF_TP1_MASK                      0x1000000u
-#define AIPS_PACRF_TP1_SHIFT                     24
-#define AIPS_PACRF_WP1_MASK                      0x2000000u
-#define AIPS_PACRF_WP1_SHIFT                     25
-#define AIPS_PACRF_SP1_MASK                      0x4000000u
-#define AIPS_PACRF_SP1_SHIFT                     26
-#define AIPS_PACRF_TP0_MASK                      0x10000000u
-#define AIPS_PACRF_TP0_SHIFT                     28
-#define AIPS_PACRF_WP0_MASK                      0x20000000u
-#define AIPS_PACRF_WP0_SHIFT                     29
-#define AIPS_PACRF_SP0_MASK                      0x40000000u
-#define AIPS_PACRF_SP0_SHIFT                     30
-/* PACRG Bit Fields */
-#define AIPS_PACRG_TP7_MASK                      0x1u
-#define AIPS_PACRG_TP7_SHIFT                     0
-#define AIPS_PACRG_WP7_MASK                      0x2u
-#define AIPS_PACRG_WP7_SHIFT                     1
-#define AIPS_PACRG_SP7_MASK                      0x4u
-#define AIPS_PACRG_SP7_SHIFT                     2
-#define AIPS_PACRG_TP6_MASK                      0x10u
-#define AIPS_PACRG_TP6_SHIFT                     4
-#define AIPS_PACRG_WP6_MASK                      0x20u
-#define AIPS_PACRG_WP6_SHIFT                     5
-#define AIPS_PACRG_SP6_MASK                      0x40u
-#define AIPS_PACRG_SP6_SHIFT                     6
-#define AIPS_PACRG_TP5_MASK                      0x100u
-#define AIPS_PACRG_TP5_SHIFT                     8
-#define AIPS_PACRG_WP5_MASK                      0x200u
-#define AIPS_PACRG_WP5_SHIFT                     9
-#define AIPS_PACRG_SP5_MASK                      0x400u
-#define AIPS_PACRG_SP5_SHIFT                     10
-#define AIPS_PACRG_TP4_MASK                      0x1000u
-#define AIPS_PACRG_TP4_SHIFT                     12
-#define AIPS_PACRG_WP4_MASK                      0x2000u
-#define AIPS_PACRG_WP4_SHIFT                     13
-#define AIPS_PACRG_SP4_MASK                      0x4000u
-#define AIPS_PACRG_SP4_SHIFT                     14
-#define AIPS_PACRG_TP3_MASK                      0x10000u
-#define AIPS_PACRG_TP3_SHIFT                     16
-#define AIPS_PACRG_WP3_MASK                      0x20000u
-#define AIPS_PACRG_WP3_SHIFT                     17
-#define AIPS_PACRG_SP3_MASK                      0x40000u
-#define AIPS_PACRG_SP3_SHIFT                     18
-#define AIPS_PACRG_TP2_MASK                      0x100000u
-#define AIPS_PACRG_TP2_SHIFT                     20
-#define AIPS_PACRG_WP2_MASK                      0x200000u
-#define AIPS_PACRG_WP2_SHIFT                     21
-#define AIPS_PACRG_SP2_MASK                      0x400000u
-#define AIPS_PACRG_SP2_SHIFT                     22
-#define AIPS_PACRG_TP1_MASK                      0x1000000u
-#define AIPS_PACRG_TP1_SHIFT                     24
-#define AIPS_PACRG_WP1_MASK                      0x2000000u
-#define AIPS_PACRG_WP1_SHIFT                     25
-#define AIPS_PACRG_SP1_MASK                      0x4000000u
-#define AIPS_PACRG_SP1_SHIFT                     26
-#define AIPS_PACRG_TP0_MASK                      0x10000000u
-#define AIPS_PACRG_TP0_SHIFT                     28
-#define AIPS_PACRG_WP0_MASK                      0x20000000u
-#define AIPS_PACRG_WP0_SHIFT                     29
-#define AIPS_PACRG_SP0_MASK                      0x40000000u
-#define AIPS_PACRG_SP0_SHIFT                     30
-/* PACRH Bit Fields */
-#define AIPS_PACRH_TP7_MASK                      0x1u
-#define AIPS_PACRH_TP7_SHIFT                     0
-#define AIPS_PACRH_WP7_MASK                      0x2u
-#define AIPS_PACRH_WP7_SHIFT                     1
-#define AIPS_PACRH_SP7_MASK                      0x4u
-#define AIPS_PACRH_SP7_SHIFT                     2
-#define AIPS_PACRH_TP6_MASK                      0x10u
-#define AIPS_PACRH_TP6_SHIFT                     4
-#define AIPS_PACRH_WP6_MASK                      0x20u
-#define AIPS_PACRH_WP6_SHIFT                     5
-#define AIPS_PACRH_SP6_MASK                      0x40u
-#define AIPS_PACRH_SP6_SHIFT                     6
-#define AIPS_PACRH_TP5_MASK                      0x100u
-#define AIPS_PACRH_TP5_SHIFT                     8
-#define AIPS_PACRH_WP5_MASK                      0x200u
-#define AIPS_PACRH_WP5_SHIFT                     9
-#define AIPS_PACRH_SP5_MASK                      0x400u
-#define AIPS_PACRH_SP5_SHIFT                     10
-#define AIPS_PACRH_TP4_MASK                      0x1000u
-#define AIPS_PACRH_TP4_SHIFT                     12
-#define AIPS_PACRH_WP4_MASK                      0x2000u
-#define AIPS_PACRH_WP4_SHIFT                     13
-#define AIPS_PACRH_SP4_MASK                      0x4000u
-#define AIPS_PACRH_SP4_SHIFT                     14
-#define AIPS_PACRH_TP3_MASK                      0x10000u
-#define AIPS_PACRH_TP3_SHIFT                     16
-#define AIPS_PACRH_WP3_MASK                      0x20000u
-#define AIPS_PACRH_WP3_SHIFT                     17
-#define AIPS_PACRH_SP3_MASK                      0x40000u
-#define AIPS_PACRH_SP3_SHIFT                     18
-#define AIPS_PACRH_TP2_MASK                      0x100000u
-#define AIPS_PACRH_TP2_SHIFT                     20
-#define AIPS_PACRH_WP2_MASK                      0x200000u
-#define AIPS_PACRH_WP2_SHIFT                     21
-#define AIPS_PACRH_SP2_MASK                      0x400000u
-#define AIPS_PACRH_SP2_SHIFT                     22
-#define AIPS_PACRH_TP1_MASK                      0x1000000u
-#define AIPS_PACRH_TP1_SHIFT                     24
-#define AIPS_PACRH_WP1_MASK                      0x2000000u
-#define AIPS_PACRH_WP1_SHIFT                     25
-#define AIPS_PACRH_SP1_MASK                      0x4000000u
-#define AIPS_PACRH_SP1_SHIFT                     26
-#define AIPS_PACRH_TP0_MASK                      0x10000000u
-#define AIPS_PACRH_TP0_SHIFT                     28
-#define AIPS_PACRH_WP0_MASK                      0x20000000u
-#define AIPS_PACRH_WP0_SHIFT                     29
-#define AIPS_PACRH_SP0_MASK                      0x40000000u
-#define AIPS_PACRH_SP0_SHIFT                     30
-/* PACRI Bit Fields */
-#define AIPS_PACRI_TP7_MASK                      0x1u
-#define AIPS_PACRI_TP7_SHIFT                     0
-#define AIPS_PACRI_WP7_MASK                      0x2u
-#define AIPS_PACRI_WP7_SHIFT                     1
-#define AIPS_PACRI_SP7_MASK                      0x4u
-#define AIPS_PACRI_SP7_SHIFT                     2
-#define AIPS_PACRI_TP6_MASK                      0x10u
-#define AIPS_PACRI_TP6_SHIFT                     4
-#define AIPS_PACRI_WP6_MASK                      0x20u
-#define AIPS_PACRI_WP6_SHIFT                     5
-#define AIPS_PACRI_SP6_MASK                      0x40u
-#define AIPS_PACRI_SP6_SHIFT                     6
-#define AIPS_PACRI_TP5_MASK                      0x100u
-#define AIPS_PACRI_TP5_SHIFT                     8
-#define AIPS_PACRI_WP5_MASK                      0x200u
-#define AIPS_PACRI_WP5_SHIFT                     9
-#define AIPS_PACRI_SP5_MASK                      0x400u
-#define AIPS_PACRI_SP5_SHIFT                     10
-#define AIPS_PACRI_TP4_MASK                      0x1000u
-#define AIPS_PACRI_TP4_SHIFT                     12
-#define AIPS_PACRI_WP4_MASK                      0x2000u
-#define AIPS_PACRI_WP4_SHIFT                     13
-#define AIPS_PACRI_SP4_MASK                      0x4000u
-#define AIPS_PACRI_SP4_SHIFT                     14
-#define AIPS_PACRI_TP3_MASK                      0x10000u
-#define AIPS_PACRI_TP3_SHIFT                     16
-#define AIPS_PACRI_WP3_MASK                      0x20000u
-#define AIPS_PACRI_WP3_SHIFT                     17
-#define AIPS_PACRI_SP3_MASK                      0x40000u
-#define AIPS_PACRI_SP3_SHIFT                     18
-#define AIPS_PACRI_TP2_MASK                      0x100000u
-#define AIPS_PACRI_TP2_SHIFT                     20
-#define AIPS_PACRI_WP2_MASK                      0x200000u
-#define AIPS_PACRI_WP2_SHIFT                     21
-#define AIPS_PACRI_SP2_MASK                      0x400000u
-#define AIPS_PACRI_SP2_SHIFT                     22
-#define AIPS_PACRI_TP1_MASK                      0x1000000u
-#define AIPS_PACRI_TP1_SHIFT                     24
-#define AIPS_PACRI_WP1_MASK                      0x2000000u
-#define AIPS_PACRI_WP1_SHIFT                     25
-#define AIPS_PACRI_SP1_MASK                      0x4000000u
-#define AIPS_PACRI_SP1_SHIFT                     26
-#define AIPS_PACRI_TP0_MASK                      0x10000000u
-#define AIPS_PACRI_TP0_SHIFT                     28
-#define AIPS_PACRI_WP0_MASK                      0x20000000u
-#define AIPS_PACRI_WP0_SHIFT                     29
-#define AIPS_PACRI_SP0_MASK                      0x40000000u
-#define AIPS_PACRI_SP0_SHIFT                     30
-/* PACRJ Bit Fields */
-#define AIPS_PACRJ_TP7_MASK                      0x1u
-#define AIPS_PACRJ_TP7_SHIFT                     0
-#define AIPS_PACRJ_WP7_MASK                      0x2u
-#define AIPS_PACRJ_WP7_SHIFT                     1
-#define AIPS_PACRJ_SP7_MASK                      0x4u
-#define AIPS_PACRJ_SP7_SHIFT                     2
-#define AIPS_PACRJ_TP6_MASK                      0x10u
-#define AIPS_PACRJ_TP6_SHIFT                     4
-#define AIPS_PACRJ_WP6_MASK                      0x20u
-#define AIPS_PACRJ_WP6_SHIFT                     5
-#define AIPS_PACRJ_SP6_MASK                      0x40u
-#define AIPS_PACRJ_SP6_SHIFT                     6
-#define AIPS_PACRJ_TP5_MASK                      0x100u
-#define AIPS_PACRJ_TP5_SHIFT                     8
-#define AIPS_PACRJ_WP5_MASK                      0x200u
-#define AIPS_PACRJ_WP5_SHIFT                     9
-#define AIPS_PACRJ_SP5_MASK                      0x400u
-#define AIPS_PACRJ_SP5_SHIFT                     10
-#define AIPS_PACRJ_TP4_MASK                      0x1000u
-#define AIPS_PACRJ_TP4_SHIFT                     12
-#define AIPS_PACRJ_WP4_MASK                      0x2000u
-#define AIPS_PACRJ_WP4_SHIFT                     13
-#define AIPS_PACRJ_SP4_MASK                      0x4000u
-#define AIPS_PACRJ_SP4_SHIFT                     14
-#define AIPS_PACRJ_TP3_MASK                      0x10000u
-#define AIPS_PACRJ_TP3_SHIFT                     16
-#define AIPS_PACRJ_WP3_MASK                      0x20000u
-#define AIPS_PACRJ_WP3_SHIFT                     17
-#define AIPS_PACRJ_SP3_MASK                      0x40000u
-#define AIPS_PACRJ_SP3_SHIFT                     18
-#define AIPS_PACRJ_TP2_MASK                      0x100000u
-#define AIPS_PACRJ_TP2_SHIFT                     20
-#define AIPS_PACRJ_WP2_MASK                      0x200000u
-#define AIPS_PACRJ_WP2_SHIFT                     21
-#define AIPS_PACRJ_SP2_MASK                      0x400000u
-#define AIPS_PACRJ_SP2_SHIFT                     22
-#define AIPS_PACRJ_TP1_MASK                      0x1000000u
-#define AIPS_PACRJ_TP1_SHIFT                     24
-#define AIPS_PACRJ_WP1_MASK                      0x2000000u
-#define AIPS_PACRJ_WP1_SHIFT                     25
-#define AIPS_PACRJ_SP1_MASK                      0x4000000u
-#define AIPS_PACRJ_SP1_SHIFT                     26
-#define AIPS_PACRJ_TP0_MASK                      0x10000000u
-#define AIPS_PACRJ_TP0_SHIFT                     28
-#define AIPS_PACRJ_WP0_MASK                      0x20000000u
-#define AIPS_PACRJ_WP0_SHIFT                     29
-#define AIPS_PACRJ_SP0_MASK                      0x40000000u
-#define AIPS_PACRJ_SP0_SHIFT                     30
-/* PACRK Bit Fields */
-#define AIPS_PACRK_TP7_MASK                      0x1u
-#define AIPS_PACRK_TP7_SHIFT                     0
-#define AIPS_PACRK_WP7_MASK                      0x2u
-#define AIPS_PACRK_WP7_SHIFT                     1
-#define AIPS_PACRK_SP7_MASK                      0x4u
-#define AIPS_PACRK_SP7_SHIFT                     2
-#define AIPS_PACRK_TP6_MASK                      0x10u
-#define AIPS_PACRK_TP6_SHIFT                     4
-#define AIPS_PACRK_WP6_MASK                      0x20u
-#define AIPS_PACRK_WP6_SHIFT                     5
-#define AIPS_PACRK_SP6_MASK                      0x40u
-#define AIPS_PACRK_SP6_SHIFT                     6
-#define AIPS_PACRK_TP5_MASK                      0x100u
-#define AIPS_PACRK_TP5_SHIFT                     8
-#define AIPS_PACRK_WP5_MASK                      0x200u
-#define AIPS_PACRK_WP5_SHIFT                     9
-#define AIPS_PACRK_SP5_MASK                      0x400u
-#define AIPS_PACRK_SP5_SHIFT                     10
-#define AIPS_PACRK_TP4_MASK                      0x1000u
-#define AIPS_PACRK_TP4_SHIFT                     12
-#define AIPS_PACRK_WP4_MASK                      0x2000u
-#define AIPS_PACRK_WP4_SHIFT                     13
-#define AIPS_PACRK_SP4_MASK                      0x4000u
-#define AIPS_PACRK_SP4_SHIFT                     14
-#define AIPS_PACRK_TP3_MASK                      0x10000u
-#define AIPS_PACRK_TP3_SHIFT                     16
-#define AIPS_PACRK_WP3_MASK                      0x20000u
-#define AIPS_PACRK_WP3_SHIFT                     17
-#define AIPS_PACRK_SP3_MASK                      0x40000u
-#define AIPS_PACRK_SP3_SHIFT                     18
-#define AIPS_PACRK_TP2_MASK                      0x100000u
-#define AIPS_PACRK_TP2_SHIFT                     20
-#define AIPS_PACRK_WP2_MASK                      0x200000u
-#define AIPS_PACRK_WP2_SHIFT                     21
-#define AIPS_PACRK_SP2_MASK                      0x400000u
-#define AIPS_PACRK_SP2_SHIFT                     22
-#define AIPS_PACRK_TP1_MASK                      0x1000000u
-#define AIPS_PACRK_TP1_SHIFT                     24
-#define AIPS_PACRK_WP1_MASK                      0x2000000u
-#define AIPS_PACRK_WP1_SHIFT                     25
-#define AIPS_PACRK_SP1_MASK                      0x4000000u
-#define AIPS_PACRK_SP1_SHIFT                     26
-#define AIPS_PACRK_TP0_MASK                      0x10000000u
-#define AIPS_PACRK_TP0_SHIFT                     28
-#define AIPS_PACRK_WP0_MASK                      0x20000000u
-#define AIPS_PACRK_WP0_SHIFT                     29
-#define AIPS_PACRK_SP0_MASK                      0x40000000u
-#define AIPS_PACRK_SP0_SHIFT                     30
-/* PACRL Bit Fields */
-#define AIPS_PACRL_TP7_MASK                      0x1u
-#define AIPS_PACRL_TP7_SHIFT                     0
-#define AIPS_PACRL_WP7_MASK                      0x2u
-#define AIPS_PACRL_WP7_SHIFT                     1
-#define AIPS_PACRL_SP7_MASK                      0x4u
-#define AIPS_PACRL_SP7_SHIFT                     2
-#define AIPS_PACRL_TP6_MASK                      0x10u
-#define AIPS_PACRL_TP6_SHIFT                     4
-#define AIPS_PACRL_WP6_MASK                      0x20u
-#define AIPS_PACRL_WP6_SHIFT                     5
-#define AIPS_PACRL_SP6_MASK                      0x40u
-#define AIPS_PACRL_SP6_SHIFT                     6
-#define AIPS_PACRL_TP5_MASK                      0x100u
-#define AIPS_PACRL_TP5_SHIFT                     8
-#define AIPS_PACRL_WP5_MASK                      0x200u
-#define AIPS_PACRL_WP5_SHIFT                     9
-#define AIPS_PACRL_SP5_MASK                      0x400u
-#define AIPS_PACRL_SP5_SHIFT                     10
-#define AIPS_PACRL_TP4_MASK                      0x1000u
-#define AIPS_PACRL_TP4_SHIFT                     12
-#define AIPS_PACRL_WP4_MASK                      0x2000u
-#define AIPS_PACRL_WP4_SHIFT                     13
-#define AIPS_PACRL_SP4_MASK                      0x4000u
-#define AIPS_PACRL_SP4_SHIFT                     14
-#define AIPS_PACRL_TP3_MASK                      0x10000u
-#define AIPS_PACRL_TP3_SHIFT                     16
-#define AIPS_PACRL_WP3_MASK                      0x20000u
-#define AIPS_PACRL_WP3_SHIFT                     17
-#define AIPS_PACRL_SP3_MASK                      0x40000u
-#define AIPS_PACRL_SP3_SHIFT                     18
-#define AIPS_PACRL_TP2_MASK                      0x100000u
-#define AIPS_PACRL_TP2_SHIFT                     20
-#define AIPS_PACRL_WP2_MASK                      0x200000u
-#define AIPS_PACRL_WP2_SHIFT                     21
-#define AIPS_PACRL_SP2_MASK                      0x400000u
-#define AIPS_PACRL_SP2_SHIFT                     22
-#define AIPS_PACRL_TP1_MASK                      0x1000000u
-#define AIPS_PACRL_TP1_SHIFT                     24
-#define AIPS_PACRL_WP1_MASK                      0x2000000u
-#define AIPS_PACRL_WP1_SHIFT                     25
-#define AIPS_PACRL_SP1_MASK                      0x4000000u
-#define AIPS_PACRL_SP1_SHIFT                     26
-#define AIPS_PACRL_TP0_MASK                      0x10000000u
-#define AIPS_PACRL_TP0_SHIFT                     28
-#define AIPS_PACRL_WP0_MASK                      0x20000000u
-#define AIPS_PACRL_WP0_SHIFT                     29
-#define AIPS_PACRL_SP0_MASK                      0x40000000u
-#define AIPS_PACRL_SP0_SHIFT                     30
-/* PACRM Bit Fields */
-#define AIPS_PACRM_TP7_MASK                      0x1u
-#define AIPS_PACRM_TP7_SHIFT                     0
-#define AIPS_PACRM_WP7_MASK                      0x2u
-#define AIPS_PACRM_WP7_SHIFT                     1
-#define AIPS_PACRM_SP7_MASK                      0x4u
-#define AIPS_PACRM_SP7_SHIFT                     2
-#define AIPS_PACRM_TP6_MASK                      0x10u
-#define AIPS_PACRM_TP6_SHIFT                     4
-#define AIPS_PACRM_WP6_MASK                      0x20u
-#define AIPS_PACRM_WP6_SHIFT                     5
-#define AIPS_PACRM_SP6_MASK                      0x40u
-#define AIPS_PACRM_SP6_SHIFT                     6
-#define AIPS_PACRM_TP5_MASK                      0x100u
-#define AIPS_PACRM_TP5_SHIFT                     8
-#define AIPS_PACRM_WP5_MASK                      0x200u
-#define AIPS_PACRM_WP5_SHIFT                     9
-#define AIPS_PACRM_SP5_MASK                      0x400u
-#define AIPS_PACRM_SP5_SHIFT                     10
-#define AIPS_PACRM_TP4_MASK                      0x1000u
-#define AIPS_PACRM_TP4_SHIFT                     12
-#define AIPS_PACRM_WP4_MASK                      0x2000u
-#define AIPS_PACRM_WP4_SHIFT                     13
-#define AIPS_PACRM_SP4_MASK                      0x4000u
-#define AIPS_PACRM_SP4_SHIFT                     14
-#define AIPS_PACRM_TP3_MASK                      0x10000u
-#define AIPS_PACRM_TP3_SHIFT                     16
-#define AIPS_PACRM_WP3_MASK                      0x20000u
-#define AIPS_PACRM_WP3_SHIFT                     17
-#define AIPS_PACRM_SP3_MASK                      0x40000u
-#define AIPS_PACRM_SP3_SHIFT                     18
-#define AIPS_PACRM_TP2_MASK                      0x100000u
-#define AIPS_PACRM_TP2_SHIFT                     20
-#define AIPS_PACRM_WP2_MASK                      0x200000u
-#define AIPS_PACRM_WP2_SHIFT                     21
-#define AIPS_PACRM_SP2_MASK                      0x400000u
-#define AIPS_PACRM_SP2_SHIFT                     22
-#define AIPS_PACRM_TP1_MASK                      0x1000000u
-#define AIPS_PACRM_TP1_SHIFT                     24
-#define AIPS_PACRM_WP1_MASK                      0x2000000u
-#define AIPS_PACRM_WP1_SHIFT                     25
-#define AIPS_PACRM_SP1_MASK                      0x4000000u
-#define AIPS_PACRM_SP1_SHIFT                     26
-#define AIPS_PACRM_TP0_MASK                      0x10000000u
-#define AIPS_PACRM_TP0_SHIFT                     28
-#define AIPS_PACRM_WP0_MASK                      0x20000000u
-#define AIPS_PACRM_WP0_SHIFT                     29
-#define AIPS_PACRM_SP0_MASK                      0x40000000u
-#define AIPS_PACRM_SP0_SHIFT                     30
-/* PACRN Bit Fields */
-#define AIPS_PACRN_TP7_MASK                      0x1u
-#define AIPS_PACRN_TP7_SHIFT                     0
-#define AIPS_PACRN_WP7_MASK                      0x2u
-#define AIPS_PACRN_WP7_SHIFT                     1
-#define AIPS_PACRN_SP7_MASK                      0x4u
-#define AIPS_PACRN_SP7_SHIFT                     2
-#define AIPS_PACRN_TP6_MASK                      0x10u
-#define AIPS_PACRN_TP6_SHIFT                     4
-#define AIPS_PACRN_WP6_MASK                      0x20u
-#define AIPS_PACRN_WP6_SHIFT                     5
-#define AIPS_PACRN_SP6_MASK                      0x40u
-#define AIPS_PACRN_SP6_SHIFT                     6
-#define AIPS_PACRN_TP5_MASK                      0x100u
-#define AIPS_PACRN_TP5_SHIFT                     8
-#define AIPS_PACRN_WP5_MASK                      0x200u
-#define AIPS_PACRN_WP5_SHIFT                     9
-#define AIPS_PACRN_SP5_MASK                      0x400u
-#define AIPS_PACRN_SP5_SHIFT                     10
-#define AIPS_PACRN_TP4_MASK                      0x1000u
-#define AIPS_PACRN_TP4_SHIFT                     12
-#define AIPS_PACRN_WP4_MASK                      0x2000u
-#define AIPS_PACRN_WP4_SHIFT                     13
-#define AIPS_PACRN_SP4_MASK                      0x4000u
-#define AIPS_PACRN_SP4_SHIFT                     14
-#define AIPS_PACRN_TP3_MASK                      0x10000u
-#define AIPS_PACRN_TP3_SHIFT                     16
-#define AIPS_PACRN_WP3_MASK                      0x20000u
-#define AIPS_PACRN_WP3_SHIFT                     17
-#define AIPS_PACRN_SP3_MASK                      0x40000u
-#define AIPS_PACRN_SP3_SHIFT                     18
-#define AIPS_PACRN_TP2_MASK                      0x100000u
-#define AIPS_PACRN_TP2_SHIFT                     20
-#define AIPS_PACRN_WP2_MASK                      0x200000u
-#define AIPS_PACRN_WP2_SHIFT                     21
-#define AIPS_PACRN_SP2_MASK                      0x400000u
-#define AIPS_PACRN_SP2_SHIFT                     22
-#define AIPS_PACRN_TP1_MASK                      0x1000000u
-#define AIPS_PACRN_TP1_SHIFT                     24
-#define AIPS_PACRN_WP1_MASK                      0x2000000u
-#define AIPS_PACRN_WP1_SHIFT                     25
-#define AIPS_PACRN_SP1_MASK                      0x4000000u
-#define AIPS_PACRN_SP1_SHIFT                     26
-#define AIPS_PACRN_TP0_MASK                      0x10000000u
-#define AIPS_PACRN_TP0_SHIFT                     28
-#define AIPS_PACRN_WP0_MASK                      0x20000000u
-#define AIPS_PACRN_WP0_SHIFT                     29
-#define AIPS_PACRN_SP0_MASK                      0x40000000u
-#define AIPS_PACRN_SP0_SHIFT                     30
-/* PACRO Bit Fields */
-#define AIPS_PACRO_TP7_MASK                      0x1u
-#define AIPS_PACRO_TP7_SHIFT                     0
-#define AIPS_PACRO_WP7_MASK                      0x2u
-#define AIPS_PACRO_WP7_SHIFT                     1
-#define AIPS_PACRO_SP7_MASK                      0x4u
-#define AIPS_PACRO_SP7_SHIFT                     2
-#define AIPS_PACRO_TP6_MASK                      0x10u
-#define AIPS_PACRO_TP6_SHIFT                     4
-#define AIPS_PACRO_WP6_MASK                      0x20u
-#define AIPS_PACRO_WP6_SHIFT                     5
-#define AIPS_PACRO_SP6_MASK                      0x40u
-#define AIPS_PACRO_SP6_SHIFT                     6
-#define AIPS_PACRO_TP5_MASK                      0x100u
-#define AIPS_PACRO_TP5_SHIFT                     8
-#define AIPS_PACRO_WP5_MASK                      0x200u
-#define AIPS_PACRO_WP5_SHIFT                     9
-#define AIPS_PACRO_SP5_MASK                      0x400u
-#define AIPS_PACRO_SP5_SHIFT                     10
-#define AIPS_PACRO_TP4_MASK                      0x1000u
-#define AIPS_PACRO_TP4_SHIFT                     12
-#define AIPS_PACRO_WP4_MASK                      0x2000u
-#define AIPS_PACRO_WP4_SHIFT                     13
-#define AIPS_PACRO_SP4_MASK                      0x4000u
-#define AIPS_PACRO_SP4_SHIFT                     14
-#define AIPS_PACRO_TP3_MASK                      0x10000u
-#define AIPS_PACRO_TP3_SHIFT                     16
-#define AIPS_PACRO_WP3_MASK                      0x20000u
-#define AIPS_PACRO_WP3_SHIFT                     17
-#define AIPS_PACRO_SP3_MASK                      0x40000u
-#define AIPS_PACRO_SP3_SHIFT                     18
-#define AIPS_PACRO_TP2_MASK                      0x100000u
-#define AIPS_PACRO_TP2_SHIFT                     20
-#define AIPS_PACRO_WP2_MASK                      0x200000u
-#define AIPS_PACRO_WP2_SHIFT                     21
-#define AIPS_PACRO_SP2_MASK                      0x400000u
-#define AIPS_PACRO_SP2_SHIFT                     22
-#define AIPS_PACRO_TP1_MASK                      0x1000000u
-#define AIPS_PACRO_TP1_SHIFT                     24
-#define AIPS_PACRO_WP1_MASK                      0x2000000u
-#define AIPS_PACRO_WP1_SHIFT                     25
-#define AIPS_PACRO_SP1_MASK                      0x4000000u
-#define AIPS_PACRO_SP1_SHIFT                     26
-#define AIPS_PACRO_TP0_MASK                      0x10000000u
-#define AIPS_PACRO_TP0_SHIFT                     28
-#define AIPS_PACRO_WP0_MASK                      0x20000000u
-#define AIPS_PACRO_WP0_SHIFT                     29
-#define AIPS_PACRO_SP0_MASK                      0x40000000u
-#define AIPS_PACRO_SP0_SHIFT                     30
-/* PACRP Bit Fields */
-#define AIPS_PACRP_TP7_MASK                      0x1u
-#define AIPS_PACRP_TP7_SHIFT                     0
-#define AIPS_PACRP_WP7_MASK                      0x2u
-#define AIPS_PACRP_WP7_SHIFT                     1
-#define AIPS_PACRP_SP7_MASK                      0x4u
-#define AIPS_PACRP_SP7_SHIFT                     2
-#define AIPS_PACRP_TP6_MASK                      0x10u
-#define AIPS_PACRP_TP6_SHIFT                     4
-#define AIPS_PACRP_WP6_MASK                      0x20u
-#define AIPS_PACRP_WP6_SHIFT                     5
-#define AIPS_PACRP_SP6_MASK                      0x40u
-#define AIPS_PACRP_SP6_SHIFT                     6
-#define AIPS_PACRP_TP5_MASK                      0x100u
-#define AIPS_PACRP_TP5_SHIFT                     8
-#define AIPS_PACRP_WP5_MASK                      0x200u
-#define AIPS_PACRP_WP5_SHIFT                     9
-#define AIPS_PACRP_SP5_MASK                      0x400u
-#define AIPS_PACRP_SP5_SHIFT                     10
-#define AIPS_PACRP_TP4_MASK                      0x1000u
-#define AIPS_PACRP_TP4_SHIFT                     12
-#define AIPS_PACRP_WP4_MASK                      0x2000u
-#define AIPS_PACRP_WP4_SHIFT                     13
-#define AIPS_PACRP_SP4_MASK                      0x4000u
-#define AIPS_PACRP_SP4_SHIFT                     14
-#define AIPS_PACRP_TP3_MASK                      0x10000u
-#define AIPS_PACRP_TP3_SHIFT                     16
-#define AIPS_PACRP_WP3_MASK                      0x20000u
-#define AIPS_PACRP_WP3_SHIFT                     17
-#define AIPS_PACRP_SP3_MASK                      0x40000u
-#define AIPS_PACRP_SP3_SHIFT                     18
-#define AIPS_PACRP_TP2_MASK                      0x100000u
-#define AIPS_PACRP_TP2_SHIFT                     20
-#define AIPS_PACRP_WP2_MASK                      0x200000u
-#define AIPS_PACRP_WP2_SHIFT                     21
-#define AIPS_PACRP_SP2_MASK                      0x400000u
-#define AIPS_PACRP_SP2_SHIFT                     22
-#define AIPS_PACRP_TP1_MASK                      0x1000000u
-#define AIPS_PACRP_TP1_SHIFT                     24
-#define AIPS_PACRP_WP1_MASK                      0x2000000u
-#define AIPS_PACRP_WP1_SHIFT                     25
-#define AIPS_PACRP_SP1_MASK                      0x4000000u
-#define AIPS_PACRP_SP1_SHIFT                     26
-#define AIPS_PACRP_TP0_MASK                      0x10000000u
-#define AIPS_PACRP_TP0_SHIFT                     28
-#define AIPS_PACRP_WP0_MASK                      0x20000000u
-#define AIPS_PACRP_WP0_SHIFT                     29
-#define AIPS_PACRP_SP0_MASK                      0x40000000u
-#define AIPS_PACRP_SP0_SHIFT                     30
+/*! @name MPRA - Master Privilege Register A */
+#define AIPS_MPRA_MPL5_MASK                      (0x100U)
+#define AIPS_MPRA_MPL5_SHIFT                     (8U)
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      (0x200U)
+#define AIPS_MPRA_MTW5_SHIFT                     (9U)
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      (0x400U)
+#define AIPS_MPRA_MTR5_SHIFT                     (10U)
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      (0x1000U)
+#define AIPS_MPRA_MPL4_SHIFT                     (12U)
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      (0x2000U)
+#define AIPS_MPRA_MTW4_SHIFT                     (13U)
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      (0x4000U)
+#define AIPS_MPRA_MTR4_SHIFT                     (14U)
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      (0x10000U)
+#define AIPS_MPRA_MPL3_SHIFT                     (16U)
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      (0x20000U)
+#define AIPS_MPRA_MTW3_SHIFT                     (17U)
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      (0x40000U)
+#define AIPS_MPRA_MTR3_SHIFT                     (18U)
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      (0x100000U)
+#define AIPS_MPRA_MPL2_SHIFT                     (20U)
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      (0x200000U)
+#define AIPS_MPRA_MTW2_SHIFT                     (21U)
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      (0x400000U)
+#define AIPS_MPRA_MTR2_SHIFT                     (22U)
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      (0x1000000U)
+#define AIPS_MPRA_MPL1_SHIFT                     (24U)
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      (0x2000000U)
+#define AIPS_MPRA_MTW1_SHIFT                     (25U)
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      (0x4000000U)
+#define AIPS_MPRA_MTR1_SHIFT                     (26U)
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      (0x10000000U)
+#define AIPS_MPRA_MPL0_SHIFT                     (28U)
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      (0x20000000U)
+#define AIPS_MPRA_MTW0_SHIFT                     (29U)
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      (0x40000000U)
+#define AIPS_MPRA_MTR0_SHIFT                     (30U)
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
+
+/*! @name PACRA - Peripheral Access Control Register */
+#define AIPS_PACRA_TP7_MASK                      (0x1U)
+#define AIPS_PACRA_TP7_SHIFT                     (0U)
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      (0x2U)
+#define AIPS_PACRA_WP7_SHIFT                     (1U)
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      (0x4U)
+#define AIPS_PACRA_SP7_SHIFT                     (2U)
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      (0x10U)
+#define AIPS_PACRA_TP6_SHIFT                     (4U)
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      (0x20U)
+#define AIPS_PACRA_WP6_SHIFT                     (5U)
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      (0x40U)
+#define AIPS_PACRA_SP6_SHIFT                     (6U)
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      (0x100U)
+#define AIPS_PACRA_TP5_SHIFT                     (8U)
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      (0x200U)
+#define AIPS_PACRA_WP5_SHIFT                     (9U)
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      (0x400U)
+#define AIPS_PACRA_SP5_SHIFT                     (10U)
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      (0x1000U)
+#define AIPS_PACRA_TP4_SHIFT                     (12U)
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      (0x2000U)
+#define AIPS_PACRA_WP4_SHIFT                     (13U)
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      (0x4000U)
+#define AIPS_PACRA_SP4_SHIFT                     (14U)
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      (0x10000U)
+#define AIPS_PACRA_TP3_SHIFT                     (16U)
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      (0x20000U)
+#define AIPS_PACRA_WP3_SHIFT                     (17U)
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      (0x40000U)
+#define AIPS_PACRA_SP3_SHIFT                     (18U)
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      (0x100000U)
+#define AIPS_PACRA_TP2_SHIFT                     (20U)
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      (0x200000U)
+#define AIPS_PACRA_WP2_SHIFT                     (21U)
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      (0x400000U)
+#define AIPS_PACRA_SP2_SHIFT                     (22U)
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRA_TP1_SHIFT                     (24U)
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRA_WP1_SHIFT                     (25U)
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRA_SP1_SHIFT                     (26U)
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRA_TP0_SHIFT                     (28U)
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRA_WP0_SHIFT                     (29U)
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRA_SP0_SHIFT                     (30U)
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+
+/*! @name PACRB - Peripheral Access Control Register */
+#define AIPS_PACRB_TP7_MASK                      (0x1U)
+#define AIPS_PACRB_TP7_SHIFT                     (0U)
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      (0x2U)
+#define AIPS_PACRB_WP7_SHIFT                     (1U)
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      (0x4U)
+#define AIPS_PACRB_SP7_SHIFT                     (2U)
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      (0x10U)
+#define AIPS_PACRB_TP6_SHIFT                     (4U)
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      (0x20U)
+#define AIPS_PACRB_WP6_SHIFT                     (5U)
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      (0x40U)
+#define AIPS_PACRB_SP6_SHIFT                     (6U)
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      (0x100U)
+#define AIPS_PACRB_TP5_SHIFT                     (8U)
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      (0x200U)
+#define AIPS_PACRB_WP5_SHIFT                     (9U)
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      (0x400U)
+#define AIPS_PACRB_SP5_SHIFT                     (10U)
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      (0x1000U)
+#define AIPS_PACRB_TP4_SHIFT                     (12U)
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      (0x2000U)
+#define AIPS_PACRB_WP4_SHIFT                     (13U)
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      (0x4000U)
+#define AIPS_PACRB_SP4_SHIFT                     (14U)
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      (0x10000U)
+#define AIPS_PACRB_TP3_SHIFT                     (16U)
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      (0x20000U)
+#define AIPS_PACRB_WP3_SHIFT                     (17U)
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      (0x40000U)
+#define AIPS_PACRB_SP3_SHIFT                     (18U)
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      (0x100000U)
+#define AIPS_PACRB_TP2_SHIFT                     (20U)
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      (0x200000U)
+#define AIPS_PACRB_WP2_SHIFT                     (21U)
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      (0x400000U)
+#define AIPS_PACRB_SP2_SHIFT                     (22U)
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRB_TP1_SHIFT                     (24U)
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRB_WP1_SHIFT                     (25U)
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRB_SP1_SHIFT                     (26U)
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRB_TP0_SHIFT                     (28U)
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRB_WP0_SHIFT                     (29U)
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRB_SP0_SHIFT                     (30U)
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
+
+/*! @name PACRC - Peripheral Access Control Register */
+#define AIPS_PACRC_TP7_MASK                      (0x1U)
+#define AIPS_PACRC_TP7_SHIFT                     (0U)
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      (0x2U)
+#define AIPS_PACRC_WP7_SHIFT                     (1U)
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      (0x4U)
+#define AIPS_PACRC_SP7_SHIFT                     (2U)
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      (0x10U)
+#define AIPS_PACRC_TP6_SHIFT                     (4U)
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      (0x20U)
+#define AIPS_PACRC_WP6_SHIFT                     (5U)
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      (0x40U)
+#define AIPS_PACRC_SP6_SHIFT                     (6U)
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      (0x100U)
+#define AIPS_PACRC_TP5_SHIFT                     (8U)
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      (0x200U)
+#define AIPS_PACRC_WP5_SHIFT                     (9U)
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      (0x400U)
+#define AIPS_PACRC_SP5_SHIFT                     (10U)
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      (0x1000U)
+#define AIPS_PACRC_TP4_SHIFT                     (12U)
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      (0x2000U)
+#define AIPS_PACRC_WP4_SHIFT                     (13U)
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      (0x4000U)
+#define AIPS_PACRC_SP4_SHIFT                     (14U)
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      (0x10000U)
+#define AIPS_PACRC_TP3_SHIFT                     (16U)
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      (0x20000U)
+#define AIPS_PACRC_WP3_SHIFT                     (17U)
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      (0x40000U)
+#define AIPS_PACRC_SP3_SHIFT                     (18U)
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      (0x100000U)
+#define AIPS_PACRC_TP2_SHIFT                     (20U)
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      (0x200000U)
+#define AIPS_PACRC_WP2_SHIFT                     (21U)
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      (0x400000U)
+#define AIPS_PACRC_SP2_SHIFT                     (22U)
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRC_TP1_SHIFT                     (24U)
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRC_WP1_SHIFT                     (25U)
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRC_SP1_SHIFT                     (26U)
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRC_TP0_SHIFT                     (28U)
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRC_WP0_SHIFT                     (29U)
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRC_SP0_SHIFT                     (30U)
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
+
+/*! @name PACRD - Peripheral Access Control Register */
+#define AIPS_PACRD_TP7_MASK                      (0x1U)
+#define AIPS_PACRD_TP7_SHIFT                     (0U)
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      (0x2U)
+#define AIPS_PACRD_WP7_SHIFT                     (1U)
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      (0x4U)
+#define AIPS_PACRD_SP7_SHIFT                     (2U)
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      (0x10U)
+#define AIPS_PACRD_TP6_SHIFT                     (4U)
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      (0x20U)
+#define AIPS_PACRD_WP6_SHIFT                     (5U)
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      (0x40U)
+#define AIPS_PACRD_SP6_SHIFT                     (6U)
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      (0x100U)
+#define AIPS_PACRD_TP5_SHIFT                     (8U)
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      (0x200U)
+#define AIPS_PACRD_WP5_SHIFT                     (9U)
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      (0x400U)
+#define AIPS_PACRD_SP5_SHIFT                     (10U)
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      (0x1000U)
+#define AIPS_PACRD_TP4_SHIFT                     (12U)
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      (0x2000U)
+#define AIPS_PACRD_WP4_SHIFT                     (13U)
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      (0x4000U)
+#define AIPS_PACRD_SP4_SHIFT                     (14U)
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      (0x10000U)
+#define AIPS_PACRD_TP3_SHIFT                     (16U)
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      (0x20000U)
+#define AIPS_PACRD_WP3_SHIFT                     (17U)
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      (0x40000U)
+#define AIPS_PACRD_SP3_SHIFT                     (18U)
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      (0x100000U)
+#define AIPS_PACRD_TP2_SHIFT                     (20U)
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      (0x200000U)
+#define AIPS_PACRD_WP2_SHIFT                     (21U)
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      (0x400000U)
+#define AIPS_PACRD_SP2_SHIFT                     (22U)
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRD_TP1_SHIFT                     (24U)
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRD_WP1_SHIFT                     (25U)
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRD_SP1_SHIFT                     (26U)
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRD_TP0_SHIFT                     (28U)
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRD_WP0_SHIFT                     (29U)
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRD_SP0_SHIFT                     (30U)
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
+
+/*! @name PACRE - Peripheral Access Control Register */
+#define AIPS_PACRE_TP7_MASK                      (0x1U)
+#define AIPS_PACRE_TP7_SHIFT                     (0U)
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      (0x2U)
+#define AIPS_PACRE_WP7_SHIFT                     (1U)
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      (0x4U)
+#define AIPS_PACRE_SP7_SHIFT                     (2U)
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      (0x10U)
+#define AIPS_PACRE_TP6_SHIFT                     (4U)
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      (0x20U)
+#define AIPS_PACRE_WP6_SHIFT                     (5U)
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      (0x40U)
+#define AIPS_PACRE_SP6_SHIFT                     (6U)
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      (0x100U)
+#define AIPS_PACRE_TP5_SHIFT                     (8U)
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      (0x200U)
+#define AIPS_PACRE_WP5_SHIFT                     (9U)
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      (0x400U)
+#define AIPS_PACRE_SP5_SHIFT                     (10U)
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      (0x1000U)
+#define AIPS_PACRE_TP4_SHIFT                     (12U)
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      (0x2000U)
+#define AIPS_PACRE_WP4_SHIFT                     (13U)
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      (0x4000U)
+#define AIPS_PACRE_SP4_SHIFT                     (14U)
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      (0x10000U)
+#define AIPS_PACRE_TP3_SHIFT                     (16U)
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      (0x20000U)
+#define AIPS_PACRE_WP3_SHIFT                     (17U)
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      (0x40000U)
+#define AIPS_PACRE_SP3_SHIFT                     (18U)
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      (0x100000U)
+#define AIPS_PACRE_TP2_SHIFT                     (20U)
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      (0x200000U)
+#define AIPS_PACRE_WP2_SHIFT                     (21U)
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      (0x400000U)
+#define AIPS_PACRE_SP2_SHIFT                     (22U)
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRE_TP1_SHIFT                     (24U)
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRE_WP1_SHIFT                     (25U)
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRE_SP1_SHIFT                     (26U)
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRE_TP0_SHIFT                     (28U)
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRE_WP0_SHIFT                     (29U)
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRE_SP0_SHIFT                     (30U)
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
+
+/*! @name PACRF - Peripheral Access Control Register */
+#define AIPS_PACRF_TP7_MASK                      (0x1U)
+#define AIPS_PACRF_TP7_SHIFT                     (0U)
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      (0x2U)
+#define AIPS_PACRF_WP7_SHIFT                     (1U)
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      (0x4U)
+#define AIPS_PACRF_SP7_SHIFT                     (2U)
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      (0x10U)
+#define AIPS_PACRF_TP6_SHIFT                     (4U)
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      (0x20U)
+#define AIPS_PACRF_WP6_SHIFT                     (5U)
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      (0x40U)
+#define AIPS_PACRF_SP6_SHIFT                     (6U)
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      (0x100U)
+#define AIPS_PACRF_TP5_SHIFT                     (8U)
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      (0x200U)
+#define AIPS_PACRF_WP5_SHIFT                     (9U)
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      (0x400U)
+#define AIPS_PACRF_SP5_SHIFT                     (10U)
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      (0x1000U)
+#define AIPS_PACRF_TP4_SHIFT                     (12U)
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      (0x2000U)
+#define AIPS_PACRF_WP4_SHIFT                     (13U)
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      (0x4000U)
+#define AIPS_PACRF_SP4_SHIFT                     (14U)
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      (0x10000U)
+#define AIPS_PACRF_TP3_SHIFT                     (16U)
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      (0x20000U)
+#define AIPS_PACRF_WP3_SHIFT                     (17U)
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      (0x40000U)
+#define AIPS_PACRF_SP3_SHIFT                     (18U)
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      (0x100000U)
+#define AIPS_PACRF_TP2_SHIFT                     (20U)
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      (0x200000U)
+#define AIPS_PACRF_WP2_SHIFT                     (21U)
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      (0x400000U)
+#define AIPS_PACRF_SP2_SHIFT                     (22U)
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRF_TP1_SHIFT                     (24U)
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRF_WP1_SHIFT                     (25U)
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRF_SP1_SHIFT                     (26U)
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRF_TP0_SHIFT                     (28U)
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRF_WP0_SHIFT                     (29U)
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRF_SP0_SHIFT                     (30U)
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
+
+/*! @name PACRG - Peripheral Access Control Register */
+#define AIPS_PACRG_TP7_MASK                      (0x1U)
+#define AIPS_PACRG_TP7_SHIFT                     (0U)
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      (0x2U)
+#define AIPS_PACRG_WP7_SHIFT                     (1U)
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      (0x4U)
+#define AIPS_PACRG_SP7_SHIFT                     (2U)
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      (0x10U)
+#define AIPS_PACRG_TP6_SHIFT                     (4U)
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      (0x20U)
+#define AIPS_PACRG_WP6_SHIFT                     (5U)
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      (0x40U)
+#define AIPS_PACRG_SP6_SHIFT                     (6U)
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      (0x100U)
+#define AIPS_PACRG_TP5_SHIFT                     (8U)
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      (0x200U)
+#define AIPS_PACRG_WP5_SHIFT                     (9U)
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      (0x400U)
+#define AIPS_PACRG_SP5_SHIFT                     (10U)
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      (0x1000U)
+#define AIPS_PACRG_TP4_SHIFT                     (12U)
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      (0x2000U)
+#define AIPS_PACRG_WP4_SHIFT                     (13U)
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      (0x4000U)
+#define AIPS_PACRG_SP4_SHIFT                     (14U)
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      (0x10000U)
+#define AIPS_PACRG_TP3_SHIFT                     (16U)
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      (0x20000U)
+#define AIPS_PACRG_WP3_SHIFT                     (17U)
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      (0x40000U)
+#define AIPS_PACRG_SP3_SHIFT                     (18U)
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      (0x100000U)
+#define AIPS_PACRG_TP2_SHIFT                     (20U)
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      (0x200000U)
+#define AIPS_PACRG_WP2_SHIFT                     (21U)
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      (0x400000U)
+#define AIPS_PACRG_SP2_SHIFT                     (22U)
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRG_TP1_SHIFT                     (24U)
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRG_WP1_SHIFT                     (25U)
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRG_SP1_SHIFT                     (26U)
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRG_TP0_SHIFT                     (28U)
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRG_WP0_SHIFT                     (29U)
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRG_SP0_SHIFT                     (30U)
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
+
+/*! @name PACRH - Peripheral Access Control Register */
+#define AIPS_PACRH_TP7_MASK                      (0x1U)
+#define AIPS_PACRH_TP7_SHIFT                     (0U)
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      (0x2U)
+#define AIPS_PACRH_WP7_SHIFT                     (1U)
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      (0x4U)
+#define AIPS_PACRH_SP7_SHIFT                     (2U)
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      (0x10U)
+#define AIPS_PACRH_TP6_SHIFT                     (4U)
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      (0x20U)
+#define AIPS_PACRH_WP6_SHIFT                     (5U)
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      (0x40U)
+#define AIPS_PACRH_SP6_SHIFT                     (6U)
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      (0x100U)
+#define AIPS_PACRH_TP5_SHIFT                     (8U)
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      (0x200U)
+#define AIPS_PACRH_WP5_SHIFT                     (9U)
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      (0x400U)
+#define AIPS_PACRH_SP5_SHIFT                     (10U)
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      (0x1000U)
+#define AIPS_PACRH_TP4_SHIFT                     (12U)
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      (0x2000U)
+#define AIPS_PACRH_WP4_SHIFT                     (13U)
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      (0x4000U)
+#define AIPS_PACRH_SP4_SHIFT                     (14U)
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      (0x10000U)
+#define AIPS_PACRH_TP3_SHIFT                     (16U)
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      (0x20000U)
+#define AIPS_PACRH_WP3_SHIFT                     (17U)
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      (0x40000U)
+#define AIPS_PACRH_SP3_SHIFT                     (18U)
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      (0x100000U)
+#define AIPS_PACRH_TP2_SHIFT                     (20U)
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      (0x200000U)
+#define AIPS_PACRH_WP2_SHIFT                     (21U)
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      (0x400000U)
+#define AIPS_PACRH_SP2_SHIFT                     (22U)
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRH_TP1_SHIFT                     (24U)
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRH_WP1_SHIFT                     (25U)
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRH_SP1_SHIFT                     (26U)
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRH_TP0_SHIFT                     (28U)
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRH_WP0_SHIFT                     (29U)
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRH_SP0_SHIFT                     (30U)
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
+
+/*! @name PACRI - Peripheral Access Control Register */
+#define AIPS_PACRI_TP7_MASK                      (0x1U)
+#define AIPS_PACRI_TP7_SHIFT                     (0U)
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      (0x2U)
+#define AIPS_PACRI_WP7_SHIFT                     (1U)
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      (0x4U)
+#define AIPS_PACRI_SP7_SHIFT                     (2U)
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      (0x10U)
+#define AIPS_PACRI_TP6_SHIFT                     (4U)
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      (0x20U)
+#define AIPS_PACRI_WP6_SHIFT                     (5U)
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      (0x40U)
+#define AIPS_PACRI_SP6_SHIFT                     (6U)
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      (0x100U)
+#define AIPS_PACRI_TP5_SHIFT                     (8U)
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      (0x200U)
+#define AIPS_PACRI_WP5_SHIFT                     (9U)
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      (0x400U)
+#define AIPS_PACRI_SP5_SHIFT                     (10U)
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      (0x1000U)
+#define AIPS_PACRI_TP4_SHIFT                     (12U)
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      (0x2000U)
+#define AIPS_PACRI_WP4_SHIFT                     (13U)
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      (0x4000U)
+#define AIPS_PACRI_SP4_SHIFT                     (14U)
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      (0x10000U)
+#define AIPS_PACRI_TP3_SHIFT                     (16U)
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      (0x20000U)
+#define AIPS_PACRI_WP3_SHIFT                     (17U)
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      (0x40000U)
+#define AIPS_PACRI_SP3_SHIFT                     (18U)
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      (0x100000U)
+#define AIPS_PACRI_TP2_SHIFT                     (20U)
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      (0x200000U)
+#define AIPS_PACRI_WP2_SHIFT                     (21U)
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      (0x400000U)
+#define AIPS_PACRI_SP2_SHIFT                     (22U)
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRI_TP1_SHIFT                     (24U)
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRI_WP1_SHIFT                     (25U)
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRI_SP1_SHIFT                     (26U)
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRI_TP0_SHIFT                     (28U)
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRI_WP0_SHIFT                     (29U)
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRI_SP0_SHIFT                     (30U)
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
+
+/*! @name PACRJ - Peripheral Access Control Register */
+#define AIPS_PACRJ_TP7_MASK                      (0x1U)
+#define AIPS_PACRJ_TP7_SHIFT                     (0U)
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      (0x2U)
+#define AIPS_PACRJ_WP7_SHIFT                     (1U)
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      (0x4U)
+#define AIPS_PACRJ_SP7_SHIFT                     (2U)
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      (0x10U)
+#define AIPS_PACRJ_TP6_SHIFT                     (4U)
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      (0x20U)
+#define AIPS_PACRJ_WP6_SHIFT                     (5U)
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      (0x40U)
+#define AIPS_PACRJ_SP6_SHIFT                     (6U)
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      (0x100U)
+#define AIPS_PACRJ_TP5_SHIFT                     (8U)
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      (0x200U)
+#define AIPS_PACRJ_WP5_SHIFT                     (9U)
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      (0x400U)
+#define AIPS_PACRJ_SP5_SHIFT                     (10U)
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      (0x1000U)
+#define AIPS_PACRJ_TP4_SHIFT                     (12U)
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      (0x2000U)
+#define AIPS_PACRJ_WP4_SHIFT                     (13U)
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      (0x4000U)
+#define AIPS_PACRJ_SP4_SHIFT                     (14U)
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      (0x10000U)
+#define AIPS_PACRJ_TP3_SHIFT                     (16U)
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      (0x20000U)
+#define AIPS_PACRJ_WP3_SHIFT                     (17U)
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      (0x40000U)
+#define AIPS_PACRJ_SP3_SHIFT                     (18U)
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      (0x100000U)
+#define AIPS_PACRJ_TP2_SHIFT                     (20U)
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      (0x200000U)
+#define AIPS_PACRJ_WP2_SHIFT                     (21U)
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      (0x400000U)
+#define AIPS_PACRJ_SP2_SHIFT                     (22U)
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRJ_TP1_SHIFT                     (24U)
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRJ_WP1_SHIFT                     (25U)
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRJ_SP1_SHIFT                     (26U)
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRJ_TP0_SHIFT                     (28U)
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRJ_WP0_SHIFT                     (29U)
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRJ_SP0_SHIFT                     (30U)
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
+
+/*! @name PACRK - Peripheral Access Control Register */
+#define AIPS_PACRK_TP7_MASK                      (0x1U)
+#define AIPS_PACRK_TP7_SHIFT                     (0U)
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      (0x2U)
+#define AIPS_PACRK_WP7_SHIFT                     (1U)
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      (0x4U)
+#define AIPS_PACRK_SP7_SHIFT                     (2U)
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      (0x10U)
+#define AIPS_PACRK_TP6_SHIFT                     (4U)
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      (0x20U)
+#define AIPS_PACRK_WP6_SHIFT                     (5U)
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      (0x40U)
+#define AIPS_PACRK_SP6_SHIFT                     (6U)
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      (0x100U)
+#define AIPS_PACRK_TP5_SHIFT                     (8U)
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      (0x200U)
+#define AIPS_PACRK_WP5_SHIFT                     (9U)
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      (0x400U)
+#define AIPS_PACRK_SP5_SHIFT                     (10U)
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      (0x1000U)
+#define AIPS_PACRK_TP4_SHIFT                     (12U)
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      (0x2000U)
+#define AIPS_PACRK_WP4_SHIFT                     (13U)
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      (0x4000U)
+#define AIPS_PACRK_SP4_SHIFT                     (14U)
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      (0x10000U)
+#define AIPS_PACRK_TP3_SHIFT                     (16U)
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      (0x20000U)
+#define AIPS_PACRK_WP3_SHIFT                     (17U)
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      (0x40000U)
+#define AIPS_PACRK_SP3_SHIFT                     (18U)
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      (0x100000U)
+#define AIPS_PACRK_TP2_SHIFT                     (20U)
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      (0x200000U)
+#define AIPS_PACRK_WP2_SHIFT                     (21U)
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      (0x400000U)
+#define AIPS_PACRK_SP2_SHIFT                     (22U)
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRK_TP1_SHIFT                     (24U)
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRK_WP1_SHIFT                     (25U)
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRK_SP1_SHIFT                     (26U)
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRK_TP0_SHIFT                     (28U)
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRK_WP0_SHIFT                     (29U)
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRK_SP0_SHIFT                     (30U)
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
+
+/*! @name PACRL - Peripheral Access Control Register */
+#define AIPS_PACRL_TP7_MASK                      (0x1U)
+#define AIPS_PACRL_TP7_SHIFT                     (0U)
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      (0x2U)
+#define AIPS_PACRL_WP7_SHIFT                     (1U)
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      (0x4U)
+#define AIPS_PACRL_SP7_SHIFT                     (2U)
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      (0x10U)
+#define AIPS_PACRL_TP6_SHIFT                     (4U)
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      (0x20U)
+#define AIPS_PACRL_WP6_SHIFT                     (5U)
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      (0x40U)
+#define AIPS_PACRL_SP6_SHIFT                     (6U)
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      (0x100U)
+#define AIPS_PACRL_TP5_SHIFT                     (8U)
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      (0x200U)
+#define AIPS_PACRL_WP5_SHIFT                     (9U)
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      (0x400U)
+#define AIPS_PACRL_SP5_SHIFT                     (10U)
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      (0x1000U)
+#define AIPS_PACRL_TP4_SHIFT                     (12U)
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      (0x2000U)
+#define AIPS_PACRL_WP4_SHIFT                     (13U)
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      (0x4000U)
+#define AIPS_PACRL_SP4_SHIFT                     (14U)
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      (0x10000U)
+#define AIPS_PACRL_TP3_SHIFT                     (16U)
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      (0x20000U)
+#define AIPS_PACRL_WP3_SHIFT                     (17U)
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      (0x40000U)
+#define AIPS_PACRL_SP3_SHIFT                     (18U)
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      (0x100000U)
+#define AIPS_PACRL_TP2_SHIFT                     (20U)
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      (0x200000U)
+#define AIPS_PACRL_WP2_SHIFT                     (21U)
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      (0x400000U)
+#define AIPS_PACRL_SP2_SHIFT                     (22U)
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRL_TP1_SHIFT                     (24U)
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRL_WP1_SHIFT                     (25U)
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRL_SP1_SHIFT                     (26U)
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRL_TP0_SHIFT                     (28U)
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRL_WP0_SHIFT                     (29U)
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRL_SP0_SHIFT                     (30U)
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
+
+/*! @name PACRM - Peripheral Access Control Register */
+#define AIPS_PACRM_TP7_MASK                      (0x1U)
+#define AIPS_PACRM_TP7_SHIFT                     (0U)
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      (0x2U)
+#define AIPS_PACRM_WP7_SHIFT                     (1U)
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      (0x4U)
+#define AIPS_PACRM_SP7_SHIFT                     (2U)
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      (0x10U)
+#define AIPS_PACRM_TP6_SHIFT                     (4U)
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      (0x20U)
+#define AIPS_PACRM_WP6_SHIFT                     (5U)
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      (0x40U)
+#define AIPS_PACRM_SP6_SHIFT                     (6U)
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      (0x100U)
+#define AIPS_PACRM_TP5_SHIFT                     (8U)
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      (0x200U)
+#define AIPS_PACRM_WP5_SHIFT                     (9U)
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      (0x400U)
+#define AIPS_PACRM_SP5_SHIFT                     (10U)
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      (0x1000U)
+#define AIPS_PACRM_TP4_SHIFT                     (12U)
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      (0x2000U)
+#define AIPS_PACRM_WP4_SHIFT                     (13U)
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      (0x4000U)
+#define AIPS_PACRM_SP4_SHIFT                     (14U)
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      (0x10000U)
+#define AIPS_PACRM_TP3_SHIFT                     (16U)
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      (0x20000U)
+#define AIPS_PACRM_WP3_SHIFT                     (17U)
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      (0x40000U)
+#define AIPS_PACRM_SP3_SHIFT                     (18U)
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      (0x100000U)
+#define AIPS_PACRM_TP2_SHIFT                     (20U)
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      (0x200000U)
+#define AIPS_PACRM_WP2_SHIFT                     (21U)
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      (0x400000U)
+#define AIPS_PACRM_SP2_SHIFT                     (22U)
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRM_TP1_SHIFT                     (24U)
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRM_WP1_SHIFT                     (25U)
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRM_SP1_SHIFT                     (26U)
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRM_TP0_SHIFT                     (28U)
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRM_WP0_SHIFT                     (29U)
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRM_SP0_SHIFT                     (30U)
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
+
+/*! @name PACRN - Peripheral Access Control Register */
+#define AIPS_PACRN_TP7_MASK                      (0x1U)
+#define AIPS_PACRN_TP7_SHIFT                     (0U)
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      (0x2U)
+#define AIPS_PACRN_WP7_SHIFT                     (1U)
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      (0x4U)
+#define AIPS_PACRN_SP7_SHIFT                     (2U)
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      (0x10U)
+#define AIPS_PACRN_TP6_SHIFT                     (4U)
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      (0x20U)
+#define AIPS_PACRN_WP6_SHIFT                     (5U)
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      (0x40U)
+#define AIPS_PACRN_SP6_SHIFT                     (6U)
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      (0x100U)
+#define AIPS_PACRN_TP5_SHIFT                     (8U)
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      (0x200U)
+#define AIPS_PACRN_WP5_SHIFT                     (9U)
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      (0x400U)
+#define AIPS_PACRN_SP5_SHIFT                     (10U)
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      (0x1000U)
+#define AIPS_PACRN_TP4_SHIFT                     (12U)
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      (0x2000U)
+#define AIPS_PACRN_WP4_SHIFT                     (13U)
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      (0x4000U)
+#define AIPS_PACRN_SP4_SHIFT                     (14U)
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      (0x10000U)
+#define AIPS_PACRN_TP3_SHIFT                     (16U)
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      (0x20000U)
+#define AIPS_PACRN_WP3_SHIFT                     (17U)
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      (0x40000U)
+#define AIPS_PACRN_SP3_SHIFT                     (18U)
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      (0x100000U)
+#define AIPS_PACRN_TP2_SHIFT                     (20U)
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      (0x200000U)
+#define AIPS_PACRN_WP2_SHIFT                     (21U)
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      (0x400000U)
+#define AIPS_PACRN_SP2_SHIFT                     (22U)
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRN_TP1_SHIFT                     (24U)
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRN_WP1_SHIFT                     (25U)
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRN_SP1_SHIFT                     (26U)
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRN_TP0_SHIFT                     (28U)
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRN_WP0_SHIFT                     (29U)
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRN_SP0_SHIFT                     (30U)
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
+
+/*! @name PACRO - Peripheral Access Control Register */
+#define AIPS_PACRO_TP7_MASK                      (0x1U)
+#define AIPS_PACRO_TP7_SHIFT                     (0U)
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      (0x2U)
+#define AIPS_PACRO_WP7_SHIFT                     (1U)
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      (0x4U)
+#define AIPS_PACRO_SP7_SHIFT                     (2U)
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      (0x10U)
+#define AIPS_PACRO_TP6_SHIFT                     (4U)
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      (0x20U)
+#define AIPS_PACRO_WP6_SHIFT                     (5U)
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      (0x40U)
+#define AIPS_PACRO_SP6_SHIFT                     (6U)
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      (0x100U)
+#define AIPS_PACRO_TP5_SHIFT                     (8U)
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      (0x200U)
+#define AIPS_PACRO_WP5_SHIFT                     (9U)
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      (0x400U)
+#define AIPS_PACRO_SP5_SHIFT                     (10U)
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      (0x1000U)
+#define AIPS_PACRO_TP4_SHIFT                     (12U)
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      (0x2000U)
+#define AIPS_PACRO_WP4_SHIFT                     (13U)
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      (0x4000U)
+#define AIPS_PACRO_SP4_SHIFT                     (14U)
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      (0x10000U)
+#define AIPS_PACRO_TP3_SHIFT                     (16U)
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      (0x20000U)
+#define AIPS_PACRO_WP3_SHIFT                     (17U)
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      (0x40000U)
+#define AIPS_PACRO_SP3_SHIFT                     (18U)
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      (0x100000U)
+#define AIPS_PACRO_TP2_SHIFT                     (20U)
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      (0x200000U)
+#define AIPS_PACRO_WP2_SHIFT                     (21U)
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      (0x400000U)
+#define AIPS_PACRO_SP2_SHIFT                     (22U)
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRO_TP1_SHIFT                     (24U)
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRO_WP1_SHIFT                     (25U)
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRO_SP1_SHIFT                     (26U)
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRO_TP0_SHIFT                     (28U)
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRO_WP0_SHIFT                     (29U)
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRO_SP0_SHIFT                     (30U)
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
+
+/*! @name PACRP - Peripheral Access Control Register */
+#define AIPS_PACRP_TP7_MASK                      (0x1U)
+#define AIPS_PACRP_TP7_SHIFT                     (0U)
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      (0x2U)
+#define AIPS_PACRP_WP7_SHIFT                     (1U)
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      (0x4U)
+#define AIPS_PACRP_SP7_SHIFT                     (2U)
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      (0x10U)
+#define AIPS_PACRP_TP6_SHIFT                     (4U)
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      (0x20U)
+#define AIPS_PACRP_WP6_SHIFT                     (5U)
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      (0x40U)
+#define AIPS_PACRP_SP6_SHIFT                     (6U)
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      (0x100U)
+#define AIPS_PACRP_TP5_SHIFT                     (8U)
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      (0x200U)
+#define AIPS_PACRP_WP5_SHIFT                     (9U)
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      (0x400U)
+#define AIPS_PACRP_SP5_SHIFT                     (10U)
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      (0x1000U)
+#define AIPS_PACRP_TP4_SHIFT                     (12U)
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      (0x2000U)
+#define AIPS_PACRP_WP4_SHIFT                     (13U)
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      (0x4000U)
+#define AIPS_PACRP_SP4_SHIFT                     (14U)
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      (0x10000U)
+#define AIPS_PACRP_TP3_SHIFT                     (16U)
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      (0x20000U)
+#define AIPS_PACRP_WP3_SHIFT                     (17U)
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      (0x40000U)
+#define AIPS_PACRP_SP3_SHIFT                     (18U)
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      (0x100000U)
+#define AIPS_PACRP_TP2_SHIFT                     (20U)
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      (0x200000U)
+#define AIPS_PACRP_WP2_SHIFT                     (21U)
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      (0x400000U)
+#define AIPS_PACRP_SP2_SHIFT                     (22U)
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRP_TP1_SHIFT                     (24U)
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRP_WP1_SHIFT                     (25U)
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRP_SP1_SHIFT                     (26U)
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRP_TP0_SHIFT                     (28U)
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRP_WP0_SHIFT                     (29U)
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRP_SP0_SHIFT                     (30U)
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
+
 
 /*!
  * @}
@@ -1594,70 +2001,15 @@ typedef struct {
 #define AIPS0_BASE                               (0x40000000u)
 /** Peripheral AIPS0 base pointer */
 #define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
-#define AIPS0_BASE_PTR                           (AIPS0)
 /** Peripheral AIPS1 base address */
 #define AIPS1_BASE                               (0x40080000u)
 /** Peripheral AIPS1 base pointer */
 #define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
-#define AIPS1_BASE_PTR                           (AIPS1)
 /** Array initializer of AIPS peripheral base addresses */
 #define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
 /** Array initializer of AIPS peripheral base pointers */
 #define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
 
-/* ----------------------------------------------------------------------------
-   -- AIPS - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
- * @{
- */
-
-
-/* AIPS - Register instance definitions */
-/* AIPS0 */
-#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
-#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
-#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
-#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
-#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
-#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
-#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
-#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
-#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
-#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
-#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
-#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
-#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
-#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
-#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
-#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
-#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
-/* AIPS1 */
-#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
-#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
-#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
-#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
-#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
-#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
-#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
-#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
-#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
-#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
-#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
-#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
-#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
-#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
-#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
-#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
-#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
-
-/*!
- * @}
- */ /* end of group AIPS_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group AIPS_Peripheral_Access_Layer */
@@ -1692,32 +2044,7 @@ typedef struct {
   __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
        uint8_t RESERVED_5[252];
   __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
-} AXBS_Type, *AXBS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- AXBS - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
- * @{
- */
-
-
-/* AXBS - Register accessors */
-#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
-#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
-#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
-#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
-#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
-#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
-#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
-#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
-
-/*!
- * @}
- */ /* end of group AXBS_Register_Accessor_Macros */
-
+} AXBS_Type;
 
 /* ----------------------------------------------------------------------------
    -- AXBS Register Masks
@@ -1728,63 +2055,79 @@ typedef struct {
  * @{
  */
 
-/* PRS Bit Fields */
-#define AXBS_PRS_M0_MASK                         0x7u
-#define AXBS_PRS_M0_SHIFT                        0
-#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
-#define AXBS_PRS_M1_MASK                         0x70u
-#define AXBS_PRS_M1_SHIFT                        4
-#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
-#define AXBS_PRS_M2_MASK                         0x700u
-#define AXBS_PRS_M2_SHIFT                        8
-#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
-#define AXBS_PRS_M3_MASK                         0x7000u
-#define AXBS_PRS_M3_SHIFT                        12
-#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
-#define AXBS_PRS_M4_MASK                         0x70000u
-#define AXBS_PRS_M4_SHIFT                        16
-#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
-#define AXBS_PRS_M5_MASK                         0x700000u
-#define AXBS_PRS_M5_SHIFT                        20
-#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
-/* CRS Bit Fields */
-#define AXBS_CRS_PARK_MASK                       0x7u
-#define AXBS_CRS_PARK_SHIFT                      0
-#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
-#define AXBS_CRS_PCTL_MASK                       0x30u
-#define AXBS_CRS_PCTL_SHIFT                      4
-#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
-#define AXBS_CRS_ARB_MASK                        0x300u
-#define AXBS_CRS_ARB_SHIFT                       8
-#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
-#define AXBS_CRS_HLP_MASK                        0x40000000u
-#define AXBS_CRS_HLP_SHIFT                       30
-#define AXBS_CRS_RO_MASK                         0x80000000u
-#define AXBS_CRS_RO_SHIFT                        31
-/* MGPCR0 Bit Fields */
-#define AXBS_MGPCR0_AULB_MASK                    0x7u
-#define AXBS_MGPCR0_AULB_SHIFT                   0
-#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
-/* MGPCR1 Bit Fields */
-#define AXBS_MGPCR1_AULB_MASK                    0x7u
-#define AXBS_MGPCR1_AULB_SHIFT                   0
-#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
-/* MGPCR2 Bit Fields */
-#define AXBS_MGPCR2_AULB_MASK                    0x7u
-#define AXBS_MGPCR2_AULB_SHIFT                   0
-#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
-/* MGPCR3 Bit Fields */
-#define AXBS_MGPCR3_AULB_MASK                    0x7u
-#define AXBS_MGPCR3_AULB_SHIFT                   0
-#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
-/* MGPCR4 Bit Fields */
-#define AXBS_MGPCR4_AULB_MASK                    0x7u
-#define AXBS_MGPCR4_AULB_SHIFT                   0
-#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
-/* MGPCR5 Bit Fields */
-#define AXBS_MGPCR5_AULB_MASK                    0x7u
-#define AXBS_MGPCR5_AULB_SHIFT                   0
-#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+/*! @name PRS - Priority Registers Slave */
+#define AXBS_PRS_M0_MASK                         (0x7U)
+#define AXBS_PRS_M0_SHIFT                        (0U)
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         (0x70U)
+#define AXBS_PRS_M1_SHIFT                        (4U)
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         (0x700U)
+#define AXBS_PRS_M2_SHIFT                        (8U)
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         (0x7000U)
+#define AXBS_PRS_M3_SHIFT                        (12U)
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         (0x70000U)
+#define AXBS_PRS_M4_SHIFT                        (16U)
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         (0x700000U)
+#define AXBS_PRS_M5_SHIFT                        (20U)
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+
+/* The count of AXBS_PRS */
+#define AXBS_PRS_COUNT                           (5U)
+
+/*! @name CRS - Control Register */
+#define AXBS_CRS_PARK_MASK                       (0x7U)
+#define AXBS_CRS_PARK_SHIFT                      (0U)
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       (0x30U)
+#define AXBS_CRS_PCTL_SHIFT                      (4U)
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        (0x300U)
+#define AXBS_CRS_ARB_SHIFT                       (8U)
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        (0x40000000U)
+#define AXBS_CRS_HLP_SHIFT                       (30U)
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         (0x80000000U)
+#define AXBS_CRS_RO_SHIFT                        (31U)
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
+
+/* The count of AXBS_CRS */
+#define AXBS_CRS_COUNT                           (5U)
+
+/*! @name MGPCR0 - Master General Purpose Control Register */
+#define AXBS_MGPCR0_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR0_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+
+/*! @name MGPCR1 - Master General Purpose Control Register */
+#define AXBS_MGPCR1_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR1_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+
+/*! @name MGPCR2 - Master General Purpose Control Register */
+#define AXBS_MGPCR2_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR2_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+
+/*! @name MGPCR3 - Master General Purpose Control Register */
+#define AXBS_MGPCR3_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR3_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
+
+/*! @name MGPCR4 - Master General Purpose Control Register */
+#define AXBS_MGPCR4_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR4_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+
+/*! @name MGPCR5 - Master General Purpose Control Register */
+#define AXBS_MGPCR5_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR5_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+
 
 /*!
  * @}
@@ -1796,50 +2139,11 @@ typedef struct {
 #define AXBS_BASE                                (0x40004000u)
 /** Peripheral AXBS base pointer */
 #define AXBS                                     ((AXBS_Type *)AXBS_BASE)
-#define AXBS_BASE_PTR                            (AXBS)
 /** Array initializer of AXBS peripheral base addresses */
 #define AXBS_BASE_ADDRS                          { AXBS_BASE }
 /** Array initializer of AXBS peripheral base pointers */
 #define AXBS_BASE_PTRS                           { AXBS }
 
-/* ----------------------------------------------------------------------------
-   -- AXBS - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
- * @{
- */
-
-
-/* AXBS - Register instance definitions */
-/* AXBS */
-#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
-#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
-#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
-#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
-#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
-#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
-#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
-#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
-#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
-#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
-#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
-#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
-#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
-#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
-#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
-#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
-
-/* AXBS - Register array accessors */
-#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
-#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
-
-/*!
- * @}
- */ /* end of group AXBS_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group AXBS_Peripheral_Access_Layer */
@@ -1884,44 +2188,7 @@ typedef struct {
   } MB[16];
        uint8_t RESERVED_5[1792];
   __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
-} CAN_Type, *CAN_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- CAN - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
- * @{
- */
-
-
-/* CAN - Register accessors */
-#define CAN_MCR_REG(base)                        ((base)->MCR)
-#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
-#define CAN_TIMER_REG(base)                      ((base)->TIMER)
-#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
-#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
-#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
-#define CAN_ECR_REG(base)                        ((base)->ECR)
-#define CAN_ESR1_REG(base)                       ((base)->ESR1)
-#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
-#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
-#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
-#define CAN_ESR2_REG(base)                       ((base)->ESR2)
-#define CAN_CRCR_REG(base)                       ((base)->CRCR)
-#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
-#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
-#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
-#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
-#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
-#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
-#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
-
-/*!
- * @}
- */ /* end of group CAN_Register_Accessor_Macros */
-
+} CAN_Type;
 
 /* ----------------------------------------------------------------------------
    -- CAN Register Masks
@@ -1932,257 +2199,349 @@ typedef struct {
  * @{
  */
 
-/* MCR Bit Fields */
-#define CAN_MCR_MAXMB_MASK                       0x7Fu
-#define CAN_MCR_MAXMB_SHIFT                      0
-#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
-#define CAN_MCR_IDAM_MASK                        0x300u
-#define CAN_MCR_IDAM_SHIFT                       8
-#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
-#define CAN_MCR_AEN_MASK                         0x1000u
-#define CAN_MCR_AEN_SHIFT                        12
-#define CAN_MCR_LPRIOEN_MASK                     0x2000u
-#define CAN_MCR_LPRIOEN_SHIFT                    13
-#define CAN_MCR_IRMQ_MASK                        0x10000u
-#define CAN_MCR_IRMQ_SHIFT                       16
-#define CAN_MCR_SRXDIS_MASK                      0x20000u
-#define CAN_MCR_SRXDIS_SHIFT                     17
-#define CAN_MCR_WAKSRC_MASK                      0x80000u
-#define CAN_MCR_WAKSRC_SHIFT                     19
-#define CAN_MCR_LPMACK_MASK                      0x100000u
-#define CAN_MCR_LPMACK_SHIFT                     20
-#define CAN_MCR_WRNEN_MASK                       0x200000u
-#define CAN_MCR_WRNEN_SHIFT                      21
-#define CAN_MCR_SLFWAK_MASK                      0x400000u
-#define CAN_MCR_SLFWAK_SHIFT                     22
-#define CAN_MCR_SUPV_MASK                        0x800000u
-#define CAN_MCR_SUPV_SHIFT                       23
-#define CAN_MCR_FRZACK_MASK                      0x1000000u
-#define CAN_MCR_FRZACK_SHIFT                     24
-#define CAN_MCR_SOFTRST_MASK                     0x2000000u
-#define CAN_MCR_SOFTRST_SHIFT                    25
-#define CAN_MCR_WAKMSK_MASK                      0x4000000u
-#define CAN_MCR_WAKMSK_SHIFT                     26
-#define CAN_MCR_NOTRDY_MASK                      0x8000000u
-#define CAN_MCR_NOTRDY_SHIFT                     27
-#define CAN_MCR_HALT_MASK                        0x10000000u
-#define CAN_MCR_HALT_SHIFT                       28
-#define CAN_MCR_RFEN_MASK                        0x20000000u
-#define CAN_MCR_RFEN_SHIFT                       29
-#define CAN_MCR_FRZ_MASK                         0x40000000u
-#define CAN_MCR_FRZ_SHIFT                        30
-#define CAN_MCR_MDIS_MASK                        0x80000000u
-#define CAN_MCR_MDIS_SHIFT                       31
-/* CTRL1 Bit Fields */
-#define CAN_CTRL1_PROPSEG_MASK                   0x7u
-#define CAN_CTRL1_PROPSEG_SHIFT                  0
-#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
-#define CAN_CTRL1_LOM_MASK                       0x8u
-#define CAN_CTRL1_LOM_SHIFT                      3
-#define CAN_CTRL1_LBUF_MASK                      0x10u
-#define CAN_CTRL1_LBUF_SHIFT                     4
-#define CAN_CTRL1_TSYN_MASK                      0x20u
-#define CAN_CTRL1_TSYN_SHIFT                     5
-#define CAN_CTRL1_BOFFREC_MASK                   0x40u
-#define CAN_CTRL1_BOFFREC_SHIFT                  6
-#define CAN_CTRL1_SMP_MASK                       0x80u
-#define CAN_CTRL1_SMP_SHIFT                      7
-#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
-#define CAN_CTRL1_RWRNMSK_SHIFT                  10
-#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
-#define CAN_CTRL1_TWRNMSK_SHIFT                  11
-#define CAN_CTRL1_LPB_MASK                       0x1000u
-#define CAN_CTRL1_LPB_SHIFT                      12
-#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
-#define CAN_CTRL1_CLKSRC_SHIFT                   13
-#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
-#define CAN_CTRL1_ERRMSK_SHIFT                   14
-#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
-#define CAN_CTRL1_BOFFMSK_SHIFT                  15
-#define CAN_CTRL1_PSEG2_MASK                     0x70000u
-#define CAN_CTRL1_PSEG2_SHIFT                    16
-#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
-#define CAN_CTRL1_PSEG1_MASK                     0x380000u
-#define CAN_CTRL1_PSEG1_SHIFT                    19
-#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
-#define CAN_CTRL1_RJW_MASK                       0xC00000u
-#define CAN_CTRL1_RJW_SHIFT                      22
-#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
-#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
-#define CAN_CTRL1_PRESDIV_SHIFT                  24
-#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
-/* TIMER Bit Fields */
-#define CAN_TIMER_TIMER_MASK                     0xFFFFu
-#define CAN_TIMER_TIMER_SHIFT                    0
-#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
-/* RXMGMASK Bit Fields */
-#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
-#define CAN_RXMGMASK_MG_SHIFT                    0
-#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
-/* RX14MASK Bit Fields */
-#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
-#define CAN_RX14MASK_RX14M_SHIFT                 0
-#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
-/* RX15MASK Bit Fields */
-#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
-#define CAN_RX15MASK_RX15M_SHIFT                 0
-#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
-/* ECR Bit Fields */
-#define CAN_ECR_TXERRCNT_MASK                    0xFFu
-#define CAN_ECR_TXERRCNT_SHIFT                   0
-#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
-#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
-#define CAN_ECR_RXERRCNT_SHIFT                   8
-#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
-/* ESR1 Bit Fields */
-#define CAN_ESR1_WAKINT_MASK                     0x1u
-#define CAN_ESR1_WAKINT_SHIFT                    0
-#define CAN_ESR1_ERRINT_MASK                     0x2u
-#define CAN_ESR1_ERRINT_SHIFT                    1
-#define CAN_ESR1_BOFFINT_MASK                    0x4u
-#define CAN_ESR1_BOFFINT_SHIFT                   2
-#define CAN_ESR1_RX_MASK                         0x8u
-#define CAN_ESR1_RX_SHIFT                        3
-#define CAN_ESR1_FLTCONF_MASK                    0x30u
-#define CAN_ESR1_FLTCONF_SHIFT                   4
-#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
-#define CAN_ESR1_TX_MASK                         0x40u
-#define CAN_ESR1_TX_SHIFT                        6
-#define CAN_ESR1_IDLE_MASK                       0x80u
-#define CAN_ESR1_IDLE_SHIFT                      7
-#define CAN_ESR1_RXWRN_MASK                      0x100u
-#define CAN_ESR1_RXWRN_SHIFT                     8
-#define CAN_ESR1_TXWRN_MASK                      0x200u
-#define CAN_ESR1_TXWRN_SHIFT                     9
-#define CAN_ESR1_STFERR_MASK                     0x400u
-#define CAN_ESR1_STFERR_SHIFT                    10
-#define CAN_ESR1_FRMERR_MASK                     0x800u
-#define CAN_ESR1_FRMERR_SHIFT                    11
-#define CAN_ESR1_CRCERR_MASK                     0x1000u
-#define CAN_ESR1_CRCERR_SHIFT                    12
-#define CAN_ESR1_ACKERR_MASK                     0x2000u
-#define CAN_ESR1_ACKERR_SHIFT                    13
-#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
-#define CAN_ESR1_BIT0ERR_SHIFT                   14
-#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
-#define CAN_ESR1_BIT1ERR_SHIFT                   15
-#define CAN_ESR1_RWRNINT_MASK                    0x10000u
-#define CAN_ESR1_RWRNINT_SHIFT                   16
-#define CAN_ESR1_TWRNINT_MASK                    0x20000u
-#define CAN_ESR1_TWRNINT_SHIFT                   17
-#define CAN_ESR1_SYNCH_MASK                      0x40000u
-#define CAN_ESR1_SYNCH_SHIFT                     18
-/* IMASK1 Bit Fields */
-#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
-#define CAN_IMASK1_BUFLM_SHIFT                   0
-#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
-/* IFLAG1 Bit Fields */
-#define CAN_IFLAG1_BUF4TO0I_MASK                 0x1Fu
-#define CAN_IFLAG1_BUF4TO0I_SHIFT                0
-#define CAN_IFLAG1_BUF4TO0I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
-#define CAN_IFLAG1_BUF5I_MASK                    0x20u
-#define CAN_IFLAG1_BUF5I_SHIFT                   5
-#define CAN_IFLAG1_BUF6I_MASK                    0x40u
-#define CAN_IFLAG1_BUF6I_SHIFT                   6
-#define CAN_IFLAG1_BUF7I_MASK                    0x80u
-#define CAN_IFLAG1_BUF7I_SHIFT                   7
-#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
-#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
-#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
-/* CTRL2 Bit Fields */
-#define CAN_CTRL2_EACEN_MASK                     0x10000u
-#define CAN_CTRL2_EACEN_SHIFT                    16
-#define CAN_CTRL2_RRS_MASK                       0x20000u
-#define CAN_CTRL2_RRS_SHIFT                      17
-#define CAN_CTRL2_MRP_MASK                       0x40000u
-#define CAN_CTRL2_MRP_SHIFT                      18
-#define CAN_CTRL2_TASD_MASK                      0xF80000u
-#define CAN_CTRL2_TASD_SHIFT                     19
-#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
-#define CAN_CTRL2_RFFN_MASK                      0xF000000u
-#define CAN_CTRL2_RFFN_SHIFT                     24
-#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
-#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
-#define CAN_CTRL2_WRMFRZ_SHIFT                   28
-/* ESR2 Bit Fields */
-#define CAN_ESR2_IMB_MASK                        0x2000u
-#define CAN_ESR2_IMB_SHIFT                       13
-#define CAN_ESR2_VPS_MASK                        0x4000u
-#define CAN_ESR2_VPS_SHIFT                       14
-#define CAN_ESR2_LPTM_MASK                       0x7F0000u
-#define CAN_ESR2_LPTM_SHIFT                      16
-#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
-/* CRCR Bit Fields */
-#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
-#define CAN_CRCR_TXCRC_SHIFT                     0
-#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
-#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
-#define CAN_CRCR_MBCRC_SHIFT                     16
-#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
-/* RXFGMASK Bit Fields */
-#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
-#define CAN_RXFGMASK_FGM_SHIFT                   0
-#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
-/* RXFIR Bit Fields */
-#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
-#define CAN_RXFIR_IDHIT_SHIFT                    0
-#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
-/* CS Bit Fields */
-#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
-#define CAN_CS_TIME_STAMP_SHIFT                  0
-#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
-#define CAN_CS_DLC_MASK                          0xF0000u
-#define CAN_CS_DLC_SHIFT                         16
-#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
-#define CAN_CS_RTR_MASK                          0x100000u
-#define CAN_CS_RTR_SHIFT                         20
-#define CAN_CS_IDE_MASK                          0x200000u
-#define CAN_CS_IDE_SHIFT                         21
-#define CAN_CS_SRR_MASK                          0x400000u
-#define CAN_CS_SRR_SHIFT                         22
-#define CAN_CS_CODE_MASK                         0xF000000u
-#define CAN_CS_CODE_SHIFT                        24
-#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
-/* ID Bit Fields */
-#define CAN_ID_EXT_MASK                          0x3FFFFu
-#define CAN_ID_EXT_SHIFT                         0
-#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
-#define CAN_ID_STD_MASK                          0x1FFC0000u
-#define CAN_ID_STD_SHIFT                         18
-#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
-#define CAN_ID_PRIO_MASK                         0xE0000000u
-#define CAN_ID_PRIO_SHIFT                        29
-#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
-/* WORD0 Bit Fields */
-#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
-#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
-#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
-#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
-#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
-#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
-#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
-#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
-#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
-#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
-#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
-#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
-/* WORD1 Bit Fields */
-#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
-#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
-#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
-#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
-#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
-#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
-#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
-#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
-#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
-#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
-#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
-#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
-/* RXIMR Bit Fields */
-#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
-#define CAN_RXIMR_MI_SHIFT                       0
-#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+/*! @name MCR - Module Configuration Register */
+#define CAN_MCR_MAXMB_MASK                       (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT                      (0U)
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        (0x300U)
+#define CAN_MCR_IDAM_SHIFT                       (8U)
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         (0x1000U)
+#define CAN_MCR_AEN_SHIFT                        (12U)
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
+#define CAN_MCR_LPRIOEN_SHIFT                    (13U)
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        (0x10000U)
+#define CAN_MCR_IRMQ_SHIFT                       (16U)
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      (0x20000U)
+#define CAN_MCR_SRXDIS_SHIFT                     (17U)
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      (0x80000U)
+#define CAN_MCR_WAKSRC_SHIFT                     (19U)
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      (0x100000U)
+#define CAN_MCR_LPMACK_SHIFT                     (20U)
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       (0x200000U)
+#define CAN_MCR_WRNEN_SHIFT                      (21U)
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      (0x400000U)
+#define CAN_MCR_SLFWAK_SHIFT                     (22U)
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        (0x800000U)
+#define CAN_MCR_SUPV_SHIFT                       (23U)
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      (0x1000000U)
+#define CAN_MCR_FRZACK_SHIFT                     (24U)
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
+#define CAN_MCR_SOFTRST_SHIFT                    (25U)
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
+#define CAN_MCR_WAKMSK_SHIFT                     (26U)
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
+#define CAN_MCR_NOTRDY_SHIFT                     (27U)
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        (0x10000000U)
+#define CAN_MCR_HALT_SHIFT                       (28U)
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        (0x20000000U)
+#define CAN_MCR_RFEN_SHIFT                       (29U)
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         (0x40000000U)
+#define CAN_MCR_FRZ_SHIFT                        (30U)
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        (0x80000000U)
+#define CAN_MCR_MDIS_SHIFT                       (31U)
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+
+/*! @name CTRL1 - Control 1 register */
+#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       (0x8U)
+#define CAN_CTRL1_LOM_SHIFT                      (3U)
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      (0x10U)
+#define CAN_CTRL1_LBUF_SHIFT                     (4U)
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      (0x20U)
+#define CAN_CTRL1_TSYN_SHIFT                     (5U)
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
+#define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       (0x80U)
+#define CAN_CTRL1_SMP_SHIFT                      (7U)
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
+#define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
+#define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       (0x1000U)
+#define CAN_CTRL1_LPB_SHIFT                      (12U)
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
+#define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
+#define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
+#define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT                      (22U)
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+
+/*! @name TIMER - Free Running Timer */
+#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT                    (0U)
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+
+/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
+#define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
+#define CAN_RXMGMASK_MG_SHIFT                    (0U)
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+
+/*! @name RX14MASK - Rx 14 Mask register */
+#define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX14MASK_RX14M_SHIFT                 (0U)
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+
+/*! @name RX15MASK - Rx 15 Mask register */
+#define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX15MASK_RX15M_SHIFT                 (0U)
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+
+/*! @name ECR - Error Counter */
+#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
+#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
+#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+
+/*! @name ESR1 - Error and Status 1 register */
+#define CAN_ESR1_WAKINT_MASK                     (0x1U)
+#define CAN_ESR1_WAKINT_SHIFT                    (0U)
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     (0x2U)
+#define CAN_ESR1_ERRINT_SHIFT                    (1U)
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    (0x4U)
+#define CAN_ESR1_BOFFINT_SHIFT                   (2U)
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         (0x8U)
+#define CAN_ESR1_RX_SHIFT                        (3U)
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         (0x40U)
+#define CAN_ESR1_TX_SHIFT                        (6U)
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       (0x80U)
+#define CAN_ESR1_IDLE_SHIFT                      (7U)
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      (0x100U)
+#define CAN_ESR1_RXWRN_SHIFT                     (8U)
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      (0x200U)
+#define CAN_ESR1_TXWRN_SHIFT                     (9U)
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     (0x400U)
+#define CAN_ESR1_STFERR_SHIFT                    (10U)
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     (0x800U)
+#define CAN_ESR1_FRMERR_SHIFT                    (11U)
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     (0x1000U)
+#define CAN_ESR1_CRCERR_SHIFT                    (12U)
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     (0x2000U)
+#define CAN_ESR1_ACKERR_SHIFT                    (13U)
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
+#define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
+#define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
+#define CAN_ESR1_RWRNINT_SHIFT                   (16U)
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
+#define CAN_ESR1_TWRNINT_SHIFT                   (17U)
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      (0x40000U)
+#define CAN_ESR1_SYNCH_SHIFT                     (18U)
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+
+/*! @name IMASK1 - Interrupt Masks 1 register */
+#define CAN_IMASK1_BUFLM_MASK                    (0xFFFFFFFFU)
+#define CAN_IMASK1_BUFLM_SHIFT                   (0U)
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
+
+/*! @name IFLAG1 - Interrupt Flags 1 register */
+#define CAN_IFLAG1_BUF4TO0I_MASK                 (0x1FU)
+#define CAN_IFLAG1_BUF4TO0I_SHIFT                (0U)
+#define CAN_IFLAG1_BUF4TO0I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
+#define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
+#define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
+#define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+
+/*! @name CTRL2 - Control 2 register */
+#define CAN_CTRL2_EACEN_MASK                     (0x10000U)
+#define CAN_CTRL2_EACEN_SHIFT                    (16U)
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       (0x20000U)
+#define CAN_CTRL2_RRS_SHIFT                      (17U)
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       (0x40000U)
+#define CAN_CTRL2_MRP_SHIFT                      (18U)
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT                     (19U)
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT                     (24U)
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
+#define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
+
+/*! @name ESR2 - Error and Status 2 register */
+#define CAN_ESR2_IMB_MASK                        (0x2000U)
+#define CAN_ESR2_IMB_SHIFT                       (13U)
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        (0x4000U)
+#define CAN_ESR2_VPS_SHIFT                       (14U)
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT                      (16U)
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+
+/*! @name CRCR - CRC Register */
+#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT                     (0U)
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT                     (16U)
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+
+/*! @name RXFGMASK - Rx FIFO Global Mask register */
+#define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
+#define CAN_RXFGMASK_FGM_SHIFT                   (0U)
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+
+/*! @name RXFIR - Rx FIFO Information Register */
+#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
+#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          (0xF0000U)
+#define CAN_CS_DLC_SHIFT                         (16U)
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          (0x100000U)
+#define CAN_CS_RTR_SHIFT                         (20U)
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          (0x200000U)
+#define CAN_CS_IDE_SHIFT                         (21U)
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          (0x400000U)
+#define CAN_CS_SRR_SHIFT                         (22U)
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         (0xF000000U)
+#define CAN_CS_CODE_SHIFT                        (24U)
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT                             (16U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
+#define CAN_ID_EXT_MASK                          (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT                         (0U)
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT                         (18U)
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT                        (29U)
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT                             (16U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
+#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT                          (16U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
+#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT                          (16U)
+
+/*! @name RXIMR - Rx Individual Mask Registers */
+#define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
+#define CAN_RXIMR_MI_SHIFT                       (0U)
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+
+/* The count of CAN_RXIMR */
+#define CAN_RXIMR_COUNT                          (16U)
+
 
 /*!
  * @}
@@ -2194,12 +2553,10 @@ typedef struct {
 #define CAN0_BASE                                (0x40024000u)
 /** Peripheral CAN0 base pointer */
 #define CAN0                                     ((CAN_Type *)CAN0_BASE)
-#define CAN0_BASE_PTR                            (CAN0)
 /** Peripheral CAN1 base address */
 #define CAN1_BASE                                (0x400A4000u)
 /** Peripheral CAN1 base pointer */
 #define CAN1                                     ((CAN_Type *)CAN1_BASE)
-#define CAN1_BASE_PTR                            (CAN1)
 /** Array initializer of CAN peripheral base addresses */
 #define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
 /** Array initializer of CAN peripheral base pointers */
@@ -2212,227 +2569,6 @@ typedef struct {
 #define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
 #define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- CAN - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
- * @{
- */
-
-
-/* CAN - Register instance definitions */
-/* CAN0 */
-#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
-#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
-#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
-#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
-#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
-#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
-#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
-#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
-#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
-#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
-#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
-#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
-#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
-#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
-#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
-#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
-#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
-#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
-#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
-#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
-#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
-#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
-#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
-#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
-#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
-#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
-#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
-#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
-#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
-#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
-#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
-#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
-#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
-#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
-#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
-#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
-#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
-#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
-#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
-#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
-#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
-#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
-#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
-#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
-#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
-#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
-#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
-#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
-#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
-#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
-#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
-#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
-#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
-#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
-#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
-#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
-#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
-#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
-#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
-#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
-#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
-#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
-#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
-#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
-#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
-#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
-#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
-#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
-#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
-#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
-#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
-#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
-#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
-#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
-#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
-#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
-#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
-#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
-#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
-#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
-#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
-#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
-#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
-#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
-#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
-#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
-#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
-#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
-#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
-#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
-#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
-#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
-#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
-#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
-#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
-/* CAN1 */
-#define CAN1_MCR                                 CAN_MCR_REG(CAN1)
-#define CAN1_CTRL1                               CAN_CTRL1_REG(CAN1)
-#define CAN1_TIMER                               CAN_TIMER_REG(CAN1)
-#define CAN1_RXMGMASK                            CAN_RXMGMASK_REG(CAN1)
-#define CAN1_RX14MASK                            CAN_RX14MASK_REG(CAN1)
-#define CAN1_RX15MASK                            CAN_RX15MASK_REG(CAN1)
-#define CAN1_ECR                                 CAN_ECR_REG(CAN1)
-#define CAN1_ESR1                                CAN_ESR1_REG(CAN1)
-#define CAN1_IMASK1                              CAN_IMASK1_REG(CAN1)
-#define CAN1_IFLAG1                              CAN_IFLAG1_REG(CAN1)
-#define CAN1_CTRL2                               CAN_CTRL2_REG(CAN1)
-#define CAN1_ESR2                                CAN_ESR2_REG(CAN1)
-#define CAN1_CRCR                                CAN_CRCR_REG(CAN1)
-#define CAN1_RXFGMASK                            CAN_RXFGMASK_REG(CAN1)
-#define CAN1_RXFIR                               CAN_RXFIR_REG(CAN1)
-#define CAN1_CS0                                 CAN_CS_REG(CAN1,0)
-#define CAN1_ID0                                 CAN_ID_REG(CAN1,0)
-#define CAN1_WORD00                              CAN_WORD0_REG(CAN1,0)
-#define CAN1_WORD10                              CAN_WORD1_REG(CAN1,0)
-#define CAN1_CS1                                 CAN_CS_REG(CAN1,1)
-#define CAN1_ID1                                 CAN_ID_REG(CAN1,1)
-#define CAN1_WORD01                              CAN_WORD0_REG(CAN1,1)
-#define CAN1_WORD11                              CAN_WORD1_REG(CAN1,1)
-#define CAN1_CS2                                 CAN_CS_REG(CAN1,2)
-#define CAN1_ID2                                 CAN_ID_REG(CAN1,2)
-#define CAN1_WORD02                              CAN_WORD0_REG(CAN1,2)
-#define CAN1_WORD12                              CAN_WORD1_REG(CAN1,2)
-#define CAN1_CS3                                 CAN_CS_REG(CAN1,3)
-#define CAN1_ID3                                 CAN_ID_REG(CAN1,3)
-#define CAN1_WORD03                              CAN_WORD0_REG(CAN1,3)
-#define CAN1_WORD13                              CAN_WORD1_REG(CAN1,3)
-#define CAN1_CS4                                 CAN_CS_REG(CAN1,4)
-#define CAN1_ID4                                 CAN_ID_REG(CAN1,4)
-#define CAN1_WORD04                              CAN_WORD0_REG(CAN1,4)
-#define CAN1_WORD14                              CAN_WORD1_REG(CAN1,4)
-#define CAN1_CS5                                 CAN_CS_REG(CAN1,5)
-#define CAN1_ID5                                 CAN_ID_REG(CAN1,5)
-#define CAN1_WORD05                              CAN_WORD0_REG(CAN1,5)
-#define CAN1_WORD15                              CAN_WORD1_REG(CAN1,5)
-#define CAN1_CS6                                 CAN_CS_REG(CAN1,6)
-#define CAN1_ID6                                 CAN_ID_REG(CAN1,6)
-#define CAN1_WORD06                              CAN_WORD0_REG(CAN1,6)
-#define CAN1_WORD16                              CAN_WORD1_REG(CAN1,6)
-#define CAN1_CS7                                 CAN_CS_REG(CAN1,7)
-#define CAN1_ID7                                 CAN_ID_REG(CAN1,7)
-#define CAN1_WORD07                              CAN_WORD0_REG(CAN1,7)
-#define CAN1_WORD17                              CAN_WORD1_REG(CAN1,7)
-#define CAN1_CS8                                 CAN_CS_REG(CAN1,8)
-#define CAN1_ID8                                 CAN_ID_REG(CAN1,8)
-#define CAN1_WORD08                              CAN_WORD0_REG(CAN1,8)
-#define CAN1_WORD18                              CAN_WORD1_REG(CAN1,8)
-#define CAN1_CS9                                 CAN_CS_REG(CAN1,9)
-#define CAN1_ID9                                 CAN_ID_REG(CAN1,9)
-#define CAN1_WORD09                              CAN_WORD0_REG(CAN1,9)
-#define CAN1_WORD19                              CAN_WORD1_REG(CAN1,9)
-#define CAN1_CS10                                CAN_CS_REG(CAN1,10)
-#define CAN1_ID10                                CAN_ID_REG(CAN1,10)
-#define CAN1_WORD010                             CAN_WORD0_REG(CAN1,10)
-#define CAN1_WORD110                             CAN_WORD1_REG(CAN1,10)
-#define CAN1_CS11                                CAN_CS_REG(CAN1,11)
-#define CAN1_ID11                                CAN_ID_REG(CAN1,11)
-#define CAN1_WORD011                             CAN_WORD0_REG(CAN1,11)
-#define CAN1_WORD111                             CAN_WORD1_REG(CAN1,11)
-#define CAN1_CS12                                CAN_CS_REG(CAN1,12)
-#define CAN1_ID12                                CAN_ID_REG(CAN1,12)
-#define CAN1_WORD012                             CAN_WORD0_REG(CAN1,12)
-#define CAN1_WORD112                             CAN_WORD1_REG(CAN1,12)
-#define CAN1_CS13                                CAN_CS_REG(CAN1,13)
-#define CAN1_ID13                                CAN_ID_REG(CAN1,13)
-#define CAN1_WORD013                             CAN_WORD0_REG(CAN1,13)
-#define CAN1_WORD113                             CAN_WORD1_REG(CAN1,13)
-#define CAN1_CS14                                CAN_CS_REG(CAN1,14)
-#define CAN1_ID14                                CAN_ID_REG(CAN1,14)
-#define CAN1_WORD014                             CAN_WORD0_REG(CAN1,14)
-#define CAN1_WORD114                             CAN_WORD1_REG(CAN1,14)
-#define CAN1_CS15                                CAN_CS_REG(CAN1,15)
-#define CAN1_ID15                                CAN_ID_REG(CAN1,15)
-#define CAN1_WORD015                             CAN_WORD0_REG(CAN1,15)
-#define CAN1_WORD115                             CAN_WORD1_REG(CAN1,15)
-#define CAN1_RXIMR0                              CAN_RXIMR_REG(CAN1,0)
-#define CAN1_RXIMR1                              CAN_RXIMR_REG(CAN1,1)
-#define CAN1_RXIMR2                              CAN_RXIMR_REG(CAN1,2)
-#define CAN1_RXIMR3                              CAN_RXIMR_REG(CAN1,3)
-#define CAN1_RXIMR4                              CAN_RXIMR_REG(CAN1,4)
-#define CAN1_RXIMR5                              CAN_RXIMR_REG(CAN1,5)
-#define CAN1_RXIMR6                              CAN_RXIMR_REG(CAN1,6)
-#define CAN1_RXIMR7                              CAN_RXIMR_REG(CAN1,7)
-#define CAN1_RXIMR8                              CAN_RXIMR_REG(CAN1,8)
-#define CAN1_RXIMR9                              CAN_RXIMR_REG(CAN1,9)
-#define CAN1_RXIMR10                             CAN_RXIMR_REG(CAN1,10)
-#define CAN1_RXIMR11                             CAN_RXIMR_REG(CAN1,11)
-#define CAN1_RXIMR12                             CAN_RXIMR_REG(CAN1,12)
-#define CAN1_RXIMR13                             CAN_RXIMR_REG(CAN1,13)
-#define CAN1_RXIMR14                             CAN_RXIMR_REG(CAN1,14)
-#define CAN1_RXIMR15                             CAN_RXIMR_REG(CAN1,15)
-
-/* CAN - Register array accessors */
-#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
-#define CAN1_CS(index)                           CAN_CS_REG(CAN1,index)
-#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
-#define CAN1_ID(index)                           CAN_ID_REG(CAN1,index)
-#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
-#define CAN1_WORD0(index)                        CAN_WORD0_REG(CAN1,index)
-#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
-#define CAN1_WORD1(index)                        CAN_WORD1_REG(CAN1,index)
-#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
-#define CAN1_RXIMR(index)                        CAN_RXIMR_REG(CAN1,index)
-
-/*!
- * @}
- */ /* end of group CAN_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group CAN_Peripheral_Access_Layer */
@@ -2451,80 +2587,38 @@ typedef struct {
 typedef struct {
   __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
        uint8_t RESERVED_0[2048];
-  __O  uint32_t LDR_CASR;                          /**< Status register  - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
   __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
   __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
        uint8_t RESERVED_1[20];
-  __I  uint32_t STR_CASR;                          /**< Status register  - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
   __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
   __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
        uint8_t RESERVED_2[20];
-  __O  uint32_t ADR_CASR;                          /**< Status register  - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
   __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
   __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
        uint8_t RESERVED_3[20];
-  __O  uint32_t RADR_CASR;                         /**< Status register  - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
   __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
   __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
        uint8_t RESERVED_4[84];
-  __O  uint32_t XOR_CASR;                          /**< Status register  - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
   __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
   __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
        uint8_t RESERVED_5[20];
-  __O  uint32_t ROTL_CASR;                         /**< Status register  - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
   __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
   __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
        uint8_t RESERVED_6[276];
-  __O  uint32_t AESC_CASR;                         /**< Status register  - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
   __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
   __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
        uint8_t RESERVED_7[20];
-  __O  uint32_t AESIC_CASR;                        /**< Status register  - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
   __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
   __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
-} CAU_Type, *CAU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- CAU - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
- * @{
- */
-
-
-/* CAU - Register accessors */
-#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
-#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
-#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
-#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
-#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
-#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
-#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
-#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
-#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
-#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
-#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
-#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
-#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
-#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
-#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
-#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
-#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
-#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
-#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
-#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
-#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
-#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
-#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
-#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
-#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
-
-/*!
- * @}
- */ /* end of group CAU_Register_Accessor_Macros */
-
+} CAU_Type;
 
 /* ----------------------------------------------------------------------------
    -- CAU Register Masks
@@ -2535,375 +2629,443 @@ typedef struct {
  * @{
  */
 
-/* DIRECT Bit Fields */
-#define CAU_DIRECT_CAU_DIRECT0_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT0_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
-#define CAU_DIRECT_CAU_DIRECT1_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT1_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
-#define CAU_DIRECT_CAU_DIRECT2_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT2_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
-#define CAU_DIRECT_CAU_DIRECT3_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT3_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
-#define CAU_DIRECT_CAU_DIRECT4_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT4_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
-#define CAU_DIRECT_CAU_DIRECT5_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT5_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
-#define CAU_DIRECT_CAU_DIRECT6_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT6_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
-#define CAU_DIRECT_CAU_DIRECT7_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT7_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
-#define CAU_DIRECT_CAU_DIRECT8_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT8_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
-#define CAU_DIRECT_CAU_DIRECT9_MASK              0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT9_SHIFT             0
-#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
-#define CAU_DIRECT_CAU_DIRECT10_MASK             0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT10_SHIFT            0
-#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
-#define CAU_DIRECT_CAU_DIRECT11_MASK             0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT11_SHIFT            0
-#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
-#define CAU_DIRECT_CAU_DIRECT12_MASK             0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT12_SHIFT            0
-#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
-#define CAU_DIRECT_CAU_DIRECT13_MASK             0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT13_SHIFT            0
-#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
-#define CAU_DIRECT_CAU_DIRECT14_MASK             0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT14_SHIFT            0
-#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
-#define CAU_DIRECT_CAU_DIRECT15_MASK             0xFFFFFFFFu
-#define CAU_DIRECT_CAU_DIRECT15_SHIFT            0
-#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
-/* LDR_CASR Bit Fields */
-#define CAU_LDR_CASR_IC_MASK                     0x1u
-#define CAU_LDR_CASR_IC_SHIFT                    0
-#define CAU_LDR_CASR_DPE_MASK                    0x2u
-#define CAU_LDR_CASR_DPE_SHIFT                   1
-#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
-#define CAU_LDR_CASR_VER_SHIFT                   28
-#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
-/* LDR_CAA Bit Fields */
-#define CAU_LDR_CAA_ACC_MASK                     0xFFFFFFFFu
-#define CAU_LDR_CAA_ACC_SHIFT                    0
-#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
-/* LDR_CA Bit Fields */
-#define CAU_LDR_CA_CA0_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA0_SHIFT                     0
-#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
-#define CAU_LDR_CA_CA1_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA1_SHIFT                     0
-#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
-#define CAU_LDR_CA_CA2_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA2_SHIFT                     0
-#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
-#define CAU_LDR_CA_CA3_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA3_SHIFT                     0
-#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
-#define CAU_LDR_CA_CA4_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA4_SHIFT                     0
-#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
-#define CAU_LDR_CA_CA5_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA5_SHIFT                     0
-#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
-#define CAU_LDR_CA_CA6_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA6_SHIFT                     0
-#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
-#define CAU_LDR_CA_CA7_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA7_SHIFT                     0
-#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
-#define CAU_LDR_CA_CA8_MASK                      0xFFFFFFFFu
-#define CAU_LDR_CA_CA8_SHIFT                     0
-#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
-/* STR_CASR Bit Fields */
-#define CAU_STR_CASR_IC_MASK                     0x1u
-#define CAU_STR_CASR_IC_SHIFT                    0
-#define CAU_STR_CASR_DPE_MASK                    0x2u
-#define CAU_STR_CASR_DPE_SHIFT                   1
-#define CAU_STR_CASR_VER_MASK                    0xF0000000u
-#define CAU_STR_CASR_VER_SHIFT                   28
-#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
-/* STR_CAA Bit Fields */
-#define CAU_STR_CAA_ACC_MASK                     0xFFFFFFFFu
-#define CAU_STR_CAA_ACC_SHIFT                    0
-#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
-/* STR_CA Bit Fields */
-#define CAU_STR_CA_CA0_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA0_SHIFT                     0
-#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
-#define CAU_STR_CA_CA1_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA1_SHIFT                     0
-#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
-#define CAU_STR_CA_CA2_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA2_SHIFT                     0
-#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
-#define CAU_STR_CA_CA3_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA3_SHIFT                     0
-#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
-#define CAU_STR_CA_CA4_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA4_SHIFT                     0
-#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
-#define CAU_STR_CA_CA5_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA5_SHIFT                     0
-#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
-#define CAU_STR_CA_CA6_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA6_SHIFT                     0
-#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
-#define CAU_STR_CA_CA7_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA7_SHIFT                     0
-#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
-#define CAU_STR_CA_CA8_MASK                      0xFFFFFFFFu
-#define CAU_STR_CA_CA8_SHIFT                     0
-#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
-/* ADR_CASR Bit Fields */
-#define CAU_ADR_CASR_IC_MASK                     0x1u
-#define CAU_ADR_CASR_IC_SHIFT                    0
-#define CAU_ADR_CASR_DPE_MASK                    0x2u
-#define CAU_ADR_CASR_DPE_SHIFT                   1
-#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
-#define CAU_ADR_CASR_VER_SHIFT                   28
-#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
-/* ADR_CAA Bit Fields */
-#define CAU_ADR_CAA_ACC_MASK                     0xFFFFFFFFu
-#define CAU_ADR_CAA_ACC_SHIFT                    0
-#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
-/* ADR_CA Bit Fields */
-#define CAU_ADR_CA_CA0_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA0_SHIFT                     0
-#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
-#define CAU_ADR_CA_CA1_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA1_SHIFT                     0
-#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
-#define CAU_ADR_CA_CA2_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA2_SHIFT                     0
-#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
-#define CAU_ADR_CA_CA3_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA3_SHIFT                     0
-#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
-#define CAU_ADR_CA_CA4_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA4_SHIFT                     0
-#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
-#define CAU_ADR_CA_CA5_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA5_SHIFT                     0
-#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
-#define CAU_ADR_CA_CA6_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA6_SHIFT                     0
-#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
-#define CAU_ADR_CA_CA7_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA7_SHIFT                     0
-#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
-#define CAU_ADR_CA_CA8_MASK                      0xFFFFFFFFu
-#define CAU_ADR_CA_CA8_SHIFT                     0
-#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
-/* RADR_CASR Bit Fields */
-#define CAU_RADR_CASR_IC_MASK                    0x1u
-#define CAU_RADR_CASR_IC_SHIFT                   0
-#define CAU_RADR_CASR_DPE_MASK                   0x2u
-#define CAU_RADR_CASR_DPE_SHIFT                  1
-#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
-#define CAU_RADR_CASR_VER_SHIFT                  28
-#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
-/* RADR_CAA Bit Fields */
-#define CAU_RADR_CAA_ACC_MASK                    0xFFFFFFFFu
-#define CAU_RADR_CAA_ACC_SHIFT                   0
-#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
-/* RADR_CA Bit Fields */
-#define CAU_RADR_CA_CA0_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA0_SHIFT                    0
-#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
-#define CAU_RADR_CA_CA1_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA1_SHIFT                    0
-#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
-#define CAU_RADR_CA_CA2_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA2_SHIFT                    0
-#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
-#define CAU_RADR_CA_CA3_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA3_SHIFT                    0
-#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
-#define CAU_RADR_CA_CA4_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA4_SHIFT                    0
-#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
-#define CAU_RADR_CA_CA5_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA5_SHIFT                    0
-#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
-#define CAU_RADR_CA_CA6_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA6_SHIFT                    0
-#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
-#define CAU_RADR_CA_CA7_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA7_SHIFT                    0
-#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
-#define CAU_RADR_CA_CA8_MASK                     0xFFFFFFFFu
-#define CAU_RADR_CA_CA8_SHIFT                    0
-#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
-/* XOR_CASR Bit Fields */
-#define CAU_XOR_CASR_IC_MASK                     0x1u
-#define CAU_XOR_CASR_IC_SHIFT                    0
-#define CAU_XOR_CASR_DPE_MASK                    0x2u
-#define CAU_XOR_CASR_DPE_SHIFT                   1
-#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
-#define CAU_XOR_CASR_VER_SHIFT                   28
-#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
-/* XOR_CAA Bit Fields */
-#define CAU_XOR_CAA_ACC_MASK                     0xFFFFFFFFu
-#define CAU_XOR_CAA_ACC_SHIFT                    0
-#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
-/* XOR_CA Bit Fields */
-#define CAU_XOR_CA_CA0_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA0_SHIFT                     0
-#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
-#define CAU_XOR_CA_CA1_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA1_SHIFT                     0
-#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
-#define CAU_XOR_CA_CA2_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA2_SHIFT                     0
-#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
-#define CAU_XOR_CA_CA3_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA3_SHIFT                     0
-#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
-#define CAU_XOR_CA_CA4_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA4_SHIFT                     0
-#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
-#define CAU_XOR_CA_CA5_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA5_SHIFT                     0
-#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
-#define CAU_XOR_CA_CA6_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA6_SHIFT                     0
-#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
-#define CAU_XOR_CA_CA7_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA7_SHIFT                     0
-#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
-#define CAU_XOR_CA_CA8_MASK                      0xFFFFFFFFu
-#define CAU_XOR_CA_CA8_SHIFT                     0
-#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
-/* ROTL_CASR Bit Fields */
-#define CAU_ROTL_CASR_IC_MASK                    0x1u
-#define CAU_ROTL_CASR_IC_SHIFT                   0
-#define CAU_ROTL_CASR_DPE_MASK                   0x2u
-#define CAU_ROTL_CASR_DPE_SHIFT                  1
-#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
-#define CAU_ROTL_CASR_VER_SHIFT                  28
-#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
-/* ROTL_CAA Bit Fields */
-#define CAU_ROTL_CAA_ACC_MASK                    0xFFFFFFFFu
-#define CAU_ROTL_CAA_ACC_SHIFT                   0
-#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
-/* ROTL_CA Bit Fields */
-#define CAU_ROTL_CA_CA0_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA0_SHIFT                    0
-#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
-#define CAU_ROTL_CA_CA1_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA1_SHIFT                    0
-#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
-#define CAU_ROTL_CA_CA2_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA2_SHIFT                    0
-#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
-#define CAU_ROTL_CA_CA3_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA3_SHIFT                    0
-#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
-#define CAU_ROTL_CA_CA4_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA4_SHIFT                    0
-#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
-#define CAU_ROTL_CA_CA5_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA5_SHIFT                    0
-#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
-#define CAU_ROTL_CA_CA6_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA6_SHIFT                    0
-#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
-#define CAU_ROTL_CA_CA7_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA7_SHIFT                    0
-#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
-#define CAU_ROTL_CA_CA8_MASK                     0xFFFFFFFFu
-#define CAU_ROTL_CA_CA8_SHIFT                    0
-#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
-/* AESC_CASR Bit Fields */
-#define CAU_AESC_CASR_IC_MASK                    0x1u
-#define CAU_AESC_CASR_IC_SHIFT                   0
-#define CAU_AESC_CASR_DPE_MASK                   0x2u
-#define CAU_AESC_CASR_DPE_SHIFT                  1
-#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
-#define CAU_AESC_CASR_VER_SHIFT                  28
-#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
-/* AESC_CAA Bit Fields */
-#define CAU_AESC_CAA_ACC_MASK                    0xFFFFFFFFu
-#define CAU_AESC_CAA_ACC_SHIFT                   0
-#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
-/* AESC_CA Bit Fields */
-#define CAU_AESC_CA_CA0_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA0_SHIFT                    0
-#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
-#define CAU_AESC_CA_CA1_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA1_SHIFT                    0
-#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
-#define CAU_AESC_CA_CA2_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA2_SHIFT                    0
-#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
-#define CAU_AESC_CA_CA3_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA3_SHIFT                    0
-#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
-#define CAU_AESC_CA_CA4_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA4_SHIFT                    0
-#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
-#define CAU_AESC_CA_CA5_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA5_SHIFT                    0
-#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
-#define CAU_AESC_CA_CA6_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA6_SHIFT                    0
-#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
-#define CAU_AESC_CA_CA7_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA7_SHIFT                    0
-#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
-#define CAU_AESC_CA_CA8_MASK                     0xFFFFFFFFu
-#define CAU_AESC_CA_CA8_SHIFT                    0
-#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
-/* AESIC_CASR Bit Fields */
-#define CAU_AESIC_CASR_IC_MASK                   0x1u
-#define CAU_AESIC_CASR_IC_SHIFT                  0
-#define CAU_AESIC_CASR_DPE_MASK                  0x2u
-#define CAU_AESIC_CASR_DPE_SHIFT                 1
-#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
-#define CAU_AESIC_CASR_VER_SHIFT                 28
-#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
-/* AESIC_CAA Bit Fields */
-#define CAU_AESIC_CAA_ACC_MASK                   0xFFFFFFFFu
-#define CAU_AESIC_CAA_ACC_SHIFT                  0
-#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
-/* AESIC_CA Bit Fields */
-#define CAU_AESIC_CA_CA0_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA0_SHIFT                   0
-#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
-#define CAU_AESIC_CA_CA1_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA1_SHIFT                   0
-#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
-#define CAU_AESIC_CA_CA2_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA2_SHIFT                   0
-#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
-#define CAU_AESIC_CA_CA3_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA3_SHIFT                   0
-#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
-#define CAU_AESIC_CA_CA4_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA4_SHIFT                   0
-#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
-#define CAU_AESIC_CA_CA5_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA5_SHIFT                   0
-#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
-#define CAU_AESIC_CA_CA6_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA6_SHIFT                   0
-#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
-#define CAU_AESIC_CA_CA7_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA7_SHIFT                   0
-#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
-#define CAU_AESIC_CA_CA8_MASK                    0xFFFFFFFFu
-#define CAU_AESIC_CA_CA8_SHIFT                   0
-#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+/*! @name DIRECT - Direct access register 0..Direct access register 15 */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
+
+/* The count of CAU_DIRECT */
+#define CAU_DIRECT_COUNT                         (16U)
+
+/*! @name LDR_CASR - Status register - Load Register command */
+#define CAU_LDR_CASR_IC_MASK                     (0x1U)
+#define CAU_LDR_CASR_IC_SHIFT                    (0U)
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    (0x2U)
+#define CAU_LDR_CASR_DPE_SHIFT                   (1U)
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_LDR_CASR_VER_SHIFT                   (28U)
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
+
+/*! @name LDR_CAA - Accumulator register - Load Register command */
+#define CAU_LDR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_LDR_CAA_ACC_SHIFT                    (0U)
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
+
+/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
+#define CAU_LDR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA0_SHIFT                     (0U)
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA1_SHIFT                     (0U)
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA2_SHIFT                     (0U)
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA3_SHIFT                     (0U)
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA4_SHIFT                     (0U)
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA5_SHIFT                     (0U)
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA6_SHIFT                     (0U)
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA7_SHIFT                     (0U)
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA8_SHIFT                     (0U)
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
+
+/* The count of CAU_LDR_CA */
+#define CAU_LDR_CA_COUNT                         (9U)
+
+/*! @name STR_CASR - Status register - Store Register command */
+#define CAU_STR_CASR_IC_MASK                     (0x1U)
+#define CAU_STR_CASR_IC_SHIFT                    (0U)
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    (0x2U)
+#define CAU_STR_CASR_DPE_SHIFT                   (1U)
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_STR_CASR_VER_SHIFT                   (28U)
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
+
+/*! @name STR_CAA - Accumulator register - Store Register command */
+#define CAU_STR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_STR_CAA_ACC_SHIFT                    (0U)
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
+
+/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
+#define CAU_STR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA0_SHIFT                     (0U)
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA1_SHIFT                     (0U)
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA2_SHIFT                     (0U)
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA3_SHIFT                     (0U)
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA4_SHIFT                     (0U)
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA5_SHIFT                     (0U)
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA6_SHIFT                     (0U)
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA7_SHIFT                     (0U)
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA8_SHIFT                     (0U)
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
+
+/* The count of CAU_STR_CA */
+#define CAU_STR_CA_COUNT                         (9U)
+
+/*! @name ADR_CASR - Status register - Add Register command */
+#define CAU_ADR_CASR_IC_MASK                     (0x1U)
+#define CAU_ADR_CASR_IC_SHIFT                    (0U)
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    (0x2U)
+#define CAU_ADR_CASR_DPE_SHIFT                   (1U)
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_ADR_CASR_VER_SHIFT                   (28U)
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
+
+/*! @name ADR_CAA - Accumulator register - Add to register command */
+#define CAU_ADR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_ADR_CAA_ACC_SHIFT                    (0U)
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
+
+/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
+#define CAU_ADR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA0_SHIFT                     (0U)
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA1_SHIFT                     (0U)
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA2_SHIFT                     (0U)
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA3_SHIFT                     (0U)
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA4_SHIFT                     (0U)
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA5_SHIFT                     (0U)
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA6_SHIFT                     (0U)
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA7_SHIFT                     (0U)
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA8_SHIFT                     (0U)
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
+
+/* The count of CAU_ADR_CA */
+#define CAU_ADR_CA_COUNT                         (9U)
+
+/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
+#define CAU_RADR_CASR_IC_MASK                    (0x1U)
+#define CAU_RADR_CASR_IC_SHIFT                   (0U)
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   (0x2U)
+#define CAU_RADR_CASR_DPE_SHIFT                  (1U)
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_RADR_CASR_VER_SHIFT                  (28U)
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
+
+/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
+#define CAU_RADR_CAA_ACC_MASK                    (0xFFFFFFFFU)
+#define CAU_RADR_CAA_ACC_SHIFT                   (0U)
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
+
+/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
+#define CAU_RADR_CA_CA0_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA0_SHIFT                    (0U)
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA1_SHIFT                    (0U)
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA2_SHIFT                    (0U)
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA3_SHIFT                    (0U)
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA4_SHIFT                    (0U)
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA5_SHIFT                    (0U)
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA6_SHIFT                    (0U)
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA7_SHIFT                    (0U)
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA8_SHIFT                    (0U)
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
+
+/* The count of CAU_RADR_CA */
+#define CAU_RADR_CA_COUNT                        (9U)
+
+/*! @name XOR_CASR - Status register - Exclusive Or command */
+#define CAU_XOR_CASR_IC_MASK                     (0x1U)
+#define CAU_XOR_CASR_IC_SHIFT                    (0U)
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    (0x2U)
+#define CAU_XOR_CASR_DPE_SHIFT                   (1U)
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_XOR_CASR_VER_SHIFT                   (28U)
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
+
+/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
+#define CAU_XOR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_XOR_CAA_ACC_SHIFT                    (0U)
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
+
+/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
+#define CAU_XOR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA0_SHIFT                     (0U)
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA1_SHIFT                     (0U)
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA2_SHIFT                     (0U)
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA3_SHIFT                     (0U)
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA4_SHIFT                     (0U)
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA5_SHIFT                     (0U)
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA6_SHIFT                     (0U)
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA7_SHIFT                     (0U)
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA8_SHIFT                     (0U)
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
+
+/* The count of CAU_XOR_CA */
+#define CAU_XOR_CA_COUNT                         (9U)
+
+/*! @name ROTL_CASR - Status register - Rotate Left command */
+#define CAU_ROTL_CASR_IC_MASK                    (0x1U)
+#define CAU_ROTL_CASR_IC_SHIFT                   (0U)
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   (0x2U)
+#define CAU_ROTL_CASR_DPE_SHIFT                  (1U)
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_ROTL_CASR_VER_SHIFT                  (28U)
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
+
+/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
+#define CAU_ROTL_CAA_ACC_MASK                    (0xFFFFFFFFU)
+#define CAU_ROTL_CAA_ACC_SHIFT                   (0U)
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
+
+/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
+#define CAU_ROTL_CA_CA0_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA0_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA1_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA2_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA3_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA4_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA5_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA6_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA7_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA8_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
+
+/* The count of CAU_ROTL_CA */
+#define CAU_ROTL_CA_COUNT                        (9U)
+
+/*! @name AESC_CASR - Status register - AES Column Operation command */
+#define CAU_AESC_CASR_IC_MASK                    (0x1U)
+#define CAU_AESC_CASR_IC_SHIFT                   (0U)
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   (0x2U)
+#define CAU_AESC_CASR_DPE_SHIFT                  (1U)
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_AESC_CASR_VER_SHIFT                  (28U)
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
+
+/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
+#define CAU_AESC_CAA_ACC_MASK                    (0xFFFFFFFFU)
+#define CAU_AESC_CAA_ACC_SHIFT                   (0U)
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
+
+/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
+#define CAU_AESC_CA_CA0_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA0_SHIFT                    (0U)
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA1_SHIFT                    (0U)
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA2_SHIFT                    (0U)
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA3_SHIFT                    (0U)
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA4_SHIFT                    (0U)
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA5_SHIFT                    (0U)
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA6_SHIFT                    (0U)
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA7_SHIFT                    (0U)
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA8_SHIFT                    (0U)
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
+
+/* The count of CAU_AESC_CA */
+#define CAU_AESC_CA_COUNT                        (9U)
+
+/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
+#define CAU_AESIC_CASR_IC_MASK                   (0x1U)
+#define CAU_AESIC_CASR_IC_SHIFT                  (0U)
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  (0x2U)
+#define CAU_AESIC_CASR_DPE_SHIFT                 (1U)
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  (0xF0000000U)
+#define CAU_AESIC_CASR_VER_SHIFT                 (28U)
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
+
+/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
+#define CAU_AESIC_CAA_ACC_MASK                   (0xFFFFFFFFU)
+#define CAU_AESIC_CAA_ACC_SHIFT                  (0U)
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
+
+/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
+#define CAU_AESIC_CA_CA0_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA0_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA1_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA2_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA3_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA4_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA5_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA6_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA7_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA8_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
+
+/* The count of CAU_AESIC_CA */
+#define CAU_AESIC_CA_COUNT                       (9U)
+
 
 /*!
  * @}
@@ -2915,145 +3077,11 @@ typedef struct {
 #define CAU_BASE                                 (0xE0081000u)
 /** Peripheral CAU base pointer */
 #define CAU                                      ((CAU_Type *)CAU_BASE)
-#define CAU_BASE_PTR                             (CAU)
 /** Array initializer of CAU peripheral base addresses */
 #define CAU_BASE_ADDRS                           { CAU_BASE }
 /** Array initializer of CAU peripheral base pointers */
 #define CAU_BASE_PTRS                            { CAU }
 
-/* ----------------------------------------------------------------------------
-   -- CAU - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
- * @{
- */
-
-
-/* CAU - Register instance definitions */
-/* CAU */
-#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
-#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
-#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
-#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
-#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
-#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
-#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
-#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
-#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
-#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
-#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
-#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
-#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
-#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
-#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
-#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
-#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
-#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
-#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
-#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
-#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
-#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
-#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
-#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
-#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
-#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
-#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
-#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
-#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
-#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
-#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
-#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
-#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
-#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
-#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
-#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
-#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
-#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
-#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
-#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
-#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
-#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
-#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
-#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
-#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
-#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
-#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
-#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
-#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
-#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
-#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
-#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
-#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
-#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
-#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
-#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
-#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
-#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
-#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
-#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
-#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
-#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
-#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
-#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
-#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
-#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
-#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
-#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
-#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
-#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
-#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
-#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
-#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
-#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
-#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
-#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
-#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
-#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
-#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
-#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
-#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
-#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
-#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
-#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
-#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
-#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
-#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
-#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
-#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
-#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
-#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
-#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
-#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
-#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
-#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
-#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
-#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
-#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
-#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
-#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
-#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
-#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
-#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
-#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
-
-/* CAU - Register array accessors */
-#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
-#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
-#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
-#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
-#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
-#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
-#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
-#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
-#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
-
-/*!
- * @}
- */ /* end of group CAU_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group CAU_Peripheral_Access_Layer */
@@ -3076,30 +3104,7 @@ typedef struct {
   __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
   __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
   __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
-} CMP_Type, *CMP_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- CMP - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register accessors */
-#define CMP_CR0_REG(base)                        ((base)->CR0)
-#define CMP_CR1_REG(base)                        ((base)->CR1)
-#define CMP_FPR_REG(base)                        ((base)->FPR)
-#define CMP_SCR_REG(base)                        ((base)->SCR)
-#define CMP_DACCR_REG(base)                      ((base)->DACCR)
-#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
+} CMP_Type;
 
 /* ----------------------------------------------------------------------------
    -- CMP Register Masks
@@ -3110,62 +3115,84 @@ typedef struct {
  * @{
  */
 
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK                     0x3u
-#define CMP_CR0_HYSTCTR_SHIFT                    0
-#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK                  0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT                 4
-#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK                          0x1u
-#define CMP_CR1_EN_SHIFT                         0
-#define CMP_CR1_OPE_MASK                         0x2u
-#define CMP_CR1_OPE_SHIFT                        1
-#define CMP_CR1_COS_MASK                         0x4u
-#define CMP_CR1_COS_SHIFT                        2
-#define CMP_CR1_INV_MASK                         0x8u
-#define CMP_CR1_INV_SHIFT                        3
-#define CMP_CR1_PMODE_MASK                       0x10u
-#define CMP_CR1_PMODE_SHIFT                      4
-#define CMP_CR1_WE_MASK                          0x40u
-#define CMP_CR1_WE_SHIFT                         6
-#define CMP_CR1_SE_MASK                          0x80u
-#define CMP_CR1_SE_SHIFT                         7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK                    0xFFu
-#define CMP_FPR_FILT_PER_SHIFT                   0
-#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK                        0x1u
-#define CMP_SCR_COUT_SHIFT                       0
-#define CMP_SCR_CFF_MASK                         0x2u
-#define CMP_SCR_CFF_SHIFT                        1
-#define CMP_SCR_CFR_MASK                         0x4u
-#define CMP_SCR_CFR_SHIFT                        2
-#define CMP_SCR_IEF_MASK                         0x8u
-#define CMP_SCR_IEF_SHIFT                        3
-#define CMP_SCR_IER_MASK                         0x10u
-#define CMP_SCR_IER_SHIFT                        4
-#define CMP_SCR_DMAEN_MASK                       0x40u
-#define CMP_SCR_DMAEN_SHIFT                      6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK                     0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT                    0
-#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK                     0x40u
-#define CMP_DACCR_VRSEL_SHIFT                    6
-#define CMP_DACCR_DACEN_MASK                     0x80u
-#define CMP_DACCR_DACEN_SHIFT                    7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK                      0x7u
-#define CMP_MUXCR_MSEL_SHIFT                     0
-#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK                      0x38u
-#define CMP_MUXCR_PSEL_SHIFT                     3
-#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-#define CMP_MUXCR_PSTM_MASK                      0x40u
-#define CMP_MUXCR_PSTM_SHIFT                     6
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK                     (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT                    (0U)
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK                          (0x1U)
+#define CMP_CR1_EN_SHIFT                         (0U)
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         (0x2U)
+#define CMP_CR1_OPE_SHIFT                        (1U)
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         (0x4U)
+#define CMP_CR1_COS_SHIFT                        (2U)
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         (0x8U)
+#define CMP_CR1_INV_SHIFT                        (3U)
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       (0x10U)
+#define CMP_CR1_PMODE_SHIFT                      (4U)
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK                          (0x40U)
+#define CMP_CR1_WE_SHIFT                         (6U)
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          (0x80U)
+#define CMP_CR1_SE_SHIFT                         (7U)
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK                    (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT                   (0U)
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK                        (0x1U)
+#define CMP_SCR_COUT_SHIFT                       (0U)
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         (0x2U)
+#define CMP_SCR_CFF_SHIFT                        (1U)
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         (0x4U)
+#define CMP_SCR_CFR_SHIFT                        (2U)
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         (0x8U)
+#define CMP_SCR_IEF_SHIFT                        (3U)
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         (0x10U)
+#define CMP_SCR_IER_SHIFT                        (4U)
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       (0x40U)
+#define CMP_SCR_DMAEN_SHIFT                      (6U)
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK                     (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT                    (0U)
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT                    (6U)
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     (0x80U)
+#define CMP_DACCR_DACEN_SHIFT                    (7U)
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK                      (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT                     (0U)
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT                     (3U)
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      (0x40U)
+#define CMP_MUXCR_PSTM_SHIFT                     (6U)
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+
 
 /*!
  * @}
@@ -3177,17 +3204,14 @@ typedef struct {
 #define CMP0_BASE                                (0x40073000u)
 /** Peripheral CMP0 base pointer */
 #define CMP0                                     ((CMP_Type *)CMP0_BASE)
-#define CMP0_BASE_PTR                            (CMP0)
 /** Peripheral CMP1 base address */
 #define CMP1_BASE                                (0x40073008u)
 /** Peripheral CMP1 base pointer */
 #define CMP1                                     ((CMP_Type *)CMP1_BASE)
-#define CMP1_BASE_PTR                            (CMP1)
 /** Peripheral CMP2 base address */
 #define CMP2_BASE                                (0x40073010u)
 /** Peripheral CMP2 base pointer */
 #define CMP2                                     ((CMP_Type *)CMP2_BASE)
-#define CMP2_BASE_PTR                            (CMP2)
 /** Array initializer of CMP peripheral base addresses */
 #define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
 /** Array initializer of CMP peripheral base pointers */
@@ -3195,44 +3219,6 @@ typedef struct {
 /** Interrupt vectors for the CMP peripheral type */
 #define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- CMP - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register instance definitions */
-/* CMP0 */
-#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
-#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
-#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
-#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
-#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
-#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
-/* CMP1 */
-#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
-#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
-#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
-#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
-#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
-#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
-/* CMP2 */
-#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
-#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
-#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
-#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
-#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
-#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group CMP_Peripheral_Access_Layer */
@@ -3261,36 +3247,7 @@ typedef struct {
   __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
   __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
   __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
-} CMT_Type, *CMT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- CMT - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
- * @{
- */
-
-
-/* CMT - Register accessors */
-#define CMT_CGH1_REG(base)                       ((base)->CGH1)
-#define CMT_CGL1_REG(base)                       ((base)->CGL1)
-#define CMT_CGH2_REG(base)                       ((base)->CGH2)
-#define CMT_CGL2_REG(base)                       ((base)->CGL2)
-#define CMT_OC_REG(base)                         ((base)->OC)
-#define CMT_MSC_REG(base)                        ((base)->MSC)
-#define CMT_CMD1_REG(base)                       ((base)->CMD1)
-#define CMT_CMD2_REG(base)                       ((base)->CMD2)
-#define CMT_CMD3_REG(base)                       ((base)->CMD3)
-#define CMT_CMD4_REG(base)                       ((base)->CMD4)
-#define CMT_PPS_REG(base)                        ((base)->PPS)
-#define CMT_DMA_REG(base)                        ((base)->DMA)
-
-/*!
- * @}
- */ /* end of group CMT_Register_Accessor_Macros */
-
+} CMT_Type;
 
 /* ----------------------------------------------------------------------------
    -- CMT Register Masks
@@ -3301,68 +3258,90 @@ typedef struct {
  * @{
  */
 
-/* CGH1 Bit Fields */
-#define CMT_CGH1_PH_MASK                         0xFFu
-#define CMT_CGH1_PH_SHIFT                        0
-#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
-/* CGL1 Bit Fields */
-#define CMT_CGL1_PL_MASK                         0xFFu
-#define CMT_CGL1_PL_SHIFT                        0
-#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
-/* CGH2 Bit Fields */
-#define CMT_CGH2_SH_MASK                         0xFFu
-#define CMT_CGH2_SH_SHIFT                        0
-#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
-/* CGL2 Bit Fields */
-#define CMT_CGL2_SL_MASK                         0xFFu
-#define CMT_CGL2_SL_SHIFT                        0
-#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
-/* OC Bit Fields */
-#define CMT_OC_IROPEN_MASK                       0x20u
-#define CMT_OC_IROPEN_SHIFT                      5
-#define CMT_OC_CMTPOL_MASK                       0x40u
-#define CMT_OC_CMTPOL_SHIFT                      6
-#define CMT_OC_IROL_MASK                         0x80u
-#define CMT_OC_IROL_SHIFT                        7
-/* MSC Bit Fields */
-#define CMT_MSC_MCGEN_MASK                       0x1u
-#define CMT_MSC_MCGEN_SHIFT                      0
-#define CMT_MSC_EOCIE_MASK                       0x2u
-#define CMT_MSC_EOCIE_SHIFT                      1
-#define CMT_MSC_FSK_MASK                         0x4u
-#define CMT_MSC_FSK_SHIFT                        2
-#define CMT_MSC_BASE_MASK                        0x8u
-#define CMT_MSC_BASE_SHIFT                       3
-#define CMT_MSC_EXSPC_MASK                       0x10u
-#define CMT_MSC_EXSPC_SHIFT                      4
-#define CMT_MSC_CMTDIV_MASK                      0x60u
-#define CMT_MSC_CMTDIV_SHIFT                     5
-#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
-#define CMT_MSC_EOCF_MASK                        0x80u
-#define CMT_MSC_EOCF_SHIFT                       7
-/* CMD1 Bit Fields */
-#define CMT_CMD1_MB_MASK                         0xFFu
-#define CMT_CMD1_MB_SHIFT                        0
-#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
-/* CMD2 Bit Fields */
-#define CMT_CMD2_MB_MASK                         0xFFu
-#define CMT_CMD2_MB_SHIFT                        0
-#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
-/* CMD3 Bit Fields */
-#define CMT_CMD3_SB_MASK                         0xFFu
-#define CMT_CMD3_SB_SHIFT                        0
-#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
-/* CMD4 Bit Fields */
-#define CMT_CMD4_SB_MASK                         0xFFu
-#define CMT_CMD4_SB_SHIFT                        0
-#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
-/* PPS Bit Fields */
-#define CMT_PPS_PPSDIV_MASK                      0xFu
-#define CMT_PPS_PPSDIV_SHIFT                     0
-#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
-/* DMA Bit Fields */
-#define CMT_DMA_DMA_MASK                         0x1u
-#define CMT_DMA_DMA_SHIFT                        0
+/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
+#define CMT_CGH1_PH_MASK                         (0xFFU)
+#define CMT_CGH1_PH_SHIFT                        (0U)
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+
+/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
+#define CMT_CGL1_PL_MASK                         (0xFFU)
+#define CMT_CGL1_PL_SHIFT                        (0U)
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+
+/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
+#define CMT_CGH2_SH_MASK                         (0xFFU)
+#define CMT_CGH2_SH_SHIFT                        (0U)
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+
+/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
+#define CMT_CGL2_SL_MASK                         (0xFFU)
+#define CMT_CGL2_SL_SHIFT                        (0U)
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+
+/*! @name OC - CMT Output Control Register */
+#define CMT_OC_IROPEN_MASK                       (0x20U)
+#define CMT_OC_IROPEN_SHIFT                      (5U)
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       (0x40U)
+#define CMT_OC_CMTPOL_SHIFT                      (6U)
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         (0x80U)
+#define CMT_OC_IROL_SHIFT                        (7U)
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
+
+/*! @name MSC - CMT Modulator Status and Control Register */
+#define CMT_MSC_MCGEN_MASK                       (0x1U)
+#define CMT_MSC_MCGEN_SHIFT                      (0U)
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       (0x2U)
+#define CMT_MSC_EOCIE_SHIFT                      (1U)
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         (0x4U)
+#define CMT_MSC_FSK_SHIFT                        (2U)
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        (0x8U)
+#define CMT_MSC_BASE_SHIFT                       (3U)
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       (0x10U)
+#define CMT_MSC_EXSPC_SHIFT                      (4U)
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      (0x60U)
+#define CMT_MSC_CMTDIV_SHIFT                     (5U)
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        (0x80U)
+#define CMT_MSC_EOCF_SHIFT                       (7U)
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
+
+/*! @name CMD1 - CMT Modulator Data Register Mark High */
+#define CMT_CMD1_MB_MASK                         (0xFFU)
+#define CMT_CMD1_MB_SHIFT                        (0U)
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+
+/*! @name CMD2 - CMT Modulator Data Register Mark Low */
+#define CMT_CMD2_MB_MASK                         (0xFFU)
+#define CMT_CMD2_MB_SHIFT                        (0U)
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+
+/*! @name CMD3 - CMT Modulator Data Register Space High */
+#define CMT_CMD3_SB_MASK                         (0xFFU)
+#define CMT_CMD3_SB_SHIFT                        (0U)
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+
+/*! @name CMD4 - CMT Modulator Data Register Space Low */
+#define CMT_CMD4_SB_MASK                         (0xFFU)
+#define CMT_CMD4_SB_SHIFT                        (0U)
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+
+/*! @name PPS - CMT Primary Prescaler Register */
+#define CMT_PPS_PPSDIV_MASK                      (0xFU)
+#define CMT_PPS_PPSDIV_SHIFT                     (0U)
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+
+/*! @name DMA - CMT Direct Memory Access Register */
+#define CMT_DMA_DMA_MASK                         (0x1U)
+#define CMT_DMA_DMA_SHIFT                        (0U)
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
+
 
 /*!
  * @}
@@ -3374,7 +3353,6 @@ typedef struct {
 #define CMT_BASE                                 (0x40062000u)
 /** Peripheral CMT base pointer */
 #define CMT                                      ((CMT_Type *)CMT_BASE)
-#define CMT_BASE_PTR                             (CMT)
 /** Array initializer of CMT peripheral base addresses */
 #define CMT_BASE_ADDRS                           { CMT_BASE }
 /** Array initializer of CMT peripheral base pointers */
@@ -3382,36 +3360,6 @@ typedef struct {
 /** Interrupt vectors for the CMT peripheral type */
 #define CMT_IRQS                                 { CMT_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- CMT - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
- * @{
- */
-
-
-/* CMT - Register instance definitions */
-/* CMT */
-#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
-#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
-#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
-#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
-#define CMT_OC                                   CMT_OC_REG(CMT)
-#define CMT_MSC                                  CMT_MSC_REG(CMT)
-#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
-#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
-#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
-#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
-#define CMT_PPS                                  CMT_PPS_REG(CMT)
-#define CMT_DMA                                  CMT_DMA_REG(CMT)
-
-/*!
- * @}
- */ /* end of group CMT_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group CMT_Peripheral_Access_Layer */
@@ -3461,40 +3409,7 @@ typedef struct {
       __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
     } CTRL_ACCESS8BIT;
   };
-} CRC_Type, *CRC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- CRC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register accessors */
-#define CRC_CRCL_REG(base)                       ((base)->ACCESS16BIT.CRCL)
-#define CRC_CRCH_REG(base)                       ((base)->ACCESS16BIT.CRCH)
-#define CRC_CRC_REG(base)                        ((base)->CRC)
-#define CRC_CRCLL_REG(base)                      ((base)->ACCESS8BIT.CRCLL)
-#define CRC_CRCLU_REG(base)                      ((base)->ACCESS8BIT.CRCLU)
-#define CRC_CRCHL_REG(base)                      ((base)->ACCESS8BIT.CRCHL)
-#define CRC_CRCHU_REG(base)                      ((base)->ACCESS8BIT.CRCHU)
-#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
-#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
-#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
-#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
-#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
-#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
-#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
-#define CRC_CTRL_REG(base)                       ((base)->CTRL)
-#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
+} CRC_Type;
 
 /* ----------------------------------------------------------------------------
    -- CRC Register Masks
@@ -3505,100 +3420,122 @@ typedef struct {
  * @{
  */
 
-/* CRCL Bit Fields */
-#define CRC_CRCL_CRCL_MASK                       0xFFFFu
-#define CRC_CRCL_CRCL_SHIFT                      0
-#define CRC_CRCL_CRCL(x)                         (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
-/* CRCH Bit Fields */
-#define CRC_CRCH_CRCH_MASK                       0xFFFFu
-#define CRC_CRCH_CRCH_SHIFT                      0
-#define CRC_CRCH_CRCH(x)                         (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
-/* CRC Bit Fields */
-#define CRC_CRC_LL_MASK                          0xFFu
-#define CRC_CRC_LL_SHIFT                         0
-#define CRC_CRC_LL(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
-#define CRC_CRC_LU_MASK                          0xFF00u
-#define CRC_CRC_LU_SHIFT                         8
-#define CRC_CRC_LU(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
-#define CRC_CRC_HL_MASK                          0xFF0000u
-#define CRC_CRC_HL_SHIFT                         16
-#define CRC_CRC_HL(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
-#define CRC_CRC_HU_MASK                          0xFF000000u
-#define CRC_CRC_HU_SHIFT                         24
-#define CRC_CRC_HU(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
-/* CRCLL Bit Fields */
-#define CRC_CRCLL_CRCLL_MASK                     0xFFu
-#define CRC_CRCLL_CRCLL_SHIFT                    0
-#define CRC_CRCLL_CRCLL(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
-/* CRCLU Bit Fields */
-#define CRC_CRCLU_CRCLU_MASK                     0xFFu
-#define CRC_CRCLU_CRCLU_SHIFT                    0
-#define CRC_CRCLU_CRCLU(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
-/* CRCHL Bit Fields */
-#define CRC_CRCHL_CRCHL_MASK                     0xFFu
-#define CRC_CRCHL_CRCHL_SHIFT                    0
-#define CRC_CRCHL_CRCHL(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
-/* CRCHU Bit Fields */
-#define CRC_CRCHU_CRCHU_MASK                     0xFFu
-#define CRC_CRCHU_CRCHU_SHIFT                    0
-#define CRC_CRCHU_CRCHU(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT                  0
-#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT                  0
-#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK                       0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT                      0
-#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT                     16
-#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
-#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
-#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
-#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
-#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK                       0x1000000u
-#define CRC_CTRL_TCRC_SHIFT                      24
-#define CRC_CTRL_WAS_MASK                        0x2000000u
-#define CRC_CTRL_WAS_SHIFT                       25
-#define CRC_CTRL_FXOR_MASK                       0x4000000u
-#define CRC_CTRL_FXOR_SHIFT                      26
-#define CRC_CTRL_TOTR_MASK                       0x30000000u
-#define CRC_CTRL_TOTR_SHIFT                      28
-#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK                        0xC0000000u
-#define CRC_CTRL_TOT_SHIFT                       30
-#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK                     0x1u
-#define CRC_CTRLHU_TCRC_SHIFT                    0
-#define CRC_CTRLHU_WAS_MASK                      0x2u
-#define CRC_CTRLHU_WAS_SHIFT                     1
-#define CRC_CTRLHU_FXOR_MASK                     0x4u
-#define CRC_CTRLHU_FXOR_SHIFT                    2
-#define CRC_CTRLHU_TOTR_MASK                     0x30u
-#define CRC_CTRLHU_TOTR_SHIFT                    4
-#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK                      0xC0u
-#define CRC_CTRLHU_TOT_SHIFT                     6
-#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+/*! @name CRCL - CRC_CRCL register. */
+#define CRC_CRCL_CRCL_MASK                       (0xFFFFU)
+#define CRC_CRCL_CRCL_SHIFT                      (0U)
+#define CRC_CRCL_CRCL(x)                         (((uint16_t)(((uint16_t)(x)) << CRC_CRCL_CRCL_SHIFT)) & CRC_CRCL_CRCL_MASK)
+
+/*! @name CRCH - CRC_CRCH register. */
+#define CRC_CRCH_CRCH_MASK                       (0xFFFFU)
+#define CRC_CRCH_CRCH_SHIFT                      (0U)
+#define CRC_CRCH_CRCH(x)                         (((uint16_t)(((uint16_t)(x)) << CRC_CRCH_CRCH_SHIFT)) & CRC_CRCH_CRCH_MASK)
+
+/*! @name CRC - CRC Data register */
+#define CRC_CRC_LL_MASK                          (0xFFU)
+#define CRC_CRC_LL_SHIFT                         (0U)
+#define CRC_CRC_LL(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LL_SHIFT)) & CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK                          (0xFF00U)
+#define CRC_CRC_LU_SHIFT                         (8U)
+#define CRC_CRC_LU(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LU_SHIFT)) & CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK                          (0xFF0000U)
+#define CRC_CRC_HL_SHIFT                         (16U)
+#define CRC_CRC_HL(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HL_SHIFT)) & CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK                          (0xFF000000U)
+#define CRC_CRC_HU_SHIFT                         (24U)
+#define CRC_CRC_HU(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HU_SHIFT)) & CRC_CRC_HU_MASK)
+
+/*! @name CRCLL - CRC_CRCLL register. */
+#define CRC_CRCLL_CRCLL_MASK                     (0xFFU)
+#define CRC_CRCLL_CRCLL_SHIFT                    (0U)
+#define CRC_CRCLL_CRCLL(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCLL_CRCLL_SHIFT)) & CRC_CRCLL_CRCLL_MASK)
+
+/*! @name CRCLU - CRC_CRCLU register. */
+#define CRC_CRCLU_CRCLU_MASK                     (0xFFU)
+#define CRC_CRCLU_CRCLU_SHIFT                    (0U)
+#define CRC_CRCLU_CRCLU(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCLU_CRCLU_SHIFT)) & CRC_CRCLU_CRCLU_MASK)
+
+/*! @name CRCHL - CRC_CRCHL register. */
+#define CRC_CRCHL_CRCHL_MASK                     (0xFFU)
+#define CRC_CRCHL_CRCHL_SHIFT                    (0U)
+#define CRC_CRCHL_CRCHL(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCHL_CRCHL_SHIFT)) & CRC_CRCHL_CRCHL_MASK)
+
+/*! @name CRCHU - CRC_CRCHU register. */
+#define CRC_CRCHU_CRCHU_MASK                     (0xFFU)
+#define CRC_CRCHU_CRCHU_SHIFT                    (0U)
+#define CRC_CRCHU_CRCHU(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCHU_CRCHU_SHIFT)) & CRC_CRCHU_CRCHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial register */
+#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT                      (0U)
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT                     (16U)
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control register */
+#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT                      (24U)
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT                       (25U)
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT                      (26U)
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT                      (28U)
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT                       (30U)
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT                     (1U)
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT                     (6U)
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
 
 /*!
  * @}
@@ -3610,46 +3547,11 @@ typedef struct {
 #define CRC_BASE                                 (0x40032000u)
 /** Peripheral CRC base pointer */
 #define CRC0                                     ((CRC_Type *)CRC_BASE)
-#define CRC_BASE_PTR                             (CRC0)
 /** Array initializer of CRC peripheral base addresses */
 #define CRC_BASE_ADDRS                           { CRC_BASE }
 /** Array initializer of CRC peripheral base pointers */
 #define CRC_BASE_PTRS                            { CRC0 }
 
-/* ----------------------------------------------------------------------------
-   -- CRC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register instance definitions */
-/* CRC */
-#define CRC_CRC                                  CRC_CRC_REG(CRC0)
-#define CRC_CRCL                                 CRC_CRCL_REG(CRC0)
-#define CRC_CRCLL                                CRC_CRCLL_REG(CRC0)
-#define CRC_CRCLU                                CRC_CRCLU_REG(CRC0)
-#define CRC_CRCH                                 CRC_CRCH_REG(CRC0)
-#define CRC_CRCHL                                CRC_CRCHL_REG(CRC0)
-#define CRC_CRCHU                                CRC_CRCHU_REG(CRC0)
-#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
-#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
-#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
-#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
-#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
-#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
-#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
-#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
-#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group CRC_Peripheral_Access_Layer */
@@ -3674,94 +3576,96 @@ typedef struct {
   __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
   __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
   __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type, *DAC_MemMapPtr;
+} DAC_Type;
 
 /* ----------------------------------------------------------------------------
-   -- DAC - Register accessor macros
+   -- DAC Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @addtogroup DAC_Register_Masks DAC Register Masks
  * @{
  */
 
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK                      (0xFFU)
+#define DAC_DATL_DATA0_SHIFT                     (0U)
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT                           (16U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK                      (0xFU)
+#define DAC_DATH_DATA1_SHIFT                     (0U)
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT                           (16U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK                    (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT                   (0U)
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT                   (1U)
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     (0x4U)
+#define DAC_SR_DACBFWMF_SHIFT                    (2U)
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK                     (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT                    (0U)
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT                    (1U)
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     (0x4U)
+#define DAC_C0_DACBWIEN_SHIFT                    (2U)
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         (0x8U)
+#define DAC_C0_LPEN_SHIFT                        (3U)
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT                    (4U)
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT                   (5U)
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       (0x40U)
+#define DAC_C0_DACRFS_SHIFT                      (6U)
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        (0x80U)
+#define DAC_C0_DACEN_SHIFT                       (7U)
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK                      (0x1U)
+#define DAC_C1_DACBFEN_SHIFT                     (0U)
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      (0x6U)
+#define DAC_C1_DACBFMD_SHIFT                     (1U)
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      (0x18U)
+#define DAC_C1_DACBFWM_SHIFT                     (3U)
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        (0x80U)
+#define DAC_C1_DMAEN_SHIFT                       (7U)
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK                      (0xFU)
+#define DAC_C2_DACBFUP_SHIFT                     (0U)
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT                     (4U)
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
 
-/* DAC - Register accessors */
-#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
-#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
-#define DAC_SR_REG(base)                         ((base)->SR)
-#define DAC_C0_REG(base)                         ((base)->C0)
-#define DAC_C1_REG(base)                         ((base)->C1)
-#define DAC_C2_REG(base)                         ((base)->C2)
 
 /*!
  * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
-   -- DAC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Masks DAC Register Masks
- * @{
- */
-
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK                      0xFFu
-#define DAC_DATL_DATA0_SHIFT                     0
-#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK                      0xFu
-#define DAC_DATH_DATA1_SHIFT                     0
-#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK                    0x1u
-#define DAC_SR_DACBFRPBF_SHIFT                   0
-#define DAC_SR_DACBFRPTF_MASK                    0x2u
-#define DAC_SR_DACBFRPTF_SHIFT                   1
-#define DAC_SR_DACBFWMF_MASK                     0x4u
-#define DAC_SR_DACBFWMF_SHIFT                    2
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK                     0x1u
-#define DAC_C0_DACBBIEN_SHIFT                    0
-#define DAC_C0_DACBTIEN_MASK                     0x2u
-#define DAC_C0_DACBTIEN_SHIFT                    1
-#define DAC_C0_DACBWIEN_MASK                     0x4u
-#define DAC_C0_DACBWIEN_SHIFT                    2
-#define DAC_C0_LPEN_MASK                         0x8u
-#define DAC_C0_LPEN_SHIFT                        3
-#define DAC_C0_DACSWTRG_MASK                     0x10u
-#define DAC_C0_DACSWTRG_SHIFT                    4
-#define DAC_C0_DACTRGSEL_MASK                    0x20u
-#define DAC_C0_DACTRGSEL_SHIFT                   5
-#define DAC_C0_DACRFS_MASK                       0x40u
-#define DAC_C0_DACRFS_SHIFT                      6
-#define DAC_C0_DACEN_MASK                        0x80u
-#define DAC_C0_DACEN_SHIFT                       7
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK                      0x1u
-#define DAC_C1_DACBFEN_SHIFT                     0
-#define DAC_C1_DACBFMD_MASK                      0x6u
-#define DAC_C1_DACBFMD_SHIFT                     1
-#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
-#define DAC_C1_DACBFWM_MASK                      0x18u
-#define DAC_C1_DACBFWM_SHIFT                     3
-#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
-#define DAC_C1_DMAEN_MASK                        0x80u
-#define DAC_C1_DMAEN_SHIFT                       7
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK                      0xFu
-#define DAC_C2_DACBFUP_SHIFT                     0
-#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
-#define DAC_C2_DACBFRP_MASK                      0xF0u
-#define DAC_C2_DACBFRP_SHIFT                     4
-#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Masks */
+ */ /* end of group DAC_Register_Masks */
 
 
 /* DAC - Peripheral instance base addresses */
@@ -3769,12 +3673,10 @@ typedef struct {
 #define DAC0_BASE                                (0x400CC000u)
 /** Peripheral DAC0 base pointer */
 #define DAC0                                     ((DAC_Type *)DAC0_BASE)
-#define DAC0_BASE_PTR                            (DAC0)
 /** Peripheral DAC1 base address */
 #define DAC1_BASE                                (0x400CD000u)
 /** Peripheral DAC1 base pointer */
 #define DAC1                                     ((DAC_Type *)DAC1_BASE)
-#define DAC1_BASE_PTR                            (DAC1)
 /** Array initializer of DAC peripheral base addresses */
 #define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
 /** Array initializer of DAC peripheral base pointers */
@@ -3782,103 +3684,6 @@ typedef struct {
 /** Interrupt vectors for the DAC peripheral type */
 #define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- DAC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register instance definitions */
-/* DAC0 */
-#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
-#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
-#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
-#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
-#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
-#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
-#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
-#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
-#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
-#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
-#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
-#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
-#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
-#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
-#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
-#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
-#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
-#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
-#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
-#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
-#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
-#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
-#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
-#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
-#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
-#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
-#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
-#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
-#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
-#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
-#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
-#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
-#define DAC0_SR                                  DAC_SR_REG(DAC0)
-#define DAC0_C0                                  DAC_C0_REG(DAC0)
-#define DAC0_C1                                  DAC_C1_REG(DAC0)
-#define DAC0_C2                                  DAC_C2_REG(DAC0)
-/* DAC1 */
-#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
-#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
-#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
-#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
-#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
-#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
-#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
-#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
-#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
-#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
-#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
-#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
-#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
-#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
-#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
-#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
-#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
-#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
-#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
-#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
-#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
-#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
-#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
-#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
-#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
-#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
-#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
-#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
-#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
-#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
-#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
-#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
-#define DAC1_SR                                  DAC_SR_REG(DAC1)
-#define DAC1_C0                                  DAC_C0_REG(DAC1)
-#define DAC1_C1                                  DAC_C1_REG(DAC1)
-#define DAC1_C2                                  DAC_C2_REG(DAC1)
-
-/* DAC - Register array accessors */
-#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
-#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
-#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
-#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group DAC_Peripheral_Access_Layer */
@@ -3956,70 +3761,7 @@ typedef struct {
       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
     };
   } TCD[16];
-} DMA_Type, *DMA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- DMA - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register accessors */
-#define DMA_CR_REG(base)                         ((base)->CR)
-#define DMA_ES_REG(base)                         ((base)->ES)
-#define DMA_ERQ_REG(base)                        ((base)->ERQ)
-#define DMA_EEI_REG(base)                        ((base)->EEI)
-#define DMA_CEEI_REG(base)                       ((base)->CEEI)
-#define DMA_SEEI_REG(base)                       ((base)->SEEI)
-#define DMA_CERQ_REG(base)                       ((base)->CERQ)
-#define DMA_SERQ_REG(base)                       ((base)->SERQ)
-#define DMA_CDNE_REG(base)                       ((base)->CDNE)
-#define DMA_SSRT_REG(base)                       ((base)->SSRT)
-#define DMA_CERR_REG(base)                       ((base)->CERR)
-#define DMA_CINT_REG(base)                       ((base)->CINT)
-#define DMA_INT_REG(base)                        ((base)->INT)
-#define DMA_ERR_REG(base)                        ((base)->ERR)
-#define DMA_HRS_REG(base)                        ((base)->HRS)
-#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
-#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
-#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
-#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
-#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
-#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
-#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
-#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
-#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
-#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
-#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
-#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
-#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
-#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
-#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
-#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
-#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
-#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
-#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
-#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
-#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
-#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
-#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
-#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
-#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
-#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
-#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
-#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
-#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
-#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
-#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
+} DMA_Type;
 
 /* ----------------------------------------------------------------------------
    -- DMA Register Masks
@@ -4030,519 +3772,773 @@ typedef struct {
  * @{
  */
 
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK                         0x2u
-#define DMA_CR_EDBG_SHIFT                        1
-#define DMA_CR_ERCA_MASK                         0x4u
-#define DMA_CR_ERCA_SHIFT                        2
-#define DMA_CR_HOE_MASK                          0x10u
-#define DMA_CR_HOE_SHIFT                         4
-#define DMA_CR_HALT_MASK                         0x20u
-#define DMA_CR_HALT_SHIFT                        5
-#define DMA_CR_CLM_MASK                          0x40u
-#define DMA_CR_CLM_SHIFT                         6
-#define DMA_CR_EMLM_MASK                         0x80u
-#define DMA_CR_EMLM_SHIFT                        7
-#define DMA_CR_ECX_MASK                          0x10000u
-#define DMA_CR_ECX_SHIFT                         16
-#define DMA_CR_CX_MASK                           0x20000u
-#define DMA_CR_CX_SHIFT                          17
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK                          0x1u
-#define DMA_ES_DBE_SHIFT                         0
-#define DMA_ES_SBE_MASK                          0x2u
-#define DMA_ES_SBE_SHIFT                         1
-#define DMA_ES_SGE_MASK                          0x4u
-#define DMA_ES_SGE_SHIFT                         2
-#define DMA_ES_NCE_MASK                          0x8u
-#define DMA_ES_NCE_SHIFT                         3
-#define DMA_ES_DOE_MASK                          0x10u
-#define DMA_ES_DOE_SHIFT                         4
-#define DMA_ES_DAE_MASK                          0x20u
-#define DMA_ES_DAE_SHIFT                         5
-#define DMA_ES_SOE_MASK                          0x40u
-#define DMA_ES_SOE_SHIFT                         6
-#define DMA_ES_SAE_MASK                          0x80u
-#define DMA_ES_SAE_SHIFT                         7
-#define DMA_ES_ERRCHN_MASK                       0xF00u
-#define DMA_ES_ERRCHN_SHIFT                      8
-#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK                          0x4000u
-#define DMA_ES_CPE_SHIFT                         14
-#define DMA_ES_ECX_MASK                          0x10000u
-#define DMA_ES_ECX_SHIFT                         16
-#define DMA_ES_VLD_MASK                          0x80000000u
-#define DMA_ES_VLD_SHIFT                         31
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK                        0x1u
-#define DMA_ERQ_ERQ0_SHIFT                       0
-#define DMA_ERQ_ERQ1_MASK                        0x2u
-#define DMA_ERQ_ERQ1_SHIFT                       1
-#define DMA_ERQ_ERQ2_MASK                        0x4u
-#define DMA_ERQ_ERQ2_SHIFT                       2
-#define DMA_ERQ_ERQ3_MASK                        0x8u
-#define DMA_ERQ_ERQ3_SHIFT                       3
-#define DMA_ERQ_ERQ4_MASK                        0x10u
-#define DMA_ERQ_ERQ4_SHIFT                       4
-#define DMA_ERQ_ERQ5_MASK                        0x20u
-#define DMA_ERQ_ERQ5_SHIFT                       5
-#define DMA_ERQ_ERQ6_MASK                        0x40u
-#define DMA_ERQ_ERQ6_SHIFT                       6
-#define DMA_ERQ_ERQ7_MASK                        0x80u
-#define DMA_ERQ_ERQ7_SHIFT                       7
-#define DMA_ERQ_ERQ8_MASK                        0x100u
-#define DMA_ERQ_ERQ8_SHIFT                       8
-#define DMA_ERQ_ERQ9_MASK                        0x200u
-#define DMA_ERQ_ERQ9_SHIFT                       9
-#define DMA_ERQ_ERQ10_MASK                       0x400u
-#define DMA_ERQ_ERQ10_SHIFT                      10
-#define DMA_ERQ_ERQ11_MASK                       0x800u
-#define DMA_ERQ_ERQ11_SHIFT                      11
-#define DMA_ERQ_ERQ12_MASK                       0x1000u
-#define DMA_ERQ_ERQ12_SHIFT                      12
-#define DMA_ERQ_ERQ13_MASK                       0x2000u
-#define DMA_ERQ_ERQ13_SHIFT                      13
-#define DMA_ERQ_ERQ14_MASK                       0x4000u
-#define DMA_ERQ_ERQ14_SHIFT                      14
-#define DMA_ERQ_ERQ15_MASK                       0x8000u
-#define DMA_ERQ_ERQ15_SHIFT                      15
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK                        0x1u
-#define DMA_EEI_EEI0_SHIFT                       0
-#define DMA_EEI_EEI1_MASK                        0x2u
-#define DMA_EEI_EEI1_SHIFT                       1
-#define DMA_EEI_EEI2_MASK                        0x4u
-#define DMA_EEI_EEI2_SHIFT                       2
-#define DMA_EEI_EEI3_MASK                        0x8u
-#define DMA_EEI_EEI3_SHIFT                       3
-#define DMA_EEI_EEI4_MASK                        0x10u
-#define DMA_EEI_EEI4_SHIFT                       4
-#define DMA_EEI_EEI5_MASK                        0x20u
-#define DMA_EEI_EEI5_SHIFT                       5
-#define DMA_EEI_EEI6_MASK                        0x40u
-#define DMA_EEI_EEI6_SHIFT                       6
-#define DMA_EEI_EEI7_MASK                        0x80u
-#define DMA_EEI_EEI7_SHIFT                       7
-#define DMA_EEI_EEI8_MASK                        0x100u
-#define DMA_EEI_EEI8_SHIFT                       8
-#define DMA_EEI_EEI9_MASK                        0x200u
-#define DMA_EEI_EEI9_SHIFT                       9
-#define DMA_EEI_EEI10_MASK                       0x400u
-#define DMA_EEI_EEI10_SHIFT                      10
-#define DMA_EEI_EEI11_MASK                       0x800u
-#define DMA_EEI_EEI11_SHIFT                      11
-#define DMA_EEI_EEI12_MASK                       0x1000u
-#define DMA_EEI_EEI12_SHIFT                      12
-#define DMA_EEI_EEI13_MASK                       0x2000u
-#define DMA_EEI_EEI13_SHIFT                      13
-#define DMA_EEI_EEI14_MASK                       0x4000u
-#define DMA_EEI_EEI14_SHIFT                      14
-#define DMA_EEI_EEI15_MASK                       0x8000u
-#define DMA_EEI_EEI15_SHIFT                      15
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK                       0xFu
-#define DMA_CEEI_CEEI_SHIFT                      0
-#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK                       0x40u
-#define DMA_CEEI_CAEE_SHIFT                      6
-#define DMA_CEEI_NOP_MASK                        0x80u
-#define DMA_CEEI_NOP_SHIFT                       7
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK                       0xFu
-#define DMA_SEEI_SEEI_SHIFT                      0
-#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK                       0x40u
-#define DMA_SEEI_SAEE_SHIFT                      6
-#define DMA_SEEI_NOP_MASK                        0x80u
-#define DMA_SEEI_NOP_SHIFT                       7
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK                       0xFu
-#define DMA_CERQ_CERQ_SHIFT                      0
-#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK                       0x40u
-#define DMA_CERQ_CAER_SHIFT                      6
-#define DMA_CERQ_NOP_MASK                        0x80u
-#define DMA_CERQ_NOP_SHIFT                       7
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK                       0xFu
-#define DMA_SERQ_SERQ_SHIFT                      0
-#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK                       0x40u
-#define DMA_SERQ_SAER_SHIFT                      6
-#define DMA_SERQ_NOP_MASK                        0x80u
-#define DMA_SERQ_NOP_SHIFT                       7
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK                       0xFu
-#define DMA_CDNE_CDNE_SHIFT                      0
-#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK                       0x40u
-#define DMA_CDNE_CADN_SHIFT                      6
-#define DMA_CDNE_NOP_MASK                        0x80u
-#define DMA_CDNE_NOP_SHIFT                       7
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK                       0xFu
-#define DMA_SSRT_SSRT_SHIFT                      0
-#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK                       0x40u
-#define DMA_SSRT_SAST_SHIFT                      6
-#define DMA_SSRT_NOP_MASK                        0x80u
-#define DMA_SSRT_NOP_SHIFT                       7
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK                       0xFu
-#define DMA_CERR_CERR_SHIFT                      0
-#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK                       0x40u
-#define DMA_CERR_CAEI_SHIFT                      6
-#define DMA_CERR_NOP_MASK                        0x80u
-#define DMA_CERR_NOP_SHIFT                       7
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK                       0xFu
-#define DMA_CINT_CINT_SHIFT                      0
-#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK                       0x40u
-#define DMA_CINT_CAIR_SHIFT                      6
-#define DMA_CINT_NOP_MASK                        0x80u
-#define DMA_CINT_NOP_SHIFT                       7
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK                        0x1u
-#define DMA_INT_INT0_SHIFT                       0
-#define DMA_INT_INT1_MASK                        0x2u
-#define DMA_INT_INT1_SHIFT                       1
-#define DMA_INT_INT2_MASK                        0x4u
-#define DMA_INT_INT2_SHIFT                       2
-#define DMA_INT_INT3_MASK                        0x8u
-#define DMA_INT_INT3_SHIFT                       3
-#define DMA_INT_INT4_MASK                        0x10u
-#define DMA_INT_INT4_SHIFT                       4
-#define DMA_INT_INT5_MASK                        0x20u
-#define DMA_INT_INT5_SHIFT                       5
-#define DMA_INT_INT6_MASK                        0x40u
-#define DMA_INT_INT6_SHIFT                       6
-#define DMA_INT_INT7_MASK                        0x80u
-#define DMA_INT_INT7_SHIFT                       7
-#define DMA_INT_INT8_MASK                        0x100u
-#define DMA_INT_INT8_SHIFT                       8
-#define DMA_INT_INT9_MASK                        0x200u
-#define DMA_INT_INT9_SHIFT                       9
-#define DMA_INT_INT10_MASK                       0x400u
-#define DMA_INT_INT10_SHIFT                      10
-#define DMA_INT_INT11_MASK                       0x800u
-#define DMA_INT_INT11_SHIFT                      11
-#define DMA_INT_INT12_MASK                       0x1000u
-#define DMA_INT_INT12_SHIFT                      12
-#define DMA_INT_INT13_MASK                       0x2000u
-#define DMA_INT_INT13_SHIFT                      13
-#define DMA_INT_INT14_MASK                       0x4000u
-#define DMA_INT_INT14_SHIFT                      14
-#define DMA_INT_INT15_MASK                       0x8000u
-#define DMA_INT_INT15_SHIFT                      15
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK                        0x1u
-#define DMA_ERR_ERR0_SHIFT                       0
-#define DMA_ERR_ERR1_MASK                        0x2u
-#define DMA_ERR_ERR1_SHIFT                       1
-#define DMA_ERR_ERR2_MASK                        0x4u
-#define DMA_ERR_ERR2_SHIFT                       2
-#define DMA_ERR_ERR3_MASK                        0x8u
-#define DMA_ERR_ERR3_SHIFT                       3
-#define DMA_ERR_ERR4_MASK                        0x10u
-#define DMA_ERR_ERR4_SHIFT                       4
-#define DMA_ERR_ERR5_MASK                        0x20u
-#define DMA_ERR_ERR5_SHIFT                       5
-#define DMA_ERR_ERR6_MASK                        0x40u
-#define DMA_ERR_ERR6_SHIFT                       6
-#define DMA_ERR_ERR7_MASK                        0x80u
-#define DMA_ERR_ERR7_SHIFT                       7
-#define DMA_ERR_ERR8_MASK                        0x100u
-#define DMA_ERR_ERR8_SHIFT                       8
-#define DMA_ERR_ERR9_MASK                        0x200u
-#define DMA_ERR_ERR9_SHIFT                       9
-#define DMA_ERR_ERR10_MASK                       0x400u
-#define DMA_ERR_ERR10_SHIFT                      10
-#define DMA_ERR_ERR11_MASK                       0x800u
-#define DMA_ERR_ERR11_SHIFT                      11
-#define DMA_ERR_ERR12_MASK                       0x1000u
-#define DMA_ERR_ERR12_SHIFT                      12
-#define DMA_ERR_ERR13_MASK                       0x2000u
-#define DMA_ERR_ERR13_SHIFT                      13
-#define DMA_ERR_ERR14_MASK                       0x4000u
-#define DMA_ERR_ERR14_SHIFT                      14
-#define DMA_ERR_ERR15_MASK                       0x8000u
-#define DMA_ERR_ERR15_SHIFT                      15
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK                        0x1u
-#define DMA_HRS_HRS0_SHIFT                       0
-#define DMA_HRS_HRS1_MASK                        0x2u
-#define DMA_HRS_HRS1_SHIFT                       1
-#define DMA_HRS_HRS2_MASK                        0x4u
-#define DMA_HRS_HRS2_SHIFT                       2
-#define DMA_HRS_HRS3_MASK                        0x8u
-#define DMA_HRS_HRS3_SHIFT                       3
-#define DMA_HRS_HRS4_MASK                        0x10u
-#define DMA_HRS_HRS4_SHIFT                       4
-#define DMA_HRS_HRS5_MASK                        0x20u
-#define DMA_HRS_HRS5_SHIFT                       5
-#define DMA_HRS_HRS6_MASK                        0x40u
-#define DMA_HRS_HRS6_SHIFT                       6
-#define DMA_HRS_HRS7_MASK                        0x80u
-#define DMA_HRS_HRS7_SHIFT                       7
-#define DMA_HRS_HRS8_MASK                        0x100u
-#define DMA_HRS_HRS8_SHIFT                       8
-#define DMA_HRS_HRS9_MASK                        0x200u
-#define DMA_HRS_HRS9_SHIFT                       9
-#define DMA_HRS_HRS10_MASK                       0x400u
-#define DMA_HRS_HRS10_SHIFT                      10
-#define DMA_HRS_HRS11_MASK                       0x800u
-#define DMA_HRS_HRS11_SHIFT                      11
-#define DMA_HRS_HRS12_MASK                       0x1000u
-#define DMA_HRS_HRS12_SHIFT                      12
-#define DMA_HRS_HRS13_MASK                       0x2000u
-#define DMA_HRS_HRS13_SHIFT                      13
-#define DMA_HRS_HRS14_MASK                       0x4000u
-#define DMA_HRS_HRS14_SHIFT                      14
-#define DMA_HRS_HRS15_MASK                       0x8000u
-#define DMA_HRS_HRS15_SHIFT                      15
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI3_CHPRI_SHIFT                  0
-#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK                     0x40u
-#define DMA_DCHPRI3_DPA_SHIFT                    6
-#define DMA_DCHPRI3_ECP_MASK                     0x80u
-#define DMA_DCHPRI3_ECP_SHIFT                    7
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI2_CHPRI_SHIFT                  0
-#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK                     0x40u
-#define DMA_DCHPRI2_DPA_SHIFT                    6
-#define DMA_DCHPRI2_ECP_MASK                     0x80u
-#define DMA_DCHPRI2_ECP_SHIFT                    7
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI1_CHPRI_SHIFT                  0
-#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK                     0x40u
-#define DMA_DCHPRI1_DPA_SHIFT                    6
-#define DMA_DCHPRI1_ECP_MASK                     0x80u
-#define DMA_DCHPRI1_ECP_SHIFT                    7
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI0_CHPRI_SHIFT                  0
-#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK                     0x40u
-#define DMA_DCHPRI0_DPA_SHIFT                    6
-#define DMA_DCHPRI0_ECP_MASK                     0x80u
-#define DMA_DCHPRI0_ECP_SHIFT                    7
-/* DCHPRI7 Bit Fields */
-#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI7_CHPRI_SHIFT                  0
-#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
-#define DMA_DCHPRI7_DPA_MASK                     0x40u
-#define DMA_DCHPRI7_DPA_SHIFT                    6
-#define DMA_DCHPRI7_ECP_MASK                     0x80u
-#define DMA_DCHPRI7_ECP_SHIFT                    7
-/* DCHPRI6 Bit Fields */
-#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI6_CHPRI_SHIFT                  0
-#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
-#define DMA_DCHPRI6_DPA_MASK                     0x40u
-#define DMA_DCHPRI6_DPA_SHIFT                    6
-#define DMA_DCHPRI6_ECP_MASK                     0x80u
-#define DMA_DCHPRI6_ECP_SHIFT                    7
-/* DCHPRI5 Bit Fields */
-#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI5_CHPRI_SHIFT                  0
-#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
-#define DMA_DCHPRI5_DPA_MASK                     0x40u
-#define DMA_DCHPRI5_DPA_SHIFT                    6
-#define DMA_DCHPRI5_ECP_MASK                     0x80u
-#define DMA_DCHPRI5_ECP_SHIFT                    7
-/* DCHPRI4 Bit Fields */
-#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI4_CHPRI_SHIFT                  0
-#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
-#define DMA_DCHPRI4_DPA_MASK                     0x40u
-#define DMA_DCHPRI4_DPA_SHIFT                    6
-#define DMA_DCHPRI4_ECP_MASK                     0x80u
-#define DMA_DCHPRI4_ECP_SHIFT                    7
-/* DCHPRI11 Bit Fields */
-#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
-#define DMA_DCHPRI11_CHPRI_SHIFT                 0
-#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
-#define DMA_DCHPRI11_DPA_MASK                    0x40u
-#define DMA_DCHPRI11_DPA_SHIFT                   6
-#define DMA_DCHPRI11_ECP_MASK                    0x80u
-#define DMA_DCHPRI11_ECP_SHIFT                   7
-/* DCHPRI10 Bit Fields */
-#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
-#define DMA_DCHPRI10_CHPRI_SHIFT                 0
-#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
-#define DMA_DCHPRI10_DPA_MASK                    0x40u
-#define DMA_DCHPRI10_DPA_SHIFT                   6
-#define DMA_DCHPRI10_ECP_MASK                    0x80u
-#define DMA_DCHPRI10_ECP_SHIFT                   7
-/* DCHPRI9 Bit Fields */
-#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI9_CHPRI_SHIFT                  0
-#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
-#define DMA_DCHPRI9_DPA_MASK                     0x40u
-#define DMA_DCHPRI9_DPA_SHIFT                    6
-#define DMA_DCHPRI9_ECP_MASK                     0x80u
-#define DMA_DCHPRI9_ECP_SHIFT                    7
-/* DCHPRI8 Bit Fields */
-#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
-#define DMA_DCHPRI8_CHPRI_SHIFT                  0
-#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
-#define DMA_DCHPRI8_DPA_MASK                     0x40u
-#define DMA_DCHPRI8_DPA_SHIFT                    6
-#define DMA_DCHPRI8_ECP_MASK                     0x80u
-#define DMA_DCHPRI8_ECP_SHIFT                    7
-/* DCHPRI15 Bit Fields */
-#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
-#define DMA_DCHPRI15_CHPRI_SHIFT                 0
-#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
-#define DMA_DCHPRI15_DPA_MASK                    0x40u
-#define DMA_DCHPRI15_DPA_SHIFT                   6
-#define DMA_DCHPRI15_ECP_MASK                    0x80u
-#define DMA_DCHPRI15_ECP_SHIFT                   7
-/* DCHPRI14 Bit Fields */
-#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
-#define DMA_DCHPRI14_CHPRI_SHIFT                 0
-#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
-#define DMA_DCHPRI14_DPA_MASK                    0x40u
-#define DMA_DCHPRI14_DPA_SHIFT                   6
-#define DMA_DCHPRI14_ECP_MASK                    0x80u
-#define DMA_DCHPRI14_ECP_SHIFT                   7
-/* DCHPRI13 Bit Fields */
-#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
-#define DMA_DCHPRI13_CHPRI_SHIFT                 0
-#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
-#define DMA_DCHPRI13_DPA_MASK                    0x40u
-#define DMA_DCHPRI13_DPA_SHIFT                   6
-#define DMA_DCHPRI13_ECP_MASK                    0x80u
-#define DMA_DCHPRI13_ECP_SHIFT                   7
-/* DCHPRI12 Bit Fields */
-#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
-#define DMA_DCHPRI12_CHPRI_SHIFT                 0
-#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
-#define DMA_DCHPRI12_DPA_MASK                    0x40u
-#define DMA_DCHPRI12_DPA_SHIFT                   6
-#define DMA_DCHPRI12_ECP_MASK                    0x80u
-#define DMA_DCHPRI12_ECP_SHIFT                   7
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT                    0
-#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK                       0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT                      0
-#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK                      0x7u
-#define DMA_ATTR_DSIZE_SHIFT                     0
-#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK                       0xF8u
-#define DMA_ATTR_DMOD_SHIFT                      3
-#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK                      0x700u
-#define DMA_ATTR_SSIZE_SHIFT                     8
-#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK                       0xF800u
-#define DMA_ATTR_SMOD_SHIFT                      11
-#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
-#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT                    0
-#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT                    0
-#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK                       0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT                      0
-#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT            0
-#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT           0
-#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
-#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
-#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK                       0x1u
-#define DMA_CSR_START_SHIFT                      0
-#define DMA_CSR_INTMAJOR_MASK                    0x2u
-#define DMA_CSR_INTMAJOR_SHIFT                   1
-#define DMA_CSR_INTHALF_MASK                     0x4u
-#define DMA_CSR_INTHALF_SHIFT                    2
-#define DMA_CSR_DREQ_MASK                        0x8u
-#define DMA_CSR_DREQ_SHIFT                       3
-#define DMA_CSR_ESG_MASK                         0x10u
-#define DMA_CSR_ESG_SHIFT                        4
-#define DMA_CSR_MAJORELINK_MASK                  0x20u
-#define DMA_CSR_MAJORELINK_SHIFT                 5
-#define DMA_CSR_ACTIVE_MASK                      0x40u
-#define DMA_CSR_ACTIVE_SHIFT                     6
-#define DMA_CSR_DONE_MASK                        0x80u
-#define DMA_CSR_DONE_SHIFT                       7
-#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
-#define DMA_CSR_MAJORLINKCH_SHIFT                8
-#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK                         0xC000u
-#define DMA_CSR_BWC_SHIFT                        14
-#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT            0
-#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT           0
-#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
-#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG_MASK                         (0x2U)
+#define DMA_CR_EDBG_SHIFT                        (1U)
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         (0x4U)
+#define DMA_CR_ERCA_SHIFT                        (2U)
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          (0x10U)
+#define DMA_CR_HOE_SHIFT                         (4U)
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         (0x20U)
+#define DMA_CR_HALT_SHIFT                        (5U)
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          (0x40U)
+#define DMA_CR_CLM_SHIFT                         (6U)
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         (0x80U)
+#define DMA_CR_EMLM_SHIFT                        (7U)
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          (0x10000U)
+#define DMA_CR_ECX_SHIFT                         (16U)
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           (0x20000U)
+#define DMA_CR_CX_SHIFT                          (17U)
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE_MASK                          (0x1U)
+#define DMA_ES_DBE_SHIFT                         (0U)
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          (0x2U)
+#define DMA_ES_SBE_SHIFT                         (1U)
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          (0x4U)
+#define DMA_ES_SGE_SHIFT                         (2U)
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          (0x8U)
+#define DMA_ES_NCE_SHIFT                         (3U)
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          (0x10U)
+#define DMA_ES_DOE_SHIFT                         (4U)
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          (0x20U)
+#define DMA_ES_DAE_SHIFT                         (5U)
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          (0x40U)
+#define DMA_ES_SOE_SHIFT                         (6U)
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          (0x80U)
+#define DMA_ES_SAE_SHIFT                         (7U)
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       (0xF00U)
+#define DMA_ES_ERRCHN_SHIFT                      (8U)
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          (0x4000U)
+#define DMA_ES_CPE_SHIFT                         (14U)
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          (0x10000U)
+#define DMA_ES_ECX_SHIFT                         (16U)
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          (0x80000000U)
+#define DMA_ES_VLD_SHIFT                         (31U)
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+
+/*! @name ERQ - Enable Request Register */
+#define DMA_ERQ_ERQ0_MASK                        (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT                       (0U)
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT                       (1U)
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT                       (2U)
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT                       (3U)
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT                       (4U)
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT                       (5U)
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT                       (6U)
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT                       (7U)
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        (0x100U)
+#define DMA_ERQ_ERQ8_SHIFT                       (8U)
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        (0x200U)
+#define DMA_ERQ_ERQ9_SHIFT                       (9U)
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       (0x400U)
+#define DMA_ERQ_ERQ10_SHIFT                      (10U)
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       (0x800U)
+#define DMA_ERQ_ERQ11_SHIFT                      (11U)
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       (0x1000U)
+#define DMA_ERQ_ERQ12_SHIFT                      (12U)
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       (0x2000U)
+#define DMA_ERQ_ERQ13_SHIFT                      (13U)
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       (0x4000U)
+#define DMA_ERQ_ERQ14_SHIFT                      (14U)
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       (0x8000U)
+#define DMA_ERQ_ERQ15_SHIFT                      (15U)
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+
+/*! @name EEI - Enable Error Interrupt Register */
+#define DMA_EEI_EEI0_MASK                        (0x1U)
+#define DMA_EEI_EEI0_SHIFT                       (0U)
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        (0x2U)
+#define DMA_EEI_EEI1_SHIFT                       (1U)
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        (0x4U)
+#define DMA_EEI_EEI2_SHIFT                       (2U)
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        (0x8U)
+#define DMA_EEI_EEI3_SHIFT                       (3U)
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        (0x10U)
+#define DMA_EEI_EEI4_SHIFT                       (4U)
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        (0x20U)
+#define DMA_EEI_EEI5_SHIFT                       (5U)
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        (0x40U)
+#define DMA_EEI_EEI6_SHIFT                       (6U)
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        (0x80U)
+#define DMA_EEI_EEI7_SHIFT                       (7U)
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        (0x100U)
+#define DMA_EEI_EEI8_SHIFT                       (8U)
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        (0x200U)
+#define DMA_EEI_EEI9_SHIFT                       (9U)
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       (0x400U)
+#define DMA_EEI_EEI10_SHIFT                      (10U)
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       (0x800U)
+#define DMA_EEI_EEI11_SHIFT                      (11U)
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       (0x1000U)
+#define DMA_EEI_EEI12_SHIFT                      (12U)
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       (0x2000U)
+#define DMA_EEI_EEI13_SHIFT                      (13U)
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       (0x4000U)
+#define DMA_EEI_EEI14_SHIFT                      (14U)
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       (0x8000U)
+#define DMA_EEI_EEI15_SHIFT                      (15U)
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK                       (0xFU)
+#define DMA_CEEI_CEEI_SHIFT                      (0U)
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       (0x40U)
+#define DMA_CEEI_CAEE_SHIFT                      (6U)
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        (0x80U)
+#define DMA_CEEI_NOP_SHIFT                       (7U)
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK                       (0xFU)
+#define DMA_SEEI_SEEI_SHIFT                      (0U)
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       (0x40U)
+#define DMA_SEEI_SAEE_SHIFT                      (6U)
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        (0x80U)
+#define DMA_SEEI_NOP_SHIFT                       (7U)
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK                       (0xFU)
+#define DMA_CERQ_CERQ_SHIFT                      (0U)
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       (0x40U)
+#define DMA_CERQ_CAER_SHIFT                      (6U)
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        (0x80U)
+#define DMA_CERQ_NOP_SHIFT                       (7U)
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK                       (0xFU)
+#define DMA_SERQ_SERQ_SHIFT                      (0U)
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       (0x40U)
+#define DMA_SERQ_SAER_SHIFT                      (6U)
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        (0x80U)
+#define DMA_SERQ_NOP_SHIFT                       (7U)
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK                       (0xFU)
+#define DMA_CDNE_CDNE_SHIFT                      (0U)
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       (0x40U)
+#define DMA_CDNE_CADN_SHIFT                      (6U)
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        (0x80U)
+#define DMA_CDNE_NOP_SHIFT                       (7U)
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK                       (0xFU)
+#define DMA_SSRT_SSRT_SHIFT                      (0U)
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       (0x40U)
+#define DMA_SSRT_SAST_SHIFT                      (6U)
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        (0x80U)
+#define DMA_SSRT_NOP_SHIFT                       (7U)
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK                       (0xFU)
+#define DMA_CERR_CERR_SHIFT                      (0U)
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       (0x40U)
+#define DMA_CERR_CAEI_SHIFT                      (6U)
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        (0x80U)
+#define DMA_CERR_NOP_SHIFT                       (7U)
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK                       (0xFU)
+#define DMA_CINT_CINT_SHIFT                      (0U)
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       (0x40U)
+#define DMA_CINT_CAIR_SHIFT                      (6U)
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        (0x80U)
+#define DMA_CINT_NOP_SHIFT                       (7U)
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+
+/*! @name INT - Interrupt Request Register */
+#define DMA_INT_INT0_MASK                        (0x1U)
+#define DMA_INT_INT0_SHIFT                       (0U)
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        (0x2U)
+#define DMA_INT_INT1_SHIFT                       (1U)
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        (0x4U)
+#define DMA_INT_INT2_SHIFT                       (2U)
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        (0x8U)
+#define DMA_INT_INT3_SHIFT                       (3U)
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        (0x10U)
+#define DMA_INT_INT4_SHIFT                       (4U)
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        (0x20U)
+#define DMA_INT_INT5_SHIFT                       (5U)
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        (0x40U)
+#define DMA_INT_INT6_SHIFT                       (6U)
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        (0x80U)
+#define DMA_INT_INT7_SHIFT                       (7U)
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        (0x100U)
+#define DMA_INT_INT8_SHIFT                       (8U)
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        (0x200U)
+#define DMA_INT_INT9_SHIFT                       (9U)
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       (0x400U)
+#define DMA_INT_INT10_SHIFT                      (10U)
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       (0x800U)
+#define DMA_INT_INT11_SHIFT                      (11U)
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       (0x1000U)
+#define DMA_INT_INT12_SHIFT                      (12U)
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       (0x2000U)
+#define DMA_INT_INT13_SHIFT                      (13U)
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       (0x4000U)
+#define DMA_INT_INT14_SHIFT                      (14U)
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       (0x8000U)
+#define DMA_INT_INT15_SHIFT                      (15U)
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+
+/*! @name ERR - Error Register */
+#define DMA_ERR_ERR0_MASK                        (0x1U)
+#define DMA_ERR_ERR0_SHIFT                       (0U)
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        (0x2U)
+#define DMA_ERR_ERR1_SHIFT                       (1U)
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        (0x4U)
+#define DMA_ERR_ERR2_SHIFT                       (2U)
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        (0x8U)
+#define DMA_ERR_ERR3_SHIFT                       (3U)
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        (0x10U)
+#define DMA_ERR_ERR4_SHIFT                       (4U)
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        (0x20U)
+#define DMA_ERR_ERR5_SHIFT                       (5U)
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        (0x40U)
+#define DMA_ERR_ERR6_SHIFT                       (6U)
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        (0x80U)
+#define DMA_ERR_ERR7_SHIFT                       (7U)
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        (0x100U)
+#define DMA_ERR_ERR8_SHIFT                       (8U)
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        (0x200U)
+#define DMA_ERR_ERR9_SHIFT                       (9U)
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       (0x400U)
+#define DMA_ERR_ERR10_SHIFT                      (10U)
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       (0x800U)
+#define DMA_ERR_ERR11_SHIFT                      (11U)
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       (0x1000U)
+#define DMA_ERR_ERR12_SHIFT                      (12U)
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       (0x2000U)
+#define DMA_ERR_ERR13_SHIFT                      (13U)
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       (0x4000U)
+#define DMA_ERR_ERR14_SHIFT                      (14U)
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       (0x8000U)
+#define DMA_ERR_ERR15_SHIFT                      (15U)
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+
+/*! @name HRS - Hardware Request Status Register */
+#define DMA_HRS_HRS0_MASK                        (0x1U)
+#define DMA_HRS_HRS0_SHIFT                       (0U)
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        (0x2U)
+#define DMA_HRS_HRS1_SHIFT                       (1U)
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        (0x4U)
+#define DMA_HRS_HRS2_SHIFT                       (2U)
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        (0x8U)
+#define DMA_HRS_HRS3_SHIFT                       (3U)
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        (0x10U)
+#define DMA_HRS_HRS4_SHIFT                       (4U)
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        (0x20U)
+#define DMA_HRS_HRS5_SHIFT                       (5U)
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        (0x40U)
+#define DMA_HRS_HRS6_SHIFT                       (6U)
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        (0x80U)
+#define DMA_HRS_HRS7_SHIFT                       (7U)
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        (0x100U)
+#define DMA_HRS_HRS8_SHIFT                       (8U)
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        (0x200U)
+#define DMA_HRS_HRS9_SHIFT                       (9U)
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       (0x400U)
+#define DMA_HRS_HRS10_SHIFT                      (10U)
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       (0x800U)
+#define DMA_HRS_HRS11_SHIFT                      (11U)
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       (0x1000U)
+#define DMA_HRS_HRS12_SHIFT                      (12U)
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       (0x2000U)
+#define DMA_HRS_HRS13_SHIFT                      (13U)
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       (0x4000U)
+#define DMA_HRS_HRS14_SHIFT                      (14U)
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       (0x8000U)
+#define DMA_HRS_HRS15_SHIFT                      (15U)
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+#define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+#define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+#define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+#define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+
+/*! @name DCHPRI7 - Channel n Priority Register */
+#define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+
+/*! @name DCHPRI6 - Channel n Priority Register */
+#define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+
+/*! @name DCHPRI5 - Channel n Priority Register */
+#define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+
+/*! @name DCHPRI4 - Channel n Priority Register */
+#define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+
+/*! @name DCHPRI11 - Channel n Priority Register */
+#define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI11_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI11_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+
+/*! @name DCHPRI10 - Channel n Priority Register */
+#define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI10_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI10_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+
+/*! @name DCHPRI9 - Channel n Priority Register */
+#define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI9_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI9_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+
+/*! @name DCHPRI8 - Channel n Priority Register */
+#define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI8_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI8_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+
+/*! @name DCHPRI15 - Channel n Priority Register */
+#define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI15_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI15_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+
+/*! @name DCHPRI14 - Channel n Priority Register */
+#define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI14_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI14_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+
+/*! @name DCHPRI13 - Channel n Priority Register */
+#define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI13_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI13_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+
+/*! @name DCHPRI12 - Channel n Priority Register */
+#define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI12_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI12_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+
+/*! @name SADDR - TCD Source Address */
+#define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT                    (0U)
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT                          (16U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT                      (0U)
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT                           (16U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK                      (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT                     (0U)
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT                      (3U)
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT                     (8U)
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT                      (11U)
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT                           (16U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT                    (16U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT                 (16U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT                (16U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+#define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT                    (0U)
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT                          (16U)
+
+/*! @name DADDR - TCD Destination Address */
+#define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT                    (0U)
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT                          (16U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT                      (0U)
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT                           (16U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT                  (16U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           (0x1E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT                 (16U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT                      (16U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START_MASK                       (0x1U)
+#define DMA_CSR_START_SHIFT                      (0U)
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT                   (1U)
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     (0x4U)
+#define DMA_CSR_INTHALF_SHIFT                    (2U)
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        (0x8U)
+#define DMA_CSR_DREQ_SHIFT                       (3U)
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         (0x10U)
+#define DMA_CSR_ESG_SHIFT                        (4U)
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT                 (5U)
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT                     (6U)
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        (0x80U)
+#define DMA_CSR_DONE_SHIFT                       (7U)
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 (0xF00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         (0xC000U)
+#define DMA_CSR_BWC_SHIFT                        (14U)
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT                            (16U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT                  (16U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           (0x1E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT                 (16U)
+
 
 /*!
  * @}
@@ -4554,321 +4550,14 @@ typedef struct {
 #define DMA_BASE                                 (0x40008000u)
 /** Peripheral DMA base pointer */
 #define DMA0                                     ((DMA_Type *)DMA_BASE)
-#define DMA_BASE_PTR                             (DMA0)
 /** Array initializer of DMA peripheral base addresses */
 #define DMA_BASE_ADDRS                           { DMA_BASE }
 /** Array initializer of DMA peripheral base pointers */
 #define DMA_BASE_PTRS                            { DMA0 }
 /** Interrupt vectors for the DMA peripheral type */
-#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_CHN_IRQS                             { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
 #define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- DMA - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register instance definitions */
-/* DMA */
-#define DMA_CR                                   DMA_CR_REG(DMA0)
-#define DMA_ES                                   DMA_ES_REG(DMA0)
-#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
-#define DMA_EEI                                  DMA_EEI_REG(DMA0)
-#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
-#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
-#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
-#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
-#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
-#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
-#define DMA_CERR                                 DMA_CERR_REG(DMA0)
-#define DMA_CINT                                 DMA_CINT_REG(DMA0)
-#define DMA_INT                                  DMA_INT_REG(DMA0)
-#define DMA_ERR                                  DMA_ERR_REG(DMA0)
-#define DMA_HRS                                  DMA_HRS_REG(DMA0)
-#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
-#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
-#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
-#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
-#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
-#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
-#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
-#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
-#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
-#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
-#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
-#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
-#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
-#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
-#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
-#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
-#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
-#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
-#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
-#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
-#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
-#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
-#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
-#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
-#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
-#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
-#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
-#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
-#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
-#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
-#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
-#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
-#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
-#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
-#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
-#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
-#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
-#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
-#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
-#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
-#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
-#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
-#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
-#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
-#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
-#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
-#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
-#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
-#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
-#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
-#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
-#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
-#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
-#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
-#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
-#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
-#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
-#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
-#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
-#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
-#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
-#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
-#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
-#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
-#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
-#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
-#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
-#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
-#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
-#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
-#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
-#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
-#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
-#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
-#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
-#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
-#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
-#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
-#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
-#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
-#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
-#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
-#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
-#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
-#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
-#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
-#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
-#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
-#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
-#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
-#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
-#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
-#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
-#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
-#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
-#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
-#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
-#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
-#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
-#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
-#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
-#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
-#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
-#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
-#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
-#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
-#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
-#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
-#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
-#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
-#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
-#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
-#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
-#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
-
-/* DMA - Register array accessors */
-#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
-#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
-#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
-#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
-#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
-#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
-#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
-#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
-#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
-#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
-#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
-#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
-#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group DMA_Peripheral_Access_Layer */
@@ -4886,25 +4575,7 @@ typedef struct {
 /** DMAMUX - Register Layout Typedef */
 typedef struct {
   __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type, *DMAMUX_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- DMAMUX - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register accessors */
-#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
+} DMAMUX_Type;
 
 /* ----------------------------------------------------------------------------
    -- DMAMUX Register Masks
@@ -4915,14 +4586,20 @@ typedef struct {
  * @{
  */
 
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT                0
-#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT                  6
-#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT                  (6U)
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT                  (7U)
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT                       (16U)
+
 
 /*!
  * @}
@@ -4934,49 +4611,11 @@ typedef struct {
 #define DMAMUX_BASE                              (0x40021000u)
 /** Peripheral DMAMUX base pointer */
 #define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
-#define DMAMUX_BASE_PTR                          (DMAMUX)
 /** Array initializer of DMAMUX peripheral base addresses */
 #define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
 /** Array initializer of DMAMUX peripheral base pointers */
 #define DMAMUX_BASE_PTRS                         { DMAMUX }
 
-/* ----------------------------------------------------------------------------
-   -- DMAMUX - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register instance definitions */
-/* DMAMUX */
-#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
-#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
-#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
-#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
-#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
-#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
-#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
-#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
-#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
-#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
-#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
-#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
-#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
-#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
-#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
-#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
-
-/* DMAMUX - Register array accessors */
-#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group DMAMUX_Peripheral_Access_Layer */
@@ -5108,120 +4747,7 @@ typedef struct {
     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
   } CHANNEL[4];
-} ENET_Type, *ENET_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- ENET - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
- * @{
- */
-
-
-/* ENET - Register accessors */
-#define ENET_EIR_REG(base)                       ((base)->EIR)
-#define ENET_EIMR_REG(base)                      ((base)->EIMR)
-#define ENET_RDAR_REG(base)                      ((base)->RDAR)
-#define ENET_TDAR_REG(base)                      ((base)->TDAR)
-#define ENET_ECR_REG(base)                       ((base)->ECR)
-#define ENET_MMFR_REG(base)                      ((base)->MMFR)
-#define ENET_MSCR_REG(base)                      ((base)->MSCR)
-#define ENET_MIBC_REG(base)                      ((base)->MIBC)
-#define ENET_RCR_REG(base)                       ((base)->RCR)
-#define ENET_TCR_REG(base)                       ((base)->TCR)
-#define ENET_PALR_REG(base)                      ((base)->PALR)
-#define ENET_PAUR_REG(base)                      ((base)->PAUR)
-#define ENET_OPD_REG(base)                       ((base)->OPD)
-#define ENET_IAUR_REG(base)                      ((base)->IAUR)
-#define ENET_IALR_REG(base)                      ((base)->IALR)
-#define ENET_GAUR_REG(base)                      ((base)->GAUR)
-#define ENET_GALR_REG(base)                      ((base)->GALR)
-#define ENET_TFWR_REG(base)                      ((base)->TFWR)
-#define ENET_RDSR_REG(base)                      ((base)->RDSR)
-#define ENET_TDSR_REG(base)                      ((base)->TDSR)
-#define ENET_MRBR_REG(base)                      ((base)->MRBR)
-#define ENET_RSFL_REG(base)                      ((base)->RSFL)
-#define ENET_RSEM_REG(base)                      ((base)->RSEM)
-#define ENET_RAEM_REG(base)                      ((base)->RAEM)
-#define ENET_RAFL_REG(base)                      ((base)->RAFL)
-#define ENET_TSEM_REG(base)                      ((base)->TSEM)
-#define ENET_TAEM_REG(base)                      ((base)->TAEM)
-#define ENET_TAFL_REG(base)                      ((base)->TAFL)
-#define ENET_TIPG_REG(base)                      ((base)->TIPG)
-#define ENET_FTRL_REG(base)                      ((base)->FTRL)
-#define ENET_TACC_REG(base)                      ((base)->TACC)
-#define ENET_RACC_REG(base)                      ((base)->RACC)
-#define ENET_RMON_T_DROP_REG(base)               ((base)->RMON_T_DROP)
-#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
-#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
-#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
-#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
-#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
-#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
-#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
-#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
-#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
-#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
-#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
-#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
-#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
-#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
-#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
-#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
-#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
-#define ENET_IEEE_T_DROP_REG(base)               ((base)->IEEE_T_DROP)
-#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
-#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
-#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
-#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
-#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
-#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
-#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
-#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
-#define ENET_IEEE_T_SQE_REG(base)                ((base)->IEEE_T_SQE)
-#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
-#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
-#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
-#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
-#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
-#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
-#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
-#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
-#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
-#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
-#define ENET_RMON_R_RESVD_0_REG(base)            ((base)->RMON_R_RESVD_0)
-#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
-#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
-#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
-#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
-#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
-#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
-#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
-#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
-#define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
-#define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
-#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
-#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
-#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
-#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
-#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
-#define ENET_ATCR_REG(base)                      ((base)->ATCR)
-#define ENET_ATVR_REG(base)                      ((base)->ATVR)
-#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
-#define ENET_ATPER_REG(base)                     ((base)->ATPER)
-#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
-#define ENET_ATINC_REG(base)                     ((base)->ATINC)
-#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
-#define ENET_TGSR_REG(base)                      ((base)->TGSR)
-#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
-#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
-
-/*!
- * @}
- */ /* end of group ENET_Register_Accessor_Macros */
-
+} ENET_Type;
 
 /* ----------------------------------------------------------------------------
    -- ENET Register Masks
@@ -5232,551 +4758,739 @@ typedef struct {
  * @{
  */
 
-/* EIR Bit Fields */
-#define ENET_EIR_TS_TIMER_MASK                   0x8000u
-#define ENET_EIR_TS_TIMER_SHIFT                  15
-#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
-#define ENET_EIR_TS_AVAIL_SHIFT                  16
-#define ENET_EIR_WAKEUP_MASK                     0x20000u
-#define ENET_EIR_WAKEUP_SHIFT                    17
-#define ENET_EIR_PLR_MASK                        0x40000u
-#define ENET_EIR_PLR_SHIFT                       18
-#define ENET_EIR_UN_MASK                         0x80000u
-#define ENET_EIR_UN_SHIFT                        19
-#define ENET_EIR_RL_MASK                         0x100000u
-#define ENET_EIR_RL_SHIFT                        20
-#define ENET_EIR_LC_MASK                         0x200000u
-#define ENET_EIR_LC_SHIFT                        21
-#define ENET_EIR_EBERR_MASK                      0x400000u
-#define ENET_EIR_EBERR_SHIFT                     22
-#define ENET_EIR_MII_MASK                        0x800000u
-#define ENET_EIR_MII_SHIFT                       23
-#define ENET_EIR_RXB_MASK                        0x1000000u
-#define ENET_EIR_RXB_SHIFT                       24
-#define ENET_EIR_RXF_MASK                        0x2000000u
-#define ENET_EIR_RXF_SHIFT                       25
-#define ENET_EIR_TXB_MASK                        0x4000000u
-#define ENET_EIR_TXB_SHIFT                       26
-#define ENET_EIR_TXF_MASK                        0x8000000u
-#define ENET_EIR_TXF_SHIFT                       27
-#define ENET_EIR_GRA_MASK                        0x10000000u
-#define ENET_EIR_GRA_SHIFT                       28
-#define ENET_EIR_BABT_MASK                       0x20000000u
-#define ENET_EIR_BABT_SHIFT                      29
-#define ENET_EIR_BABR_MASK                       0x40000000u
-#define ENET_EIR_BABR_SHIFT                      30
-/* EIMR Bit Fields */
-#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
-#define ENET_EIMR_TS_TIMER_SHIFT                 15
-#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
-#define ENET_EIMR_TS_AVAIL_SHIFT                 16
-#define ENET_EIMR_WAKEUP_MASK                    0x20000u
-#define ENET_EIMR_WAKEUP_SHIFT                   17
-#define ENET_EIMR_PLR_MASK                       0x40000u
-#define ENET_EIMR_PLR_SHIFT                      18
-#define ENET_EIMR_UN_MASK                        0x80000u
-#define ENET_EIMR_UN_SHIFT                       19
-#define ENET_EIMR_RL_MASK                        0x100000u
-#define ENET_EIMR_RL_SHIFT                       20
-#define ENET_EIMR_LC_MASK                        0x200000u
-#define ENET_EIMR_LC_SHIFT                       21
-#define ENET_EIMR_EBERR_MASK                     0x400000u
-#define ENET_EIMR_EBERR_SHIFT                    22
-#define ENET_EIMR_MII_MASK                       0x800000u
-#define ENET_EIMR_MII_SHIFT                      23
-#define ENET_EIMR_RXB_MASK                       0x1000000u
-#define ENET_EIMR_RXB_SHIFT                      24
-#define ENET_EIMR_RXF_MASK                       0x2000000u
-#define ENET_EIMR_RXF_SHIFT                      25
-#define ENET_EIMR_TXB_MASK                       0x4000000u
-#define ENET_EIMR_TXB_SHIFT                      26
-#define ENET_EIMR_TXF_MASK                       0x8000000u
-#define ENET_EIMR_TXF_SHIFT                      27
-#define ENET_EIMR_GRA_MASK                       0x10000000u
-#define ENET_EIMR_GRA_SHIFT                      28
-#define ENET_EIMR_BABT_MASK                      0x20000000u
-#define ENET_EIMR_BABT_SHIFT                     29
-#define ENET_EIMR_BABR_MASK                      0x40000000u
-#define ENET_EIMR_BABR_SHIFT                     30
-/* RDAR Bit Fields */
-#define ENET_RDAR_RDAR_MASK                      0x1000000u
-#define ENET_RDAR_RDAR_SHIFT                     24
-/* TDAR Bit Fields */
-#define ENET_TDAR_TDAR_MASK                      0x1000000u
-#define ENET_TDAR_TDAR_SHIFT                     24
-/* ECR Bit Fields */
-#define ENET_ECR_RESET_MASK                      0x1u
-#define ENET_ECR_RESET_SHIFT                     0
-#define ENET_ECR_ETHEREN_MASK                    0x2u
-#define ENET_ECR_ETHEREN_SHIFT                   1
-#define ENET_ECR_MAGICEN_MASK                    0x4u
-#define ENET_ECR_MAGICEN_SHIFT                   2
-#define ENET_ECR_SLEEP_MASK                      0x8u
-#define ENET_ECR_SLEEP_SHIFT                     3
-#define ENET_ECR_EN1588_MASK                     0x10u
-#define ENET_ECR_EN1588_SHIFT                    4
-#define ENET_ECR_DBGEN_MASK                      0x40u
-#define ENET_ECR_DBGEN_SHIFT                     6
-#define ENET_ECR_STOPEN_MASK                     0x80u
-#define ENET_ECR_STOPEN_SHIFT                    7
-#define ENET_ECR_DBSWP_MASK                      0x100u
-#define ENET_ECR_DBSWP_SHIFT                     8
-/* MMFR Bit Fields */
-#define ENET_MMFR_DATA_MASK                      0xFFFFu
-#define ENET_MMFR_DATA_SHIFT                     0
-#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
-#define ENET_MMFR_TA_MASK                        0x30000u
-#define ENET_MMFR_TA_SHIFT                       16
-#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
-#define ENET_MMFR_RA_MASK                        0x7C0000u
-#define ENET_MMFR_RA_SHIFT                       18
-#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
-#define ENET_MMFR_PA_MASK                        0xF800000u
-#define ENET_MMFR_PA_SHIFT                       23
-#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
-#define ENET_MMFR_OP_MASK                        0x30000000u
-#define ENET_MMFR_OP_SHIFT                       28
-#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
-#define ENET_MMFR_ST_MASK                        0xC0000000u
-#define ENET_MMFR_ST_SHIFT                       30
-#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
-/* MSCR Bit Fields */
-#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
-#define ENET_MSCR_MII_SPEED_SHIFT                1
-#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
-#define ENET_MSCR_DIS_PRE_MASK                   0x80u
-#define ENET_MSCR_DIS_PRE_SHIFT                  7
-#define ENET_MSCR_HOLDTIME_MASK                  0x700u
-#define ENET_MSCR_HOLDTIME_SHIFT                 8
-#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
-/* MIBC Bit Fields */
-#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
-#define ENET_MIBC_MIB_CLEAR_SHIFT                29
-#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
-#define ENET_MIBC_MIB_IDLE_SHIFT                 30
-#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
-#define ENET_MIBC_MIB_DIS_SHIFT                  31
-/* RCR Bit Fields */
-#define ENET_RCR_LOOP_MASK                       0x1u
-#define ENET_RCR_LOOP_SHIFT                      0
-#define ENET_RCR_DRT_MASK                        0x2u
-#define ENET_RCR_DRT_SHIFT                       1
-#define ENET_RCR_MII_MODE_MASK                   0x4u
-#define ENET_RCR_MII_MODE_SHIFT                  2
-#define ENET_RCR_PROM_MASK                       0x8u
-#define ENET_RCR_PROM_SHIFT                      3
-#define ENET_RCR_BC_REJ_MASK                     0x10u
-#define ENET_RCR_BC_REJ_SHIFT                    4
-#define ENET_RCR_FCE_MASK                        0x20u
-#define ENET_RCR_FCE_SHIFT                       5
-#define ENET_RCR_RMII_MODE_MASK                  0x100u
-#define ENET_RCR_RMII_MODE_SHIFT                 8
-#define ENET_RCR_RMII_10T_MASK                   0x200u
-#define ENET_RCR_RMII_10T_SHIFT                  9
-#define ENET_RCR_PADEN_MASK                      0x1000u
-#define ENET_RCR_PADEN_SHIFT                     12
-#define ENET_RCR_PAUFWD_MASK                     0x2000u
-#define ENET_RCR_PAUFWD_SHIFT                    13
-#define ENET_RCR_CRCFWD_MASK                     0x4000u
-#define ENET_RCR_CRCFWD_SHIFT                    14
-#define ENET_RCR_CFEN_MASK                       0x8000u
-#define ENET_RCR_CFEN_SHIFT                      15
-#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
-#define ENET_RCR_MAX_FL_SHIFT                    16
-#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
-#define ENET_RCR_NLC_MASK                        0x40000000u
-#define ENET_RCR_NLC_SHIFT                       30
-#define ENET_RCR_GRS_MASK                        0x80000000u
-#define ENET_RCR_GRS_SHIFT                       31
-/* TCR Bit Fields */
-#define ENET_TCR_GTS_MASK                        0x1u
-#define ENET_TCR_GTS_SHIFT                       0
-#define ENET_TCR_FDEN_MASK                       0x4u
-#define ENET_TCR_FDEN_SHIFT                      2
-#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
-#define ENET_TCR_TFC_PAUSE_SHIFT                 3
-#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
-#define ENET_TCR_RFC_PAUSE_SHIFT                 4
-#define ENET_TCR_ADDSEL_MASK                     0xE0u
-#define ENET_TCR_ADDSEL_SHIFT                    5
-#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
-#define ENET_TCR_ADDINS_MASK                     0x100u
-#define ENET_TCR_ADDINS_SHIFT                    8
-#define ENET_TCR_CRCFWD_MASK                     0x200u
-#define ENET_TCR_CRCFWD_SHIFT                    9
-/* PALR Bit Fields */
-#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
-#define ENET_PALR_PADDR1_SHIFT                   0
-#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
-/* PAUR Bit Fields */
-#define ENET_PAUR_TYPE_MASK                      0xFFFFu
-#define ENET_PAUR_TYPE_SHIFT                     0
-#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
-#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
-#define ENET_PAUR_PADDR2_SHIFT                   16
-#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
-/* OPD Bit Fields */
-#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
-#define ENET_OPD_PAUSE_DUR_SHIFT                 0
-#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
-#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
-#define ENET_OPD_OPCODE_SHIFT                    16
-#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
-/* IAUR Bit Fields */
-#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
-#define ENET_IAUR_IADDR1_SHIFT                   0
-#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
-/* IALR Bit Fields */
-#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
-#define ENET_IALR_IADDR2_SHIFT                   0
-#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
-/* GAUR Bit Fields */
-#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
-#define ENET_GAUR_GADDR1_SHIFT                   0
-#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
-/* GALR Bit Fields */
-#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
-#define ENET_GALR_GADDR2_SHIFT                   0
-#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
-/* TFWR Bit Fields */
-#define ENET_TFWR_TFWR_MASK                      0x3Fu
-#define ENET_TFWR_TFWR_SHIFT                     0
-#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
-#define ENET_TFWR_STRFWD_MASK                    0x100u
-#define ENET_TFWR_STRFWD_SHIFT                   8
-/* RDSR Bit Fields */
-#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
-#define ENET_RDSR_R_DES_START_SHIFT              3
-#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
-/* TDSR Bit Fields */
-#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
-#define ENET_TDSR_X_DES_START_SHIFT              3
-#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
-/* MRBR Bit Fields */
-#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
-#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
-#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
-/* RSFL Bit Fields */
-#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
-#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
-#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
-/* RSEM Bit Fields */
-#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
-#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
-#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
-/* RAEM Bit Fields */
-#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
-#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
-#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
-/* RAFL Bit Fields */
-#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
-#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
-#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
-/* TSEM Bit Fields */
-#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
-#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
-#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
-/* TAEM Bit Fields */
-#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
-#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
-#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
-/* TAFL Bit Fields */
-#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
-#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
-#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
-/* TIPG Bit Fields */
-#define ENET_TIPG_IPG_MASK                       0x1Fu
-#define ENET_TIPG_IPG_SHIFT                      0
-#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
-/* FTRL Bit Fields */
-#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
-#define ENET_FTRL_TRUNC_FL_SHIFT                 0
-#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
-/* TACC Bit Fields */
-#define ENET_TACC_SHIFT16_MASK                   0x1u
-#define ENET_TACC_SHIFT16_SHIFT                  0
-#define ENET_TACC_IPCHK_MASK                     0x8u
-#define ENET_TACC_IPCHK_SHIFT                    3
-#define ENET_TACC_PROCHK_MASK                    0x10u
-#define ENET_TACC_PROCHK_SHIFT                   4
-/* RACC Bit Fields */
-#define ENET_RACC_PADREM_MASK                    0x1u
-#define ENET_RACC_PADREM_SHIFT                   0
-#define ENET_RACC_IPDIS_MASK                     0x2u
-#define ENET_RACC_IPDIS_SHIFT                    1
-#define ENET_RACC_PRODIS_MASK                    0x4u
-#define ENET_RACC_PRODIS_SHIFT                   2
-#define ENET_RACC_LINEDIS_MASK                   0x40u
-#define ENET_RACC_LINEDIS_SHIFT                  6
-#define ENET_RACC_SHIFT16_MASK                   0x80u
-#define ENET_RACC_SHIFT16_SHIFT                  7
-/* RMON_T_PACKETS Bit Fields */
-#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
-#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
-#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
-/* RMON_T_BC_PKT Bit Fields */
-#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
-#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
-#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
-/* RMON_T_MC_PKT Bit Fields */
-#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
-#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
-#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
-/* RMON_T_CRC_ALIGN Bit Fields */
-#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
-#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
-#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
-/* RMON_T_UNDERSIZE Bit Fields */
-#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
-#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
-#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
-/* RMON_T_OVERSIZE Bit Fields */
-#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
-#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
-#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
-/* RMON_T_FRAG Bit Fields */
-#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
-#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
-#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
-/* RMON_T_JAB Bit Fields */
-#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
-#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
-#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
-/* RMON_T_COL Bit Fields */
-#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
-#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
-#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
-/* RMON_T_P64 Bit Fields */
-#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
-#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
-#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
-/* RMON_T_P65TO127 Bit Fields */
-#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
-#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
-#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
-/* RMON_T_P128TO255 Bit Fields */
-#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
-#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
-#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
-/* RMON_T_P256TO511 Bit Fields */
-#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
-#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
-#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
-/* RMON_T_P512TO1023 Bit Fields */
-#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
-#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
-#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
-/* RMON_T_P1024TO2047 Bit Fields */
-#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
-#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
-#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
-/* RMON_T_P_GTE2048 Bit Fields */
-#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
-#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
-#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
-/* RMON_T_OCTETS Bit Fields */
-#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
-#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
-#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
-/* IEEE_T_FRAME_OK Bit Fields */
-#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
-#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
-#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
-/* IEEE_T_1COL Bit Fields */
-#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
-#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
-#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
-/* IEEE_T_MCOL Bit Fields */
-#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
-#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
-#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
-/* IEEE_T_DEF Bit Fields */
-#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
-#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
-#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
-/* IEEE_T_LCOL Bit Fields */
-#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
-#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
-#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
-/* IEEE_T_EXCOL Bit Fields */
-#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
-#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
-#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
-/* IEEE_T_MACERR Bit Fields */
-#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
-#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
-#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
-/* IEEE_T_CSERR Bit Fields */
-#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
-#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
-#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
-/* IEEE_T_FDXFC Bit Fields */
-#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
-#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
-#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
-/* IEEE_T_OCTETS_OK Bit Fields */
-#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
-#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
-#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
-/* RMON_R_PACKETS Bit Fields */
-#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
-#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
-#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
-/* RMON_R_BC_PKT Bit Fields */
-#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
-#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
-#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
-/* RMON_R_MC_PKT Bit Fields */
-#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
-#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
-#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
-/* RMON_R_CRC_ALIGN Bit Fields */
-#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
-#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
-#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
-/* RMON_R_UNDERSIZE Bit Fields */
-#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
-#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
-#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
-/* RMON_R_OVERSIZE Bit Fields */
-#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
-#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
-#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
-/* RMON_R_FRAG Bit Fields */
-#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
-#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
-#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
-/* RMON_R_JAB Bit Fields */
-#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
-#define ENET_RMON_R_JAB_COUNT_SHIFT              0
-#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
-/* RMON_R_P64 Bit Fields */
-#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
-#define ENET_RMON_R_P64_COUNT_SHIFT              0
-#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
-/* RMON_R_P65TO127 Bit Fields */
-#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
-#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
-#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
-/* RMON_R_P128TO255 Bit Fields */
-#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
-#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
-#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
-/* RMON_R_P256TO511 Bit Fields */
-#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
-#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
-#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
-/* RMON_R_P512TO1023 Bit Fields */
-#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
-#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
-#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
-/* RMON_R_P1024TO2047 Bit Fields */
-#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
-#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
-#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
-/* RMON_R_P_GTE2048 Bit Fields */
-#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
-#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
-#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
-/* RMON_R_OCTETS Bit Fields */
-#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
-#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
-#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
-/* IEEE_R_DROP Bit Fields */
-#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
-#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
-#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
-/* IEEE_R_FRAME_OK Bit Fields */
-#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
-#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
-#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
-/* IEEE_R_CRC Bit Fields */
-#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
-#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
-#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
-/* IEEE_R_ALIGN Bit Fields */
-#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
-#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
-#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
-/* IEEE_R_MACERR Bit Fields */
-#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
-#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
-#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
-/* IEEE_R_FDXFC Bit Fields */
-#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
-#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
-#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
-/* IEEE_R_OCTETS_OK Bit Fields */
-#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
-#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
-#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
-/* ATCR Bit Fields */
-#define ENET_ATCR_EN_MASK                        0x1u
-#define ENET_ATCR_EN_SHIFT                       0
-#define ENET_ATCR_OFFEN_MASK                     0x4u
-#define ENET_ATCR_OFFEN_SHIFT                    2
-#define ENET_ATCR_OFFRST_MASK                    0x8u
-#define ENET_ATCR_OFFRST_SHIFT                   3
-#define ENET_ATCR_PEREN_MASK                     0x10u
-#define ENET_ATCR_PEREN_SHIFT                    4
-#define ENET_ATCR_PINPER_MASK                    0x80u
-#define ENET_ATCR_PINPER_SHIFT                   7
-#define ENET_ATCR_RESTART_MASK                   0x200u
-#define ENET_ATCR_RESTART_SHIFT                  9
-#define ENET_ATCR_CAPTURE_MASK                   0x800u
-#define ENET_ATCR_CAPTURE_SHIFT                  11
-#define ENET_ATCR_SLAVE_MASK                     0x2000u
-#define ENET_ATCR_SLAVE_SHIFT                    13
-/* ATVR Bit Fields */
-#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
-#define ENET_ATVR_ATIME_SHIFT                    0
-#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
-/* ATOFF Bit Fields */
-#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
-#define ENET_ATOFF_OFFSET_SHIFT                  0
-#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
-/* ATPER Bit Fields */
-#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
-#define ENET_ATPER_PERIOD_SHIFT                  0
-#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
-/* ATCOR Bit Fields */
-#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
-#define ENET_ATCOR_COR_SHIFT                     0
-#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
-/* ATINC Bit Fields */
-#define ENET_ATINC_INC_MASK                      0x7Fu
-#define ENET_ATINC_INC_SHIFT                     0
-#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
-#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
-#define ENET_ATINC_INC_CORR_SHIFT                8
-#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
-/* ATSTMP Bit Fields */
-#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
-#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
-#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
-/* TGSR Bit Fields */
-#define ENET_TGSR_TF0_MASK                       0x1u
-#define ENET_TGSR_TF0_SHIFT                      0
-#define ENET_TGSR_TF1_MASK                       0x2u
-#define ENET_TGSR_TF1_SHIFT                      1
-#define ENET_TGSR_TF2_MASK                       0x4u
-#define ENET_TGSR_TF2_SHIFT                      2
-#define ENET_TGSR_TF3_MASK                       0x8u
-#define ENET_TGSR_TF3_SHIFT                      3
-/* TCSR Bit Fields */
-#define ENET_TCSR_TDRE_MASK                      0x1u
-#define ENET_TCSR_TDRE_SHIFT                     0
-#define ENET_TCSR_TMODE_MASK                     0x3Cu
-#define ENET_TCSR_TMODE_SHIFT                    2
-#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
-#define ENET_TCSR_TIE_MASK                       0x40u
-#define ENET_TCSR_TIE_SHIFT                      6
-#define ENET_TCSR_TF_MASK                        0x80u
-#define ENET_TCSR_TF_SHIFT                       7
-/* TCCR Bit Fields */
-#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
-#define ENET_TCCR_TCC_SHIFT                      0
-#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+/*! @name EIR - Interrupt Event Register */
+#define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
+#define ENET_EIR_TS_TIMER_SHIFT                  (15U)
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
+#define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     (0x20000U)
+#define ENET_EIR_WAKEUP_SHIFT                    (17U)
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        (0x40000U)
+#define ENET_EIR_PLR_SHIFT                       (18U)
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         (0x80000U)
+#define ENET_EIR_UN_SHIFT                        (19U)
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         (0x100000U)
+#define ENET_EIR_RL_SHIFT                        (20U)
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         (0x200000U)
+#define ENET_EIR_LC_SHIFT                        (21U)
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      (0x400000U)
+#define ENET_EIR_EBERR_SHIFT                     (22U)
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        (0x800000U)
+#define ENET_EIR_MII_SHIFT                       (23U)
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        (0x1000000U)
+#define ENET_EIR_RXB_SHIFT                       (24U)
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        (0x2000000U)
+#define ENET_EIR_RXF_SHIFT                       (25U)
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        (0x4000000U)
+#define ENET_EIR_TXB_SHIFT                       (26U)
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        (0x8000000U)
+#define ENET_EIR_TXF_SHIFT                       (27U)
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        (0x10000000U)
+#define ENET_EIR_GRA_SHIFT                       (28U)
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       (0x20000000U)
+#define ENET_EIR_BABT_SHIFT                      (29U)
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       (0x40000000U)
+#define ENET_EIR_BABR_SHIFT                      (30U)
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
+
+/*! @name EIMR - Interrupt Mask Register */
+#define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
+#define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
+#define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
+#define ENET_EIMR_WAKEUP_SHIFT                   (17U)
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       (0x40000U)
+#define ENET_EIMR_PLR_SHIFT                      (18U)
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        (0x80000U)
+#define ENET_EIMR_UN_SHIFT                       (19U)
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        (0x100000U)
+#define ENET_EIMR_RL_SHIFT                       (20U)
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        (0x200000U)
+#define ENET_EIMR_LC_SHIFT                       (21U)
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     (0x400000U)
+#define ENET_EIMR_EBERR_SHIFT                    (22U)
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       (0x800000U)
+#define ENET_EIMR_MII_SHIFT                      (23U)
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       (0x1000000U)
+#define ENET_EIMR_RXB_SHIFT                      (24U)
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       (0x2000000U)
+#define ENET_EIMR_RXF_SHIFT                      (25U)
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       (0x4000000U)
+#define ENET_EIMR_TXB_SHIFT                      (26U)
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       (0x8000000U)
+#define ENET_EIMR_TXF_SHIFT                      (27U)
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       (0x10000000U)
+#define ENET_EIMR_GRA_SHIFT                      (28U)
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      (0x20000000U)
+#define ENET_EIMR_BABT_SHIFT                     (29U)
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      (0x40000000U)
+#define ENET_EIMR_BABR_SHIFT                     (30U)
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
+
+/*! @name RDAR - Receive Descriptor Active Register */
+#define ENET_RDAR_RDAR_MASK                      (0x1000000U)
+#define ENET_RDAR_RDAR_SHIFT                     (24U)
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
+
+/*! @name TDAR - Transmit Descriptor Active Register */
+#define ENET_TDAR_TDAR_MASK                      (0x1000000U)
+#define ENET_TDAR_TDAR_SHIFT                     (24U)
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
+
+/*! @name ECR - Ethernet Control Register */
+#define ENET_ECR_RESET_MASK                      (0x1U)
+#define ENET_ECR_RESET_SHIFT                     (0U)
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    (0x2U)
+#define ENET_ECR_ETHEREN_SHIFT                   (1U)
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    (0x4U)
+#define ENET_ECR_MAGICEN_SHIFT                   (2U)
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      (0x8U)
+#define ENET_ECR_SLEEP_SHIFT                     (3U)
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     (0x10U)
+#define ENET_ECR_EN1588_SHIFT                    (4U)
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      (0x40U)
+#define ENET_ECR_DBGEN_SHIFT                     (6U)
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     (0x80U)
+#define ENET_ECR_STOPEN_SHIFT                    (7U)
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      (0x100U)
+#define ENET_ECR_DBSWP_SHIFT                     (8U)
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
+
+/*! @name MMFR - MII Management Frame Register */
+#define ENET_MMFR_DATA_MASK                      (0xFFFFU)
+#define ENET_MMFR_DATA_SHIFT                     (0U)
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        (0x30000U)
+#define ENET_MMFR_TA_SHIFT                       (16U)
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        (0x7C0000U)
+#define ENET_MMFR_RA_SHIFT                       (18U)
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        (0xF800000U)
+#define ENET_MMFR_PA_SHIFT                       (23U)
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        (0x30000000U)
+#define ENET_MMFR_OP_SHIFT                       (28U)
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        (0xC0000000U)
+#define ENET_MMFR_ST_SHIFT                       (30U)
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
+
+/*! @name MSCR - MII Speed Control Register */
+#define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
+#define ENET_MSCR_MII_SPEED_SHIFT                (1U)
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
+#define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
+#define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
+
+/*! @name MIBC - MIB Control Register */
+#define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
+#define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
+#define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
+#define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
+
+/*! @name RCR - Receive Control Register */
+#define ENET_RCR_LOOP_MASK                       (0x1U)
+#define ENET_RCR_LOOP_SHIFT                      (0U)
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        (0x2U)
+#define ENET_RCR_DRT_SHIFT                       (1U)
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   (0x4U)
+#define ENET_RCR_MII_MODE_SHIFT                  (2U)
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       (0x8U)
+#define ENET_RCR_PROM_SHIFT                      (3U)
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     (0x10U)
+#define ENET_RCR_BC_REJ_SHIFT                    (4U)
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        (0x20U)
+#define ENET_RCR_FCE_SHIFT                       (5U)
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  (0x100U)
+#define ENET_RCR_RMII_MODE_SHIFT                 (8U)
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   (0x200U)
+#define ENET_RCR_RMII_10T_SHIFT                  (9U)
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      (0x1000U)
+#define ENET_RCR_PADEN_SHIFT                     (12U)
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     (0x2000U)
+#define ENET_RCR_PAUFWD_SHIFT                    (13U)
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     (0x4000U)
+#define ENET_RCR_CRCFWD_SHIFT                    (14U)
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       (0x8000U)
+#define ENET_RCR_CFEN_SHIFT                      (15U)
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
+#define ENET_RCR_MAX_FL_SHIFT                    (16U)
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        (0x40000000U)
+#define ENET_RCR_NLC_SHIFT                       (30U)
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        (0x80000000U)
+#define ENET_RCR_GRS_SHIFT                       (31U)
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
+
+/*! @name TCR - Transmit Control Register */
+#define ENET_TCR_GTS_MASK                        (0x1U)
+#define ENET_TCR_GTS_SHIFT                       (0U)
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       (0x4U)
+#define ENET_TCR_FDEN_SHIFT                      (2U)
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
+#define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
+#define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     (0xE0U)
+#define ENET_TCR_ADDSEL_SHIFT                    (5U)
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     (0x100U)
+#define ENET_TCR_ADDINS_SHIFT                    (8U)
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     (0x200U)
+#define ENET_TCR_CRCFWD_SHIFT                    (9U)
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
+
+/*! @name PALR - Physical Address Lower Register */
+#define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_PALR_PADDR1_SHIFT                   (0U)
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
+
+/*! @name PAUR - Physical Address Upper Register */
+#define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
+#define ENET_PAUR_TYPE_SHIFT                     (0U)
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
+#define ENET_PAUR_PADDR2_SHIFT                   (16U)
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
+
+/*! @name OPD - Opcode/Pause Duration Register */
+#define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
+#define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
+#define ENET_OPD_OPCODE_SHIFT                    (16U)
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
+
+/*! @name IAUR - Descriptor Individual Upper Address Register */
+#define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_IAUR_IADDR1_SHIFT                   (0U)
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
+
+/*! @name IALR - Descriptor Individual Lower Address Register */
+#define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
+#define ENET_IALR_IADDR2_SHIFT                   (0U)
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
+
+/*! @name GAUR - Descriptor Group Upper Address Register */
+#define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_GAUR_GADDR1_SHIFT                   (0U)
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
+
+/*! @name GALR - Descriptor Group Lower Address Register */
+#define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
+#define ENET_GALR_GADDR2_SHIFT                   (0U)
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
+
+/*! @name TFWR - Transmit FIFO Watermark Register */
+#define ENET_TFWR_TFWR_MASK                      (0x3FU)
+#define ENET_TFWR_TFWR_SHIFT                     (0U)
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    (0x100U)
+#define ENET_TFWR_STRFWD_SHIFT                   (8U)
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
+
+/*! @name RDSR - Receive Descriptor Ring Start Register */
+#define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_RDSR_R_DES_START_SHIFT              (3U)
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
+
+/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
+#define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_TDSR_X_DES_START_SHIFT              (3U)
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
+
+/*! @name MRBR - Maximum Receive Buffer Size Register */
+#define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
+
+/*! @name RSFL - Receive FIFO Section Full Threshold */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           (0xFFU)
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
+
+/*! @name RSEM - Receive FIFO Section Empty Threshold */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
+
+/*! @name RAEM - Receive FIFO Almost Empty Threshold */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+
+/*! @name RAFL - Receive FIFO Almost Full Threshold */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
+
+/*! @name TSEM - Transmit FIFO Section Empty Threshold */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
+
+/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+
+/*! @name TAFL - Transmit FIFO Almost Full Threshold */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
+
+/*! @name TIPG - Transmit Inter-Packet Gap */
+#define ENET_TIPG_IPG_MASK                       (0x1FU)
+#define ENET_TIPG_IPG_SHIFT                      (0U)
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
+
+/*! @name FTRL - Frame Truncation Length */
+#define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
+#define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
+
+/*! @name TACC - Transmit Accelerator Function Configuration */
+#define ENET_TACC_SHIFT16_MASK                   (0x1U)
+#define ENET_TACC_SHIFT16_SHIFT                  (0U)
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     (0x8U)
+#define ENET_TACC_IPCHK_SHIFT                    (3U)
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    (0x10U)
+#define ENET_TACC_PROCHK_SHIFT                   (4U)
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
+
+/*! @name RACC - Receive Accelerator Function Configuration */
+#define ENET_RACC_PADREM_MASK                    (0x1U)
+#define ENET_RACC_PADREM_SHIFT                   (0U)
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     (0x2U)
+#define ENET_RACC_IPDIS_SHIFT                    (1U)
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    (0x4U)
+#define ENET_RACC_PRODIS_SHIFT                   (2U)
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   (0x40U)
+#define ENET_RACC_LINEDIS_SHIFT                  (6U)
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   (0x80U)
+#define ENET_RACC_SHIFT16_SHIFT                  (7U)
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
+
+/*! @name RMON_T_PACKETS - RMON Tx packet count (RMON_T_PACKETS) */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
+
+/*! @name RMON_T_BC_PKT - RMON Tx Broadcast Packets (RMON_T_BC_PKT) */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+
+/*! @name RMON_T_MC_PKT - RMON Tx Multicast Packets (RMON_T_MC_PKT) */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+
+/*! @name RMON_T_CRC_ALIGN - RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN) */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+
+/*! @name RMON_T_UNDERSIZE - RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE) */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+
+/*! @name RMON_T_OVERSIZE - RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE) */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+
+/*! @name RMON_T_FRAG - RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG) */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
+
+/*! @name RMON_T_JAB - RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB) */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
+
+/*! @name RMON_T_COL - RMON Tx collision count (RMON_T_COL) */
+#define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
+
+/*! @name RMON_T_P64 - RMON Tx 64 byte packets (RMON_T_P64) */
+#define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
+
+/*! @name RMON_T_P65TO127 - RMON Tx 65 to 127 byte packets (RMON_T_P65TO127) */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
+
+/*! @name RMON_T_P128TO255 - RMON Tx 128 to 255 byte packets (RMON_T_P128TO255) */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
+
+/*! @name RMON_T_P256TO511 - RMON Tx 256 to 511 byte packets (RMON_T_P256TO511) */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
+
+/*! @name RMON_T_P512TO1023 - RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023) */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+
+/*! @name RMON_T_P1024TO2047 - RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047) */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+
+/*! @name RMON_T_P_GTE2048 - RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048) */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+
+/*! @name RMON_T_OCTETS - RMON Tx Octets (RMON_T_OCTETS) */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
+
+/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK (IEEE_T_FRAME_OK) */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+
+/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision (IEEE_T_1COL) */
+#define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
+
+/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions (IEEE_T_MCOL) */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
+
+/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay (IEEE_T_DEF) */
+#define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
+
+/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision (IEEE_T_LCOL) */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
+
+/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL) */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
+
+/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR) */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
+
+/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR) */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
+
+/*! @name IEEE_T_FDXFC - Flow Control Pause frames transmitted (IEEE_T_FDXFC) */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
+
+/*! @name IEEE_T_OCTETS_OK - Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields). */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+
+/*! @name RMON_R_PACKETS - RMON Rx packet count (RMON_R_PACKETS) */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
+
+/*! @name RMON_R_BC_PKT - RMON Rx Broadcast Packets (RMON_R_BC_PKT) */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
+
+/*! @name RMON_R_MC_PKT - RMON Rx Multicast Packets (RMON_R_MC_PKT) */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
+
+/*! @name RMON_R_CRC_ALIGN - RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN) */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+
+/*! @name RMON_R_UNDERSIZE - RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE) */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+
+/*! @name RMON_R_OVERSIZE - RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE) */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
+
+/*! @name RMON_R_FRAG - RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG) */
+#define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
+
+/*! @name RMON_R_JAB - RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB) */
+#define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
+
+/*! @name RMON_R_P64 - RMON Rx 64 byte packets (RMON_R_P64) */
+#define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
+
+/*! @name RMON_R_P65TO127 - RMON Rx 65 to 127 byte packets (RMON_R_P65TO127) */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
+
+/*! @name RMON_R_P128TO255 - RMON Rx 128 to 255 byte packets (RMON_R_P128TO255) */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
+
+/*! @name RMON_R_P256TO511 - RMON Rx 256 to 511 byte packets (RMON_R_P256TO511) */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
+
+/*! @name RMON_R_P512TO1023 - RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023) */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
+
+/*! @name RMON_R_P1024TO2047 - RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047) */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
+
+/*! @name RMON_R_P_GTE2048 - RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048) */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
+
+/*! @name RMON_R_OCTETS - RMON Rx Octets (RMON_R_OCTETS) */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
+
+/*! @name IEEE_R_DROP - Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments. */
+#define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
+
+/*! @name IEEE_R_FRAME_OK - Frames Received OK (IEEE_R_FRAME_OK) */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+
+/*! @name IEEE_R_CRC - Frames Received with CRC Error (IEEE_R_CRC) */
+#define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
+
+/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error (IEEE_R_ALIGN) */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
+
+/*! @name IEEE_R_MACERR - Receive Fifo Overflow count (IEEE_R_MACERR) */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
+
+/*! @name IEEE_R_FDXFC - Flow Control Pause frames received (IEEE_R_FDXFC) */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
+
+/*! @name IEEE_R_OCTETS_OK - Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields). */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+
+/*! @name ATCR - Timer Control Register */
+#define ENET_ATCR_EN_MASK                        (0x1U)
+#define ENET_ATCR_EN_SHIFT                       (0U)
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     (0x4U)
+#define ENET_ATCR_OFFEN_SHIFT                    (2U)
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    (0x8U)
+#define ENET_ATCR_OFFRST_SHIFT                   (3U)
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     (0x10U)
+#define ENET_ATCR_PEREN_SHIFT                    (4U)
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    (0x80U)
+#define ENET_ATCR_PINPER_SHIFT                   (7U)
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   (0x200U)
+#define ENET_ATCR_RESTART_SHIFT                  (9U)
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   (0x800U)
+#define ENET_ATCR_CAPTURE_SHIFT                  (11U)
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     (0x2000U)
+#define ENET_ATCR_SLAVE_SHIFT                    (13U)
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
+
+/*! @name ATVR - Timer Value Register */
+#define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
+#define ENET_ATVR_ATIME_SHIFT                    (0U)
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
+
+/*! @name ATOFF - Timer Offset Register */
+#define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
+#define ENET_ATOFF_OFFSET_SHIFT                  (0U)
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
+
+/*! @name ATPER - Timer Period Register */
+#define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
+#define ENET_ATPER_PERIOD_SHIFT                  (0U)
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
+
+/*! @name ATCOR - Timer Correction Register */
+#define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
+#define ENET_ATCOR_COR_SHIFT                     (0U)
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
+
+/*! @name ATINC - Time-Stamping Clock Period Register */
+#define ENET_ATINC_INC_MASK                      (0x7FU)
+#define ENET_ATINC_INC_SHIFT                     (0U)
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
+#define ENET_ATINC_INC_CORR_SHIFT                (8U)
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
+
+/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
+#define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
+
+/*! @name TGSR - Timer Global Status Register */
+#define ENET_TGSR_TF0_MASK                       (0x1U)
+#define ENET_TGSR_TF0_SHIFT                      (0U)
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       (0x2U)
+#define ENET_TGSR_TF1_SHIFT                      (1U)
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       (0x4U)
+#define ENET_TGSR_TF2_SHIFT                      (2U)
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       (0x8U)
+#define ENET_TGSR_TF3_SHIFT                      (3U)
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
+
+/*! @name TCSR - Timer Control Status Register */
+#define ENET_TCSR_TDRE_MASK                      (0x1U)
+#define ENET_TCSR_TDRE_SHIFT                     (0U)
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     (0x3CU)
+#define ENET_TCSR_TMODE_SHIFT                    (2U)
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       (0x40U)
+#define ENET_TCSR_TIE_SHIFT                      (6U)
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        (0x80U)
+#define ENET_TCSR_TF_SHIFT                       (7U)
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
+
+/* The count of ENET_TCSR */
+#define ENET_TCSR_COUNT                          (4U)
+
+/*! @name TCCR - Timer Compare Capture Register */
+#define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
+#define ENET_TCCR_TCC_SHIFT                      (0U)
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
+
+/* The count of ENET_TCCR */
+#define ENET_TCCR_COUNT                          (4U)
+
 
 /*!
  * @}
@@ -5788,7 +5502,6 @@ typedef struct {
 #define ENET_BASE                                (0x400C0000u)
 /** Peripheral ENET base pointer */
 #define ENET                                     ((ENET_Type *)ENET_BASE)
-#define ENET_BASE_PTR                            (ENET)
 /** Array initializer of ENET peripheral base addresses */
 #define ENET_BASE_ADDRS                          { ENET_BASE }
 /** Array initializer of ENET peripheral base pointers */
@@ -5798,129 +5511,8 @@ typedef struct {
 #define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
 #define ENET_Error_IRQS                          { ENET_Error_IRQn }
 #define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
-
-/* ----------------------------------------------------------------------------
-   -- ENET - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
- * @{
- */
-
-
-/* ENET - Register instance definitions */
-/* ENET */
-#define ENET_EIR                                 ENET_EIR_REG(ENET)
-#define ENET_EIMR                                ENET_EIMR_REG(ENET)
-#define ENET_RDAR                                ENET_RDAR_REG(ENET)
-#define ENET_TDAR                                ENET_TDAR_REG(ENET)
-#define ENET_ECR                                 ENET_ECR_REG(ENET)
-#define ENET_MMFR                                ENET_MMFR_REG(ENET)
-#define ENET_MSCR                                ENET_MSCR_REG(ENET)
-#define ENET_MIBC                                ENET_MIBC_REG(ENET)
-#define ENET_RCR                                 ENET_RCR_REG(ENET)
-#define ENET_TCR                                 ENET_TCR_REG(ENET)
-#define ENET_PALR                                ENET_PALR_REG(ENET)
-#define ENET_PAUR                                ENET_PAUR_REG(ENET)
-#define ENET_OPD                                 ENET_OPD_REG(ENET)
-#define ENET_IAUR                                ENET_IAUR_REG(ENET)
-#define ENET_IALR                                ENET_IALR_REG(ENET)
-#define ENET_GAUR                                ENET_GAUR_REG(ENET)
-#define ENET_GALR                                ENET_GALR_REG(ENET)
-#define ENET_TFWR                                ENET_TFWR_REG(ENET)
-#define ENET_RDSR                                ENET_RDSR_REG(ENET)
-#define ENET_TDSR                                ENET_TDSR_REG(ENET)
-#define ENET_MRBR                                ENET_MRBR_REG(ENET)
-#define ENET_RSFL                                ENET_RSFL_REG(ENET)
-#define ENET_RSEM                                ENET_RSEM_REG(ENET)
-#define ENET_RAEM                                ENET_RAEM_REG(ENET)
-#define ENET_RAFL                                ENET_RAFL_REG(ENET)
-#define ENET_TSEM                                ENET_TSEM_REG(ENET)
-#define ENET_TAEM                                ENET_TAEM_REG(ENET)
-#define ENET_TAFL                                ENET_TAFL_REG(ENET)
-#define ENET_TIPG                                ENET_TIPG_REG(ENET)
-#define ENET_FTRL                                ENET_FTRL_REG(ENET)
-#define ENET_TACC                                ENET_TACC_REG(ENET)
-#define ENET_RACC                                ENET_RACC_REG(ENET)
-#define ENET_RMON_T_DROP                         ENET_RMON_T_DROP_REG(ENET)
-#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
-#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
-#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
-#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
-#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
-#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
-#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
-#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
-#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
-#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
-#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
-#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
-#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
-#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
-#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
-#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
-#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
-#define ENET_IEEE_T_DROP                         ENET_IEEE_T_DROP_REG(ENET)
-#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
-#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
-#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
-#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
-#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
-#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
-#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
-#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
-#define ENET_IEEE_T_SQE                          ENET_IEEE_T_SQE_REG(ENET)
-#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
-#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
-#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
-#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
-#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
-#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
-#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
-#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
-#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
-#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
-#define ENET_RMON_R_RESVD_0                      ENET_RMON_R_RESVD_0_REG(ENET)
-#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
-#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
-#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
-#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
-#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
-#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
-#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
-#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
-#define ENET_IEEE_R_DROP                         ENET_IEEE_R_DROP_REG(ENET)
-#define ENET_IEEE_R_FRAME_OK                     ENET_IEEE_R_FRAME_OK_REG(ENET)
-#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
-#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
-#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
-#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
-#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
-#define ENET_ATCR                                ENET_ATCR_REG(ENET)
-#define ENET_ATVR                                ENET_ATVR_REG(ENET)
-#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
-#define ENET_ATPER                               ENET_ATPER_REG(ENET)
-#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
-#define ENET_ATINC                               ENET_ATINC_REG(ENET)
-#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
-#define ENET_TGSR                                ENET_TGSR_REG(ENET)
-#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
-#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
-#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
-#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
-#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
-#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
-#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
-#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
-
-/* ENET - Register array accessors */
-#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
-#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
-
-/*!
- * @}
- */ /* end of group ENET_Register_Accessor_Macros */
+/* ENET Buffer Descriptor and Buffer Address Alignment. */
+#define ENET_BUFF_ALIGNMENT                      (16U)
 
 
 /*!
@@ -5945,64 +5537,51 @@ typedef struct {
   __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
        uint8_t RESERVED_0[1];
   __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
-} EWM_Type, *EWM_MemMapPtr;
+} EWM_Type;
 
 /* ----------------------------------------------------------------------------
-   -- EWM - Register accessor macros
+   -- EWM Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @addtogroup EWM_Register_Masks EWM Register Masks
  * @{
  */
 
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN_MASK                      (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT                     (0U)
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT                     (1U)
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       (0x4U)
+#define EWM_CTRL_INEN_SHIFT                      (2U)
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      (0x8U)
+#define EWM_CTRL_INTEN_SHIFT                     (3U)
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
 
-/* EWM - Register accessors */
-#define EWM_CTRL_REG(base)                       ((base)->CTRL)
-#define EWM_SERV_REG(base)                       ((base)->SERV)
-#define EWM_CMPL_REG(base)                       ((base)->CMPL)
-#define EWM_CMPH_REG(base)                       ((base)->CMPH)
-#define EWM_CLKPRESCALER_REG(base)               ((base)->CLKPRESCALER)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK                    (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT                   (0U)
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
 
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
 
-/* ----------------------------------------------------------------------------
-   -- EWM Register Masks
-   ---------------------------------------------------------------------------- */
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
 
-/*!
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
+/*! @name CLKPRESCALER - Clock Prescaler Register */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
+#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
 
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK                      0x1u
-#define EWM_CTRL_EWMEN_SHIFT                     0
-#define EWM_CTRL_ASSIN_MASK                      0x2u
-#define EWM_CTRL_ASSIN_SHIFT                     1
-#define EWM_CTRL_INEN_MASK                       0x4u
-#define EWM_CTRL_INEN_SHIFT                      2
-#define EWM_CTRL_INTEN_MASK                      0x8u
-#define EWM_CTRL_INTEN_SHIFT                     3
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK                    0xFFu
-#define EWM_SERV_SERVICE_SHIFT                   0
-#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK                   0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT                  0
-#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK                   0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT                  0
-#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
-/* CLKPRESCALER Bit Fields */
-#define EWM_CLKPRESCALER_CLK_DIV_MASK            0xFFu
-#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           0
-#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
 
 /*!
  * @}
@@ -6014,7 +5593,6 @@ typedef struct {
 #define EWM_BASE                                 (0x40061000u)
 /** Peripheral EWM base pointer */
 #define EWM                                      ((EWM_Type *)EWM_BASE)
-#define EWM_BASE_PTR                             (EWM)
 /** Array initializer of EWM peripheral base addresses */
 #define EWM_BASE_ADDRS                           { EWM_BASE }
 /** Array initializer of EWM peripheral base pointers */
@@ -6022,29 +5600,6 @@ typedef struct {
 /** Interrupt vectors for the EWM peripheral type */
 #define EWM_IRQS                                 { WDOG_EWM_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- EWM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register instance definitions */
-/* EWM */
-#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
-#define EWM_SERV                                 EWM_SERV_REG(EWM)
-#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
-#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
-#define EWM_CLKPRESCALER                         EWM_CLKPRESCALER_REG(EWM)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group EWM_Peripheral_Access_Layer */
@@ -6068,28 +5623,7 @@ typedef struct {
   } CS[6];
        uint8_t RESERVED_0[24];
   __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
-} FB_Type, *FB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- FB - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register accessors */
-#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
-#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
-#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
-#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
+} FB_Type;
 
 /* ----------------------------------------------------------------------------
    -- FB Register Masks
@@ -6100,67 +5634,89 @@ typedef struct {
  * @{
  */
 
-/* CSAR Bit Fields */
-#define FB_CSAR_BA_MASK                          0xFFFF0000u
-#define FB_CSAR_BA_SHIFT                         16
-#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
-/* CSMR Bit Fields */
-#define FB_CSMR_V_MASK                           0x1u
-#define FB_CSMR_V_SHIFT                          0
-#define FB_CSMR_WP_MASK                          0x100u
-#define FB_CSMR_WP_SHIFT                         8
-#define FB_CSMR_BAM_MASK                         0xFFFF0000u
-#define FB_CSMR_BAM_SHIFT                        16
-#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
-/* CSCR Bit Fields */
-#define FB_CSCR_BSTW_MASK                        0x8u
-#define FB_CSCR_BSTW_SHIFT                       3
-#define FB_CSCR_BSTR_MASK                        0x10u
-#define FB_CSCR_BSTR_SHIFT                       4
-#define FB_CSCR_BEM_MASK                         0x20u
-#define FB_CSCR_BEM_SHIFT                        5
-#define FB_CSCR_PS_MASK                          0xC0u
-#define FB_CSCR_PS_SHIFT                         6
-#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
-#define FB_CSCR_AA_MASK                          0x100u
-#define FB_CSCR_AA_SHIFT                         8
-#define FB_CSCR_BLS_MASK                         0x200u
-#define FB_CSCR_BLS_SHIFT                        9
-#define FB_CSCR_WS_MASK                          0xFC00u
-#define FB_CSCR_WS_SHIFT                         10
-#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
-#define FB_CSCR_WRAH_MASK                        0x30000u
-#define FB_CSCR_WRAH_SHIFT                       16
-#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
-#define FB_CSCR_RDAH_MASK                        0xC0000u
-#define FB_CSCR_RDAH_SHIFT                       18
-#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
-#define FB_CSCR_ASET_MASK                        0x300000u
-#define FB_CSCR_ASET_SHIFT                       20
-#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
-#define FB_CSCR_EXTS_MASK                        0x400000u
-#define FB_CSCR_EXTS_SHIFT                       22
-#define FB_CSCR_SWSEN_MASK                       0x800000u
-#define FB_CSCR_SWSEN_SHIFT                      23
-#define FB_CSCR_SWS_MASK                         0xFC000000u
-#define FB_CSCR_SWS_SHIFT                        26
-#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
-/* CSPMCR Bit Fields */
-#define FB_CSPMCR_GROUP5_MASK                    0xF000u
-#define FB_CSPMCR_GROUP5_SHIFT                   12
-#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
-#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
-#define FB_CSPMCR_GROUP4_SHIFT                   16
-#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
-#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
-#define FB_CSPMCR_GROUP3_SHIFT                   20
-#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
-#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
-#define FB_CSPMCR_GROUP2_SHIFT                   24
-#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
-#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
-#define FB_CSPMCR_GROUP1_SHIFT                   28
-#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+/*! @name CSAR - Chip Select Address Register */
+#define FB_CSAR_BA_MASK                          (0xFFFF0000U)
+#define FB_CSAR_BA_SHIFT                         (16U)
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+
+/* The count of FB_CSAR */
+#define FB_CSAR_COUNT                            (6U)
+
+/*! @name CSMR - Chip Select Mask Register */
+#define FB_CSMR_V_MASK                           (0x1U)
+#define FB_CSMR_V_SHIFT                          (0U)
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          (0x100U)
+#define FB_CSMR_WP_SHIFT                         (8U)
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         (0xFFFF0000U)
+#define FB_CSMR_BAM_SHIFT                        (16U)
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+
+/* The count of FB_CSMR */
+#define FB_CSMR_COUNT                            (6U)
+
+/*! @name CSCR - Chip Select Control Register */
+#define FB_CSCR_BSTW_MASK                        (0x8U)
+#define FB_CSCR_BSTW_SHIFT                       (3U)
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        (0x10U)
+#define FB_CSCR_BSTR_SHIFT                       (4U)
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         (0x20U)
+#define FB_CSCR_BEM_SHIFT                        (5U)
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          (0xC0U)
+#define FB_CSCR_PS_SHIFT                         (6U)
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          (0x100U)
+#define FB_CSCR_AA_SHIFT                         (8U)
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         (0x200U)
+#define FB_CSCR_BLS_SHIFT                        (9U)
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          (0xFC00U)
+#define FB_CSCR_WS_SHIFT                         (10U)
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        (0x30000U)
+#define FB_CSCR_WRAH_SHIFT                       (16U)
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        (0xC0000U)
+#define FB_CSCR_RDAH_SHIFT                       (18U)
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        (0x300000U)
+#define FB_CSCR_ASET_SHIFT                       (20U)
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        (0x400000U)
+#define FB_CSCR_EXTS_SHIFT                       (22U)
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       (0x800000U)
+#define FB_CSCR_SWSEN_SHIFT                      (23U)
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         (0xFC000000U)
+#define FB_CSCR_SWS_SHIFT                        (26U)
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+
+/* The count of FB_CSCR */
+#define FB_CSCR_COUNT                            (6U)
+
+/*! @name CSPMCR - Chip Select port Multiplexing Control Register */
+#define FB_CSPMCR_GROUP5_MASK                    (0xF000U)
+#define FB_CSPMCR_GROUP5_SHIFT                   (12U)
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    (0xF0000U)
+#define FB_CSPMCR_GROUP4_SHIFT                   (16U)
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    (0xF00000U)
+#define FB_CSPMCR_GROUP3_SHIFT                   (20U)
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    (0xF000000U)
+#define FB_CSPMCR_GROUP2_SHIFT                   (24U)
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    (0xF0000000U)
+#define FB_CSPMCR_GROUP1_SHIFT                   (28U)
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+
 
 /*!
  * @}
@@ -6172,54 +5728,11 @@ typedef struct {
 #define FB_BASE                                  (0x4000C000u)
 /** Peripheral FB base pointer */
 #define FB                                       ((FB_Type *)FB_BASE)
-#define FB_BASE_PTR                              (FB)
 /** Array initializer of FB peripheral base addresses */
 #define FB_BASE_ADDRS                            { FB_BASE }
 /** Array initializer of FB peripheral base pointers */
 #define FB_BASE_PTRS                             { FB }
 
-/* ----------------------------------------------------------------------------
-   -- FB - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register instance definitions */
-/* FB */
-#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
-#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
-#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
-#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
-#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
-#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
-#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
-#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
-#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
-#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
-#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
-#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
-#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
-#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
-#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
-#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
-#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
-#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
-#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
-
-/* FB - Register array accessors */
-#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
-#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
-#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group FB_Peripheral_Access_Layer */
@@ -6246,30 +5759,7 @@ typedef struct {
     __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
     __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
   } SET[4][8];
-} FMC_Type, *FMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- FMC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register accessors */
-#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
-#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
-#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
-#define FMC_TAGVD_REG(base,index,index2)         ((base)->TAGVD[index][index2])
-#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
-#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
+} FMC_Type;
 
 /* ----------------------------------------------------------------------------
    -- FMC Register Masks
@@ -6280,106 +5770,150 @@ typedef struct {
  * @{
  */
 
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK                      0x3u
-#define FMC_PFAPR_M0AP_SHIFT                     0
-#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK                      0xCu
-#define FMC_PFAPR_M1AP_SHIFT                     2
-#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK                      0x30u
-#define FMC_PFAPR_M2AP_SHIFT                     4
-#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK                      0xC0u
-#define FMC_PFAPR_M3AP_SHIFT                     6
-#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M4AP_MASK                      0x300u
-#define FMC_PFAPR_M4AP_SHIFT                     8
-#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
-#define FMC_PFAPR_M5AP_MASK                      0xC00u
-#define FMC_PFAPR_M5AP_SHIFT                     10
-#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
-#define FMC_PFAPR_M6AP_MASK                      0x3000u
-#define FMC_PFAPR_M6AP_SHIFT                     12
-#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
-#define FMC_PFAPR_M7AP_MASK                      0xC000u
-#define FMC_PFAPR_M7AP_SHIFT                     14
-#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK                     0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT                    16
-#define FMC_PFAPR_M1PFD_MASK                     0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT                    17
-#define FMC_PFAPR_M2PFD_MASK                     0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT                    18
-#define FMC_PFAPR_M3PFD_MASK                     0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT                    19
-#define FMC_PFAPR_M4PFD_MASK                     0x100000u
-#define FMC_PFAPR_M4PFD_SHIFT                    20
-#define FMC_PFAPR_M5PFD_MASK                     0x200000u
-#define FMC_PFAPR_M5PFD_SHIFT                    21
-#define FMC_PFAPR_M6PFD_MASK                     0x400000u
-#define FMC_PFAPR_M6PFD_SHIFT                    22
-#define FMC_PFAPR_M7PFD_MASK                     0x800000u
-#define FMC_PFAPR_M7PFD_SHIFT                    23
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT                  0
-#define FMC_PFB0CR_B0IPE_MASK                    0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT                   1
-#define FMC_PFB0CR_B0DPE_MASK                    0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT                   2
-#define FMC_PFB0CR_B0ICE_MASK                    0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT                   3
-#define FMC_PFB0CR_B0DCE_MASK                    0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT                   4
-#define FMC_PFB0CR_CRC_MASK                      0xE0u
-#define FMC_PFB0CR_CRC_SHIFT                     5
-#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK                     0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT                    17
-#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT                 19
-#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT                20
-#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
-#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT                  28
-#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* PFB1CR Bit Fields */
-#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
-#define FMC_PFB1CR_B1SEBE_SHIFT                  0
-#define FMC_PFB1CR_B1IPE_MASK                    0x2u
-#define FMC_PFB1CR_B1IPE_SHIFT                   1
-#define FMC_PFB1CR_B1DPE_MASK                    0x4u
-#define FMC_PFB1CR_B1DPE_SHIFT                   2
-#define FMC_PFB1CR_B1ICE_MASK                    0x8u
-#define FMC_PFB1CR_B1ICE_SHIFT                   3
-#define FMC_PFB1CR_B1DCE_MASK                    0x10u
-#define FMC_PFB1CR_B1DCE_SHIFT                   4
-#define FMC_PFB1CR_B1MW_MASK                     0x60000u
-#define FMC_PFB1CR_B1MW_SHIFT                    17
-#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
-#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
-#define FMC_PFB1CR_B1RWSC_SHIFT                  28
-#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
-/* TAGVD Bit Fields */
-#define FMC_TAGVD_valid_MASK                     0x1u
-#define FMC_TAGVD_valid_SHIFT                    0
-#define FMC_TAGVD_tag_MASK                       0x7FFC0u
-#define FMC_TAGVD_tag_SHIFT                      6
-#define FMC_TAGVD_tag(x)                         (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
-/* DATA_U Bit Fields */
-#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
-#define FMC_DATA_U_data_SHIFT                    0
-#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
-/* DATA_L Bit Fields */
-#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
-#define FMC_DATA_L_data_SHIFT                    0
-#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+/*! @name PFAPR - Flash Access Protection Register */
+#define FMC_PFAPR_M0AP_MASK                      (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT                     (0U)
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT                     (2U)
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT                     (4U)
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT                     (6U)
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      (0x300U)
+#define FMC_PFAPR_M4AP_SHIFT                     (8U)
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      (0xC00U)
+#define FMC_PFAPR_M5AP_SHIFT                     (10U)
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      (0x3000U)
+#define FMC_PFAPR_M6AP_SHIFT                     (12U)
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      (0xC000U)
+#define FMC_PFAPR_M7AP_SHIFT                     (14U)
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     (0x10000U)
+#define FMC_PFAPR_M0PFD_SHIFT                    (16U)
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     (0x20000U)
+#define FMC_PFAPR_M1PFD_SHIFT                    (17U)
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     (0x40000U)
+#define FMC_PFAPR_M2PFD_SHIFT                    (18U)
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     (0x80000U)
+#define FMC_PFAPR_M3PFD_SHIFT                    (19U)
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     (0x100000U)
+#define FMC_PFAPR_M4PFD_SHIFT                    (20U)
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     (0x200000U)
+#define FMC_PFAPR_M5PFD_SHIFT                    (21U)
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     (0x400000U)
+#define FMC_PFAPR_M6PFD_SHIFT                    (22U)
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     (0x800000U)
+#define FMC_PFAPR_M7PFD_SHIFT                    (23U)
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+
+/*! @name PFB0CR - Flash Bank 0 Control Register */
+#define FMC_PFB0CR_B0SEBE_MASK                   (0x1U)
+#define FMC_PFB0CR_B0SEBE_SHIFT                  (0U)
+#define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK                    (0x2U)
+#define FMC_PFB0CR_B0IPE_SHIFT                   (1U)
+#define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK                    (0x4U)
+#define FMC_PFB0CR_B0DPE_SHIFT                   (2U)
+#define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK                    (0x8U)
+#define FMC_PFB0CR_B0ICE_SHIFT                   (3U)
+#define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK                    (0x10U)
+#define FMC_PFB0CR_B0DCE_SHIFT                   (4U)
+#define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK                      (0xE0U)
+#define FMC_PFB0CR_CRC_SHIFT                     (5U)
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     (0x60000U)
+#define FMC_PFB0CR_B0MW_SHIFT                    (17U)
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  (0x80000U)
+#define FMC_PFB0CR_S_B_INV_SHIFT                 (19U)
+#define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK                 (0xF00000U)
+#define FMC_PFB0CR_CINV_WAY_SHIFT                (20U)
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 (0xF000000U)
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                (24U)
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   (0xF0000000U)
+#define FMC_PFB0CR_B0RWSC_SHIFT                  (28U)
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
+
+/*! @name PFB1CR - Flash Bank 1 Control Register */
+#define FMC_PFB1CR_B1SEBE_MASK                   (0x1U)
+#define FMC_PFB1CR_B1SEBE_SHIFT                  (0U)
+#define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK                    (0x2U)
+#define FMC_PFB1CR_B1IPE_SHIFT                   (1U)
+#define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK                    (0x4U)
+#define FMC_PFB1CR_B1DPE_SHIFT                   (2U)
+#define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK                    (0x8U)
+#define FMC_PFB1CR_B1ICE_SHIFT                   (3U)
+#define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK                    (0x10U)
+#define FMC_PFB1CR_B1DCE_SHIFT                   (4U)
+#define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK                     (0x60000U)
+#define FMC_PFB1CR_B1MW_SHIFT                    (17U)
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   (0xF0000000U)
+#define FMC_PFB1CR_B1RWSC_SHIFT                  (28U)
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
+
+/*! @name TAGVD - Cache Tag Storage */
+#define FMC_TAGVD_valid_MASK                     (0x1U)
+#define FMC_TAGVD_valid_SHIFT                    (0U)
+#define FMC_TAGVD_valid(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK)
+#define FMC_TAGVD_tag_MASK                       (0x7FFC0U)
+#define FMC_TAGVD_tag_SHIFT                      (6U)
+#define FMC_TAGVD_tag(x)                         (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK)
+
+/* The count of FMC_TAGVD */
+#define FMC_TAGVD_COUNT                          (4U)
+
+/* The count of FMC_TAGVD */
+#define FMC_TAGVD_COUNT2                         (8U)
+
+/*! @name DATA_U - Cache Data Storage (upper word) */
+#define FMC_DATA_U_data_MASK                     (0xFFFFFFFFU)
+#define FMC_DATA_U_data_SHIFT                    (0U)
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT                         (4U)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT2                        (8U)
+
+/*! @name DATA_L - Cache Data Storage (lower word) */
+#define FMC_DATA_L_data_MASK                     (0xFFFFFFFFU)
+#define FMC_DATA_L_data_SHIFT                    (0U)
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT                         (4U)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT2                        (8U)
+
 
 /*!
  * @}
@@ -6391,134 +5925,11 @@ typedef struct {
 #define FMC_BASE                                 (0x4001F000u)
 /** Peripheral FMC base pointer */
 #define FMC                                      ((FMC_Type *)FMC_BASE)
-#define FMC_BASE_PTR                             (FMC)
 /** Array initializer of FMC peripheral base addresses */
 #define FMC_BASE_ADDRS                           { FMC_BASE }
 /** Array initializer of FMC peripheral base pointers */
 #define FMC_BASE_PTRS                            { FMC }
 
-/* ----------------------------------------------------------------------------
-   -- FMC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register instance definitions */
-/* FMC */
-#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
-#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
-#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
-#define FMC_TAGVDW0S0                            FMC_TAGVD_REG(FMC,0,0)
-#define FMC_TAGVDW0S1                            FMC_TAGVD_REG(FMC,0,1)
-#define FMC_TAGVDW0S2                            FMC_TAGVD_REG(FMC,0,2)
-#define FMC_TAGVDW0S3                            FMC_TAGVD_REG(FMC,0,3)
-#define FMC_TAGVDW0S4                            FMC_TAGVD_REG(FMC,0,4)
-#define FMC_TAGVDW0S5                            FMC_TAGVD_REG(FMC,0,5)
-#define FMC_TAGVDW0S6                            FMC_TAGVD_REG(FMC,0,6)
-#define FMC_TAGVDW0S7                            FMC_TAGVD_REG(FMC,0,7)
-#define FMC_TAGVDW1S0                            FMC_TAGVD_REG(FMC,1,0)
-#define FMC_TAGVDW1S1                            FMC_TAGVD_REG(FMC,1,1)
-#define FMC_TAGVDW1S2                            FMC_TAGVD_REG(FMC,1,2)
-#define FMC_TAGVDW1S3                            FMC_TAGVD_REG(FMC,1,3)
-#define FMC_TAGVDW1S4                            FMC_TAGVD_REG(FMC,1,4)
-#define FMC_TAGVDW1S5                            FMC_TAGVD_REG(FMC,1,5)
-#define FMC_TAGVDW1S6                            FMC_TAGVD_REG(FMC,1,6)
-#define FMC_TAGVDW1S7                            FMC_TAGVD_REG(FMC,1,7)
-#define FMC_TAGVDW2S0                            FMC_TAGVD_REG(FMC,2,0)
-#define FMC_TAGVDW2S1                            FMC_TAGVD_REG(FMC,2,1)
-#define FMC_TAGVDW2S2                            FMC_TAGVD_REG(FMC,2,2)
-#define FMC_TAGVDW2S3                            FMC_TAGVD_REG(FMC,2,3)
-#define FMC_TAGVDW2S4                            FMC_TAGVD_REG(FMC,2,4)
-#define FMC_TAGVDW2S5                            FMC_TAGVD_REG(FMC,2,5)
-#define FMC_TAGVDW2S6                            FMC_TAGVD_REG(FMC,2,6)
-#define FMC_TAGVDW2S7                            FMC_TAGVD_REG(FMC,2,7)
-#define FMC_TAGVDW3S0                            FMC_TAGVD_REG(FMC,3,0)
-#define FMC_TAGVDW3S1                            FMC_TAGVD_REG(FMC,3,1)
-#define FMC_TAGVDW3S2                            FMC_TAGVD_REG(FMC,3,2)
-#define FMC_TAGVDW3S3                            FMC_TAGVD_REG(FMC,3,3)
-#define FMC_TAGVDW3S4                            FMC_TAGVD_REG(FMC,3,4)
-#define FMC_TAGVDW3S5                            FMC_TAGVD_REG(FMC,3,5)
-#define FMC_TAGVDW3S6                            FMC_TAGVD_REG(FMC,3,6)
-#define FMC_TAGVDW3S7                            FMC_TAGVD_REG(FMC,3,7)
-#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
-#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
-#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
-#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
-#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
-#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
-#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
-#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
-#define FMC_DATAW0S4U                            FMC_DATA_U_REG(FMC,0,4)
-#define FMC_DATAW0S4L                            FMC_DATA_L_REG(FMC,0,4)
-#define FMC_DATAW0S5U                            FMC_DATA_U_REG(FMC,0,5)
-#define FMC_DATAW0S5L                            FMC_DATA_L_REG(FMC,0,5)
-#define FMC_DATAW0S6U                            FMC_DATA_U_REG(FMC,0,6)
-#define FMC_DATAW0S6L                            FMC_DATA_L_REG(FMC,0,6)
-#define FMC_DATAW0S7U                            FMC_DATA_U_REG(FMC,0,7)
-#define FMC_DATAW0S7L                            FMC_DATA_L_REG(FMC,0,7)
-#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
-#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
-#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
-#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
-#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
-#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
-#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
-#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
-#define FMC_DATAW1S4U                            FMC_DATA_U_REG(FMC,1,4)
-#define FMC_DATAW1S4L                            FMC_DATA_L_REG(FMC,1,4)
-#define FMC_DATAW1S5U                            FMC_DATA_U_REG(FMC,1,5)
-#define FMC_DATAW1S5L                            FMC_DATA_L_REG(FMC,1,5)
-#define FMC_DATAW1S6U                            FMC_DATA_U_REG(FMC,1,6)
-#define FMC_DATAW1S6L                            FMC_DATA_L_REG(FMC,1,6)
-#define FMC_DATAW1S7U                            FMC_DATA_U_REG(FMC,1,7)
-#define FMC_DATAW1S7L                            FMC_DATA_L_REG(FMC,1,7)
-#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
-#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
-#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
-#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
-#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
-#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
-#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
-#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
-#define FMC_DATAW2S4U                            FMC_DATA_U_REG(FMC,2,4)
-#define FMC_DATAW2S4L                            FMC_DATA_L_REG(FMC,2,4)
-#define FMC_DATAW2S5U                            FMC_DATA_U_REG(FMC,2,5)
-#define FMC_DATAW2S5L                            FMC_DATA_L_REG(FMC,2,5)
-#define FMC_DATAW2S6U                            FMC_DATA_U_REG(FMC,2,6)
-#define FMC_DATAW2S6L                            FMC_DATA_L_REG(FMC,2,6)
-#define FMC_DATAW2S7U                            FMC_DATA_U_REG(FMC,2,7)
-#define FMC_DATAW2S7L                            FMC_DATA_L_REG(FMC,2,7)
-#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
-#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
-#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
-#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
-#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
-#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
-#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
-#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
-#define FMC_DATAW3S4U                            FMC_DATA_U_REG(FMC,3,4)
-#define FMC_DATAW3S4L                            FMC_DATA_L_REG(FMC,3,4)
-#define FMC_DATAW3S5U                            FMC_DATA_U_REG(FMC,3,5)
-#define FMC_DATAW3S5L                            FMC_DATA_L_REG(FMC,3,5)
-#define FMC_DATAW3S6U                            FMC_DATA_U_REG(FMC,3,6)
-#define FMC_DATAW3S6L                            FMC_DATA_L_REG(FMC,3,6)
-#define FMC_DATAW3S7U                            FMC_DATA_U_REG(FMC,3,7)
-#define FMC_DATAW3S7L                            FMC_DATA_L_REG(FMC,3,7)
-
-/* FMC - Register array accessors */
-#define FMC_TAGVD(index,index2)                  FMC_TAGVD_REG(FMC,index,index2)
-#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
-#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group FMC_Peripheral_Access_Layer */
@@ -6558,46 +5969,7 @@ typedef struct {
        uint8_t RESERVED_0[2];
   __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
   __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
-} FTFL_Type, *FTFL_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- FTFL - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFL_Register_Accessor_Macros FTFL - Register accessor macros
- * @{
- */
-
-
-/* FTFL - Register accessors */
-#define FTFL_FSTAT_REG(base)                     ((base)->FSTAT)
-#define FTFL_FCNFG_REG(base)                     ((base)->FCNFG)
-#define FTFL_FSEC_REG(base)                      ((base)->FSEC)
-#define FTFL_FOPT_REG(base)                      ((base)->FOPT)
-#define FTFL_FCCOB3_REG(base)                    ((base)->FCCOB3)
-#define FTFL_FCCOB2_REG(base)                    ((base)->FCCOB2)
-#define FTFL_FCCOB1_REG(base)                    ((base)->FCCOB1)
-#define FTFL_FCCOB0_REG(base)                    ((base)->FCCOB0)
-#define FTFL_FCCOB7_REG(base)                    ((base)->FCCOB7)
-#define FTFL_FCCOB6_REG(base)                    ((base)->FCCOB6)
-#define FTFL_FCCOB5_REG(base)                    ((base)->FCCOB5)
-#define FTFL_FCCOB4_REG(base)                    ((base)->FCCOB4)
-#define FTFL_FCCOBB_REG(base)                    ((base)->FCCOBB)
-#define FTFL_FCCOBA_REG(base)                    ((base)->FCCOBA)
-#define FTFL_FCCOB9_REG(base)                    ((base)->FCCOB9)
-#define FTFL_FCCOB8_REG(base)                    ((base)->FCCOB8)
-#define FTFL_FPROT3_REG(base)                    ((base)->FPROT3)
-#define FTFL_FPROT2_REG(base)                    ((base)->FPROT2)
-#define FTFL_FPROT1_REG(base)                    ((base)->FPROT1)
-#define FTFL_FPROT0_REG(base)                    ((base)->FPROT0)
-#define FTFL_FEPROT_REG(base)                    ((base)->FEPROT)
-#define FTFL_FDPROT_REG(base)                    ((base)->FDPROT)
-
-/*!
- * @}
- */ /* end of group FTFL_Register_Accessor_Macros */
-
+} FTFL_Type;
 
 /* ----------------------------------------------------------------------------
    -- FTFL Register Masks
@@ -6608,123 +5980,158 @@ typedef struct {
  * @{
  */
 
-/* FSTAT Bit Fields */
-#define FTFL_FSTAT_MGSTAT0_MASK                  0x1u
-#define FTFL_FSTAT_MGSTAT0_SHIFT                 0
-#define FTFL_FSTAT_FPVIOL_MASK                   0x10u
-#define FTFL_FSTAT_FPVIOL_SHIFT                  4
-#define FTFL_FSTAT_ACCERR_MASK                   0x20u
-#define FTFL_FSTAT_ACCERR_SHIFT                  5
-#define FTFL_FSTAT_RDCOLERR_MASK                 0x40u
-#define FTFL_FSTAT_RDCOLERR_SHIFT                6
-#define FTFL_FSTAT_CCIF_MASK                     0x80u
-#define FTFL_FSTAT_CCIF_SHIFT                    7
-/* FCNFG Bit Fields */
-#define FTFL_FCNFG_EEERDY_MASK                   0x1u
-#define FTFL_FCNFG_EEERDY_SHIFT                  0
-#define FTFL_FCNFG_RAMRDY_MASK                   0x2u
-#define FTFL_FCNFG_RAMRDY_SHIFT                  1
-#define FTFL_FCNFG_PFLSH_MASK                    0x4u
-#define FTFL_FCNFG_PFLSH_SHIFT                   2
-#define FTFL_FCNFG_SWAP_MASK                     0x8u
-#define FTFL_FCNFG_SWAP_SHIFT                    3
-#define FTFL_FCNFG_ERSSUSP_MASK                  0x10u
-#define FTFL_FCNFG_ERSSUSP_SHIFT                 4
-#define FTFL_FCNFG_ERSAREQ_MASK                  0x20u
-#define FTFL_FCNFG_ERSAREQ_SHIFT                 5
-#define FTFL_FCNFG_RDCOLLIE_MASK                 0x40u
-#define FTFL_FCNFG_RDCOLLIE_SHIFT                6
-#define FTFL_FCNFG_CCIE_MASK                     0x80u
-#define FTFL_FCNFG_CCIE_SHIFT                    7
-/* FSEC Bit Fields */
-#define FTFL_FSEC_SEC_MASK                       0x3u
-#define FTFL_FSEC_SEC_SHIFT                      0
-#define FTFL_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
-#define FTFL_FSEC_FSLACC_MASK                    0xCu
-#define FTFL_FSEC_FSLACC_SHIFT                   2
-#define FTFL_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
-#define FTFL_FSEC_MEEN_MASK                      0x30u
-#define FTFL_FSEC_MEEN_SHIFT                     4
-#define FTFL_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
-#define FTFL_FSEC_KEYEN_MASK                     0xC0u
-#define FTFL_FSEC_KEYEN_SHIFT                    6
-#define FTFL_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFL_FOPT_OPT_MASK                       0xFFu
-#define FTFL_FOPT_OPT_SHIFT                      0
-#define FTFL_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFL_FCCOB3_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB3_CCOBn_SHIFT                  0
-#define FTFL_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFL_FCCOB2_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB2_CCOBn_SHIFT                  0
-#define FTFL_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFL_FCCOB1_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB1_CCOBn_SHIFT                  0
-#define FTFL_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFL_FCCOB0_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB0_CCOBn_SHIFT                  0
-#define FTFL_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFL_FCCOB7_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB7_CCOBn_SHIFT                  0
-#define FTFL_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFL_FCCOB6_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB6_CCOBn_SHIFT                  0
-#define FTFL_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFL_FCCOB5_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB5_CCOBn_SHIFT                  0
-#define FTFL_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFL_FCCOB4_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB4_CCOBn_SHIFT                  0
-#define FTFL_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFL_FCCOBB_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOBB_CCOBn_SHIFT                  0
-#define FTFL_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFL_FCCOBA_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOBA_CCOBn_SHIFT                  0
-#define FTFL_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFL_FCCOB9_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB9_CCOBn_SHIFT                  0
-#define FTFL_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFL_FCCOB8_CCOBn_MASK                   0xFFu
-#define FTFL_FCCOB8_CCOBn_SHIFT                  0
-#define FTFL_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFL_FPROT3_PROT_MASK                    0xFFu
-#define FTFL_FPROT3_PROT_SHIFT                   0
-#define FTFL_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFL_FPROT2_PROT_MASK                    0xFFu
-#define FTFL_FPROT2_PROT_SHIFT                   0
-#define FTFL_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFL_FPROT1_PROT_MASK                    0xFFu
-#define FTFL_FPROT1_PROT_SHIFT                   0
-#define FTFL_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFL_FPROT0_PROT_MASK                    0xFFu
-#define FTFL_FPROT0_PROT_SHIFT                   0
-#define FTFL_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
-/* FEPROT Bit Fields */
-#define FTFL_FEPROT_EPROT_MASK                   0xFFu
-#define FTFL_FEPROT_EPROT_SHIFT                  0
-#define FTFL_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define FTFL_FDPROT_DPROT_MASK                   0xFFu
-#define FTFL_FDPROT_DPROT_SHIFT                  0
-#define FTFL_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
+/*! @name FSTAT - Flash Status Register */
+#define FTFL_FSTAT_MGSTAT0_MASK                  (0x1U)
+#define FTFL_FSTAT_MGSTAT0_SHIFT                 (0U)
+#define FTFL_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_MGSTAT0_SHIFT)) & FTFL_FSTAT_MGSTAT0_MASK)
+#define FTFL_FSTAT_FPVIOL_MASK                   (0x10U)
+#define FTFL_FSTAT_FPVIOL_SHIFT                  (4U)
+#define FTFL_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_FPVIOL_SHIFT)) & FTFL_FSTAT_FPVIOL_MASK)
+#define FTFL_FSTAT_ACCERR_MASK                   (0x20U)
+#define FTFL_FSTAT_ACCERR_SHIFT                  (5U)
+#define FTFL_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_ACCERR_SHIFT)) & FTFL_FSTAT_ACCERR_MASK)
+#define FTFL_FSTAT_RDCOLERR_MASK                 (0x40U)
+#define FTFL_FSTAT_RDCOLERR_SHIFT                (6U)
+#define FTFL_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_RDCOLERR_SHIFT)) & FTFL_FSTAT_RDCOLERR_MASK)
+#define FTFL_FSTAT_CCIF_MASK                     (0x80U)
+#define FTFL_FSTAT_CCIF_SHIFT                    (7U)
+#define FTFL_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_CCIF_SHIFT)) & FTFL_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFL_FCNFG_EEERDY_MASK                   (0x1U)
+#define FTFL_FCNFG_EEERDY_SHIFT                  (0U)
+#define FTFL_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_EEERDY_SHIFT)) & FTFL_FCNFG_EEERDY_MASK)
+#define FTFL_FCNFG_RAMRDY_MASK                   (0x2U)
+#define FTFL_FCNFG_RAMRDY_SHIFT                  (1U)
+#define FTFL_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RAMRDY_SHIFT)) & FTFL_FCNFG_RAMRDY_MASK)
+#define FTFL_FCNFG_PFLSH_MASK                    (0x4U)
+#define FTFL_FCNFG_PFLSH_SHIFT                   (2U)
+#define FTFL_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_PFLSH_SHIFT)) & FTFL_FCNFG_PFLSH_MASK)
+#define FTFL_FCNFG_SWAP_MASK                     (0x8U)
+#define FTFL_FCNFG_SWAP_SHIFT                    (3U)
+#define FTFL_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_SWAP_SHIFT)) & FTFL_FCNFG_SWAP_MASK)
+#define FTFL_FCNFG_ERSSUSP_MASK                  (0x10U)
+#define FTFL_FCNFG_ERSSUSP_SHIFT                 (4U)
+#define FTFL_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSSUSP_SHIFT)) & FTFL_FCNFG_ERSSUSP_MASK)
+#define FTFL_FCNFG_ERSAREQ_MASK                  (0x20U)
+#define FTFL_FCNFG_ERSAREQ_SHIFT                 (5U)
+#define FTFL_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSAREQ_SHIFT)) & FTFL_FCNFG_ERSAREQ_MASK)
+#define FTFL_FCNFG_RDCOLLIE_MASK                 (0x40U)
+#define FTFL_FCNFG_RDCOLLIE_SHIFT                (6U)
+#define FTFL_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RDCOLLIE_SHIFT)) & FTFL_FCNFG_RDCOLLIE_MASK)
+#define FTFL_FCNFG_CCIE_MASK                     (0x80U)
+#define FTFL_FCNFG_CCIE_SHIFT                    (7U)
+#define FTFL_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_CCIE_SHIFT)) & FTFL_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFL_FSEC_SEC_MASK                       (0x3U)
+#define FTFL_FSEC_SEC_SHIFT                      (0U)
+#define FTFL_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_SEC_SHIFT)) & FTFL_FSEC_SEC_MASK)
+#define FTFL_FSEC_FSLACC_MASK                    (0xCU)
+#define FTFL_FSEC_FSLACC_SHIFT                   (2U)
+#define FTFL_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_FSLACC_SHIFT)) & FTFL_FSEC_FSLACC_MASK)
+#define FTFL_FSEC_MEEN_MASK                      (0x30U)
+#define FTFL_FSEC_MEEN_SHIFT                     (4U)
+#define FTFL_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_MEEN_SHIFT)) & FTFL_FSEC_MEEN_MASK)
+#define FTFL_FSEC_KEYEN_MASK                     (0xC0U)
+#define FTFL_FSEC_KEYEN_SHIFT                    (6U)
+#define FTFL_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_KEYEN_SHIFT)) & FTFL_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFL_FOPT_OPT_MASK                       (0xFFU)
+#define FTFL_FOPT_OPT_SHIFT                      (0U)
+#define FTFL_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFL_FOPT_OPT_SHIFT)) & FTFL_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFL_FCCOB3_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB3_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB3_CCOBn_SHIFT)) & FTFL_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFL_FCCOB2_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB2_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB2_CCOBn_SHIFT)) & FTFL_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFL_FCCOB1_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB1_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB1_CCOBn_SHIFT)) & FTFL_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFL_FCCOB0_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB0_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB0_CCOBn_SHIFT)) & FTFL_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFL_FCCOB7_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB7_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB7_CCOBn_SHIFT)) & FTFL_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFL_FCCOB6_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB6_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB6_CCOBn_SHIFT)) & FTFL_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFL_FCCOB5_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB5_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB5_CCOBn_SHIFT)) & FTFL_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFL_FCCOB4_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB4_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB4_CCOBn_SHIFT)) & FTFL_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFL_FCCOBB_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOBB_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBB_CCOBn_SHIFT)) & FTFL_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFL_FCCOBA_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOBA_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBA_CCOBn_SHIFT)) & FTFL_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFL_FCCOB9_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB9_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB9_CCOBn_SHIFT)) & FTFL_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFL_FCCOB8_CCOBn_MASK                   (0xFFU)
+#define FTFL_FCCOB8_CCOBn_SHIFT                  (0U)
+#define FTFL_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB8_CCOBn_SHIFT)) & FTFL_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFL_FPROT3_PROT_MASK                    (0xFFU)
+#define FTFL_FPROT3_PROT_SHIFT                   (0U)
+#define FTFL_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT3_PROT_SHIFT)) & FTFL_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFL_FPROT2_PROT_MASK                    (0xFFU)
+#define FTFL_FPROT2_PROT_SHIFT                   (0U)
+#define FTFL_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT2_PROT_SHIFT)) & FTFL_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFL_FPROT1_PROT_MASK                    (0xFFU)
+#define FTFL_FPROT1_PROT_SHIFT                   (0U)
+#define FTFL_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT1_PROT_SHIFT)) & FTFL_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFL_FPROT0_PROT_MASK                    (0xFFU)
+#define FTFL_FPROT0_PROT_SHIFT                   (0U)
+#define FTFL_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT0_PROT_SHIFT)) & FTFL_FPROT0_PROT_MASK)
+
+/*! @name FEPROT - EEPROM Protection Register */
+#define FTFL_FEPROT_EPROT_MASK                   (0xFFU)
+#define FTFL_FEPROT_EPROT_SHIFT                  (0U)
+#define FTFL_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FEPROT_EPROT_SHIFT)) & FTFL_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Data Flash Protection Register */
+#define FTFL_FDPROT_DPROT_MASK                   (0xFFU)
+#define FTFL_FDPROT_DPROT_SHIFT                  (0U)
+#define FTFL_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFL_FDPROT_DPROT_SHIFT)) & FTFL_FDPROT_DPROT_MASK)
+
 
 /*!
  * @}
@@ -6736,7 +6143,6 @@ typedef struct {
 #define FTFL_BASE                                (0x40020000u)
 /** Peripheral FTFL base pointer */
 #define FTFL                                     ((FTFL_Type *)FTFL_BASE)
-#define FTFL_BASE_PTR                            (FTFL)
 /** Array initializer of FTFL peripheral base addresses */
 #define FTFL_BASE_ADDRS                          { FTFL_BASE }
 /** Array initializer of FTFL peripheral base pointers */
@@ -6745,46 +6151,6 @@ typedef struct {
 #define FTFL_COMMAND_COMPLETE_IRQS               { FTFL_IRQn }
 #define FTFL_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- FTFL - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFL_Register_Accessor_Macros FTFL - Register accessor macros
- * @{
- */
-
-
-/* FTFL - Register instance definitions */
-/* FTFL */
-#define FTFL_FSTAT                               FTFL_FSTAT_REG(FTFL)
-#define FTFL_FCNFG                               FTFL_FCNFG_REG(FTFL)
-#define FTFL_FSEC                                FTFL_FSEC_REG(FTFL)
-#define FTFL_FOPT                                FTFL_FOPT_REG(FTFL)
-#define FTFL_FCCOB3                              FTFL_FCCOB3_REG(FTFL)
-#define FTFL_FCCOB2                              FTFL_FCCOB2_REG(FTFL)
-#define FTFL_FCCOB1                              FTFL_FCCOB1_REG(FTFL)
-#define FTFL_FCCOB0                              FTFL_FCCOB0_REG(FTFL)
-#define FTFL_FCCOB7                              FTFL_FCCOB7_REG(FTFL)
-#define FTFL_FCCOB6                              FTFL_FCCOB6_REG(FTFL)
-#define FTFL_FCCOB5                              FTFL_FCCOB5_REG(FTFL)
-#define FTFL_FCCOB4                              FTFL_FCCOB4_REG(FTFL)
-#define FTFL_FCCOBB                              FTFL_FCCOBB_REG(FTFL)
-#define FTFL_FCCOBA                              FTFL_FCCOBA_REG(FTFL)
-#define FTFL_FCCOB9                              FTFL_FCCOB9_REG(FTFL)
-#define FTFL_FCCOB8                              FTFL_FCCOB8_REG(FTFL)
-#define FTFL_FPROT3                              FTFL_FPROT3_REG(FTFL)
-#define FTFL_FPROT2                              FTFL_FPROT2_REG(FTFL)
-#define FTFL_FPROT1                              FTFL_FPROT1_REG(FTFL)
-#define FTFL_FPROT0                              FTFL_FPROT0_REG(FTFL)
-#define FTFL_FEPROT                              FTFL_FEPROT_REG(FTFL)
-#define FTFL_FDPROT                              FTFL_FDPROT_REG(FTFL)
-
-/*!
- * @}
- */ /* end of group FTFL_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group FTFL_Peripheral_Access_Layer */
@@ -6828,49 +6194,7 @@ typedef struct {
   __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
   __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
   __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type, *FTM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- FTM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register accessors */
-#define FTM_SC_REG(base)                         ((base)->SC)
-#define FTM_CNT_REG(base)                        ((base)->CNT)
-#define FTM_MOD_REG(base)                        ((base)->MOD)
-#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
-#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
-#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
-#define FTM_STATUS_REG(base)                     ((base)->STATUS)
-#define FTM_MODE_REG(base)                       ((base)->MODE)
-#define FTM_SYNC_REG(base)                       ((base)->SYNC)
-#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
-#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
-#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
-#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
-#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
-#define FTM_POL_REG(base)                        ((base)->POL)
-#define FTM_FMS_REG(base)                        ((base)->FMS)
-#define FTM_FILTER_REG(base)                     ((base)->FILTER)
-#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
-#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
-#define FTM_CONF_REG(base)                       ((base)->CONF)
-#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
-#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
-#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
-#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
-#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
+} FTM_Type;
 
 /* ----------------------------------------------------------------------------
    -- FTM Register Masks
@@ -6881,409 +6205,605 @@ typedef struct {
  * @{
  */
 
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK                           0x7u
-#define FTM_SC_PS_SHIFT                          0
-#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK                         0x18u
-#define FTM_SC_CLKS_SHIFT                        3
-#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK                        0x20u
-#define FTM_SC_CPWMS_SHIFT                       5
-#define FTM_SC_TOIE_MASK                         0x40u
-#define FTM_SC_TOIE_SHIFT                        6
-#define FTM_SC_TOF_MASK                          0x80u
-#define FTM_SC_TOF_SHIFT                         7
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK                       0xFFFFu
-#define FTM_CNT_COUNT_SHIFT                      0
-#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK                         0xFFFFu
-#define FTM_MOD_MOD_SHIFT                        0
-#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK                        0x1u
-#define FTM_CnSC_DMA_SHIFT                       0
-#define FTM_CnSC_ELSA_MASK                       0x4u
-#define FTM_CnSC_ELSA_SHIFT                      2
-#define FTM_CnSC_ELSB_MASK                       0x8u
-#define FTM_CnSC_ELSB_SHIFT                      3
-#define FTM_CnSC_MSA_MASK                        0x10u
-#define FTM_CnSC_MSA_SHIFT                       4
-#define FTM_CnSC_MSB_MASK                        0x20u
-#define FTM_CnSC_MSB_SHIFT                       5
-#define FTM_CnSC_CHIE_MASK                       0x40u
-#define FTM_CnSC_CHIE_SHIFT                      6
-#define FTM_CnSC_CHF_MASK                        0x80u
-#define FTM_CnSC_CHF_SHIFT                       7
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK                         0xFFFFu
-#define FTM_CnV_VAL_SHIFT                        0
-#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK                      0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT                     0
-#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK                     0x1u
-#define FTM_STATUS_CH0F_SHIFT                    0
-#define FTM_STATUS_CH1F_MASK                     0x2u
-#define FTM_STATUS_CH1F_SHIFT                    1
-#define FTM_STATUS_CH2F_MASK                     0x4u
-#define FTM_STATUS_CH2F_SHIFT                    2
-#define FTM_STATUS_CH3F_MASK                     0x8u
-#define FTM_STATUS_CH3F_SHIFT                    3
-#define FTM_STATUS_CH4F_MASK                     0x10u
-#define FTM_STATUS_CH4F_SHIFT                    4
-#define FTM_STATUS_CH5F_MASK                     0x20u
-#define FTM_STATUS_CH5F_SHIFT                    5
-#define FTM_STATUS_CH6F_MASK                     0x40u
-#define FTM_STATUS_CH6F_SHIFT                    6
-#define FTM_STATUS_CH7F_MASK                     0x80u
-#define FTM_STATUS_CH7F_SHIFT                    7
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK                      0x1u
-#define FTM_MODE_FTMEN_SHIFT                     0
-#define FTM_MODE_INIT_MASK                       0x2u
-#define FTM_MODE_INIT_SHIFT                      1
-#define FTM_MODE_WPDIS_MASK                      0x4u
-#define FTM_MODE_WPDIS_SHIFT                     2
-#define FTM_MODE_PWMSYNC_MASK                    0x8u
-#define FTM_MODE_PWMSYNC_SHIFT                   3
-#define FTM_MODE_CAPTEST_MASK                    0x10u
-#define FTM_MODE_CAPTEST_SHIFT                   4
-#define FTM_MODE_FAULTM_MASK                     0x60u
-#define FTM_MODE_FAULTM_SHIFT                    5
-#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK                    0x80u
-#define FTM_MODE_FAULTIE_SHIFT                   7
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK                     0x1u
-#define FTM_SYNC_CNTMIN_SHIFT                    0
-#define FTM_SYNC_CNTMAX_MASK                     0x2u
-#define FTM_SYNC_CNTMAX_SHIFT                    1
-#define FTM_SYNC_REINIT_MASK                     0x4u
-#define FTM_SYNC_REINIT_SHIFT                    2
-#define FTM_SYNC_SYNCHOM_MASK                    0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT                   3
-#define FTM_SYNC_TRIG0_MASK                      0x10u
-#define FTM_SYNC_TRIG0_SHIFT                     4
-#define FTM_SYNC_TRIG1_MASK                      0x20u
-#define FTM_SYNC_TRIG1_SHIFT                     5
-#define FTM_SYNC_TRIG2_MASK                      0x40u
-#define FTM_SYNC_TRIG2_SHIFT                     6
-#define FTM_SYNC_SWSYNC_MASK                     0x80u
-#define FTM_SYNC_SWSYNC_SHIFT                    7
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK                   0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT                  0
-#define FTM_OUTINIT_CH1OI_MASK                   0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT                  1
-#define FTM_OUTINIT_CH2OI_MASK                   0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT                  2
-#define FTM_OUTINIT_CH3OI_MASK                   0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT                  3
-#define FTM_OUTINIT_CH4OI_MASK                   0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT                  4
-#define FTM_OUTINIT_CH5OI_MASK                   0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT                  5
-#define FTM_OUTINIT_CH6OI_MASK                   0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT                  6
-#define FTM_OUTINIT_CH7OI_MASK                   0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT                  7
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK                   0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT                  0
-#define FTM_OUTMASK_CH1OM_MASK                   0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT                  1
-#define FTM_OUTMASK_CH2OM_MASK                   0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT                  2
-#define FTM_OUTMASK_CH3OM_MASK                   0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT                  3
-#define FTM_OUTMASK_CH4OM_MASK                   0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT                  4
-#define FTM_OUTMASK_CH5OM_MASK                   0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT                  5
-#define FTM_OUTMASK_CH6OM_MASK                   0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT                  6
-#define FTM_OUTMASK_CH7OM_MASK                   0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT                  7
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK                0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT               0
-#define FTM_COMBINE_COMP0_MASK                   0x2u
-#define FTM_COMBINE_COMP0_SHIFT                  1
-#define FTM_COMBINE_DECAPEN0_MASK                0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT               2
-#define FTM_COMBINE_DECAP0_MASK                  0x8u
-#define FTM_COMBINE_DECAP0_SHIFT                 3
-#define FTM_COMBINE_DTEN0_MASK                   0x10u
-#define FTM_COMBINE_DTEN0_SHIFT                  4
-#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT                5
-#define FTM_COMBINE_FAULTEN0_MASK                0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT               6
-#define FTM_COMBINE_COMBINE1_MASK                0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT               8
-#define FTM_COMBINE_COMP1_MASK                   0x200u
-#define FTM_COMBINE_COMP1_SHIFT                  9
-#define FTM_COMBINE_DECAPEN1_MASK                0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT               10
-#define FTM_COMBINE_DECAP1_MASK                  0x800u
-#define FTM_COMBINE_DECAP1_SHIFT                 11
-#define FTM_COMBINE_DTEN1_MASK                   0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT                  12
-#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT                13
-#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT               14
-#define FTM_COMBINE_COMBINE2_MASK                0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT               16
-#define FTM_COMBINE_COMP2_MASK                   0x20000u
-#define FTM_COMBINE_COMP2_SHIFT                  17
-#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT               18
-#define FTM_COMBINE_DECAP2_MASK                  0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT                 19
-#define FTM_COMBINE_DTEN2_MASK                   0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT                  20
-#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT                21
-#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT               22
-#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT               24
-#define FTM_COMBINE_COMP3_MASK                   0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT                  25
-#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT               26
-#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT                 27
-#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT                  28
-#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT                29
-#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT               30
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT                 0
-#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK                   0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT                  6
-#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
-#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
-#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
-#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
-#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
-#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
-#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
-#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT                  7
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK                        0x1u
-#define FTM_POL_POL0_SHIFT                       0
-#define FTM_POL_POL1_MASK                        0x2u
-#define FTM_POL_POL1_SHIFT                       1
-#define FTM_POL_POL2_MASK                        0x4u
-#define FTM_POL_POL2_SHIFT                       2
-#define FTM_POL_POL3_MASK                        0x8u
-#define FTM_POL_POL3_SHIFT                       3
-#define FTM_POL_POL4_MASK                        0x10u
-#define FTM_POL_POL4_SHIFT                       4
-#define FTM_POL_POL5_MASK                        0x20u
-#define FTM_POL_POL5_SHIFT                       5
-#define FTM_POL_POL6_MASK                        0x40u
-#define FTM_POL_POL6_SHIFT                       6
-#define FTM_POL_POL7_MASK                        0x80u
-#define FTM_POL_POL7_SHIFT                       7
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK                     0x1u
-#define FTM_FMS_FAULTF0_SHIFT                    0
-#define FTM_FMS_FAULTF1_MASK                     0x2u
-#define FTM_FMS_FAULTF1_SHIFT                    1
-#define FTM_FMS_FAULTF2_MASK                     0x4u
-#define FTM_FMS_FAULTF2_SHIFT                    2
-#define FTM_FMS_FAULTF3_MASK                     0x8u
-#define FTM_FMS_FAULTF3_SHIFT                    3
-#define FTM_FMS_FAULTIN_MASK                     0x20u
-#define FTM_FMS_FAULTIN_SHIFT                    5
-#define FTM_FMS_WPEN_MASK                        0x40u
-#define FTM_FMS_WPEN_SHIFT                       6
-#define FTM_FMS_FAULTF_MASK                      0x80u
-#define FTM_FMS_FAULTF_SHIFT                     7
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK                  0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT                 0
-#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT                 4
-#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT                 8
-#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT                 12
-#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
-#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
-#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
-#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
-#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
-#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
-#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
-#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
-#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT                  8
-#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK                   0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT                  0
-#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT                  1
-#define FTM_QDCTRL_QUADIR_MASK                   0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT                  2
-#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT                3
-#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT                  4
-#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT                  5
-#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
-#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK                     0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT                    0
-#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK                    0xC0u
-#define FTM_CONF_BDMMODE_SHIFT                   6
-#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK                     0x200u
-#define FTM_CONF_GTBEEN_SHIFT                    9
-#define FTM_CONF_GTBEOUT_MASK                    0x400u
-#define FTM_CONF_GTBEOUT_SHIFT                   10
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT                 0
-#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT                 1
-#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT                 2
-#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT                 3
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
-#define FTM_SYNCONF_CNTINC_MASK                  0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT                 2
-#define FTM_SYNCONF_INVC_MASK                    0x10u
-#define FTM_SYNCONF_INVC_SHIFT                   4
-#define FTM_SYNCONF_SWOC_MASK                    0x20u
-#define FTM_SYNCONF_SWOC_SHIFT                   5
-#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT               7
-#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
-#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT                9
-#define FTM_SYNCONF_SWOM_MASK                    0x400u
-#define FTM_SYNCONF_SWOM_SHIFT                   10
-#define FTM_SYNCONF_SWINVC_MASK                  0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT                 11
-#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT                  12
-#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
-#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT                17
-#define FTM_SYNCONF_HWOM_MASK                    0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT                   18
-#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT                 19
-#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT                  20
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK                  0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT                 0
-#define FTM_INVCTRL_INV1EN_MASK                  0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT                 1
-#define FTM_INVCTRL_INV2EN_MASK                  0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT                 2
-#define FTM_INVCTRL_INV3EN_MASK                  0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT                 3
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT                  0
-#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT                  1
-#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT                  2
-#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT                  3
-#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT                  4
-#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT                  5
-#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT                  6
-#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT                  7
-#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
-#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
-#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
-#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
-#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
-#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
-#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
-#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
-#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
-#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
-#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
-#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
-#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
-#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
-#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
-#define FTM_PWMLOAD_LDOK_MASK                    0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT                   9
+/*! @name SC - Status And Control */
+#define FTM_SC_PS_MASK                           (0x7U)
+#define FTM_SC_PS_SHIFT                          (0U)
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         (0x18U)
+#define FTM_SC_CLKS_SHIFT                        (3U)
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        (0x20U)
+#define FTM_SC_CPWMS_SHIFT                       (5U)
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         (0x40U)
+#define FTM_SC_TOIE_SHIFT                        (6U)
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          (0x80U)
+#define FTM_SC_TOF_SHIFT                         (7U)
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+
+/*! @name CNT - Counter */
+#define FTM_CNT_COUNT_MASK                       (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT                      (0U)
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define FTM_MOD_MOD_MASK                         (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT                        (0U)
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status And Control */
+#define FTM_CnSC_DMA_MASK                        (0x1U)
+#define FTM_CnSC_DMA_SHIFT                       (0U)
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       (0x4U)
+#define FTM_CnSC_ELSA_SHIFT                      (2U)
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       (0x8U)
+#define FTM_CnSC_ELSB_SHIFT                      (3U)
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        (0x10U)
+#define FTM_CnSC_MSA_SHIFT                       (4U)
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        (0x20U)
+#define FTM_CnSC_MSB_SHIFT                       (5U)
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       (0x40U)
+#define FTM_CnSC_CHIE_SHIFT                      (6U)
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        (0x80U)
+#define FTM_CnSC_CHF_SHIFT                       (7U)
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT                           (8U)
+
+/*! @name CnV - Channel (n) Value */
+#define FTM_CnV_VAL_MASK                         (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT                        (0U)
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT                            (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+#define FTM_CNTIN_INIT_MASK                      (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT                     (0U)
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+
+/*! @name STATUS - Capture And Compare Status */
+#define FTM_STATUS_CH0F_MASK                     (0x1U)
+#define FTM_STATUS_CH0F_SHIFT                    (0U)
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     (0x2U)
+#define FTM_STATUS_CH1F_SHIFT                    (1U)
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     (0x4U)
+#define FTM_STATUS_CH2F_SHIFT                    (2U)
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     (0x8U)
+#define FTM_STATUS_CH3F_SHIFT                    (3U)
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     (0x10U)
+#define FTM_STATUS_CH4F_SHIFT                    (4U)
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     (0x20U)
+#define FTM_STATUS_CH5F_SHIFT                    (5U)
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     (0x40U)
+#define FTM_STATUS_CH6F_SHIFT                    (6U)
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     (0x80U)
+#define FTM_STATUS_CH7F_SHIFT                    (7U)
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+
+/*! @name MODE - Features Mode Selection */
+#define FTM_MODE_FTMEN_MASK                      (0x1U)
+#define FTM_MODE_FTMEN_SHIFT                     (0U)
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       (0x2U)
+#define FTM_MODE_INIT_SHIFT                      (1U)
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      (0x4U)
+#define FTM_MODE_WPDIS_SHIFT                     (2U)
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    (0x8U)
+#define FTM_MODE_PWMSYNC_SHIFT                   (3U)
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    (0x10U)
+#define FTM_MODE_CAPTEST_SHIFT                   (4U)
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     (0x60U)
+#define FTM_MODE_FAULTM_SHIFT                    (5U)
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    (0x80U)
+#define FTM_MODE_FAULTIE_SHIFT                   (7U)
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+
+/*! @name SYNC - Synchronization */
+#define FTM_SYNC_CNTMIN_MASK                     (0x1U)
+#define FTM_SYNC_CNTMIN_SHIFT                    (0U)
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     (0x2U)
+#define FTM_SYNC_CNTMAX_SHIFT                    (1U)
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     (0x4U)
+#define FTM_SYNC_REINIT_SHIFT                    (2U)
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    (0x8U)
+#define FTM_SYNC_SYNCHOM_SHIFT                   (3U)
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      (0x10U)
+#define FTM_SYNC_TRIG0_SHIFT                     (4U)
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      (0x20U)
+#define FTM_SYNC_TRIG1_SHIFT                     (5U)
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      (0x40U)
+#define FTM_SYNC_TRIG2_SHIFT                     (6U)
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     (0x80U)
+#define FTM_SYNC_SWSYNC_SHIFT                    (7U)
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+
+/*! @name OUTINIT - Initial State For Channels Output */
+#define FTM_OUTINIT_CH0OI_MASK                   (0x1U)
+#define FTM_OUTINIT_CH0OI_SHIFT                  (0U)
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   (0x2U)
+#define FTM_OUTINIT_CH1OI_SHIFT                  (1U)
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   (0x4U)
+#define FTM_OUTINIT_CH2OI_SHIFT                  (2U)
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   (0x8U)
+#define FTM_OUTINIT_CH3OI_SHIFT                  (3U)
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   (0x10U)
+#define FTM_OUTINIT_CH4OI_SHIFT                  (4U)
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   (0x20U)
+#define FTM_OUTINIT_CH5OI_SHIFT                  (5U)
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   (0x40U)
+#define FTM_OUTINIT_CH6OI_SHIFT                  (6U)
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   (0x80U)
+#define FTM_OUTINIT_CH7OI_SHIFT                  (7U)
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+
+/*! @name OUTMASK - Output Mask */
+#define FTM_OUTMASK_CH0OM_MASK                   (0x1U)
+#define FTM_OUTMASK_CH0OM_SHIFT                  (0U)
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   (0x2U)
+#define FTM_OUTMASK_CH1OM_SHIFT                  (1U)
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   (0x4U)
+#define FTM_OUTMASK_CH2OM_SHIFT                  (2U)
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   (0x8U)
+#define FTM_OUTMASK_CH3OM_SHIFT                  (3U)
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   (0x10U)
+#define FTM_OUTMASK_CH4OM_SHIFT                  (4U)
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   (0x20U)
+#define FTM_OUTMASK_CH5OM_SHIFT                  (5U)
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   (0x40U)
+#define FTM_OUTMASK_CH6OM_SHIFT                  (6U)
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   (0x80U)
+#define FTM_OUTMASK_CH7OM_SHIFT                  (7U)
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+
+/*! @name COMBINE - Function For Linked Channels */
+#define FTM_COMBINE_COMBINE0_MASK                (0x1U)
+#define FTM_COMBINE_COMBINE0_SHIFT               (0U)
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   (0x2U)
+#define FTM_COMBINE_COMP0_SHIFT                  (1U)
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                (0x4U)
+#define FTM_COMBINE_DECAPEN0_SHIFT               (2U)
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  (0x8U)
+#define FTM_COMBINE_DECAP0_SHIFT                 (3U)
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   (0x10U)
+#define FTM_COMBINE_DTEN0_SHIFT                  (4U)
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 (0x20U)
+#define FTM_COMBINE_SYNCEN0_SHIFT                (5U)
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                (0x40U)
+#define FTM_COMBINE_FAULTEN0_SHIFT               (6U)
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                (0x100U)
+#define FTM_COMBINE_COMBINE1_SHIFT               (8U)
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   (0x200U)
+#define FTM_COMBINE_COMP1_SHIFT                  (9U)
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                (0x400U)
+#define FTM_COMBINE_DECAPEN1_SHIFT               (10U)
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  (0x800U)
+#define FTM_COMBINE_DECAP1_SHIFT                 (11U)
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   (0x1000U)
+#define FTM_COMBINE_DTEN1_SHIFT                  (12U)
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 (0x2000U)
+#define FTM_COMBINE_SYNCEN1_SHIFT                (13U)
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                (0x4000U)
+#define FTM_COMBINE_FAULTEN1_SHIFT               (14U)
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                (0x10000U)
+#define FTM_COMBINE_COMBINE2_SHIFT               (16U)
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   (0x20000U)
+#define FTM_COMBINE_COMP2_SHIFT                  (17U)
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                (0x40000U)
+#define FTM_COMBINE_DECAPEN2_SHIFT               (18U)
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  (0x80000U)
+#define FTM_COMBINE_DECAP2_SHIFT                 (19U)
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   (0x100000U)
+#define FTM_COMBINE_DTEN2_SHIFT                  (20U)
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 (0x200000U)
+#define FTM_COMBINE_SYNCEN2_SHIFT                (21U)
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                (0x400000U)
+#define FTM_COMBINE_FAULTEN2_SHIFT               (22U)
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                (0x1000000U)
+#define FTM_COMBINE_COMBINE3_SHIFT               (24U)
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   (0x2000000U)
+#define FTM_COMBINE_COMP3_SHIFT                  (25U)
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                (0x4000000U)
+#define FTM_COMBINE_DECAPEN3_SHIFT               (26U)
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  (0x8000000U)
+#define FTM_COMBINE_DECAP3_SHIFT                 (27U)
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   (0x10000000U)
+#define FTM_COMBINE_DTEN3_SHIFT                  (28U)
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 (0x20000000U)
+#define FTM_COMBINE_SYNCEN3_SHIFT                (29U)
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                (0x40000000U)
+#define FTM_COMBINE_FAULTEN3_SHIFT               (30U)
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+#define FTM_DEADTIME_DTVAL_MASK                  (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT                 (0U)
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT                  (6U)
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+
+/*! @name EXTTRIG - FTM External Trigger */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 (0x1U)
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                (0U)
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 (0x2U)
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                (1U)
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 (0x4U)
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                (2U)
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 (0x8U)
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                (3U)
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 (0x10U)
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                (4U)
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 (0x20U)
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                (5U)
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              (0x40U)
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             (6U)
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   (0x80U)
+#define FTM_EXTTRIG_TRIGF_SHIFT                  (7U)
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+
+/*! @name POL - Channels Polarity */
+#define FTM_POL_POL0_MASK                        (0x1U)
+#define FTM_POL_POL0_SHIFT                       (0U)
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        (0x2U)
+#define FTM_POL_POL1_SHIFT                       (1U)
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        (0x4U)
+#define FTM_POL_POL2_SHIFT                       (2U)
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        (0x8U)
+#define FTM_POL_POL3_SHIFT                       (3U)
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        (0x10U)
+#define FTM_POL_POL4_SHIFT                       (4U)
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        (0x20U)
+#define FTM_POL_POL5_SHIFT                       (5U)
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        (0x40U)
+#define FTM_POL_POL6_SHIFT                       (6U)
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        (0x80U)
+#define FTM_POL_POL7_SHIFT                       (7U)
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+
+/*! @name FMS - Fault Mode Status */
+#define FTM_FMS_FAULTF0_MASK                     (0x1U)
+#define FTM_FMS_FAULTF0_SHIFT                    (0U)
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     (0x2U)
+#define FTM_FMS_FAULTF1_SHIFT                    (1U)
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     (0x4U)
+#define FTM_FMS_FAULTF2_SHIFT                    (2U)
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     (0x8U)
+#define FTM_FMS_FAULTF3_SHIFT                    (3U)
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     (0x20U)
+#define FTM_FMS_FAULTIN_SHIFT                    (5U)
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        (0x40U)
+#define FTM_FMS_WPEN_SHIFT                       (6U)
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      (0x80U)
+#define FTM_FMS_FAULTF_SHIFT                     (7U)
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+
+/*! @name FILTER - Input Capture Filter Control */
+#define FTM_FILTER_CH0FVAL_MASK                  (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT                 (0U)
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT                 (4U)
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT                 (8U)
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT                 (12U)
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+
+/*! @name FLTCTRL - Fault Control */
+#define FTM_FLTCTRL_FAULT0EN_MASK                (0x1U)
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               (0U)
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                (0x2U)
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               (1U)
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                (0x4U)
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               (2U)
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                (0x8U)
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               (3U)
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                (0x10U)
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               (4U)
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                (0x20U)
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               (5U)
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                (0x40U)
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               (6U)
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                (0x80U)
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               (7U)
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT                  (8U)
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control And Status */
+#define FTM_QDCTRL_QUADEN_MASK                   (0x1U)
+#define FTM_QDCTRL_QUADEN_SHIFT                  (0U)
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   (0x2U)
+#define FTM_QDCTRL_TOFDIR_SHIFT                  (1U)
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   (0x4U)
+#define FTM_QDCTRL_QUADIR_SHIFT                  (2U)
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 (0x8U)
+#define FTM_QDCTRL_QUADMODE_SHIFT                (3U)
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   (0x10U)
+#define FTM_QDCTRL_PHBPOL_SHIFT                  (4U)
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   (0x20U)
+#define FTM_QDCTRL_PHAPOL_SHIFT                  (5U)
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                (0x40U)
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               (6U)
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                (0x80U)
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               (7U)
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+
+/*! @name CONF - Configuration */
+#define FTM_CONF_NUMTOF_MASK                     (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT                    (0U)
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT                   (6U)
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     (0x200U)
+#define FTM_CONF_GTBEEN_SHIFT                    (9U)
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    (0x400U)
+#define FTM_CONF_GTBEOUT_SHIFT                   (10U)
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+#define FTM_FLTPOL_FLT0POL_MASK                  (0x1U)
+#define FTM_FLTPOL_FLT0POL_SHIFT                 (0U)
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  (0x2U)
+#define FTM_FLTPOL_FLT1POL_SHIFT                 (1U)
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  (0x4U)
+#define FTM_FLTPOL_FLT2POL_SHIFT                 (2U)
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  (0x8U)
+#define FTM_FLTPOL_FLT3POL_SHIFT                 (3U)
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+
+/*! @name SYNCONF - Synchronization Configuration */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              (0x1U)
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             (0U)
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  (0x4U)
+#define FTM_SYNCONF_CNTINC_SHIFT                 (2U)
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    (0x10U)
+#define FTM_SYNCONF_INVC_SHIFT                   (4U)
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    (0x20U)
+#define FTM_SYNCONF_SWOC_SHIFT                   (5U)
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                (0x80U)
+#define FTM_SYNCONF_SYNCMODE_SHIFT               (7U)
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                (0x100U)
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               (8U)
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 (0x200U)
+#define FTM_SYNCONF_SWWRBUF_SHIFT                (9U)
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    (0x400U)
+#define FTM_SYNCONF_SWOM_SHIFT                   (10U)
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  (0x800U)
+#define FTM_SYNCONF_SWINVC_SHIFT                 (11U)
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   (0x1000U)
+#define FTM_SYNCONF_SWSOC_SHIFT                  (12U)
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                (0x10000U)
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               (16U)
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 (0x20000U)
+#define FTM_SYNCONF_HWWRBUF_SHIFT                (17U)
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    (0x40000U)
+#define FTM_SYNCONF_HWOM_SHIFT                   (18U)
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  (0x80000U)
+#define FTM_SYNCONF_HWINVC_SHIFT                 (19U)
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   (0x100000U)
+#define FTM_SYNCONF_HWSOC_SHIFT                  (20U)
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+
+/*! @name INVCTRL - FTM Inverting Control */
+#define FTM_INVCTRL_INV0EN_MASK                  (0x1U)
+#define FTM_INVCTRL_INV0EN_SHIFT                 (0U)
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  (0x2U)
+#define FTM_INVCTRL_INV1EN_SHIFT                 (1U)
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  (0x4U)
+#define FTM_INVCTRL_INV2EN_SHIFT                 (2U)
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  (0x8U)
+#define FTM_INVCTRL_INV3EN_SHIFT                 (3U)
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+
+/*! @name SWOCTRL - FTM Software Output Control */
+#define FTM_SWOCTRL_CH0OC_MASK                   (0x1U)
+#define FTM_SWOCTRL_CH0OC_SHIFT                  (0U)
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   (0x2U)
+#define FTM_SWOCTRL_CH1OC_SHIFT                  (1U)
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   (0x4U)
+#define FTM_SWOCTRL_CH2OC_SHIFT                  (2U)
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   (0x8U)
+#define FTM_SWOCTRL_CH3OC_SHIFT                  (3U)
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   (0x10U)
+#define FTM_SWOCTRL_CH4OC_SHIFT                  (4U)
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   (0x20U)
+#define FTM_SWOCTRL_CH5OC_SHIFT                  (5U)
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   (0x40U)
+#define FTM_SWOCTRL_CH6OC_SHIFT                  (6U)
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   (0x80U)
+#define FTM_SWOCTRL_CH7OC_SHIFT                  (7U)
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  (0x100U)
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 (8U)
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  (0x200U)
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 (9U)
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  (0x400U)
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 (10U)
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  (0x800U)
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 (11U)
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  (0x1000U)
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 (12U)
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  (0x2000U)
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 (13U)
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  (0x4000U)
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 (14U)
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  (0x8000U)
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 (15U)
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+
+/*! @name PWMLOAD - FTM PWM Load */
+#define FTM_PWMLOAD_CH0SEL_MASK                  (0x1U)
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 (0U)
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  (0x2U)
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 (1U)
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  (0x4U)
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 (2U)
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  (0x8U)
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 (3U)
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  (0x10U)
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 (4U)
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  (0x20U)
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 (5U)
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  (0x40U)
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 (6U)
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  (0x80U)
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 (7U)
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    (0x200U)
+#define FTM_PWMLOAD_LDOK_SHIFT                   (9U)
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+
 
 /*!
  * @}
@@ -7295,17 +6815,14 @@ typedef struct {
 #define FTM0_BASE                                (0x40038000u)
 /** Peripheral FTM0 base pointer */
 #define FTM0                                     ((FTM_Type *)FTM0_BASE)
-#define FTM0_BASE_PTR                            (FTM0)
 /** Peripheral FTM1 base address */
 #define FTM1_BASE                                (0x40039000u)
 /** Peripheral FTM1 base pointer */
 #define FTM1                                     ((FTM_Type *)FTM1_BASE)
-#define FTM1_BASE_PTR                            (FTM1)
 /** Peripheral FTM2 base address */
 #define FTM2_BASE                                (0x400B8000u)
 /** Peripheral FTM2 base pointer */
 #define FTM2                                     ((FTM_Type *)FTM2_BASE)
-#define FTM2_BASE_PTR                            (FTM2)
 /** Array initializer of FTM peripheral base addresses */
 #define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE }
 /** Array initializer of FTM peripheral base pointers */
@@ -7313,127 +6830,6 @@ typedef struct {
 /** Interrupt vectors for the FTM peripheral type */
 #define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- FTM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register instance definitions */
-/* FTM0 */
-#define FTM0_SC                                  FTM_SC_REG(FTM0)
-#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
-#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
-#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
-#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
-#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
-#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
-#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
-#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
-#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
-#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
-#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
-#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
-#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
-#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
-#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
-#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
-#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
-#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
-#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
-#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
-#define FTM0_MODE                                FTM_MODE_REG(FTM0)
-#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
-#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
-#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
-#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
-#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
-#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
-#define FTM0_POL                                 FTM_POL_REG(FTM0)
-#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
-#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
-#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
-#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
-#define FTM0_CONF                                FTM_CONF_REG(FTM0)
-#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
-#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
-#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
-#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
-#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
-/* FTM1 */
-#define FTM1_SC                                  FTM_SC_REG(FTM1)
-#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
-#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
-#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
-#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
-#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
-#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
-#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
-#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
-#define FTM1_MODE                                FTM_MODE_REG(FTM1)
-#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
-#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
-#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
-#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
-#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
-#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
-#define FTM1_POL                                 FTM_POL_REG(FTM1)
-#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
-#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
-#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
-#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
-#define FTM1_CONF                                FTM_CONF_REG(FTM1)
-#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
-#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
-#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
-#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
-#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
-/* FTM2 */
-#define FTM2_SC                                  FTM_SC_REG(FTM2)
-#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
-#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
-#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
-#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
-#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
-#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
-#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
-#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
-#define FTM2_MODE                                FTM_MODE_REG(FTM2)
-#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
-#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
-#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
-#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
-#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
-#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
-#define FTM2_POL                                 FTM_POL_REG(FTM2)
-#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
-#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
-#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
-#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
-#define FTM2_CONF                                FTM_CONF_REG(FTM2)
-#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
-#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
-#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
-#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
-#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
-
-/* FTM - Register array accessors */
-#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
-#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
-#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
-#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
-#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
-#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group FTM_Peripheral_Access_Layer */
@@ -7456,64 +6852,47 @@ typedef struct {
   __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
   __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
   __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type, *GPIO_MemMapPtr;
+} GPIO_Type;
 
 /* ----------------------------------------------------------------------------
-   -- GPIO - Register accessor macros
+   -- GPIO Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
  * @{
  */
 
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT                      (0U)
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
 
-/* GPIO - Register accessors */
-#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
-#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
-#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
-#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
-#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
-#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT                     (0U)
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
 
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT                     (0U)
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
 
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT                     (0U)
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
 
-/* ----------------------------------------------------------------------------
-   -- GPIO Register Masks
-   ---------------------------------------------------------------------------- */
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT                      (0U)
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
 
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT                      (0U)
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
 
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT                      0
-#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT                     0
-#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT                     0
-#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT                     0
-#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT                      0
-#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT                      0
-#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
 
 /*!
  * @}
@@ -7525,95 +6904,38 @@ typedef struct {
 #define GPIOA_BASE                               (0x400FF000u)
 /** Peripheral GPIOA base pointer */
 #define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
-#define GPIOA_BASE_PTR                           (GPIOA)
 /** Peripheral GPIOB base address */
 #define GPIOB_BASE                               (0x400FF040u)
 /** Peripheral GPIOB base pointer */
 #define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
-#define GPIOB_BASE_PTR                           (GPIOB)
 /** Peripheral GPIOC base address */
 #define GPIOC_BASE                               (0x400FF080u)
 /** Peripheral GPIOC base pointer */
 #define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
-#define GPIOC_BASE_PTR                           (GPIOC)
 /** Peripheral GPIOD base address */
 #define GPIOD_BASE                               (0x400FF0C0u)
 /** Peripheral GPIOD base pointer */
 #define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
-#define GPIOD_BASE_PTR                           (GPIOD)
 /** Peripheral GPIOE base address */
 #define GPIOE_BASE                               (0x400FF100u)
 /** Peripheral GPIOE base pointer */
 #define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
-#define GPIOE_BASE_PTR                           (GPIOE)
 /** Array initializer of GPIO peripheral base addresses */
 #define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
 /** Array initializer of GPIO peripheral base pointers */
 #define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
 
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
 /* ----------------------------------------------------------------------------
-   -- GPIO - Register accessor macros
+   -- I2C Peripheral Access Layer
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register instance definitions */
-/* GPIOA */
-#define GPIOA_PDOR                               GPIO_PDOR_REG(GPIOA)
-#define GPIOA_PSOR                               GPIO_PSOR_REG(GPIOA)
-#define GPIOA_PCOR                               GPIO_PCOR_REG(GPIOA)
-#define GPIOA_PTOR                               GPIO_PTOR_REG(GPIOA)
-#define GPIOA_PDIR                               GPIO_PDIR_REG(GPIOA)
-#define GPIOA_PDDR                               GPIO_PDDR_REG(GPIOA)
-/* GPIOB */
-#define GPIOB_PDOR                               GPIO_PDOR_REG(GPIOB)
-#define GPIOB_PSOR                               GPIO_PSOR_REG(GPIOB)
-#define GPIOB_PCOR                               GPIO_PCOR_REG(GPIOB)
-#define GPIOB_PTOR                               GPIO_PTOR_REG(GPIOB)
-#define GPIOB_PDIR                               GPIO_PDIR_REG(GPIOB)
-#define GPIOB_PDDR                               GPIO_PDDR_REG(GPIOB)
-/* GPIOC */
-#define GPIOC_PDOR                               GPIO_PDOR_REG(GPIOC)
-#define GPIOC_PSOR                               GPIO_PSOR_REG(GPIOC)
-#define GPIOC_PCOR                               GPIO_PCOR_REG(GPIOC)
-#define GPIOC_PTOR                               GPIO_PTOR_REG(GPIOC)
-#define GPIOC_PDIR                               GPIO_PDIR_REG(GPIOC)
-#define GPIOC_PDDR                               GPIO_PDDR_REG(GPIOC)
-/* GPIOD */
-#define GPIOD_PDOR                               GPIO_PDOR_REG(GPIOD)
-#define GPIOD_PSOR                               GPIO_PSOR_REG(GPIOD)
-#define GPIOD_PCOR                               GPIO_PCOR_REG(GPIOD)
-#define GPIOD_PTOR                               GPIO_PTOR_REG(GPIOD)
-#define GPIOD_PDIR                               GPIO_PDIR_REG(GPIOD)
-#define GPIOD_PDDR                               GPIO_PDDR_REG(GPIOD)
-/* GPIOE */
-#define GPIOE_PDOR                               GPIO_PDOR_REG(GPIOE)
-#define GPIOE_PSOR                               GPIO_PSOR_REG(GPIOE)
-#define GPIOE_PCOR                               GPIO_PCOR_REG(GPIOE)
-#define GPIOE_PTOR                               GPIO_PTOR_REG(GPIOE)
-#define GPIOE_PDIR                               GPIO_PDIR_REG(GPIOE)
-#define GPIOE_PDDR                               GPIO_PDDR_REG(GPIOE)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- I2C Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
  * @{
  */
 
@@ -7631,36 +6953,7 @@ typedef struct {
   __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
   __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
   __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type, *I2C_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- I2C - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register accessors */
-#define I2C_A1_REG(base)                         ((base)->A1)
-#define I2C_F_REG(base)                          ((base)->F)
-#define I2C_C1_REG(base)                         ((base)->C1)
-#define I2C_S_REG(base)                          ((base)->S)
-#define I2C_D_REG(base)                          ((base)->D)
-#define I2C_C2_REG(base)                         ((base)->C2)
-#define I2C_FLT_REG(base)                        ((base)->FLT)
-#define I2C_RA_REG(base)                         ((base)->RA)
-#define I2C_SMB_REG(base)                        ((base)->SMB)
-#define I2C_A2_REG(base)                         ((base)->A2)
-#define I2C_SLTH_REG(base)                       ((base)->SLTH)
-#define I2C_SLTL_REG(base)                       ((base)->SLTL)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
+} I2C_Type;
 
 /* ----------------------------------------------------------------------------
    -- I2C Register Masks
@@ -7671,106 +6964,147 @@ typedef struct {
  * @{
  */
 
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK                           0xFEu
-#define I2C_A1_AD_SHIFT                          1
-#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK                           0x3Fu
-#define I2C_F_ICR_SHIFT                          0
-#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK                          0xC0u
-#define I2C_F_MULT_SHIFT                         6
-#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK                        0x1u
-#define I2C_C1_DMAEN_SHIFT                       0
-#define I2C_C1_WUEN_MASK                         0x2u
-#define I2C_C1_WUEN_SHIFT                        1
-#define I2C_C1_RSTA_MASK                         0x4u
-#define I2C_C1_RSTA_SHIFT                        2
-#define I2C_C1_TXAK_MASK                         0x8u
-#define I2C_C1_TXAK_SHIFT                        3
-#define I2C_C1_TX_MASK                           0x10u
-#define I2C_C1_TX_SHIFT                          4
-#define I2C_C1_MST_MASK                          0x20u
-#define I2C_C1_MST_SHIFT                         5
-#define I2C_C1_IICIE_MASK                        0x40u
-#define I2C_C1_IICIE_SHIFT                       6
-#define I2C_C1_IICEN_MASK                        0x80u
-#define I2C_C1_IICEN_SHIFT                       7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK                          0x1u
-#define I2C_S_RXAK_SHIFT                         0
-#define I2C_S_IICIF_MASK                         0x2u
-#define I2C_S_IICIF_SHIFT                        1
-#define I2C_S_SRW_MASK                           0x4u
-#define I2C_S_SRW_SHIFT                          2
-#define I2C_S_RAM_MASK                           0x8u
-#define I2C_S_RAM_SHIFT                          3
-#define I2C_S_ARBL_MASK                          0x10u
-#define I2C_S_ARBL_SHIFT                         4
-#define I2C_S_BUSY_MASK                          0x20u
-#define I2C_S_BUSY_SHIFT                         5
-#define I2C_S_IAAS_MASK                          0x40u
-#define I2C_S_IAAS_SHIFT                         6
-#define I2C_S_TCF_MASK                           0x80u
-#define I2C_S_TCF_SHIFT                          7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK                          0xFFu
-#define I2C_D_DATA_SHIFT                         0
-#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK                           0x7u
-#define I2C_C2_AD_SHIFT                          0
-#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK                         0x8u
-#define I2C_C2_RMEN_SHIFT                        3
-#define I2C_C2_SBRC_MASK                         0x10u
-#define I2C_C2_SBRC_SHIFT                        4
-#define I2C_C2_HDRS_MASK                         0x20u
-#define I2C_C2_HDRS_SHIFT                        5
-#define I2C_C2_ADEXT_MASK                        0x40u
-#define I2C_C2_ADEXT_SHIFT                       6
-#define I2C_C2_GCAEN_MASK                        0x80u
-#define I2C_C2_GCAEN_SHIFT                       7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK                         0x1Fu
-#define I2C_FLT_FLT_SHIFT                        0
-#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK                          0xFEu
-#define I2C_RA_RAD_SHIFT                         1
-#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK                     0x1u
-#define I2C_SMB_SHTF2IE_SHIFT                    0
-#define I2C_SMB_SHTF2_MASK                       0x2u
-#define I2C_SMB_SHTF2_SHIFT                      1
-#define I2C_SMB_SHTF1_MASK                       0x4u
-#define I2C_SMB_SHTF1_SHIFT                      2
-#define I2C_SMB_SLTF_MASK                        0x8u
-#define I2C_SMB_SLTF_SHIFT                       3
-#define I2C_SMB_TCKSEL_MASK                      0x10u
-#define I2C_SMB_TCKSEL_SHIFT                     4
-#define I2C_SMB_SIICAEN_MASK                     0x20u
-#define I2C_SMB_SIICAEN_SHIFT                    5
-#define I2C_SMB_ALERTEN_MASK                     0x40u
-#define I2C_SMB_ALERTEN_SHIFT                    6
-#define I2C_SMB_FACK_MASK                        0x80u
-#define I2C_SMB_FACK_SHIFT                       7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK                          0xFEu
-#define I2C_A2_SAD_SHIFT                         1
-#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK                       0xFFu
-#define I2C_SLTH_SSLT_SHIFT                      0
-#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK                       0xFFu
-#define I2C_SLTL_SSLT_SHIFT                      0
-#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK                           (0xFEU)
+#define I2C_A1_AD_SHIFT                          (1U)
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK                           (0x3FU)
+#define I2C_F_ICR_SHIFT                          (0U)
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          (0xC0U)
+#define I2C_F_MULT_SHIFT                         (6U)
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK                        (0x1U)
+#define I2C_C1_DMAEN_SHIFT                       (0U)
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         (0x2U)
+#define I2C_C1_WUEN_SHIFT                        (1U)
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         (0x4U)
+#define I2C_C1_RSTA_SHIFT                        (2U)
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         (0x8U)
+#define I2C_C1_TXAK_SHIFT                        (3U)
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           (0x10U)
+#define I2C_C1_TX_SHIFT                          (4U)
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          (0x20U)
+#define I2C_C1_MST_SHIFT                         (5U)
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        (0x40U)
+#define I2C_C1_IICIE_SHIFT                       (6U)
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        (0x80U)
+#define I2C_C1_IICEN_SHIFT                       (7U)
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK                          (0x1U)
+#define I2C_S_RXAK_SHIFT                         (0U)
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         (0x2U)
+#define I2C_S_IICIF_SHIFT                        (1U)
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           (0x4U)
+#define I2C_S_SRW_SHIFT                          (2U)
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           (0x8U)
+#define I2C_S_RAM_SHIFT                          (3U)
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          (0x10U)
+#define I2C_S_ARBL_SHIFT                         (4U)
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          (0x20U)
+#define I2C_S_BUSY_SHIFT                         (5U)
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          (0x40U)
+#define I2C_S_IAAS_SHIFT                         (6U)
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           (0x80U)
+#define I2C_S_TCF_SHIFT                          (7U)
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK                          (0xFFU)
+#define I2C_D_DATA_SHIFT                         (0U)
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK                           (0x7U)
+#define I2C_C2_AD_SHIFT                          (0U)
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         (0x8U)
+#define I2C_C2_RMEN_SHIFT                        (3U)
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         (0x10U)
+#define I2C_C2_SBRC_SHIFT                        (4U)
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         (0x20U)
+#define I2C_C2_HDRS_SHIFT                        (5U)
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        (0x40U)
+#define I2C_C2_ADEXT_SHIFT                       (6U)
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        (0x80U)
+#define I2C_C2_GCAEN_SHIFT                       (7U)
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter register */
+#define I2C_FLT_FLT_MASK                         (0x1FU)
+#define I2C_FLT_FLT_SHIFT                        (0U)
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK                          (0xFEU)
+#define I2C_RA_RAD_SHIFT                         (1U)
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK                     (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT                    (0U)
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       (0x2U)
+#define I2C_SMB_SHTF2_SHIFT                      (1U)
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       (0x4U)
+#define I2C_SMB_SHTF1_SHIFT                      (2U)
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        (0x8U)
+#define I2C_SMB_SLTF_SHIFT                       (3U)
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT                     (4U)
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT                    (5U)
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT                    (6U)
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        (0x80U)
+#define I2C_SMB_FACK_SHIFT                       (7U)
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK                          (0xFEU)
+#define I2C_A2_SAD_SHIFT                         (1U)
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK                       (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT                      (0U)
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK                       (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT                      (0U)
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
 
 /*!
  * @}
@@ -7782,12 +7116,10 @@ typedef struct {
 #define I2C0_BASE                                (0x40066000u)
 /** Peripheral I2C0 base pointer */
 #define I2C0                                     ((I2C_Type *)I2C0_BASE)
-#define I2C0_BASE_PTR                            (I2C0)
 /** Peripheral I2C1 base address */
 #define I2C1_BASE                                (0x40067000u)
 /** Peripheral I2C1 base pointer */
 #define I2C1                                     ((I2C_Type *)I2C1_BASE)
-#define I2C1_BASE_PTR                            (I2C1)
 /** Array initializer of I2C peripheral base addresses */
 #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
 /** Array initializer of I2C peripheral base pointers */
@@ -7795,49 +7127,6 @@ typedef struct {
 /** Interrupt vectors for the I2C peripheral type */
 #define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- I2C - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register instance definitions */
-/* I2C0 */
-#define I2C0_A1                                  I2C_A1_REG(I2C0)
-#define I2C0_F                                   I2C_F_REG(I2C0)
-#define I2C0_C1                                  I2C_C1_REG(I2C0)
-#define I2C0_S                                   I2C_S_REG(I2C0)
-#define I2C0_D                                   I2C_D_REG(I2C0)
-#define I2C0_C2                                  I2C_C2_REG(I2C0)
-#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
-#define I2C0_RA                                  I2C_RA_REG(I2C0)
-#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
-#define I2C0_A2                                  I2C_A2_REG(I2C0)
-#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
-#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
-/* I2C1 */
-#define I2C1_A1                                  I2C_A1_REG(I2C1)
-#define I2C1_F                                   I2C_F_REG(I2C1)
-#define I2C1_C1                                  I2C_C1_REG(I2C1)
-#define I2C1_S                                   I2C_S_REG(I2C1)
-#define I2C1_D                                   I2C_D_REG(I2C1)
-#define I2C1_C2                                  I2C_C2_REG(I2C1)
-#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
-#define I2C1_RA                                  I2C_RA_REG(I2C1)
-#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
-#define I2C1_A2                                  I2C_A2_REG(I2C1)
-#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
-#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group I2C_Peripheral_Access_Layer */
@@ -7882,44 +7171,7 @@ typedef struct {
        uint8_t RESERVED_7[28];
   __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
   __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
-} I2S_Type, *I2S_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- I2S - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register accessors */
-#define I2S_TCSR_REG(base)                       ((base)->TCSR)
-#define I2S_TCR1_REG(base)                       ((base)->TCR1)
-#define I2S_TCR2_REG(base)                       ((base)->TCR2)
-#define I2S_TCR3_REG(base)                       ((base)->TCR3)
-#define I2S_TCR4_REG(base)                       ((base)->TCR4)
-#define I2S_TCR5_REG(base)                       ((base)->TCR5)
-#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
-#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
-#define I2S_TMR_REG(base)                        ((base)->TMR)
-#define I2S_RCSR_REG(base)                       ((base)->RCSR)
-#define I2S_RCR1_REG(base)                       ((base)->RCR1)
-#define I2S_RCR2_REG(base)                       ((base)->RCR2)
-#define I2S_RCR3_REG(base)                       ((base)->RCR3)
-#define I2S_RCR4_REG(base)                       ((base)->RCR4)
-#define I2S_RCR5_REG(base)                       ((base)->RCR5)
-#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
-#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
-#define I2S_RMR_REG(base)                        ((base)->RMR)
-#define I2S_MCR_REG(base)                        ((base)->MCR)
-#define I2S_MDR_REG(base)                        ((base)->MDR)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
+} I2S_Type;
 
 /* ----------------------------------------------------------------------------
    -- I2S Register Masks
@@ -7930,233 +7182,319 @@ typedef struct {
  * @{
  */
 
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK                       0x1u
-#define I2S_TCSR_FRDE_SHIFT                      0
-#define I2S_TCSR_FWDE_MASK                       0x2u
-#define I2S_TCSR_FWDE_SHIFT                      1
-#define I2S_TCSR_FRIE_MASK                       0x100u
-#define I2S_TCSR_FRIE_SHIFT                      8
-#define I2S_TCSR_FWIE_MASK                       0x200u
-#define I2S_TCSR_FWIE_SHIFT                      9
-#define I2S_TCSR_FEIE_MASK                       0x400u
-#define I2S_TCSR_FEIE_SHIFT                      10
-#define I2S_TCSR_SEIE_MASK                       0x800u
-#define I2S_TCSR_SEIE_SHIFT                      11
-#define I2S_TCSR_WSIE_MASK                       0x1000u
-#define I2S_TCSR_WSIE_SHIFT                      12
-#define I2S_TCSR_FRF_MASK                        0x10000u
-#define I2S_TCSR_FRF_SHIFT                       16
-#define I2S_TCSR_FWF_MASK                        0x20000u
-#define I2S_TCSR_FWF_SHIFT                       17
-#define I2S_TCSR_FEF_MASK                        0x40000u
-#define I2S_TCSR_FEF_SHIFT                       18
-#define I2S_TCSR_SEF_MASK                        0x80000u
-#define I2S_TCSR_SEF_SHIFT                       19
-#define I2S_TCSR_WSF_MASK                        0x100000u
-#define I2S_TCSR_WSF_SHIFT                       20
-#define I2S_TCSR_SR_MASK                         0x1000000u
-#define I2S_TCSR_SR_SHIFT                        24
-#define I2S_TCSR_FR_MASK                         0x2000000u
-#define I2S_TCSR_FR_SHIFT                        25
-#define I2S_TCSR_BCE_MASK                        0x10000000u
-#define I2S_TCSR_BCE_SHIFT                       28
-#define I2S_TCSR_DBGE_MASK                       0x20000000u
-#define I2S_TCSR_DBGE_SHIFT                      29
-#define I2S_TCSR_STOPE_MASK                      0x40000000u
-#define I2S_TCSR_STOPE_SHIFT                     30
-#define I2S_TCSR_TE_MASK                         0x80000000u
-#define I2S_TCSR_TE_SHIFT                        31
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK                        0x7u
-#define I2S_TCR1_TFW_SHIFT                       0
-#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK                        0xFFu
-#define I2S_TCR2_DIV_SHIFT                       0
-#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK                        0x1000000u
-#define I2S_TCR2_BCD_SHIFT                       24
-#define I2S_TCR2_BCP_MASK                        0x2000000u
-#define I2S_TCR2_BCP_SHIFT                       25
-#define I2S_TCR2_MSEL_MASK                       0xC000000u
-#define I2S_TCR2_MSEL_SHIFT                      26
-#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK                        0x10000000u
-#define I2S_TCR2_BCI_SHIFT                       28
-#define I2S_TCR2_BCS_MASK                        0x20000000u
-#define I2S_TCR2_BCS_SHIFT                       29
-#define I2S_TCR2_SYNC_MASK                       0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT                      30
-#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK                       0x1Fu
-#define I2S_TCR3_WDFL_SHIFT                      0
-#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK                        0x30000u
-#define I2S_TCR3_TCE_SHIFT                       16
-#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK                        0x1u
-#define I2S_TCR4_FSD_SHIFT                       0
-#define I2S_TCR4_FSP_MASK                        0x2u
-#define I2S_TCR4_FSP_SHIFT                       1
-#define I2S_TCR4_FSE_MASK                        0x8u
-#define I2S_TCR4_FSE_SHIFT                       3
-#define I2S_TCR4_MF_MASK                         0x10u
-#define I2S_TCR4_MF_SHIFT                        4
-#define I2S_TCR4_SYWD_MASK                       0x1F00u
-#define I2S_TCR4_SYWD_SHIFT                      8
-#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
-#define I2S_TCR4_FRSZ_SHIFT                      16
-#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK                        0x1F00u
-#define I2S_TCR5_FBT_SHIFT                       8
-#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK                        0x1F0000u
-#define I2S_TCR5_W0W_SHIFT                       16
-#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK                        0x1F000000u
-#define I2S_TCR5_WNW_SHIFT                       24
-#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT                        0
-#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK                         0xFu
-#define I2S_TFR_RFP_SHIFT                        0
-#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK                         0xF0000u
-#define I2S_TFR_WFP_SHIFT                        16
-#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
-#define I2S_TMR_TWM_SHIFT                        0
-#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK                       0x1u
-#define I2S_RCSR_FRDE_SHIFT                      0
-#define I2S_RCSR_FWDE_MASK                       0x2u
-#define I2S_RCSR_FWDE_SHIFT                      1
-#define I2S_RCSR_FRIE_MASK                       0x100u
-#define I2S_RCSR_FRIE_SHIFT                      8
-#define I2S_RCSR_FWIE_MASK                       0x200u
-#define I2S_RCSR_FWIE_SHIFT                      9
-#define I2S_RCSR_FEIE_MASK                       0x400u
-#define I2S_RCSR_FEIE_SHIFT                      10
-#define I2S_RCSR_SEIE_MASK                       0x800u
-#define I2S_RCSR_SEIE_SHIFT                      11
-#define I2S_RCSR_WSIE_MASK                       0x1000u
-#define I2S_RCSR_WSIE_SHIFT                      12
-#define I2S_RCSR_FRF_MASK                        0x10000u
-#define I2S_RCSR_FRF_SHIFT                       16
-#define I2S_RCSR_FWF_MASK                        0x20000u
-#define I2S_RCSR_FWF_SHIFT                       17
-#define I2S_RCSR_FEF_MASK                        0x40000u
-#define I2S_RCSR_FEF_SHIFT                       18
-#define I2S_RCSR_SEF_MASK                        0x80000u
-#define I2S_RCSR_SEF_SHIFT                       19
-#define I2S_RCSR_WSF_MASK                        0x100000u
-#define I2S_RCSR_WSF_SHIFT                       20
-#define I2S_RCSR_SR_MASK                         0x1000000u
-#define I2S_RCSR_SR_SHIFT                        24
-#define I2S_RCSR_FR_MASK                         0x2000000u
-#define I2S_RCSR_FR_SHIFT                        25
-#define I2S_RCSR_BCE_MASK                        0x10000000u
-#define I2S_RCSR_BCE_SHIFT                       28
-#define I2S_RCSR_DBGE_MASK                       0x20000000u
-#define I2S_RCSR_DBGE_SHIFT                      29
-#define I2S_RCSR_STOPE_MASK                      0x40000000u
-#define I2S_RCSR_STOPE_SHIFT                     30
-#define I2S_RCSR_RE_MASK                         0x80000000u
-#define I2S_RCSR_RE_SHIFT                        31
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK                        0x7u
-#define I2S_RCR1_RFW_SHIFT                       0
-#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK                        0xFFu
-#define I2S_RCR2_DIV_SHIFT                       0
-#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK                        0x1000000u
-#define I2S_RCR2_BCD_SHIFT                       24
-#define I2S_RCR2_BCP_MASK                        0x2000000u
-#define I2S_RCR2_BCP_SHIFT                       25
-#define I2S_RCR2_MSEL_MASK                       0xC000000u
-#define I2S_RCR2_MSEL_SHIFT                      26
-#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK                        0x10000000u
-#define I2S_RCR2_BCI_SHIFT                       28
-#define I2S_RCR2_BCS_MASK                        0x20000000u
-#define I2S_RCR2_BCS_SHIFT                       29
-#define I2S_RCR2_SYNC_MASK                       0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT                      30
-#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK                       0x1Fu
-#define I2S_RCR3_WDFL_SHIFT                      0
-#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK                        0x30000u
-#define I2S_RCR3_RCE_SHIFT                       16
-#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK                        0x1u
-#define I2S_RCR4_FSD_SHIFT                       0
-#define I2S_RCR4_FSP_MASK                        0x2u
-#define I2S_RCR4_FSP_SHIFT                       1
-#define I2S_RCR4_FSE_MASK                        0x8u
-#define I2S_RCR4_FSE_SHIFT                       3
-#define I2S_RCR4_MF_MASK                         0x10u
-#define I2S_RCR4_MF_SHIFT                        4
-#define I2S_RCR4_SYWD_MASK                       0x1F00u
-#define I2S_RCR4_SYWD_SHIFT                      8
-#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
-#define I2S_RCR4_FRSZ_SHIFT                      16
-#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK                        0x1F00u
-#define I2S_RCR5_FBT_SHIFT                       8
-#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK                        0x1F0000u
-#define I2S_RCR5_W0W_SHIFT                       16
-#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK                        0x1F000000u
-#define I2S_RCR5_WNW_SHIFT                       24
-#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT                        0
-#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK                         0xFu
-#define I2S_RFR_RFP_SHIFT                        0
-#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK                         0xF0000u
-#define I2S_RFR_WFP_SHIFT                        16
-#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
-#define I2S_RMR_RWM_SHIFT                        0
-#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK                        0x3000000u
-#define I2S_MCR_MICS_SHIFT                       24
-#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK                         0x40000000u
-#define I2S_MCR_MOE_SHIFT                        30
-#define I2S_MCR_DUF_MASK                         0x80000000u
-#define I2S_MCR_DUF_SHIFT                        31
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK                      0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT                     0
-#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK                       0xFF000u
-#define I2S_MDR_FRACT_SHIFT                      12
-#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FRDE_MASK                       (0x1U)
+#define I2S_TCSR_FRDE_SHIFT                      (0U)
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       (0x2U)
+#define I2S_TCSR_FWDE_SHIFT                      (1U)
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       (0x100U)
+#define I2S_TCSR_FRIE_SHIFT                      (8U)
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       (0x200U)
+#define I2S_TCSR_FWIE_SHIFT                      (9U)
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       (0x400U)
+#define I2S_TCSR_FEIE_SHIFT                      (10U)
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       (0x800U)
+#define I2S_TCSR_SEIE_SHIFT                      (11U)
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT                      (12U)
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        (0x10000U)
+#define I2S_TCSR_FRF_SHIFT                       (16U)
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        (0x20000U)
+#define I2S_TCSR_FWF_SHIFT                       (17U)
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        (0x40000U)
+#define I2S_TCSR_FEF_SHIFT                       (18U)
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        (0x80000U)
+#define I2S_TCSR_SEF_SHIFT                       (19U)
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        (0x100000U)
+#define I2S_TCSR_WSF_SHIFT                       (20U)
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         (0x1000000U)
+#define I2S_TCSR_SR_SHIFT                        (24U)
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         (0x2000000U)
+#define I2S_TCSR_FR_SHIFT                        (25U)
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT                       (28U)
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT                      (29U)
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT                     (30U)
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         (0x80000000U)
+#define I2S_TCSR_TE_SHIFT                        (31U)
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+#define I2S_TCR1_TFW_MASK                        (0x7U)
+#define I2S_TCR1_TFW_SHIFT                       (0U)
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK                        (0xFFU)
+#define I2S_TCR2_DIV_SHIFT                       (0U)
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT                       (24U)
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT                       (25U)
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT                      (26U)
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT                       (28U)
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT                       (29U)
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT                      (30U)
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK                       (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT                      (0U)
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        (0x30000U)
+#define I2S_TCR3_TCE_SHIFT                       (16U)
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK                        (0x1U)
+#define I2S_TCR4_FSD_SHIFT                       (0U)
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        (0x2U)
+#define I2S_TCR4_FSP_SHIFT                       (1U)
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK                        (0x8U)
+#define I2S_TCR4_FSE_SHIFT                       (3U)
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         (0x10U)
+#define I2S_TCR4_MF_SHIFT                        (4U)
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT                      (8U)
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT                      (16U)
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK                        (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT                       (8U)
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT                       (16U)
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT                       (24U)
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT                        (0U)
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT                            (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+#define I2S_TFR_RFP_MASK                         (0xFU)
+#define I2S_TFR_RFP_SHIFT                        (0U)
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         (0xF0000U)
+#define I2S_TFR_WFP_SHIFT                        (16U)
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT                            (2U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
+#define I2S_TMR_TWM_SHIFT                        (0U)
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FRDE_MASK                       (0x1U)
+#define I2S_RCSR_FRDE_SHIFT                      (0U)
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       (0x2U)
+#define I2S_RCSR_FWDE_SHIFT                      (1U)
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       (0x100U)
+#define I2S_RCSR_FRIE_SHIFT                      (8U)
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       (0x200U)
+#define I2S_RCSR_FWIE_SHIFT                      (9U)
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       (0x400U)
+#define I2S_RCSR_FEIE_SHIFT                      (10U)
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       (0x800U)
+#define I2S_RCSR_SEIE_SHIFT                      (11U)
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT                      (12U)
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        (0x10000U)
+#define I2S_RCSR_FRF_SHIFT                       (16U)
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        (0x20000U)
+#define I2S_RCSR_FWF_SHIFT                       (17U)
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        (0x40000U)
+#define I2S_RCSR_FEF_SHIFT                       (18U)
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        (0x80000U)
+#define I2S_RCSR_SEF_SHIFT                       (19U)
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        (0x100000U)
+#define I2S_RCSR_WSF_SHIFT                       (20U)
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         (0x1000000U)
+#define I2S_RCSR_SR_SHIFT                        (24U)
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         (0x2000000U)
+#define I2S_RCSR_FR_SHIFT                        (25U)
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT                       (28U)
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT                      (29U)
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT                     (30U)
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         (0x80000000U)
+#define I2S_RCSR_RE_SHIFT                        (31U)
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+#define I2S_RCR1_RFW_MASK                        (0x7U)
+#define I2S_RCR1_RFW_SHIFT                       (0U)
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK                        (0xFFU)
+#define I2S_RCR2_DIV_SHIFT                       (0U)
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT                       (24U)
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT                       (25U)
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT                      (26U)
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT                       (28U)
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT                       (29U)
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT                      (30U)
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK                       (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT                      (0U)
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        (0x30000U)
+#define I2S_RCR3_RCE_SHIFT                       (16U)
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK                        (0x1U)
+#define I2S_RCR4_FSD_SHIFT                       (0U)
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        (0x2U)
+#define I2S_RCR4_FSP_SHIFT                       (1U)
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK                        (0x8U)
+#define I2S_RCR4_FSE_SHIFT                       (3U)
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         (0x10U)
+#define I2S_RCR4_MF_SHIFT                        (4U)
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT                      (8U)
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT                      (16U)
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK                        (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT                       (8U)
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT                       (16U)
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT                       (24U)
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT                        (0U)
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT                            (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+#define I2S_RFR_RFP_MASK                         (0xFU)
+#define I2S_RFR_RFP_SHIFT                        (0U)
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         (0xF0000U)
+#define I2S_RFR_WFP_SHIFT                        (16U)
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT                            (2U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
+#define I2S_RMR_RWM_SHIFT                        (0U)
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK                        (0x3000000U)
+#define I2S_MCR_MICS_SHIFT                       (24U)
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         (0x40000000U)
+#define I2S_MCR_MOE_SHIFT                        (30U)
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         (0x80000000U)
+#define I2S_MCR_DUF_SHIFT                        (31U)
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK                      (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT                     (0U)
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT                      (12U)
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
 
 /*!
  * @}
@@ -8168,7 +7506,6 @@ typedef struct {
 #define I2S0_BASE                                (0x4002F000u)
 /** Peripheral I2S0 base pointer */
 #define I2S0                                     ((I2S_Type *)I2S0_BASE)
-#define I2S0_BASE_PTR                            (I2S0)
 /** Array initializer of I2S peripheral base addresses */
 #define I2S_BASE_ADDRS                           { I2S0_BASE }
 /** Array initializer of I2S peripheral base pointers */
@@ -8177,54 +7514,6 @@ typedef struct {
 #define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
 #define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- I2S - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register instance definitions */
-/* I2S0 */
-#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
-#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
-#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
-#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
-#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
-#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
-#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
-#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
-#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
-#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
-#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
-#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
-#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
-#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
-#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
-#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
-#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
-#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
-#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
-#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
-#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
-#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
-#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
-#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
-
-/* I2S - Register array accessors */
-#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
-#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
-#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
-#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group I2S_Peripheral_Access_Layer */
@@ -8252,35 +7541,7 @@ typedef struct {
   __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
   __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
   __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
-} LLWU_Type, *LLWU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- LLWU - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register accessors */
-#define LLWU_PE1_REG(base)                       ((base)->PE1)
-#define LLWU_PE2_REG(base)                       ((base)->PE2)
-#define LLWU_PE3_REG(base)                       ((base)->PE3)
-#define LLWU_PE4_REG(base)                       ((base)->PE4)
-#define LLWU_ME_REG(base)                        ((base)->ME)
-#define LLWU_F1_REG(base)                        ((base)->F1)
-#define LLWU_F2_REG(base)                        ((base)->F2)
-#define LLWU_F3_REG(base)                        ((base)->F3)
-#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
-#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
-#define LLWU_RST_REG(base)                       ((base)->RST)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
+} LLWU_Type;
 
 /* ----------------------------------------------------------------------------
    -- LLWU Register Masks
@@ -8291,149 +7552,196 @@ typedef struct {
  * @{
  */
 
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK                      0x3u
-#define LLWU_PE1_WUPE0_SHIFT                     0
-#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK                      0xCu
-#define LLWU_PE1_WUPE1_SHIFT                     2
-#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK                      0x30u
-#define LLWU_PE1_WUPE2_SHIFT                     4
-#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK                      0xC0u
-#define LLWU_PE1_WUPE3_SHIFT                     6
-#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK                      0x3u
-#define LLWU_PE2_WUPE4_SHIFT                     0
-#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK                      0xCu
-#define LLWU_PE2_WUPE5_SHIFT                     2
-#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK                      0x30u
-#define LLWU_PE2_WUPE6_SHIFT                     4
-#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK                      0xC0u
-#define LLWU_PE2_WUPE7_SHIFT                     6
-#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK                      0x3u
-#define LLWU_PE3_WUPE8_SHIFT                     0
-#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK                      0xCu
-#define LLWU_PE3_WUPE9_SHIFT                     2
-#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK                     0x30u
-#define LLWU_PE3_WUPE10_SHIFT                    4
-#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK                     0xC0u
-#define LLWU_PE3_WUPE11_SHIFT                    6
-#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK                     0x3u
-#define LLWU_PE4_WUPE12_SHIFT                    0
-#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK                     0xCu
-#define LLWU_PE4_WUPE13_SHIFT                    2
-#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK                     0x30u
-#define LLWU_PE4_WUPE14_SHIFT                    4
-#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK                     0xC0u
-#define LLWU_PE4_WUPE15_SHIFT                    6
-#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK                       0x1u
-#define LLWU_ME_WUME0_SHIFT                      0
-#define LLWU_ME_WUME1_MASK                       0x2u
-#define LLWU_ME_WUME1_SHIFT                      1
-#define LLWU_ME_WUME2_MASK                       0x4u
-#define LLWU_ME_WUME2_SHIFT                      2
-#define LLWU_ME_WUME3_MASK                       0x8u
-#define LLWU_ME_WUME3_SHIFT                      3
-#define LLWU_ME_WUME4_MASK                       0x10u
-#define LLWU_ME_WUME4_SHIFT                      4
-#define LLWU_ME_WUME5_MASK                       0x20u
-#define LLWU_ME_WUME5_SHIFT                      5
-#define LLWU_ME_WUME6_MASK                       0x40u
-#define LLWU_ME_WUME6_SHIFT                      6
-#define LLWU_ME_WUME7_MASK                       0x80u
-#define LLWU_ME_WUME7_SHIFT                      7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK                        0x1u
-#define LLWU_F1_WUF0_SHIFT                       0
-#define LLWU_F1_WUF1_MASK                        0x2u
-#define LLWU_F1_WUF1_SHIFT                       1
-#define LLWU_F1_WUF2_MASK                        0x4u
-#define LLWU_F1_WUF2_SHIFT                       2
-#define LLWU_F1_WUF3_MASK                        0x8u
-#define LLWU_F1_WUF3_SHIFT                       3
-#define LLWU_F1_WUF4_MASK                        0x10u
-#define LLWU_F1_WUF4_SHIFT                       4
-#define LLWU_F1_WUF5_MASK                        0x20u
-#define LLWU_F1_WUF5_SHIFT                       5
-#define LLWU_F1_WUF6_MASK                        0x40u
-#define LLWU_F1_WUF6_SHIFT                       6
-#define LLWU_F1_WUF7_MASK                        0x80u
-#define LLWU_F1_WUF7_SHIFT                       7
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK                        0x1u
-#define LLWU_F2_WUF8_SHIFT                       0
-#define LLWU_F2_WUF9_MASK                        0x2u
-#define LLWU_F2_WUF9_SHIFT                       1
-#define LLWU_F2_WUF10_MASK                       0x4u
-#define LLWU_F2_WUF10_SHIFT                      2
-#define LLWU_F2_WUF11_MASK                       0x8u
-#define LLWU_F2_WUF11_SHIFT                      3
-#define LLWU_F2_WUF12_MASK                       0x10u
-#define LLWU_F2_WUF12_SHIFT                      4
-#define LLWU_F2_WUF13_MASK                       0x20u
-#define LLWU_F2_WUF13_SHIFT                      5
-#define LLWU_F2_WUF14_MASK                       0x40u
-#define LLWU_F2_WUF14_SHIFT                      6
-#define LLWU_F2_WUF15_MASK                       0x80u
-#define LLWU_F2_WUF15_SHIFT                      7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK                       0x1u
-#define LLWU_F3_MWUF0_SHIFT                      0
-#define LLWU_F3_MWUF1_MASK                       0x2u
-#define LLWU_F3_MWUF1_SHIFT                      1
-#define LLWU_F3_MWUF2_MASK                       0x4u
-#define LLWU_F3_MWUF2_SHIFT                      2
-#define LLWU_F3_MWUF3_MASK                       0x8u
-#define LLWU_F3_MWUF3_SHIFT                      3
-#define LLWU_F3_MWUF4_MASK                       0x10u
-#define LLWU_F3_MWUF4_SHIFT                      4
-#define LLWU_F3_MWUF5_MASK                       0x20u
-#define LLWU_F3_MWUF5_SHIFT                      5
-#define LLWU_F3_MWUF6_MASK                       0x40u
-#define LLWU_F3_MWUF6_SHIFT                      6
-#define LLWU_F3_MWUF7_MASK                       0x80u
-#define LLWU_F3_MWUF7_SHIFT                      7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK                  0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT                 0
-#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK                    0x60u
-#define LLWU_FILT1_FILTE_SHIFT                   5
-#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK                    0x80u
-#define LLWU_FILT1_FILTF_SHIFT                   7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK                  0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT                 0
-#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK                    0x60u
-#define LLWU_FILT2_FILTE_SHIFT                   5
-#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK                    0x80u
-#define LLWU_FILT2_FILTF_SHIFT                   7
-/* RST Bit Fields */
-#define LLWU_RST_RSTFILT_MASK                    0x1u
-#define LLWU_RST_RSTFILT_SHIFT                   0
-#define LLWU_RST_LLRSTE_MASK                     0x2u
-#define LLWU_RST_LLRSTE_SHIFT                    1
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK                      (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT                     (0U)
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT                     (2U)
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT                     (4U)
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT                     (6U)
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK                      (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT                     (0U)
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT                     (2U)
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT                     (4U)
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT                     (6U)
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK                      (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT                     (0U)
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT                     (2U)
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT                    (4U)
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT                    (6U)
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK                     (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT                    (0U)
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT                    (2U)
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT                    (4U)
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT                    (6U)
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK                       (0x1U)
+#define LLWU_ME_WUME0_SHIFT                      (0U)
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       (0x2U)
+#define LLWU_ME_WUME1_SHIFT                      (1U)
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       (0x4U)
+#define LLWU_ME_WUME2_SHIFT                      (2U)
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       (0x8U)
+#define LLWU_ME_WUME3_SHIFT                      (3U)
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       (0x10U)
+#define LLWU_ME_WUME4_SHIFT                      (4U)
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       (0x20U)
+#define LLWU_ME_WUME5_SHIFT                      (5U)
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       (0x40U)
+#define LLWU_ME_WUME6_SHIFT                      (6U)
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       (0x80U)
+#define LLWU_ME_WUME7_SHIFT                      (7U)
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name F1 - LLWU Flag 1 register */
+#define LLWU_F1_WUF0_MASK                        (0x1U)
+#define LLWU_F1_WUF0_SHIFT                       (0U)
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        (0x2U)
+#define LLWU_F1_WUF1_SHIFT                       (1U)
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        (0x4U)
+#define LLWU_F1_WUF2_SHIFT                       (2U)
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        (0x8U)
+#define LLWU_F1_WUF3_SHIFT                       (3U)
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        (0x10U)
+#define LLWU_F1_WUF4_SHIFT                       (4U)
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        (0x20U)
+#define LLWU_F1_WUF5_SHIFT                       (5U)
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        (0x40U)
+#define LLWU_F1_WUF6_SHIFT                       (6U)
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        (0x80U)
+#define LLWU_F1_WUF7_SHIFT                       (7U)
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+
+/*! @name F2 - LLWU Flag 2 register */
+#define LLWU_F2_WUF8_MASK                        (0x1U)
+#define LLWU_F2_WUF8_SHIFT                       (0U)
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        (0x2U)
+#define LLWU_F2_WUF9_SHIFT                       (1U)
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       (0x4U)
+#define LLWU_F2_WUF10_SHIFT                      (2U)
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       (0x8U)
+#define LLWU_F2_WUF11_SHIFT                      (3U)
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       (0x10U)
+#define LLWU_F2_WUF12_SHIFT                      (4U)
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       (0x20U)
+#define LLWU_F2_WUF13_SHIFT                      (5U)
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       (0x40U)
+#define LLWU_F2_WUF14_SHIFT                      (6U)
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       (0x80U)
+#define LLWU_F2_WUF15_SHIFT                      (7U)
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+
+/*! @name F3 - LLWU Flag 3 register */
+#define LLWU_F3_MWUF0_MASK                       (0x1U)
+#define LLWU_F3_MWUF0_SHIFT                      (0U)
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       (0x2U)
+#define LLWU_F3_MWUF1_SHIFT                      (1U)
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       (0x4U)
+#define LLWU_F3_MWUF2_SHIFT                      (2U)
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       (0x8U)
+#define LLWU_F3_MWUF3_SHIFT                      (3U)
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       (0x10U)
+#define LLWU_F3_MWUF4_SHIFT                      (4U)
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       (0x20U)
+#define LLWU_F3_MWUF5_SHIFT                      (5U)
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       (0x40U)
+#define LLWU_F3_MWUF6_SHIFT                      (6U)
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       (0x80U)
+#define LLWU_F3_MWUF7_SHIFT                      (7U)
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK                  (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT                   (5U)
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT                   (7U)
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK                  (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT                   (5U)
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT                   (7U)
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
+/*! @name RST - LLWU Reset Enable register */
+#define LLWU_RST_RSTFILT_MASK                    (0x1U)
+#define LLWU_RST_RSTFILT_SHIFT                   (0U)
+#define LLWU_RST_RSTFILT(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK                     (0x2U)
+#define LLWU_RST_LLRSTE_SHIFT                    (1U)
+#define LLWU_RST_LLRSTE(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
+
 
 /*!
  * @}
@@ -8445,42 +7753,12 @@ typedef struct {
 #define LLWU_BASE                                (0x4007C000u)
 /** Peripheral LLWU base pointer */
 #define LLWU                                     ((LLWU_Type *)LLWU_BASE)
-#define LLWU_BASE_PTR                            (LLWU)
 /** Array initializer of LLWU peripheral base addresses */
 #define LLWU_BASE_ADDRS                          { LLWU_BASE }
 /** Array initializer of LLWU peripheral base pointers */
 #define LLWU_BASE_PTRS                           { LLWU }
 /** Interrupt vectors for the LLWU peripheral type */
-#define LLWU_IRQS                                { LLW_IRQn }
-
-/* ----------------------------------------------------------------------------
-   -- LLWU - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register instance definitions */
-/* LLWU */
-#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
-#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
-#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
-#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
-#define LLWU_ME                                  LLWU_ME_REG(LLWU)
-#define LLWU_F1                                  LLWU_F1_REG(LLWU)
-#define LLWU_F2                                  LLWU_F2_REG(LLWU)
-#define LLWU_F3                                  LLWU_F3_REG(LLWU)
-#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
-#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
-#define LLWU_RST                                 LLWU_RST_REG(LLWU)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
+#define LLWU_IRQS                                { LLWU_IRQn }
 
 /*!
  * @}
@@ -8502,28 +7780,7 @@ typedef struct {
   __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
   __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
   __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type, *LPTMR_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- LPTMR - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register accessors */
-#define LPTMR_CSR_REG(base)                      ((base)->CSR)
-#define LPTMR_PSR_REG(base)                      ((base)->PSR)
-#define LPTMR_CMR_REG(base)                      ((base)->CMR)
-#define LPTMR_CNR_REG(base)                      ((base)->CNR)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
+} LPTMR_Type;
 
 /* ----------------------------------------------------------------------------
    -- LPTMR Register Masks
@@ -8534,39 +7791,50 @@ typedef struct {
  * @{
  */
 
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK                       0x1u
-#define LPTMR_CSR_TEN_SHIFT                      0
-#define LPTMR_CSR_TMS_MASK                       0x2u
-#define LPTMR_CSR_TMS_SHIFT                      1
-#define LPTMR_CSR_TFC_MASK                       0x4u
-#define LPTMR_CSR_TFC_SHIFT                      2
-#define LPTMR_CSR_TPP_MASK                       0x8u
-#define LPTMR_CSR_TPP_SHIFT                      3
-#define LPTMR_CSR_TPS_MASK                       0x30u
-#define LPTMR_CSR_TPS_SHIFT                      4
-#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK                       0x40u
-#define LPTMR_CSR_TIE_SHIFT                      6
-#define LPTMR_CSR_TCF_MASK                       0x80u
-#define LPTMR_CSR_TCF_SHIFT                      7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK                       0x3u
-#define LPTMR_PSR_PCS_SHIFT                      0
-#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK                      0x4u
-#define LPTMR_PSR_PBYP_SHIFT                     2
-#define LPTMR_PSR_PRESCALE_MASK                  0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT                 3
-#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT                  0
-#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT                  0
-#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK                       (0x1U)
+#define LPTMR_CSR_TEN_SHIFT                      (0U)
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       (0x2U)
+#define LPTMR_CSR_TMS_SHIFT                      (1U)
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       (0x4U)
+#define LPTMR_CSR_TFC_SHIFT                      (2U)
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       (0x8U)
+#define LPTMR_CSR_TPP_SHIFT                      (3U)
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       (0x40U)
+#define LPTMR_CSR_TIE_SHIFT                      (6U)
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       (0x80U)
+#define LPTMR_CSR_TCF_SHIFT                      (7U)
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT                     (2U)
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
 
 /*!
  * @}
@@ -8578,7 +7846,6 @@ typedef struct {
 #define LPTMR0_BASE                              (0x40040000u)
 /** Peripheral LPTMR0 base pointer */
 #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
-#define LPTMR0_BASE_PTR                          (LPTMR0)
 /** Array initializer of LPTMR peripheral base addresses */
 #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
 /** Array initializer of LPTMR peripheral base pointers */
@@ -8586,28 +7853,6 @@ typedef struct {
 /** Interrupt vectors for the LPTMR peripheral type */
 #define LPTMR_IRQS                               { LPTMR0_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- LPTMR - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register instance definitions */
-/* LPTMR0 */
-#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
-#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
-#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
-#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group LPTMR_Peripheral_Access_Layer */
@@ -8640,38 +7885,7 @@ typedef struct {
   __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
   __I  uint8_t C9;                                 /**< MCG Control 9 Register, offset: 0xE */
   __I  uint8_t C10;                                /**< MCG Control 10 Register, offset: 0xF */
-} MCG_Type, *MCG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- MCG - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register accessors */
-#define MCG_C1_REG(base)                         ((base)->C1)
-#define MCG_C2_REG(base)                         ((base)->C2)
-#define MCG_C3_REG(base)                         ((base)->C3)
-#define MCG_C4_REG(base)                         ((base)->C4)
-#define MCG_C5_REG(base)                         ((base)->C5)
-#define MCG_C6_REG(base)                         ((base)->C6)
-#define MCG_S_REG(base)                          ((base)->S)
-#define MCG_SC_REG(base)                         ((base)->SC)
-#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
-#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
-#define MCG_C7_REG(base)                         ((base)->C7)
-#define MCG_C8_REG(base)                         ((base)->C8)
-#define MCG_C9_REG(base)                         ((base)->C9)
-#define MCG_C10_REG(base)                        ((base)->C10)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
+} MCG_Type;
 
 /* ----------------------------------------------------------------------------
    -- MCG Register Masks
@@ -8682,116 +7896,159 @@ typedef struct {
  * @{
  */
 
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK                     0x1u
-#define MCG_C1_IREFSTEN_SHIFT                    0
-#define MCG_C1_IRCLKEN_MASK                      0x2u
-#define MCG_C1_IRCLKEN_SHIFT                     1
-#define MCG_C1_IREFS_MASK                        0x4u
-#define MCG_C1_IREFS_SHIFT                       2
-#define MCG_C1_FRDIV_MASK                        0x38u
-#define MCG_C1_FRDIV_SHIFT                       3
-#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK                         0xC0u
-#define MCG_C1_CLKS_SHIFT                        6
-#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK                         0x1u
-#define MCG_C2_IRCS_SHIFT                        0
-#define MCG_C2_LP_MASK                           0x2u
-#define MCG_C2_LP_SHIFT                          1
-#define MCG_C2_EREFS0_MASK                       0x4u
-#define MCG_C2_EREFS0_SHIFT                      2
-#define MCG_C2_HGO0_MASK                         0x8u
-#define MCG_C2_HGO0_SHIFT                        3
-#define MCG_C2_RANGE0_MASK                       0x30u
-#define MCG_C2_RANGE0_SHIFT                      4
-#define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
-#define MCG_C2_LOCRE0_MASK                       0x80u
-#define MCG_C2_LOCRE0_SHIFT                      7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK                       0xFFu
-#define MCG_C3_SCTRIM_SHIFT                      0
-#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK                      0x1u
-#define MCG_C4_SCFTRIM_SHIFT                     0
-#define MCG_C4_FCTRIM_MASK                       0x1Eu
-#define MCG_C4_FCTRIM_SHIFT                      1
-#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK                     0x60u
-#define MCG_C4_DRST_DRS_SHIFT                    5
-#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK                        0x80u
-#define MCG_C4_DMX32_SHIFT                       7
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK                       0x1Fu
-#define MCG_C5_PRDIV0_SHIFT                      0
-#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK                     0x20u
-#define MCG_C5_PLLSTEN0_SHIFT                    5
-#define MCG_C5_PLLCLKEN0_MASK                    0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT                   6
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK                        0x1Fu
-#define MCG_C6_VDIV0_SHIFT                       0
-#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK                         0x20u
-#define MCG_C6_CME0_SHIFT                        5
-#define MCG_C6_PLLS_MASK                         0x40u
-#define MCG_C6_PLLS_SHIFT                        6
-#define MCG_C6_LOLIE0_MASK                       0x80u
-#define MCG_C6_LOLIE0_SHIFT                      7
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK                         0x1u
-#define MCG_S_IRCST_SHIFT                        0
-#define MCG_S_OSCINIT0_MASK                      0x2u
-#define MCG_S_OSCINIT0_SHIFT                     1
-#define MCG_S_CLKST_MASK                         0xCu
-#define MCG_S_CLKST_SHIFT                        2
-#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK                        0x10u
-#define MCG_S_IREFST_SHIFT                       4
-#define MCG_S_PLLST_MASK                         0x20u
-#define MCG_S_PLLST_SHIFT                        5
-#define MCG_S_LOCK0_MASK                         0x40u
-#define MCG_S_LOCK0_SHIFT                        6
-#define MCG_S_LOLS_MASK                          0x80u
-#define MCG_S_LOLS_SHIFT                         7
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK                        0x1u
-#define MCG_SC_LOCS0_SHIFT                       0
-#define MCG_SC_FCRDIV_MASK                       0xEu
-#define MCG_SC_FCRDIV_SHIFT                      1
-#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK                     0x10u
-#define MCG_SC_FLTPRSRV_SHIFT                    4
-#define MCG_SC_ATMF_MASK                         0x20u
-#define MCG_SC_ATMF_SHIFT                        5
-#define MCG_SC_ATMS_MASK                         0x40u
-#define MCG_SC_ATMS_SHIFT                        6
-#define MCG_SC_ATME_MASK                         0x80u
-#define MCG_SC_ATME_SHIFT                        7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK                     0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT                    0
-#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK                     0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT                    0
-#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK                       0x1u
-#define MCG_C7_OSCSEL_SHIFT                      0
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK                        0x1u
-#define MCG_C8_LOCS1_SHIFT                       0
-#define MCG_C8_CME1_MASK                         0x20u
-#define MCG_C8_CME1_SHIFT                        5
-#define MCG_C8_LOLRE_MASK                        0x40u
-#define MCG_C8_LOLRE_SHIFT                       6
-#define MCG_C8_LOCRE1_MASK                       0x80u
-#define MCG_C8_LOCRE1_SHIFT                      7
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK                     (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT                    (0U)
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT                     (1U)
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        (0x4U)
+#define MCG_C1_IREFS_SHIFT                       (2U)
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        (0x38U)
+#define MCG_C1_FRDIV_SHIFT                       (3U)
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         (0xC0U)
+#define MCG_C1_CLKS_SHIFT                        (6U)
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK                         (0x1U)
+#define MCG_C2_IRCS_SHIFT                        (0U)
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           (0x2U)
+#define MCG_C2_LP_SHIFT                          (1U)
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS0_MASK                       (0x4U)
+#define MCG_C2_EREFS0_SHIFT                      (2U)
+#define MCG_C2_EREFS0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
+#define MCG_C2_HGO0_MASK                         (0x8U)
+#define MCG_C2_HGO0_SHIFT                        (3U)
+#define MCG_C2_HGO0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
+#define MCG_C2_RANGE0_MASK                       (0x30U)
+#define MCG_C2_RANGE0_SHIFT                      (4U)
+#define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK                       (0x80U)
+#define MCG_C2_LOCRE0_SHIFT                      (7U)
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK                       (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT                      (0U)
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK                      (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT                     (0U)
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT                      (1U)
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT                    (5U)
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        (0x80U)
+#define MCG_C4_DMX32_SHIFT                       (7U)
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV0_MASK                       (0x1FU)
+#define MCG_C5_PRDIV0_SHIFT                      (0U)
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     (0x20U)
+#define MCG_C5_PLLSTEN0_SHIFT                    (5U)
+#define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK                    (0x40U)
+#define MCG_C5_PLLCLKEN0_SHIFT                   (6U)
+#define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV0_MASK                        (0x1FU)
+#define MCG_C6_VDIV0_SHIFT                       (0U)
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         (0x20U)
+#define MCG_C6_CME0_SHIFT                        (5U)
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         (0x40U)
+#define MCG_C6_PLLS_SHIFT                        (6U)
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       (0x80U)
+#define MCG_C6_LOLIE0_SHIFT                      (7U)
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK                         (0x1U)
+#define MCG_S_IRCST_SHIFT                        (0U)
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      (0x2U)
+#define MCG_S_OSCINIT0_SHIFT                     (1U)
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         (0xCU)
+#define MCG_S_CLKST_SHIFT                        (2U)
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        (0x10U)
+#define MCG_S_IREFST_SHIFT                       (4U)
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         (0x20U)
+#define MCG_S_PLLST_SHIFT                        (5U)
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         (0x40U)
+#define MCG_S_LOCK0_SHIFT                        (6U)
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS_MASK                          (0x80U)
+#define MCG_S_LOLS_SHIFT                         (7U)
+#define MCG_S_LOLS(x)                            (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS_SHIFT)) & MCG_S_LOLS_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK                        (0x1U)
+#define MCG_SC_LOCS0_SHIFT                       (0U)
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       (0xEU)
+#define MCG_SC_FCRDIV_SHIFT                      (1U)
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT                    (4U)
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         (0x20U)
+#define MCG_SC_ATMF_SHIFT                        (5U)
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         (0x40U)
+#define MCG_SC_ATMS_SHIFT                        (6U)
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         (0x80U)
+#define MCG_SC_ATME_SHIFT                        (7U)
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK                     (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT                    (0U)
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK                     (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT                    (0U)
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK                       (0x1U)
+#define MCG_C7_OSCSEL_SHIFT                      (0U)
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1_MASK                        (0x1U)
+#define MCG_C8_LOCS1_SHIFT                       (0U)
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         (0x20U)
+#define MCG_C8_CME1_SHIFT                        (5U)
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        (0x40U)
+#define MCG_C8_LOLRE_SHIFT                       (6U)
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       (0x80U)
+#define MCG_C8_LOCRE1_SHIFT                      (7U)
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+
 
 /*!
  * @}
@@ -8803,42 +8060,35 @@ typedef struct {
 #define MCG_BASE                                 (0x40064000u)
 /** Peripheral MCG base pointer */
 #define MCG                                      ((MCG_Type *)MCG_BASE)
-#define MCG_BASE_PTR                             (MCG)
 /** Array initializer of MCG peripheral base addresses */
 #define MCG_BASE_ADDRS                           { MCG_BASE }
 /** Array initializer of MCG peripheral base pointers */
 #define MCG_BASE_PTRS                            { MCG }
+/** Interrupt vectors for the MCG peripheral type */
+#define MCG_IRQS                                 { MCG_IRQn }
+/* MCG C2[EREFS] backward compatibility */
+#define MCG_C2_EREFS_MASK         (MCG_C2_EREFS0_MASK)
+#define MCG_C2_EREFS_SHIFT        (MCG_C2_EREFS0_SHIFT)
+#define MCG_C2_EREFS_WIDTH        (MCG_C2_EREFS0_WIDTH)
+#define MCG_C2_EREFS(x)           (MCG_C2_EREFS0(x))
 
-/* ----------------------------------------------------------------------------
-   -- MCG - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
+/* MCG C2[HGO] backward compatibility */
+#define MCG_C2_HGO_MASK         (MCG_C2_HGO0_MASK)
+#define MCG_C2_HGO_SHIFT        (MCG_C2_HGO0_SHIFT)
+#define MCG_C2_HGO_WIDTH        (MCG_C2_HGO0_WIDTH)
+#define MCG_C2_HGO(x)           (MCG_C2_HGO0(x))
 
-/* MCG - Register instance definitions */
-/* MCG */
-#define MCG_C1                                   MCG_C1_REG(MCG)
-#define MCG_C2                                   MCG_C2_REG(MCG)
-#define MCG_C3                                   MCG_C3_REG(MCG)
-#define MCG_C4                                   MCG_C4_REG(MCG)
-#define MCG_C5                                   MCG_C5_REG(MCG)
-#define MCG_C6                                   MCG_C6_REG(MCG)
-#define MCG_S                                    MCG_S_REG(MCG)
-#define MCG_SC                                   MCG_SC_REG(MCG)
-#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
-#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
-#define MCG_C7                                   MCG_C7_REG(MCG)
-#define MCG_C8                                   MCG_C8_REG(MCG)
-#define MCG_C9                                   MCG_C9_REG(MCG)
-#define MCG_C10                                  MCG_C10_REG(MCG)
+/* MCG C2[RANGE] backward compatibility */
+#define MCG_C2_RANGE_MASK         (MCG_C2_RANGE0_MASK)
+#define MCG_C2_RANGE_SHIFT        (MCG_C2_RANGE0_SHIFT)
+#define MCG_C2_RANGE_WIDTH        (MCG_C2_RANGE0_WIDTH)
+#define MCG_C2_RANGE(x)           (MCG_C2_RANGE0(x))
 
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
+/* MCG S[LOLS0] backward compatibility */
+#define MCG_S_LOLS0_MASK         (MCG_S_LOLS_MASK)
+#define MCG_S_LOLS0_SHIFT        (MCG_S_LOLS_SHIFT)
+#define MCG_S_LOLS0_WIDTH        (MCG_S_LOLS_WIDTH)
+#define MCG_S_LOLS0(x)           (MCG_S_LOLS(x))
 
 
 /*!
@@ -8867,32 +8117,7 @@ typedef struct {
   __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
        uint8_t RESERVED_1[16];
   __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
-} MCM_Type, *MCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- MCM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register accessors */
-#define MCM_PLASC_REG(base)                      ((base)->PLASC)
-#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
-#define MCM_CR_REG(base)                         ((base)->CR)
-#define MCM_ISR_REG(base)                        ((base)->ISR)
-#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
-#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
-#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
-#define MCM_PID_REG(base)                        ((base)->PID)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
+} MCM_Type;
 
 /* ----------------------------------------------------------------------------
    -- MCM Register Masks
@@ -8903,56 +8128,73 @@ typedef struct {
  * @{
  */
 
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK                       0xFFu
-#define MCM_PLASC_ASC_SHIFT                      0
-#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK                       0xFFu
-#define MCM_PLAMC_AMC_SHIFT                      0
-#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* CR Bit Fields */
-#define MCM_CR_SRAMUAP_MASK                      0x3000000u
-#define MCM_CR_SRAMUAP_SHIFT                     24
-#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
-#define MCM_CR_SRAMUWP_MASK                      0x4000000u
-#define MCM_CR_SRAMUWP_SHIFT                     26
-#define MCM_CR_SRAMLAP_MASK                      0x30000000u
-#define MCM_CR_SRAMLAP_SHIFT                     28
-#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
-#define MCM_CR_SRAMLWP_MASK                      0x40000000u
-#define MCM_CR_SRAMLWP_SHIFT                     30
-/* ISR Bit Fields */
-#define MCM_ISR_IRQ_MASK                         0x2u
-#define MCM_ISR_IRQ_SHIFT                        1
-#define MCM_ISR_NMI_MASK                         0x4u
-#define MCM_ISR_NMI_SHIFT                        2
-#define MCM_ISR_DHREQ_MASK                       0x8u
-#define MCM_ISR_DHREQ_SHIFT                      3
-/* ETBCC Bit Fields */
-#define MCM_ETBCC_CNTEN_MASK                     0x1u
-#define MCM_ETBCC_CNTEN_SHIFT                    0
-#define MCM_ETBCC_RSPT_MASK                      0x6u
-#define MCM_ETBCC_RSPT_SHIFT                     1
-#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
-#define MCM_ETBCC_RLRQ_MASK                      0x8u
-#define MCM_ETBCC_RLRQ_SHIFT                     3
-#define MCM_ETBCC_ETDIS_MASK                     0x10u
-#define MCM_ETBCC_ETDIS_SHIFT                    4
-#define MCM_ETBCC_ITDIS_MASK                     0x20u
-#define MCM_ETBCC_ITDIS_SHIFT                    5
-/* ETBRL Bit Fields */
-#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
-#define MCM_ETBRL_RELOAD_SHIFT                   0
-#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
-/* ETBCNT Bit Fields */
-#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
-#define MCM_ETBCNT_COUNTER_SHIFT                 0
-#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
-/* PID Bit Fields */
-#define MCM_PID_PID_MASK                         0xFFu
-#define MCM_PID_PID_SHIFT                        0
-#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK                       (0xFFU)
+#define MCM_PLASC_ASC_SHIFT                      (0U)
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK                       (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT                      (0U)
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name CR - Control Register */
+#define MCM_CR_SRAMUAP_MASK                      (0x3000000U)
+#define MCM_CR_SRAMUAP_SHIFT                     (24U)
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      (0x4000000U)
+#define MCM_CR_SRAMUWP_SHIFT                     (26U)
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      (0x30000000U)
+#define MCM_CR_SRAMLAP_SHIFT                     (28U)
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      (0x40000000U)
+#define MCM_CR_SRAMLWP_SHIFT                     (30U)
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
+
+/*! @name ISR - Interrupt Status Register */
+#define MCM_ISR_IRQ_MASK                         (0x2U)
+#define MCM_ISR_IRQ_SHIFT                        (1U)
+#define MCM_ISR_IRQ(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_ISR_IRQ_SHIFT)) & MCM_ISR_IRQ_MASK)
+#define MCM_ISR_NMI_MASK                         (0x4U)
+#define MCM_ISR_NMI_SHIFT                        (2U)
+#define MCM_ISR_NMI(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_ISR_NMI_SHIFT)) & MCM_ISR_NMI_MASK)
+#define MCM_ISR_DHREQ_MASK                       (0x8U)
+#define MCM_ISR_DHREQ_SHIFT                      (3U)
+#define MCM_ISR_DHREQ(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISR_DHREQ_SHIFT)) & MCM_ISR_DHREQ_MASK)
+
+/*! @name ETBCC - ETB Counter Control register */
+#define MCM_ETBCC_CNTEN_MASK                     (0x1U)
+#define MCM_ETBCC_CNTEN_SHIFT                    (0U)
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      (0x6U)
+#define MCM_ETBCC_RSPT_SHIFT                     (1U)
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      (0x8U)
+#define MCM_ETBCC_RLRQ_SHIFT                     (3U)
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     (0x10U)
+#define MCM_ETBCC_ETDIS_SHIFT                    (4U)
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     (0x20U)
+#define MCM_ETBCC_ITDIS_SHIFT                    (5U)
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
+
+/*! @name ETBRL - ETB Reload register */
+#define MCM_ETBRL_RELOAD_MASK                    (0x7FFU)
+#define MCM_ETBRL_RELOAD_SHIFT                   (0U)
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
+
+/*! @name ETBCNT - ETB Counter Value register */
+#define MCM_ETBCNT_COUNTER_MASK                  (0x7FFU)
+#define MCM_ETBCNT_COUNTER_SHIFT                 (0U)
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
+
+/*! @name PID - Process ID register */
+#define MCM_PID_PID_MASK                         (0xFFU)
+#define MCM_PID_PID_SHIFT                        (0U)
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
+
 
 /*!
  * @}
@@ -8964,335 +8206,18 @@ typedef struct {
 #define MCM_BASE                                 (0xE0080000u)
 /** Peripheral MCM base pointer */
 #define MCM                                      ((MCM_Type *)MCM_BASE)
-#define MCM_BASE_PTR                             (MCM)
 /** Array initializer of MCM peripheral base addresses */
 #define MCM_BASE_ADDRS                           { MCM_BASE }
 /** Array initializer of MCM peripheral base pointers */
 #define MCM_BASE_PTRS                            { MCM }
-
-/* ----------------------------------------------------------------------------
-   -- MCM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register instance definitions */
-/* MCM */
-#define MCM_PLASC                                MCM_PLASC_REG(MCM)
-#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
-#define MCM_CR                                   MCM_CR_REG(MCM)
-#define MCM_ISR                                  MCM_ISR_REG(MCM)
-#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
-#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
-#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
-#define MCM_PID                                  MCM_PID_REG(MCM)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
 
 /*!
  * @}
  */ /* end of group MCM_Peripheral_Access_Layer */
 
 
-/* ----------------------------------------------------------------------------
-   -- MPU Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
- * @{
- */
-
-/** MPU - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
-       uint8_t RESERVED_0[12];
-  struct {                                         /* offset: 0x10, array step: 0x8 */
-    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
-    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
-  } SP[5];
-       uint8_t RESERVED_1[968];
-  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
-       uint8_t RESERVED_2[832];
-  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
-} MPU_Type, *MPU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- MPU - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
- * @{
- */
-
-
-/* MPU - Register accessors */
-#define MPU_CESR_REG(base)                       ((base)->CESR)
-#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
-#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
-#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
-#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
-
-/*!
- * @}
- */ /* end of group MPU_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
-   -- MPU Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Masks MPU Register Masks
- * @{
- */
-
-/* CESR Bit Fields */
-#define MPU_CESR_VLD_MASK                        0x1u
-#define MPU_CESR_VLD_SHIFT                       0
-#define MPU_CESR_NRGD_MASK                       0xF00u
-#define MPU_CESR_NRGD_SHIFT                      8
-#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
-#define MPU_CESR_NSP_MASK                        0xF000u
-#define MPU_CESR_NSP_SHIFT                       12
-#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
-#define MPU_CESR_HRL_MASK                        0xF0000u
-#define MPU_CESR_HRL_SHIFT                       16
-#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
-#define MPU_CESR_SPERR_MASK                      0xF8000000u
-#define MPU_CESR_SPERR_SHIFT                     27
-#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
-/* EAR Bit Fields */
-#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
-#define MPU_EAR_EADDR_SHIFT                      0
-#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
-/* EDR Bit Fields */
-#define MPU_EDR_ERW_MASK                         0x1u
-#define MPU_EDR_ERW_SHIFT                        0
-#define MPU_EDR_EATTR_MASK                       0xEu
-#define MPU_EDR_EATTR_SHIFT                      1
-#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
-#define MPU_EDR_EMN_MASK                         0xF0u
-#define MPU_EDR_EMN_SHIFT                        4
-#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
-#define MPU_EDR_EACD_MASK                        0xFFFF0000u
-#define MPU_EDR_EACD_SHIFT                       16
-#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
-/* WORD Bit Fields */
-#define MPU_WORD_M0UM_MASK                       0x7u
-#define MPU_WORD_M0UM_SHIFT                      0
-#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
-#define MPU_WORD_VLD_MASK                        0x1u
-#define MPU_WORD_VLD_SHIFT                       0
-#define MPU_WORD_M0SM_MASK                       0x18u
-#define MPU_WORD_M0SM_SHIFT                      3
-#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
-#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
-#define MPU_WORD_ENDADDR_SHIFT                   5
-#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
-#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
-#define MPU_WORD_SRTADDR_SHIFT                   5
-#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
-#define MPU_WORD_M1UM_MASK                       0x1C0u
-#define MPU_WORD_M1UM_SHIFT                      6
-#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
-#define MPU_WORD_M1SM_MASK                       0x600u
-#define MPU_WORD_M1SM_SHIFT                      9
-#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
-#define MPU_WORD_M2UM_MASK                       0x7000u
-#define MPU_WORD_M2UM_SHIFT                      12
-#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
-#define MPU_WORD_M2SM_MASK                       0x18000u
-#define MPU_WORD_M2SM_SHIFT                      15
-#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
-#define MPU_WORD_M3UM_MASK                       0x1C0000u
-#define MPU_WORD_M3UM_SHIFT                      18
-#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
-#define MPU_WORD_M3SM_MASK                       0x600000u
-#define MPU_WORD_M3SM_SHIFT                      21
-#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
-#define MPU_WORD_M4WE_MASK                       0x1000000u
-#define MPU_WORD_M4WE_SHIFT                      24
-#define MPU_WORD_M4RE_MASK                       0x2000000u
-#define MPU_WORD_M4RE_SHIFT                      25
-#define MPU_WORD_M5WE_MASK                       0x4000000u
-#define MPU_WORD_M5WE_SHIFT                      26
-#define MPU_WORD_M5RE_MASK                       0x8000000u
-#define MPU_WORD_M5RE_SHIFT                      27
-#define MPU_WORD_M6WE_MASK                       0x10000000u
-#define MPU_WORD_M6WE_SHIFT                      28
-#define MPU_WORD_M6RE_MASK                       0x20000000u
-#define MPU_WORD_M6RE_SHIFT                      29
-#define MPU_WORD_M7WE_MASK                       0x40000000u
-#define MPU_WORD_M7WE_SHIFT                      30
-#define MPU_WORD_M7RE_MASK                       0x80000000u
-#define MPU_WORD_M7RE_SHIFT                      31
-/* RGDAAC Bit Fields */
-#define MPU_RGDAAC_M0UM_MASK                     0x7u
-#define MPU_RGDAAC_M0UM_SHIFT                    0
-#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
-#define MPU_RGDAAC_M0SM_MASK                     0x18u
-#define MPU_RGDAAC_M0SM_SHIFT                    3
-#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
-#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
-#define MPU_RGDAAC_M1UM_SHIFT                    6
-#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
-#define MPU_RGDAAC_M1SM_MASK                     0x600u
-#define MPU_RGDAAC_M1SM_SHIFT                    9
-#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
-#define MPU_RGDAAC_M2UM_MASK                     0x7000u
-#define MPU_RGDAAC_M2UM_SHIFT                    12
-#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
-#define MPU_RGDAAC_M2SM_MASK                     0x18000u
-#define MPU_RGDAAC_M2SM_SHIFT                    15
-#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
-#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
-#define MPU_RGDAAC_M3UM_SHIFT                    18
-#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
-#define MPU_RGDAAC_M3SM_MASK                     0x600000u
-#define MPU_RGDAAC_M3SM_SHIFT                    21
-#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
-#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
-#define MPU_RGDAAC_M4WE_SHIFT                    24
-#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
-#define MPU_RGDAAC_M4RE_SHIFT                    25
-#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
-#define MPU_RGDAAC_M5WE_SHIFT                    26
-#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
-#define MPU_RGDAAC_M5RE_SHIFT                    27
-#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
-#define MPU_RGDAAC_M6WE_SHIFT                    28
-#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
-#define MPU_RGDAAC_M6RE_SHIFT                    29
-#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
-#define MPU_RGDAAC_M7WE_SHIFT                    30
-#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
-#define MPU_RGDAAC_M7RE_SHIFT                    31
-
-/*!
- * @}
- */ /* end of group MPU_Register_Masks */
-
-
-/* MPU - Peripheral instance base addresses */
-/** Peripheral MPU base address */
-#define MPU_BASE                                 (0x4000D000u)
-/** Peripheral MPU base pointer */
-#define MPU                                      ((MPU_Type *)MPU_BASE)
-#define MPU_BASE_PTR                             (MPU)
-/** Array initializer of MPU peripheral base addresses */
-#define MPU_BASE_ADDRS                           { MPU_BASE }
-/** Array initializer of MPU peripheral base pointers */
-#define MPU_BASE_PTRS                            { MPU }
-
-/* ----------------------------------------------------------------------------
-   -- MPU - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
- * @{
- */
-
-
-/* MPU - Register instance definitions */
-/* MPU */
-#define MPU_CESR                                 MPU_CESR_REG(MPU)
-#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
-#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
-#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
-#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
-#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
-#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
-#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
-#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
-#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
-#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
-#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
-#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
-#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
-#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
-#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
-#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
-#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
-#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
-#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
-#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
-#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
-#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
-#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
-#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
-#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
-#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
-#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
-#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
-#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
-#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
-#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
-#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
-#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
-#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
-#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
-#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
-#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
-#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
-#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
-#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
-#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
-#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
-#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
-#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
-#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
-#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
-#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
-#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
-#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
-#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
-#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
-#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
-#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
-#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
-#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
-#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
-#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
-#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
-#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
-#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
-#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
-#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
-#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
-#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
-#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
-#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
-#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
-#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
-#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
-#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
-
-/* MPU - Register array accessors */
-#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
-#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
-#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
-#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
-
-/*!
- * @}
- */ /* end of group MPU_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group MPU_Peripheral_Access_Layer */
-
-
 /* ----------------------------------------------------------------------------
    -- NV Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -9320,40 +8245,7 @@ typedef struct {
   __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
   __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
   __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
-} NV_Type, *NV_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- NV - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register accessors */
-#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
-#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
-#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
-#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
-#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
-#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
-#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
-#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
-#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
-#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
-#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
-#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
-#define NV_FSEC_REG(base)                        ((base)->FSEC)
-#define NV_FOPT_REG(base)                        ((base)->FOPT)
-#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
-#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
+} NV_Type;
 
 /* ----------------------------------------------------------------------------
    -- NV Register Masks
@@ -9364,82 +8256,101 @@ typedef struct {
  * @{
  */
 
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK                     0xFFu
-#define NV_BACKKEY3_KEY_SHIFT                    0
-#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK                     0xFFu
-#define NV_BACKKEY2_KEY_SHIFT                    0
-#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK                     0xFFu
-#define NV_BACKKEY1_KEY_SHIFT                    0
-#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK                     0xFFu
-#define NV_BACKKEY0_KEY_SHIFT                    0
-#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK                     0xFFu
-#define NV_BACKKEY7_KEY_SHIFT                    0
-#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK                     0xFFu
-#define NV_BACKKEY6_KEY_SHIFT                    0
-#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK                     0xFFu
-#define NV_BACKKEY5_KEY_SHIFT                    0
-#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK                     0xFFu
-#define NV_BACKKEY4_KEY_SHIFT                    0
-#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK                      0xFFu
-#define NV_FPROT3_PROT_SHIFT                     0
-#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK                      0xFFu
-#define NV_FPROT2_PROT_SHIFT                     0
-#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK                      0xFFu
-#define NV_FPROT1_PROT_SHIFT                     0
-#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK                      0xFFu
-#define NV_FPROT0_PROT_SHIFT                     0
-#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK                         0x3u
-#define NV_FSEC_SEC_SHIFT                        0
-#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK                      0xCu
-#define NV_FSEC_FSLACC_SHIFT                     2
-#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK                        0x30u
-#define NV_FSEC_MEEN_SHIFT                       4
-#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK                       0xC0u
-#define NV_FSEC_KEYEN_SHIFT                      6
-#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK                      0x1u
-#define NV_FOPT_LPBOOT_SHIFT                     0
-#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT                 1
-#define NV_FOPT_NMI_DIS_MASK                     0x4u
-#define NV_FOPT_NMI_DIS_SHIFT                    2
-/* FEPROT Bit Fields */
-#define NV_FEPROT_EPROT_MASK                     0xFFu
-#define NV_FEPROT_EPROT_SHIFT                    0
-#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define NV_FDPROT_DPROT_MASK                     0xFFu
-#define NV_FDPROT_DPROT_SHIFT                    0
-#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT                    (0U)
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT                    (0U)
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT                    (0U)
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT                    (0U)
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT                    (0U)
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT                    (0U)
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT                    (0U)
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT                    (0U)
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK                      (0xFFU)
+#define NV_FPROT3_PROT_SHIFT                     (0U)
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK                      (0xFFU)
+#define NV_FPROT2_PROT_SHIFT                     (0U)
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK                      (0xFFU)
+#define NV_FPROT1_PROT_SHIFT                     (0U)
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK                      (0xFFU)
+#define NV_FPROT0_PROT_SHIFT                     (0U)
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK                         (0x3U)
+#define NV_FSEC_SEC_SHIFT                        (0U)
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      (0xCU)
+#define NV_FSEC_FSLACC_SHIFT                     (2U)
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        (0x30U)
+#define NV_FSEC_MEEN_SHIFT                       (4U)
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT                      (6U)
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT_MASK                      (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT                     (0U)
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  (0x2U)
+#define NV_FOPT_EZPORT_DIS_SHIFT                 (1U)
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_NMI_DIS_MASK                     (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT                    (2U)
+#define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+
+/*! @name FEPROT - Non-volatile EERAM Protection Register */
+#define NV_FEPROT_EPROT_MASK                     (0xFFU)
+#define NV_FEPROT_EPROT_SHIFT                    (0U)
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Non-volatile D-Flash Protection Register */
+#define NV_FDPROT_DPROT_MASK                     (0xFFU)
+#define NV_FDPROT_DPROT_SHIFT                    (0U)
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
+
 
 /*!
  * @}
@@ -9451,46 +8362,11 @@ typedef struct {
 #define FTFL_FlashConfig_BASE                    (0x400u)
 /** Peripheral FTFL_FlashConfig base pointer */
 #define FTFL_FlashConfig                         ((NV_Type *)FTFL_FlashConfig_BASE)
-#define FTFL_FlashConfig_BASE_PTR                (FTFL_FlashConfig)
 /** Array initializer of NV peripheral base addresses */
 #define NV_BASE_ADDRS                            { FTFL_FlashConfig_BASE }
 /** Array initializer of NV peripheral base pointers */
 #define NV_BASE_PTRS                             { FTFL_FlashConfig }
 
-/* ----------------------------------------------------------------------------
-   -- NV - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register instance definitions */
-/* FTFL_FlashConfig */
-#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFL_FlashConfig)
-#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFL_FlashConfig)
-#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFL_FlashConfig)
-#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFL_FlashConfig)
-#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFL_FlashConfig)
-#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFL_FlashConfig)
-#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFL_FlashConfig)
-#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFL_FlashConfig)
-#define NV_FPROT3                                NV_FPROT3_REG(FTFL_FlashConfig)
-#define NV_FPROT2                                NV_FPROT2_REG(FTFL_FlashConfig)
-#define NV_FPROT1                                NV_FPROT1_REG(FTFL_FlashConfig)
-#define NV_FPROT0                                NV_FPROT0_REG(FTFL_FlashConfig)
-#define NV_FSEC                                  NV_FSEC_REG(FTFL_FlashConfig)
-#define NV_FOPT                                  NV_FOPT_REG(FTFL_FlashConfig)
-#define NV_FEPROT                                NV_FEPROT_REG(FTFL_FlashConfig)
-#define NV_FDPROT                                NV_FDPROT_REG(FTFL_FlashConfig)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group NV_Peripheral_Access_Layer */
@@ -9508,25 +8384,7 @@ typedef struct {
 /** OSC - Register Layout Typedef */
 typedef struct {
   __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
-} OSC_Type, *OSC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- OSC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register accessors */
-#define OSC_CR_REG(base)                         ((base)->CR)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
+} OSC_Type;
 
 /* ----------------------------------------------------------------------------
    -- OSC Register Masks
@@ -9537,19 +8395,26 @@ typedef struct {
  * @{
  */
 
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK                        0x1u
-#define OSC_CR_SC16P_SHIFT                       0
-#define OSC_CR_SC8P_MASK                         0x2u
-#define OSC_CR_SC8P_SHIFT                        1
-#define OSC_CR_SC4P_MASK                         0x4u
-#define OSC_CR_SC4P_SHIFT                        2
-#define OSC_CR_SC2P_MASK                         0x8u
-#define OSC_CR_SC2P_SHIFT                        3
-#define OSC_CR_EREFSTEN_MASK                     0x20u
-#define OSC_CR_EREFSTEN_SHIFT                    5
-#define OSC_CR_ERCLKEN_MASK                      0x80u
-#define OSC_CR_ERCLKEN_SHIFT                     7
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK                        (0x1U)
+#define OSC_CR_SC16P_SHIFT                       (0U)
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         (0x2U)
+#define OSC_CR_SC8P_SHIFT                        (1U)
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         (0x4U)
+#define OSC_CR_SC4P_SHIFT                        (2U)
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         (0x8U)
+#define OSC_CR_SC2P_SHIFT                        (3U)
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT                    (5U)
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT                     (7U)
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
 
 /*!
  * @}
@@ -9561,31 +8426,11 @@ typedef struct {
 #define OSC_BASE                                 (0x40065000u)
 /** Peripheral OSC base pointer */
 #define OSC                                      ((OSC_Type *)OSC_BASE)
-#define OSC_BASE_PTR                             (OSC)
 /** Array initializer of OSC peripheral base addresses */
 #define OSC_BASE_ADDRS                           { OSC_BASE }
 /** Array initializer of OSC peripheral base pointers */
 #define OSC_BASE_PTRS                            { OSC }
 
-/* ----------------------------------------------------------------------------
-   -- OSC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register instance definitions */
-/* OSC */
-#define OSC_CR                                   OSC_CR_REG(OSC)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group OSC_Peripheral_Access_Layer */
@@ -9620,35 +8465,7 @@ typedef struct {
        uint8_t RESERVED_1[48];
   __IO uint32_t POEN;                              /**< Pulse-Out n Enable Register, offset: 0x190 */
   __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
-} PDB_Type, *PDB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- PDB - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register accessors */
-#define PDB_SC_REG(base)                         ((base)->SC)
-#define PDB_MOD_REG(base)                        ((base)->MOD)
-#define PDB_CNT_REG(base)                        ((base)->CNT)
-#define PDB_IDLY_REG(base)                       ((base)->IDLY)
-#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
-#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
-#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
-#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
-#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
-#define PDB_POEN_REG(base)                       ((base)->POEN)
-#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
+} PDB_Type;
 
 /* ----------------------------------------------------------------------------
    -- PDB Register Masks
@@ -9659,88 +8476,130 @@ typedef struct {
  * @{
  */
 
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK                         0x1u
-#define PDB_SC_LDOK_SHIFT                        0
-#define PDB_SC_CONT_MASK                         0x2u
-#define PDB_SC_CONT_SHIFT                        1
-#define PDB_SC_MULT_MASK                         0xCu
-#define PDB_SC_MULT_SHIFT                        2
-#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK                        0x20u
-#define PDB_SC_PDBIE_SHIFT                       5
-#define PDB_SC_PDBIF_MASK                        0x40u
-#define PDB_SC_PDBIF_SHIFT                       6
-#define PDB_SC_PDBEN_MASK                        0x80u
-#define PDB_SC_PDBEN_SHIFT                       7
-#define PDB_SC_TRGSEL_MASK                       0xF00u
-#define PDB_SC_TRGSEL_SHIFT                      8
-#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK                    0x7000u
-#define PDB_SC_PRESCALER_SHIFT                   12
-#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK                        0x8000u
-#define PDB_SC_DMAEN_SHIFT                       15
-#define PDB_SC_SWTRIG_MASK                       0x10000u
-#define PDB_SC_SWTRIG_SHIFT                      16
-#define PDB_SC_PDBEIE_MASK                       0x20000u
-#define PDB_SC_PDBEIE_SHIFT                      17
-#define PDB_SC_LDMOD_MASK                        0xC0000u
-#define PDB_SC_LDMOD_SHIFT                       18
-#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK                         0xFFFFu
-#define PDB_MOD_MOD_SHIFT                        0
-#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK                         0xFFFFu
-#define PDB_CNT_CNT_SHIFT                        0
-#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK                       0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT                      0
-#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK                           0xFFu
-#define PDB_C1_EN_SHIFT                          0
-#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK                          0xFF00u
-#define PDB_C1_TOS_SHIFT                         8
-#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK                           0xFF0000u
-#define PDB_C1_BB_SHIFT                          16
-#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK                           0xFFu
-#define PDB_S_ERR_SHIFT                          0
-#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK                            0xFF0000u
-#define PDB_S_CF_SHIFT                           16
-#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK                         0xFFFFu
-#define PDB_DLY_DLY_SHIFT                        0
-#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* INTC Bit Fields */
-#define PDB_INTC_TOE_MASK                        0x1u
-#define PDB_INTC_TOE_SHIFT                       0
-#define PDB_INTC_EXT_MASK                        0x2u
-#define PDB_INTC_EXT_SHIFT                       1
-/* INT Bit Fields */
-#define PDB_INT_INT_MASK                         0xFFFFu
-#define PDB_INT_INT_SHIFT                        0
-#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK                       0xFFu
-#define PDB_POEN_POEN_SHIFT                      0
-#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK                      0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT                     0
-#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT                     16
-#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+/*! @name SC - Status and Control Register */
+#define PDB_SC_LDOK_MASK                         (0x1U)
+#define PDB_SC_LDOK_SHIFT                        (0U)
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         (0x2U)
+#define PDB_SC_CONT_SHIFT                        (1U)
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         (0xCU)
+#define PDB_SC_MULT_SHIFT                        (2U)
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        (0x20U)
+#define PDB_SC_PDBIE_SHIFT                       (5U)
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        (0x40U)
+#define PDB_SC_PDBIF_SHIFT                       (6U)
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        (0x80U)
+#define PDB_SC_PDBEN_SHIFT                       (7U)
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT                      (8U)
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT                   (12U)
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        (0x8000U)
+#define PDB_SC_DMAEN_SHIFT                       (15U)
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       (0x10000U)
+#define PDB_SC_SWTRIG_SHIFT                      (16U)
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       (0x20000U)
+#define PDB_SC_PDBEIE_SHIFT                      (17U)
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT                       (18U)
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+
+/*! @name MOD - Modulus Register */
+#define PDB_MOD_MOD_MASK                         (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT                        (0U)
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+
+/*! @name CNT - Counter Register */
+#define PDB_CNT_CNT_MASK                         (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT                        (0U)
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+
+/*! @name IDLY - Interrupt Delay Register */
+#define PDB_IDLY_IDLY_MASK                       (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT                      (0U)
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+
+/*! @name C1 - Channel n Control Register 1 */
+#define PDB_C1_EN_MASK                           (0xFFU)
+#define PDB_C1_EN_SHIFT                          (0U)
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          (0xFF00U)
+#define PDB_C1_TOS_SHIFT                         (8U)
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           (0xFF0000U)
+#define PDB_C1_BB_SHIFT                          (16U)
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT                             (2U)
+
+/*! @name S - Channel n Status Register */
+#define PDB_S_ERR_MASK                           (0xFFU)
+#define PDB_S_ERR_SHIFT                          (0U)
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            (0xFF0000U)
+#define PDB_S_CF_SHIFT                           (16U)
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+
+/* The count of PDB_S */
+#define PDB_S_COUNT                              (2U)
+
+/*! @name DLY - Channel n Delay 0 Register..Channel n Delay 1 Register */
+#define PDB_DLY_DLY_MASK                         (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT                        (0U)
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT                            (2U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2                           (2U)
+
+/*! @name INTC - DAC Interval Trigger n Control Register */
+#define PDB_INTC_TOE_MASK                        (0x1U)
+#define PDB_INTC_TOE_SHIFT                       (0U)
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        (0x2U)
+#define PDB_INTC_EXT_SHIFT                       (1U)
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+
+/* The count of PDB_INTC */
+#define PDB_INTC_COUNT                           (2U)
+
+/*! @name INT - DAC Interval n Register */
+#define PDB_INT_INT_MASK                         (0xFFFFU)
+#define PDB_INT_INT_SHIFT                        (0U)
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+
+/* The count of PDB_INT */
+#define PDB_INT_COUNT                            (2U)
+
+/*! @name POEN - Pulse-Out n Enable Register */
+#define PDB_POEN_POEN_MASK                       (0xFFU)
+#define PDB_POEN_POEN_SHIFT                      (0U)
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+
+/*! @name PODLY - Pulse-Out n Delay Register */
+#define PDB_PODLY_DLY2_MASK                      (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT                     (0U)
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT                     (16U)
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT                          (3U)
+
 
 /*!
  * @}
@@ -9752,7 +8611,6 @@ typedef struct {
 #define PDB0_BASE                                (0x40036000u)
 /** Peripheral PDB0 base pointer */
 #define PDB0                                     ((PDB_Type *)PDB0_BASE)
-#define PDB0_BASE_PTR                            (PDB0)
 /** Array initializer of PDB peripheral base addresses */
 #define PDB_BASE_ADDRS                           { PDB0_BASE }
 /** Array initializer of PDB peripheral base pointers */
@@ -9760,52 +8618,6 @@ typedef struct {
 /** Interrupt vectors for the PDB peripheral type */
 #define PDB_IRQS                                 { PDB0_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- PDB - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register instance definitions */
-/* PDB0 */
-#define PDB0_SC                                  PDB_SC_REG(PDB0)
-#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
-#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
-#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
-#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
-#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
-#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
-#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
-#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
-#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
-#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
-#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
-#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
-#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
-#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
-#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
-#define PDB0_POEN                                PDB_POEN_REG(PDB0)
-#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
-#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
-#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
-
-/* PDB - Register array accessors */
-#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
-#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
-#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
-#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
-#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
-#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group PDB_Peripheral_Access_Layer */
@@ -9830,62 +8642,63 @@ typedef struct {
     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
   } CHANNEL[4];
-} PIT_Type, *PIT_MemMapPtr;
+} PIT_Type;
 
 /* ----------------------------------------------------------------------------
-   -- PIT - Register accessor macros
+   -- PIT Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @addtogroup PIT_Register_Masks PIT Register Masks
  * @{
  */
 
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK                         (0x1U)
+#define PIT_MCR_FRZ_SHIFT                        (0U)
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        (0x2U)
+#define PIT_MCR_MDIS_SHIFT                       (1U)
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
 
-/* PIT - Register accessors */
-#define PIT_MCR_REG(base)                        ((base)->MCR)
-#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
-#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
-#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
-#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT                      (0U)
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
 
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT                          (4U)
 
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT                       (0U)
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
 
-/* ----------------------------------------------------------------------------
-   -- PIT Register Masks
-   ---------------------------------------------------------------------------- */
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT                           (4U)
 
-/*!
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK                       (0x1U)
+#define PIT_TCTRL_TEN_SHIFT                      (0U)
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       (0x2U)
+#define PIT_TCTRL_TIE_SHIFT                      (1U)
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       (0x4U)
+#define PIT_TCTRL_CHN_SHIFT                      (2U)
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT                          (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK                        (0x1U)
+#define PIT_TFLG_TIF_SHIFT                       (0U)
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT                           (4U)
 
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK                         0x1u
-#define PIT_MCR_FRZ_SHIFT                        0
-#define PIT_MCR_MDIS_MASK                        0x2u
-#define PIT_MCR_MDIS_SHIFT                       1
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT                      0
-#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT                       0
-#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK                       0x1u
-#define PIT_TCTRL_TEN_SHIFT                      0
-#define PIT_TCTRL_TIE_MASK                       0x2u
-#define PIT_TCTRL_TIE_SHIFT                      1
-#define PIT_TCTRL_CHN_MASK                       0x4u
-#define PIT_TCTRL_CHN_SHIFT                      2
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK                        0x1u
-#define PIT_TFLG_TIF_SHIFT                       0
 
 /*!
  * @}
@@ -9897,54 +8710,12 @@ typedef struct {
 #define PIT_BASE                                 (0x40037000u)
 /** Peripheral PIT base pointer */
 #define PIT                                      ((PIT_Type *)PIT_BASE)
-#define PIT_BASE_PTR                             (PIT)
 /** Array initializer of PIT peripheral base addresses */
-#define PIT_BASE_ADDRS                           { PIT_BASE }
-/** Array initializer of PIT peripheral base pointers */
-#define PIT_BASE_PTRS                            { PIT }
-/** Interrupt vectors for the PIT peripheral type */
-#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
-
-/* ----------------------------------------------------------------------------
-   -- PIT - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register instance definitions */
-/* PIT */
-#define PIT_MCR                                  PIT_MCR_REG(PIT)
-#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
-#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
-#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
-#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
-#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
-#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
-#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
-#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
-#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
-#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
-#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
-#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
-#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
-#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
-#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
-#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
-
-/* PIT - Register array accessors */
-#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
-#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
-#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
-#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
 
 /*!
  * @}
@@ -9965,27 +8736,7 @@ typedef struct {
   __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
   __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
   __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type, *PMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- PMC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register accessors */
-#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
-#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
-#define PMC_REGSC_REG(base)                      ((base)->REGSC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
+} PMC_Type;
 
 /* ----------------------------------------------------------------------------
    -- PMC Register Masks
@@ -9996,37 +8747,51 @@ typedef struct {
  * @{
  */
 
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK                     0x3u
-#define PMC_LVDSC1_LVDV_SHIFT                    0
-#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK                    0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT                   4
-#define PMC_LVDSC1_LVDIE_MASK                    0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT                   5
-#define PMC_LVDSC1_LVDACK_MASK                   0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT                  6
-#define PMC_LVDSC1_LVDF_MASK                     0x80u
-#define PMC_LVDSC1_LVDF_SHIFT                    7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK                     0x3u
-#define PMC_LVDSC2_LVWV_SHIFT                    0
-#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK                    0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT                   5
-#define PMC_LVDSC2_LVWACK_MASK                   0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT                  6
-#define PMC_LVDSC2_LVWF_MASK                     0x80u
-#define PMC_LVDSC2_LVWF_SHIFT                    7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK                      0x1u
-#define PMC_REGSC_BGBE_SHIFT                     0
-#define PMC_REGSC_REGONS_MASK                    0x4u
-#define PMC_REGSC_REGONS_SHIFT                   2
-#define PMC_REGSC_ACKISO_MASK                    0x8u
-#define PMC_REGSC_ACKISO_SHIFT                   3
-#define PMC_REGSC_BGEN_MASK                      0x10u
-#define PMC_REGSC_BGEN_SHIFT                     4
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK                     (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT                    (0U)
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT                   (4U)
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT                   (5U)
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT                  (6U)
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT                    (7U)
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK                     (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT                    (0U)
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT                   (5U)
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT                  (6U)
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT                    (7U)
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK                      (0x1U)
+#define PMC_REGSC_BGBE_SHIFT                     (0U)
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    (0x4U)
+#define PMC_REGSC_REGONS_SHIFT                   (2U)
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT                   (3U)
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      (0x10U)
+#define PMC_REGSC_BGEN_SHIFT                     (4U)
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+
 
 /*!
  * @}
@@ -10038,7 +8803,6 @@ typedef struct {
 #define PMC_BASE                                 (0x4007D000u)
 /** Peripheral PMC base pointer */
 #define PMC                                      ((PMC_Type *)PMC_BASE)
-#define PMC_BASE_PTR                             (PMC)
 /** Array initializer of PMC peripheral base addresses */
 #define PMC_BASE_ADDRS                           { PMC_BASE }
 /** Array initializer of PMC peripheral base pointers */
@@ -10046,27 +8810,6 @@ typedef struct {
 /** Interrupt vectors for the PMC peripheral type */
 #define PMC_IRQS                                 { LVD_LVW_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- PMC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register instance definitions */
-/* PMC */
-#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
-#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
-#define PMC_REGSC                                PMC_REGSC_REG(PMC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group PMC_Peripheral_Access_Layer */
@@ -10092,31 +8835,7 @@ typedef struct {
   __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
   __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
   __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type, *PORT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- PORT - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register accessors */
-#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
-#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
-#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
-#define PORT_ISFR_REG(base)                      ((base)->ISFR)
-#define PORT_DFER_REG(base)                      ((base)->DFER)
-#define PORT_DFCR_REG(base)                      ((base)->DFCR)
-#define PORT_DFWR_REG(base)                      ((base)->DFWR)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
+} PORT_Type;
 
 /* ----------------------------------------------------------------------------
    -- PORT Register Masks
@@ -10127,58 +8846,77 @@ typedef struct {
  * @{
  */
 
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK                         0x1u
-#define PORT_PCR_PS_SHIFT                        0
-#define PORT_PCR_PE_MASK                         0x2u
-#define PORT_PCR_PE_SHIFT                        1
-#define PORT_PCR_SRE_MASK                        0x4u
-#define PORT_PCR_SRE_SHIFT                       2
-#define PORT_PCR_PFE_MASK                        0x10u
-#define PORT_PCR_PFE_SHIFT                       4
-#define PORT_PCR_ODE_MASK                        0x20u
-#define PORT_PCR_ODE_SHIFT                       5
-#define PORT_PCR_DSE_MASK                        0x40u
-#define PORT_PCR_DSE_SHIFT                       6
-#define PORT_PCR_MUX_MASK                        0x700u
-#define PORT_PCR_MUX_SHIFT                       8
-#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK                         0x8000u
-#define PORT_PCR_LK_SHIFT                        15
-#define PORT_PCR_IRQC_MASK                       0xF0000u
-#define PORT_PCR_IRQC_SHIFT                      16
-#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK                        0x1000000u
-#define PORT_PCR_ISF_SHIFT                       24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT                    0
-#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT                    16
-#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT                    0
-#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT                    16
-#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT                      0
-#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT                      0
-#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK                        0x1u
-#define PORT_DFCR_CS_SHIFT                       0
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK                      0x1Fu
-#define PORT_DFWR_FILT_SHIFT                     0
-#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK                         (0x1U)
+#define PORT_PCR_PS_SHIFT                        (0U)
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         (0x2U)
+#define PORT_PCR_PE_SHIFT                        (1U)
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        (0x4U)
+#define PORT_PCR_SRE_SHIFT                       (2U)
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        (0x10U)
+#define PORT_PCR_PFE_SHIFT                       (4U)
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        (0x20U)
+#define PORT_PCR_ODE_SHIFT                       (5U)
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        (0x40U)
+#define PORT_PCR_DSE_SHIFT                       (6U)
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        (0x700U)
+#define PORT_PCR_MUX_SHIFT                       (8U)
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         (0x8000U)
+#define PORT_PCR_LK_SHIFT                        (15U)
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT                      (16U)
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        (0x1000000U)
+#define PORT_PCR_ISF_SHIFT                       (24U)
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT                           (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT                    (16U)
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT                    (16U)
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT                      (0U)
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+/*! @name DFER - Digital Filter Enable Register */
+#define PORT_DFER_DFE_MASK                       (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT                      (0U)
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+
+/*! @name DFCR - Digital Filter Clock Register */
+#define PORT_DFCR_CS_MASK                        (0x1U)
+#define PORT_DFCR_CS_SHIFT                       (0U)
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+
+/*! @name DFWR - Digital Filter Width Register */
+#define PORT_DFWR_FILT_MASK                      (0x1FU)
+#define PORT_DFWR_FILT_SHIFT                     (0U)
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+
 
 /*!
  * @}
@@ -10190,27 +8928,22 @@ typedef struct {
 #define PORTA_BASE                               (0x40049000u)
 /** Peripheral PORTA base pointer */
 #define PORTA                                    ((PORT_Type *)PORTA_BASE)
-#define PORTA_BASE_PTR                           (PORTA)
 /** Peripheral PORTB base address */
 #define PORTB_BASE                               (0x4004A000u)
 /** Peripheral PORTB base pointer */
 #define PORTB                                    ((PORT_Type *)PORTB_BASE)
-#define PORTB_BASE_PTR                           (PORTB)
 /** Peripheral PORTC base address */
 #define PORTC_BASE                               (0x4004B000u)
 /** Peripheral PORTC base pointer */
 #define PORTC                                    ((PORT_Type *)PORTC_BASE)
-#define PORTC_BASE_PTR                           (PORTC)
 /** Peripheral PORTD base address */
 #define PORTD_BASE                               (0x4004C000u)
 /** Peripheral PORTD base pointer */
 #define PORTD                                    ((PORT_Type *)PORTD_BASE)
-#define PORTD_BASE_PTR                           (PORTD)
 /** Peripheral PORTE base address */
 #define PORTE_BASE                               (0x4004D000u)
 /** Peripheral PORTE base pointer */
 #define PORTE                                    ((PORT_Type *)PORTE_BASE)
-#define PORTE_BASE_PTR                           (PORTE)
 /** Array initializer of PORT peripheral base addresses */
 #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
 /** Array initializer of PORT peripheral base pointers */
@@ -10218,225 +8951,6 @@ typedef struct {
 /** Interrupt vectors for the PORT peripheral type */
 #define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- PORT - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register instance definitions */
-/* PORTA */
-#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
-#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
-#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
-#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
-#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
-#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
-#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
-#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
-#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
-#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
-#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
-#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
-#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
-#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
-#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
-#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
-#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
-#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
-#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
-#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
-#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
-#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
-#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
-#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
-#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
-#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
-#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
-#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
-#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
-#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
-#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
-#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
-#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
-#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
-#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
-#define PORTA_DFER                               PORT_DFER_REG(PORTA)
-#define PORTA_DFCR                               PORT_DFCR_REG(PORTA)
-#define PORTA_DFWR                               PORT_DFWR_REG(PORTA)
-/* PORTB */
-#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
-#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
-#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
-#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
-#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
-#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
-#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
-#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
-#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
-#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
-#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
-#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
-#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
-#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
-#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
-#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
-#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
-#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
-#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
-#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
-#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
-#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
-#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
-#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
-#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
-#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
-#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
-#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
-#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
-#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
-#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
-#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
-#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
-#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
-#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
-#define PORTB_DFER                               PORT_DFER_REG(PORTB)
-#define PORTB_DFCR                               PORT_DFCR_REG(PORTB)
-#define PORTB_DFWR                               PORT_DFWR_REG(PORTB)
-/* PORTC */
-#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
-#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
-#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
-#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
-#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
-#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
-#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
-#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
-#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
-#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
-#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
-#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
-#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
-#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
-#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
-#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
-#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
-#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
-#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
-#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
-#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
-#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
-#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
-#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
-#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
-#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
-#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
-#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
-#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
-#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
-#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
-#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
-#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
-#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
-#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
-#define PORTC_DFER                               PORT_DFER_REG(PORTC)
-#define PORTC_DFCR                               PORT_DFCR_REG(PORTC)
-#define PORTC_DFWR                               PORT_DFWR_REG(PORTC)
-/* PORTD */
-#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
-#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
-#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
-#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
-#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
-#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
-#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
-#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
-#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
-#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
-#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
-#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
-#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
-#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
-#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
-#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
-#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
-#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
-#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
-#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
-#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
-#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
-#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
-#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
-#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
-#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
-#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
-#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
-#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
-#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
-#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
-#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
-#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
-#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
-#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
-#define PORTD_DFER                               PORT_DFER_REG(PORTD)
-#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
-#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
-/* PORTE */
-#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
-#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
-#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
-#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
-#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
-#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
-#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
-#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
-#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
-#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
-#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
-#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
-#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
-#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
-#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
-#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
-#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
-#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
-#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
-#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
-#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
-#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
-#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
-#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
-#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
-#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
-#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
-#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
-#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
-#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
-#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
-#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
-#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
-#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
-#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
-#define PORTE_DFER                               PORT_DFER_REG(PORTE)
-#define PORTE_DFCR                               PORT_DFCR_REG(PORTE)
-#define PORTE_DFWR                               PORT_DFWR_REG(PORTE)
-
-/* PORT - Register array accessors */
-#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
-#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
-#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
-#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
-#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group PORT_Peripheral_Access_Layer */
@@ -10460,29 +8974,7 @@ typedef struct {
   __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
        uint8_t RESERVED_1[1];
   __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
-} RCM_Type, *RCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- RCM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register accessors */
-#define RCM_SRS0_REG(base)                       ((base)->SRS0)
-#define RCM_SRS1_REG(base)                       ((base)->SRS1)
-#define RCM_RPFC_REG(base)                       ((base)->RPFC)
-#define RCM_RPFW_REG(base)                       ((base)->RPFW)
-#define RCM_MR_REG(base)                         ((base)->MR)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
+} RCM_Type;
 
 /* ----------------------------------------------------------------------------
    -- RCM Register Masks
@@ -10493,47 +8985,67 @@ typedef struct {
  * @{
  */
 
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK                     0x1u
-#define RCM_SRS0_WAKEUP_SHIFT                    0
-#define RCM_SRS0_LVD_MASK                        0x2u
-#define RCM_SRS0_LVD_SHIFT                       1
-#define RCM_SRS0_LOC_MASK                        0x4u
-#define RCM_SRS0_LOC_SHIFT                       2
-#define RCM_SRS0_LOL_MASK                        0x8u
-#define RCM_SRS0_LOL_SHIFT                       3
-#define RCM_SRS0_WDOG_MASK                       0x20u
-#define RCM_SRS0_WDOG_SHIFT                      5
-#define RCM_SRS0_PIN_MASK                        0x40u
-#define RCM_SRS0_PIN_SHIFT                       6
-#define RCM_SRS0_POR_MASK                        0x80u
-#define RCM_SRS0_POR_SHIFT                       7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK                       0x1u
-#define RCM_SRS1_JTAG_SHIFT                      0
-#define RCM_SRS1_LOCKUP_MASK                     0x2u
-#define RCM_SRS1_LOCKUP_SHIFT                    1
-#define RCM_SRS1_SW_MASK                         0x4u
-#define RCM_SRS1_SW_SHIFT                        2
-#define RCM_SRS1_MDM_AP_MASK                     0x8u
-#define RCM_SRS1_MDM_AP_SHIFT                    3
-#define RCM_SRS1_EZPT_MASK                       0x10u
-#define RCM_SRS1_EZPT_SHIFT                      4
-#define RCM_SRS1_SACKERR_MASK                    0x20u
-#define RCM_SRS1_SACKERR_SHIFT                   5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
-#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT                  2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
-#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK                       0x2u
-#define RCM_MR_EZP_MS_SHIFT                      1
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK                     (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT                    (0U)
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        (0x2U)
+#define RCM_SRS0_LVD_SHIFT                       (1U)
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        (0x4U)
+#define RCM_SRS0_LOC_SHIFT                       (2U)
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        (0x8U)
+#define RCM_SRS0_LOL_SHIFT                       (3U)
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       (0x20U)
+#define RCM_SRS0_WDOG_SHIFT                      (5U)
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        (0x40U)
+#define RCM_SRS0_PIN_SHIFT                       (6U)
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        (0x80U)
+#define RCM_SRS0_POR_SHIFT                       (7U)
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_JTAG_MASK                       (0x1U)
+#define RCM_SRS1_JTAG_SHIFT                      (0U)
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT                    (1U)
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         (0x4U)
+#define RCM_SRS1_SW_SHIFT                        (2U)
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT                    (3U)
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       (0x10U)
+#define RCM_SRS1_EZPT_SHIFT                      (4U)
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT                   (5U)
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT                  (2U)
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_EZP_MS_MASK                       (0x2U)
+#define RCM_MR_EZP_MS_SHIFT                      (1U)
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+
 
 /*!
  * @}
@@ -10545,35 +9057,11 @@ typedef struct {
 #define RCM_BASE                                 (0x4007F000u)
 /** Peripheral RCM base pointer */
 #define RCM                                      ((RCM_Type *)RCM_BASE)
-#define RCM_BASE_PTR                             (RCM)
 /** Array initializer of RCM peripheral base addresses */
 #define RCM_BASE_ADDRS                           { RCM_BASE }
 /** Array initializer of RCM peripheral base pointers */
 #define RCM_BASE_PTRS                            { RCM }
 
-/* ----------------------------------------------------------------------------
-   -- RCM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register instance definitions */
-/* RCM */
-#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
-#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
-#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
-#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
-#define RCM_MR                                   RCM_MR_REG(RCM)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group RCM_Peripheral_Access_Layer */
@@ -10591,25 +9079,7 @@ typedef struct {
 /** RFSYS - Register Layout Typedef */
 typedef struct {
   __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type, *RFSYS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- RFSYS - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register accessors */
-#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
+} RFSYS_Type;
 
 /* ----------------------------------------------------------------------------
    -- RFSYS Register Masks
@@ -10620,19 +9090,23 @@ typedef struct {
  * @{
  */
 
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK                        0xFFu
-#define RFSYS_REG_LL_SHIFT                       0
-#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK                        0xFF00u
-#define RFSYS_REG_LH_SHIFT                       8
-#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK                        0xFF0000u
-#define RFSYS_REG_HL_SHIFT                       16
-#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK                        0xFF000000u
-#define RFSYS_REG_HH_SHIFT                       24
-#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK                        (0xFFU)
+#define RFSYS_REG_LL_SHIFT                       (0U)
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        (0xFF00U)
+#define RFSYS_REG_LH_SHIFT                       (8U)
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT                       (16U)
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT                       (24U)
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT                          (8U)
+
 
 /*!
  * @}
@@ -10644,41 +9118,11 @@ typedef struct {
 #define RFSYS_BASE                               (0x40041000u)
 /** Peripheral RFSYS base pointer */
 #define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
-#define RFSYS_BASE_PTR                           (RFSYS)
 /** Array initializer of RFSYS peripheral base addresses */
 #define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
 /** Array initializer of RFSYS peripheral base pointers */
 #define RFSYS_BASE_PTRS                          { RFSYS }
 
-/* ----------------------------------------------------------------------------
-   -- RFSYS - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register instance definitions */
-/* RFSYS */
-#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
-#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
-#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
-#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
-#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
-#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
-#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
-#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
-
-/* RFSYS - Register array accessors */
-#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group RFSYS_Peripheral_Access_Layer */
@@ -10696,25 +9140,7 @@ typedef struct {
 /** RFVBAT - Register Layout Typedef */
 typedef struct {
   __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type, *RFVBAT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- RFVBAT - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register accessors */
-#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
+} RFVBAT_Type;
 
 /* ----------------------------------------------------------------------------
    -- RFVBAT Register Masks
@@ -10725,19 +9151,23 @@ typedef struct {
  * @{
  */
 
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK                       0xFFu
-#define RFVBAT_REG_LL_SHIFT                      0
-#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK                       0xFF00u
-#define RFVBAT_REG_LH_SHIFT                      8
-#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK                       0xFF0000u
-#define RFVBAT_REG_HL_SHIFT                      16
-#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK                       0xFF000000u
-#define RFVBAT_REG_HH_SHIFT                      24
-#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK                       (0xFFU)
+#define RFVBAT_REG_LL_SHIFT                      (0U)
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT                      (8U)
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT                      (16U)
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT                      (24U)
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT                         (8U)
+
 
 /*!
  * @}
@@ -10749,41 +9179,11 @@ typedef struct {
 #define RFVBAT_BASE                              (0x4003E000u)
 /** Peripheral RFVBAT base pointer */
 #define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
-#define RFVBAT_BASE_PTR                          (RFVBAT)
 /** Array initializer of RFVBAT peripheral base addresses */
 #define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
 /** Array initializer of RFVBAT peripheral base pointers */
 #define RFVBAT_BASE_PTRS                         { RFVBAT }
 
-/* ----------------------------------------------------------------------------
-   -- RFVBAT - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register instance definitions */
-/* RFVBAT */
-#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
-#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
-#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
-#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
-#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
-#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
-#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
-#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
-
-/* RFVBAT - Register array accessors */
-#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group RFVBAT_Peripheral_Access_Layer */
@@ -10804,28 +9204,7 @@ typedef struct {
   __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
   __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
   __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
-} RNG_Type, *RNG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- RNG - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register accessors */
-#define RNG_CR_REG(base)                         ((base)->CR)
-#define RNG_SR_REG(base)                         ((base)->SR)
-#define RNG_ER_REG(base)                         ((base)->ER)
-#define RNG_OR_REG(base)                         ((base)->OR)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
+} RNG_Type;
 
 /* ----------------------------------------------------------------------------
    -- RNG Register Masks
@@ -10836,42 +9215,56 @@ typedef struct {
  * @{
  */
 
-/* CR Bit Fields */
-#define RNG_CR_GO_MASK                           0x1u
-#define RNG_CR_GO_SHIFT                          0
-#define RNG_CR_HA_MASK                           0x2u
-#define RNG_CR_HA_SHIFT                          1
-#define RNG_CR_INTM_MASK                         0x4u
-#define RNG_CR_INTM_SHIFT                        2
-#define RNG_CR_CLRI_MASK                         0x8u
-#define RNG_CR_CLRI_SHIFT                        3
-#define RNG_CR_SLP_MASK                          0x10u
-#define RNG_CR_SLP_SHIFT                         4
-/* SR Bit Fields */
-#define RNG_SR_SECV_MASK                         0x1u
-#define RNG_SR_SECV_SHIFT                        0
-#define RNG_SR_LRS_MASK                          0x2u
-#define RNG_SR_LRS_SHIFT                         1
-#define RNG_SR_ORU_MASK                          0x4u
-#define RNG_SR_ORU_SHIFT                         2
-#define RNG_SR_ERRI_MASK                         0x8u
-#define RNG_SR_ERRI_SHIFT                        3
-#define RNG_SR_SLP_MASK                          0x10u
-#define RNG_SR_SLP_SHIFT                         4
-#define RNG_SR_OREG_LVL_MASK                     0xFF00u
-#define RNG_SR_OREG_LVL_SHIFT                    8
-#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
-#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
-#define RNG_SR_OREG_SIZE_SHIFT                   16
-#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
-/* ER Bit Fields */
-#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
-#define RNG_ER_EXT_ENT_SHIFT                     0
-#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
-/* OR Bit Fields */
-#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
-#define RNG_OR_RANDOUT_SHIFT                     0
-#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+/*! @name CR - RNGA Control Register */
+#define RNG_CR_GO_MASK                           (0x1U)
+#define RNG_CR_GO_SHIFT                          (0U)
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           (0x2U)
+#define RNG_CR_HA_SHIFT                          (1U)
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         (0x4U)
+#define RNG_CR_INTM_SHIFT                        (2U)
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         (0x8U)
+#define RNG_CR_CLRI_SHIFT                        (3U)
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          (0x10U)
+#define RNG_CR_SLP_SHIFT                         (4U)
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
+
+/*! @name SR - RNGA Status Register */
+#define RNG_SR_SECV_MASK                         (0x1U)
+#define RNG_SR_SECV_SHIFT                        (0U)
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          (0x2U)
+#define RNG_SR_LRS_SHIFT                         (1U)
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          (0x4U)
+#define RNG_SR_ORU_SHIFT                         (2U)
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         (0x8U)
+#define RNG_SR_ERRI_SHIFT                        (3U)
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          (0x10U)
+#define RNG_SR_SLP_SHIFT                         (4U)
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     (0xFF00U)
+#define RNG_SR_OREG_LVL_SHIFT                    (8U)
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    (0xFF0000U)
+#define RNG_SR_OREG_SIZE_SHIFT                   (16U)
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
+
+/*! @name ER - RNGA Entropy Register */
+#define RNG_ER_EXT_ENT_MASK                      (0xFFFFFFFFU)
+#define RNG_ER_EXT_ENT_SHIFT                     (0U)
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
+
+/*! @name OR - RNGA Output Register */
+#define RNG_OR_RANDOUT_MASK                      (0xFFFFFFFFU)
+#define RNG_OR_RANDOUT_SHIFT                     (0U)
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
+
 
 /*!
  * @}
@@ -10883,7 +9276,6 @@ typedef struct {
 #define RNG_BASE                                 (0x400A0000u)
 /** Peripheral RNG base pointer */
 #define RNG                                      ((RNG_Type *)RNG_BASE)
-#define RNG_BASE_PTR                             (RNG)
 /** Array initializer of RNG peripheral base addresses */
 #define RNG_BASE_ADDRS                           { RNG_BASE }
 /** Array initializer of RNG peripheral base pointers */
@@ -10891,28 +9283,6 @@ typedef struct {
 /** Interrupt vectors for the RNG peripheral type */
 #define RNG_IRQS                                 { RNG_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- RNG - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register instance definitions */
-/* RNG */
-#define RNG_CR                                   RNG_CR_REG(RNG)
-#define RNG_SR                                   RNG_SR_REG(RNG)
-#define RNG_ER                                   RNG_ER_REG(RNG)
-#define RNG_OR                                   RNG_OR_REG(RNG)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group RNG_Peripheral_Access_Layer */
@@ -10940,34 +9310,7 @@ typedef struct {
        uint8_t RESERVED_0[2016];
   __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
   __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type, *RTC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- RTC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register accessors */
-#define RTC_TSR_REG(base)                        ((base)->TSR)
-#define RTC_TPR_REG(base)                        ((base)->TPR)
-#define RTC_TAR_REG(base)                        ((base)->TAR)
-#define RTC_TCR_REG(base)                        ((base)->TCR)
-#define RTC_CR_REG(base)                         ((base)->CR)
-#define RTC_SR_REG(base)                         ((base)->SR)
-#define RTC_LR_REG(base)                         ((base)->LR)
-#define RTC_IER_REG(base)                        ((base)->IER)
-#define RTC_WAR_REG(base)                        ((base)->WAR)
-#define RTC_RAR_REG(base)                        ((base)->RAR)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
+} RTC_Type;
 
 /* ----------------------------------------------------------------------------
    -- RTC Register Masks
@@ -10978,115 +9321,164 @@ typedef struct {
  * @{
  */
 
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT                        0
-#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK                         0xFFFFu
-#define RTC_TPR_TPR_SHIFT                        0
-#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT                        0
-#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK                         0xFFu
-#define RTC_TCR_TCR_SHIFT                        0
-#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK                         0xFF00u
-#define RTC_TCR_CIR_SHIFT                        8
-#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK                         0xFF0000u
-#define RTC_TCR_TCV_SHIFT                        16
-#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK                         0xFF000000u
-#define RTC_TCR_CIC_SHIFT                        24
-#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK                          0x1u
-#define RTC_CR_SWR_SHIFT                         0
-#define RTC_CR_WPE_MASK                          0x2u
-#define RTC_CR_WPE_SHIFT                         1
-#define RTC_CR_SUP_MASK                          0x4u
-#define RTC_CR_SUP_SHIFT                         2
-#define RTC_CR_UM_MASK                           0x8u
-#define RTC_CR_UM_SHIFT                          3
-#define RTC_CR_OSCE_MASK                         0x100u
-#define RTC_CR_OSCE_SHIFT                        8
-#define RTC_CR_CLKO_MASK                         0x200u
-#define RTC_CR_CLKO_SHIFT                        9
-#define RTC_CR_SC16P_MASK                        0x400u
-#define RTC_CR_SC16P_SHIFT                       10
-#define RTC_CR_SC8P_MASK                         0x800u
-#define RTC_CR_SC8P_SHIFT                        11
-#define RTC_CR_SC4P_MASK                         0x1000u
-#define RTC_CR_SC4P_SHIFT                        12
-#define RTC_CR_SC2P_MASK                         0x2000u
-#define RTC_CR_SC2P_SHIFT                        13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK                          0x1u
-#define RTC_SR_TIF_SHIFT                         0
-#define RTC_SR_TOF_MASK                          0x2u
-#define RTC_SR_TOF_SHIFT                         1
-#define RTC_SR_TAF_MASK                          0x4u
-#define RTC_SR_TAF_SHIFT                         2
-#define RTC_SR_TCE_MASK                          0x10u
-#define RTC_SR_TCE_SHIFT                         4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK                          0x8u
-#define RTC_LR_TCL_SHIFT                         3
-#define RTC_LR_CRL_MASK                          0x10u
-#define RTC_LR_CRL_SHIFT                         4
-#define RTC_LR_SRL_MASK                          0x20u
-#define RTC_LR_SRL_SHIFT                         5
-#define RTC_LR_LRL_MASK                          0x40u
-#define RTC_LR_LRL_SHIFT                         6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK                        0x1u
-#define RTC_IER_TIIE_SHIFT                       0
-#define RTC_IER_TOIE_MASK                        0x2u
-#define RTC_IER_TOIE_SHIFT                       1
-#define RTC_IER_TAIE_MASK                        0x4u
-#define RTC_IER_TAIE_SHIFT                       2
-#define RTC_IER_TSIE_MASK                        0x10u
-#define RTC_IER_TSIE_SHIFT                       4
-#define RTC_IER_WPON_MASK                        0x80u
-#define RTC_IER_WPON_SHIFT                       7
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK                        0x1u
-#define RTC_WAR_TSRW_SHIFT                       0
-#define RTC_WAR_TPRW_MASK                        0x2u
-#define RTC_WAR_TPRW_SHIFT                       1
-#define RTC_WAR_TARW_MASK                        0x4u
-#define RTC_WAR_TARW_SHIFT                       2
-#define RTC_WAR_TCRW_MASK                        0x8u
-#define RTC_WAR_TCRW_SHIFT                       3
-#define RTC_WAR_CRW_MASK                         0x10u
-#define RTC_WAR_CRW_SHIFT                        4
-#define RTC_WAR_SRW_MASK                         0x20u
-#define RTC_WAR_SRW_SHIFT                        5
-#define RTC_WAR_LRW_MASK                         0x40u
-#define RTC_WAR_LRW_SHIFT                        6
-#define RTC_WAR_IERW_MASK                        0x80u
-#define RTC_WAR_IERW_SHIFT                       7
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK                        0x1u
-#define RTC_RAR_TSRR_SHIFT                       0
-#define RTC_RAR_TPRR_MASK                        0x2u
-#define RTC_RAR_TPRR_SHIFT                       1
-#define RTC_RAR_TARR_MASK                        0x4u
-#define RTC_RAR_TARR_SHIFT                       2
-#define RTC_RAR_TCRR_MASK                        0x8u
-#define RTC_RAR_TCRR_SHIFT                       3
-#define RTC_RAR_CRR_MASK                         0x10u
-#define RTC_RAR_CRR_SHIFT                        4
-#define RTC_RAR_SRR_MASK                         0x20u
-#define RTC_RAR_SRR_SHIFT                        5
-#define RTC_RAR_LRR_MASK                         0x40u
-#define RTC_RAR_LRR_SHIFT                        6
-#define RTC_RAR_IERR_MASK                        0x80u
-#define RTC_RAR_IERR_SHIFT                       7
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT                        (0U)
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT                        (0U)
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK                          (0x1U)
+#define RTC_CR_SWR_SHIFT                         (0U)
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          (0x2U)
+#define RTC_CR_WPE_SHIFT                         (1U)
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          (0x4U)
+#define RTC_CR_SUP_SHIFT                         (2U)
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           (0x8U)
+#define RTC_CR_UM_SHIFT                          (3U)
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_OSCE_MASK                         (0x100U)
+#define RTC_CR_OSCE_SHIFT                        (8U)
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         (0x200U)
+#define RTC_CR_CLKO_SHIFT                        (9U)
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        (0x400U)
+#define RTC_CR_SC16P_SHIFT                       (10U)
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         (0x800U)
+#define RTC_CR_SC8P_SHIFT                        (11U)
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         (0x1000U)
+#define RTC_CR_SC4P_SHIFT                        (12U)
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         (0x2000U)
+#define RTC_CR_SC2P_SHIFT                        (13U)
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK                          (0x1U)
+#define RTC_SR_TIF_SHIFT                         (0U)
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          (0x2U)
+#define RTC_SR_TOF_SHIFT                         (1U)
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          (0x4U)
+#define RTC_SR_TAF_SHIFT                         (2U)
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          (0x10U)
+#define RTC_SR_TCE_SHIFT                         (4U)
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK                          (0x8U)
+#define RTC_LR_TCL_SHIFT                         (3U)
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          (0x10U)
+#define RTC_LR_CRL_SHIFT                         (4U)
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          (0x20U)
+#define RTC_LR_SRL_SHIFT                         (5U)
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          (0x40U)
+#define RTC_LR_LRL_SHIFT                         (6U)
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK                        (0x1U)
+#define RTC_IER_TIIE_SHIFT                       (0U)
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        (0x2U)
+#define RTC_IER_TOIE_SHIFT                       (1U)
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        (0x4U)
+#define RTC_IER_TAIE_SHIFT                       (2U)
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        (0x10U)
+#define RTC_IER_TSIE_SHIFT                       (4U)
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        (0x80U)
+#define RTC_IER_WPON_SHIFT                       (7U)
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW_MASK                        (0x1U)
+#define RTC_WAR_TSRW_SHIFT                       (0U)
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        (0x2U)
+#define RTC_WAR_TPRW_SHIFT                       (1U)
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        (0x4U)
+#define RTC_WAR_TARW_SHIFT                       (2U)
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        (0x8U)
+#define RTC_WAR_TCRW_SHIFT                       (3U)
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         (0x10U)
+#define RTC_WAR_CRW_SHIFT                        (4U)
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         (0x20U)
+#define RTC_WAR_SRW_SHIFT                        (5U)
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         (0x40U)
+#define RTC_WAR_LRW_SHIFT                        (6U)
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        (0x80U)
+#define RTC_WAR_IERW_SHIFT                       (7U)
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR_MASK                        (0x1U)
+#define RTC_RAR_TSRR_SHIFT                       (0U)
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        (0x2U)
+#define RTC_RAR_TPRR_SHIFT                       (1U)
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        (0x4U)
+#define RTC_RAR_TARR_SHIFT                       (2U)
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        (0x8U)
+#define RTC_RAR_TCRR_SHIFT                       (3U)
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         (0x10U)
+#define RTC_RAR_CRR_SHIFT                        (4U)
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         (0x20U)
+#define RTC_RAR_SRR_SHIFT                        (5U)
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         (0x40U)
+#define RTC_RAR_LRR_SHIFT                        (6U)
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        (0x80U)
+#define RTC_RAR_IERR_SHIFT                       (7U)
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+
 
 /*!
  * @}
@@ -11098,7 +9490,6 @@ typedef struct {
 #define RTC_BASE                                 (0x4003D000u)
 /** Peripheral RTC base pointer */
 #define RTC                                      ((RTC_Type *)RTC_BASE)
-#define RTC_BASE_PTR                             (RTC)
 /** Array initializer of RTC peripheral base addresses */
 #define RTC_BASE_ADDRS                           { RTC_BASE }
 /** Array initializer of RTC peripheral base pointers */
@@ -11107,34 +9498,6 @@ typedef struct {
 #define RTC_IRQS                                 { RTC_IRQn }
 #define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- RTC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register instance definitions */
-/* RTC */
-#define RTC_TSR                                  RTC_TSR_REG(RTC)
-#define RTC_TPR                                  RTC_TPR_REG(RTC)
-#define RTC_TAR                                  RTC_TAR_REG(RTC)
-#define RTC_TCR                                  RTC_TCR_REG(RTC)
-#define RTC_CR                                   RTC_CR_REG(RTC)
-#define RTC_SR                                   RTC_SR_REG(RTC)
-#define RTC_LR                                   RTC_LR_REG(RTC)
-#define RTC_IER                                  RTC_IER_REG(RTC)
-#define RTC_WAR                                  RTC_WAR_REG(RTC)
-#define RTC_RAR                                  RTC_RAR_REG(RTC)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group RTC_Peripheral_Access_Layer */
@@ -11175,45 +9538,7 @@ typedef struct {
   __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
        uint8_t RESERVED_2[52];
   __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
-} SDHC_Type, *SDHC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- SDHC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
- * @{
- */
-
-
-/* SDHC - Register accessors */
-#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
-#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
-#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
-#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
-#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
-#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
-#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
-#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
-#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
-#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
-#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
-#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
-#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
-#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
-#define SDHC_WML_REG(base)                       ((base)->WML)
-#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
-#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
-#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
-#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
-#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
-#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
-
-/*!
- * @}
- */ /* end of group SDHC_Register_Accessor_Macros */
-
+} SDHC_Type;
 
 /* ----------------------------------------------------------------------------
    -- SDHC Register Masks
@@ -11224,378 +9549,534 @@ typedef struct {
  * @{
  */
 
-/* DSADDR Bit Fields */
-#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
-#define SDHC_DSADDR_DSADDR_SHIFT                 2
-#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
-/* BLKATTR Bit Fields */
-#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
-#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
-#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
-#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
-#define SDHC_BLKATTR_BLKCNT_SHIFT                16
-#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
-/* CMDARG Bit Fields */
-#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
-#define SDHC_CMDARG_CMDARG_SHIFT                 0
-#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
-/* XFERTYP Bit Fields */
-#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
-#define SDHC_XFERTYP_DMAEN_SHIFT                 0
-#define SDHC_XFERTYP_BCEN_MASK                   0x2u
-#define SDHC_XFERTYP_BCEN_SHIFT                  1
-#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
-#define SDHC_XFERTYP_AC12EN_SHIFT                2
-#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
-#define SDHC_XFERTYP_DTDSEL_SHIFT                4
-#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
-#define SDHC_XFERTYP_MSBSEL_SHIFT                5
-#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
-#define SDHC_XFERTYP_RSPTYP_SHIFT                16
-#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
-#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
-#define SDHC_XFERTYP_CCCEN_SHIFT                 19
-#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
-#define SDHC_XFERTYP_CICEN_SHIFT                 20
-#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
-#define SDHC_XFERTYP_DPSEL_SHIFT                 21
-#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
-#define SDHC_XFERTYP_CMDTYP_SHIFT                22
-#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
-#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
-#define SDHC_XFERTYP_CMDINX_SHIFT                24
-#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
-/* CMDRSP Bit Fields */
-#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
-#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
-#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
-#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
-#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
-#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
-#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
-#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
-/* DATPORT Bit Fields */
-#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
-#define SDHC_DATPORT_DATCONT_SHIFT               0
-#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
-/* PRSSTAT Bit Fields */
-#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
-#define SDHC_PRSSTAT_CIHB_SHIFT                  0
-#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
-#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
-#define SDHC_PRSSTAT_DLA_MASK                    0x4u
-#define SDHC_PRSSTAT_DLA_SHIFT                   2
-#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
-#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
-#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
-#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
-#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
-#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
-#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
-#define SDHC_PRSSTAT_PEROFF_SHIFT                6
-#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
-#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
-#define SDHC_PRSSTAT_WTA_MASK                    0x100u
-#define SDHC_PRSSTAT_WTA_SHIFT                   8
-#define SDHC_PRSSTAT_RTA_MASK                    0x200u
-#define SDHC_PRSSTAT_RTA_SHIFT                   9
-#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
-#define SDHC_PRSSTAT_BWEN_SHIFT                  10
-#define SDHC_PRSSTAT_BREN_MASK                   0x800u
-#define SDHC_PRSSTAT_BREN_SHIFT                  11
-#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
-#define SDHC_PRSSTAT_CINS_SHIFT                  16
-#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
-#define SDHC_PRSSTAT_CLSL_SHIFT                  23
-#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
-#define SDHC_PRSSTAT_DLSL_SHIFT                  24
-#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
-/* PROCTL Bit Fields */
-#define SDHC_PROCTL_LCTL_MASK                    0x1u
-#define SDHC_PROCTL_LCTL_SHIFT                   0
-#define SDHC_PROCTL_DTW_MASK                     0x6u
-#define SDHC_PROCTL_DTW_SHIFT                    1
-#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
-#define SDHC_PROCTL_D3CD_MASK                    0x8u
-#define SDHC_PROCTL_D3CD_SHIFT                   3
-#define SDHC_PROCTL_EMODE_MASK                   0x30u
-#define SDHC_PROCTL_EMODE_SHIFT                  4
-#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
-#define SDHC_PROCTL_CDTL_MASK                    0x40u
-#define SDHC_PROCTL_CDTL_SHIFT                   6
-#define SDHC_PROCTL_CDSS_MASK                    0x80u
-#define SDHC_PROCTL_CDSS_SHIFT                   7
-#define SDHC_PROCTL_DMAS_MASK                    0x300u
-#define SDHC_PROCTL_DMAS_SHIFT                   8
-#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
-#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
-#define SDHC_PROCTL_SABGREQ_SHIFT                16
-#define SDHC_PROCTL_CREQ_MASK                    0x20000u
-#define SDHC_PROCTL_CREQ_SHIFT                   17
-#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
-#define SDHC_PROCTL_RWCTL_SHIFT                  18
-#define SDHC_PROCTL_IABG_MASK                    0x80000u
-#define SDHC_PROCTL_IABG_SHIFT                   19
-#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
-#define SDHC_PROCTL_WECINT_SHIFT                 24
-#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
-#define SDHC_PROCTL_WECINS_SHIFT                 25
-#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
-#define SDHC_PROCTL_WECRM_SHIFT                  26
-/* SYSCTL Bit Fields */
-#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
-#define SDHC_SYSCTL_IPGEN_SHIFT                  0
-#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
-#define SDHC_SYSCTL_HCKEN_SHIFT                  1
-#define SDHC_SYSCTL_PEREN_MASK                   0x4u
-#define SDHC_SYSCTL_PEREN_SHIFT                  2
-#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
-#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
-#define SDHC_SYSCTL_DVS_MASK                     0xF0u
-#define SDHC_SYSCTL_DVS_SHIFT                    4
-#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
-#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
-#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
-#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
-#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
-#define SDHC_SYSCTL_DTOCV_SHIFT                  16
-#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
-#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
-#define SDHC_SYSCTL_RSTA_SHIFT                   24
-#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
-#define SDHC_SYSCTL_RSTC_SHIFT                   25
-#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
-#define SDHC_SYSCTL_RSTD_SHIFT                   26
-#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
-#define SDHC_SYSCTL_INITA_SHIFT                  27
-/* IRQSTAT Bit Fields */
-#define SDHC_IRQSTAT_CC_MASK                     0x1u
-#define SDHC_IRQSTAT_CC_SHIFT                    0
-#define SDHC_IRQSTAT_TC_MASK                     0x2u
-#define SDHC_IRQSTAT_TC_SHIFT                    1
-#define SDHC_IRQSTAT_BGE_MASK                    0x4u
-#define SDHC_IRQSTAT_BGE_SHIFT                   2
-#define SDHC_IRQSTAT_DINT_MASK                   0x8u
-#define SDHC_IRQSTAT_DINT_SHIFT                  3
-#define SDHC_IRQSTAT_BWR_MASK                    0x10u
-#define SDHC_IRQSTAT_BWR_SHIFT                   4
-#define SDHC_IRQSTAT_BRR_MASK                    0x20u
-#define SDHC_IRQSTAT_BRR_SHIFT                   5
-#define SDHC_IRQSTAT_CINS_MASK                   0x40u
-#define SDHC_IRQSTAT_CINS_SHIFT                  6
-#define SDHC_IRQSTAT_CRM_MASK                    0x80u
-#define SDHC_IRQSTAT_CRM_SHIFT                   7
-#define SDHC_IRQSTAT_CINT_MASK                   0x100u
-#define SDHC_IRQSTAT_CINT_SHIFT                  8
-#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
-#define SDHC_IRQSTAT_CTOE_SHIFT                  16
-#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
-#define SDHC_IRQSTAT_CCE_SHIFT                   17
-#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
-#define SDHC_IRQSTAT_CEBE_SHIFT                  18
-#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
-#define SDHC_IRQSTAT_CIE_SHIFT                   19
-#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
-#define SDHC_IRQSTAT_DTOE_SHIFT                  20
-#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
-#define SDHC_IRQSTAT_DCE_SHIFT                   21
-#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
-#define SDHC_IRQSTAT_DEBE_SHIFT                  22
-#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
-#define SDHC_IRQSTAT_AC12E_SHIFT                 24
-#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
-#define SDHC_IRQSTAT_DMAE_SHIFT                  28
-/* IRQSTATEN Bit Fields */
-#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
-#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
-#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
-#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
-#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
-#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
-#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
-#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
-#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
-#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
-#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
-#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
-#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
-#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
-#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
-#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
-#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
-#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
-#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
-#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
-#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
-#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
-#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
-#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
-#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
-#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
-#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
-#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
-#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
-#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
-#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
-#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
-#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
-#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
-#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
-#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
-/* IRQSIGEN Bit Fields */
-#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
-#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
-#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
-#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
-#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
-#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
-#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
-#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
-#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
-#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
-#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
-#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
-#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
-#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
-#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
-#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
-#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
-#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
-#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
-#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
-#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
-#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
-#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
-#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
-#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
-#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
-#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
-#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
-#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
-#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
-#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
-#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
-#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
-#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
-#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
-#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
-/* AC12ERR Bit Fields */
-#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
-#define SDHC_AC12ERR_AC12NE_SHIFT                0
-#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
-#define SDHC_AC12ERR_AC12TOE_SHIFT               1
-#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
-#define SDHC_AC12ERR_AC12EBE_SHIFT               2
-#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
-#define SDHC_AC12ERR_AC12CE_SHIFT                3
-#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
-#define SDHC_AC12ERR_AC12IE_SHIFT                4
-#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
-#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
-/* HTCAPBLT Bit Fields */
-#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
-#define SDHC_HTCAPBLT_MBL_SHIFT                  16
-#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
-#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
-#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
-#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
-#define SDHC_HTCAPBLT_HSS_SHIFT                  21
-#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
-#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
-#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
-#define SDHC_HTCAPBLT_SRS_SHIFT                  23
-#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
-#define SDHC_HTCAPBLT_VS33_SHIFT                 24
-#define SDHC_HTCAPBLT_VS30_MASK                  0x2000000u
-#define SDHC_HTCAPBLT_VS30_SHIFT                 25
-#define SDHC_HTCAPBLT_VS18_MASK                  0x4000000u
-#define SDHC_HTCAPBLT_VS18_SHIFT                 26
-/* WML Bit Fields */
-#define SDHC_WML_RDWML_MASK                      0xFFu
-#define SDHC_WML_RDWML_SHIFT                     0
-#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
-#define SDHC_WML_WRWML_MASK                      0xFF0000u
-#define SDHC_WML_WRWML_SHIFT                     16
-#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
-/* FEVT Bit Fields */
-#define SDHC_FEVT_AC12NE_MASK                    0x1u
-#define SDHC_FEVT_AC12NE_SHIFT                   0
-#define SDHC_FEVT_AC12TOE_MASK                   0x2u
-#define SDHC_FEVT_AC12TOE_SHIFT                  1
-#define SDHC_FEVT_AC12CE_MASK                    0x4u
-#define SDHC_FEVT_AC12CE_SHIFT                   2
-#define SDHC_FEVT_AC12EBE_MASK                   0x8u
-#define SDHC_FEVT_AC12EBE_SHIFT                  3
-#define SDHC_FEVT_AC12IE_MASK                    0x10u
-#define SDHC_FEVT_AC12IE_SHIFT                   4
-#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
-#define SDHC_FEVT_CNIBAC12E_SHIFT                7
-#define SDHC_FEVT_CTOE_MASK                      0x10000u
-#define SDHC_FEVT_CTOE_SHIFT                     16
-#define SDHC_FEVT_CCE_MASK                       0x20000u
-#define SDHC_FEVT_CCE_SHIFT                      17
-#define SDHC_FEVT_CEBE_MASK                      0x40000u
-#define SDHC_FEVT_CEBE_SHIFT                     18
-#define SDHC_FEVT_CIE_MASK                       0x80000u
-#define SDHC_FEVT_CIE_SHIFT                      19
-#define SDHC_FEVT_DTOE_MASK                      0x100000u
-#define SDHC_FEVT_DTOE_SHIFT                     20
-#define SDHC_FEVT_DCE_MASK                       0x200000u
-#define SDHC_FEVT_DCE_SHIFT                      21
-#define SDHC_FEVT_DEBE_MASK                      0x400000u
-#define SDHC_FEVT_DEBE_SHIFT                     22
-#define SDHC_FEVT_AC12E_MASK                     0x1000000u
-#define SDHC_FEVT_AC12E_SHIFT                    24
-#define SDHC_FEVT_DMAE_MASK                      0x10000000u
-#define SDHC_FEVT_DMAE_SHIFT                     28
-#define SDHC_FEVT_CINT_MASK                      0x80000000u
-#define SDHC_FEVT_CINT_SHIFT                     31
-/* ADMAES Bit Fields */
-#define SDHC_ADMAES_ADMAES_MASK                  0x3u
-#define SDHC_ADMAES_ADMAES_SHIFT                 0
-#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
-#define SDHC_ADMAES_ADMALME_MASK                 0x4u
-#define SDHC_ADMAES_ADMALME_SHIFT                2
-#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
-#define SDHC_ADMAES_ADMADCE_SHIFT                3
-/* ADSADDR Bit Fields */
-#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
-#define SDHC_ADSADDR_ADSADDR_SHIFT               2
-#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
-/* VENDOR Bit Fields */
-#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
-#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
-#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
-#define SDHC_VENDOR_EXBLKNU_SHIFT                1
-#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
-#define SDHC_VENDOR_INTSTVAL_SHIFT               16
-#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
-/* MMCBOOT Bit Fields */
-#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
-#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
-#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
-#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
-#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
-#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
-#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
-#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
-#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
-#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
-#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
-#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
-#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
-#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
-/* HOSTVER Bit Fields */
-#define SDHC_HOSTVER_SVN_MASK                    0xFFu
-#define SDHC_HOSTVER_SVN_SHIFT                   0
-#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
-#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
-#define SDHC_HOSTVER_VVN_SHIFT                   8
-#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+/*! @name DSADDR - DMA System Address register */
+#define SDHC_DSADDR_DSADDR_MASK                  (0xFFFFFFFCU)
+#define SDHC_DSADDR_DSADDR_SHIFT                 (2U)
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
+
+/*! @name BLKATTR - Block Attributes register */
+#define SDHC_BLKATTR_BLKSIZE_MASK                (0x1FFFU)
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               (0U)
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 (0xFFFF0000U)
+#define SDHC_BLKATTR_BLKCNT_SHIFT                (16U)
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
+
+/*! @name CMDARG - Command Argument register */
+#define SDHC_CMDARG_CMDARG_MASK                  (0xFFFFFFFFU)
+#define SDHC_CMDARG_CMDARG_SHIFT                 (0U)
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
+
+/*! @name XFERTYP - Transfer Type register */
+#define SDHC_XFERTYP_DMAEN_MASK                  (0x1U)
+#define SDHC_XFERTYP_DMAEN_SHIFT                 (0U)
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   (0x2U)
+#define SDHC_XFERTYP_BCEN_SHIFT                  (1U)
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 (0x4U)
+#define SDHC_XFERTYP_AC12EN_SHIFT                (2U)
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 (0x10U)
+#define SDHC_XFERTYP_DTDSEL_SHIFT                (4U)
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 (0x20U)
+#define SDHC_XFERTYP_MSBSEL_SHIFT                (5U)
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 (0x30000U)
+#define SDHC_XFERTYP_RSPTYP_SHIFT                (16U)
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  (0x80000U)
+#define SDHC_XFERTYP_CCCEN_SHIFT                 (19U)
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  (0x100000U)
+#define SDHC_XFERTYP_CICEN_SHIFT                 (20U)
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  (0x200000U)
+#define SDHC_XFERTYP_DPSEL_SHIFT                 (21U)
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 (0xC00000U)
+#define SDHC_XFERTYP_CMDTYP_SHIFT                (22U)
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 (0x3F000000U)
+#define SDHC_XFERTYP_CMDINX_SHIFT                (24U)
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
+
+/*! @name CMDRSP - Command Response 0..Command Response 3 */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
+
+/* The count of SDHC_CMDRSP */
+#define SDHC_CMDRSP_COUNT                        (4U)
+
+/*! @name DATPORT - Buffer Data Port register */
+#define SDHC_DATPORT_DATCONT_MASK                (0xFFFFFFFFU)
+#define SDHC_DATPORT_DATCONT_SHIFT               (0U)
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
+
+/*! @name PRSSTAT - Present State register */
+#define SDHC_PRSSTAT_CIHB_MASK                   (0x1U)
+#define SDHC_PRSSTAT_CIHB_SHIFT                  (0U)
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  (0x2U)
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 (1U)
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    (0x4U)
+#define SDHC_PRSSTAT_DLA_SHIFT                   (2U)
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  (0x8U)
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 (3U)
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 (0x10U)
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                (4U)
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 (0x20U)
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                (5U)
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 (0x40U)
+#define SDHC_PRSSTAT_PEROFF_SHIFT                (6U)
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  (0x80U)
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 (7U)
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    (0x100U)
+#define SDHC_PRSSTAT_WTA_SHIFT                   (8U)
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    (0x200U)
+#define SDHC_PRSSTAT_RTA_SHIFT                   (9U)
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   (0x400U)
+#define SDHC_PRSSTAT_BWEN_SHIFT                  (10U)
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   (0x800U)
+#define SDHC_PRSSTAT_BREN_SHIFT                  (11U)
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   (0x10000U)
+#define SDHC_PRSSTAT_CINS_SHIFT                  (16U)
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   (0x800000U)
+#define SDHC_PRSSTAT_CLSL_SHIFT                  (23U)
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   (0xFF000000U)
+#define SDHC_PRSSTAT_DLSL_SHIFT                  (24U)
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
+
+/*! @name PROCTL - Protocol Control register */
+#define SDHC_PROCTL_LCTL_MASK                    (0x1U)
+#define SDHC_PROCTL_LCTL_SHIFT                   (0U)
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     (0x6U)
+#define SDHC_PROCTL_DTW_SHIFT                    (1U)
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    (0x8U)
+#define SDHC_PROCTL_D3CD_SHIFT                   (3U)
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   (0x30U)
+#define SDHC_PROCTL_EMODE_SHIFT                  (4U)
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    (0x40U)
+#define SDHC_PROCTL_CDTL_SHIFT                   (6U)
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    (0x80U)
+#define SDHC_PROCTL_CDSS_SHIFT                   (7U)
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    (0x300U)
+#define SDHC_PROCTL_DMAS_SHIFT                   (8U)
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 (0x10000U)
+#define SDHC_PROCTL_SABGREQ_SHIFT                (16U)
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    (0x20000U)
+#define SDHC_PROCTL_CREQ_SHIFT                   (17U)
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   (0x40000U)
+#define SDHC_PROCTL_RWCTL_SHIFT                  (18U)
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    (0x80000U)
+#define SDHC_PROCTL_IABG_SHIFT                   (19U)
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  (0x1000000U)
+#define SDHC_PROCTL_WECINT_SHIFT                 (24U)
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  (0x2000000U)
+#define SDHC_PROCTL_WECINS_SHIFT                 (25U)
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   (0x4000000U)
+#define SDHC_PROCTL_WECRM_SHIFT                  (26U)
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
+
+/*! @name SYSCTL - System Control register */
+#define SDHC_SYSCTL_IPGEN_MASK                   (0x1U)
+#define SDHC_SYSCTL_IPGEN_SHIFT                  (0U)
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   (0x2U)
+#define SDHC_SYSCTL_HCKEN_SHIFT                  (1U)
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   (0x4U)
+#define SDHC_SYSCTL_PEREN_SHIFT                  (2U)
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 (0x8U)
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                (3U)
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     (0xF0U)
+#define SDHC_SYSCTL_DVS_SHIFT                    (4U)
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 (0xFF00U)
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                (8U)
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   (0xF0000U)
+#define SDHC_SYSCTL_DTOCV_SHIFT                  (16U)
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    (0x1000000U)
+#define SDHC_SYSCTL_RSTA_SHIFT                   (24U)
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    (0x2000000U)
+#define SDHC_SYSCTL_RSTC_SHIFT                   (25U)
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    (0x4000000U)
+#define SDHC_SYSCTL_RSTD_SHIFT                   (26U)
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   (0x8000000U)
+#define SDHC_SYSCTL_INITA_SHIFT                  (27U)
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
+
+/*! @name IRQSTAT - Interrupt Status register */
+#define SDHC_IRQSTAT_CC_MASK                     (0x1U)
+#define SDHC_IRQSTAT_CC_SHIFT                    (0U)
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     (0x2U)
+#define SDHC_IRQSTAT_TC_SHIFT                    (1U)
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    (0x4U)
+#define SDHC_IRQSTAT_BGE_SHIFT                   (2U)
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   (0x8U)
+#define SDHC_IRQSTAT_DINT_SHIFT                  (3U)
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    (0x10U)
+#define SDHC_IRQSTAT_BWR_SHIFT                   (4U)
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    (0x20U)
+#define SDHC_IRQSTAT_BRR_SHIFT                   (5U)
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   (0x40U)
+#define SDHC_IRQSTAT_CINS_SHIFT                  (6U)
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    (0x80U)
+#define SDHC_IRQSTAT_CRM_SHIFT                   (7U)
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   (0x100U)
+#define SDHC_IRQSTAT_CINT_SHIFT                  (8U)
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   (0x10000U)
+#define SDHC_IRQSTAT_CTOE_SHIFT                  (16U)
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    (0x20000U)
+#define SDHC_IRQSTAT_CCE_SHIFT                   (17U)
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   (0x40000U)
+#define SDHC_IRQSTAT_CEBE_SHIFT                  (18U)
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    (0x80000U)
+#define SDHC_IRQSTAT_CIE_SHIFT                   (19U)
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   (0x100000U)
+#define SDHC_IRQSTAT_DTOE_SHIFT                  (20U)
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    (0x200000U)
+#define SDHC_IRQSTAT_DCE_SHIFT                   (21U)
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   (0x400000U)
+#define SDHC_IRQSTAT_DEBE_SHIFT                  (22U)
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  (0x1000000U)
+#define SDHC_IRQSTAT_AC12E_SHIFT                 (24U)
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   (0x10000000U)
+#define SDHC_IRQSTAT_DMAE_SHIFT                  (28U)
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
+
+/*! @name IRQSTATEN - Interrupt Status Enable register */
+#define SDHC_IRQSTATEN_CCSEN_MASK                (0x1U)
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               (0U)
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                (0x2U)
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               (1U)
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               (0x4U)
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              (2U)
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              (0x8U)
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             (3U)
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               (0x10U)
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              (4U)
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               (0x20U)
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              (5U)
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               (0x40U)
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              (6U)
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               (0x80U)
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              (7U)
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              (0x100U)
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             (8U)
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              (0x10000U)
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             (16U)
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               (0x20000U)
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              (17U)
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              (0x40000U)
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             (18U)
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               (0x80000U)
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              (19U)
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              (0x100000U)
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             (20U)
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               (0x200000U)
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              (21U)
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              (0x400000U)
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             (22U)
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             (0x1000000U)
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            (24U)
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              (0x10000000U)
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             (28U)
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
+
+/*! @name IRQSIGEN - Interrupt Signal Enable register */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 (0x1U)
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                (0U)
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 (0x2U)
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                (1U)
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                (0x4U)
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               (2U)
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               (0x8U)
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              (3U)
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                (0x10U)
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               (4U)
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                (0x20U)
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               (5U)
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               (0x40U)
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              (6U)
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                (0x80U)
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               (7U)
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               (0x100U)
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              (8U)
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               (0x10000U)
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              (16U)
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                (0x20000U)
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               (17U)
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               (0x40000U)
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              (18U)
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                (0x80000U)
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               (19U)
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               (0x100000U)
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              (20U)
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                (0x200000U)
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               (21U)
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               (0x400000U)
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              (22U)
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              (0x1000000U)
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             (24U)
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               (0x10000000U)
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              (28U)
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
+
+/*! @name AC12ERR - Auto CMD12 Error Status Register */
+#define SDHC_AC12ERR_AC12NE_MASK                 (0x1U)
+#define SDHC_AC12ERR_AC12NE_SHIFT                (0U)
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                (0x2U)
+#define SDHC_AC12ERR_AC12TOE_SHIFT               (1U)
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                (0x4U)
+#define SDHC_AC12ERR_AC12EBE_SHIFT               (2U)
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 (0x8U)
+#define SDHC_AC12ERR_AC12CE_SHIFT                (3U)
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 (0x10U)
+#define SDHC_AC12ERR_AC12IE_SHIFT                (4U)
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              (0x80U)
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             (7U)
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
+
+/*! @name HTCAPBLT - Host Controller Capabilities */
+#define SDHC_HTCAPBLT_MBL_MASK                   (0x70000U)
+#define SDHC_HTCAPBLT_MBL_SHIFT                  (16U)
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 (0x100000U)
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                (20U)
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   (0x200000U)
+#define SDHC_HTCAPBLT_HSS_SHIFT                  (21U)
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  (0x400000U)
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 (22U)
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   (0x800000U)
+#define SDHC_HTCAPBLT_SRS_SHIFT                  (23U)
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  (0x1000000U)
+#define SDHC_HTCAPBLT_VS33_SHIFT                 (24U)
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
+#define SDHC_HTCAPBLT_VS30_MASK                  (0x2000000U)
+#define SDHC_HTCAPBLT_VS30_SHIFT                 (25U)
+#define SDHC_HTCAPBLT_VS30(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS30_SHIFT)) & SDHC_HTCAPBLT_VS30_MASK)
+#define SDHC_HTCAPBLT_VS18_MASK                  (0x4000000U)
+#define SDHC_HTCAPBLT_VS18_SHIFT                 (26U)
+#define SDHC_HTCAPBLT_VS18(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS18_SHIFT)) & SDHC_HTCAPBLT_VS18_MASK)
+
+/*! @name WML - Watermark Level Register */
+#define SDHC_WML_RDWML_MASK                      (0xFFU)
+#define SDHC_WML_RDWML_SHIFT                     (0U)
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      (0xFF0000U)
+#define SDHC_WML_WRWML_SHIFT                     (16U)
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
+
+/*! @name FEVT - Force Event register */
+#define SDHC_FEVT_AC12NE_MASK                    (0x1U)
+#define SDHC_FEVT_AC12NE_SHIFT                   (0U)
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   (0x2U)
+#define SDHC_FEVT_AC12TOE_SHIFT                  (1U)
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    (0x4U)
+#define SDHC_FEVT_AC12CE_SHIFT                   (2U)
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   (0x8U)
+#define SDHC_FEVT_AC12EBE_SHIFT                  (3U)
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    (0x10U)
+#define SDHC_FEVT_AC12IE_SHIFT                   (4U)
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 (0x80U)
+#define SDHC_FEVT_CNIBAC12E_SHIFT                (7U)
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      (0x10000U)
+#define SDHC_FEVT_CTOE_SHIFT                     (16U)
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       (0x20000U)
+#define SDHC_FEVT_CCE_SHIFT                      (17U)
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      (0x40000U)
+#define SDHC_FEVT_CEBE_SHIFT                     (18U)
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       (0x80000U)
+#define SDHC_FEVT_CIE_SHIFT                      (19U)
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      (0x100000U)
+#define SDHC_FEVT_DTOE_SHIFT                     (20U)
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       (0x200000U)
+#define SDHC_FEVT_DCE_SHIFT                      (21U)
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      (0x400000U)
+#define SDHC_FEVT_DEBE_SHIFT                     (22U)
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     (0x1000000U)
+#define SDHC_FEVT_AC12E_SHIFT                    (24U)
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      (0x10000000U)
+#define SDHC_FEVT_DMAE_SHIFT                     (28U)
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      (0x80000000U)
+#define SDHC_FEVT_CINT_SHIFT                     (31U)
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
+
+/*! @name ADMAES - ADMA Error Status register */
+#define SDHC_ADMAES_ADMAES_MASK                  (0x3U)
+#define SDHC_ADMAES_ADMAES_SHIFT                 (0U)
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 (0x4U)
+#define SDHC_ADMAES_ADMALME_SHIFT                (2U)
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 (0x8U)
+#define SDHC_ADMAES_ADMADCE_SHIFT                (3U)
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
+
+/*! @name ADSADDR - ADMA System Addressregister */
+#define SDHC_ADSADDR_ADSADDR_MASK                (0xFFFFFFFCU)
+#define SDHC_ADSADDR_ADSADDR_SHIFT               (2U)
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
+
+/*! @name VENDOR - Vendor Specific register */
+#define SDHC_VENDOR_EXTDMAEN_MASK                (0x1U)
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               (0U)
+#define SDHC_VENDOR_EXTDMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK                 (0x2U)
+#define SDHC_VENDOR_EXBLKNU_SHIFT                (1U)
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                (0xFF0000U)
+#define SDHC_VENDOR_INTSTVAL_SHIFT               (16U)
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
+
+/*! @name MMCBOOT - MMC Boot register */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               (0xFU)
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              (0U)
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                (0x10U)
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               (4U)
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               (0x20U)
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              (5U)
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 (0x40U)
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                (6U)
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             (0x80U)
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            (7U)
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             (0xFFFF0000U)
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            (16U)
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+
+/*! @name HOSTVER - Host Controller Version */
+#define SDHC_HOSTVER_SVN_MASK                    (0xFFU)
+#define SDHC_HOSTVER_SVN_SHIFT                   (0U)
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    (0xFF00U)
+#define SDHC_HOSTVER_VVN_SHIFT                   (8U)
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
+
 
 /*!
  * @}
@@ -11607,7 +10088,6 @@ typedef struct {
 #define SDHC_BASE                                (0x400B1000u)
 /** Peripheral SDHC base pointer */
 #define SDHC                                     ((SDHC_Type *)SDHC_BASE)
-#define SDHC_BASE_PTR                            (SDHC)
 /** Array initializer of SDHC peripheral base addresses */
 #define SDHC_BASE_ADDRS                          { SDHC_BASE }
 /** Array initializer of SDHC peripheral base pointers */
@@ -11615,51 +10095,6 @@ typedef struct {
 /** Interrupt vectors for the SDHC peripheral type */
 #define SDHC_IRQS                                { SDHC_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- SDHC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
- * @{
- */
-
-
-/* SDHC - Register instance definitions */
-/* SDHC */
-#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
-#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
-#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
-#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
-#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
-#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
-#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
-#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
-#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
-#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
-#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
-#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
-#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
-#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
-#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
-#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
-#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
-#define SDHC_WML                                 SDHC_WML_REG(SDHC)
-#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
-#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
-#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
-#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
-#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
-#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
-
-/* SDHC - Register array accessors */
-#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
-
-/*!
- * @}
- */ /* end of group SDHC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group SDHC_Peripheral_Access_Layer */
@@ -11702,46 +10137,7 @@ typedef struct {
   __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
   __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
   __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type, *SIM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- SIM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register accessors */
-#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
-#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
-#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
-#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
-#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
-#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
-#define SIM_SDID_REG(base)                       ((base)->SDID)
-#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
-#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
-#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
-#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
-#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
-#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
-#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
-#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
-#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
-#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
-#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
-#define SIM_UIDH_REG(base)                       ((base)->UIDH)
-#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
-#define SIM_UIDML_REG(base)                      ((base)->UIDML)
-#define SIM_UIDL_REG(base)                       ((base)->UIDL)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
+} SIM_Type;
 
 /* ----------------------------------------------------------------------------
    -- SIM Register Masks
@@ -11752,280 +10148,380 @@ typedef struct {
  * @{
  */
 
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT                  12
-#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT                18
-#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT                 29
-#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT                 30
-#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT                 31
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT                  24
-#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
-#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT                 26
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
-#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
-#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_FBSL_MASK                      0x300u
-#define SIM_SOPT2_FBSL_SHIFT                     8
-#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
-#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
-#define SIM_SOPT2_PTD7PAD_SHIFT                  11
-#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
-#define SIM_SOPT2_PLLFLLSEL_MASK                 0x10000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
-#define SIM_SOPT2_USBSRC_MASK                    0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT                   18
-#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
-#define SIM_SOPT2_RMIISRC_SHIFT                  19
-#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
-#define SIM_SOPT2_TIMESRC_SHIFT                  20
-#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
-#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
-#define SIM_SOPT2_SDHCSRC_SHIFT                  28
-#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
-#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
-#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
-#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
-#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
-#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
-#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
-#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
-#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
-#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
-#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
-#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
-#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
-#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
-#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
-#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
-#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
-#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT               0
-#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT               2
-#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT               4
-#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT               6
-#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
-#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
-#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
-#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
-#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
-#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
-#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
-#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
-#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK                      0xFu
-#define SIM_SDID_PINID_SHIFT                     0
-#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK                      0x70u
-#define SIM_SDID_FAMID_SHIFT                     4
-#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_REVID_MASK                      0xF000u
-#define SIM_SDID_REVID_SHIFT                     12
-#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-/* SCGC1 Bit Fields */
-#define SIM_SCGC1_UART4_MASK                     0x400u
-#define SIM_SCGC1_UART4_SHIFT                    10
-#define SIM_SCGC1_UART5_MASK                     0x800u
-#define SIM_SCGC1_UART5_SHIFT                    11
-/* SCGC2 Bit Fields */
-#define SIM_SCGC2_ENET_MASK                      0x1u
-#define SIM_SCGC2_ENET_SHIFT                     0
-#define SIM_SCGC2_DAC0_MASK                      0x1000u
-#define SIM_SCGC2_DAC0_SHIFT                     12
-#define SIM_SCGC2_DAC1_MASK                      0x2000u
-#define SIM_SCGC2_DAC1_SHIFT                     13
-/* SCGC3 Bit Fields */
-#define SIM_SCGC3_RNGA_MASK                      0x1u
-#define SIM_SCGC3_RNGA_SHIFT                     0
-#define SIM_SCGC3_FLEXCAN1_MASK                  0x10u
-#define SIM_SCGC3_FLEXCAN1_SHIFT                 4
-#define SIM_SCGC3_SPI2_MASK                      0x1000u
-#define SIM_SCGC3_SPI2_SHIFT                     12
-#define SIM_SCGC3_SDHC_MASK                      0x20000u
-#define SIM_SCGC3_SDHC_SHIFT                     17
-#define SIM_SCGC3_FTM2_MASK                      0x1000000u
-#define SIM_SCGC3_FTM2_SHIFT                     24
-#define SIM_SCGC3_ADC1_MASK                      0x8000000u
-#define SIM_SCGC3_ADC1_SHIFT                     27
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK                       0x2u
-#define SIM_SCGC4_EWM_SHIFT                      1
-#define SIM_SCGC4_CMT_MASK                       0x4u
-#define SIM_SCGC4_CMT_SHIFT                      2
-#define SIM_SCGC4_I2C0_MASK                      0x40u
-#define SIM_SCGC4_I2C0_SHIFT                     6
-#define SIM_SCGC4_I2C1_MASK                      0x80u
-#define SIM_SCGC4_I2C1_SHIFT                     7
-#define SIM_SCGC4_UART0_MASK                     0x400u
-#define SIM_SCGC4_UART0_SHIFT                    10
-#define SIM_SCGC4_UART1_MASK                     0x800u
-#define SIM_SCGC4_UART1_SHIFT                    11
-#define SIM_SCGC4_UART2_MASK                     0x1000u
-#define SIM_SCGC4_UART2_SHIFT                    12
-#define SIM_SCGC4_UART3_MASK                     0x2000u
-#define SIM_SCGC4_UART3_SHIFT                    13
-#define SIM_SCGC4_USBOTG_MASK                    0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT                   18
-#define SIM_SCGC4_CMP_MASK                       0x80000u
-#define SIM_SCGC4_CMP_SHIFT                      19
-#define SIM_SCGC4_VREF_MASK                      0x100000u
-#define SIM_SCGC4_VREF_SHIFT                     20
-#define SIM_SCGC4_LLWU_MASK                      0x10000000u
-#define SIM_SCGC4_LLWU_SHIFT                     28
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTIMER_MASK                   0x1u
-#define SIM_SCGC5_LPTIMER_SHIFT                  0
-#define SIM_SCGC5_TSI_MASK                       0x20u
-#define SIM_SCGC5_TSI_SHIFT                      5
-#define SIM_SCGC5_PORTA_MASK                     0x200u
-#define SIM_SCGC5_PORTA_SHIFT                    9
-#define SIM_SCGC5_PORTB_MASK                     0x400u
-#define SIM_SCGC5_PORTB_SHIFT                    10
-#define SIM_SCGC5_PORTC_MASK                     0x800u
-#define SIM_SCGC5_PORTC_SHIFT                    11
-#define SIM_SCGC5_PORTD_MASK                     0x1000u
-#define SIM_SCGC5_PORTD_SHIFT                    12
-#define SIM_SCGC5_PORTE_MASK                     0x2000u
-#define SIM_SCGC5_PORTE_SHIFT                    13
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTFL_MASK                      0x1u
-#define SIM_SCGC6_FTFL_SHIFT                     0
-#define SIM_SCGC6_DMAMUX_MASK                    0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT                   1
-#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
-#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
-#define SIM_SCGC6_SPI0_MASK                      0x1000u
-#define SIM_SCGC6_SPI0_SHIFT                     12
-#define SIM_SCGC6_SPI1_MASK                      0x2000u
-#define SIM_SCGC6_SPI1_SHIFT                     13
-#define SIM_SCGC6_I2S_MASK                       0x8000u
-#define SIM_SCGC6_I2S_SHIFT                      15
-#define SIM_SCGC6_CRC_MASK                       0x40000u
-#define SIM_SCGC6_CRC_SHIFT                      18
-#define SIM_SCGC6_USBDCD_MASK                    0x200000u
-#define SIM_SCGC6_USBDCD_SHIFT                   21
-#define SIM_SCGC6_PDB_MASK                       0x400000u
-#define SIM_SCGC6_PDB_SHIFT                      22
-#define SIM_SCGC6_PIT_MASK                       0x800000u
-#define SIM_SCGC6_PIT_SHIFT                      23
-#define SIM_SCGC6_FTM0_MASK                      0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT                     24
-#define SIM_SCGC6_FTM1_MASK                      0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT                     25
-#define SIM_SCGC6_ADC0_MASK                      0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT                     27
-#define SIM_SCGC6_RTC_MASK                       0x20000000u
-#define SIM_SCGC6_RTC_SHIFT                      29
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
-#define SIM_SCGC7_FLEXBUS_SHIFT                  0
-#define SIM_SCGC7_DMA_MASK                       0x2u
-#define SIM_SCGC7_DMA_SHIFT                      1
-#define SIM_SCGC7_MPU_MASK                       0x4u
-#define SIM_SCGC7_MPU_SHIFT                      2
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
-#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
-#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
-#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
-#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
-#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT                0
-#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT                 1
-#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT                 0
-#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT                1
-#define SIM_FCFG1_DEPART_MASK                    0xF00u
-#define SIM_FCFG1_DEPART_SHIFT                   8
-#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
-#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
-#define SIM_FCFG1_EESIZE_SHIFT                   16
-#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
-#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT                   24
-#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
-#define SIM_FCFG1_NVMSIZE_SHIFT                  28
-#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT                 16
-#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_PFLSH_MASK                     0x800000u
-#define SIM_FCFG2_PFLSH_SHIFT                    23
-#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT                 24
-#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-#define SIM_FCFG2_SWAPPFLSH_MASK                 0x80000000u
-#define SIM_FCFG2_SWAPPFLSH_SHIFT                31
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT                       0
-#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT                      0
-#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT                      0
-#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT                       0
-#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK                   (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT                  (12U)
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT                 (29U)
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT                 (30U)
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT                 (31U)
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE_MASK                   (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT                  (24U)
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 (25U)
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT                 (26U)
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                (5U)
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      (0x300U)
+#define SIM_SOPT2_FBSL_SHIFT                     (8U)
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   (0x800U)
+#define SIM_SOPT2_PTD7PAD_SHIFT                  (11U)
+#define SIM_SOPT2_PTD7PAD(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               (0x1000U)
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              (12U)
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 (0x10000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                (16U)
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT                   (18U)
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_RMIISRC_MASK                   (0x80000U)
+#define SIM_SOPT2_RMIISRC_SHIFT                  (19U)
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   (0x300000U)
+#define SIM_SOPT2_TIMESRC_SHIFT                  (20U)
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   (0x30000000U)
+#define SIM_SOPT2_SDHCSRC_SHIFT                  (28U)
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_FTM0FLT0_MASK                  (0x1U)
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 (0U)
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  (0x2U)
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 (1U)
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  (0x4U)
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 (2U)
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  (0x10U)
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 (4U)
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  (0x100U)
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 (8U)
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               (18U)
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                (0x300000U)
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               (20U)
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                (0x1000000U)
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               (24U)
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                (0x2000000U)
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               (25U)
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                (0x4000000U)
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               (26U)
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               (0x10000000U)
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              (28U)
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               (0x20000000U)
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              (29U)
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK                (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT               (0U)
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT               (2U)
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT               (4U)
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT               (6U)
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                (0xF00U)
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               (8U)
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             (0x1000U)
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            (12U)
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              (0x8000U)
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             (15U)
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK                      (0xFU)
+#define SIM_SDID_PINID_SHIFT                     (0U)
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      (0x70U)
+#define SIM_SDID_FAMID_SHIFT                     (4U)
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_REVID_MASK                      (0xF000U)
+#define SIM_SDID_REVID_SHIFT                     (12U)
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+
+/*! @name SCGC1 - System Clock Gating Control Register 1 */
+#define SIM_SCGC1_UART4_MASK                     (0x400U)
+#define SIM_SCGC1_UART4_SHIFT                    (10U)
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK                     (0x800U)
+#define SIM_SCGC1_UART5_SHIFT                    (11U)
+#define SIM_SCGC1_UART5(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
+
+/*! @name SCGC2 - System Clock Gating Control Register 2 */
+#define SIM_SCGC2_ENET_MASK                      (0x1U)
+#define SIM_SCGC2_ENET_SHIFT                     (0U)
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_DAC0_MASK                      (0x1000U)
+#define SIM_SCGC2_DAC0_SHIFT                     (12U)
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      (0x2000U)
+#define SIM_SCGC2_DAC1_SHIFT                     (13U)
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
+
+/*! @name SCGC3 - System Clock Gating Control Register 3 */
+#define SIM_SCGC3_RNGA_MASK                      (0x1U)
+#define SIM_SCGC3_RNGA_SHIFT                     (0U)
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_FLEXCAN1_MASK                  (0x10U)
+#define SIM_SCGC3_FLEXCAN1_SHIFT                 (4U)
+#define SIM_SCGC3_FLEXCAN1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
+#define SIM_SCGC3_SPI2_MASK                      (0x1000U)
+#define SIM_SCGC3_SPI2_SHIFT                     (12U)
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      (0x20000U)
+#define SIM_SCGC3_SDHC_SHIFT                     (17U)
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      (0x1000000U)
+#define SIM_SCGC3_FTM2_SHIFT                     (24U)
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_ADC1_MASK                      (0x8000000U)
+#define SIM_SCGC3_ADC1_SHIFT                     (27U)
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM_MASK                       (0x2U)
+#define SIM_SCGC4_EWM_SHIFT                      (1U)
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       (0x4U)
+#define SIM_SCGC4_CMT_SHIFT                      (2U)
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT                     (6U)
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT                     (7U)
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     (0x400U)
+#define SIM_SCGC4_UART0_SHIFT                    (10U)
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     (0x800U)
+#define SIM_SCGC4_UART1_SHIFT                    (11U)
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT                    (12U)
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     (0x2000U)
+#define SIM_SCGC4_UART3_SHIFT                    (13U)
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT                   (18U)
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT                      (19U)
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT                     (20U)
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+#define SIM_SCGC4_LLWU_MASK                      (0x10000000U)
+#define SIM_SCGC4_LLWU_SHIFT                     (28U)
+#define SIM_SCGC4_LLWU(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_LLWU_SHIFT)) & SIM_SCGC4_LLWU_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTIMER_MASK                   (0x1U)
+#define SIM_SCGC5_LPTIMER_SHIFT                  (0U)
+#define SIM_SCGC5_LPTIMER(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTIMER_SHIFT)) & SIM_SCGC5_LPTIMER_MASK)
+#define SIM_SCGC5_TSI_MASK                       (0x20U)
+#define SIM_SCGC5_TSI_SHIFT                      (5U)
+#define SIM_SCGC5_TSI(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_PORTA_MASK                     (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT                    (9U)
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT                    (10U)
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT                    (11U)
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT                    (12U)
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT                    (13U)
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTFL_MASK                      (0x1U)
+#define SIM_SCGC6_FTFL_SHIFT                     (0U)
+#define SIM_SCGC6_FTFL(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT                   (1U)
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  (0x10U)
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 (4U)
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_SPI0_MASK                      (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT                     (12U)
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      (0x2000U)
+#define SIM_SCGC6_SPI1_SHIFT                     (13U)
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT                      (15U)
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT                      (18U)
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    (0x200000U)
+#define SIM_SCGC6_USBDCD_SHIFT                   (21U)
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       (0x400000U)
+#define SIM_SCGC6_PDB_SHIFT                      (22U)
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT                      (23U)
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      (0x1000000U)
+#define SIM_SCGC6_FTM0_SHIFT                     (24U)
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      (0x2000000U)
+#define SIM_SCGC6_FTM1_SHIFT                     (25U)
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_ADC0_MASK                      (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT                     (27U)
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT                      (29U)
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_FLEXBUS_MASK                   (0x1U)
+#define SIM_SCGC7_FLEXBUS_SHIFT                  (0U)
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       (0x2U)
+#define SIM_SCGC7_DMA_SHIFT                      (1U)
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       (0x4U)
+#define SIM_SCGC7_MPU_SHIFT                      (2U)
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                (16U)
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 (0xF00000U)
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                (20U)
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                (24U)
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                (28U)
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC_MASK                 (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT                (0U)
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT                 (1U)
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    (0xF00U)
+#define SIM_FCFG1_DEPART_SHIFT                   (8U)
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    (0xF0000U)
+#define SIM_FCFG1_EESIZE_SHIFT                   (16U)
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   (0xF0000000U)
+#define SIM_FCFG1_NVMSIZE_SHIFT                  (28U)
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK                  (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT                 (16U)
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     (0x800000U)
+#define SIM_FCFG2_PFLSH_SHIFT                    (23U)
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+#define SIM_FCFG2_SWAPPFLSH_MASK                 (0x80000000U)
+#define SIM_FCFG2_SWAPPFLSH_SHIFT                (31U)
+#define SIM_FCFG2_SWAPPFLSH(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
+
+/*! @name UIDH - Unique Identification Register High */
+#define SIM_UIDH_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT                       (0U)
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK                       (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT                      (0U)
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK                       (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT                      (0U)
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT                       (0U)
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
 
 /*!
  * @}
@@ -12036,52 +10532,11 @@ typedef struct {
 /** Peripheral SIM base address */
 #define SIM_BASE                                 (0x40047000u)
 /** Peripheral SIM base pointer */
-#define SIM                                      ((SIM_Type *)SIM_BASE)
-#define SIM_BASE_PTR                             (SIM)
-/** Array initializer of SIM peripheral base addresses */
-#define SIM_BASE_ADDRS                           { SIM_BASE }
-/** Array initializer of SIM peripheral base pointers */
-#define SIM_BASE_PTRS                            { SIM }
-
-/* ----------------------------------------------------------------------------
-   -- SIM - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register instance definitions */
-/* SIM */
-#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
-#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
-#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
-#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
-#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
-#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
-#define SIM_SDID                                 SIM_SDID_REG(SIM)
-#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
-#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
-#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
-#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
-#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
-#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
-#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
-#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
-#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
-#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
-#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
-#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
-#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
-#define SIM_UIDML                                SIM_UIDML_REG(SIM)
-#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
 
 /*!
  * @}
@@ -12103,28 +10558,7 @@ typedef struct {
   __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
   __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
   __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type, *SMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- SMC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register accessors */
-#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
-#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
-#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
-#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
+} SMC_Type;
 
 /* ----------------------------------------------------------------------------
    -- SMC Register Masks
@@ -12135,34 +10569,44 @@ typedef struct {
  * @{
  */
 
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK                    0x2u
-#define SMC_PMPROT_AVLLS_SHIFT                   1
-#define SMC_PMPROT_ALLS_MASK                     0x8u
-#define SMC_PMPROT_ALLS_SHIFT                    3
-#define SMC_PMPROT_AVLP_MASK                     0x20u
-#define SMC_PMPROT_AVLP_SHIFT                    5
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK                    0x7u
-#define SMC_PMCTRL_STOPM_SHIFT                   0
-#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK                    0x8u
-#define SMC_PMCTRL_STOPA_SHIFT                   3
-#define SMC_PMCTRL_RUNM_MASK                     0x60u
-#define SMC_PMCTRL_RUNM_SHIFT                    5
-#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-#define SMC_PMCTRL_LPWUI_MASK                    0x80u
-#define SMC_PMCTRL_LPWUI_SHIFT                   7
-/* VLLSCTRL Bit Fields */
-#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
-#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
-#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
-#define SMC_VLLSCTRL_RAM2PO_MASK                 0x10u
-#define SMC_VLLSCTRL_RAM2PO_SHIFT                4
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
-#define SMC_PMSTAT_PMSTAT_SHIFT                  0
-#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK                    (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT                   (1U)
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT                    (3U)
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT                    (5U)
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK                    (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT                   (0U)
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT                   (3U)
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT                    (5U)
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    (0x80U)
+#define SMC_PMCTRL_LPWUI_SHIFT                   (7U)
+#define SMC_PMCTRL_LPWUI(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
+
+/*! @name VLLSCTRL - VLLS Control register */
+#define SMC_VLLSCTRL_VLLSM_MASK                  (0x7U)
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 (0U)
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_RAM2PO_MASK                 (0x10U)
+#define SMC_VLLSCTRL_RAM2PO_SHIFT                (4U)
+#define SMC_VLLSCTRL_RAM2PO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_RAM2PO_SHIFT)) & SMC_VLLSCTRL_RAM2PO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK                   (0x7FU)
+#define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
 
 /*!
  * @}
@@ -12174,34 +10618,11 @@ typedef struct {
 #define SMC_BASE                                 (0x4007E000u)
 /** Peripheral SMC base pointer */
 #define SMC                                      ((SMC_Type *)SMC_BASE)
-#define SMC_BASE_PTR                             (SMC)
 /** Array initializer of SMC peripheral base addresses */
 #define SMC_BASE_ADDRS                           { SMC_BASE }
 /** Array initializer of SMC peripheral base pointers */
 #define SMC_BASE_PTRS                            { SMC }
 
-/* ----------------------------------------------------------------------------
-   -- SMC - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register instance definitions */
-/* SMC */
-#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
-#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
-#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
-#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group SMC_Peripheral_Access_Layer */
@@ -12242,41 +10663,7 @@ typedef struct {
   __I  uint32_t RXFR1;                             /**< DSPI Receive FIFO Registers, offset: 0x80 */
   __I  uint32_t RXFR2;                             /**< DSPI Receive FIFO Registers, offset: 0x84 */
   __I  uint32_t RXFR3;                             /**< DSPI Receive FIFO Registers, offset: 0x88 */
-} SPI_Type, *SPI_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- SPI - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register accessors */
-#define SPI_MCR_REG(base)                        ((base)->MCR)
-#define SPI_TCR_REG(base)                        ((base)->TCR)
-#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
-#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
-#define SPI_SR_REG(base)                         ((base)->SR)
-#define SPI_RSER_REG(base)                       ((base)->RSER)
-#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
-#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
-#define SPI_POPR_REG(base)                       ((base)->POPR)
-#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
-#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
-#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
-#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
-#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
-#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
-#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
-#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
+} SPI_Type;
 
 /* ----------------------------------------------------------------------------
    -- SPI Register Masks
@@ -12287,202 +10674,262 @@ typedef struct {
  * @{
  */
 
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK                        0x1u
-#define SPI_MCR_HALT_SHIFT                       0
-#define SPI_MCR_SMPL_PT_MASK                     0x300u
-#define SPI_MCR_SMPL_PT_SHIFT                    8
-#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK                     0x400u
-#define SPI_MCR_CLR_RXF_SHIFT                    10
-#define SPI_MCR_CLR_TXF_MASK                     0x800u
-#define SPI_MCR_CLR_TXF_SHIFT                    11
-#define SPI_MCR_DIS_RXF_MASK                     0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT                    12
-#define SPI_MCR_DIS_TXF_MASK                     0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT                    13
-#define SPI_MCR_MDIS_MASK                        0x4000u
-#define SPI_MCR_MDIS_SHIFT                       14
-#define SPI_MCR_DOZE_MASK                        0x8000u
-#define SPI_MCR_DOZE_SHIFT                       15
-#define SPI_MCR_PCSIS_MASK                       0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT                      16
-#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK                        0x1000000u
-#define SPI_MCR_ROOE_SHIFT                       24
-#define SPI_MCR_PCSSE_MASK                       0x2000000u
-#define SPI_MCR_PCSSE_SHIFT                      25
-#define SPI_MCR_MTFE_MASK                        0x4000000u
-#define SPI_MCR_MTFE_SHIFT                       26
-#define SPI_MCR_FRZ_MASK                         0x8000000u
-#define SPI_MCR_FRZ_SHIFT                        27
-#define SPI_MCR_DCONF_MASK                       0x30000000u
-#define SPI_MCR_DCONF_SHIFT                      28
-#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT                  30
-#define SPI_MCR_MSTR_MASK                        0x80000000u
-#define SPI_MCR_MSTR_SHIFT                       31
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT                   16
-#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK                         0xFu
-#define SPI_CTAR_BR_SHIFT                        0
-#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK                         0xF0u
-#define SPI_CTAR_DT_SHIFT                        4
-#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK                        0xF00u
-#define SPI_CTAR_ASC_SHIFT                       8
-#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK                      0xF000u
-#define SPI_CTAR_CSSCK_SHIFT                     12
-#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK                        0x30000u
-#define SPI_CTAR_PBR_SHIFT                       16
-#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK                        0xC0000u
-#define SPI_CTAR_PDT_SHIFT                       18
-#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK                       0x300000u
-#define SPI_CTAR_PASC_SHIFT                      20
-#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT                    22
-#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK                      0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT                     24
-#define SPI_CTAR_CPHA_MASK                       0x2000000u
-#define SPI_CTAR_CPHA_SHIFT                      25
-#define SPI_CTAR_CPOL_MASK                       0x4000000u
-#define SPI_CTAR_CPOL_SHIFT                      26
-#define SPI_CTAR_FMSZ_MASK                       0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT                      27
-#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK                        0x80000000u
-#define SPI_CTAR_DBR_SHIFT                       31
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
-#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
-#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
-#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK                    0xFu
-#define SPI_SR_POPNXTPTR_SHIFT                   0
-#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK                        0xF0u
-#define SPI_SR_RXCTR_SHIFT                       4
-#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK                     0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT                    8
-#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK                        0xF000u
-#define SPI_SR_TXCTR_SHIFT                       12
-#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK                         0x20000u
-#define SPI_SR_RFDF_SHIFT                        17
-#define SPI_SR_RFOF_MASK                         0x80000u
-#define SPI_SR_RFOF_SHIFT                        19
-#define SPI_SR_TFFF_MASK                         0x2000000u
-#define SPI_SR_TFFF_SHIFT                        25
-#define SPI_SR_TFUF_MASK                         0x8000000u
-#define SPI_SR_TFUF_SHIFT                        27
-#define SPI_SR_EOQF_MASK                         0x10000000u
-#define SPI_SR_EOQF_SHIFT                        28
-#define SPI_SR_TXRXS_MASK                        0x40000000u
-#define SPI_SR_TXRXS_SHIFT                       30
-#define SPI_SR_TCF_MASK                          0x80000000u
-#define SPI_SR_TCF_SHIFT                         31
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT                 16
-#define SPI_RSER_RFDF_RE_MASK                    0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT                   17
-#define SPI_RSER_RFOF_RE_MASK                    0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT                   19
-#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT                 24
-#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT                   25
-#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT                   27
-#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT                   28
-#define SPI_RSER_TCF_RE_MASK                     0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT                    31
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT                   0
-#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK                       0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT                      16
-#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT                    26
-#define SPI_PUSHR_EOQ_MASK                       0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT                      27
-#define SPI_PUSHR_CTAS_MASK                      0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT                     28
-#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK                      0x80000000u
-#define SPI_PUSHR_CONT_SHIFT                     31
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
-#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT                    0
-#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT                   0
-#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
-#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT                   0
-#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
-#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT                   0
-#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
-#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT                   0
-#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
-#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT                   0
-#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT                   0
-#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT                   0
-#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT                   0
-#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+/*! @name MCR - Module Configuration Register */
+#define SPI_MCR_HALT_MASK                        (0x1U)
+#define SPI_MCR_HALT_SHIFT                       (0U)
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT                    (8U)
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT                    (10U)
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT                    (11U)
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT                    (12U)
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT                    (13U)
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        (0x4000U)
+#define SPI_MCR_MDIS_SHIFT                       (14U)
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        (0x8000U)
+#define SPI_MCR_DOZE_SHIFT                       (15U)
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT                      (16U)
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT                       (24U)
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT                      (25U)
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT                       (26U)
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT                        (27U)
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT                      (28U)
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT                  (30U)
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT                       (31U)
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+
+/*! @name TCR - Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK                    (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT                   (16U)
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - DSPI Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK                         (0xFU)
+#define SPI_CTAR_BR_SHIFT                        (0U)
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         (0xF0U)
+#define SPI_CTAR_DT_SHIFT                        (4U)
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        (0xF00U)
+#define SPI_CTAR_ASC_SHIFT                       (8U)
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT                     (12U)
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        (0x30000U)
+#define SPI_CTAR_PBR_SHIFT                       (16U)
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT                       (18U)
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       (0x300000U)
+#define SPI_CTAR_PASC_SHIFT                      (20U)
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT                    (22U)
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT                     (24U)
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT                      (25U)
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT                      (26U)
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT                      (27U)
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT                       (31U)
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT                           (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                (25U)
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                (26U)
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 (0xF8000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT                     (1U)
+
+/*! @name SR - DSPI Status Register */
+#define SPI_SR_POPNXTPTR_MASK                    (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT                   (0U)
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        (0xF0U)
+#define SPI_SR_RXCTR_SHIFT                       (4U)
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT                    (8U)
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        (0xF000U)
+#define SPI_SR_TXCTR_SHIFT                       (12U)
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         (0x20000U)
+#define SPI_SR_RFDF_SHIFT                        (17U)
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         (0x80000U)
+#define SPI_SR_RFOF_SHIFT                        (19U)
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         (0x2000000U)
+#define SPI_SR_TFFF_SHIFT                        (25U)
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         (0x8000000U)
+#define SPI_SR_TFUF_SHIFT                        (27U)
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         (0x10000000U)
+#define SPI_SR_EOQF_SHIFT                        (28U)
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT                       (30U)
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          (0x80000000U)
+#define SPI_SR_TCF_SHIFT                         (31U)
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS_MASK                  (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT                 (16U)
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT                   (17U)
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT                   (19U)
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT                 (24U)
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT                   (25U)
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT                   (27U)
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT                   (28U)
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT                    (31U)
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK                    (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT                   (0U)
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT                      (16U)
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT                    (26U)
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT                      (27U)
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT                     (28U)
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT                     (31U)
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+
+/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              (0xFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+
+/*! @name POPR - POP RX FIFO Register */
+#define SPI_POPR_RXDATA_MASK                     (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT                    (0U)
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+
+/*! @name TXFR0 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*! @name RXFR0 - DSPI Receive FIFO Registers */
+#define SPI_RXFR0_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+
+/*! @name RXFR1 - DSPI Receive FIFO Registers */
+#define SPI_RXFR1_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+
+/*! @name RXFR2 - DSPI Receive FIFO Registers */
+#define SPI_RXFR2_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+
+/*! @name RXFR3 - DSPI Receive FIFO Registers */
+#define SPI_RXFR3_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+
 
 /*!
  * @}
@@ -12494,17 +10941,14 @@ typedef struct {
 #define SPI0_BASE                                (0x4002C000u)
 /** Peripheral SPI0 base pointer */
 #define SPI0                                     ((SPI_Type *)SPI0_BASE)
-#define SPI0_BASE_PTR                            (SPI0)
 /** Peripheral SPI1 base address */
 #define SPI1_BASE                                (0x4002D000u)
 /** Peripheral SPI1 base pointer */
 #define SPI1                                     ((SPI_Type *)SPI1_BASE)
-#define SPI1_BASE_PTR                            (SPI1)
 /** Peripheral SPI2 base address */
 #define SPI2_BASE                                (0x400AC000u)
 /** Peripheral SPI2 base pointer */
 #define SPI2                                     ((SPI_Type *)SPI2_BASE)
-#define SPI2_BASE_PTR                            (SPI2)
 /** Array initializer of SPI peripheral base addresses */
 #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
 /** Array initializer of SPI peripheral base pointers */
@@ -12512,91 +10956,222 @@ typedef struct {
 /** Interrupt vectors for the SPI peripheral type */
 #define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
 
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
 /* ----------------------------------------------------------------------------
-   -- SPI - Register accessor macros
+   -- SYSMPU Peripheral Access Layer
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
  * @{
  */
 
-
-/* SPI - Register instance definitions */
-/* SPI0 */
-#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
-#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
-#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
-#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
-#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
-#define SPI0_SR                                  SPI_SR_REG(SPI0)
-#define SPI0_RSER                                SPI_RSER_REG(SPI0)
-#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
-#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
-#define SPI0_POPR                                SPI_POPR_REG(SPI0)
-#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
-#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
-#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
-#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
-#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
-#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
-#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
-#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
-/* SPI1 */
-#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
-#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
-#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
-#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
-#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
-#define SPI1_SR                                  SPI_SR_REG(SPI1)
-#define SPI1_RSER                                SPI_RSER_REG(SPI1)
-#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
-#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
-#define SPI1_POPR                                SPI_POPR_REG(SPI1)
-#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
-#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
-#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
-#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
-#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
-#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
-#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
-#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
-/* SPI2 */
-#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
-#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
-#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
-#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
-#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
-#define SPI2_SR                                  SPI_SR_REG(SPI2)
-#define SPI2_RSER                                SPI_RSER_REG(SPI2)
-#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
-#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
-#define SPI2_POPR                                SPI_POPR_REG(SPI2)
-#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
-#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
-#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
-#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
-#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
-#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
-#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
-#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
-
-/* SPI - Register array accessors */
-#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
-#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
-#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
-#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
-#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
-#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
+/** SYSMPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} SYSMPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSMPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+#define SYSMPU_CESR_VLD_MASK                     (0x1U)
+#define SYSMPU_CESR_VLD_SHIFT                    (0U)
+#define SYSMPU_CESR_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_NRGD_MASK                    (0xF00U)
+#define SYSMPU_CESR_NRGD_SHIFT                   (8U)
+#define SYSMPU_CESR_NRGD(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NSP_MASK                     (0xF000U)
+#define SYSMPU_CESR_NSP_SHIFT                    (12U)
+#define SYSMPU_CESR_NSP(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_HRL_MASK                     (0xF0000U)
+#define SYSMPU_CESR_HRL_SHIFT                    (16U)
+#define SYSMPU_CESR_HRL(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_SPERR_MASK                   (0xF8000000U)
+#define SYSMPU_CESR_SPERR_SHIFT                  (27U)
+#define SYSMPU_CESR_SPERR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+
+/*! @name EAR - Error Address Register, slave port n */
+#define SYSMPU_EAR_EADDR_MASK                    (0xFFFFFFFFU)
+#define SYSMPU_EAR_EADDR_SHIFT                   (0U)
+#define SYSMPU_EAR_EADDR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+
+/* The count of SYSMPU_EAR */
+#define SYSMPU_EAR_COUNT                         (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+#define SYSMPU_EDR_ERW_MASK                      (0x1U)
+#define SYSMPU_EDR_ERW_SHIFT                     (0U)
+#define SYSMPU_EDR_ERW(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_EATTR_MASK                    (0xEU)
+#define SYSMPU_EDR_EATTR_SHIFT                   (1U)
+#define SYSMPU_EDR_EATTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EMN_MASK                      (0xF0U)
+#define SYSMPU_EDR_EMN_SHIFT                     (4U)
+#define SYSMPU_EDR_EMN(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EACD_MASK                     (0xFFFF0000U)
+#define SYSMPU_EDR_EACD_SHIFT                    (16U)
+#define SYSMPU_EDR_EACD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+
+/* The count of SYSMPU_EDR */
+#define SYSMPU_EDR_COUNT                         (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+#define SYSMPU_WORD_M0UM_MASK                    (0x7U)
+#define SYSMPU_WORD_M0UM_SHIFT                   (0U)
+#define SYSMPU_WORD_M0UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_VLD_MASK                     (0x1U)
+#define SYSMPU_WORD_VLD_SHIFT                    (0U)
+#define SYSMPU_WORD_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_M0SM_MASK                    (0x18U)
+#define SYSMPU_WORD_M0SM_SHIFT                   (3U)
+#define SYSMPU_WORD_M0SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_ENDADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_ENDADDR_SHIFT                (5U)
+#define SYSMPU_WORD_ENDADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_SRTADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_SRTADDR_SHIFT                (5U)
+#define SYSMPU_WORD_SRTADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_M1UM_MASK                    (0x1C0U)
+#define SYSMPU_WORD_M1UM_SHIFT                   (6U)
+#define SYSMPU_WORD_M1UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1SM_MASK                    (0x600U)
+#define SYSMPU_WORD_M1SM_SHIFT                   (9U)
+#define SYSMPU_WORD_M1SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M2UM_MASK                    (0x7000U)
+#define SYSMPU_WORD_M2UM_SHIFT                   (12U)
+#define SYSMPU_WORD_M2UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2SM_MASK                    (0x18000U)
+#define SYSMPU_WORD_M2SM_SHIFT                   (15U)
+#define SYSMPU_WORD_M2SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_M3UM_MASK                    (0x1C0000U)
+#define SYSMPU_WORD_M3UM_SHIFT                   (18U)
+#define SYSMPU_WORD_M3UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3SM_MASK                    (0x600000U)
+#define SYSMPU_WORD_M3SM_SHIFT                   (21U)
+#define SYSMPU_WORD_M3SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M4WE_MASK                    (0x1000000U)
+#define SYSMPU_WORD_M4WE_SHIFT                   (24U)
+#define SYSMPU_WORD_M4WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_M4RE_MASK                    (0x2000000U)
+#define SYSMPU_WORD_M4RE_SHIFT                   (25U)
+#define SYSMPU_WORD_M4RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M5WE_MASK                    (0x4000000U)
+#define SYSMPU_WORD_M5WE_SHIFT                   (26U)
+#define SYSMPU_WORD_M5WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5RE_MASK                    (0x8000000U)
+#define SYSMPU_WORD_M5RE_SHIFT                   (27U)
+#define SYSMPU_WORD_M5RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M6WE_MASK                    (0x10000000U)
+#define SYSMPU_WORD_M6WE_SHIFT                   (28U)
+#define SYSMPU_WORD_M6WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6RE_MASK                    (0x20000000U)
+#define SYSMPU_WORD_M6RE_SHIFT                   (29U)
+#define SYSMPU_WORD_M6RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M7WE_MASK                    (0x40000000U)
+#define SYSMPU_WORD_M7WE_SHIFT                   (30U)
+#define SYSMPU_WORD_M7WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7RE_MASK                    (0x80000000U)
+#define SYSMPU_WORD_M7RE_SHIFT                   (31U)
+#define SYSMPU_WORD_M7RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT                        (12U)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT2                       (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+#define SYSMPU_RGDAAC_M0UM_MASK                  (0x7U)
+#define SYSMPU_RGDAAC_M0UM_SHIFT                 (0U)
+#define SYSMPU_RGDAAC_M0UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0SM_MASK                  (0x18U)
+#define SYSMPU_RGDAAC_M0SM_SHIFT                 (3U)
+#define SYSMPU_RGDAAC_M0SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M1UM_MASK                  (0x1C0U)
+#define SYSMPU_RGDAAC_M1UM_SHIFT                 (6U)
+#define SYSMPU_RGDAAC_M1UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1SM_MASK                  (0x600U)
+#define SYSMPU_RGDAAC_M1SM_SHIFT                 (9U)
+#define SYSMPU_RGDAAC_M1SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M2UM_MASK                  (0x7000U)
+#define SYSMPU_RGDAAC_M2UM_SHIFT                 (12U)
+#define SYSMPU_RGDAAC_M2UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2SM_MASK                  (0x18000U)
+#define SYSMPU_RGDAAC_M2SM_SHIFT                 (15U)
+#define SYSMPU_RGDAAC_M2SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M3UM_MASK                  (0x1C0000U)
+#define SYSMPU_RGDAAC_M3UM_SHIFT                 (18U)
+#define SYSMPU_RGDAAC_M3UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3SM_MASK                  (0x600000U)
+#define SYSMPU_RGDAAC_M3SM_SHIFT                 (21U)
+#define SYSMPU_RGDAAC_M3SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M4WE_MASK                  (0x1000000U)
+#define SYSMPU_RGDAAC_M4WE_SHIFT                 (24U)
+#define SYSMPU_RGDAAC_M4WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4RE_MASK                  (0x2000000U)
+#define SYSMPU_RGDAAC_M4RE_SHIFT                 (25U)
+#define SYSMPU_RGDAAC_M4RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M5WE_MASK                  (0x4000000U)
+#define SYSMPU_RGDAAC_M5WE_SHIFT                 (26U)
+#define SYSMPU_RGDAAC_M5WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5RE_MASK                  (0x8000000U)
+#define SYSMPU_RGDAAC_M5RE_SHIFT                 (27U)
+#define SYSMPU_RGDAAC_M5RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M6WE_MASK                  (0x10000000U)
+#define SYSMPU_RGDAAC_M6WE_SHIFT                 (28U)
+#define SYSMPU_RGDAAC_M6WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6RE_MASK                  (0x20000000U)
+#define SYSMPU_RGDAAC_M6RE_SHIFT                 (29U)
+#define SYSMPU_RGDAAC_M6RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M7WE_MASK                  (0x40000000U)
+#define SYSMPU_RGDAAC_M7WE_SHIFT                 (30U)
+#define SYSMPU_RGDAAC_M7WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7RE_MASK                  (0x80000000U)
+#define SYSMPU_RGDAAC_M7RE_SHIFT                 (31U)
+#define SYSMPU_RGDAAC_M7RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+
+/* The count of SYSMPU_RGDAAC */
+#define SYSMPU_RGDAAC_COUNT                      (12U)
+
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Register_Masks */
+
+
+/* SYSMPU - Peripheral instance base addresses */
+/** Peripheral SYSMPU base address */
+#define SYSMPU_BASE                              (0x4000D000u)
+/** Peripheral SYSMPU base pointer */
+#define SYSMPU                                   ((SYSMPU_Type *)SYSMPU_BASE)
+/** Array initializer of SYSMPU peripheral base addresses */
+#define SYSMPU_BASE_ADDRS                        { SYSMPU_BASE }
+/** Array initializer of SYSMPU peripheral base pointers */
+#define SYSMPU_BASE_PTRS                         { SYSMPU }
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Peripheral_Access_Layer */
 
 
 /* ----------------------------------------------------------------------------
@@ -12624,37 +11199,7 @@ typedef struct {
   __I  uint32_t CNTR13;                            /**< Counter Register, offset: 0x118 */
   __I  uint32_t CNTR15;                            /**< Counter Register, offset: 0x11C */
   __IO uint32_t THRESHOLD;                         /**< Low-Power Channel Threshold register, offset: 0x120 */
-} TSI_Type, *TSI_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- TSI - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
- * @{
- */
-
-
-/* TSI - Register accessors */
-#define TSI_GENCS_REG(base)                      ((base)->GENCS)
-#define TSI_SCANC_REG(base)                      ((base)->SCANC)
-#define TSI_PEN_REG(base)                        ((base)->PEN)
-#define TSI_WUCNTR_REG(base)                     ((base)->WUCNTR)
-#define TSI_CNTR1_REG(base)                      ((base)->CNTR1)
-#define TSI_CNTR3_REG(base)                      ((base)->CNTR3)
-#define TSI_CNTR5_REG(base)                      ((base)->CNTR5)
-#define TSI_CNTR7_REG(base)                      ((base)->CNTR7)
-#define TSI_CNTR9_REG(base)                      ((base)->CNTR9)
-#define TSI_CNTR11_REG(base)                     ((base)->CNTR11)
-#define TSI_CNTR13_REG(base)                     ((base)->CNTR13)
-#define TSI_CNTR15_REG(base)                     ((base)->CNTR15)
-#define TSI_THRESHOLD_REG(base)                  ((base)->THRESHOLD)
-
-/*!
- * @}
- */ /* end of group TSI_Register_Accessor_Macros */
-
+} TSI_Type;
 
 /* ----------------------------------------------------------------------------
    -- TSI Register Masks
@@ -12665,161 +11210,203 @@ typedef struct {
  * @{
  */
 
-/* GENCS Bit Fields */
-#define TSI_GENCS_STPE_MASK                      0x1u
-#define TSI_GENCS_STPE_SHIFT                     0
-#define TSI_GENCS_STM_MASK                       0x2u
-#define TSI_GENCS_STM_SHIFT                      1
-#define TSI_GENCS_ESOR_MASK                      0x10u
-#define TSI_GENCS_ESOR_SHIFT                     4
-#define TSI_GENCS_ERIE_MASK                      0x20u
-#define TSI_GENCS_ERIE_SHIFT                     5
-#define TSI_GENCS_TSIIE_MASK                     0x40u
-#define TSI_GENCS_TSIIE_SHIFT                    6
-#define TSI_GENCS_TSIEN_MASK                     0x80u
-#define TSI_GENCS_TSIEN_SHIFT                    7
-#define TSI_GENCS_SWTS_MASK                      0x100u
-#define TSI_GENCS_SWTS_SHIFT                     8
-#define TSI_GENCS_SCNIP_MASK                     0x200u
-#define TSI_GENCS_SCNIP_SHIFT                    9
-#define TSI_GENCS_OVRF_MASK                      0x1000u
-#define TSI_GENCS_OVRF_SHIFT                     12
-#define TSI_GENCS_EXTERF_MASK                    0x2000u
-#define TSI_GENCS_EXTERF_SHIFT                   13
-#define TSI_GENCS_OUTRGF_MASK                    0x4000u
-#define TSI_GENCS_OUTRGF_SHIFT                   14
-#define TSI_GENCS_EOSF_MASK                      0x8000u
-#define TSI_GENCS_EOSF_SHIFT                     15
-#define TSI_GENCS_PS_MASK                        0x70000u
-#define TSI_GENCS_PS_SHIFT                       16
-#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
-#define TSI_GENCS_NSCN_MASK                      0xF80000u
-#define TSI_GENCS_NSCN_SHIFT                     19
-#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
-#define TSI_GENCS_LPSCNITV_MASK                  0xF000000u
-#define TSI_GENCS_LPSCNITV_SHIFT                 24
-#define TSI_GENCS_LPSCNITV(x)                    (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
-#define TSI_GENCS_LPCLKS_MASK                    0x10000000u
-#define TSI_GENCS_LPCLKS_SHIFT                   28
-/* SCANC Bit Fields */
-#define TSI_SCANC_AMPSC_MASK                     0x7u
-#define TSI_SCANC_AMPSC_SHIFT                    0
-#define TSI_SCANC_AMPSC(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
-#define TSI_SCANC_AMCLKS_MASK                    0x18u
-#define TSI_SCANC_AMCLKS_SHIFT                   3
-#define TSI_SCANC_AMCLKS(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
-#define TSI_SCANC_SMOD_MASK                      0xFF00u
-#define TSI_SCANC_SMOD_SHIFT                     8
-#define TSI_SCANC_SMOD(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
-#define TSI_SCANC_EXTCHRG_MASK                   0xF0000u
-#define TSI_SCANC_EXTCHRG_SHIFT                  16
-#define TSI_SCANC_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
-#define TSI_SCANC_REFCHRG_MASK                   0xF000000u
-#define TSI_SCANC_REFCHRG_SHIFT                  24
-#define TSI_SCANC_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
-/* PEN Bit Fields */
-#define TSI_PEN_PEN0_MASK                        0x1u
-#define TSI_PEN_PEN0_SHIFT                       0
-#define TSI_PEN_PEN1_MASK                        0x2u
-#define TSI_PEN_PEN1_SHIFT                       1
-#define TSI_PEN_PEN2_MASK                        0x4u
-#define TSI_PEN_PEN2_SHIFT                       2
-#define TSI_PEN_PEN3_MASK                        0x8u
-#define TSI_PEN_PEN3_SHIFT                       3
-#define TSI_PEN_PEN4_MASK                        0x10u
-#define TSI_PEN_PEN4_SHIFT                       4
-#define TSI_PEN_PEN5_MASK                        0x20u
-#define TSI_PEN_PEN5_SHIFT                       5
-#define TSI_PEN_PEN6_MASK                        0x40u
-#define TSI_PEN_PEN6_SHIFT                       6
-#define TSI_PEN_PEN7_MASK                        0x80u
-#define TSI_PEN_PEN7_SHIFT                       7
-#define TSI_PEN_PEN8_MASK                        0x100u
-#define TSI_PEN_PEN8_SHIFT                       8
-#define TSI_PEN_PEN9_MASK                        0x200u
-#define TSI_PEN_PEN9_SHIFT                       9
-#define TSI_PEN_PEN10_MASK                       0x400u
-#define TSI_PEN_PEN10_SHIFT                      10
-#define TSI_PEN_PEN11_MASK                       0x800u
-#define TSI_PEN_PEN11_SHIFT                      11
-#define TSI_PEN_PEN12_MASK                       0x1000u
-#define TSI_PEN_PEN12_SHIFT                      12
-#define TSI_PEN_PEN13_MASK                       0x2000u
-#define TSI_PEN_PEN13_SHIFT                      13
-#define TSI_PEN_PEN14_MASK                       0x4000u
-#define TSI_PEN_PEN14_SHIFT                      14
-#define TSI_PEN_PEN15_MASK                       0x8000u
-#define TSI_PEN_PEN15_SHIFT                      15
-#define TSI_PEN_LPSP_MASK                        0xF0000u
-#define TSI_PEN_LPSP_SHIFT                       16
-#define TSI_PEN_LPSP(x)                          (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
-/* WUCNTR Bit Fields */
-#define TSI_WUCNTR_WUCNT_MASK                    0xFFFFu
-#define TSI_WUCNTR_WUCNT_SHIFT                   0
-#define TSI_WUCNTR_WUCNT(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
-/* CNTR1 Bit Fields */
-#define TSI_CNTR1_CTN1_MASK                      0xFFFFu
-#define TSI_CNTR1_CTN1_SHIFT                     0
-#define TSI_CNTR1_CTN1(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
-#define TSI_CNTR1_CTN_MASK                       0xFFFF0000u
-#define TSI_CNTR1_CTN_SHIFT                      16
-#define TSI_CNTR1_CTN(x)                         (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
-/* CNTR3 Bit Fields */
-#define TSI_CNTR3_CTN1_MASK                      0xFFFFu
-#define TSI_CNTR3_CTN1_SHIFT                     0
-#define TSI_CNTR3_CTN1(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
-#define TSI_CNTR3_CTN_MASK                       0xFFFF0000u
-#define TSI_CNTR3_CTN_SHIFT                      16
-#define TSI_CNTR3_CTN(x)                         (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
-/* CNTR5 Bit Fields */
-#define TSI_CNTR5_CTN1_MASK                      0xFFFFu
-#define TSI_CNTR5_CTN1_SHIFT                     0
-#define TSI_CNTR5_CTN1(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
-#define TSI_CNTR5_CTN_MASK                       0xFFFF0000u
-#define TSI_CNTR5_CTN_SHIFT                      16
-#define TSI_CNTR5_CTN(x)                         (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
-/* CNTR7 Bit Fields */
-#define TSI_CNTR7_CTN1_MASK                      0xFFFFu
-#define TSI_CNTR7_CTN1_SHIFT                     0
-#define TSI_CNTR7_CTN1(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
-#define TSI_CNTR7_CTN_MASK                       0xFFFF0000u
-#define TSI_CNTR7_CTN_SHIFT                      16
-#define TSI_CNTR7_CTN(x)                         (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
-/* CNTR9 Bit Fields */
-#define TSI_CNTR9_CTN1_MASK                      0xFFFFu
-#define TSI_CNTR9_CTN1_SHIFT                     0
-#define TSI_CNTR9_CTN1(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
-#define TSI_CNTR9_CTN_MASK                       0xFFFF0000u
-#define TSI_CNTR9_CTN_SHIFT                      16
-#define TSI_CNTR9_CTN(x)                         (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
-/* CNTR11 Bit Fields */
-#define TSI_CNTR11_CTN1_MASK                     0xFFFFu
-#define TSI_CNTR11_CTN1_SHIFT                    0
-#define TSI_CNTR11_CTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
-#define TSI_CNTR11_CTN_MASK                      0xFFFF0000u
-#define TSI_CNTR11_CTN_SHIFT                     16
-#define TSI_CNTR11_CTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
-/* CNTR13 Bit Fields */
-#define TSI_CNTR13_CTN1_MASK                     0xFFFFu
-#define TSI_CNTR13_CTN1_SHIFT                    0
-#define TSI_CNTR13_CTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
-#define TSI_CNTR13_CTN_MASK                      0xFFFF0000u
-#define TSI_CNTR13_CTN_SHIFT                     16
-#define TSI_CNTR13_CTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
-/* CNTR15 Bit Fields */
-#define TSI_CNTR15_CTN1_MASK                     0xFFFFu
-#define TSI_CNTR15_CTN1_SHIFT                    0
-#define TSI_CNTR15_CTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
-#define TSI_CNTR15_CTN_MASK                      0xFFFF0000u
-#define TSI_CNTR15_CTN_SHIFT                     16
-#define TSI_CNTR15_CTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
-/* THRESHOLD Bit Fields */
-#define TSI_THRESHOLD_HTHH_MASK                  0xFFFFu
-#define TSI_THRESHOLD_HTHH_SHIFT                 0
-#define TSI_THRESHOLD_HTHH(x)                    (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
-#define TSI_THRESHOLD_LTHH_MASK                  0xFFFF0000u
-#define TSI_THRESHOLD_LTHH_SHIFT                 16
-#define TSI_THRESHOLD_LTHH(x)                    (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
+/*! @name GENCS - General Control and Status register */
+#define TSI_GENCS_STPE_MASK                      (0x1U)
+#define TSI_GENCS_STPE_SHIFT                     (0U)
+#define TSI_GENCS_STPE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_STM_MASK                       (0x2U)
+#define TSI_GENCS_STM_SHIFT                      (1U)
+#define TSI_GENCS_STM(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_ESOR_MASK                      (0x10U)
+#define TSI_GENCS_ESOR_SHIFT                     (4U)
+#define TSI_GENCS_ESOR(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_ERIE_MASK                      (0x20U)
+#define TSI_GENCS_ERIE_SHIFT                     (5U)
+#define TSI_GENCS_ERIE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ERIE_SHIFT)) & TSI_GENCS_ERIE_MASK)
+#define TSI_GENCS_TSIIE_MASK                     (0x40U)
+#define TSI_GENCS_TSIIE_SHIFT                    (6U)
+#define TSI_GENCS_TSIIE(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIE_SHIFT)) & TSI_GENCS_TSIIE_MASK)
+#define TSI_GENCS_TSIEN_MASK                     (0x80U)
+#define TSI_GENCS_TSIEN_SHIFT                    (7U)
+#define TSI_GENCS_TSIEN(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_SWTS_MASK                      (0x100U)
+#define TSI_GENCS_SWTS_SHIFT                     (8U)
+#define TSI_GENCS_SWTS(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK)
+#define TSI_GENCS_SCNIP_MASK                     (0x200U)
+#define TSI_GENCS_SCNIP_SHIFT                    (9U)
+#define TSI_GENCS_SCNIP(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_OVRF_MASK                      (0x1000U)
+#define TSI_GENCS_OVRF_SHIFT                     (12U)
+#define TSI_GENCS_OVRF(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OVRF_SHIFT)) & TSI_GENCS_OVRF_MASK)
+#define TSI_GENCS_EXTERF_MASK                    (0x2000U)
+#define TSI_GENCS_EXTERF_SHIFT                   (13U)
+#define TSI_GENCS_EXTERF(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTERF_SHIFT)) & TSI_GENCS_EXTERF_MASK)
+#define TSI_GENCS_OUTRGF_MASK                    (0x4000U)
+#define TSI_GENCS_OUTRGF_SHIFT                   (14U)
+#define TSI_GENCS_OUTRGF(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+#define TSI_GENCS_EOSF_MASK                      (0x8000U)
+#define TSI_GENCS_EOSF_SHIFT                     (15U)
+#define TSI_GENCS_EOSF(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_PS_MASK                        (0x70000U)
+#define TSI_GENCS_PS_SHIFT                       (16U)
+#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_NSCN_MASK                      (0xF80000U)
+#define TSI_GENCS_NSCN_SHIFT                     (19U)
+#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_LPSCNITV_MASK                  (0xF000000U)
+#define TSI_GENCS_LPSCNITV_SHIFT                 (24U)
+#define TSI_GENCS_LPSCNITV(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPSCNITV_SHIFT)) & TSI_GENCS_LPSCNITV_MASK)
+#define TSI_GENCS_LPCLKS_MASK                    (0x10000000U)
+#define TSI_GENCS_LPCLKS_SHIFT                   (28U)
+#define TSI_GENCS_LPCLKS(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPCLKS_SHIFT)) & TSI_GENCS_LPCLKS_MASK)
+
+/*! @name SCANC - SCAN Control register */
+#define TSI_SCANC_AMPSC_MASK                     (0x7U)
+#define TSI_SCANC_AMPSC_SHIFT                    (0U)
+#define TSI_SCANC_AMPSC(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMPSC_SHIFT)) & TSI_SCANC_AMPSC_MASK)
+#define TSI_SCANC_AMCLKS_MASK                    (0x18U)
+#define TSI_SCANC_AMCLKS_SHIFT                   (3U)
+#define TSI_SCANC_AMCLKS(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMCLKS_SHIFT)) & TSI_SCANC_AMCLKS_MASK)
+#define TSI_SCANC_SMOD_MASK                      (0xFF00U)
+#define TSI_SCANC_SMOD_SHIFT                     (8U)
+#define TSI_SCANC_SMOD(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_SMOD_SHIFT)) & TSI_SCANC_SMOD_MASK)
+#define TSI_SCANC_EXTCHRG_MASK                   (0xF0000U)
+#define TSI_SCANC_EXTCHRG_SHIFT                  (16U)
+#define TSI_SCANC_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_EXTCHRG_SHIFT)) & TSI_SCANC_EXTCHRG_MASK)
+#define TSI_SCANC_REFCHRG_MASK                   (0xF000000U)
+#define TSI_SCANC_REFCHRG_SHIFT                  (24U)
+#define TSI_SCANC_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_REFCHRG_SHIFT)) & TSI_SCANC_REFCHRG_MASK)
+
+/*! @name PEN - Pin Enable register */
+#define TSI_PEN_PEN0_MASK                        (0x1U)
+#define TSI_PEN_PEN0_SHIFT                       (0U)
+#define TSI_PEN_PEN0(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN0_SHIFT)) & TSI_PEN_PEN0_MASK)
+#define TSI_PEN_PEN1_MASK                        (0x2U)
+#define TSI_PEN_PEN1_SHIFT                       (1U)
+#define TSI_PEN_PEN1(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN1_SHIFT)) & TSI_PEN_PEN1_MASK)
+#define TSI_PEN_PEN2_MASK                        (0x4U)
+#define TSI_PEN_PEN2_SHIFT                       (2U)
+#define TSI_PEN_PEN2(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN2_SHIFT)) & TSI_PEN_PEN2_MASK)
+#define TSI_PEN_PEN3_MASK                        (0x8U)
+#define TSI_PEN_PEN3_SHIFT                       (3U)
+#define TSI_PEN_PEN3(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN3_SHIFT)) & TSI_PEN_PEN3_MASK)
+#define TSI_PEN_PEN4_MASK                        (0x10U)
+#define TSI_PEN_PEN4_SHIFT                       (4U)
+#define TSI_PEN_PEN4(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN4_SHIFT)) & TSI_PEN_PEN4_MASK)
+#define TSI_PEN_PEN5_MASK                        (0x20U)
+#define TSI_PEN_PEN5_SHIFT                       (5U)
+#define TSI_PEN_PEN5(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN5_SHIFT)) & TSI_PEN_PEN5_MASK)
+#define TSI_PEN_PEN6_MASK                        (0x40U)
+#define TSI_PEN_PEN6_SHIFT                       (6U)
+#define TSI_PEN_PEN6(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN6_SHIFT)) & TSI_PEN_PEN6_MASK)
+#define TSI_PEN_PEN7_MASK                        (0x80U)
+#define TSI_PEN_PEN7_SHIFT                       (7U)
+#define TSI_PEN_PEN7(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN7_SHIFT)) & TSI_PEN_PEN7_MASK)
+#define TSI_PEN_PEN8_MASK                        (0x100U)
+#define TSI_PEN_PEN8_SHIFT                       (8U)
+#define TSI_PEN_PEN8(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN8_SHIFT)) & TSI_PEN_PEN8_MASK)
+#define TSI_PEN_PEN9_MASK                        (0x200U)
+#define TSI_PEN_PEN9_SHIFT                       (9U)
+#define TSI_PEN_PEN9(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN9_SHIFT)) & TSI_PEN_PEN9_MASK)
+#define TSI_PEN_PEN10_MASK                       (0x400U)
+#define TSI_PEN_PEN10_SHIFT                      (10U)
+#define TSI_PEN_PEN10(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN10_SHIFT)) & TSI_PEN_PEN10_MASK)
+#define TSI_PEN_PEN11_MASK                       (0x800U)
+#define TSI_PEN_PEN11_SHIFT                      (11U)
+#define TSI_PEN_PEN11(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN11_SHIFT)) & TSI_PEN_PEN11_MASK)
+#define TSI_PEN_PEN12_MASK                       (0x1000U)
+#define TSI_PEN_PEN12_SHIFT                      (12U)
+#define TSI_PEN_PEN12(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN12_SHIFT)) & TSI_PEN_PEN12_MASK)
+#define TSI_PEN_PEN13_MASK                       (0x2000U)
+#define TSI_PEN_PEN13_SHIFT                      (13U)
+#define TSI_PEN_PEN13(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN13_SHIFT)) & TSI_PEN_PEN13_MASK)
+#define TSI_PEN_PEN14_MASK                       (0x4000U)
+#define TSI_PEN_PEN14_SHIFT                      (14U)
+#define TSI_PEN_PEN14(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN14_SHIFT)) & TSI_PEN_PEN14_MASK)
+#define TSI_PEN_PEN15_MASK                       (0x8000U)
+#define TSI_PEN_PEN15_SHIFT                      (15U)
+#define TSI_PEN_PEN15(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN15_SHIFT)) & TSI_PEN_PEN15_MASK)
+#define TSI_PEN_LPSP_MASK                        (0xF0000U)
+#define TSI_PEN_LPSP_SHIFT                       (16U)
+#define TSI_PEN_LPSP(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_PEN_LPSP_SHIFT)) & TSI_PEN_LPSP_MASK)
+
+/*! @name WUCNTR - Wake-Up Channel Counter Register */
+#define TSI_WUCNTR_WUCNT_MASK                    (0xFFFFU)
+#define TSI_WUCNTR_WUCNT_SHIFT                   (0U)
+#define TSI_WUCNTR_WUCNT(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_WUCNTR_WUCNT_SHIFT)) & TSI_WUCNTR_WUCNT_MASK)
+
+/*! @name CNTR1 - Counter Register */
+#define TSI_CNTR1_CTN1_MASK                      (0xFFFFU)
+#define TSI_CNTR1_CTN1_SHIFT                     (0U)
+#define TSI_CNTR1_CTN1(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN1_SHIFT)) & TSI_CNTR1_CTN1_MASK)
+#define TSI_CNTR1_CTN_MASK                       (0xFFFF0000U)
+#define TSI_CNTR1_CTN_SHIFT                      (16U)
+#define TSI_CNTR1_CTN(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN_SHIFT)) & TSI_CNTR1_CTN_MASK)
+
+/*! @name CNTR3 - Counter Register */
+#define TSI_CNTR3_CTN1_MASK                      (0xFFFFU)
+#define TSI_CNTR3_CTN1_SHIFT                     (0U)
+#define TSI_CNTR3_CTN1(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN1_SHIFT)) & TSI_CNTR3_CTN1_MASK)
+#define TSI_CNTR3_CTN_MASK                       (0xFFFF0000U)
+#define TSI_CNTR3_CTN_SHIFT                      (16U)
+#define TSI_CNTR3_CTN(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN_SHIFT)) & TSI_CNTR3_CTN_MASK)
+
+/*! @name CNTR5 - Counter Register */
+#define TSI_CNTR5_CTN1_MASK                      (0xFFFFU)
+#define TSI_CNTR5_CTN1_SHIFT                     (0U)
+#define TSI_CNTR5_CTN1(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN1_SHIFT)) & TSI_CNTR5_CTN1_MASK)
+#define TSI_CNTR5_CTN_MASK                       (0xFFFF0000U)
+#define TSI_CNTR5_CTN_SHIFT                      (16U)
+#define TSI_CNTR5_CTN(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN_SHIFT)) & TSI_CNTR5_CTN_MASK)
+
+/*! @name CNTR7 - Counter Register */
+#define TSI_CNTR7_CTN1_MASK                      (0xFFFFU)
+#define TSI_CNTR7_CTN1_SHIFT                     (0U)
+#define TSI_CNTR7_CTN1(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN1_SHIFT)) & TSI_CNTR7_CTN1_MASK)
+#define TSI_CNTR7_CTN_MASK                       (0xFFFF0000U)
+#define TSI_CNTR7_CTN_SHIFT                      (16U)
+#define TSI_CNTR7_CTN(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN_SHIFT)) & TSI_CNTR7_CTN_MASK)
+
+/*! @name CNTR9 - Counter Register */
+#define TSI_CNTR9_CTN1_MASK                      (0xFFFFU)
+#define TSI_CNTR9_CTN1_SHIFT                     (0U)
+#define TSI_CNTR9_CTN1(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN1_SHIFT)) & TSI_CNTR9_CTN1_MASK)
+#define TSI_CNTR9_CTN_MASK                       (0xFFFF0000U)
+#define TSI_CNTR9_CTN_SHIFT                      (16U)
+#define TSI_CNTR9_CTN(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN_SHIFT)) & TSI_CNTR9_CTN_MASK)
+
+/*! @name CNTR11 - Counter Register */
+#define TSI_CNTR11_CTN1_MASK                     (0xFFFFU)
+#define TSI_CNTR11_CTN1_SHIFT                    (0U)
+#define TSI_CNTR11_CTN1(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN1_SHIFT)) & TSI_CNTR11_CTN1_MASK)
+#define TSI_CNTR11_CTN_MASK                      (0xFFFF0000U)
+#define TSI_CNTR11_CTN_SHIFT                     (16U)
+#define TSI_CNTR11_CTN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN_SHIFT)) & TSI_CNTR11_CTN_MASK)
+
+/*! @name CNTR13 - Counter Register */
+#define TSI_CNTR13_CTN1_MASK                     (0xFFFFU)
+#define TSI_CNTR13_CTN1_SHIFT                    (0U)
+#define TSI_CNTR13_CTN1(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN1_SHIFT)) & TSI_CNTR13_CTN1_MASK)
+#define TSI_CNTR13_CTN_MASK                      (0xFFFF0000U)
+#define TSI_CNTR13_CTN_SHIFT                     (16U)
+#define TSI_CNTR13_CTN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN_SHIFT)) & TSI_CNTR13_CTN_MASK)
+
+/*! @name CNTR15 - Counter Register */
+#define TSI_CNTR15_CTN1_MASK                     (0xFFFFU)
+#define TSI_CNTR15_CTN1_SHIFT                    (0U)
+#define TSI_CNTR15_CTN1(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN1_SHIFT)) & TSI_CNTR15_CTN1_MASK)
+#define TSI_CNTR15_CTN_MASK                      (0xFFFF0000U)
+#define TSI_CNTR15_CTN_SHIFT                     (16U)
+#define TSI_CNTR15_CTN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN_SHIFT)) & TSI_CNTR15_CTN_MASK)
+
+/*! @name THRESHOLD - Low-Power Channel Threshold register */
+#define TSI_THRESHOLD_HTHH_MASK                  (0xFFFFU)
+#define TSI_THRESHOLD_HTHH_SHIFT                 (0U)
+#define TSI_THRESHOLD_HTHH(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_HTHH_SHIFT)) & TSI_THRESHOLD_HTHH_MASK)
+#define TSI_THRESHOLD_LTHH_MASK                  (0xFFFF0000U)
+#define TSI_THRESHOLD_LTHH_SHIFT                 (16U)
+#define TSI_THRESHOLD_LTHH(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_LTHH_SHIFT)) & TSI_THRESHOLD_LTHH_MASK)
+
 
 /*!
  * @}
@@ -12831,7 +11418,6 @@ typedef struct {
 #define TSI0_BASE                                (0x40045000u)
 /** Peripheral TSI0 base pointer */
 #define TSI0                                     ((TSI_Type *)TSI0_BASE)
-#define TSI0_BASE_PTR                            (TSI0)
 /** Array initializer of TSI peripheral base addresses */
 #define TSI_BASE_ADDRS                           { TSI0_BASE }
 /** Array initializer of TSI peripheral base pointers */
@@ -12839,37 +11425,6 @@ typedef struct {
 /** Interrupt vectors for the TSI peripheral type */
 #define TSI_IRQS                                 { TSI0_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- TSI - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
- * @{
- */
-
-
-/* TSI - Register instance definitions */
-/* TSI0 */
-#define TSI0_GENCS                               TSI_GENCS_REG(TSI0)
-#define TSI0_SCANC                               TSI_SCANC_REG(TSI0)
-#define TSI0_PEN                                 TSI_PEN_REG(TSI0)
-#define TSI0_WUCNTR                              TSI_WUCNTR_REG(TSI0)
-#define TSI0_CNTR1                               TSI_CNTR1_REG(TSI0)
-#define TSI0_CNTR3                               TSI_CNTR3_REG(TSI0)
-#define TSI0_CNTR5                               TSI_CNTR5_REG(TSI0)
-#define TSI0_CNTR7                               TSI_CNTR7_REG(TSI0)
-#define TSI0_CNTR9                               TSI_CNTR9_REG(TSI0)
-#define TSI0_CNTR11                              TSI_CNTR11_REG(TSI0)
-#define TSI0_CNTR13                              TSI_CNTR13_REG(TSI0)
-#define TSI0_CNTR15                              TSI_CNTR15_REG(TSI0)
-#define TSI0_THRESHOLD                           TSI_THRESHOLD_REG(TSI0)
-
-/*!
- * @}
- */ /* end of group TSI_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group TSI_Peripheral_Access_Layer */
@@ -12939,72 +11494,7 @@ typedef struct {
   __IO uint8_t CPW;                                /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
   __IO uint8_t RIDT;                               /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
   __IO uint8_t TIDT;                               /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
-} UART_Type, *UART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- UART - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register accessors */
-#define UART_BDH_REG(base)                       ((base)->BDH)
-#define UART_BDL_REG(base)                       ((base)->BDL)
-#define UART_C1_REG(base)                        ((base)->C1)
-#define UART_C2_REG(base)                        ((base)->C2)
-#define UART_S1_REG(base)                        ((base)->S1)
-#define UART_S2_REG(base)                        ((base)->S2)
-#define UART_C3_REG(base)                        ((base)->C3)
-#define UART_D_REG(base)                         ((base)->D)
-#define UART_MA1_REG(base)                       ((base)->MA1)
-#define UART_MA2_REG(base)                       ((base)->MA2)
-#define UART_C4_REG(base)                        ((base)->C4)
-#define UART_C5_REG(base)                        ((base)->C5)
-#define UART_ED_REG(base)                        ((base)->ED)
-#define UART_MODEM_REG(base)                     ((base)->MODEM)
-#define UART_IR_REG(base)                        ((base)->IR)
-#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
-#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
-#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
-#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
-#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
-#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
-#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
-#define UART_C7816_REG(base)                     ((base)->C7816)
-#define UART_IE7816_REG(base)                    ((base)->IE7816)
-#define UART_IS7816_REG(base)                    ((base)->IS7816)
-#define UART_WP7816T0_REG(base)                  ((base)->WP7816T0)
-#define UART_WP7816T1_REG(base)                  ((base)->WP7816T1)
-#define UART_WN7816_REG(base)                    ((base)->WN7816)
-#define UART_WF7816_REG(base)                    ((base)->WF7816)
-#define UART_ET7816_REG(base)                    ((base)->ET7816)
-#define UART_TL7816_REG(base)                    ((base)->TL7816)
-#define UART_C6_REG(base)                        ((base)->C6)
-#define UART_PCTH_REG(base)                      ((base)->PCTH)
-#define UART_PCTL_REG(base)                      ((base)->PCTL)
-#define UART_B1T_REG(base)                       ((base)->B1T)
-#define UART_SDTH_REG(base)                      ((base)->SDTH)
-#define UART_SDTL_REG(base)                      ((base)->SDTL)
-#define UART_PRE_REG(base)                       ((base)->PRE)
-#define UART_TPL_REG(base)                       ((base)->TPL)
-#define UART_IE_REG(base)                        ((base)->IE)
-#define UART_WB_REG(base)                        ((base)->WB)
-#define UART_S3_REG(base)                        ((base)->S3)
-#define UART_S4_REG(base)                        ((base)->S4)
-#define UART_RPL_REG(base)                       ((base)->RPL)
-#define UART_RPREL_REG(base)                     ((base)->RPREL)
-#define UART_CPW_REG(base)                       ((base)->CPW)
-#define UART_RIDT_REG(base)                      ((base)->RIDT)
-#define UART_TIDT_REG(base)                      ((base)->TIDT)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
+} UART_Type;
 
 /* ----------------------------------------------------------------------------
    -- UART Register Masks
@@ -13015,373 +11505,528 @@ typedef struct {
  * @{
  */
 
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK                        0x1Fu
-#define UART_BDH_SBR_SHIFT                       0
-#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_RXEDGIE_MASK                    0x40u
-#define UART_BDH_RXEDGIE_SHIFT                   6
-#define UART_BDH_LBKDIE_MASK                     0x80u
-#define UART_BDH_LBKDIE_SHIFT                    7
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK                        0xFFu
-#define UART_BDL_SBR_SHIFT                       0
-#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK                          0x1u
-#define UART_C1_PT_SHIFT                         0
-#define UART_C1_PE_MASK                          0x2u
-#define UART_C1_PE_SHIFT                         1
-#define UART_C1_ILT_MASK                         0x4u
-#define UART_C1_ILT_SHIFT                        2
-#define UART_C1_WAKE_MASK                        0x8u
-#define UART_C1_WAKE_SHIFT                       3
-#define UART_C1_M_MASK                           0x10u
-#define UART_C1_M_SHIFT                          4
-#define UART_C1_RSRC_MASK                        0x20u
-#define UART_C1_RSRC_SHIFT                       5
-#define UART_C1_UARTSWAI_MASK                    0x40u
-#define UART_C1_UARTSWAI_SHIFT                   6
-#define UART_C1_LOOPS_MASK                       0x80u
-#define UART_C1_LOOPS_SHIFT                      7
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK                         0x1u
-#define UART_C2_SBK_SHIFT                        0
-#define UART_C2_RWU_MASK                         0x2u
-#define UART_C2_RWU_SHIFT                        1
-#define UART_C2_RE_MASK                          0x4u
-#define UART_C2_RE_SHIFT                         2
-#define UART_C2_TE_MASK                          0x8u
-#define UART_C2_TE_SHIFT                         3
-#define UART_C2_ILIE_MASK                        0x10u
-#define UART_C2_ILIE_SHIFT                       4
-#define UART_C2_RIE_MASK                         0x20u
-#define UART_C2_RIE_SHIFT                        5
-#define UART_C2_TCIE_MASK                        0x40u
-#define UART_C2_TCIE_SHIFT                       6
-#define UART_C2_TIE_MASK                         0x80u
-#define UART_C2_TIE_SHIFT                        7
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK                          0x1u
-#define UART_S1_PF_SHIFT                         0
-#define UART_S1_FE_MASK                          0x2u
-#define UART_S1_FE_SHIFT                         1
-#define UART_S1_NF_MASK                          0x4u
-#define UART_S1_NF_SHIFT                         2
-#define UART_S1_OR_MASK                          0x8u
-#define UART_S1_OR_SHIFT                         3
-#define UART_S1_IDLE_MASK                        0x10u
-#define UART_S1_IDLE_SHIFT                       4
-#define UART_S1_RDRF_MASK                        0x20u
-#define UART_S1_RDRF_SHIFT                       5
-#define UART_S1_TC_MASK                          0x40u
-#define UART_S1_TC_SHIFT                         6
-#define UART_S1_TDRE_MASK                        0x80u
-#define UART_S1_TDRE_SHIFT                       7
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK                         0x1u
-#define UART_S2_RAF_SHIFT                        0
-#define UART_S2_LBKDE_MASK                       0x2u
-#define UART_S2_LBKDE_SHIFT                      1
-#define UART_S2_BRK13_MASK                       0x4u
-#define UART_S2_BRK13_SHIFT                      2
-#define UART_S2_RWUID_MASK                       0x8u
-#define UART_S2_RWUID_SHIFT                      3
-#define UART_S2_RXINV_MASK                       0x10u
-#define UART_S2_RXINV_SHIFT                      4
-#define UART_S2_MSBF_MASK                        0x20u
-#define UART_S2_MSBF_SHIFT                       5
-#define UART_S2_RXEDGIF_MASK                     0x40u
-#define UART_S2_RXEDGIF_SHIFT                    6
-#define UART_S2_LBKDIF_MASK                      0x80u
-#define UART_S2_LBKDIF_SHIFT                     7
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK                        0x1u
-#define UART_C3_PEIE_SHIFT                       0
-#define UART_C3_FEIE_MASK                        0x2u
-#define UART_C3_FEIE_SHIFT                       1
-#define UART_C3_NEIE_MASK                        0x4u
-#define UART_C3_NEIE_SHIFT                       2
-#define UART_C3_ORIE_MASK                        0x8u
-#define UART_C3_ORIE_SHIFT                       3
-#define UART_C3_TXINV_MASK                       0x10u
-#define UART_C3_TXINV_SHIFT                      4
-#define UART_C3_TXDIR_MASK                       0x20u
-#define UART_C3_TXDIR_SHIFT                      5
-#define UART_C3_T8_MASK                          0x40u
-#define UART_C3_T8_SHIFT                         6
-#define UART_C3_R8_MASK                          0x80u
-#define UART_C3_R8_SHIFT                         7
-/* D Bit Fields */
-#define UART_D_RT_MASK                           0xFFu
-#define UART_D_RT_SHIFT                          0
-#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK                         0xFFu
-#define UART_MA1_MA_SHIFT                        0
-#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK                         0xFFu
-#define UART_MA2_MA_SHIFT                        0
-#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK                        0x1Fu
-#define UART_C4_BRFA_SHIFT                       0
-#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK                         0x20u
-#define UART_C4_M10_SHIFT                        5
-#define UART_C4_MAEN2_MASK                       0x40u
-#define UART_C4_MAEN2_SHIFT                      6
-#define UART_C4_MAEN1_MASK                       0x80u
-#define UART_C4_MAEN1_SHIFT                      7
-/* C5 Bit Fields */
-#define UART_C5_RDMAS_MASK                       0x20u
-#define UART_C5_RDMAS_SHIFT                      5
-#define UART_C5_TDMAS_MASK                       0x80u
-#define UART_C5_TDMAS_SHIFT                      7
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK                     0x40u
-#define UART_ED_PARITYE_SHIFT                    6
-#define UART_ED_NOISY_MASK                       0x80u
-#define UART_ED_NOISY_SHIFT                      7
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK                   0x1u
-#define UART_MODEM_TXCTSE_SHIFT                  0
-#define UART_MODEM_TXRTSE_MASK                   0x2u
-#define UART_MODEM_TXRTSE_SHIFT                  1
-#define UART_MODEM_TXRTSPOL_MASK                 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT                2
-#define UART_MODEM_RXRTSE_MASK                   0x8u
-#define UART_MODEM_RXRTSE_SHIFT                  3
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK                         0x3u
-#define UART_IR_TNP_SHIFT                        0
-#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK                        0x4u
-#define UART_IR_IREN_SHIFT                       2
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
-#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK                     0x8u
-#define UART_PFIFO_RXFE_SHIFT                    3
-#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
-#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK                     0x80u
-#define UART_PFIFO_TXFE_SHIFT                    7
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK                    0x1u
-#define UART_CFIFO_RXUFE_SHIFT                   0
-#define UART_CFIFO_TXOFE_MASK                    0x2u
-#define UART_CFIFO_TXOFE_SHIFT                   1
-#define UART_CFIFO_RXOFE_MASK                    0x4u
-#define UART_CFIFO_RXOFE_SHIFT                   2
-#define UART_CFIFO_RXFLUSH_MASK                  0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT                 6
-#define UART_CFIFO_TXFLUSH_MASK                  0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT                 7
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK                     0x1u
-#define UART_SFIFO_RXUF_SHIFT                    0
-#define UART_SFIFO_TXOF_MASK                     0x2u
-#define UART_SFIFO_TXOF_SHIFT                    1
-#define UART_SFIFO_RXOF_MASK                     0x4u
-#define UART_SFIFO_RXOF_SHIFT                    2
-#define UART_SFIFO_RXEMPT_MASK                   0x40u
-#define UART_SFIFO_RXEMPT_SHIFT                  6
-#define UART_SFIFO_TXEMPT_MASK                   0x80u
-#define UART_SFIFO_TXEMPT_SHIFT                  7
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK                 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT                0
-#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT                0
-#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK                 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT                0
-#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT                0
-#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK                0x1u
-#define UART_C7816_ISO_7816E_SHIFT               0
-#define UART_C7816_TTYPE_MASK                    0x2u
-#define UART_C7816_TTYPE_SHIFT                   1
-#define UART_C7816_INIT_MASK                     0x4u
-#define UART_C7816_INIT_SHIFT                    2
-#define UART_C7816_ANACK_MASK                    0x8u
-#define UART_C7816_ANACK_SHIFT                   3
-#define UART_C7816_ONACK_MASK                    0x10u
-#define UART_C7816_ONACK_SHIFT                   4
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK                    0x1u
-#define UART_IE7816_RXTE_SHIFT                   0
-#define UART_IE7816_TXTE_MASK                    0x2u
-#define UART_IE7816_TXTE_SHIFT                   1
-#define UART_IE7816_GTVE_MASK                    0x4u
-#define UART_IE7816_GTVE_SHIFT                   2
-#define UART_IE7816_INITDE_MASK                  0x10u
-#define UART_IE7816_INITDE_SHIFT                 4
-#define UART_IE7816_BWTE_MASK                    0x20u
-#define UART_IE7816_BWTE_SHIFT                   5
-#define UART_IE7816_CWTE_MASK                    0x40u
-#define UART_IE7816_CWTE_SHIFT                   6
-#define UART_IE7816_WTE_MASK                     0x80u
-#define UART_IE7816_WTE_SHIFT                    7
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK                     0x1u
-#define UART_IS7816_RXT_SHIFT                    0
-#define UART_IS7816_TXT_MASK                     0x2u
-#define UART_IS7816_TXT_SHIFT                    1
-#define UART_IS7816_GTV_MASK                     0x4u
-#define UART_IS7816_GTV_SHIFT                    2
-#define UART_IS7816_INITD_MASK                   0x10u
-#define UART_IS7816_INITD_SHIFT                  4
-#define UART_IS7816_BWT_MASK                     0x20u
-#define UART_IS7816_BWT_SHIFT                    5
-#define UART_IS7816_CWT_MASK                     0x40u
-#define UART_IS7816_CWT_SHIFT                    6
-#define UART_IS7816_WT_MASK                      0x80u
-#define UART_IS7816_WT_SHIFT                     7
-/* WP7816T0 Bit Fields */
-#define UART_WP7816T0_WI_MASK                    0xFFu
-#define UART_WP7816T0_WI_SHIFT                   0
-#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
-/* WP7816T1 Bit Fields */
-#define UART_WP7816T1_BWI_MASK                   0xFu
-#define UART_WP7816T1_BWI_SHIFT                  0
-#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
-#define UART_WP7816T1_CWI_MASK                   0xF0u
-#define UART_WP7816T1_CWI_SHIFT                  4
-#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK                     0xFFu
-#define UART_WN7816_GTN_SHIFT                    0
-#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK                    0xFFu
-#define UART_WF7816_GTFD_SHIFT                   0
-#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT            0
-#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT            4
-#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK                    0xFFu
-#define UART_TL7816_TLEN_SHIFT                   0
-#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-/* C6 Bit Fields */
-#define UART_C6_CP_MASK                          0x10u
-#define UART_C6_CP_SHIFT                         4
-#define UART_C6_CE_MASK                          0x20u
-#define UART_C6_CE_SHIFT                         5
-#define UART_C6_TX709_MASK                       0x40u
-#define UART_C6_TX709_SHIFT                      6
-#define UART_C6_EN709_MASK                       0x80u
-#define UART_C6_EN709_SHIFT                      7
-/* PCTH Bit Fields */
-#define UART_PCTH_PCTH_MASK                      0xFFu
-#define UART_PCTH_PCTH_SHIFT                     0
-#define UART_PCTH_PCTH(x)                        (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
-/* PCTL Bit Fields */
-#define UART_PCTL_PCTL_MASK                      0xFFu
-#define UART_PCTL_PCTL_SHIFT                     0
-#define UART_PCTL_PCTL(x)                        (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
-/* B1T Bit Fields */
-#define UART_B1T_B1T_MASK                        0xFFu
-#define UART_B1T_B1T_SHIFT                       0
-#define UART_B1T_B1T(x)                          (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
-/* SDTH Bit Fields */
-#define UART_SDTH_SDTH_MASK                      0xFFu
-#define UART_SDTH_SDTH_SHIFT                     0
-#define UART_SDTH_SDTH(x)                        (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
-/* SDTL Bit Fields */
-#define UART_SDTL_SDTL_MASK                      0xFFu
-#define UART_SDTL_SDTL_SHIFT                     0
-#define UART_SDTL_SDTL(x)                        (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
-/* PRE Bit Fields */
-#define UART_PRE_PREAMBLE_MASK                   0xFFu
-#define UART_PRE_PREAMBLE_SHIFT                  0
-#define UART_PRE_PREAMBLE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
-/* TPL Bit Fields */
-#define UART_TPL_TPL_MASK                        0xFFu
-#define UART_TPL_TPL_SHIFT                       0
-#define UART_TPL_TPL(x)                          (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
-/* IE Bit Fields */
-#define UART_IE_TXFIE_MASK                       0x1u
-#define UART_IE_TXFIE_SHIFT                      0
-#define UART_IE_PSIE_MASK                        0x2u
-#define UART_IE_PSIE_SHIFT                       1
-#define UART_IE_PCTEIE_MASK                      0x4u
-#define UART_IE_PCTEIE_SHIFT                     2
-#define UART_IE_PTXIE_MASK                       0x8u
-#define UART_IE_PTXIE_SHIFT                      3
-#define UART_IE_PRXIE_MASK                       0x10u
-#define UART_IE_PRXIE_SHIFT                      4
-#define UART_IE_ISDIE_MASK                       0x20u
-#define UART_IE_ISDIE_SHIFT                      5
-#define UART_IE_WBEIE_MASK                       0x40u
-#define UART_IE_WBEIE_SHIFT                      6
-/* WB Bit Fields */
-#define UART_WB_WBASE_MASK                       0xFFu
-#define UART_WB_WBASE_SHIFT                      0
-#define UART_WB_WBASE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
-/* S3 Bit Fields */
-#define UART_S3_TXFF_MASK                        0x1u
-#define UART_S3_TXFF_SHIFT                       0
-#define UART_S3_PSF_MASK                         0x2u
-#define UART_S3_PSF_SHIFT                        1
-#define UART_S3_PCTEF_MASK                       0x4u
-#define UART_S3_PCTEF_SHIFT                      2
-#define UART_S3_PTXF_MASK                        0x8u
-#define UART_S3_PTXF_SHIFT                       3
-#define UART_S3_PRXF_MASK                        0x10u
-#define UART_S3_PRXF_SHIFT                       4
-#define UART_S3_ISD_MASK                         0x20u
-#define UART_S3_ISD_SHIFT                        5
-#define UART_S3_WBEF_MASK                        0x40u
-#define UART_S3_WBEF_SHIFT                       6
-#define UART_S3_PEF_MASK                         0x80u
-#define UART_S3_PEF_SHIFT                        7
-/* S4 Bit Fields */
-#define UART_S4_FE_MASK                          0x1u
-#define UART_S4_FE_SHIFT                         0
-#define UART_S4_ILCV_MASK                        0x2u
-#define UART_S4_ILCV_SHIFT                       1
-#define UART_S4_CDET_MASK                        0xCu
-#define UART_S4_CDET_SHIFT                       2
-#define UART_S4_CDET(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
-#define UART_S4_INITF_MASK                       0x10u
-#define UART_S4_INITF_SHIFT                      4
-/* RPL Bit Fields */
-#define UART_RPL_RPL_MASK                        0xFFu
-#define UART_RPL_RPL_SHIFT                       0
-#define UART_RPL_RPL(x)                          (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
-/* RPREL Bit Fields */
-#define UART_RPREL_RPREL_MASK                    0xFFu
-#define UART_RPREL_RPREL_SHIFT                   0
-#define UART_RPREL_RPREL(x)                      (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
-/* CPW Bit Fields */
-#define UART_CPW_CPW_MASK                        0xFFu
-#define UART_CPW_CPW_SHIFT                       0
-#define UART_CPW_CPW(x)                          (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
-/* RIDT Bit Fields */
-#define UART_RIDT_RIDT_MASK                      0xFFu
-#define UART_RIDT_RIDT_SHIFT                     0
-#define UART_RIDT_RIDT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
-/* TIDT Bit Fields */
-#define UART_TIDT_TIDT_MASK                      0xFFu
-#define UART_TIDT_TIDT_SHIFT                     0
-#define UART_TIDT_TIDT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
+/*! @name BDH - UART Baud Rate Registers: High */
+#define UART_BDH_SBR_MASK                        (0x1FU)
+#define UART_BDH_SBR_SHIFT                       (0U)
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK                    (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT                   (6U)
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     (0x80U)
+#define UART_BDH_LBKDIE_SHIFT                    (7U)
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+#define UART_BDL_SBR_MASK                        (0xFFU)
+#define UART_BDL_SBR_SHIFT                       (0U)
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK                          (0x1U)
+#define UART_C1_PT_SHIFT                         (0U)
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          (0x2U)
+#define UART_C1_PE_SHIFT                         (1U)
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         (0x4U)
+#define UART_C1_ILT_SHIFT                        (2U)
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        (0x8U)
+#define UART_C1_WAKE_SHIFT                       (3U)
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           (0x10U)
+#define UART_C1_M_SHIFT                          (4U)
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        (0x20U)
+#define UART_C1_RSRC_SHIFT                       (5U)
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    (0x40U)
+#define UART_C1_UARTSWAI_SHIFT                   (6U)
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       (0x80U)
+#define UART_C1_LOOPS_SHIFT                      (7U)
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK                         (0x1U)
+#define UART_C2_SBK_SHIFT                        (0U)
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         (0x2U)
+#define UART_C2_RWU_SHIFT                        (1U)
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          (0x4U)
+#define UART_C2_RE_SHIFT                         (2U)
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          (0x8U)
+#define UART_C2_TE_SHIFT                         (3U)
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        (0x10U)
+#define UART_C2_ILIE_SHIFT                       (4U)
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         (0x20U)
+#define UART_C2_RIE_SHIFT                        (5U)
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        (0x40U)
+#define UART_C2_TCIE_SHIFT                       (6U)
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         (0x80U)
+#define UART_C2_TIE_SHIFT                        (7U)
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK                          (0x1U)
+#define UART_S1_PF_SHIFT                         (0U)
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          (0x2U)
+#define UART_S1_FE_SHIFT                         (1U)
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          (0x4U)
+#define UART_S1_NF_SHIFT                         (2U)
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          (0x8U)
+#define UART_S1_OR_SHIFT                         (3U)
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        (0x10U)
+#define UART_S1_IDLE_SHIFT                       (4U)
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        (0x20U)
+#define UART_S1_RDRF_SHIFT                       (5U)
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          (0x40U)
+#define UART_S1_TC_SHIFT                         (6U)
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        (0x80U)
+#define UART_S1_TDRE_SHIFT                       (7U)
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK                         (0x1U)
+#define UART_S2_RAF_SHIFT                        (0U)
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       (0x2U)
+#define UART_S2_LBKDE_SHIFT                      (1U)
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       (0x4U)
+#define UART_S2_BRK13_SHIFT                      (2U)
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       (0x8U)
+#define UART_S2_RWUID_SHIFT                      (3U)
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       (0x10U)
+#define UART_S2_RXINV_SHIFT                      (4U)
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        (0x20U)
+#define UART_S2_MSBF_SHIFT                       (5U)
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     (0x40U)
+#define UART_S2_RXEDGIF_SHIFT                    (6U)
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      (0x80U)
+#define UART_S2_LBKDIF_SHIFT                     (7U)
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK                        (0x1U)
+#define UART_C3_PEIE_SHIFT                       (0U)
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        (0x2U)
+#define UART_C3_FEIE_SHIFT                       (1U)
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        (0x4U)
+#define UART_C3_NEIE_SHIFT                       (2U)
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        (0x8U)
+#define UART_C3_ORIE_SHIFT                       (3U)
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       (0x10U)
+#define UART_C3_TXINV_SHIFT                      (4U)
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       (0x20U)
+#define UART_C3_TXDIR_SHIFT                      (5U)
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          (0x40U)
+#define UART_C3_T8_SHIFT                         (6U)
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          (0x80U)
+#define UART_C3_R8_SHIFT                         (7U)
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_RT_MASK                           (0xFFU)
+#define UART_D_RT_SHIFT                          (0U)
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART_MA1_MA_MASK                         (0xFFU)
+#define UART_MA1_MA_SHIFT                        (0U)
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART_MA2_MA_MASK                         (0xFFU)
+#define UART_MA2_MA_SHIFT                        (0U)
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_BRFA_MASK                        (0x1FU)
+#define UART_C4_BRFA_SHIFT                       (0U)
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         (0x20U)
+#define UART_C4_M10_SHIFT                        (5U)
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       (0x40U)
+#define UART_C4_MAEN2_SHIFT                      (6U)
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       (0x80U)
+#define UART_C4_MAEN1_SHIFT                      (7U)
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART_C5_RDMAS_MASK                       (0x20U)
+#define UART_C5_RDMAS_SHIFT                      (5U)
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       (0x80U)
+#define UART_C5_TDMAS_SHIFT                      (7U)
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+
+/*! @name ED - UART Extended Data Register */
+#define UART_ED_PARITYE_MASK                     (0x40U)
+#define UART_ED_PARITYE_SHIFT                    (6U)
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       (0x80U)
+#define UART_ED_NOISY_SHIFT                      (7U)
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+
+/*! @name MODEM - UART Modem Register */
+#define UART_MODEM_TXCTSE_MASK                   (0x1U)
+#define UART_MODEM_TXCTSE_SHIFT                  (0U)
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   (0x2U)
+#define UART_MODEM_TXRTSE_SHIFT                  (1U)
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 (0x4U)
+#define UART_MODEM_TXRTSPOL_SHIFT                (2U)
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   (0x8U)
+#define UART_MODEM_RXRTSE_SHIFT                  (3U)
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+
+/*! @name IR - UART Infrared Register */
+#define UART_IR_TNP_MASK                         (0x3U)
+#define UART_IR_TNP_SHIFT                        (0U)
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        (0x4U)
+#define UART_IR_IREN_SHIFT                       (2U)
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+
+/*! @name PFIFO - UART FIFO Parameters */
+#define UART_PFIFO_RXFIFOSIZE_MASK               (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              (0U)
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     (0x8U)
+#define UART_PFIFO_RXFE_SHIFT                    (3U)
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              (4U)
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     (0x80U)
+#define UART_PFIFO_TXFE_SHIFT                    (7U)
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+
+/*! @name CFIFO - UART FIFO Control Register */
+#define UART_CFIFO_RXUFE_MASK                    (0x1U)
+#define UART_CFIFO_RXUFE_SHIFT                   (0U)
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    (0x2U)
+#define UART_CFIFO_TXOFE_SHIFT                   (1U)
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    (0x4U)
+#define UART_CFIFO_RXOFE_SHIFT                   (2U)
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  (0x40U)
+#define UART_CFIFO_RXFLUSH_SHIFT                 (6U)
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  (0x80U)
+#define UART_CFIFO_TXFLUSH_SHIFT                 (7U)
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+
+/*! @name SFIFO - UART FIFO Status Register */
+#define UART_SFIFO_RXUF_MASK                     (0x1U)
+#define UART_SFIFO_RXUF_SHIFT                    (0U)
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     (0x2U)
+#define UART_SFIFO_TXOF_SHIFT                    (1U)
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     (0x4U)
+#define UART_SFIFO_RXOF_SHIFT                    (2U)
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   (0x40U)
+#define UART_SFIFO_RXEMPT_SHIFT                  (6U)
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   (0x80U)
+#define UART_SFIFO_TXEMPT_SHIFT                  (7U)
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+#define UART_TWFIFO_TXWATER_MASK                 (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT                (0U)
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+#define UART_TCFIFO_TXCOUNT_MASK                 (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT                (0U)
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+#define UART_RWFIFO_RXWATER_MASK                 (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT                (0U)
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+#define UART_RCFIFO_RXCOUNT_MASK                 (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT                (0U)
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+
+/*! @name C7816 - UART 7816 Control Register */
+#define UART_C7816_ISO_7816E_MASK                (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT               (0U)
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    (0x2U)
+#define UART_C7816_TTYPE_SHIFT                   (1U)
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     (0x4U)
+#define UART_C7816_INIT_SHIFT                    (2U)
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    (0x8U)
+#define UART_C7816_ANACK_SHIFT                   (3U)
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    (0x10U)
+#define UART_C7816_ONACK_SHIFT                   (4U)
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+#define UART_IE7816_RXTE_MASK                    (0x1U)
+#define UART_IE7816_RXTE_SHIFT                   (0U)
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    (0x2U)
+#define UART_IE7816_TXTE_SHIFT                   (1U)
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    (0x4U)
+#define UART_IE7816_GTVE_SHIFT                   (2U)
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK                  (0x10U)
+#define UART_IE7816_INITDE_SHIFT                 (4U)
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    (0x20U)
+#define UART_IE7816_BWTE_SHIFT                   (5U)
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    (0x40U)
+#define UART_IE7816_CWTE_SHIFT                   (6U)
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     (0x80U)
+#define UART_IE7816_WTE_SHIFT                    (7U)
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+#define UART_IS7816_RXT_MASK                     (0x1U)
+#define UART_IS7816_RXT_SHIFT                    (0U)
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     (0x2U)
+#define UART_IS7816_TXT_SHIFT                    (1U)
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     (0x4U)
+#define UART_IS7816_GTV_SHIFT                    (2U)
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK                   (0x10U)
+#define UART_IS7816_INITD_SHIFT                  (4U)
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     (0x20U)
+#define UART_IS7816_BWT_SHIFT                    (5U)
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     (0x40U)
+#define UART_IS7816_CWT_SHIFT                    (6U)
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      (0x80U)
+#define UART_IS7816_WT_SHIFT                     (7U)
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+
+/*! @name WP7816T0 - UART 7816 Wait Parameter Register */
+#define UART_WP7816T0_WI_MASK                    (0xFFU)
+#define UART_WP7816T0_WI_SHIFT                   (0U)
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
+
+/*! @name WP7816T1 - UART 7816 Wait Parameter Register */
+#define UART_WP7816T1_BWI_MASK                   (0xFU)
+#define UART_WP7816T1_BWI_SHIFT                  (0U)
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   (0xF0U)
+#define UART_WP7816T1_CWI_SHIFT                  (4U)
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+#define UART_WN7816_GTN_MASK                     (0xFFU)
+#define UART_WN7816_GTN_SHIFT                    (0U)
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+#define UART_WF7816_GTFD_MASK                    (0xFFU)
+#define UART_WF7816_GTFD_SHIFT                   (0U)
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+#define UART_ET7816_RXTHRESHOLD_MASK             (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT            (0U)
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT            (4U)
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+#define UART_TL7816_TLEN_MASK                    (0xFFU)
+#define UART_TL7816_TLEN_SHIFT                   (0U)
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+
+/*! @name C6 - UART CEA709.1-B Control Register 6 */
+#define UART_C6_CP_MASK                          (0x10U)
+#define UART_C6_CP_SHIFT                         (4U)
+#define UART_C6_CP(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C6_CP_SHIFT)) & UART_C6_CP_MASK)
+#define UART_C6_CE_MASK                          (0x20U)
+#define UART_C6_CE_SHIFT                         (5U)
+#define UART_C6_CE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C6_CE_SHIFT)) & UART_C6_CE_MASK)
+#define UART_C6_TX709_MASK                       (0x40U)
+#define UART_C6_TX709_SHIFT                      (6U)
+#define UART_C6_TX709(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C6_TX709_SHIFT)) & UART_C6_TX709_MASK)
+#define UART_C6_EN709_MASK                       (0x80U)
+#define UART_C6_EN709_SHIFT                      (7U)
+#define UART_C6_EN709(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C6_EN709_SHIFT)) & UART_C6_EN709_MASK)
+
+/*! @name PCTH - UART CEA709.1-B Packet Cycle Time Counter High */
+#define UART_PCTH_PCTH_MASK                      (0xFFU)
+#define UART_PCTH_PCTH_SHIFT                     (0U)
+#define UART_PCTH_PCTH(x)                        (((uint8_t)(((uint8_t)(x)) << UART_PCTH_PCTH_SHIFT)) & UART_PCTH_PCTH_MASK)
+
+/*! @name PCTL - UART CEA709.1-B Packet Cycle Time Counter Low */
+#define UART_PCTL_PCTL_MASK                      (0xFFU)
+#define UART_PCTL_PCTL_SHIFT                     (0U)
+#define UART_PCTL_PCTL(x)                        (((uint8_t)(((uint8_t)(x)) << UART_PCTL_PCTL_SHIFT)) & UART_PCTL_PCTL_MASK)
+
+/*! @name B1T - UART CEA709.1-B Beta1 Timer */
+#define UART_B1T_B1T_MASK                        (0xFFU)
+#define UART_B1T_B1T_SHIFT                       (0U)
+#define UART_B1T_B1T(x)                          (((uint8_t)(((uint8_t)(x)) << UART_B1T_B1T_SHIFT)) & UART_B1T_B1T_MASK)
+
+/*! @name SDTH - UART CEA709.1-B Secondary Delay Timer High */
+#define UART_SDTH_SDTH_MASK                      (0xFFU)
+#define UART_SDTH_SDTH_SHIFT                     (0U)
+#define UART_SDTH_SDTH(x)                        (((uint8_t)(((uint8_t)(x)) << UART_SDTH_SDTH_SHIFT)) & UART_SDTH_SDTH_MASK)
+
+/*! @name SDTL - UART CEA709.1-B Secondary Delay Timer Low */
+#define UART_SDTL_SDTL_MASK                      (0xFFU)
+#define UART_SDTL_SDTL_SHIFT                     (0U)
+#define UART_SDTL_SDTL(x)                        (((uint8_t)(((uint8_t)(x)) << UART_SDTL_SDTL_SHIFT)) & UART_SDTL_SDTL_MASK)
+
+/*! @name PRE - UART CEA709.1-B Preamble */
+#define UART_PRE_PREAMBLE_MASK                   (0xFFU)
+#define UART_PRE_PREAMBLE_SHIFT                  (0U)
+#define UART_PRE_PREAMBLE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_PRE_PREAMBLE_SHIFT)) & UART_PRE_PREAMBLE_MASK)
+
+/*! @name TPL - UART CEA709.1-B Transmit Packet Length */
+#define UART_TPL_TPL_MASK                        (0xFFU)
+#define UART_TPL_TPL_SHIFT                       (0U)
+#define UART_TPL_TPL(x)                          (((uint8_t)(((uint8_t)(x)) << UART_TPL_TPL_SHIFT)) & UART_TPL_TPL_MASK)
+
+/*! @name IE - UART CEA709.1-B Interrupt Enable Register */
+#define UART_IE_TXFIE_MASK                       (0x1U)
+#define UART_IE_TXFIE_SHIFT                      (0U)
+#define UART_IE_TXFIE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_IE_TXFIE_SHIFT)) & UART_IE_TXFIE_MASK)
+#define UART_IE_PSIE_MASK                        (0x2U)
+#define UART_IE_PSIE_SHIFT                       (1U)
+#define UART_IE_PSIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_IE_PSIE_SHIFT)) & UART_IE_PSIE_MASK)
+#define UART_IE_PCTEIE_MASK                      (0x4U)
+#define UART_IE_PCTEIE_SHIFT                     (2U)
+#define UART_IE_PCTEIE(x)                        (((uint8_t)(((uint8_t)(x)) << UART_IE_PCTEIE_SHIFT)) & UART_IE_PCTEIE_MASK)
+#define UART_IE_PTXIE_MASK                       (0x8U)
+#define UART_IE_PTXIE_SHIFT                      (3U)
+#define UART_IE_PTXIE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_IE_PTXIE_SHIFT)) & UART_IE_PTXIE_MASK)
+#define UART_IE_PRXIE_MASK                       (0x10U)
+#define UART_IE_PRXIE_SHIFT                      (4U)
+#define UART_IE_PRXIE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_IE_PRXIE_SHIFT)) & UART_IE_PRXIE_MASK)
+#define UART_IE_ISDIE_MASK                       (0x20U)
+#define UART_IE_ISDIE_SHIFT                      (5U)
+#define UART_IE_ISDIE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_IE_ISDIE_SHIFT)) & UART_IE_ISDIE_MASK)
+#define UART_IE_WBEIE_MASK                       (0x40U)
+#define UART_IE_WBEIE_SHIFT                      (6U)
+#define UART_IE_WBEIE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_IE_WBEIE_SHIFT)) & UART_IE_WBEIE_MASK)
+
+/*! @name WB - UART CEA709.1-B WBASE */
+#define UART_WB_WBASE_MASK                       (0xFFU)
+#define UART_WB_WBASE_SHIFT                      (0U)
+#define UART_WB_WBASE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_WB_WBASE_SHIFT)) & UART_WB_WBASE_MASK)
+
+/*! @name S3 - UART CEA709.1-B Status Register */
+#define UART_S3_TXFF_MASK                        (0x1U)
+#define UART_S3_TXFF_SHIFT                       (0U)
+#define UART_S3_TXFF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S3_TXFF_SHIFT)) & UART_S3_TXFF_MASK)
+#define UART_S3_PSF_MASK                         (0x2U)
+#define UART_S3_PSF_SHIFT                        (1U)
+#define UART_S3_PSF(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S3_PSF_SHIFT)) & UART_S3_PSF_MASK)
+#define UART_S3_PCTEF_MASK                       (0x4U)
+#define UART_S3_PCTEF_SHIFT                      (2U)
+#define UART_S3_PCTEF(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S3_PCTEF_SHIFT)) & UART_S3_PCTEF_MASK)
+#define UART_S3_PTXF_MASK                        (0x8U)
+#define UART_S3_PTXF_SHIFT                       (3U)
+#define UART_S3_PTXF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S3_PTXF_SHIFT)) & UART_S3_PTXF_MASK)
+#define UART_S3_PRXF_MASK                        (0x10U)
+#define UART_S3_PRXF_SHIFT                       (4U)
+#define UART_S3_PRXF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S3_PRXF_SHIFT)) & UART_S3_PRXF_MASK)
+#define UART_S3_ISD_MASK                         (0x20U)
+#define UART_S3_ISD_SHIFT                        (5U)
+#define UART_S3_ISD(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S3_ISD_SHIFT)) & UART_S3_ISD_MASK)
+#define UART_S3_WBEF_MASK                        (0x40U)
+#define UART_S3_WBEF_SHIFT                       (6U)
+#define UART_S3_WBEF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S3_WBEF_SHIFT)) & UART_S3_WBEF_MASK)
+#define UART_S3_PEF_MASK                         (0x80U)
+#define UART_S3_PEF_SHIFT                        (7U)
+#define UART_S3_PEF(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S3_PEF_SHIFT)) & UART_S3_PEF_MASK)
+
+/*! @name S4 - UART CEA709.1-B Status Register */
+#define UART_S4_FE_MASK                          (0x1U)
+#define UART_S4_FE_SHIFT                         (0U)
+#define UART_S4_FE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S4_FE_SHIFT)) & UART_S4_FE_MASK)
+#define UART_S4_ILCV_MASK                        (0x2U)
+#define UART_S4_ILCV_SHIFT                       (1U)
+#define UART_S4_ILCV(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S4_ILCV_SHIFT)) & UART_S4_ILCV_MASK)
+#define UART_S4_CDET_MASK                        (0xCU)
+#define UART_S4_CDET_SHIFT                       (2U)
+#define UART_S4_CDET(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S4_CDET_SHIFT)) & UART_S4_CDET_MASK)
+#define UART_S4_INITF_MASK                       (0x10U)
+#define UART_S4_INITF_SHIFT                      (4U)
+#define UART_S4_INITF(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S4_INITF_SHIFT)) & UART_S4_INITF_MASK)
+
+/*! @name RPL - UART CEA709.1-B Received Packet Length */
+#define UART_RPL_RPL_MASK                        (0xFFU)
+#define UART_RPL_RPL_SHIFT                       (0U)
+#define UART_RPL_RPL(x)                          (((uint8_t)(((uint8_t)(x)) << UART_RPL_RPL_SHIFT)) & UART_RPL_RPL_MASK)
+
+/*! @name RPREL - UART CEA709.1-B Received Preamble Length */
+#define UART_RPREL_RPREL_MASK                    (0xFFU)
+#define UART_RPREL_RPREL_SHIFT                   (0U)
+#define UART_RPREL_RPREL(x)                      (((uint8_t)(((uint8_t)(x)) << UART_RPREL_RPREL_SHIFT)) & UART_RPREL_RPREL_MASK)
+
+/*! @name CPW - UART CEA709.1-B Collision Pulse Width */
+#define UART_CPW_CPW_MASK                        (0xFFU)
+#define UART_CPW_CPW_SHIFT                       (0U)
+#define UART_CPW_CPW(x)                          (((uint8_t)(((uint8_t)(x)) << UART_CPW_CPW_SHIFT)) & UART_CPW_CPW_MASK)
+
+/*! @name RIDT - UART CEA709.1-B Receive Indeterminate Time */
+#define UART_RIDT_RIDT_MASK                      (0xFFU)
+#define UART_RIDT_RIDT_SHIFT                     (0U)
+#define UART_RIDT_RIDT(x)                        (((uint8_t)(((uint8_t)(x)) << UART_RIDT_RIDT_SHIFT)) & UART_RIDT_RIDT_MASK)
+
+/*! @name TIDT - UART CEA709.1-B Transmit Indeterminate Time */
+#define UART_TIDT_TIDT_MASK                      (0xFFU)
+#define UART_TIDT_TIDT_SHIFT                     (0U)
+#define UART_TIDT_TIDT(x)                        (((uint8_t)(((uint8_t)(x)) << UART_TIDT_TIDT_SHIFT)) & UART_TIDT_TIDT_MASK)
+
 
 /*!
  * @}
@@ -13393,32 +12038,26 @@ typedef struct {
 #define UART0_BASE                               (0x4006A000u)
 /** Peripheral UART0 base pointer */
 #define UART0                                    ((UART_Type *)UART0_BASE)
-#define UART0_BASE_PTR                           (UART0)
 /** Peripheral UART1 base address */
 #define UART1_BASE                               (0x4006B000u)
 /** Peripheral UART1 base pointer */
 #define UART1                                    ((UART_Type *)UART1_BASE)
-#define UART1_BASE_PTR                           (UART1)
 /** Peripheral UART2 base address */
 #define UART2_BASE                               (0x4006C000u)
 /** Peripheral UART2 base pointer */
 #define UART2                                    ((UART_Type *)UART2_BASE)
-#define UART2_BASE_PTR                           (UART2)
 /** Peripheral UART3 base address */
 #define UART3_BASE                               (0x4006D000u)
 /** Peripheral UART3 base pointer */
 #define UART3                                    ((UART_Type *)UART3_BASE)
-#define UART3_BASE_PTR                           (UART3)
 /** Peripheral UART4 base address */
 #define UART4_BASE                               (0x400EA000u)
 /** Peripheral UART4 base pointer */
 #define UART4                                    ((UART_Type *)UART4_BASE)
-#define UART4_BASE_PTR                           (UART4)
 /** Peripheral UART5 base address */
 #define UART5_BASE                               (0x400EB000u)
 /** Peripheral UART5 base pointer */
 #define UART5                                    ((UART_Type *)UART5_BASE)
-#define UART5_BASE_PTR                           (UART5)
 /** Array initializer of UART peripheral base addresses */
 #define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
 /** Array initializer of UART peripheral base pointers */
@@ -13428,187 +12067,6 @@ typedef struct {
 #define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
 #define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- UART - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register instance definitions */
-/* UART0 */
-#define UART0_BDH                                UART_BDH_REG(UART0)
-#define UART0_BDL                                UART_BDL_REG(UART0)
-#define UART0_C1                                 UART_C1_REG(UART0)
-#define UART0_C2                                 UART_C2_REG(UART0)
-#define UART0_S1                                 UART_S1_REG(UART0)
-#define UART0_S2                                 UART_S2_REG(UART0)
-#define UART0_C3                                 UART_C3_REG(UART0)
-#define UART0_D                                  UART_D_REG(UART0)
-#define UART0_MA1                                UART_MA1_REG(UART0)
-#define UART0_MA2                                UART_MA2_REG(UART0)
-#define UART0_C4                                 UART_C4_REG(UART0)
-#define UART0_C5                                 UART_C5_REG(UART0)
-#define UART0_ED                                 UART_ED_REG(UART0)
-#define UART0_MODEM                              UART_MODEM_REG(UART0)
-#define UART0_IR                                 UART_IR_REG(UART0)
-#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
-#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
-#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
-#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
-#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
-#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
-#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
-#define UART0_C7816                              UART_C7816_REG(UART0)
-#define UART0_IE7816                             UART_IE7816_REG(UART0)
-#define UART0_IS7816                             UART_IS7816_REG(UART0)
-#define UART0_WP7816T0                           UART_WP7816T0_REG(UART0)
-#define UART0_WP7816T1                           UART_WP7816T1_REG(UART0)
-#define UART0_WN7816                             UART_WN7816_REG(UART0)
-#define UART0_WF7816                             UART_WF7816_REG(UART0)
-#define UART0_ET7816                             UART_ET7816_REG(UART0)
-#define UART0_TL7816                             UART_TL7816_REG(UART0)
-#define UART0_C6                                 UART_C6_REG(UART0)
-#define UART0_PCTH                               UART_PCTH_REG(UART0)
-#define UART0_PCTL                               UART_PCTL_REG(UART0)
-#define UART0_B1T                                UART_B1T_REG(UART0)
-#define UART0_SDTH                               UART_SDTH_REG(UART0)
-#define UART0_SDTL                               UART_SDTL_REG(UART0)
-#define UART0_PRE                                UART_PRE_REG(UART0)
-#define UART0_TPL                                UART_TPL_REG(UART0)
-#define UART0_IE                                 UART_IE_REG(UART0)
-#define UART0_WB                                 UART_WB_REG(UART0)
-#define UART0_S3                                 UART_S3_REG(UART0)
-#define UART0_S4                                 UART_S4_REG(UART0)
-#define UART0_RPL                                UART_RPL_REG(UART0)
-#define UART0_RPREL                              UART_RPREL_REG(UART0)
-#define UART0_CPW                                UART_CPW_REG(UART0)
-#define UART0_RIDT                               UART_RIDT_REG(UART0)
-#define UART0_TIDT                               UART_TIDT_REG(UART0)
-/* UART1 */
-#define UART1_BDH                                UART_BDH_REG(UART1)
-#define UART1_BDL                                UART_BDL_REG(UART1)
-#define UART1_C1                                 UART_C1_REG(UART1)
-#define UART1_C2                                 UART_C2_REG(UART1)
-#define UART1_S1                                 UART_S1_REG(UART1)
-#define UART1_S2                                 UART_S2_REG(UART1)
-#define UART1_C3                                 UART_C3_REG(UART1)
-#define UART1_D                                  UART_D_REG(UART1)
-#define UART1_MA1                                UART_MA1_REG(UART1)
-#define UART1_MA2                                UART_MA2_REG(UART1)
-#define UART1_C4                                 UART_C4_REG(UART1)
-#define UART1_C5                                 UART_C5_REG(UART1)
-#define UART1_ED                                 UART_ED_REG(UART1)
-#define UART1_MODEM                              UART_MODEM_REG(UART1)
-#define UART1_IR                                 UART_IR_REG(UART1)
-#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
-#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
-#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
-#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
-#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
-#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
-#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
-/* UART2 */
-#define UART2_BDH                                UART_BDH_REG(UART2)
-#define UART2_BDL                                UART_BDL_REG(UART2)
-#define UART2_C1                                 UART_C1_REG(UART2)
-#define UART2_C2                                 UART_C2_REG(UART2)
-#define UART2_S1                                 UART_S1_REG(UART2)
-#define UART2_S2                                 UART_S2_REG(UART2)
-#define UART2_C3                                 UART_C3_REG(UART2)
-#define UART2_D                                  UART_D_REG(UART2)
-#define UART2_MA1                                UART_MA1_REG(UART2)
-#define UART2_MA2                                UART_MA2_REG(UART2)
-#define UART2_C4                                 UART_C4_REG(UART2)
-#define UART2_C5                                 UART_C5_REG(UART2)
-#define UART2_ED                                 UART_ED_REG(UART2)
-#define UART2_MODEM                              UART_MODEM_REG(UART2)
-#define UART2_IR                                 UART_IR_REG(UART2)
-#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
-#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
-#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
-#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
-#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
-#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
-#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
-/* UART3 */
-#define UART3_BDH                                UART_BDH_REG(UART3)
-#define UART3_BDL                                UART_BDL_REG(UART3)
-#define UART3_C1                                 UART_C1_REG(UART3)
-#define UART3_C2                                 UART_C2_REG(UART3)
-#define UART3_S1                                 UART_S1_REG(UART3)
-#define UART3_S2                                 UART_S2_REG(UART3)
-#define UART3_C3                                 UART_C3_REG(UART3)
-#define UART3_D                                  UART_D_REG(UART3)
-#define UART3_MA1                                UART_MA1_REG(UART3)
-#define UART3_MA2                                UART_MA2_REG(UART3)
-#define UART3_C4                                 UART_C4_REG(UART3)
-#define UART3_C5                                 UART_C5_REG(UART3)
-#define UART3_ED                                 UART_ED_REG(UART3)
-#define UART3_MODEM                              UART_MODEM_REG(UART3)
-#define UART3_IR                                 UART_IR_REG(UART3)
-#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
-#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
-#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
-#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
-#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
-#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
-#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
-/* UART4 */
-#define UART4_BDH                                UART_BDH_REG(UART4)
-#define UART4_BDL                                UART_BDL_REG(UART4)
-#define UART4_C1                                 UART_C1_REG(UART4)
-#define UART4_C2                                 UART_C2_REG(UART4)
-#define UART4_S1                                 UART_S1_REG(UART4)
-#define UART4_S2                                 UART_S2_REG(UART4)
-#define UART4_C3                                 UART_C3_REG(UART4)
-#define UART4_D                                  UART_D_REG(UART4)
-#define UART4_MA1                                UART_MA1_REG(UART4)
-#define UART4_MA2                                UART_MA2_REG(UART4)
-#define UART4_C4                                 UART_C4_REG(UART4)
-#define UART4_C5                                 UART_C5_REG(UART4)
-#define UART4_ED                                 UART_ED_REG(UART4)
-#define UART4_MODEM                              UART_MODEM_REG(UART4)
-#define UART4_IR                                 UART_IR_REG(UART4)
-#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
-#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
-#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
-#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
-#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
-#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
-#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
-/* UART5 */
-#define UART5_BDH                                UART_BDH_REG(UART5)
-#define UART5_BDL                                UART_BDL_REG(UART5)
-#define UART5_C1                                 UART_C1_REG(UART5)
-#define UART5_C2                                 UART_C2_REG(UART5)
-#define UART5_S1                                 UART_S1_REG(UART5)
-#define UART5_S2                                 UART_S2_REG(UART5)
-#define UART5_C3                                 UART_C3_REG(UART5)
-#define UART5_D                                  UART_D_REG(UART5)
-#define UART5_MA1                                UART_MA1_REG(UART5)
-#define UART5_MA2                                UART_MA2_REG(UART5)
-#define UART5_C4                                 UART_C4_REG(UART5)
-#define UART5_C5                                 UART_C5_REG(UART5)
-#define UART5_ED                                 UART_ED_REG(UART5)
-#define UART5_MODEM                              UART_MODEM_REG(UART5)
-#define UART5_IR                                 UART_IR_REG(UART5)
-#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
-#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
-#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
-#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
-#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
-#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
-#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group UART_Peripheral_Access_Layer */
@@ -13682,52 +12140,7 @@ typedef struct {
   __IO uint8_t USBTRC0;                            /**< USB Transceiver Control Register 0, offset: 0x10C */
        uint8_t RESERVED_25[7];
   __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
-} USB_Type, *USB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- USB - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register accessors */
-#define USB_PERID_REG(base)                      ((base)->PERID)
-#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
-#define USB_REV_REG(base)                        ((base)->REV)
-#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
-#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
-#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
-#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
-#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
-#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
-#define USB_INTEN_REG(base)                      ((base)->INTEN)
-#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
-#define USB_ERREN_REG(base)                      ((base)->ERREN)
-#define USB_STAT_REG(base)                       ((base)->STAT)
-#define USB_CTL_REG(base)                        ((base)->CTL)
-#define USB_ADDR_REG(base)                       ((base)->ADDR)
-#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
-#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
-#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
-#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
-#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
-#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
-#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
-#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
-#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
-#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
-#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
-#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
-#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
+} USB_Type;
 
 /* ----------------------------------------------------------------------------
    -- USB Register Masks
@@ -13738,241 +12151,353 @@ typedef struct {
  * @{
  */
 
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK                        0x3Fu
-#define USB_PERID_ID_SHIFT                       0
-#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK                      0x3Fu
-#define USB_IDCOMP_NID_SHIFT                     0
-#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK                         0xFFu
-#define USB_REV_REV_SHIFT                        0
-#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK                  0x1u
-#define USB_ADDINFO_IEHOST_SHIFT                 0
-#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
-#define USB_ADDINFO_IRQNUM_SHIFT                 3
-#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
-#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
-#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
-#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT               6
-#define USB_OTGISTAT_IDCHG_MASK                  0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT                 7
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK                  0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT                 0
-#define USB_OTGICR_BSESSEN_MASK                  0x4u
-#define USB_OTGICR_BSESSEN_SHIFT                 2
-#define USB_OTGICR_SESSVLDEN_MASK                0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT               3
-#define USB_OTGICR_LINESTATEEN_MASK              0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT             5
-#define USB_OTGICR_ONEMSECEN_MASK                0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT               6
-#define USB_OTGICR_IDEN_MASK                     0x80u
-#define USB_OTGICR_IDEN_SHIFT                    7
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
-#define USB_OTGSTAT_BSESSEND_MASK                0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT               2
-#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT               3
-#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
-#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
-#define USB_OTGSTAT_ID_MASK                      0x80u
-#define USB_OTGSTAT_ID_SHIFT                     7
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK                    0x4u
-#define USB_OTGCTL_OTGEN_SHIFT                   2
-#define USB_OTGCTL_DMLOW_MASK                    0x10u
-#define USB_OTGCTL_DMLOW_SHIFT                   4
-#define USB_OTGCTL_DPLOW_MASK                    0x20u
-#define USB_OTGCTL_DPLOW_SHIFT                   5
-#define USB_OTGCTL_DPHIGH_MASK                   0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT                  7
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK                    0x1u
-#define USB_ISTAT_USBRST_SHIFT                   0
-#define USB_ISTAT_ERROR_MASK                     0x2u
-#define USB_ISTAT_ERROR_SHIFT                    1
-#define USB_ISTAT_SOFTOK_MASK                    0x4u
-#define USB_ISTAT_SOFTOK_SHIFT                   2
-#define USB_ISTAT_TOKDNE_MASK                    0x8u
-#define USB_ISTAT_TOKDNE_SHIFT                   3
-#define USB_ISTAT_SLEEP_MASK                     0x10u
-#define USB_ISTAT_SLEEP_SHIFT                    4
-#define USB_ISTAT_RESUME_MASK                    0x20u
-#define USB_ISTAT_RESUME_SHIFT                   5
-#define USB_ISTAT_ATTACH_MASK                    0x40u
-#define USB_ISTAT_ATTACH_SHIFT                   6
-#define USB_ISTAT_STALL_MASK                     0x80u
-#define USB_ISTAT_STALL_SHIFT                    7
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK                  0x1u
-#define USB_INTEN_USBRSTEN_SHIFT                 0
-#define USB_INTEN_ERROREN_MASK                   0x2u
-#define USB_INTEN_ERROREN_SHIFT                  1
-#define USB_INTEN_SOFTOKEN_MASK                  0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT                 2
-#define USB_INTEN_TOKDNEEN_MASK                  0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT                 3
-#define USB_INTEN_SLEEPEN_MASK                   0x10u
-#define USB_INTEN_SLEEPEN_SHIFT                  4
-#define USB_INTEN_RESUMEEN_MASK                  0x20u
-#define USB_INTEN_RESUMEEN_SHIFT                 5
-#define USB_INTEN_ATTACHEN_MASK                  0x40u
-#define USB_INTEN_ATTACHEN_SHIFT                 6
-#define USB_INTEN_STALLEN_MASK                   0x80u
-#define USB_INTEN_STALLEN_SHIFT                  7
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK                  0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT                 0
-#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT                1
-#define USB_ERRSTAT_CRC16_MASK                   0x4u
-#define USB_ERRSTAT_CRC16_SHIFT                  2
-#define USB_ERRSTAT_DFN8_MASK                    0x8u
-#define USB_ERRSTAT_DFN8_SHIFT                   3
-#define USB_ERRSTAT_BTOERR_MASK                  0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT                 4
-#define USB_ERRSTAT_DMAERR_MASK                  0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT                 5
-#define USB_ERRSTAT_BTSERR_MASK                  0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT                 7
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK                  0x1u
-#define USB_ERREN_PIDERREN_SHIFT                 0
-#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT                1
-#define USB_ERREN_CRC16EN_MASK                   0x4u
-#define USB_ERREN_CRC16EN_SHIFT                  2
-#define USB_ERREN_DFN8EN_MASK                    0x8u
-#define USB_ERREN_DFN8EN_SHIFT                   3
-#define USB_ERREN_BTOERREN_MASK                  0x10u
-#define USB_ERREN_BTOERREN_SHIFT                 4
-#define USB_ERREN_DMAERREN_MASK                  0x20u
-#define USB_ERREN_DMAERREN_SHIFT                 5
-#define USB_ERREN_BTSERREN_MASK                  0x80u
-#define USB_ERREN_BTSERREN_SHIFT                 7
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK                        0x4u
-#define USB_STAT_ODD_SHIFT                       2
-#define USB_STAT_TX_MASK                         0x8u
-#define USB_STAT_TX_SHIFT                        3
-#define USB_STAT_ENDP_MASK                       0xF0u
-#define USB_STAT_ENDP_SHIFT                      4
-#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK                  0x1u
-#define USB_CTL_USBENSOFEN_SHIFT                 0
-#define USB_CTL_ODDRST_MASK                      0x2u
-#define USB_CTL_ODDRST_SHIFT                     1
-#define USB_CTL_RESUME_MASK                      0x4u
-#define USB_CTL_RESUME_SHIFT                     2
-#define USB_CTL_HOSTMODEEN_MASK                  0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT                 3
-#define USB_CTL_RESET_MASK                       0x10u
-#define USB_CTL_RESET_SHIFT                      4
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
-#define USB_CTL_SE0_MASK                         0x40u
-#define USB_CTL_SE0_SHIFT                        6
-#define USB_CTL_JSTATE_MASK                      0x80u
-#define USB_CTL_JSTATE_SHIFT                     7
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK                       0x7Fu
-#define USB_ADDR_ADDR_SHIFT                      0
-#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK                       0x80u
-#define USB_ADDR_LSEN_SHIFT                      7
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT                 1
-#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK                     0xFFu
-#define USB_FRMNUML_FRM_SHIFT                    0
-#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK                     0x7u
-#define USB_FRMNUMH_FRM_SHIFT                    0
-#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK                0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT               0
-#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK                  0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT                 4
-#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK                     0xFFu
-#define USB_SOFTHLD_CNT_SHIFT                    0
-#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT                 0
-#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT                 0
-#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK                    0x1u
-#define USB_ENDPT_EPHSHK_SHIFT                   0
-#define USB_ENDPT_EPSTALL_MASK                   0x2u
-#define USB_ENDPT_EPSTALL_SHIFT                  1
-#define USB_ENDPT_EPTXEN_MASK                    0x4u
-#define USB_ENDPT_EPTXEN_SHIFT                   2
-#define USB_ENDPT_EPRXEN_MASK                    0x8u
-#define USB_ENDPT_EPRXEN_SHIFT                   3
-#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT                 4
-#define USB_ENDPT_RETRYDIS_MASK                  0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT                 6
-#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT                7
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK                     0x40u
-#define USB_USBCTRL_PDE_SHIFT                    6
-#define USB_USBCTRL_SUSP_MASK                    0x80u
-#define USB_USBCTRL_SUSP_SHIFT                   7
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK                    0x10u
-#define USB_OBSERVE_DMPD_SHIFT                   4
-#define USB_OBSERVE_DPPD_MASK                    0x40u
-#define USB_OBSERVE_DPPD_SHIFT                   6
-#define USB_OBSERVE_DPPU_MASK                    0x80u
-#define USB_OBSERVE_DPPU_SHIFT                   7
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
-#define USB_USBTRC0_SYNC_DET_MASK                0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT               1
-#define USB_USBTRC0_USBRESMEN_MASK               0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT              5
-#define USB_USBTRC0_USBRESET_MASK                0x80u
-#define USB_USBTRC0_USBRESET_SHIFT               7
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT               0
-#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK                        (0x3FU)
+#define USB_PERID_ID_SHIFT                       (0U)
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK                      (0x3FU)
+#define USB_IDCOMP_NID_SHIFT                     (0U)
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK                         (0xFFU)
+#define USB_REV_REV_SHIFT                        (0U)
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK                  (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT                 (0U)
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK                  (0xF8U)
+#define USB_ADDINFO_IRQNUM_SHIFT                 (3U)
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_AVBUSCHG_MASK               (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              (0U)
+#define USB_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK             (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK             (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT               (6U)
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK                  (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT                 (7U)
+#define USB_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control Register */
+#define USB_OTGICR_AVBUSEN_MASK                  (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT                 (0U)
+#define USB_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK                  (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT                 (2U)
+#define USB_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK                (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT               (3U)
+#define USB_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK              (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT             (5U)
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT               (6U)
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK                     (0x80U)
+#define USB_OTGICR_IDEN_SHIFT                    (7U)
+#define USB_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_AVBUSVLD_MASK                (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               (0U)
+#define USB_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK                (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT               (2U)
+#define USB_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK                (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT               (3U)
+#define USB_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              (6U)
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK                      (0x80U)
+#define USB_OTGSTAT_ID_SHIFT                     (7U)
+#define USB_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK                    (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT                   (2U)
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT                   (4U)
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT                   (5U)
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT                  (7U)
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK                    (0x1U)
+#define USB_ISTAT_USBRST_SHIFT                   (0U)
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     (0x2U)
+#define USB_ISTAT_ERROR_SHIFT                    (1U)
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT                   (2U)
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT                   (3U)
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT                    (4U)
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    (0x20U)
+#define USB_ISTAT_RESUME_SHIFT                   (5U)
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT                   (6U)
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     (0x80U)
+#define USB_ISTAT_STALL_SHIFT                    (7U)
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK                  (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT                 (0U)
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   (0x2U)
+#define USB_INTEN_ERROREN_SHIFT                  (1U)
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT                  (4U)
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT                 (5U)
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT                 (6U)
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   (0x80U)
+#define USB_INTEN_STALLEN_SHIFT                  (7U)
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT                (1U)
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT                  (2U)
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT                   (3U)
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK                  (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT                 (0U)
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT                  (2U)
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT                   (3U)
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT                 (4U)
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT                 (5U)
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT                 (7U)
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK                        (0x4U)
+#define USB_STAT_ODD_SHIFT                       (2U)
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         (0x8U)
+#define USB_STAT_TX_SHIFT                        (3U)
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       (0xF0U)
+#define USB_STAT_ENDP_SHIFT                      (4U)
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK                  (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT                 (0U)
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      (0x2U)
+#define USB_CTL_ODDRST_SHIFT                     (1U)
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      (0x4U)
+#define USB_CTL_RESUME_SHIFT                     (2U)
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT                 (3U)
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       (0x10U)
+#define USB_CTL_RESET_SHIFT                      (4U)
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         (0x40U)
+#define USB_CTL_SE0_SHIFT                        (6U)
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      (0x80U)
+#define USB_CTL_JSTATE_SHIFT                     (7U)
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK                       (0x7FU)
+#define USB_ADDR_ADDR_SHIFT                      (0U)
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       (0x80U)
+#define USB_ADDR_LSEN_SHIFT                      (7U)
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page Register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number Register Low */
+#define USB_FRMNUML_FRM_MASK                     (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT                    (0U)
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number Register High */
+#define USB_FRMNUMH_FRM_MASK                     (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT                    (0U)
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK                (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT               (0U)
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT                 (4U)
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold Register */
+#define USB_SOFTHLD_CNT_MASK                     (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT                    (0U)
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK                    (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT                   (0U)
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT                  (1U)
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT                   (2U)
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT                   (3U)
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT                 (6U)
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT                (7U)
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_PDE_MASK                     (0x40U)
+#define USB_USBCTRL_PDE_SHIFT                    (6U)
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT                   (7U)
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK                    (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT                   (4U)
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT                   (6U)
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT                   (7U)
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control Register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT               (7U)
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK                (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT               (0U)
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
 
 /*!
  * @}
@@ -13984,7 +12509,6 @@ typedef struct {
 #define USB0_BASE                                (0x40072000u)
 /** Peripheral USB0 base pointer */
 #define USB0                                     ((USB_Type *)USB0_BASE)
-#define USB0_BASE_PTR                            (USB0)
 /** Array initializer of USB peripheral base addresses */
 #define USB_BASE_ADDRS                           { USB0_BASE }
 /** Array initializer of USB peripheral base pointers */
@@ -13992,70 +12516,6 @@ typedef struct {
 /** Interrupt vectors for the USB peripheral type */
 #define USB_IRQS                                 { USB0_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- USB - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register instance definitions */
-/* USB0 */
-#define USB0_PERID                               USB_PERID_REG(USB0)
-#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
-#define USB0_REV                                 USB_REV_REG(USB0)
-#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
-#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
-#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
-#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
-#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
-#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
-#define USB0_INTEN                               USB_INTEN_REG(USB0)
-#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
-#define USB0_ERREN                               USB_ERREN_REG(USB0)
-#define USB0_STAT                                USB_STAT_REG(USB0)
-#define USB0_CTL                                 USB_CTL_REG(USB0)
-#define USB0_ADDR                                USB_ADDR_REG(USB0)
-#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
-#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
-#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
-#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
-#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
-#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
-#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
-#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
-#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
-#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
-#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
-#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
-#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
-#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
-#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
-#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
-#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
-#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
-#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
-#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
-#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
-#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
-#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
-#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
-#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
-#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
-#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
-#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
-
-/* USB - Register array accessors */
-#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group USB_Peripheral_Access_Layer */
@@ -14079,30 +12539,7 @@ typedef struct {
   __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
   __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
   __IO uint32_t TIMER2;                            /**< TIMER2 register, offset: 0x18 */
-} USBDCD_Type, *USBDCD_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- USBDCD - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
- * @{
- */
-
-
-/* USBDCD - Register accessors */
-#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
-#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
-#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
-#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
-#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
-#define USBDCD_TIMER2_REG(base)                  ((base)->TIMER2)
-
-/*!
- * @}
- */ /* end of group USBDCD_Register_Accessor_Macros */
-
+} USBDCD_Type;
 
 /* ----------------------------------------------------------------------------
    -- USBDCD Register Masks
@@ -14113,57 +12550,72 @@ typedef struct {
  * @{
  */
 
-/* CONTROL Bit Fields */
-#define USBDCD_CONTROL_IACK_MASK                 0x1u
-#define USBDCD_CONTROL_IACK_SHIFT                0
-#define USBDCD_CONTROL_IF_MASK                   0x100u
-#define USBDCD_CONTROL_IF_SHIFT                  8
-#define USBDCD_CONTROL_IE_MASK                   0x10000u
-#define USBDCD_CONTROL_IE_SHIFT                  16
-#define USBDCD_CONTROL_START_MASK                0x1000000u
-#define USBDCD_CONTROL_START_SHIFT               24
-#define USBDCD_CONTROL_SR_MASK                   0x2000000u
-#define USBDCD_CONTROL_SR_SHIFT                  25
-/* CLOCK Bit Fields */
-#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
-#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
-#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
-#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
-#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
-/* STATUS Bit Fields */
-#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
-#define USBDCD_STATUS_SEQ_RES_SHIFT              16
-#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
-#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
-#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
-#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
-#define USBDCD_STATUS_ERR_MASK                   0x100000u
-#define USBDCD_STATUS_ERR_SHIFT                  20
-#define USBDCD_STATUS_TO_MASK                    0x200000u
-#define USBDCD_STATUS_TO_SHIFT                   21
-#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
-#define USBDCD_STATUS_ACTIVE_SHIFT               22
-/* TIMER0 Bit Fields */
-#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
-#define USBDCD_TIMER0_TUNITCON_SHIFT             0
-#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
-#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
-#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
-#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
-/* TIMER1 Bit Fields */
-#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
-#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
-#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
-#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
-#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
-#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
-/* TIMER2 Bit Fields */
-#define USBDCD_TIMER2_CHECK_DM_MASK              0xFu
-#define USBDCD_TIMER2_CHECK_DM_SHIFT             0
-#define USBDCD_TIMER2_CHECK_DM(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
-#define USBDCD_TIMER2_TVDPSRC_CON_MASK           0x3FF0000u
-#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT          16
-#define USBDCD_TIMER2_TVDPSRC_CON(x)             (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
+/*! @name CONTROL - Control register */
+#define USBDCD_CONTROL_IACK_MASK                 (0x1U)
+#define USBDCD_CONTROL_IACK_SHIFT                (0U)
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   (0x100U)
+#define USBDCD_CONTROL_IF_SHIFT                  (8U)
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   (0x10000U)
+#define USBDCD_CONTROL_IE_SHIFT                  (16U)
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_START_MASK                (0x1000000U)
+#define USBDCD_CONTROL_START_SHIFT               (24U)
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   (0x2000000U)
+#define USBDCD_CONTROL_SR_SHIFT                  (25U)
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
+
+/*! @name CLOCK - Clock register */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             (0x1U)
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            (0U)
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            (0xFFCU)
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           (2U)
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+
+/*! @name STATUS - Status register */
+#define USBDCD_STATUS_SEQ_RES_MASK               (0x30000U)
+#define USBDCD_STATUS_SEQ_RES_SHIFT              (16U)
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              (0xC0000U)
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             (18U)
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   (0x100000U)
+#define USBDCD_STATUS_ERR_SHIFT                  (20U)
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    (0x200000U)
+#define USBDCD_STATUS_TO_SHIFT                   (21U)
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                (0x400000U)
+#define USBDCD_STATUS_ACTIVE_SHIFT               (22U)
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
+
+/*! @name TIMER0 - TIMER0 register */
+#define USBDCD_TIMER0_TUNITCON_MASK              (0xFFFU)
+#define USBDCD_TIMER0_TUNITCON_SHIFT             (0U)
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             (0x3FF0000U)
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            (16U)
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+
+/*! @name TIMER1 - TIMER1 register */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            (0x3FFU)
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           (0U)
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             (0x3FF0000U)
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            (16U)
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+
+/*! @name TIMER2 - TIMER2 register */
+#define USBDCD_TIMER2_CHECK_DM_MASK              (0xFU)
+#define USBDCD_TIMER2_CHECK_DM_SHIFT             (0U)
+#define USBDCD_TIMER2_CHECK_DM(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_CHECK_DM_SHIFT)) & USBDCD_TIMER2_CHECK_DM_MASK)
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK           (0x3FF0000U)
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT          (16U)
+#define USBDCD_TIMER2_TVDPSRC_CON(x)             (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_TVDPSRC_CON_MASK)
+
 
 /*!
  * @}
@@ -14175,7 +12627,6 @@ typedef struct {
 #define USBDCD_BASE                              (0x40035000u)
 /** Peripheral USBDCD base pointer */
 #define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
-#define USBDCD_BASE_PTR                          (USBDCD)
 /** Array initializer of USBDCD peripheral base addresses */
 #define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
 /** Array initializer of USBDCD peripheral base pointers */
@@ -14183,30 +12634,6 @@ typedef struct {
 /** Interrupt vectors for the USBDCD peripheral type */
 #define USBDCD_IRQS                              { USBDCD_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- USBDCD - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
- * @{
- */
-
-
-/* USBDCD - Register instance definitions */
-/* USBDCD */
-#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
-#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
-#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
-#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
-#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
-#define USBDCD_TIMER2                            USBDCD_TIMER2_REG(USBDCD)
-
-/*!
- * @}
- */ /* end of group USBDCD_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group USBDCD_Peripheral_Access_Layer */
@@ -14225,26 +12652,7 @@ typedef struct {
 typedef struct {
   __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
   __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type, *VREF_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- VREF - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register accessors */
-#define VREF_TRM_REG(base)                       ((base)->TRM)
-#define VREF_SC_REG(base)                        ((base)->SC)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
+} VREF_Type;
 
 /* ----------------------------------------------------------------------------
    -- VREF Register Masks
@@ -14255,24 +12663,31 @@ typedef struct {
  * @{
  */
 
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK                       0x3Fu
-#define VREF_TRM_TRIM_SHIFT                      0
-#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK                     0x40u
-#define VREF_TRM_CHOPEN_SHIFT                    6
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK                     0x3u
-#define VREF_SC_MODE_LV_SHIFT                    0
-#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK                      0x4u
-#define VREF_SC_VREFST_SHIFT                     2
-#define VREF_SC_ICOMPEN_MASK                     0x20u
-#define VREF_SC_ICOMPEN_SHIFT                    5
-#define VREF_SC_REGEN_MASK                       0x40u
-#define VREF_SC_REGEN_SHIFT                      6
-#define VREF_SC_VREFEN_MASK                      0x80u
-#define VREF_SC_VREFEN_SHIFT                     7
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK                       (0x3FU)
+#define VREF_TRM_TRIM_SHIFT                      (0U)
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT                    (6U)
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK                     (0x3U)
+#define VREF_SC_MODE_LV_SHIFT                    (0U)
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      (0x4U)
+#define VREF_SC_VREFST_SHIFT                     (2U)
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT                    (5U)
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       (0x40U)
+#define VREF_SC_REGEN_SHIFT                      (6U)
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      (0x80U)
+#define VREF_SC_VREFEN_SHIFT                     (7U)
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+
 
 /*!
  * @}
@@ -14284,32 +12699,11 @@ typedef struct {
 #define VREF_BASE                                (0x40074000u)
 /** Peripheral VREF base pointer */
 #define VREF                                     ((VREF_Type *)VREF_BASE)
-#define VREF_BASE_PTR                            (VREF)
 /** Array initializer of VREF peripheral base addresses */
 #define VREF_BASE_ADDRS                          { VREF_BASE }
 /** Array initializer of VREF peripheral base pointers */
 #define VREF_BASE_PTRS                           { VREF }
 
-/* ----------------------------------------------------------------------------
-   -- VREF - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register instance definitions */
-/* VREF */
-#define VREF_TRM                                 VREF_TRM_REG(VREF)
-#define VREF_SC                                  VREF_SC_REG(VREF)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group VREF_Peripheral_Access_Layer */
@@ -14338,36 +12732,7 @@ typedef struct {
   __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
   __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
   __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
-} WDOG_Type, *WDOG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
-   -- WDOG - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register accessors */
-#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
-#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
-#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
-#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
-#define WDOG_WINH_REG(base)                      ((base)->WINH)
-#define WDOG_WINL_REG(base)                      ((base)->WINL)
-#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
-#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
-#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
-#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
-#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
-#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
+} WDOG_Type;
 
 /* ----------------------------------------------------------------------------
    -- WDOG Register Masks
@@ -14378,75 +12743,99 @@ typedef struct {
  * @{
  */
 
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT                0
-#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT                1
-#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
-#define WDOG_STCTRLH_WINEN_MASK                  0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT                 3
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
-#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT                 5
-#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT                6
-#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT                7
-#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
-#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT               11
-#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT               12
-#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT                15
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
-#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT               0
-#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT                  0
-#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT                   0
-#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
-#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
-#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
-#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
-#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
-#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT                8
-#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN_MASK                 (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT                (0U)
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT                (1U)
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              (2U)
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT                 (3U)
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           (4U)
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT                 (5U)
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT                (6U)
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT                (7U)
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              (10U)
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT               (11U)
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT               (12U)
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           (14U)
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG_MASK                 (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT                (15U)
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+#define WDOG_TOVALH_TOVALHIGH_MASK               (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              (0U)
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+#define WDOG_TOVALL_TOVALLOW_MASK                (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT               (0U)
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+
+/*! @name WINH - Watchdog Window Register High */
+#define WDOG_WINH_WINHIGH_MASK                   (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT                  (0U)
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+
+/*! @name WINL - Watchdog Window Register Low */
+#define WDOG_WINL_WINLOW_MASK                    (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT                   (0U)
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+
+/*! @name REFRESH - Watchdog Refresh register */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+
+/*! @name UNLOCK - Watchdog Unlock register */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+
+/*! @name RSTCNT - Watchdog Reset Count register */
+#define WDOG_RSTCNT_RSTCNT_MASK                  (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 (0U)
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+
+/*! @name PRESC - Watchdog Prescaler register */
+#define WDOG_PRESC_PRESCVAL_MASK                 (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT                (8U)
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
 
 /*!
  * @}
@@ -14458,7 +12847,6 @@ typedef struct {
 #define WDOG_BASE                                (0x40052000u)
 /** Peripheral WDOG base pointer */
 #define WDOG                                     ((WDOG_Type *)WDOG_BASE)
-#define WDOG_BASE_PTR                            (WDOG)
 /** Array initializer of WDOG peripheral base addresses */
 #define WDOG_BASE_ADDRS                          { WDOG_BASE }
 /** Array initializer of WDOG peripheral base pointers */
@@ -14466,36 +12854,6 @@ typedef struct {
 /** Interrupt vectors for the WDOG peripheral type */
 #define WDOG_IRQS                                { WDOG_EWM_IRQn }
 
-/* ----------------------------------------------------------------------------
-   -- WDOG - Register accessor macros
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register instance definitions */
-/* WDOG */
-#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
-#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
-#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
-#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
-#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
-#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
-#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
-#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
-#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
-#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
-#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
-#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
 /*!
  * @}
  */ /* end of group WDOG_Peripheral_Access_Layer */
@@ -14523,14 +12881,56 @@ typedef struct {
 
 
 /* ----------------------------------------------------------------------------
-   -- Backward Compatibility
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
  * @{
  */
 
+#define DSPI0                                    SPI0
+#define DSPI1                                    SPI1
+#define DSPI2                                    SPI2
+#define FLEXCAN0                                 CAN0
+#define FLEXCAN1                                 CAN1
 #define PTA_BASE                                 GPIOA_BASE
 #define PTA                                      GPIOA
 #define PTB_BASE                                 GPIOB_BASE
@@ -14541,6 +12941,7 @@ typedef struct {
 #define PTD                                      GPIOD
 #define PTE_BASE                                 GPIOE_BASE
 #define PTE                                      GPIOE
+#define DMAMUX0                                  DMAMUX
 #define WP7816_T_TYPE0                           WP7816T0
 #define WP7816_T_TYPE1                           WP7816T1
 #define UART_WP7816_T_TYPE0_WI_MASK              UART_WP7816T0_WI_MASK
@@ -14567,14 +12968,14 @@ typedef struct {
 #define DAC_DATH_DATA_MASK                       DAC_DATH_DATA1_MASK
 #define DAC_DATH_DATA_SHIFT                      DAC_DATH_DATA1_SHIFT
 #define DAC_DATH_DATA(x)                         DAC_DATH_DATA1(x)
-#define MCG_S_LOLS0_MASK                         MCG_S_LOLS_MASK
-#define MCG_S_LOLS0_SHIFT                        MCG_S_LOLS_SHIFT
 #define SIM_SCGC6_RNGA_MASK                      This_symbol_has_been_deprecated
 #define SIM_SCGC6_RNGA_SHIFT                     This_symbol_has_been_deprecated
 #define Watchdog_IRQn                            WDOG_EWM_IRQn
 #define Watchdog_IRQHandler                      WDOG_EWM_IRQHandler
 #define LPTimer_IRQn                             LPTMR0_IRQn
 #define LPTimer_IRQHandler                       LPTMR0_IRQHandler
+#define LLW_IRQn                                 LLWU_IRQn
+#define LLW_IRQHandler                           LLWU_IRQHandler
 
 /* Compatibility defines for compatibility with differing module names between
  * MK60 and MKW22 headers */
@@ -14584,20 +12985,8 @@ typedef struct {
 
 /*!
  * @}
- */ /* end of group Backward_Compatibility_Symbols */
+ */ /* end of group SDK_Compatibility_Symbols */
 
 
-#else /* #if !defined(MK60D10_H_) */
-  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
-  #if (MCU_MEM_MAP_VERSION != 0x0100u)
-    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
-      #warning There are included two not compatible versions of memory maps. Please check possible differences.
-    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
-  #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
-#endif  /* #if !defined(MK60D10_H_) */
-
-#ifdef __cplusplus
-}
-#endif
+#endif  /* _MK60D10_H_ */
 
-/* MK60D10.h, eof. */
diff --git a/cpu/kw41z/Makefile b/cpu/kw41z/Makefile
index 68605a469b55f..b478eba931af9 100644
--- a/cpu/kw41z/Makefile
+++ b/cpu/kw41z/Makefile
@@ -1,8 +1,9 @@
 # define the module that is build
 MODULE = cpu
 
-# add a list of subdirectories, that should also be build
-DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
+# add a list of directories that should also be built
+DIRS += periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
+DIRS += vendor/XCVR/MKW41Z4
 
 # (file triggers compiler bug. see #5775)
 SRC_NOLTO += vectors.c
diff --git a/cpu/kw41z/Makefile.include b/cpu/kw41z/Makefile.include
index f5dd10f9178d3..ea91063aba79b 100644
--- a/cpu/kw41z/Makefile.include
+++ b/cpu/kw41z/Makefile.include
@@ -21,4 +21,11 @@ export COMMON_STARTUP = $(KINETIS_COMMON)
 # add the CPU specific system calls implementations for the linker
 export UNDEF += $(BINDIR)/cpu/vectors.o
 
+# Vendor supplied transceiver driver
+export INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/Common
+export INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/OSAbstraction/Interface
+export INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/XCVR/MKW41Z4
+
+export USEMODULE += mcux_xcvr
+
 include $(RIOTMAKE)/arch/cortexm.inc.mk
diff --git a/cpu/kw41z/include/vendor/MKW21Z4.h b/cpu/kw41z/include/vendor/MKW21Z4.h
index c37f661c67e03..018e3e142028e 100644
--- a/cpu/kw41z/include/vendor/MKW21Z4.h
+++ b/cpu/kw41z/include/vendor/MKW21Z4.h
@@ -5,19 +5,18 @@
 **
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          GNU C Compiler
-**                          GNU C Compiler - CodeSourcery Sourcery G++
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    MKW41Z512RM Rev. 0.1, 04/2016
 **     Version:             rev. 1.0, 2015-09-23
-**     Build:               b160720
+**     Build:               b170112
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MKW21Z4
 **
 **     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -28,7 +27,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -43,8 +42,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2015-09-23)
@@ -85,6 +84,9 @@
 #define NUMBER_OF_INT_VECTORS 48                 /**< Number of interrupts in the Vector table */
 
 typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
   /* Core interrupts */
   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
   HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
@@ -148,13 +150,114 @@ typedef enum IRQn {
 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
 
 #include "core_cm0plus.h"              /* Core Peripheral Access Layer */
-#include "system_MKW21Z4.h"            /* Device specific configuration file */
 
 /*!
  * @}
  */ /* end of group Cortex_Core_Configuration */
 
 
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
+    kDmaRequestMux0LPUART0Rx        = 2|0x100U,    /**< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx        = 3|0x100U,    /**< LPUART0 Transmit. */
+    kDmaRequestMux0Reserved4        = 4|0x100U,    /**< Reserved4 */
+    kDmaRequestMux0Reserved5        = 5|0x100U,    /**< Reserved5 */
+    kDmaRequestMux0Reserved6        = 6|0x100U,    /**< Reserved6 */
+    kDmaRequestMux0Reserved7        = 7|0x100U,    /**< Reserved7 */
+    kDmaRequestMux0Reserved8        = 8|0x100U,    /**< Reserved8 */
+    kDmaRequestMux0Reserved9        = 9|0x100U,    /**< Reserved9 */
+    kDmaRequestMux0Reserved10       = 10|0x100U,   /**< Reserved10 */
+    kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
+    kDmaRequestMux0Reserved12       = 12|0x100U,   /**< Reserved12 */
+    kDmaRequestMux0Reserved13       = 13|0x100U,   /**< Reserved13 */
+    kDmaRequestMux0Reserved14       = 14|0x100U,   /**< Reserved14 */
+    kDmaRequestMux0Reserved15       = 15|0x100U,   /**< Reserved15 */
+    kDmaRequestMux0SPI0Rx           = 16|0x100U,   /**< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx           = 17|0x100U,   /**< SPI0 Transmit. */
+    kDmaRequestMux0SPI1Rx           = 18|0x100U,   /**< SPI1 Receive. */
+    kDmaRequestMux0SPI1Tx           = 19|0x100U,   /**< SPI1 Transmit. */
+    kDmaRequestMux0LTC0InputFIFO    = 20|0x100U,   /**< LTC0 Input FIFO. */
+    kDmaRequestMux0LTC0OutputFIFO   = 21|0x100U,   /**< LTC0 Output FIFO. */
+    kDmaRequestMux0I2C0             = 22|0x100U,   /**< I2C0. */
+    kDmaRequestMux0I2C1             = 23|0x100U,   /**< I2C1. */
+    kDmaRequestMux0TPM0Channel0     = 24|0x100U,   /**< TPM0 C0V. */
+    kDmaRequestMux0TPM0Channel1     = 25|0x100U,   /**< TPM0 C1V. */
+    kDmaRequestMux0TPM0Channel2     = 26|0x100U,   /**< TPM0 C2V. */
+    kDmaRequestMux0TPM0Channel3     = 27|0x100U,   /**< TPM0 C3V. */
+    kDmaRequestMux0Reserved28       = 28|0x100U,   /**< Reserved28 */
+    kDmaRequestMux0Reserved29       = 29|0x100U,   /**< Reserved29 */
+    kDmaRequestMux0Reserved30       = 30|0x100U,   /**< Reserved30 */
+    kDmaRequestMux0Reserved31       = 31|0x100U,   /**< Reserved31 */
+    kDmaRequestMux0TPM1Channel0     = 32|0x100U,   /**< TPM1 C0V. */
+    kDmaRequestMux0TPM1Channel1     = 33|0x100U,   /**< TPM1 C1V. */
+    kDmaRequestMux0TPM2Channel0     = 34|0x100U,   /**< TPM2 C0V. */
+    kDmaRequestMux0TPM2Channel1     = 35|0x100U,   /**< TPM2 C1V. */
+    kDmaRequestMux0Reserved36       = 36|0x100U,   /**< Reserved36 */
+    kDmaRequestMux0Reserved37       = 37|0x100U,   /**< Reserved37 */
+    kDmaRequestMux0Reserved38       = 38|0x100U,   /**< Reserved38 */
+    kDmaRequestMux0Reserved39       = 39|0x100U,   /**< Reserved39 */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
+    kDmaRequestMux0Reserved41       = 41|0x100U,   /**< Reserved41 */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
+    kDmaRequestMux0Reserved43       = 43|0x100U,   /**< Reserved43 */
+    kDmaRequestMux0Reserved44       = 44|0x100U,   /**< Reserved44 */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
+    kDmaRequestMux0Reserved46       = 46|0x100U,   /**< Reserved46 */
+    kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT. */
+    kDmaRequestMux0Reserved48       = 48|0x100U,   /**< Reserved48 */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
+    kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
+    kDmaRequestMux0Reserved52       = 52|0x100U,   /**< Reserved52 */
+    kDmaRequestMux0Reserved53       = 53|0x100U,   /**< Reserved53 */
+    kDmaRequestMux0TPM0Overflow     = 54|0x100U,   /**< TPM0. */
+    kDmaRequestMux0TPM1Overflow     = 55|0x100U,   /**< TPM1. */
+    kDmaRequestMux0TPM2Overflow     = 56|0x100U,   /**< TPM2. */
+    kDmaRequestMux0TSI0             = 57|0x100U,   /**< TSI0. */
+    kDmaRequestMux0Reserved58       = 58|0x100U,   /**< Reserved58 */
+    kDmaRequestMux0Reserved59       = 59|0x100U,   /**< Reserved59 */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
 /* ----------------------------------------------------------------------------
    -- Device Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -434,6 +537,8 @@ typedef struct {
 #define ADC_BASE_ADDRS                           { ADC0_BASE }
 /** Array initializer of ADC peripheral base pointers */
 #define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
 
 /*!
  * @}
@@ -902,6 +1007,8 @@ typedef struct {
 #define CMP_BASE_ADDRS                           { CMP0_BASE }
 /** Array initializer of CMP peripheral base pointers */
 #define CMP_BASE_PTRS                            { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn }
 
 /*!
  * @}
@@ -1041,6 +1148,8 @@ typedef struct {
 #define CMT_BASE_ADDRS                           { CMT_BASE }
 /** Array initializer of CMT peripheral base pointers */
 #define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
 
 /*!
  * @}
@@ -1168,6 +1277,8 @@ typedef struct {
 #define DAC_BASE_ADDRS                           { DAC0_BASE }
 /** Array initializer of DAC peripheral base pointers */
 #define DAC_BASE_PTRS                            { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn }
 
 /*!
  * @}
@@ -1946,6 +2057,8 @@ typedef struct {
 #define DMA_BASE_ADDRS                           { DMA_BASE }
 /** Array initializer of DMA peripheral base pointers */
 #define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
 
 /*!
  * @}
@@ -2394,6 +2507,8 @@ typedef struct {
 #define FTFA_BASE_ADDRS                          { FTFA_BASE }
 /** Array initializer of FTFA peripheral base pointers */
 #define FTFA_BASE_PTRS                           { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS               { FTFA_IRQn }
 
 /*!
  * @}
@@ -3184,6 +3299,8 @@ typedef struct {
 #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
 /** Array initializer of I2C peripheral base pointers */
 #define I2C_BASE_PTRS                            { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
 
 /*!
  * @}
@@ -3419,6 +3536,8 @@ typedef struct {
 #define LLWU_BASE_ADDRS                          { LLWU_BASE }
 /** Array initializer of LLWU peripheral base pointers */
 #define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
 
 /*!
  * @}
@@ -3510,6 +3629,8 @@ typedef struct {
 #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
 /** Array initializer of LPTMR peripheral base pointers */
 #define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
 
 /*!
  * @}
@@ -3820,6 +3941,9 @@ typedef struct {
 #define LPUART_BASE_ADDRS                        { LPUART0_BASE }
 /** Array initializer of LPUART peripheral base pointers */
 #define LPUART_BASE_PTRS                         { LPUART0 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn }
 
 /*!
  * @}
@@ -4089,6 +4213,8 @@ typedef struct {
 #define LTC_BASE_ADDRS                           { LTC0_BASE }
 /** Array initializer of LTC peripheral base pointers */
 #define LTC_BASE_PTRS                            { LTC0 }
+/** Interrupt vectors for the LTC peripheral type */
+#define LTC_IRQS                                 { LTC0_IRQn }
 
 /*!
  * @}
@@ -4270,6 +4396,8 @@ typedef struct {
 #define MCG_BASE_ADDRS                           { MCG_BASE }
 /** Array initializer of MCG peripheral base pointers */
 #define MCG_BASE_PTRS                            { MCG }
+/** Interrupt vectors for the MCG peripheral type */
+#define MCG_IRQS                                 { MCG_IRQn }
 
 /*!
  * @}
@@ -5020,6 +5148,8 @@ typedef struct {
 #define PIT_BASE_ADDRS                           { PIT_BASE }
 /** Array initializer of PIT peripheral base pointers */
 #define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { { PIT_IRQn, PIT_IRQn } }
 
 /*!
  * @}
@@ -5111,6 +5241,8 @@ typedef struct {
 #define PMC_BASE_ADDRS                           { PMC_BASE }
 /** Array initializer of PMC peripheral base pointers */
 #define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_DCDC_IRQn }
 
 /*!
  * @}
@@ -5217,6 +5349,8 @@ typedef struct {
 #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE }
 /** Array initializer of PORT peripheral base pointers */
 #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn }
 
 /*!
  * @}
@@ -6041,6 +6175,9 @@ typedef struct {
 #define RTC_BASE_ADDRS                           { RTC_BASE }
 /** Array initializer of RTC peripheral base pointers */
 #define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
 
 /*!
  * @}
@@ -6774,6 +6911,8 @@ typedef struct {
 #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
 /** Array initializer of SPI peripheral base pointers */
 #define SPI_BASE_PTRS                            { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
 
 /*!
  * @}
@@ -7015,6 +7154,8 @@ typedef struct {
 #define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
 /** Array initializer of TPM peripheral base pointers */
 #define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
 
 /*!
  * @}
@@ -7524,6 +7665,8 @@ typedef struct {
 #define TRNG_BASE_ADDRS                          { TRNG0_BASE }
 /** Array initializer of TRNG peripheral base pointers */
 #define TRNG_BASE_PTRS                           { TRNG0 }
+/** Interrupt vectors for the TRNG peripheral type */
+#define TRNG_IRQS                                { TRNG0_IRQn }
 
 /*!
  * @}
@@ -7639,6 +7782,8 @@ typedef struct {
 #define TSI_BASE_ADDRS                           { TSI0_BASE }
 /** Array initializer of TSI peripheral base pointers */
 #define TSI_BASE_PTRS                            { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS                                 { TSI0_IRQn }
 
 /*!
  * @}
@@ -12741,6 +12886,43 @@ typedef struct {
  */ /* end of group Peripheral_access_layer */
 
 
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
 /* ----------------------------------------------------------------------------
    -- SDK Compatibility
    ---------------------------------------------------------------------------- */
diff --git a/cpu/kw41z/include/vendor/MKW21Z4_features.h b/cpu/kw41z/include/vendor/MKW21Z4_features.h
new file mode 100644
index 0000000000000..f9e93c01dc69f
--- /dev/null
+++ b/cpu/kw41z/include/vendor/MKW21Z4_features.h
@@ -0,0 +1,1781 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2015-09-23
+**     Build:               b170228
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-09-23)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _MKW21Z4_FEATURES_H_
+#define _MKW21Z4_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ACMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACMP_COUNT (0)
+/* @brief ADC16 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC16_COUNT (1)
+/* @brief ADC12 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC12_COUNT (0)
+/* @brief AFE availability on the SoC. */
+#define FSL_FEATURE_SOC_AFE_COUNT (0)
+/* @brief AIPS availability on the SoC. */
+#define FSL_FEATURE_SOC_AIPS_COUNT (0)
+/* @brief AOI availability on the SoC. */
+#define FSL_FEATURE_SOC_AOI_COUNT (0)
+/* @brief AXBS availability on the SoC. */
+#define FSL_FEATURE_SOC_AXBS_COUNT (0)
+/* @brief ASMC availability on the SoC. */
+#define FSL_FEATURE_SOC_ASMC_COUNT (0)
+/* @brief CADC availability on the SoC. */
+#define FSL_FEATURE_SOC_CADC_COUNT (0)
+/* @brief FLEXCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
+/* @brief MMCAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
+/* @brief CMP availability on the SoC. */
+#define FSL_FEATURE_SOC_CMP_COUNT (1)
+/* @brief CMT availability on the SoC. */
+#define FSL_FEATURE_SOC_CMT_COUNT (1)
+/* @brief CNC availability on the SoC. */
+#define FSL_FEATURE_SOC_CNC_COUNT (0)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (0)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DAC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC32_COUNT (0)
+/* @brief DCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_DCDC_COUNT (1)
+/* @brief DDR availability on the SoC. */
+#define FSL_FEATURE_SOC_DDR_COUNT (0)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (0)
+/* @brief EDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_EDMA_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief DRY availability on the SoC. */
+#define FSL_FEATURE_SOC_DRY_COUNT (0)
+/* @brief DSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_DSPI_COUNT (2)
+/* @brief EMVSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+/* @brief ENC availability on the SoC. */
+#define FSL_FEATURE_SOC_ENC_COUNT (0)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_ENET_COUNT (0)
+/* @brief EWM availability on the SoC. */
+#define FSL_FEATURE_SOC_EWM_COUNT (0)
+/* @brief FB availability on the SoC. */
+#define FSL_FEATURE_SOC_FB_COUNT (0)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (3)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (0)
+/* @brief FSKDT availability on the SoC. */
+#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+/* @brief FTFA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFA_COUNT (1)
+/* @brief FTFE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFE_COUNT (0)
+/* @brief FTFL availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFL_COUNT (0)
+/* @brief FTM availability on the SoC. */
+#define FSL_FEATURE_SOC_FTM_COUNT (0)
+/* @brief FTMRA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+/* @brief FTMRE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+/* @brief FTMRH availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (3)
+/* @brief HSADC availability on the SoC. */
+#define FSL_FEATURE_SOC_HSADC_COUNT (0)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (0)
+/* @brief ICS availability on the SoC. */
+#define FSL_FEATURE_SOC_ICS_COUNT (0)
+/* @brief INTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
+/* @brief IRQ availability on the SoC. */
+#define FSL_FEATURE_SOC_IRQ_COUNT (0)
+/* @brief KBI availability on the SoC. */
+#define FSL_FEATURE_SOC_KBI_COUNT (0)
+/* @brief SLCD availability on the SoC. */
+#define FSL_FEATURE_SOC_SLCD_COUNT (0)
+/* @brief LCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_LCDC_COUNT (0)
+/* @brief LDO availability on the SoC. */
+#define FSL_FEATURE_SOC_LDO_COUNT (0)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (1)
+/* @brief LMEM availability on the SoC. */
+#define FSL_FEATURE_SOC_LMEM_COUNT (0)
+/* @brief LPI2C availability on the SoC. */
+#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
+/* @brief LPIT availability on the SoC. */
+#define FSL_FEATURE_SOC_LPIT_COUNT (0)
+/* @brief LPSCI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+/* @brief LPSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+/* @brief LPTPM availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (1)
+/* @brief LTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LTC_COUNT (1)
+/* @brief MC availability on the SoC. */
+#define FSL_FEATURE_SOC_MC_COUNT (0)
+/* @brief MCG availability on the SoC. */
+#define FSL_FEATURE_SOC_MCG_COUNT (1)
+/* @brief MCGLITE availability on the SoC. */
+#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MMAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMAU_COUNT (0)
+/* @brief MMDVSQ availability on the SoC. */
+#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+/* @brief SYSMPU availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSMPU_COUNT (0)
+/* @brief MSCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+/* @brief MSCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCM_COUNT (0)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief MU availability on the SoC. */
+#define FSL_FEATURE_SOC_MU_COUNT (0)
+/* @brief NFC availability on the SoC. */
+#define FSL_FEATURE_SOC_NFC_COUNT (0)
+/* @brief OPAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+/* @brief OSC availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC_COUNT (0)
+/* @brief OSC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC32_COUNT (0)
+/* @brief OTFAD availability on the SoC. */
+#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+/* @brief PDB availability on the SoC. */
+#define FSL_FEATURE_SOC_PDB_COUNT (0)
+/* @brief PCC availability on the SoC. */
+#define FSL_FEATURE_SOC_PCC_COUNT (0)
+/* @brief PGA availability on the SoC. */
+#define FSL_FEATURE_SOC_PGA_COUNT (0)
+/* @brief PIT availability on the SoC. */
+#define FSL_FEATURE_SOC_PIT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (3)
+/* @brief PWM availability on the SoC. */
+#define FSL_FEATURE_SOC_PWM_COUNT (0)
+/* @brief PWT availability on the SoC. */
+#define FSL_FEATURE_SOC_PWT_COUNT (0)
+/* @brief QuadSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
+/* @brief RCM availability on the SoC. */
+#define FSL_FEATURE_SOC_RCM_COUNT (1)
+/* @brief RFSYS availability on the SoC. */
+#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+/* @brief RFVBAT availability on the SoC. */
+#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_RNG_COUNT (0)
+/* @brief RNGB availability on the SoC. */
+#define FSL_FEATURE_SOC_RNGB_COUNT (0)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_RSIM_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCG availability on the SoC. */
+#define FSL_FEATURE_SOC_SCG_COUNT (0)
+/* @brief SCI availability on the SoC. */
+#define FSL_FEATURE_SOC_SCI_COUNT (0)
+/* @brief SDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_SDHC_COUNT (0)
+/* @brief SDRAM availability on the SoC. */
+#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+/* @brief SEMA42 availability on the SoC. */
+#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (0)
+/* @brief TMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TMR_COUNT (0)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (3)
+/* @brief TRGMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
+/* @brief TRIAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief TSI availability on the SoC. */
+#define FSL_FEATURE_SOC_TSI_COUNT (1)
+/* @brief TSTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
+/* @brief UART availability on the SoC. */
+#define FSL_FEATURE_SOC_UART_COUNT (0)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (0)
+/* @brief USBDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
+/* @brief USBHS availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHS_COUNT (0)
+/* @brief USBHSDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+/* @brief WDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_WDOG_COUNT (0)
+/* @brief XBAR availability on the SoC. */
+#define FSL_FEATURE_SOC_XBAR_COUNT (0)
+/* @brief XBARA availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARA_COUNT (0)
+/* @brief XBARB availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARB_COUNT (0)
+/* @brief XCVR availability on the SoC. */
+#define FSL_FEATURE_SOC_XCVR_COUNT (1)
+/* @brief XRDC availability on the SoC. */
+#define FSL_FEATURE_SOC_XRDC_COUNT (0)
+/* @brief ZLL availability on the SoC. */
+#define FSL_FEATURE_SOC_ZLL_COUNT (1)
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* COP module features */
+
+/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
+#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
+/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
+#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
+/* @brief Has more clock sources like MCGIRC */
+#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
+/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
+#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
+
+/* DCDC module features */
+
+/* @brief Has VDD1P5 bits in DCDC REG3. */
+#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1)
+/* @brief Has VDD1P45 bits in DCDC REG3. */
+#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* FLASH module features */
+
+#if defined(CPU_MKW21Z256VHT4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKW21Z512VHT4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#endif /* defined(CPU_MKW21Z256VHT4) */
+
+/* GENFSK module features */
+
+/* No feature definitions */
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has PF register. */
+#define FSL_FEATURE_LLWU_HAS_PF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has no internal module wakeup flag register. */
+#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+/* @brief Has Version ID Register (LLWU_VERID). */
+#define FSL_FEATURE_LLWU_HAS_VERID (0)
+/* @brief Has Parameter Register (LLWU_PARAM). */
+#define FSL_FEATURE_LLWU_HAS_PARAM (0)
+/* @brief Width of registers of the LLWU. */
+#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+/* @brief Has DMA Enable register (LLWU_DE). */
+#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
+
+/* LPUART module features */
+
+/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
+#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (0)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (0)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (0)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
+
+/* LTC module features */
+
+/* @brief LTC module supports DES algorithm. */
+#define FSL_FEATURE_LTC_HAS_DES (0)
+/* @brief LTC module supports PKHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_PKHA (0)
+/* @brief LTC module supports SHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_SHA (0)
+/* @brief LTC module supports AES GCM mode. */
+#define FSL_FEATURE_LTC_HAS_GCM (0)
+/* @brief LTC module supports DPAMS registers. */
+#define FSL_FEATURE_LTC_HAS_DPAMS (0)
+/* @brief LTC module supports AES with 24 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES192 (0)
+/* @brief LTC module supports AES with 32 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES256 (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (0)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (0)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief MCGFFCLK divider. */
+#define FSL_FEATURE_MCG_FFCLK_DIV (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (0)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (0)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
+#define FSL_FEATURE_MCG_HAS_PLL (0)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (2)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (0)
+/* @brief Has Bandgap Buffer Enable. */
+#define FSL_FEATURE_PMC_HAS_BGBE (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+/* @brief Has Low-Voltage Detect Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVDV (1)
+/* @brief Has Low-Voltage Warning Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVWV (1)
+/* @brief Has LPO. */
+#define FSL_FEATURE_PMC_HAS_LPO (0)
+/* @brief Has VLPx option PMC_REGSC[VLPO]. */
+#define FSL_FEATURE_PMC_HAS_VLPO (1)
+/* @brief Has acknowledge isolation support. */
+#define FSL_FEATURE_PMC_HAS_ACKISO (1)
+/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
+#define FSL_FEATURE_PMC_HAS_REGFPM (0)
+/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
+#define FSL_FEATURE_PMC_HAS_REGONS (1)
+/* @brief Has PMC_HVDSC1. */
+#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
+/* @brief Has PMC_PARAM. */
+#define FSL_FEATURE_PMC_HAS_PARAM (0)
+/* @brief Has PMC_VERID. */
+#define FSL_FEATURE_PMC_HAS_VERID (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* RADIO module features */
+
+/* @brief Zigbee availability. */
+#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1)
+/* @brief Bluetooth availability. */
+#define FSL_FEATURE_RADIO_HAS_BLE (0)
+/* @brief ANT availability */
+#define FSL_FEATURE_RADIO_HAS_ANT (1)
+/* @brief Generic FSK module availability */
+#define FSL_FEATURE_RADIO_HAS_GENFSK (1)
+/* @brief Major version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MAJOR (2)
+/* @brief Minor version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MINOR (0)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (0)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (0)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (0)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (0)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+/* @brief Has Version ID Register (RCM_VERID). */
+#define FSL_FEATURE_RCM_HAS_VERID (0)
+/* @brief Has Parameter Register (RCM_PARAM). */
+#define FSL_FEATURE_RCM_HAS_PARAM (0)
+/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
+#define FSL_FEATURE_RCM_HAS_SRIE (0)
+/* @brief Width of registers of the RCM. */
+#define FSL_FEATURE_RCM_REG_WIDTH (8)
+/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
+#define FSL_FEATURE_RCM_HAS_CORE1 (0)
+/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
+#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
+/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
+#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
+
+/* RSIM module features */
+
+/* No feature definitions */
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (0)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (0)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (0)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
+/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
+/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
+/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
+/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
+/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
+/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (1)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (0)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Bus clock is the source clock for the module. */
+#define FSL_FEATURE_TPM_BUS_CLOCK (0)
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+    ((x) == TPM0 ? (4) : \
+    ((x) == TPM1 ? (2) : \
+    ((x) == TPM2 ? (2) : (-1))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (0)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (0)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (0)
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
+/* @brief Has TPM_COMBINE register. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (1)
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER register. */
+#define FSL_FEATURE_TPM_HAS_FILTER (1)
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+/* @brief Has TPM_QDCTRL register. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+
+/* TRNG module features */
+
+/* No feature definitions */
+
+/* TSI module features */
+
+/* @brief TSI module version. */
+#define FSL_FEATURE_TSI_VERSION (4)
+/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
+#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
+/* @brief Number of TSI channels. */
+#define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief If high/low buffer mode supported */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+/* @brief Has VREF_TRM4. */
+#define FSL_FEATURE_VREF_HAS_TRM4 (0)
+
+/* XCVR_ANALOG module features */
+
+/* No feature definitions */
+
+/* XCVR_PHY module features */
+
+/* No feature definitions */
+
+/* ZLL module features */
+
+/* No feature definitions */
+
+#endif /* _MKW21Z4_FEATURES_H_ */
+
diff --git a/cpu/kw41z/include/vendor/MKW31Z4.h b/cpu/kw41z/include/vendor/MKW31Z4.h
index 689fe7e83d1a2..6b1f4e982a814 100644
--- a/cpu/kw41z/include/vendor/MKW31Z4.h
+++ b/cpu/kw41z/include/vendor/MKW31Z4.h
@@ -1,23 +1,23 @@
 /*
 ** ###################################################################
 **     Processors:          MKW31Z256VHT4
+**                          MKW31Z512CAT4
 **                          MKW31Z512VHT4
 **
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          GNU C Compiler
-**                          GNU C Compiler - CodeSourcery Sourcery G++
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    MKW41Z512RM Rev. 0.1, 04/2016
 **     Version:             rev. 1.0, 2015-09-23
-**     Build:               b160720
+**     Build:               b170213
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MKW31Z4
 **
-**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -28,7 +28,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -43,8 +43,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2015-09-23)
@@ -85,6 +85,9 @@
 #define NUMBER_OF_INT_VECTORS 48                 /**< Number of interrupts in the Vector table */
 
 typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
   /* Core interrupts */
   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
   HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
@@ -148,13 +151,114 @@ typedef enum IRQn {
 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
 
 #include "core_cm0plus.h"              /* Core Peripheral Access Layer */
-#include "system_MKW31Z4.h"            /* Device specific configuration file */
 
 /*!
  * @}
  */ /* end of group Cortex_Core_Configuration */
 
 
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
+    kDmaRequestMux0LPUART0Rx        = 2|0x100U,    /**< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx        = 3|0x100U,    /**< LPUART0 Transmit. */
+    kDmaRequestMux0Reserved4        = 4|0x100U,    /**< Reserved4 */
+    kDmaRequestMux0Reserved5        = 5|0x100U,    /**< Reserved5 */
+    kDmaRequestMux0Reserved6        = 6|0x100U,    /**< Reserved6 */
+    kDmaRequestMux0Reserved7        = 7|0x100U,    /**< Reserved7 */
+    kDmaRequestMux0Reserved8        = 8|0x100U,    /**< Reserved8 */
+    kDmaRequestMux0Reserved9        = 9|0x100U,    /**< Reserved9 */
+    kDmaRequestMux0Reserved10       = 10|0x100U,   /**< Reserved10 */
+    kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
+    kDmaRequestMux0Reserved12       = 12|0x100U,   /**< Reserved12 */
+    kDmaRequestMux0Reserved13       = 13|0x100U,   /**< Reserved13 */
+    kDmaRequestMux0Reserved14       = 14|0x100U,   /**< Reserved14 */
+    kDmaRequestMux0Reserved15       = 15|0x100U,   /**< Reserved15 */
+    kDmaRequestMux0SPI0Rx           = 16|0x100U,   /**< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx           = 17|0x100U,   /**< SPI0 Transmit. */
+    kDmaRequestMux0SPI1Rx           = 18|0x100U,   /**< SPI1 Receive. */
+    kDmaRequestMux0SPI1Tx           = 19|0x100U,   /**< SPI1 Transmit. */
+    kDmaRequestMux0LTC0InputFIFO    = 20|0x100U,   /**< LTC0 Input FIFO. */
+    kDmaRequestMux0LTC0OutputFIFO   = 21|0x100U,   /**< LTC0 Output FIFO. */
+    kDmaRequestMux0I2C0             = 22|0x100U,   /**< I2C0. */
+    kDmaRequestMux0I2C1             = 23|0x100U,   /**< I2C1. */
+    kDmaRequestMux0TPM0Channel0     = 24|0x100U,   /**< TPM0 C0V. */
+    kDmaRequestMux0TPM0Channel1     = 25|0x100U,   /**< TPM0 C1V. */
+    kDmaRequestMux0TPM0Channel2     = 26|0x100U,   /**< TPM0 C2V. */
+    kDmaRequestMux0TPM0Channel3     = 27|0x100U,   /**< TPM0 C3V. */
+    kDmaRequestMux0Reserved28       = 28|0x100U,   /**< Reserved28 */
+    kDmaRequestMux0Reserved29       = 29|0x100U,   /**< Reserved29 */
+    kDmaRequestMux0Reserved30       = 30|0x100U,   /**< Reserved30 */
+    kDmaRequestMux0Reserved31       = 31|0x100U,   /**< Reserved31 */
+    kDmaRequestMux0TPM1Channel0     = 32|0x100U,   /**< TPM1 C0V. */
+    kDmaRequestMux0TPM1Channel1     = 33|0x100U,   /**< TPM1 C1V. */
+    kDmaRequestMux0TPM2Channel0     = 34|0x100U,   /**< TPM2 C0V. */
+    kDmaRequestMux0TPM2Channel1     = 35|0x100U,   /**< TPM2 C1V. */
+    kDmaRequestMux0Reserved36       = 36|0x100U,   /**< Reserved36 */
+    kDmaRequestMux0Reserved37       = 37|0x100U,   /**< Reserved37 */
+    kDmaRequestMux0Reserved38       = 38|0x100U,   /**< Reserved38 */
+    kDmaRequestMux0Reserved39       = 39|0x100U,   /**< Reserved39 */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
+    kDmaRequestMux0Reserved41       = 41|0x100U,   /**< Reserved41 */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
+    kDmaRequestMux0Reserved43       = 43|0x100U,   /**< Reserved43 */
+    kDmaRequestMux0Reserved44       = 44|0x100U,   /**< Reserved44 */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
+    kDmaRequestMux0Reserved46       = 46|0x100U,   /**< Reserved46 */
+    kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT. */
+    kDmaRequestMux0Reserved48       = 48|0x100U,   /**< Reserved48 */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
+    kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
+    kDmaRequestMux0Reserved52       = 52|0x100U,   /**< Reserved52 */
+    kDmaRequestMux0Reserved53       = 53|0x100U,   /**< Reserved53 */
+    kDmaRequestMux0TPM0Overflow     = 54|0x100U,   /**< TPM0. */
+    kDmaRequestMux0TPM1Overflow     = 55|0x100U,   /**< TPM1. */
+    kDmaRequestMux0TPM2Overflow     = 56|0x100U,   /**< TPM2. */
+    kDmaRequestMux0TSI0             = 57|0x100U,   /**< TSI0. */
+    kDmaRequestMux0Reserved58       = 58|0x100U,   /**< Reserved58 */
+    kDmaRequestMux0Reserved59       = 59|0x100U,   /**< Reserved59 */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
 /* ----------------------------------------------------------------------------
    -- Device Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -434,6 +538,8 @@ typedef struct {
 #define ADC_BASE_ADDRS                           { ADC0_BASE }
 /** Array initializer of ADC peripheral base pointers */
 #define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
 
 /*!
  * @}
@@ -972,6 +1078,8 @@ typedef struct {
 #define CMP_BASE_ADDRS                           { CMP0_BASE }
 /** Array initializer of CMP peripheral base pointers */
 #define CMP_BASE_PTRS                            { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn }
 
 /*!
  * @}
@@ -1111,6 +1219,8 @@ typedef struct {
 #define CMT_BASE_ADDRS                           { CMT_BASE }
 /** Array initializer of CMT peripheral base pointers */
 #define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
 
 /*!
  * @}
@@ -1238,6 +1348,8 @@ typedef struct {
 #define DAC_BASE_ADDRS                           { DAC0_BASE }
 /** Array initializer of DAC peripheral base pointers */
 #define DAC_BASE_PTRS                            { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn }
 
 /*!
  * @}
@@ -2016,6 +2128,8 @@ typedef struct {
 #define DMA_BASE_ADDRS                           { DMA_BASE }
 /** Array initializer of DMA peripheral base pointers */
 #define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
 
 /*!
  * @}
@@ -2464,6 +2578,8 @@ typedef struct {
 #define FTFA_BASE_ADDRS                          { FTFA_BASE }
 /** Array initializer of FTFA peripheral base pointers */
 #define FTFA_BASE_PTRS                           { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS               { FTFA_IRQn }
 
 /*!
  * @}
@@ -3254,6 +3370,8 @@ typedef struct {
 #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
 /** Array initializer of I2C peripheral base pointers */
 #define I2C_BASE_PTRS                            { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
 
 /*!
  * @}
@@ -3489,6 +3607,8 @@ typedef struct {
 #define LLWU_BASE_ADDRS                          { LLWU_BASE }
 /** Array initializer of LLWU peripheral base pointers */
 #define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
 
 /*!
  * @}
@@ -3580,6 +3700,8 @@ typedef struct {
 #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
 /** Array initializer of LPTMR peripheral base pointers */
 #define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
 
 /*!
  * @}
@@ -3890,6 +4012,9 @@ typedef struct {
 #define LPUART_BASE_ADDRS                        { LPUART0_BASE }
 /** Array initializer of LPUART peripheral base pointers */
 #define LPUART_BASE_PTRS                         { LPUART0 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn }
 
 /*!
  * @}
@@ -4159,6 +4284,8 @@ typedef struct {
 #define LTC_BASE_ADDRS                           { LTC0_BASE }
 /** Array initializer of LTC peripheral base pointers */
 #define LTC_BASE_PTRS                            { LTC0 }
+/** Interrupt vectors for the LTC peripheral type */
+#define LTC_IRQS                                 { LTC0_IRQn }
 
 /*!
  * @}
@@ -4340,6 +4467,8 @@ typedef struct {
 #define MCG_BASE_ADDRS                           { MCG_BASE }
 /** Array initializer of MCG peripheral base pointers */
 #define MCG_BASE_PTRS                            { MCG }
+/** Interrupt vectors for the MCG peripheral type */
+#define MCG_IRQS                                 { MCG_IRQn }
 
 /*!
  * @}
@@ -5090,6 +5219,8 @@ typedef struct {
 #define PIT_BASE_ADDRS                           { PIT_BASE }
 /** Array initializer of PIT peripheral base pointers */
 #define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { { PIT_IRQn, PIT_IRQn } }
 
 /*!
  * @}
@@ -5181,6 +5312,8 @@ typedef struct {
 #define PMC_BASE_ADDRS                           { PMC_BASE }
 /** Array initializer of PMC peripheral base pointers */
 #define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_DCDC_IRQn }
 
 /*!
  * @}
@@ -5287,6 +5420,8 @@ typedef struct {
 #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE }
 /** Array initializer of PORT peripheral base pointers */
 #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn }
 
 /*!
  * @}
@@ -6111,6 +6246,9 @@ typedef struct {
 #define RTC_BASE_ADDRS                           { RTC_BASE }
 /** Array initializer of RTC peripheral base pointers */
 #define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
 
 /*!
  * @}
@@ -6844,6 +6982,8 @@ typedef struct {
 #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
 /** Array initializer of SPI peripheral base pointers */
 #define SPI_BASE_PTRS                            { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
 
 /*!
  * @}
@@ -7085,6 +7225,8 @@ typedef struct {
 #define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
 /** Array initializer of TPM peripheral base pointers */
 #define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
 
 /*!
  * @}
@@ -7594,6 +7736,8 @@ typedef struct {
 #define TRNG_BASE_ADDRS                          { TRNG0_BASE }
 /** Array initializer of TRNG peripheral base pointers */
 #define TRNG_BASE_PTRS                           { TRNG0 }
+/** Interrupt vectors for the TRNG peripheral type */
+#define TRNG_IRQS                                { TRNG0_IRQn }
 
 /*!
  * @}
@@ -7709,6 +7853,8 @@ typedef struct {
 #define TSI_BASE_ADDRS                           { TSI0_BASE }
 /** Array initializer of TSI peripheral base pointers */
 #define TSI_BASE_PTRS                            { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS                                 { TSI0_IRQn }
 
 /*!
  * @}
@@ -12108,6 +12254,43 @@ typedef struct {
  */ /* end of group Peripheral_access_layer */
 
 
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
 /* ----------------------------------------------------------------------------
    -- SDK Compatibility
    ---------------------------------------------------------------------------- */
diff --git a/cpu/kw41z/include/vendor/MKW31Z4_features.h b/cpu/kw41z/include/vendor/MKW31Z4_features.h
new file mode 100644
index 0000000000000..56b14a01a5b49
--- /dev/null
+++ b/cpu/kw41z/include/vendor/MKW31Z4_features.h
@@ -0,0 +1,2016 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2015-09-23
+**     Build:               b170228
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-09-23)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _MKW31Z4_FEATURES_H_
+#define _MKW31Z4_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ACMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACMP_COUNT (0)
+/* @brief ADC16 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC16_COUNT (1)
+/* @brief ADC12 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC12_COUNT (0)
+/* @brief AFE availability on the SoC. */
+#define FSL_FEATURE_SOC_AFE_COUNT (0)
+/* @brief AIPS availability on the SoC. */
+#define FSL_FEATURE_SOC_AIPS_COUNT (0)
+/* @brief AOI availability on the SoC. */
+#define FSL_FEATURE_SOC_AOI_COUNT (0)
+/* @brief AXBS availability on the SoC. */
+#define FSL_FEATURE_SOC_AXBS_COUNT (0)
+/* @brief ASMC availability on the SoC. */
+#define FSL_FEATURE_SOC_ASMC_COUNT (0)
+/* @brief CADC availability on the SoC. */
+#define FSL_FEATURE_SOC_CADC_COUNT (0)
+/* @brief FLEXCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
+/* @brief MMCAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
+/* @brief CMP availability on the SoC. */
+#define FSL_FEATURE_SOC_CMP_COUNT (1)
+/* @brief CMT availability on the SoC. */
+#define FSL_FEATURE_SOC_CMT_COUNT (1)
+/* @brief CNC availability on the SoC. */
+#define FSL_FEATURE_SOC_CNC_COUNT (0)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (0)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DAC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC32_COUNT (0)
+/* @brief DCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_DCDC_COUNT (1)
+/* @brief DDR availability on the SoC. */
+#define FSL_FEATURE_SOC_DDR_COUNT (0)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (0)
+/* @brief EDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_EDMA_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief DRY availability on the SoC. */
+#define FSL_FEATURE_SOC_DRY_COUNT (0)
+/* @brief DSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_DSPI_COUNT (2)
+/* @brief EMVSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+/* @brief ENC availability on the SoC. */
+#define FSL_FEATURE_SOC_ENC_COUNT (0)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_ENET_COUNT (0)
+/* @brief EWM availability on the SoC. */
+#define FSL_FEATURE_SOC_EWM_COUNT (0)
+/* @brief FB availability on the SoC. */
+#define FSL_FEATURE_SOC_FB_COUNT (0)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (3)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (0)
+/* @brief FSKDT availability on the SoC. */
+#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+/* @brief FTFA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFA_COUNT (1)
+/* @brief FTFE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFE_COUNT (0)
+/* @brief FTFL availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFL_COUNT (0)
+/* @brief FTM availability on the SoC. */
+#define FSL_FEATURE_SOC_FTM_COUNT (0)
+/* @brief FTMRA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+/* @brief FTMRE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+/* @brief FTMRH availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (3)
+/* @brief HSADC availability on the SoC. */
+#define FSL_FEATURE_SOC_HSADC_COUNT (0)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (0)
+/* @brief ICS availability on the SoC. */
+#define FSL_FEATURE_SOC_ICS_COUNT (0)
+/* @brief INTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
+/* @brief IRQ availability on the SoC. */
+#define FSL_FEATURE_SOC_IRQ_COUNT (0)
+/* @brief KBI availability on the SoC. */
+#define FSL_FEATURE_SOC_KBI_COUNT (0)
+/* @brief SLCD availability on the SoC. */
+#define FSL_FEATURE_SOC_SLCD_COUNT (0)
+/* @brief LCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_LCDC_COUNT (0)
+/* @brief LDO availability on the SoC. */
+#define FSL_FEATURE_SOC_LDO_COUNT (0)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (1)
+/* @brief LMEM availability on the SoC. */
+#define FSL_FEATURE_SOC_LMEM_COUNT (0)
+/* @brief LPI2C availability on the SoC. */
+#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
+/* @brief LPIT availability on the SoC. */
+#define FSL_FEATURE_SOC_LPIT_COUNT (0)
+/* @brief LPSCI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+/* @brief LPSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+/* @brief LPTPM availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (1)
+/* @brief LTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LTC_COUNT (1)
+/* @brief MC availability on the SoC. */
+#define FSL_FEATURE_SOC_MC_COUNT (0)
+/* @brief MCG availability on the SoC. */
+#define FSL_FEATURE_SOC_MCG_COUNT (1)
+/* @brief MCGLITE availability on the SoC. */
+#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MMAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMAU_COUNT (0)
+/* @brief MMDVSQ availability on the SoC. */
+#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+/* @brief SYSMPU availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSMPU_COUNT (0)
+/* @brief MSCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+/* @brief MSCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCM_COUNT (0)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief MU availability on the SoC. */
+#define FSL_FEATURE_SOC_MU_COUNT (0)
+/* @brief NFC availability on the SoC. */
+#define FSL_FEATURE_SOC_NFC_COUNT (0)
+/* @brief OPAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+/* @brief OSC availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC_COUNT (0)
+/* @brief OSC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC32_COUNT (0)
+/* @brief OTFAD availability on the SoC. */
+#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+/* @brief PDB availability on the SoC. */
+#define FSL_FEATURE_SOC_PDB_COUNT (0)
+/* @brief PCC availability on the SoC. */
+#define FSL_FEATURE_SOC_PCC_COUNT (0)
+/* @brief PGA availability on the SoC. */
+#define FSL_FEATURE_SOC_PGA_COUNT (0)
+/* @brief PIT availability on the SoC. */
+#define FSL_FEATURE_SOC_PIT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (3)
+/* @brief PWM availability on the SoC. */
+#define FSL_FEATURE_SOC_PWM_COUNT (0)
+/* @brief PWT availability on the SoC. */
+#define FSL_FEATURE_SOC_PWT_COUNT (0)
+/* @brief QuadSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
+/* @brief RCM availability on the SoC. */
+#define FSL_FEATURE_SOC_RCM_COUNT (1)
+/* @brief RFSYS availability on the SoC. */
+#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+/* @brief RFVBAT availability on the SoC. */
+#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_RNG_COUNT (0)
+/* @brief RNGB availability on the SoC. */
+#define FSL_FEATURE_SOC_RNGB_COUNT (0)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_RSIM_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCG availability on the SoC. */
+#define FSL_FEATURE_SOC_SCG_COUNT (0)
+/* @brief SCI availability on the SoC. */
+#define FSL_FEATURE_SOC_SCI_COUNT (0)
+/* @brief SDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_SDHC_COUNT (0)
+/* @brief SDRAM availability on the SoC. */
+#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+/* @brief SEMA42 availability on the SoC. */
+#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (0)
+/* @brief TMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TMR_COUNT (0)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (3)
+/* @brief TRGMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
+/* @brief TRIAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief TSI availability on the SoC. */
+#define FSL_FEATURE_SOC_TSI_COUNT (1)
+/* @brief TSTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
+/* @brief UART availability on the SoC. */
+#define FSL_FEATURE_SOC_UART_COUNT (0)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (0)
+/* @brief USBDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
+/* @brief USBHS availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHS_COUNT (0)
+/* @brief USBHSDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+/* @brief WDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_WDOG_COUNT (0)
+/* @brief XBAR availability on the SoC. */
+#define FSL_FEATURE_SOC_XBAR_COUNT (0)
+/* @brief XBARA availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARA_COUNT (0)
+/* @brief XBARB availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARB_COUNT (0)
+/* @brief XCVR availability on the SoC. */
+#define FSL_FEATURE_SOC_XCVR_COUNT (1)
+/* @brief XRDC availability on the SoC. */
+#define FSL_FEATURE_SOC_XRDC_COUNT (0)
+/* @brief ZLL availability on the SoC. */
+#define FSL_FEATURE_SOC_ZLL_COUNT (1)
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* BTLE_RF module features */
+
+/* No feature definitions */
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* COP module features */
+
+/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
+#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
+/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
+#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
+/* @brief Has more clock sources like MCGIRC */
+#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
+/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
+#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
+
+/* DCDC module features */
+
+/* @brief Has VDD1P5 bits in DCDC REG3. */
+#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1)
+/* @brief Has VDD1P45 bits in DCDC REG3. */
+#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* FLASH module features */
+
+#if defined(CPU_MKW31Z256VHT4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKW31Z512CAT4) || defined(CPU_MKW31Z512VHT4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#endif /* defined(CPU_MKW31Z256VHT4) */
+
+/* GENFSK module features */
+
+/* No feature definitions */
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1)
+
+/* LLWU module features */
+
+#if defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4)
+    /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+    /* @brief Has pins 8-15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+    /* @brief Maximum number of internal modules connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+    /* @brief Number of digital filters. */
+    #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+    /* @brief Has MF register. */
+    #define FSL_FEATURE_LLWU_HAS_MF (0)
+    /* @brief Has PF register. */
+    #define FSL_FEATURE_LLWU_HAS_PF (0)
+    /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+    #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+    /* @brief Has no internal module wakeup flag register. */
+    #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
+    /* @brief Has external pin 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16)
+    /* @brief Has external pin 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17)
+    /* @brief Has external pin 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18)
+    /* @brief Has external pin 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19)
+    /* @brief Has external pin 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16)
+    /* @brief Has external pin 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17)
+    /* @brief Has external pin 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18)
+    /* @brief Has external pin 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19)
+    /* @brief Has external pin 8 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0)
+    /* @brief Has external pin 9 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0)
+    /* @brief Has external pin 10 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2)
+    /* @brief Has external pin 11 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3)
+    /* @brief Has external pin 12 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4)
+    /* @brief Has external pin 13 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5)
+    /* @brief Has external pin 14 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6)
+    /* @brief Has external pin 15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
+    /* @brief Has external pin 16 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+    /* @brief Has external pin 17 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+    /* @brief Has external pin 18 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+    /* @brief Has external pin 19 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+    /* @brief Has external pin 20 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+    /* @brief Has external pin 21 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+    /* @brief Has external pin 22 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+    /* @brief Has external pin 23 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+    /* @brief Has external pin 24 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+    /* @brief Has external pin 25 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+    /* @brief Has external pin 26 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+    /* @brief Has external pin 27 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+    /* @brief Has external pin 28 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+    /* @brief Has external pin 29 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+    /* @brief Has external pin 30 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+    /* @brief Has external pin 31 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+    /* @brief Has internal module 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+    /* @brief Has internal module 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+    /* @brief Has internal module 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+    /* @brief Has internal module 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+    /* @brief Has internal module 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+    /* @brief Has internal module 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+    /* @brief Has internal module 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+    /* @brief Has internal module 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+    /* @brief Has Version ID Register (LLWU_VERID). */
+    #define FSL_FEATURE_LLWU_HAS_VERID (0)
+    /* @brief Has Parameter Register (LLWU_PARAM). */
+    #define FSL_FEATURE_LLWU_HAS_PARAM (0)
+    /* @brief Width of registers of the LLWU. */
+    #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+    /* @brief Has DMA Enable register (LLWU_DE). */
+    #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+#elif defined(CPU_MKW31Z512CAT4)
+    /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+    /* @brief Has pins 8-15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+    /* @brief Maximum number of internal modules connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+    /* @brief Number of digital filters. */
+    #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+    /* @brief Has MF register. */
+    #define FSL_FEATURE_LLWU_HAS_MF (0)
+    /* @brief Has PF register. */
+    #define FSL_FEATURE_LLWU_HAS_PF (0)
+    /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+    #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+    /* @brief Has no internal module wakeup flag register. */
+    #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
+    /* @brief Has external pin 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16)
+    /* @brief Has external pin 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17)
+    /* @brief Has external pin 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18)
+    /* @brief Has external pin 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19)
+    /* @brief Has external pin 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16)
+    /* @brief Has external pin 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17)
+    /* @brief Has external pin 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18)
+    /* @brief Has external pin 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19)
+    /* @brief Has external pin 8 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0)
+    /* @brief Has external pin 9 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0)
+    /* @brief Has external pin 10 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2)
+    /* @brief Has external pin 11 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3)
+    /* @brief Has external pin 12 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4)
+    /* @brief Has external pin 13 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5)
+    /* @brief Has external pin 14 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6)
+    /* @brief Has external pin 15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
+    /* @brief Has external pin 16 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+    /* @brief Has external pin 17 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+    /* @brief Has external pin 18 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+    /* @brief Has external pin 19 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+    /* @brief Has external pin 20 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+    /* @brief Has external pin 21 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+    /* @brief Has external pin 22 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+    /* @brief Has external pin 23 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+    /* @brief Has external pin 24 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+    /* @brief Has external pin 25 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+    /* @brief Has external pin 26 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+    /* @brief Has external pin 27 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+    /* @brief Has external pin 28 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+    /* @brief Has external pin 29 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+    /* @brief Has external pin 30 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+    /* @brief Has external pin 31 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+    /* @brief Has internal module 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+    /* @brief Has internal module 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+    /* @brief Has internal module 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+    /* @brief Has internal module 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+    /* @brief Has internal module 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+    /* @brief Has internal module 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+    /* @brief Has internal module 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+    /* @brief Has internal module 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+    /* @brief Has Version ID Register (LLWU_VERID). */
+    #define FSL_FEATURE_LLWU_HAS_VERID (0)
+    /* @brief Has Parameter Register (LLWU_PARAM). */
+    #define FSL_FEATURE_LLWU_HAS_PARAM (0)
+    /* @brief Width of registers of the LLWU. */
+    #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+    /* @brief Has DMA Enable register (LLWU_DE). */
+    #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+#endif /* defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) */
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
+
+/* LPUART module features */
+
+/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
+#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (0)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (0)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (0)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
+
+/* LTC module features */
+
+/* @brief LTC module supports DES algorithm. */
+#define FSL_FEATURE_LTC_HAS_DES (0)
+/* @brief LTC module supports PKHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_PKHA (0)
+/* @brief LTC module supports SHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_SHA (0)
+/* @brief LTC module supports AES GCM mode. */
+#define FSL_FEATURE_LTC_HAS_GCM (0)
+/* @brief LTC module supports DPAMS registers. */
+#define FSL_FEATURE_LTC_HAS_DPAMS (0)
+/* @brief LTC module supports AES with 24 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES192 (0)
+/* @brief LTC module supports AES with 32 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES256 (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (0)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (0)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief MCGFFCLK divider. */
+#define FSL_FEATURE_MCG_FFCLK_DIV (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (0)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (0)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
+#define FSL_FEATURE_MCG_HAS_PLL (0)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (2)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (0)
+/* @brief Has Bandgap Buffer Enable. */
+#define FSL_FEATURE_PMC_HAS_BGBE (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+/* @brief Has Low-Voltage Detect Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVDV (1)
+/* @brief Has Low-Voltage Warning Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVWV (1)
+/* @brief Has LPO. */
+#define FSL_FEATURE_PMC_HAS_LPO (0)
+/* @brief Has VLPx option PMC_REGSC[VLPO]. */
+#define FSL_FEATURE_PMC_HAS_VLPO (1)
+/* @brief Has acknowledge isolation support. */
+#define FSL_FEATURE_PMC_HAS_ACKISO (1)
+/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
+#define FSL_FEATURE_PMC_HAS_REGFPM (0)
+/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
+#define FSL_FEATURE_PMC_HAS_REGONS (1)
+/* @brief Has PMC_HVDSC1. */
+#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
+/* @brief Has PMC_PARAM. */
+#define FSL_FEATURE_PMC_HAS_PARAM (0)
+/* @brief Has PMC_VERID. */
+#define FSL_FEATURE_PMC_HAS_VERID (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* RADIO module features */
+
+/* @brief Zigbee availability. */
+#define FSL_FEATURE_RADIO_HAS_ZIGBEE (0)
+/* @brief Bluetooth availability. */
+#define FSL_FEATURE_RADIO_HAS_BLE (1)
+/* @brief ANT availability */
+#define FSL_FEATURE_RADIO_HAS_ANT (1)
+/* @brief Generic FSK module availability */
+#define FSL_FEATURE_RADIO_HAS_GENFSK (1)
+/* @brief Major version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MAJOR (2)
+/* @brief Minor version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MINOR (0)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (0)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (0)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (0)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (0)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+/* @brief Has Version ID Register (RCM_VERID). */
+#define FSL_FEATURE_RCM_HAS_VERID (0)
+/* @brief Has Parameter Register (RCM_PARAM). */
+#define FSL_FEATURE_RCM_HAS_PARAM (0)
+/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
+#define FSL_FEATURE_RCM_HAS_SRIE (0)
+/* @brief Width of registers of the RCM. */
+#define FSL_FEATURE_RCM_REG_WIDTH (8)
+/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
+#define FSL_FEATURE_RCM_HAS_CORE1 (0)
+/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
+#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
+/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
+#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
+
+/* RSIM module features */
+
+/* No feature definitions */
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (0)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (0)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (0)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
+/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
+/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
+/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
+/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
+/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
+/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (1)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (0)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Bus clock is the source clock for the module. */
+#define FSL_FEATURE_TPM_BUS_CLOCK (0)
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+    ((x) == TPM0 ? (4) : \
+    ((x) == TPM1 ? (2) : \
+    ((x) == TPM2 ? (2) : (-1))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (0)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (0)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (0)
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
+/* @brief Has TPM_COMBINE register. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (1)
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER register. */
+#define FSL_FEATURE_TPM_HAS_FILTER (1)
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+/* @brief Has TPM_QDCTRL register. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+
+/* TRNG module features */
+
+/* No feature definitions */
+
+/* TSI module features */
+
+/* @brief TSI module version. */
+#define FSL_FEATURE_TSI_VERSION (4)
+/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
+#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
+/* @brief Number of TSI channels. */
+#define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief If high/low buffer mode supported */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+/* @brief Has VREF_TRM4. */
+#define FSL_FEATURE_VREF_HAS_TRM4 (0)
+
+/* XCVR_ANALOG module features */
+
+/* No feature definitions */
+
+/* XCVR_PHY module features */
+
+/* No feature definitions */
+
+#endif /* _MKW31Z4_FEATURES_H_ */
+
diff --git a/cpu/kw41z/include/vendor/MKW41Z4.h b/cpu/kw41z/include/vendor/MKW41Z4.h
index f434595bfa54e..08c1ee3aec107 100644
--- a/cpu/kw41z/include/vendor/MKW41Z4.h
+++ b/cpu/kw41z/include/vendor/MKW41Z4.h
@@ -1,23 +1,23 @@
 /*
 ** ###################################################################
 **     Processors:          MKW41Z256VHT4
+**                          MKW41Z512CAT4
 **                          MKW41Z512VHT4
 **
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          GNU C Compiler
-**                          GNU C Compiler - CodeSourcery Sourcery G++
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    MKW41Z512RM Rev. 0.1, 04/2016
 **     Version:             rev. 1.0, 2015-09-23
-**     Build:               b160720
+**     Build:               b170213
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MKW41Z4
 **
-**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -28,7 +28,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -43,8 +43,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2015-09-23)
@@ -85,6 +85,9 @@
 #define NUMBER_OF_INT_VECTORS 48                 /**< Number of interrupts in the Vector table */
 
 typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
   /* Core interrupts */
   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
   HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
@@ -154,6 +157,108 @@ typedef enum IRQn {
  */ /* end of group Cortex_Core_Configuration */
 
 
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
+    kDmaRequestMux0LPUART0Rx        = 2|0x100U,    /**< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx        = 3|0x100U,    /**< LPUART0 Transmit. */
+    kDmaRequestMux0Reserved4        = 4|0x100U,    /**< Reserved4 */
+    kDmaRequestMux0Reserved5        = 5|0x100U,    /**< Reserved5 */
+    kDmaRequestMux0Reserved6        = 6|0x100U,    /**< Reserved6 */
+    kDmaRequestMux0Reserved7        = 7|0x100U,    /**< Reserved7 */
+    kDmaRequestMux0Reserved8        = 8|0x100U,    /**< Reserved8 */
+    kDmaRequestMux0Reserved9        = 9|0x100U,    /**< Reserved9 */
+    kDmaRequestMux0Reserved10       = 10|0x100U,   /**< Reserved10 */
+    kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
+    kDmaRequestMux0Reserved12       = 12|0x100U,   /**< Reserved12 */
+    kDmaRequestMux0Reserved13       = 13|0x100U,   /**< Reserved13 */
+    kDmaRequestMux0Reserved14       = 14|0x100U,   /**< Reserved14 */
+    kDmaRequestMux0Reserved15       = 15|0x100U,   /**< Reserved15 */
+    kDmaRequestMux0SPI0Rx           = 16|0x100U,   /**< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx           = 17|0x100U,   /**< SPI0 Transmit. */
+    kDmaRequestMux0SPI1Rx           = 18|0x100U,   /**< SPI1 Receive. */
+    kDmaRequestMux0SPI1Tx           = 19|0x100U,   /**< SPI1 Transmit. */
+    kDmaRequestMux0LTC0InputFIFO    = 20|0x100U,   /**< LTC0 Input FIFO. */
+    kDmaRequestMux0LTC0OutputFIFO   = 21|0x100U,   /**< LTC0 Output FIFO. */
+    kDmaRequestMux0I2C0             = 22|0x100U,   /**< I2C0. */
+    kDmaRequestMux0I2C1             = 23|0x100U,   /**< I2C1. */
+    kDmaRequestMux0TPM0Channel0     = 24|0x100U,   /**< TPM0 C0V. */
+    kDmaRequestMux0TPM0Channel1     = 25|0x100U,   /**< TPM0 C1V. */
+    kDmaRequestMux0TPM0Channel2     = 26|0x100U,   /**< TPM0 C2V. */
+    kDmaRequestMux0TPM0Channel3     = 27|0x100U,   /**< TPM0 C3V. */
+    kDmaRequestMux0Reserved28       = 28|0x100U,   /**< Reserved28 */
+    kDmaRequestMux0Reserved29       = 29|0x100U,   /**< Reserved29 */
+    kDmaRequestMux0Reserved30       = 30|0x100U,   /**< Reserved30 */
+    kDmaRequestMux0Reserved31       = 31|0x100U,   /**< Reserved31 */
+    kDmaRequestMux0TPM1Channel0     = 32|0x100U,   /**< TPM1 C0V. */
+    kDmaRequestMux0TPM1Channel1     = 33|0x100U,   /**< TPM1 C1V. */
+    kDmaRequestMux0TPM2Channel0     = 34|0x100U,   /**< TPM2 C0V. */
+    kDmaRequestMux0TPM2Channel1     = 35|0x100U,   /**< TPM2 C1V. */
+    kDmaRequestMux0Reserved36       = 36|0x100U,   /**< Reserved36 */
+    kDmaRequestMux0Reserved37       = 37|0x100U,   /**< Reserved37 */
+    kDmaRequestMux0Reserved38       = 38|0x100U,   /**< Reserved38 */
+    kDmaRequestMux0Reserved39       = 39|0x100U,   /**< Reserved39 */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
+    kDmaRequestMux0Reserved41       = 41|0x100U,   /**< Reserved41 */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
+    kDmaRequestMux0Reserved43       = 43|0x100U,   /**< Reserved43 */
+    kDmaRequestMux0Reserved44       = 44|0x100U,   /**< Reserved44 */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
+    kDmaRequestMux0Reserved46       = 46|0x100U,   /**< Reserved46 */
+    kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT. */
+    kDmaRequestMux0Reserved48       = 48|0x100U,   /**< Reserved48 */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
+    kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
+    kDmaRequestMux0Reserved52       = 52|0x100U,   /**< Reserved52 */
+    kDmaRequestMux0Reserved53       = 53|0x100U,   /**< Reserved53 */
+    kDmaRequestMux0TPM0Overflow     = 54|0x100U,   /**< TPM0. */
+    kDmaRequestMux0TPM1Overflow     = 55|0x100U,   /**< TPM1. */
+    kDmaRequestMux0TPM2Overflow     = 56|0x100U,   /**< TPM2. */
+    kDmaRequestMux0TSI0             = 57|0x100U,   /**< TSI0. */
+    kDmaRequestMux0Reserved58       = 58|0x100U,   /**< Reserved58 */
+    kDmaRequestMux0Reserved59       = 59|0x100U,   /**< Reserved59 */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
 /* ----------------------------------------------------------------------------
    -- Device Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -433,6 +538,8 @@ typedef struct {
 #define ADC_BASE_ADDRS                           { ADC0_BASE }
 /** Array initializer of ADC peripheral base pointers */
 #define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
 
 /*!
  * @}
@@ -971,6 +1078,8 @@ typedef struct {
 #define CMP_BASE_ADDRS                           { CMP0_BASE }
 /** Array initializer of CMP peripheral base pointers */
 #define CMP_BASE_PTRS                            { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn }
 
 /*!
  * @}
@@ -1110,6 +1219,8 @@ typedef struct {
 #define CMT_BASE_ADDRS                           { CMT_BASE }
 /** Array initializer of CMT peripheral base pointers */
 #define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
 
 /*!
  * @}
@@ -1237,6 +1348,8 @@ typedef struct {
 #define DAC_BASE_ADDRS                           { DAC0_BASE }
 /** Array initializer of DAC peripheral base pointers */
 #define DAC_BASE_PTRS                            { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn }
 
 /*!
  * @}
@@ -2015,6 +2128,8 @@ typedef struct {
 #define DMA_BASE_ADDRS                           { DMA_BASE }
 /** Array initializer of DMA peripheral base pointers */
 #define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
 
 /*!
  * @}
@@ -2463,6 +2578,8 @@ typedef struct {
 #define FTFA_BASE_ADDRS                          { FTFA_BASE }
 /** Array initializer of FTFA peripheral base pointers */
 #define FTFA_BASE_PTRS                           { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS               { FTFA_IRQn }
 
 /*!
  * @}
@@ -3253,6 +3370,8 @@ typedef struct {
 #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
 /** Array initializer of I2C peripheral base pointers */
 #define I2C_BASE_PTRS                            { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
 
 /*!
  * @}
@@ -3488,6 +3607,8 @@ typedef struct {
 #define LLWU_BASE_ADDRS                          { LLWU_BASE }
 /** Array initializer of LLWU peripheral base pointers */
 #define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
 
 /*!
  * @}
@@ -3579,6 +3700,8 @@ typedef struct {
 #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
 /** Array initializer of LPTMR peripheral base pointers */
 #define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
 
 /*!
  * @}
@@ -3889,6 +4012,9 @@ typedef struct {
 #define LPUART_BASE_ADDRS                        { LPUART0_BASE }
 /** Array initializer of LPUART peripheral base pointers */
 #define LPUART_BASE_PTRS                         { LPUART0 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn }
 
 /*!
  * @}
@@ -4158,6 +4284,8 @@ typedef struct {
 #define LTC_BASE_ADDRS                           { LTC0_BASE }
 /** Array initializer of LTC peripheral base pointers */
 #define LTC_BASE_PTRS                            { LTC0 }
+/** Interrupt vectors for the LTC peripheral type */
+#define LTC_IRQS                                 { LTC0_IRQn }
 
 /*!
  * @}
@@ -4339,6 +4467,8 @@ typedef struct {
 #define MCG_BASE_ADDRS                           { MCG_BASE }
 /** Array initializer of MCG peripheral base pointers */
 #define MCG_BASE_PTRS                            { MCG }
+/** Interrupt vectors for the MCG peripheral type */
+#define MCG_IRQS                                 { MCG_IRQn }
 
 /*!
  * @}
@@ -5089,6 +5219,8 @@ typedef struct {
 #define PIT_BASE_ADDRS                           { PIT_BASE }
 /** Array initializer of PIT peripheral base pointers */
 #define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { { PIT_IRQn, PIT_IRQn } }
 
 /*!
  * @}
@@ -5180,6 +5312,8 @@ typedef struct {
 #define PMC_BASE_ADDRS                           { PMC_BASE }
 /** Array initializer of PMC peripheral base pointers */
 #define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_DCDC_IRQn }
 
 /*!
  * @}
@@ -5286,6 +5420,8 @@ typedef struct {
 #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE }
 /** Array initializer of PORT peripheral base pointers */
 #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn }
 
 /*!
  * @}
@@ -6110,6 +6246,9 @@ typedef struct {
 #define RTC_BASE_ADDRS                           { RTC_BASE }
 /** Array initializer of RTC peripheral base pointers */
 #define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
 
 /*!
  * @}
@@ -6843,6 +6982,8 @@ typedef struct {
 #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
 /** Array initializer of SPI peripheral base pointers */
 #define SPI_BASE_PTRS                            { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
 
 /*!
  * @}
@@ -7084,6 +7225,8 @@ typedef struct {
 #define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
 /** Array initializer of TPM peripheral base pointers */
 #define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
 
 /*!
  * @}
@@ -7593,6 +7736,8 @@ typedef struct {
 #define TRNG_BASE_ADDRS                          { TRNG0_BASE }
 /** Array initializer of TRNG peripheral base pointers */
 #define TRNG_BASE_PTRS                           { TRNG0 }
+/** Interrupt vectors for the TRNG peripheral type */
+#define TRNG_IRQS                                { TRNG0_IRQn }
 
 /*!
  * @}
@@ -7708,6 +7853,8 @@ typedef struct {
 #define TSI_BASE_ADDRS                           { TSI0_BASE }
 /** Array initializer of TSI peripheral base pointers */
 #define TSI_BASE_PTRS                            { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS                                 { TSI0_IRQn }
 
 /*!
  * @}
@@ -12810,6 +12957,43 @@ typedef struct {
  */ /* end of group Peripheral_access_layer */
 
 
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
 /* ----------------------------------------------------------------------------
    -- SDK Compatibility
    ---------------------------------------------------------------------------- */
diff --git a/cpu/kw41z/include/vendor/MKW41Z4_features.h b/cpu/kw41z/include/vendor/MKW41Z4_features.h
new file mode 100644
index 0000000000000..7e7fee364b5c7
--- /dev/null
+++ b/cpu/kw41z/include/vendor/MKW41Z4_features.h
@@ -0,0 +1,2020 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2015-09-23
+**     Build:               b170228
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-09-23)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _MKW41Z4_FEATURES_H_
+#define _MKW41Z4_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ACMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACMP_COUNT (0)
+/* @brief ADC16 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC16_COUNT (1)
+/* @brief ADC12 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC12_COUNT (0)
+/* @brief AFE availability on the SoC. */
+#define FSL_FEATURE_SOC_AFE_COUNT (0)
+/* @brief AIPS availability on the SoC. */
+#define FSL_FEATURE_SOC_AIPS_COUNT (0)
+/* @brief AOI availability on the SoC. */
+#define FSL_FEATURE_SOC_AOI_COUNT (0)
+/* @brief AXBS availability on the SoC. */
+#define FSL_FEATURE_SOC_AXBS_COUNT (0)
+/* @brief ASMC availability on the SoC. */
+#define FSL_FEATURE_SOC_ASMC_COUNT (0)
+/* @brief CADC availability on the SoC. */
+#define FSL_FEATURE_SOC_CADC_COUNT (0)
+/* @brief FLEXCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
+/* @brief MMCAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
+/* @brief CMP availability on the SoC. */
+#define FSL_FEATURE_SOC_CMP_COUNT (1)
+/* @brief CMT availability on the SoC. */
+#define FSL_FEATURE_SOC_CMT_COUNT (1)
+/* @brief CNC availability on the SoC. */
+#define FSL_FEATURE_SOC_CNC_COUNT (0)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (0)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DAC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC32_COUNT (0)
+/* @brief DCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_DCDC_COUNT (1)
+/* @brief DDR availability on the SoC. */
+#define FSL_FEATURE_SOC_DDR_COUNT (0)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (0)
+/* @brief EDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_EDMA_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief DRY availability on the SoC. */
+#define FSL_FEATURE_SOC_DRY_COUNT (0)
+/* @brief DSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_DSPI_COUNT (2)
+/* @brief EMVSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+/* @brief ENC availability on the SoC. */
+#define FSL_FEATURE_SOC_ENC_COUNT (0)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_ENET_COUNT (0)
+/* @brief EWM availability on the SoC. */
+#define FSL_FEATURE_SOC_EWM_COUNT (0)
+/* @brief FB availability on the SoC. */
+#define FSL_FEATURE_SOC_FB_COUNT (0)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (3)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (0)
+/* @brief FSKDT availability on the SoC. */
+#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+/* @brief FTFA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFA_COUNT (1)
+/* @brief FTFE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFE_COUNT (0)
+/* @brief FTFL availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFL_COUNT (0)
+/* @brief FTM availability on the SoC. */
+#define FSL_FEATURE_SOC_FTM_COUNT (0)
+/* @brief FTMRA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+/* @brief FTMRE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+/* @brief FTMRH availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (3)
+/* @brief HSADC availability on the SoC. */
+#define FSL_FEATURE_SOC_HSADC_COUNT (0)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (0)
+/* @brief ICS availability on the SoC. */
+#define FSL_FEATURE_SOC_ICS_COUNT (0)
+/* @brief INTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
+/* @brief IRQ availability on the SoC. */
+#define FSL_FEATURE_SOC_IRQ_COUNT (0)
+/* @brief KBI availability on the SoC. */
+#define FSL_FEATURE_SOC_KBI_COUNT (0)
+/* @brief SLCD availability on the SoC. */
+#define FSL_FEATURE_SOC_SLCD_COUNT (0)
+/* @brief LCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_LCDC_COUNT (0)
+/* @brief LDO availability on the SoC. */
+#define FSL_FEATURE_SOC_LDO_COUNT (0)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (1)
+/* @brief LMEM availability on the SoC. */
+#define FSL_FEATURE_SOC_LMEM_COUNT (0)
+/* @brief LPI2C availability on the SoC. */
+#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
+/* @brief LPIT availability on the SoC. */
+#define FSL_FEATURE_SOC_LPIT_COUNT (0)
+/* @brief LPSCI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+/* @brief LPSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+/* @brief LPTPM availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (1)
+/* @brief LTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LTC_COUNT (1)
+/* @brief MC availability on the SoC. */
+#define FSL_FEATURE_SOC_MC_COUNT (0)
+/* @brief MCG availability on the SoC. */
+#define FSL_FEATURE_SOC_MCG_COUNT (1)
+/* @brief MCGLITE availability on the SoC. */
+#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MMAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMAU_COUNT (0)
+/* @brief MMDVSQ availability on the SoC. */
+#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+/* @brief SYSMPU availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSMPU_COUNT (0)
+/* @brief MSCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+/* @brief MSCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCM_COUNT (0)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief MU availability on the SoC. */
+#define FSL_FEATURE_SOC_MU_COUNT (0)
+/* @brief NFC availability on the SoC. */
+#define FSL_FEATURE_SOC_NFC_COUNT (0)
+/* @brief OPAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+/* @brief OSC availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC_COUNT (0)
+/* @brief OSC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC32_COUNT (0)
+/* @brief OTFAD availability on the SoC. */
+#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+/* @brief PDB availability on the SoC. */
+#define FSL_FEATURE_SOC_PDB_COUNT (0)
+/* @brief PCC availability on the SoC. */
+#define FSL_FEATURE_SOC_PCC_COUNT (0)
+/* @brief PGA availability on the SoC. */
+#define FSL_FEATURE_SOC_PGA_COUNT (0)
+/* @brief PIT availability on the SoC. */
+#define FSL_FEATURE_SOC_PIT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (3)
+/* @brief PWM availability on the SoC. */
+#define FSL_FEATURE_SOC_PWM_COUNT (0)
+/* @brief PWT availability on the SoC. */
+#define FSL_FEATURE_SOC_PWT_COUNT (0)
+/* @brief QuadSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
+/* @brief RCM availability on the SoC. */
+#define FSL_FEATURE_SOC_RCM_COUNT (1)
+/* @brief RFSYS availability on the SoC. */
+#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+/* @brief RFVBAT availability on the SoC. */
+#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_RNG_COUNT (0)
+/* @brief RNGB availability on the SoC. */
+#define FSL_FEATURE_SOC_RNGB_COUNT (0)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_RSIM_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCG availability on the SoC. */
+#define FSL_FEATURE_SOC_SCG_COUNT (0)
+/* @brief SCI availability on the SoC. */
+#define FSL_FEATURE_SOC_SCI_COUNT (0)
+/* @brief SDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_SDHC_COUNT (0)
+/* @brief SDRAM availability on the SoC. */
+#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+/* @brief SEMA42 availability on the SoC. */
+#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (0)
+/* @brief TMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TMR_COUNT (0)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (3)
+/* @brief TRGMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
+/* @brief TRIAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief TSI availability on the SoC. */
+#define FSL_FEATURE_SOC_TSI_COUNT (1)
+/* @brief TSTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
+/* @brief UART availability on the SoC. */
+#define FSL_FEATURE_SOC_UART_COUNT (0)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (0)
+/* @brief USBDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
+/* @brief USBHS availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHS_COUNT (0)
+/* @brief USBHSDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+/* @brief WDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_WDOG_COUNT (0)
+/* @brief XBAR availability on the SoC. */
+#define FSL_FEATURE_SOC_XBAR_COUNT (0)
+/* @brief XBARA availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARA_COUNT (0)
+/* @brief XBARB availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARB_COUNT (0)
+/* @brief XCVR availability on the SoC. */
+#define FSL_FEATURE_SOC_XCVR_COUNT (1)
+/* @brief XRDC availability on the SoC. */
+#define FSL_FEATURE_SOC_XRDC_COUNT (0)
+/* @brief ZLL availability on the SoC. */
+#define FSL_FEATURE_SOC_ZLL_COUNT (1)
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* BTLE_RF module features */
+
+/* No feature definitions */
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* COP module features */
+
+/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
+#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
+/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
+#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
+/* @brief Has more clock sources like MCGIRC */
+#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
+/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
+#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (2)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0)
+
+/* DCDC module features */
+
+/* @brief Has VDD1P5 bits in DCDC REG3. */
+#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1)
+/* @brief Has VDD1P45 bits in DCDC REG3. */
+#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* FLASH module features */
+
+#if defined(CPU_MKW41Z256VHT4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#elif defined(CPU_MKW41Z512CAT4) || defined(CPU_MKW41Z512VHT4)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (1)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (0)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x49 Erase All Blocks Unsecure command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+#endif /* defined(CPU_MKW41Z256VHT4) */
+
+/* GENFSK module features */
+
+/* No feature definitions */
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1)
+
+/* LLWU module features */
+
+#if defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4)
+    /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+    /* @brief Has pins 8-15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+    /* @brief Maximum number of internal modules connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+    /* @brief Number of digital filters. */
+    #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+    /* @brief Has MF register. */
+    #define FSL_FEATURE_LLWU_HAS_MF (0)
+    /* @brief Has PF register. */
+    #define FSL_FEATURE_LLWU_HAS_PF (0)
+    /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+    #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+    /* @brief Has no internal module wakeup flag register. */
+    #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
+    /* @brief Has external pin 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16)
+    /* @brief Has external pin 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17)
+    /* @brief Has external pin 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18)
+    /* @brief Has external pin 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19)
+    /* @brief Has external pin 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16)
+    /* @brief Has external pin 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17)
+    /* @brief Has external pin 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18)
+    /* @brief Has external pin 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19)
+    /* @brief Has external pin 8 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0)
+    /* @brief Has external pin 9 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0)
+    /* @brief Has external pin 10 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2)
+    /* @brief Has external pin 11 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3)
+    /* @brief Has external pin 12 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4)
+    /* @brief Has external pin 13 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5)
+    /* @brief Has external pin 14 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6)
+    /* @brief Has external pin 15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
+    /* @brief Has external pin 16 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+    /* @brief Has external pin 17 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+    /* @brief Has external pin 18 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+    /* @brief Has external pin 19 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+    /* @brief Has external pin 20 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+    /* @brief Has external pin 21 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+    /* @brief Has external pin 22 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+    /* @brief Has external pin 23 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+    /* @brief Has external pin 24 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+    /* @brief Has external pin 25 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+    /* @brief Has external pin 26 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+    /* @brief Has external pin 27 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+    /* @brief Has external pin 28 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+    /* @brief Has external pin 29 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+    /* @brief Has external pin 30 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+    /* @brief Has external pin 31 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+    /* @brief Has internal module 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+    /* @brief Has internal module 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+    /* @brief Has internal module 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+    /* @brief Has internal module 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+    /* @brief Has internal module 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+    /* @brief Has internal module 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+    /* @brief Has internal module 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+    /* @brief Has internal module 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+    /* @brief Has Version ID Register (LLWU_VERID). */
+    #define FSL_FEATURE_LLWU_HAS_VERID (0)
+    /* @brief Has Parameter Register (LLWU_PARAM). */
+    #define FSL_FEATURE_LLWU_HAS_PARAM (0)
+    /* @brief Width of registers of the LLWU. */
+    #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+    /* @brief Has DMA Enable register (LLWU_DE). */
+    #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+#elif defined(CPU_MKW41Z512CAT4)
+    /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+    /* @brief Has pins 8-15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+    /* @brief Maximum number of internal modules connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+    /* @brief Number of digital filters. */
+    #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+    /* @brief Has MF register. */
+    #define FSL_FEATURE_LLWU_HAS_MF (0)
+    /* @brief Has PF register. */
+    #define FSL_FEATURE_LLWU_HAS_PF (0)
+    /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+    #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+    /* @brief Has no internal module wakeup flag register. */
+    #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
+    /* @brief Has external pin 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16)
+    /* @brief Has external pin 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17)
+    /* @brief Has external pin 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18)
+    /* @brief Has external pin 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19)
+    /* @brief Has external pin 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16)
+    /* @brief Has external pin 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17)
+    /* @brief Has external pin 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18)
+    /* @brief Has external pin 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19)
+    /* @brief Has external pin 8 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0)
+    /* @brief Has external pin 9 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0)
+    /* @brief Has external pin 10 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2)
+    /* @brief Has external pin 11 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3)
+    /* @brief Has external pin 12 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4)
+    /* @brief Has external pin 13 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5)
+    /* @brief Has external pin 14 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6)
+    /* @brief Has external pin 15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
+    /* @brief Has external pin 16 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+    /* @brief Has external pin 17 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+    /* @brief Has external pin 18 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+    /* @brief Has external pin 19 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+    /* @brief Has external pin 20 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+    /* @brief Has external pin 21 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+    /* @brief Has external pin 22 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+    /* @brief Has external pin 23 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+    /* @brief Has external pin 24 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+    /* @brief Has external pin 25 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+    /* @brief Has external pin 26 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+    /* @brief Has external pin 27 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+    /* @brief Has external pin 28 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+    /* @brief Has external pin 29 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+    /* @brief Has external pin 30 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+    /* @brief Has external pin 31 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+    /* @brief Has internal module 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+    /* @brief Has internal module 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+    /* @brief Has internal module 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+    /* @brief Has internal module 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+    /* @brief Has internal module 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+    /* @brief Has internal module 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+    /* @brief Has internal module 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+    /* @brief Has internal module 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+    /* @brief Has Version ID Register (LLWU_VERID). */
+    #define FSL_FEATURE_LLWU_HAS_VERID (0)
+    /* @brief Has Parameter Register (LLWU_PARAM). */
+    #define FSL_FEATURE_LLWU_HAS_PARAM (0)
+    /* @brief Width of registers of the LLWU. */
+    #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+    /* @brief Has DMA Enable register (LLWU_DE). */
+    #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+#endif /* defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) */
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
+
+/* LPUART module features */
+
+/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
+#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (0)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (0)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (0)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
+
+/* LTC module features */
+
+/* @brief LTC module supports DES algorithm. */
+#define FSL_FEATURE_LTC_HAS_DES (0)
+/* @brief LTC module supports PKHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_PKHA (0)
+/* @brief LTC module supports SHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_SHA (0)
+/* @brief LTC module supports AES GCM mode. */
+#define FSL_FEATURE_LTC_HAS_GCM (0)
+/* @brief LTC module supports DPAMS registers. */
+#define FSL_FEATURE_LTC_HAS_DPAMS (0)
+/* @brief LTC module supports AES with 24 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES192 (0)
+/* @brief LTC module supports AES with 32 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES256 (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (0)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (0)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief MCGFFCLK divider. */
+#define FSL_FEATURE_MCG_FFCLK_DIV (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (0)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (0)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
+#define FSL_FEATURE_MCG_HAS_PLL (0)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (2)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (0)
+/* @brief Has Bandgap Buffer Enable. */
+#define FSL_FEATURE_PMC_HAS_BGBE (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+/* @brief Has Low-Voltage Detect Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVDV (1)
+/* @brief Has Low-Voltage Warning Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVWV (1)
+/* @brief Has LPO. */
+#define FSL_FEATURE_PMC_HAS_LPO (0)
+/* @brief Has VLPx option PMC_REGSC[VLPO]. */
+#define FSL_FEATURE_PMC_HAS_VLPO (1)
+/* @brief Has acknowledge isolation support. */
+#define FSL_FEATURE_PMC_HAS_ACKISO (1)
+/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
+#define FSL_FEATURE_PMC_HAS_REGFPM (0)
+/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
+#define FSL_FEATURE_PMC_HAS_REGONS (1)
+/* @brief Has PMC_HVDSC1. */
+#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
+/* @brief Has PMC_PARAM. */
+#define FSL_FEATURE_PMC_HAS_PARAM (0)
+/* @brief Has PMC_VERID. */
+#define FSL_FEATURE_PMC_HAS_VERID (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* RADIO module features */
+
+/* @brief Zigbee availability. */
+#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1)
+/* @brief Bluetooth availability. */
+#define FSL_FEATURE_RADIO_HAS_BLE (1)
+/* @brief ANT availability */
+#define FSL_FEATURE_RADIO_HAS_ANT (1)
+/* @brief Generic FSK module availability */
+#define FSL_FEATURE_RADIO_HAS_GENFSK (1)
+/* @brief Major version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MAJOR (2)
+/* @brief Minor version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MINOR (0)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (0)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (0)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (0)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (0)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+/* @brief Has Version ID Register (RCM_VERID). */
+#define FSL_FEATURE_RCM_HAS_VERID (0)
+/* @brief Has Parameter Register (RCM_PARAM). */
+#define FSL_FEATURE_RCM_HAS_PARAM (0)
+/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
+#define FSL_FEATURE_RCM_HAS_SRIE (0)
+/* @brief Width of registers of the RCM. */
+#define FSL_FEATURE_RCM_REG_WIDTH (8)
+/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
+#define FSL_FEATURE_RCM_HAS_CORE1 (0)
+/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
+#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
+/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
+#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
+
+/* RSIM module features */
+
+/* No feature definitions */
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (0)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (0)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (0)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
+/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
+/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
+/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
+/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
+/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
+/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (1)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (0)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Bus clock is the source clock for the module. */
+#define FSL_FEATURE_TPM_BUS_CLOCK (0)
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+    ((x) == TPM0 ? (4) : \
+    ((x) == TPM1 ? (2) : \
+    ((x) == TPM2 ? (2) : (-1))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (0)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (0)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (0)
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
+/* @brief Has TPM_COMBINE register. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (1)
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER register. */
+#define FSL_FEATURE_TPM_HAS_FILTER (1)
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+/* @brief Has TPM_QDCTRL register. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \
+    ((x) == TPM0 ? (0) : \
+    ((x) == TPM1 ? (1) : \
+    ((x) == TPM2 ? (1) : (-1))))
+
+/* TRNG module features */
+
+/* No feature definitions */
+
+/* TSI module features */
+
+/* @brief TSI module version. */
+#define FSL_FEATURE_TSI_VERSION (4)
+/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
+#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
+/* @brief Number of TSI channels. */
+#define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief If high/low buffer mode supported */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+/* @brief Has VREF_TRM4. */
+#define FSL_FEATURE_VREF_HAS_TRM4 (0)
+
+/* XCVR_ANALOG module features */
+
+/* No feature definitions */
+
+/* XCVR_PHY module features */
+
+/* No feature definitions */
+
+/* ZLL module features */
+
+/* No feature definitions */
+
+#endif /* _MKW41Z4_FEATURES_H_ */
+
diff --git a/cpu/kw41z/vendor/Common/EmbeddedTypes.h b/cpu/kw41z/vendor/Common/EmbeddedTypes.h
new file mode 100644
index 0000000000000..822661649c025
--- /dev/null
+++ b/cpu/kw41z/vendor/Common/EmbeddedTypes.h
@@ -0,0 +1,181 @@
+/*!
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2017 NXP
+*
+* \file
+*
+* This file holds type definitions that maps the standard c-types into types
+* with guaranteed sizes. The types are target/platform specific and must be edited
+* for each new target/platform.
+* The header file also provides definitions for TRUE, FALSE and NULL.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _EMBEDDEDTYPES_H_
+#define _EMBEDDEDTYPES_H_
+
+
+/************************************************************************************
+*
+*       INCLUDES
+*
+************************************************************************************/
+
+#include <stdint.h>
+
+
+/************************************************************************************
+*
+*       TYPE DEFINITIONS
+*
+************************************************************************************/
+
+/* boolean types */
+typedef uint8_t   bool_t;
+
+typedef uint8_t   index_t;
+
+/* TRUE/FALSE definition*/
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* null pointer definition*/
+#ifndef NULL
+#define NULL (( void * )( 0x0UL ))
+#endif
+
+#if defined(__GNUC__)
+#define PACKED_STRUCT struct __attribute__ ((__packed__))
+#define PACKED_UNION  union __attribute__ ((__packed__))
+#elif defined(__IAR_SYSTEMS_ICC__)
+#define PACKED_STRUCT __packed struct
+#define PACKED_UNION __packed union
+#else
+#define PACKED_STRUCT struct
+#define PACKED_UNION union
+#endif
+
+typedef unsigned char uintn8_t;
+typedef unsigned long uintn32_t;
+
+typedef unsigned char uchar_t;
+
+#if !defined(MIN)
+#define MIN(a,b)                    (((a) < (b))?(a):(b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a,b)                    (((a) > (b))?(a):(b))
+#endif
+
+/* Compute the number of elements of an array */
+#define NumberOfElements(x) (sizeof(x)/sizeof((x)[0]))
+
+/* Compute the size of a string initialized with quotation marks */
+#define SizeOfString(string) (sizeof(string) - 1)
+
+#define GetRelAddr(strct, member) ((uint32_t)&(((strct*)(void *)0)->member))
+#define GetSizeOfMember(strct, member) sizeof(((strct*)(void *)0)->member)
+
+/* Type definitions for link configuration of instantiable layers  */
+#define gInvalidInstanceId_c (instanceId_t)(-1)
+typedef uint32_t instanceId_t;
+
+/* Shift definitions */
+#define SHIFT0      (0)
+#define SHIFT1      (1)
+#define SHIFT2      (2)
+#define SHIFT3      (3)
+#define SHIFT4      (4)
+#define SHIFT5      (5)
+#define SHIFT6      (6)
+#define SHIFT7      (7)
+#define SHIFT8      (8)
+#define SHIFT9      (9)
+#define SHIFT10     (10)
+#define SHIFT11     (11)
+#define SHIFT12     (12)
+#define SHIFT13     (13)
+#define SHIFT14     (14)
+#define SHIFT15     (15)
+#define SHIFT16     (16)
+#define SHIFT17     (17)
+#define SHIFT18     (18)
+#define SHIFT19     (19)
+#define SHIFT20     (20)
+#define SHIFT21     (21)
+#define SHIFT22     (22)
+#define SHIFT23     (23)
+#define SHIFT24     (24)
+#define SHIFT25     (25)
+#define SHIFT26     (26)
+#define SHIFT27     (27)
+#define SHIFT28     (28)
+#define SHIFT29     (29)
+#define SHIFT30     (30)
+#define SHIFT31     (31)
+
+#define SHIFT32     (32)
+#define SHIFT33     (33)
+#define SHIFT34     (34)
+#define SHIFT35     (35)
+#define SHIFT36     (36)
+#define SHIFT37     (37)
+#define SHIFT38     (38)
+#define SHIFT39     (39)
+#define SHIFT40     (40)
+#define SHIFT41     (41)
+#define SHIFT42     (42)
+#define SHIFT43     (43)
+#define SHIFT44     (44)
+#define SHIFT45     (45)
+#define SHIFT46     (46)
+#define SHIFT47     (47)
+#define SHIFT48     (48)
+#define SHIFT49     (49)
+#define SHIFT50     (50)
+#define SHIFT51     (51)
+#define SHIFT52     (52)
+#define SHIFT53     (53)
+#define SHIFT54     (54)
+#define SHIFT55     (55)
+#define SHIFT56     (56)
+#define SHIFT57     (57)
+#define SHIFT58     (58)
+#define SHIFT59     (59)
+#define SHIFT60     (60)
+#define SHIFT61     (61)
+#define SHIFT62     (62)
+#define SHIFT63     (63)
+
+
+#endif /* _EMBEDDEDTYPES_H_ */
diff --git a/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction.h b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction.h
new file mode 100644
index 0000000000000..8f974571164b9
--- /dev/null
+++ b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction.h
@@ -0,0 +1,608 @@
+/*!
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2017 NXP
+*
+* \file
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#ifndef _FSL_OS_ABSTRACTION_H_
+#define _FSL_OS_ABSTRACTION_H_
+
+#include "EmbeddedTypes.h"
+#include "fsl_os_abstraction_config.h"
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+    
+/*! *********************************************************************************
+*************************************************************************************
+* Public type definitions
+*************************************************************************************
+********************************************************************************** */
+/*! @brief Type for the Task Priority*/    
+  typedef uint16_t osaTaskPriority_t;   
+/*! @brief Type for the timer definition*/    
+  typedef enum  {
+    osaTimer_Once             =     0, /*!< one-shot timer*/
+    osaTimer_Periodic         =     1  /*!< repeating timer*/ 
+  } osaTimer_t; 
+  /*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */  
+  typedef void* osaTaskId_t;
+/*! @brief Type for the parameter to be passed to the task at its creation */    
+  typedef void* osaTaskParam_t;
+  /*! @brief Type for task pointer. Task prototype declaration */    
+  typedef void (*osaTaskPtr_t) (osaTaskParam_t task_param); 
+/*! @brief Type for the semaphore handler, returned by the OSA_SemaphoreCreate function. */    
+  typedef void* osaSemaphoreId_t; 
+/*! @brief Type for the mutex handler, returned by the OSA_MutexCreate function. */      
+  typedef void* osaMutexId_t; 
+/*! @brief Type for the event handler, returned by the OSA_EventCreate function. */        
+  typedef void* osaEventId_t; 
+/*! @brief Type for an event flags group, bit 32 is reserved. */  
+  typedef uint32_t osaEventFlags_t; 
+/*! @brief Message definition. */    
+  typedef void* osaMsg_t; 
+/*! @brief Type for the message queue handler, returned by the OSA_MsgQCreate function. */          
+  typedef void* osaMsgQId_t; 
+  /*! @brief Type for the Timer handler, returned by the OSA_TimerCreate function. */          
+  typedef void *osaTimerId_t;
+/*! @brief Type for the Timer callback function pointer. */          
+  typedef void (*osaTimerFctPtr_t) (void const *argument); 
+/*! @brief Thread Definition structure contains startup information of a thread.*/ 
+typedef struct osaThreadDef_tag  {
+  osaTaskPtr_t           pthread;    /*!< start address of thread function*/ 
+  uint32_t             tpriority;    /*!< initial thread priority*/ 
+  uint32_t             instances;    /*!< maximum number of instances of that thread function*/
+  uint32_t             stacksize;    /*!< stack size requirements in bytes; 0 is default stack size*/
+  uint32_t              *tstack;
+  void                 *tlink;
+  uint8_t               *tname;
+  bool_t               useFloat;
+} osaThreadDef_t;
+/*! @brief Thread Link Definition structure .*/ 
+typedef struct osaThreadLink_tag{
+  uint8_t          link[12];
+  osaTaskId_t      osThreadId;
+  osaThreadDef_t    *osThreadDefHandle;
+  uint32_t          *osThreadStackHandle;
+}osaThreadLink_t, *osaThreadLinkHandle_t;
+
+/*! @Timer Definition structure contains timer parameters.*/ 
+typedef struct osaTimerDef_tag  {
+  osaTimerFctPtr_t       pfCallback;    /* < start address of a timer function */
+  void                   *argument;
+} osaTimerDef_t;
+/*! @brief Defines the return status of OSA's functions */
+typedef enum osaStatus_tag
+{
+    osaStatus_Success = 0U, /*!< Success */
+    osaStatus_Error   = 1U, /*!< Failed */
+    osaStatus_Timeout = 2U, /*!< Timeout occurs while waiting */
+    osaStatus_Idle    = 3U  /*!< Used for bare metal only, the wait object is not ready
+                                and timeout still not occur */
+}osaStatus_t;
+
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public macros
+*************************************************************************************
+********************************************************************************** */
+#if defined (FSL_RTOS_MQX)
+    #define USE_RTOS 1
+#elif defined (FSL_RTOS_FREE_RTOS)
+    #define USE_RTOS 1
+#elif defined (FSL_RTOS_UCOSII)
+    #define USE_RTOS 1
+#elif defined (FSL_RTOS_UCOSIII)
+    #define USE_RTOS 1
+#else
+    #define USE_RTOS 0
+#endif
+
+#define OSA_PRIORITY_IDLE          (6)
+#define OSA_PRIORITY_LOW           (5)
+#define OSA_PRIORITY_BELOW_NORMAL  (4)
+#define OSA_PRIORITY_NORMAL        (3)
+#define OSA_PRIORITY_ABOVE_NORMAL  (2)
+#define OSA_PRIORITY_HIGH          (1)
+#define OSA_PRIORITY_REAL_TIME     (0)
+#define OSA_TASK_PRIORITY_MAX (0)
+#define OSA_TASK_PRIORITY_MIN (15)  
+#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) 
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define osaWaitForever_c   ((uint32_t)(-1))
+#define osaEventFlagsAll_c  ((osaEventFlags_t)(0x00FFFFFF))
+#define osThreadStackArray(name) osThread_##name##_stack
+#define osThreadStackDef(name, stacksize, instances) \
+        uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize)*(instances)];
+
+/* ==== Thread Management ==== */
+
+/* Create a Thread Definition with function, priority, and stack requirements. 
+ * \param         name         name of the thread function. 
+ * \param         priority     initial priority of the thread function.
+ * \param         instances    number of possible thread instances.
+ * \param         stackSz      stack size (in bytes) requirements for the thread function.
+ * \param         useFloat             
+ */ 
+#if defined(FSL_RTOS_MQX)        
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)  \
+osaThreadLink_t osThreadLink_##name[instances] = {0}; \
+osThreadStackDef(name, stackSz, instances) \
+osaThreadDef_t os_thread_def_##name = { (name), \
+                                       (priority), \
+                                       (instances), \
+                                       (stackSz), \
+                                       osThreadStackArray(name), \
+                                       osThreadLink_##name, \
+                                       (uint8_t*) #name,\
+                                       (useFloat)}
+#elif defined (FSL_RTOS_UCOSII)         
+  #if gTaskMultipleInstancesManagement_c                                       
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)  \
+osaThreadLink_t osThreadLink_##name[instances] = {0}; \
+osThreadStackDef(name, stackSz, instances) \
+osaThreadDef_t os_thread_def_##name = { (name), \
+                                        (priority), \
+                                        (instances), \
+                                        (stackSz), \
+                                        osThreadStackArray(name), \
+                                        osThreadLink_##name, \
+                                        (uint8_t*) #name,\
+                                        (useFloat)}                                       
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)  \
+osThreadStackDef(name, stackSz, instances) \
+osaThreadDef_t os_thread_def_##name = { (name), \
+                                        (priority), \
+                                        (instances), \
+                                        (stackSz), \
+                                        osThreadStackArray(name), \
+                                        NULL, \
+                                        (uint8_t*) #name,\
+                                        (useFloat)}                                                                               
+#endif
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)  \
+osaThreadDef_t os_thread_def_##name = { (name), \
+                                       (priority), \
+                                       (instances), \
+                                       (stackSz), \
+                                       NULL, \
+                                       NULL, \
+                                       (uint8_t*) #name,\
+                                       (useFloat)}                                       
+#endif                                       
+/* Access a Thread defintion. 
+ * \param         name          name of the thread definition object. 
+ */
+#define OSA_TASK(name)  \
+&os_thread_def_##name
+
+#define OSA_TASK_PROTO(name)  \
+extern osaThreadDef_t os_thread_def_##name
+/*  ==== Timer Management  ====
+ * Define a Timer object.
+ * \param         name          name of the timer object.
+ * \param         function      name of the timer call back function.
+ */
+
+#define OSA_TIMER_DEF(name, function)  \
+osaTimerDef_t os_timer_def_##name = \
+{ (function), NULL }
+
+/* Access a Timer definition. 
+ * \param         name          name of the timer object.
+ */
+#define OSA_TIMER(name) \
+&os_timer_def_##name
+
+
+/*****************************************************************************
+******************************************************************************
+* Public memory declarations
+******************************************************************************
+*****************************************************************************/
+extern const uint8_t gUseRtos_c;
+
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*!
+ * @name Task management
+ * @{
+ */
+
+/*!
+ * @brief Creates a task.
+ *
+ * This function is used to create task based on the resources defined
+ * by the macro OSA_TASK_DEFINE.
+ *
+ * @param thread_def      pointer to the osaThreadDef_t structure which defines the task.
+ * @param task_param     Pointer to be passed to the task when it is created.
+ *
+ * @retval taskId The task is successfully created.
+ * @retval NULL   The task can not be created..
+ *
+ * Example:
+   @code
+   osaTaskId_t taskId;
+   OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH,  1,   800, 0);;
+   taskId = OSA__TaskCreate(OSA__TASK(Job1), (osaTaskParam_t)NULL);
+   @endcode
+ */
+osaTaskId_t OSA_TaskCreate(osaThreadDef_t *thread_def, osaTaskParam_t task_param);
+
+/*!
+ * @brief Gets the handler of active task.
+ *
+ * @return Handler to current active task.
+ */
+osaTaskId_t OSA_TaskGetId(void);
+
+/*!
+ * @brief Puts the active task to the end of scheduler's queue.
+ *
+ * When a task calls this function, it gives up the CPU and puts itself to the
+ * end of a task ready list.
+ *
+ * @retval osaStatus_Success The function is called successfully.
+ * @retval osaStatus_Error   Error occurs with this function.
+  */
+osaStatus_t OSA_TaskYield(void);
+
+/*!
+ * @brief Gets the priority of a task.
+ *
+ * @param taskId The handler of the task whose priority is received.
+ *
+ * @return Task's priority.
+ */
+osaTaskPriority_t OSA_TaskGetPriority(osaTaskId_t taskId);
+
+/*!
+ * @brief Sets the priority of a task.
+ *
+ * @param taskId  The handler of the task whose priority is set.
+ * @param taskPriority The priority to set.
+ *
+ * @retval osaStatus_Success Task's priority is set successfully.
+ * @retval osaStatus_Error   Task's priority can not be set.
+ */
+osaStatus_t OSA_TaskSetPriority(osaTaskId_t taskId, osaTaskPriority_t taskPriority);
+/*!
+ * @brief Destroys a previously created task.
+ *
+ * @param taskId The handler of the task to destroy. Returned by the OSA_TaskCreate function.
+ *
+ * @retval osaStatus_Success The task was successfully destroyed.
+ * @retval osaStatus_Error   Task destruction failed or invalid parameter.
+  */
+osaStatus_t OSA_TaskDestroy(osaTaskId_t taskId);
+
+/*!
+ * @brief Creates a semaphore with a given value.
+ *
+ * This function creates a semaphore and sets the value to the parameter
+ * initValue.
+ *
+ * @param initValue Initial value the semaphore will be set to.
+ *
+ * @retval handler to the new semaphore if the semaphore is created successfully.
+ * @retval NULL   if the semaphore can not be created.
+ *
+ *
+ */
+osaSemaphoreId_t OSA_SemaphoreCreate(uint32_t initValue);
+
+/*!
+ * @brief Destroys a previously created semaphore.
+ *
+ * @param semId Pointer to the semaphore to destroy.
+ *
+ * @retval osaStatus_Success The semaphore is successfully destroyed.
+ * @retval osaStatus_Error   The semaphore can not be destroyed.
+ */
+osaStatus_t OSA_SemaphoreDestroy(osaSemaphoreId_t semId);
+
+/*!
+ * @brief Pending a semaphore with timeout.
+ *
+ * This function checks the semaphore's counting value. If it is positive,
+ * decreases it and returns osaStatus_Success. Otherwise, a timeout is used
+ * to wait.
+ *
+ * @param semId    Pointer to the semaphore.
+ * @param millisec The maximum number of milliseconds to wait if semaphore is not
+ *                 positive. Pass osaWaitForever_c to wait indefinitely, pass 0
+ *                 will return osaStatus_Timeout immediately.
+ *
+ * @retval osaStatus_Success  The semaphore is received.
+ * @retval osaStatus_Timeout  The semaphore is not received within the specified 'timeout'.
+ * @retval osaStatus_Error    An incorrect parameter was passed.
+ */
+osaStatus_t OSA_SemaphoreWait(osaSemaphoreId_t semId, uint32_t millisec);
+
+/*!
+ * @brief Signals for someone waiting on the semaphore to wake up.
+ *
+ * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
+ * the semaphore's counting value.
+ *
+ * @param semId Pointer to the semaphore to signal.
+ *
+ * @retval osaStatus_Success The semaphore is successfully signaled.
+ * @retval osaStatus_Error   The object can not be signaled or invalid parameter.
+ *
+ */
+osaStatus_t OSA_SemaphorePost(osaSemaphoreId_t semId);
+
+/*!
+ * @brief Create an unlocked mutex.
+ *
+ * This function creates a non-recursive mutex and sets it to unlocked status.
+ *
+ * @param none.
+ *
+ * @retval handler to the new mutex if the mutex is created successfully.
+ * @retval NULL   if the mutex can not be created.
+ */
+osaMutexId_t OSA_MutexCreate(void);
+
+/*!
+ * @brief Waits for a mutex and locks it.
+ *
+ * This function checks the mutex's status. If it is unlocked, locks it and returns the
+ * osaStatus_Success. Otherwise, waits for a timeout in milliseconds to lock.
+ *
+ * @param mutexId Pointer to the Mutex.
+ * @param millisec The maximum number of milliseconds to wait for the mutex.
+ *                 If the mutex is locked, Pass the value osaWaitForever_c will
+ *                 wait indefinitely, pass 0 will return osaStatus_Timeout
+ *                 immediately.
+ *
+ * @retval osaStatus_Success The mutex is locked successfully.
+ * @retval osaStatus_Timeout Timeout occurred.
+ * @retval osaStatus_Error   Incorrect parameter was passed.
+ *
+ * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked.
+ */
+osaStatus_t OSA_MutexLock(osaMutexId_t mutexId, uint32_t millisec);
+
+/*!
+ * @brief Unlocks a previously locked mutex.
+ *
+ * @param mutexId Pointer to the Mutex.
+ *
+ * @retval osaStatus_Success The mutex is successfully unlocked.
+ * @retval osaStatus_Error   The mutex can not be unlocked or invalid parameter.
+ */
+osaStatus_t OSA_MutexUnlock(osaMutexId_t mutexId);
+
+/*!
+ * @brief Destroys a previously created mutex.
+ *
+ * @param mutexId Pointer to the Mutex.
+ *
+ * @retval osaStatus_Success The mutex is successfully destroyed.
+ * @retval osaStatus_Error   The mutex can not be destroyed.
+ *
+ */
+osaStatus_t OSA_MutexDestroy(osaMutexId_t mutexId);
+
+/*!
+ * @brief Initializes an event object with all flags cleared.
+ *
+ * This function creates an event object and set its clear mode. If autoClear
+ * is TRUE, when a task gets the event flags, these flags will be
+ * cleared automatically. Otherwise these flags must
+ * be cleared manually.
+ *
+ * @param autoClear TRUE The event is auto-clear.
+ *                  FALSE The event manual-clear
+ * @retval handler to the new event if the event is created successfully.
+ * @retval NULL   if the event can not be created.
+ */
+osaEventId_t OSA_EventCreate(bool_t autoClear);
+
+/*!
+ * @brief Sets one or more event flags.
+ *
+ * Sets specified flags of an event object.
+ *
+ * @param eventId     Pointer to the event.
+ * @param flagsToSet  Flags to be set.
+ *
+ * @retval osaStatus_Success The flags were successfully set.
+ * @retval osaStatus_Error   An incorrect parameter was passed.
+ */
+osaStatus_t OSA_EventSet(osaEventId_t eventId, osaEventFlags_t flagsToSet);
+
+/*!
+ * @brief Clears one or more flags.
+ *
+ * Clears specified flags of an event object.
+ *
+ * @param eventId       Pointer to the event.
+ * @param flagsToClear  Flags to be clear.
+ *
+ * @retval osaStatus_Success The flags were successfully cleared.
+ * @retval osaStatus_Error   An incorrect parameter was passed.
+ */
+osaStatus_t OSA_EventClear(osaEventId_t eventId, osaEventFlags_t flagsToClear);
+
+/*!
+ * @brief Waits for specified event flags to be set.
+ *
+ * This function waits for a combination of flags to be set in an event object.
+ * Applications can wait for any/all bits to be set. Also this function could
+ * obtain the flags who wakeup the waiting task.
+ *
+ * @param eventId     Pointer to the event.
+ * @param flagsToWait Flags that to wait.
+ * @param waitAll     Wait all flags or any flag to be set.
+ * @param millisec    The maximum number of milliseconds to wait for the event.
+ *                    If the wait condition is not met, pass osaWaitForever_c will
+ *                    wait indefinitely, pass 0 will return osaStatus_Timeout
+ *                    immediately.
+ * @param setFlags    Flags that wakeup the waiting task are obtained by this parameter.
+ *
+ * @retval osaStatus_Success The wait condition met and function returns successfully.
+ * @retval osaStatus_Timeout Has not met wait condition within timeout.
+ * @retval osaStatus_Error   An incorrect parameter was passed.
+ 
+ *
+ * @note    Please pay attention to the flags bit width, FreeRTOS uses the most
+ *          significant 8 bis as control bits, so do not wait these bits while using
+ *          FreeRTOS.
+ *
+ */
+osaStatus_t OSA_EventWait(osaEventId_t eventId, osaEventFlags_t flagsToWait, bool_t waitAll, uint32_t millisec, osaEventFlags_t *pSetFlags);
+
+/*!
+ * @brief Destroys a previously created event object.
+ *
+ * @param eventId Pointer to the event.
+ *
+ * @retval osaStatus_Success The event is successfully destroyed.
+ * @retval osaStatus_Error   Event destruction failed.
+ */
+osaStatus_t OSA_EventDestroy(osaEventId_t eventId);
+
+/*!
+ * @brief Initializes a message queue.
+ *
+ * This function  allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*.
+ *
+ * @param msgNo :number of messages the message queue should accommodate.
+ *               This parameter should not exceed osNumberOfMessages defined in OSAbstractionConfig.h. 
+ *
+* @return:  Handler to access the queue for put and get operations. If message queue
+ *         creation failed, return NULL.
+ */
+osaMsgQId_t OSA_MsgQCreate(uint32_t  msgNo);
+
+/*!
+ * @brief Puts a message at the end of the queue.
+ *
+ * This function puts a message to the end of the message queue. If the queue
+ * is full, this function returns the osaStatus_Error;
+ *
+ * @param msgQId  pointer to queue returned by the OSA_MsgQCreate function.
+ * @param pMessage Pointer to the message to be put into the queue.
+ *
+ * @retval osaStatus_Success Message successfully put into the queue.
+ * @retval osaStatus_Error   The queue was full or an invalid parameter was passed.
+ */
+osaStatus_t OSA_MsgQPut(osaMsgQId_t msgQId, osaMsg_t pMessage);
+
+/*!
+ * @brief Reads and remove a message at the head of the queue.
+ *
+ * This function gets a message from the head of the message queue. If the
+ * queue is empty, timeout is used to wait.
+ *
+ * @param msgQId   Queue handler returned by the OSA_MsgQCreate function.
+ * @param pMessage Pointer to a memory to save the message.
+ * @param millisec The number of milliseconds to wait for a message. If the
+ *                 queue is empty, pass osaWaitForever_c will wait indefinitely,
+ *                 pass 0 will return osaStatus_Timeout immediately.
+ *
+ * @retval osaStatus_Success   Message successfully obtained from the queue.
+ * @retval osaStatus_Timeout   The queue remains empty after timeout.
+ * @retval osaStatus_Error     Invalid parameter.
+ */
+osaStatus_t OSA_MsgQGet(osaMsgQId_t msgQId, osaMsg_t pMessage, uint32_t millisec);
+
+/*!
+ * @brief Destroys a previously created queue.
+ *
+ * @param msgQId queue handler returned by the OSA_MsgQCreate function.
+ *
+ * @retval osaStatus_Success The queue was successfully destroyed.
+ * @retval osaStatus_Error   Message queue destruction failed.
+*/
+osaStatus_t OSA_MsgQDestroy(osaMsgQId_t msgQId);
+
+/*!
+ * @brief Enable all interrupts.
+*/
+void OSA_InterruptEnable(void);
+
+/*!
+ * @brief Disable all interrupts.
+*/
+void OSA_InterruptDisable(void);
+
+/*!
+ * @brief Enable all interrupts using PRIMASK.
+*/
+void OSA_EnableIRQGlobal(void);
+
+/*!
+ * @brief Disable all interrupts using PRIMASK.
+*/
+void OSA_DisableIRQGlobal(void);
+
+/*!
+ * @brief Delays execution for a number of milliseconds.
+ *
+ * @param millisec The time in milliseconds to wait.
+ */
+void OSA_TimeDelay(uint32_t millisec);
+
+/*!
+ * @brief This function gets current time in milliseconds.
+ *
+ * @retval current time in milliseconds
+ */
+uint32_t OSA_TimeGetMsec(void);
+
+/*!
+ * @brief Installs the interrupt handler.
+ *
+ * @param IRQNumber IRQ number of the interrupt.
+ * @param handler The interrupt handler to install.
+ */
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void));
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif  
diff --git a/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h
new file mode 100644
index 0000000000000..43d2927c67f37
--- /dev/null
+++ b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h
@@ -0,0 +1,63 @@
+/*!
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2017 NXP
+*
+* \file
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
+#define _FSL_OS_ABSTRACTION_CONFIG_H_
+
+#ifndef osNumberOfSemaphores
+#define osNumberOfSemaphores 5
+#endif
+#ifndef osNumberOfMutexes
+#define osNumberOfMutexes    5
+#endif
+#ifndef osNumberOfMessageQs
+#define osNumberOfMessageQs  0
+#endif
+#ifndef osNumberOfMessages
+#define osNumberOfMessages   10
+#endif
+#ifndef osNumberOfEvents
+#define osNumberOfEvents     5
+#endif
+
+#ifndef gMainThreadStackSize_c
+#define gMainThreadStackSize_c 1024
+#endif
+#ifndef gMainThreadPriority_c
+#define gMainThreadPriority_c 7
+#endif
+
+#ifndef gTaskMultipleInstancesManagement_c
+#define gTaskMultipleInstancesManagement_c  0
+#endif
+#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile b/cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile
new file mode 100644
index 0000000000000..ab64856aad2a3
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile
@@ -0,0 +1,3 @@
+MODULE = mcux_xcvr
+
+include $(RIOTBASE)/Makefile.base
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c
new file mode 100644
index 0000000000000..7a5c118ce0c46
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c
@@ -0,0 +1,212 @@
+/*!
+* Copyright 2016-2017 NXP
+*
+* \file
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_xcvr.h"
+#include "xcvr_test_fsk.h"
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private type definitions
+*************************************************************************************
+********************************************************************************** */
+enum {
+    gDftNormal_c          = 0,
+    gDftTxNoMod_Carrier_c = 1,
+    gDftTxPattern_c       = 2,
+    gDftTxRandom_c        = 3,
+};
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private memory declarations
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public prototypes
+*************************************************************************************
+********************************************************************************** */
+void XcvrFskModTx(void);
+void XcvrFskNoModTx(void);
+void XcvrFskIdle(void);
+void XcvrFskTxRand(void);
+void XcvrFskLoadPattern(uint32_t u32Pattern);
+void XcvrFskSetTxPower(uint8_t u8TxPow);
+void XcvrFskSetTxChannel(uint8_t u8TxChan);
+void XcvrFskRestoreTXControl(void);
+uint8_t XcvrFskGetInstantRssi(void);
+
+/*! *********************************************************************************
+* XcvrFskModTx
+***********************************************************************************/
+void XcvrFskModTx(void)
+{
+    XcvrFskIdle();
+    XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK |
+                           XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK);
+    XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxPattern_c) |
+    XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK;
+    XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK;
+    XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
+}
+
+/*! *********************************************************************************
+* XcvrFskNoModTx
+***********************************************************************************/
+void XcvrFskNoModTx(void)
+{
+    XcvrFskIdle();
+    XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK |
+                           XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK);
+    XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxNoMod_Carrier_c);
+    XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK;
+    XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
+}
+
+/*! *********************************************************************************
+* XcvrFskIdle
+***********************************************************************************/
+void XcvrFskIdle(void)
+{
+    XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | 
+                           XCVR_TX_DIG_CTRL_LFSR_EN_MASK | 
+                           XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK);
+    XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
+    XCVR_MISC->DTEST_CTRL &= ~XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK;
+}
+
+/*! *********************************************************************************
+* XcvrFskTxRand
+***********************************************************************************/
+void XcvrFskTxRand(void)
+{
+    XcvrFskIdle();
+    XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK |
+                           XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK |
+                           XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK);
+    XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxRandom_c) |
+                         XCVR_TX_DIG_CTRL_LFSR_LENGTH(0) | /* length 9 */
+                         XCVR_TX_DIG_CTRL_LFSR_EN_MASK;
+    XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK;
+    XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
+}
+
+/*! *********************************************************************************
+* XcvrFskLoadPattern
+***********************************************************************************/
+void XcvrFskLoadPattern(uint32_t u32Pattern)
+{
+    XCVR_TX_DIG->DFT_PATTERN = u32Pattern;
+}
+
+/*! *********************************************************************************
+* XcvrFskGetInstantRssi
+***********************************************************************************/
+uint8_t XcvrFskGetInstantRssi(void)
+{
+    uint8_t u8Rssi;
+    uint32_t t1,t2,t3;
+    t1 = XCVR_RX_DIG->RX_DIG_CTRL;
+    t2 = XCVR_RX_DIG->RSSI_CTRL_0;
+    t3 = XCVR_PHY->CFG1;
+    XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(1) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | /* 1=OSR8, 2=OSR16, 4=OSR32 */
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0) | /* Source Rate 0 is default */
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) |
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(22) | /* Dec filt gain for SRC rate ==  0 */
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1) ;
+
+    XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK;
+    XCVR_RX_DIG->RSSI_CTRL_0 |=  XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(0x5);
+
+    XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK;
+    XCVR_RX_DIG->RSSI_CTRL_0 |=  XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(0x3); 
+
+    uint32_t temp = XCVR_PHY->CFG1;
+    temp &= ~XCVR_PHY_CFG1_CTS_THRESH_MASK;
+    temp |= XCVR_PHY_CFG1_CTS_THRESH(0xFF);
+    XCVR_PHY->CFG1 = temp;
+
+    XCVR_ForceRxWu();
+    for(uint32_t i = 0; i < 10000; i++)
+    {
+        __asm("nop");
+    }
+    u8Rssi = (uint8_t)((XCVR_RX_DIG->RSSI_CTRL_1 & 
+                        XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) >> 
+                        XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT);
+    XCVR_ForceRxWd();
+
+    XCVR_RX_DIG->RX_DIG_CTRL = t1;
+    XCVR_RX_DIG->RSSI_CTRL_0 = t2;
+    XCVR_PHY->CFG1 = t3;
+    return u8Rssi;
+}
+
+/*! *********************************************************************************
+* XcvrFskSetTxPower
+***********************************************************************************/
+void XcvrFskSetTxPower(uint8_t u8TxPow)
+{
+    return;
+}
+
+/*! *********************************************************************************
+* XcvrFskSetTxChannel
+***********************************************************************************/
+void XcvrFskSetTxChannel(uint8_t u8TxChan)
+{
+    return;
+}
+
+/*! *********************************************************************************
+* XcvrFskRestoreTXControl
+* After calling this function user should switch to
+* previous protocol and set the protocol channel to default
+***********************************************************************************/
+void XcvrFskRestoreTXControl(void)
+{
+    return;
+}
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h
new file mode 100644
index 0000000000000..a3be92c53c2e5
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h
@@ -0,0 +1,157 @@
+/*!
+* Copyright 2016-2017 NXP
+*
+* \file
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef __XCVR_TEST_FSK_H__
+#define __XCVR_TEST_FSK_H__
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public type definitions
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public prototypes
+*************************************************************************************
+********************************************************************************** */
+/*! *********************************************************************************
+* \brief  This function returns instant RSSI value and returns it as unsigned byte.
+*
+* \param[in] None.
+*
+* \ingroup TestFunctions
+*
+* \details Initialization of the xcvr is necessary prior to calling this function
+*
+***********************************************************************************/
+extern uint8_t XcvrFskGetInstantRssi(void);
+
+/*! *********************************************************************************
+* \brief  This function sets the transceiver into continuous modulated transmission.
+*
+* \param[in] None.
+*
+* \ingroup TestFunctions
+*
+* \details Initialization of the xcvr and calling XcvrFskLoadPattern are necessary
+*         prior to calling this function
+*
+***********************************************************************************/
+extern void XcvrFskModTx(void);
+
+/*! *********************************************************************************
+* \brief  This function sets the transceiver into continuous unmodulated transmission.
+*
+* \param[in] None.
+*
+* \ingroup TestFunctions
+*
+* \details 
+*
+***********************************************************************************/
+extern void XcvrFskNoModTx(void);
+
+/*! *********************************************************************************
+* \brief  This function sets the transceiver into idle.
+*
+* \param[in] None.
+*
+* \ingroup TestFunctions
+*
+* \details 
+*
+***********************************************************************************/
+extern void XcvrFskIdle(void);
+
+/*! *********************************************************************************
+* \brief  This function sets the transceiver into continuous modulated transmission.
+*
+* \param[in] None.
+*
+* \ingroup TestFunctions
+*
+* \details The modulation used is a pseudo-random pattern generated using a LFSR.
+*
+***********************************************************************************/
+extern void XcvrFskTxRand(void);
+
+/*! *********************************************************************************
+* \brief  This function loads a 32 bit value into the pattern register used by XcvrFskModTx.
+*
+* \param[in] u32Pattern The pattern to be loaded.
+*
+* \ingroup TestFunctions
+*
+* \details 
+*
+***********************************************************************************/
+extern void XcvrFskLoadPattern(uint32_t u32Pattern);
+
+/*! *********************************************************************************
+* \brief  This function gives tx power control to xcvr and sets the power to u8TxPow.
+*
+* \param[in] u8TxPow Values should be between 0x00 and 0x0F.
+*
+* \ingroup TestFunctions
+*
+* \details 
+*
+***********************************************************************************/
+extern void XcvrFskSetTxPower(uint8_t u8TxPow);
+
+/*! *********************************************************************************
+* \brief  This function gives tx channel control to xcvr and sets the channel to u8TxChan.
+*
+* \param[in] u8TxChan Values should be between 0 and 39.
+*
+* \ingroup TestFunctions
+*
+* \details 
+*
+***********************************************************************************/
+extern void XcvrFskSetTxChannel(uint8_t u8TxChan);
+
+/*! *********************************************************************************
+* \brief  This function gives tx channel control and power to the upper layer.
+*
+* \param[in] None.
+*
+* \ingroup TestFunctions
+*
+* \details Call this function only if XcvrFskSetTxChannel or XcvrFskSetTxPower were called
+*         previously.
+*
+***********************************************************************************/
+extern void XcvrFskRestoreTXControl(void);
+
+#endif
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.c
new file mode 100644
index 0000000000000..31812fa9f773b
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cpu.h"
+#include "fsl_xcvr.h"
+#include "dbg_ram_capture.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if RADIO_IS_GEN_3P0
+#define PKT_RAM_SIZE_16B_WORDS  (1152) /* Number of 16bit entries in each Packet RAM bank */
+#else
+#define PKT_RAM_SIZE_16B_WORDS  (544) /* Number of 16bit entries in each Packet RAM bank */
+#endif /* RADIO_IS_GEN_3P0 */
+#define SIGN_EXTND_12_16(x)     ((x) | (((x) & 0x800) ? 0xF000 : 0x0))
+#define SIGN_EXTND_5_8(x)       ((x) | (((x) & 0x10) ? 0xE0 : 0x0))
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void dbg_ram_init(void)
+{
+    XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK;  /* Turns on clocking to DMA/DBG blocks */
+    XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK;  /* Make PKT RAM available to just XCVR */
+
+    /* Some external code must perform the RX warmup request. */
+}
+
+
+dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer)
+{
+    dbgRamStatus_t status = DBG_RAM_SUCCESS;
+    uint32_t temp;
+    volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1;
+    uint8_t * output_ptr;
+    uint16_t i;
+
+    /* Some external code must perform the RX warmup request after the dbg_ram_init() call */
+
+    if (result_buffer == NULL)
+    {
+        status = DBG_RAM_FAIL_NULL_POINTER;
+    }
+    else
+    {
+        if (buffer_sz_bytes > (544*2*2))
+        {
+            status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT;
+        }
+        else
+        {
+            temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK;
+            switch (dbg_page)
+            {
+                case DBG_PAGE_RXDIGIQ:
+                case DBG_PAGE_RAWADCIQ:
+                case DBG_PAGE_DCESTIQ:
+                    XCVR_MISC->PACKET_RAM_CTRL =  temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page);
+
+                    while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2)))
+                    {
+                        /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */
+                    }
+                    /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */
+                    output_ptr = result_buffer;
+#if !RADIO_IS_GEN_2P1
+                    pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]);
+                    pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]);
+#else
+                    pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]);
+                    pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */
+#endif /* !RADIO_IS_GEN_2P1 */
+                    /* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */
+                    for (i = 0; i < buffer_sz_bytes / 4; i++)
+                    {
+                        *output_ptr++ = *pkt_ram_ptr0++;
+                        *output_ptr++ = *pkt_ram_ptr0++;
+                        *output_ptr++ = *pkt_ram_ptr1++;
+                        *output_ptr++ = *pkt_ram_ptr1++;
+                    }
+
+                    break;
+                case DBG_PAGE_RXINPH:
+                case DBG_PAGE_DEMOD_HARD:
+                case DBG_PAGE_DEMOD_SOFT:
+                case DBG_PAGE_DEMOD_DATA:
+                case DBG_PAGE_DEMOD_CFO_PH:
+                    XCVR_MISC->PACKET_RAM_CTRL =  temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page);
+                    while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2)))
+                    {
+                        /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */
+                    }
+                    /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */
+                    output_ptr = result_buffer;
+#if !RADIO_IS_GEN_2P1
+                    pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]);
+#else
+                    pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]);
+#endif /* !RADIO_IS_GEN_2P1 */
+                    /* This is for non I/Q */
+                    for (i = 0; i < buffer_sz_bytes; i++)
+                    {
+                        *output_ptr = *pkt_ram_ptr0;
+                        pkt_ram_ptr0++;
+                        output_ptr++;
+                    }
+                    break;
+                case DBG_PAGE_IDLE:
+                default:
+                    status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */
+                    break;
+            }
+        }
+    }
+
+    XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */
+
+    /* Process the samples and copy to output pointer */
+
+    XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */
+    XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */
+
+    return status;
+}
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.h
new file mode 100644
index 0000000000000..4fc56ba4b4fb0
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _DBG_RAM_CAPTURE_H_
+/* clang-format off */
+#define _DBG_RAM_CAPTURE_H_
+/* clang-format on */
+
+#include <stdint.h>
+
+/*!
+ * @addtogroup xcvr
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Page definitions */
+#define DBG_PAGE_IDLE           (0x00)
+#define DBG_PAGE_RXDIGIQ        (0x01)
+#define DBG_PAGE_RAWADCIQ       (0x04)
+#define DBG_PAGE_DCESTIQ        (0x07)
+#define DBG_PAGE_RXINPH         (0x0A)
+#define DBG_PAGE_DEMOD_HARD     (0x0B)
+#define DBG_PAGE_DEMOD_SOFT     (0x0C)
+#define DBG_PAGE_DEMOD_DATA     (0x0D)
+#define DBG_PAGE_DEMOD_CFO_PH   (0x0E)
+
+typedef enum _dbgRamStatus
+{
+    DBG_RAM_SUCCESS = 0,
+    DBG_RAM_FAIL_SAMPLE_NUM_LIMIT = 1,
+    DBG_RAM_FAIL_PAGE_ERROR = 2,
+    DBG_RAM_FAIL_NULL_POINTER = 3,
+    DBG_RAM_INVALID_TRIG_SETTING = 4,
+    DBG_RAM_FAIL_NOT_ENOUGH_SAMPLES = 5,
+    DBG_RAM_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling */
+} dbgRamStatus_t;
+
+#if RADIO_IS_GEN_3P0
+typedef enum _dbgRamStartTriggerType
+{
+    NO_START_TRIG = 0,
+    START_ON_FSK_PREAMBLE_FOUND = 1,
+    START_ON_FSK_AA_MATCH = 2,
+    START_ON_ZBDEMOD_PREAMBLE_FOUND = 3,
+    START_ON_ZBDEMOD_SFD_MATCH = 4,
+    START_ON_AGC_DCOC_GAIN_CHG = 5,
+    START_ON_TSM_RX_DIG_EN = 6,
+    START_ON_TSM_SPARE2_EN = 7,
+    INVALID_START_TRIG = 8
+} dbgRamStartTriggerType;
+
+typedef enum _dbgRamStopTriggerType
+{
+    NO_STOP_TRIG = 0,
+    STOP_ON_FSK_PREAMBLE_FOUND = 1,
+    STOP_ON_FSK_AA_MATCH = 2,
+    STOP_ON_ZBDEMOD_PREAMBLE_FOUND = 3,
+    STOP_ON_ZBDEMOD_SFD_MATCH = 4,
+    STOP_ON_AGC_DCOC_GAIN_CHG = 5,
+    STOP_ON_TSM_RX_DIG_EN = 6,
+    STOP_ON_TSM_SPARE3_EN = 7,
+    STOP_ON_TSM_PLL_UNLOCK = 8,
+    STOP_ON_BLE_CRC_ERROR_INC = 9,
+    STOP_ON_CRC_FAIL_ZGBE_GENFSK = 10,
+    STOP_ON_GENFSK_HEADER_FAIL = 11,
+    INVALID_STOP_TRIG = 12
+} dbgRamStopTriggerType;
+#endif /* RADIO_IS_GEN_3P0 */
+
+/*! *********************************************************************************
+ * \brief  This function prepares for sample capture to packet RAM.
+ *
+ * \return None.
+ *
+ * \details
+ * This routine assumes that some other functions in the calling routine both set
+ * the channel and force RX warmup before calling ::dbg_ram_capture().
+ ***********************************************************************************/
+void dbg_ram_init(void);
+
+/*! *********************************************************************************
+ * \brief  This function performs any state restoration at the completion of PKT RAM capture.
+ *
+ * \details
+ * Any clocks enabled to the packet RAM capture circuitry are disabled.
+ ***********************************************************************************/
+void dbg_ram_release(void);
+
+#if RADIO_IS_GEN_3P0
+/*! *********************************************************************************
+ * \brief  This function initiates the capture of transceiver data to the transceiver packet RAM.
+ *
+ * \param[in] dbg_page - The page selector (DBG_PAGE).
+ * \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled).
+ * \param[in] dbg_stop_trigger - The trigger to stop acquisition (must be "no trigger" if a start trigger is enabled).
+ *
+ * \return Status of the request.
+ *
+ * \details
+ * This function starts the process of capturing data to the packet RAM. Depending upon the start and stop trigger
+ * settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to
+ * perform a blocking wait for completion or allow polling for completion of the capture.
+ * After any capture has completed, a separate routine must be called to postprocess the capture and copy all
+ * data out of the packet RAM into a normal RAM buffer.
+ ***********************************************************************************/
+dbgRamStatus_t dbg_ram_start_capture(uint8_t dbg_page, dbgRamStartTriggerType start_trig, dbgRamStopTriggerType stop_trig);
+
+/*! *********************************************************************************
+ * \brief  This function performs a blocking wait for completion of the capture of transceiver data to the transceiver packet RAM.
+ *
+ * \return Status of the request, DBG_RAM_SUCCESS if capture is complete.
+ *
+ * \details
+ * This function performs a wait loop for capture completion and may take an indeterminate amount of time for
+ * some capture trigger types.
+ ***********************************************************************************/
+dbgRamStatus_t dbg_ram_wait_for_complete(void); /* Blocking wait for capture completion, no matter what trigger type */
+
+/*! *********************************************************************************
+ * \brief  This function polls the state of the capture of transceiver data to the transceiver packet RAM.
+ *
+ * \return Status of the request, DBG_RAM_SUCCESS if capture is complete, DBG_RAM_CAPTURE_NOT_COMPLETE if not complete.
+ *
+ ***********************************************************************************/
+dbgRamStatus_t dbg_ram_poll_capture_status(void); /* Non-blocking completion check, just reads the current status of the capure */
+
+/*! *********************************************************************************
+ * \brief  This function processes the captured data into a usable order and copies from packet RAM to normal RAM.
+ *
+ * \param[in] dbg_page - The page selector (DBG_PAGE).
+ * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes)
+ * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples.
+ *
+ * \return None.
+ *
+ * \details
+ * Data is copied from packet RAM in bytes to ensure no access problems. Data is unpacked from packet RAM
+ * (either sequentially captured or simultaneously captured) into a linear RAM buffer in system RAM.
+ * If a start trigger is enabled then the first buffer_sz_bytes that are captured are copied out.
+ * If a stop trigger is enabled then the last buffer_sz_bytes that are captured are copied out.
+ ***********************************************************************************/
+dbgRamStatus_t dbg_ram_postproc_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); /* postprocess a capture to unpack data */
+
+#else
+/*! *********************************************************************************
+ * \brief  This function captures transceiver data to the transceiver packet RAM.
+ *
+ * \param[in] dbg_page - The page selector (DBG_PAGE).
+ * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes)
+ * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples.
+ *
+ * \return None.
+ *
+ * \details
+ * The capture to packet RAM always captures a full PKT_RAM worth of samples. The samples will be
+ * copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have
+ * been copied. Data will be copied
+ * NOTE: This routine has a slight hazard of getting stuck waiting for debug RAM to fill up when RX has
+ * not been enabled or RX ends before the RAM fills up (such as when capturing packet data ). It is
+ * intended to be used with manually triggered RX where RX data will continue as long as needed.
+ ***********************************************************************************/
+dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer);
+#endif /* RADIO_IS_GEN_3P0 */
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _DBG_RAM_CAPTURE_H_ */
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c
new file mode 100644
index 0000000000000..c0f86fc9b67d9
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c
@@ -0,0 +1,27 @@
+#include "irq.h"
+
+#include "fsl_os_abstraction.h"
+
+static unsigned int irq_mask;
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptEnable
+ * Description   : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptEnable(void)
+{
+    irq_restore(irq_mask);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptDisable
+ * Description   : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptDisable(void)
+{
+    irq_mask = irq_disable();
+}
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c
new file mode 100644
index 0000000000000..1103133c4a5a7
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c
@@ -0,0 +1,2121 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "EmbeddedTypes.h"
+#include "cpu.h"
+#include "fsl_xcvr.h"
+#include "fsl_xcvr_trim.h"
+#include "ifr_radio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define channelMapTableSize (128U)
+#define gPllDenom_c         0x02000000U /* Denominator is a constant value */
+#define ABS(x) ((x) > 0 ? (x) : -(x))
+
+#ifndef TRUE
+#define TRUE                        (true)
+#endif
+
+#ifndef FALSE
+#define FALSE                       (false)
+#endif
+#define RF_OSCILLATOR_STAYS_ON     (false) /* Control whether RF_OSC can be left on all the time. */
+#define RF_OSCILLATOR_READY        ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U)
+
+#ifndef EXTERNAL_CLOCK_GEN
+#define EXTERNAL_CLOCK_GEN   0
+#endif
+
+#define ANT_A   1
+#define ANT_B   0
+
+#ifndef XCVR_COEX_RF_ACTIVE_PIN
+#define XCVR_COEX_RF_ACTIVE_PIN ANT_B
+#endif /* XCVR_COEX_RF_ACTIVE_PIN */
+
+typedef struct xcvr_pllChannel_tag
+{
+    unsigned int integer;
+    unsigned int numerator;
+} xcvr_pllChannel_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address);
+void rf_osc_startup(void);
+void rf_osc_shutdown(void);
+extern double trunc (double);
+extern double round (double);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static panic_fptr s_PanicFunctionPtr = NULL;
+const xcvr_pllChannel_t mapTable [channelMapTableSize] =
+{
+    {0x00000025, 0x07C00000}, /* 0 */
+    {0x00000025, 0x07C80000}, /* 1 */
+    {0x00000025, 0x07D00000}, /* 2 */
+    {0x00000025, 0x07D80000}, /* 3 */
+    {0x00000025, 0x07E00000}, /* 4 */
+    {0x00000025, 0x07E80000}, /* 5 */
+    {0x00000025, 0x07F00000}, /* 6 */
+    {0x00000025, 0x07F80000}, /* 7 */
+    {0x00000025, 0x00000000}, /* 8 */
+    {0x00000025, 0x00080000}, /* 9 */
+    {0x00000025, 0x00100000}, /* 10 */
+    {0x00000025, 0x00180000}, /* 11 */
+    {0x00000025, 0x00200000}, /* 12 */
+    {0x00000025, 0x00280000}, /* 13 */
+    {0x00000025, 0x00300000}, /* 14 */
+    {0x00000025, 0x00380000}, /* 15 */
+    {0x00000025, 0x00400000}, /* 16 */
+    {0x00000025, 0x00480000}, /* 17 */
+    {0x00000025, 0x00500000}, /* 18 */
+    {0x00000025, 0x00580000}, /* 19 */
+    {0x00000025, 0x00600000}, /* 20 */
+    {0x00000025, 0x00680000}, /* 21 */
+    {0x00000025, 0x00700000}, /* 22 */
+    {0x00000025, 0x00780000}, /* 23 */
+    {0x00000025, 0x00800000}, /* 24 */
+    {0x00000025, 0x00880000}, /* 25 */
+    {0x00000025, 0x00900000}, /* 26 */
+    {0x00000025, 0x00980000}, /* 27 */
+    {0x00000025, 0x00A00000}, /* 28 */
+    {0x00000025, 0x00A80000}, /* 29 */
+    {0x00000025, 0x00B00000}, /* 30 */
+    {0x00000025, 0x00B80000}, /* 31 */
+    {0x00000025, 0x00C00000}, /* 32 */
+    {0x00000025, 0x00C80000}, /* 33 */
+    {0x00000025, 0x00D00000}, /* 34 */
+    {0x00000025, 0x00D80000}, /* 35 */
+    {0x00000025, 0x00E00000}, /* 36 */
+    {0x00000025, 0x00E80000}, /* 37 */
+    {0x00000025, 0x00F00000}, /* 38 */
+    {0x00000025, 0x00F80000}, /* 39 */
+    {0x00000025, 0x01000000}, /* 40 */
+    {0x00000026, 0x07080000}, /* 41 */
+    {0x00000026, 0x07100000}, /* 42 */
+    {0x00000026, 0x07180000}, /* 43 */
+    {0x00000026, 0x07200000}, /* 44 */
+    {0x00000026, 0x07280000}, /* 45 */
+    {0x00000026, 0x07300000}, /* 46 */
+    {0x00000026, 0x07380000}, /* 47 */
+    {0x00000026, 0x07400000}, /* 48 */
+    {0x00000026, 0x07480000}, /* 49 */
+    {0x00000026, 0x07500000}, /* 50 */
+    {0x00000026, 0x07580000}, /* 51 */
+    {0x00000026, 0x07600000}, /* 52 */
+    {0x00000026, 0x07680000}, /* 53 */
+    {0x00000026, 0x07700000}, /* 54 */
+    {0x00000026, 0x07780000}, /* 55 */
+    {0x00000026, 0x07800000}, /* 56 */
+    {0x00000026, 0x07880000}, /* 57 */
+    {0x00000026, 0x07900000}, /* 58 */
+    {0x00000026, 0x07980000}, /* 59 */
+    {0x00000026, 0x07A00000}, /* 60 */
+    {0x00000026, 0x07A80000}, /* 61 */
+    {0x00000026, 0x07B00000}, /* 62 */
+    {0x00000026, 0x07B80000}, /* 63 */
+    {0x00000026, 0x07C00000}, /* 64 */
+    {0x00000026, 0x07C80000}, /* 65 */
+    {0x00000026, 0x07D00000}, /* 66 */
+    {0x00000026, 0x07D80000}, /* 67 */
+    {0x00000026, 0x07E00000}, /* 68 */
+    {0x00000026, 0x07E80000}, /* 69 */
+    {0x00000026, 0x07F00000}, /* 70 */
+    {0x00000026, 0x07F80000}, /* 71 */
+    {0x00000026, 0x00000000}, /* 72 */
+    {0x00000026, 0x00080000}, /* 73 */
+    {0x00000026, 0x00100000}, /* 74 */
+    {0x00000026, 0x00180000}, /* 75 */
+    {0x00000026, 0x00200000}, /* 76 */
+    {0x00000026, 0x00280000}, /* 77 */
+    {0x00000026, 0x00300000}, /* 78 */
+    {0x00000026, 0x00380000}, /* 79 */
+    {0x00000026, 0x00400000}, /* 80 */
+    {0x00000026, 0x00480000}, /* 81 */
+    {0x00000026, 0x00500000}, /* 82 */
+    {0x00000026, 0x00580000}, /* 83 */
+    {0x00000026, 0x00600000}, /* 84 */
+    {0x00000026, 0x00680000}, /* 85 */
+    {0x00000026, 0x00700000}, /* 86 */
+    {0x00000026, 0x00780000}, /* 87 */
+    {0x00000026, 0x00800000}, /* 88 */
+    {0x00000026, 0x00880000}, /* 89 */
+    {0x00000026, 0x00900000}, /* 90 */
+    {0x00000026, 0x00980000}, /* 91 */
+    {0x00000026, 0x00A00000}, /* 92 */
+    {0x00000026, 0x00A80000}, /* 93 */
+    {0x00000026, 0x00B00000}, /* 94 */
+    {0x00000026, 0x00B80000}, /* 95 */
+    {0x00000026, 0x00C00000}, /* 96 */
+    {0x00000026, 0x00C80000}, /* 97 */
+    {0x00000026, 0x00D00000}, /* 98 */
+    {0x00000026, 0x00D80000}, /* 99 */
+    {0x00000026, 0x00E00000}, /* 100 */
+    {0x00000026, 0x00E80000}, /* 101 */
+    {0x00000026, 0x00F00000}, /* 102 */
+    {0x00000026, 0x00F80000}, /* 103 */
+    {0x00000026, 0x01000000}, /* 104 */
+    {0x00000027, 0x07080000}, /* 105 */
+    {0x00000027, 0x07100000}, /* 106 */
+    {0x00000027, 0x07180000}, /* 107 */
+    {0x00000027, 0x07200000}, /* 108 */
+    {0x00000027, 0x07280000}, /* 109 */
+    {0x00000027, 0x07300000}, /* 110 */
+    {0x00000027, 0x07380000}, /* 111 */
+    {0x00000027, 0x07400000}, /* 112 */
+    {0x00000027, 0x07480000}, /* 113 */
+    {0x00000027, 0x07500000}, /* 114 */
+    {0x00000027, 0x07580000}, /* 115 */
+    {0x00000027, 0x07600000}, /* 116 */
+    {0x00000027, 0x07680000}, /* 117 */
+    {0x00000027, 0x07700000}, /* 118 */
+    {0x00000027, 0x07780000}, /* 119 */
+    {0x00000027, 0x07800000}, /* 120 */
+    {0x00000027, 0x07880000}, /* 121 */
+    {0x00000027, 0x07900000}, /* 122 */
+    {0x00000027, 0x07980000}, /* 123 */
+    {0x00000027, 0x07A00000}, /* 124 */
+    {0x00000027, 0x07A80000}, /* 125 */
+    {0x00000027, 0x07B00000}, /* 126 */
+    {0x00000027, 0x07B80000}  /* 127 */
+};
+
+/* Registers for timing of TX & RX */
+#if RADIO_IS_GEN_3P0
+uint16_t tx_rx_on_delay = TX_RX_ON_DELinit;
+uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init;
+#else
+#if RF_OSC_26MHZ == 1
+uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ;
+#else
+uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL;
+#endif /* RF_OSC_26MHZ == 1 */
+uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL;
+#endif /* RADIO_IS_GEN_3P0 */
+
+/* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */
+#if RADIO_IS_GEN_3P0
+const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] =
+{
+    (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
+    (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
+    (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
+    &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config,
+    &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config,
+    (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
+    (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
+    &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config,
+    &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config,
+    &xcvr_MSK_2mbps_config,
+};
+#endif /* RADIO_IS_GEN_3P0 */
+
+const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] =
+{
+    &xcvr_BLE_1mbps_config,
+#if RADIO_IS_GEN_2P1
+    NULL,
+    NULL,
+#else
+    &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */
+    &xcvr_ANT_1mbps_config,
+#endif /* RADIO_IS_GEN_2P1 */
+    &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config,
+    &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config,
+    &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config,
+    &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config,
+    &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config,
+    &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config,
+    &xcvr_MSK_1mbps_config,
+};
+
+const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] =
+{
+    &xcvr_BLE_1mbps_config, /* Invalid option */
+#if RADIO_IS_GEN_2P1
+    NULL,
+    NULL,
+#else
+    &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */
+    &xcvr_ANT_1mbps_config, /* Invalid option */
+#endif /* RADIO_IS_GEN_2P1 */
+    &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config,
+    &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config,
+    &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config,
+    &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config,
+    &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config,
+    &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config,
+    &xcvr_MSK_500kbps_config,
+};
+const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] =
+{
+    &xcvr_BLE_1mbps_config, /* Invalid option */
+#if RADIO_IS_GEN_2P1
+    NULL,
+    NULL,
+#else
+    &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */
+    &xcvr_ANT_1mbps_config, /* Invalid option */
+#endif /* RADIO_IS_GEN_2P1 */
+    &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config,
+    &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config,
+    &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config,
+    &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config,
+    &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config,
+    &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config,
+    &xcvr_MSK_250kbps_config,
+};
+
+static xcvr_currConfig_t current_xcvr_config;
+
+void rf_osc_startup(void)
+{
+    if (!RF_OSCILLATOR_READY)
+    {
+        RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK;
+    }
+    while (!RF_OSCILLATOR_READY)
+    {
+        /* Wait for RF_OSC_READY to be asserted before continuing */
+    }
+}
+
+void rf_osc_shutdown(void)
+{
+    if (!RF_OSCILLATOR_STAYS_ON)
+    {
+        RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK;
+    }
+}
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate)
+{
+    const xcvr_mode_datarate_config_t * mode_datarate_config;
+    const xcvr_datarate_config_t * datarate_config ;
+    const xcvr_mode_config_t * radio_mode_cfg;
+    const xcvr_common_config_t * radio_common_config;
+
+    xcvrStatus_t status;
+
+    IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] =
+    {
+        {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/
+        {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/
+    };
+    const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T);
+
+#ifndef SIMULATION
+
+#if (EXTERNAL_CLOCK_GEN)
+    RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */
+#endif /* EXTERNAL_CLOCK_GEN */
+
+#if RADIO_IS_GEN_2P0
+    RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */
+    RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */
+#endif /* RADIO_IS_GEN_2P0 */
+
+    /* Check that this is the proper radio version */
+    {
+        uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT);
+
+        if (
+#if RADIO_IS_GEN_3P0
+            (radio_id != 0x5) /* KW3 Gen3 */
+#elif RADIO_IS_GEN_2P1
+            (radio_id != 0x5) /* KW35 Gen2.1 */
+#else
+            (radio_id != 0x3) &&  /* KW41/31/21 v1 */
+            (radio_id != 0xB) /* KW41/31/21 v1.1 */
+#endif /* RADIO_IS_GEN_3P0 */
+            )
+        {
+            XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init);
+        }
+    }
+
+#if RADIO_IS_GEN_3P0
+    /* Assert Radio Run Request and wait for ack from SPM. */
+    RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK;
+    while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0)
+    {
+    }
+    RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK;
+    rf_osc_startup(); /* Start RF_OSC to allow radio registers access */
+#else
+    SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK;
+
+    /* Load IFR trim values */
+    handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES);
+#endif /* RADIO_IS_GEN_3P0 */
+
+#endif /* ifndef SIMULATION */
+
+    /* Perform the desired XCVR initialization and configuration */
+    status = XCVR_GetDefaultConfig(radio_mode, data_rate,
+                                   (const xcvr_common_config_t **)&radio_common_config,
+                                   (const xcvr_mode_config_t **)&radio_mode_cfg,
+                                   (const xcvr_mode_datarate_config_t **)&mode_datarate_config,
+                                   (const xcvr_datarate_config_t **)&datarate_config);
+
+    if (status == gXcvrSuccess_c)
+    {
+        status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config,
+                                (const xcvr_mode_config_t *)radio_mode_cfg,
+                                (const xcvr_mode_datarate_config_t *)mode_datarate_config,
+                                (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT);
+        current_xcvr_config.radio_mode = radio_mode;
+        current_xcvr_config.data_rate = data_rate;
+    }
+
+    return status;
+}
+
+void XCVR_Deinit(void)
+{
+#if RADIO_IS_GEN_3P0
+    rf_osc_shutdown();
+    RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */
+    RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */
+#else
+
+#endif /* RADIO_IS_GEN_3P0 */
+}
+
+xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode,
+                                   data_rate_t data_rate,
+                                   const xcvr_common_config_t ** com_config,
+                                   const xcvr_mode_config_t ** mode_config,
+                                   const xcvr_mode_datarate_config_t ** mode_datarate_config,
+                                   const xcvr_datarate_config_t ** datarate_config)
+{
+    xcvrStatus_t status = gXcvrSuccess_c;
+    /* Common configuration pointer */
+    *com_config = (const xcvr_common_config_t *)&xcvr_common_config;
+
+    /* Mode dependent configuration pointer */
+    switch (radio_mode)
+    {
+#if !RADIO_IS_GEN_2P1
+        case ZIGBEE_MODE:
+            *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */
+            break;
+        case ANT_MODE:
+            *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */
+            break;
+#endif /* !RADIO_IS_GEN_2P1 */
+        case BLE_MODE:
+            *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */
+            break;
+        case GFSK_BT_0p5_h_0p5:
+            *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */
+            break;
+        case GFSK_BT_0p5_h_0p32:
+            *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */
+            break;
+        case GFSK_BT_0p5_h_0p7:
+            *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */
+            break;
+        case GFSK_BT_0p5_h_1p0:
+            *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */
+            break;
+        case GFSK_BT_0p3_h_0p5:
+            *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */
+            break;
+        case GFSK_BT_0p7_h_0p5:
+            *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */
+            break;
+        case MSK:
+            *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */
+            break;
+        default:
+            status = gXcvrInvalidParameters_c;
+            break;
+    }
+
+    /* Data rate dependent and modeXdatarate dependent configuration pointers */
+    if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */
+    {
+        switch (data_rate)
+        {
+#if RADIO_IS_GEN_3P0
+            case DR_2MBPS:
+                if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE))
+                {
+                    status = gXcvrInvalidParameters_c;
+                }
+                else
+                {
+                    *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */
+                    *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode];
+                }
+                break;
+#endif /* RADIO_IS_GEN_3P0 */
+            case DR_1MBPS:
+                *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */
+                *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode];
+                break;
+            case DR_500KBPS:
+                if (radio_mode == ZIGBEE_MODE)
+                {
+                    /* See fsl_xcvr_zgbe_config.c for settings */
+#if !RADIO_IS_GEN_2P1
+                    *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */
+#endif /* !RADIO_IS_GEN_2P1 */
+                }
+                else
+                {
+                    *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */
+                }
+                *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode];
+                break;
+            case DR_250KBPS:
+                *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */
+                *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode];
+                break;
+            default:
+                status = gXcvrInvalidParameters_c;
+                break;
+        }
+    }
+
+    return status;
+}
+
+xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config,
+                            const xcvr_mode_config_t *mode_config,
+                            const xcvr_mode_datarate_config_t *mode_datarate_config,
+                            const xcvr_datarate_config_t *datarate_config,
+                            int16_t tempDegC,
+                            XCVR_INIT_MODE_CHG_T first_init)
+{
+    xcvrStatus_t config_status = gXcvrSuccess_c;
+    uint32_t temp;
+
+    /* Turn on the module clocks before doing anything */
+#if RADIO_IS_GEN_3P0
+    RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */
+#else
+    SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits;
+#endif /* RADIO_IS_GEN_3P0 */
+
+    /*******************************************************************************/
+    /* XCVR_ANA configs */
+    /*******************************************************************************/
+
+    /* Configure PLL Loop Filter */
+    if (first_init)
+    {
+        XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask;
+        XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init;
+    }
+
+    /* Configure VCO KVM */
+    XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask;
+    XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init;
+
+    /* Configure analog filter bandwidth */
+    XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask;
+    XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init;
+    XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask;
+    XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init;
+
+#if RADIO_IS_GEN_2P0
+    if (first_init)
+    {
+        temp = XCVR_ANA->TX_DAC_PA;
+        temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK;
+        temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4);
+        XCVR_ANA->TX_DAC_PA = temp;
+
+        temp = XCVR_ANA->BB_LDO_2;
+        temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK;
+        temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0);
+        XCVR_ANA->BB_LDO_2 = temp;
+
+        temp = XCVR_ANA->RX_LNA;
+        temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK;
+        temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1);
+        XCVR_ANA->RX_LNA = temp;
+
+        temp = XCVR_ANA->BB_LDO_1;
+        temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK;
+        temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1);
+        XCVR_ANA->BB_LDO_1 = temp;
+    }
+#endif /* RADIO_IS_GEN_2P0 */
+
+    /*******************************************************************************/
+    /* XCVR_MISC configs */
+    /*******************************************************************************/
+    temp = XCVR_MISC->XCVR_CTRL;
+    temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK);
+    temp |= mode_config->xcvr_ctrl.init;
+
+#if RF_OSC_26MHZ == 1
+    {
+        temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1);
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+
+    XCVR_MISC->XCVR_CTRL = temp;
+
+#if RADIO_IS_GEN_2P1
+    XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK;
+#endif /* RADIO_IS_GEN_2P1 */
+
+    /*******************************************************************************/
+    /* XCVR_PHY configs */
+    /*******************************************************************************/
+#if RADIO_IS_GEN_3P0
+    XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0;
+    XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1;
+    XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg;
+    XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate;
+    XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl;
+#else
+    XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init;
+    XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init;
+    XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init;
+    XCVR_PHY->CFG1 = mode_config->phy_cfg1_init;
+    XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init;
+    XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */
+#endif /* RADIO_IS_GEN_3P0 */
+
+    /*******************************************************************************/
+    /* XCVR_PLL_DIG configs */
+    /*******************************************************************************/
+    if (first_init)
+    {
+        XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump;
+        XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl;
+        XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map;
+        XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect;
+        XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl;
+#if !RADIO_IS_GEN_2P1
+        XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl;
+#endif /* !RADIO_IS_GEN_2P1 */
+        XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res;
+        XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl;
+        XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1;
+        XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match;
+        XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl;
+    }
+
+    /*******************************************************************************/
+    /* XCVR_RX_DIG configs */
+    /*******************************************************************************/
+
+    /* Configure RF Aux PLL for proper operation based on external clock frequency */
+    if (first_init)
+    {
+        temp = XCVR_ANA->RX_AUXPLL;
+        temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK;
+#if RF_OSC_26MHZ == 1
+        {
+            temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4);
+        }
+#else
+        {
+            temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7);
+        }
+#endif /* RF_OSC_26MHZ == 1 */
+        XCVR_ANA->RX_AUXPLL = temp;
+    }
+
+    /* Configure RX_DIG_CTRL */
+#if RF_OSC_26MHZ == 1
+    {
+        temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */
+               mode_config->rx_dig_ctrl_init_26mhz | /* Mode  specific portion of RX_DIG_CTRL init */
+               datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */
+               XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */
+    }
+#else
+    {
+        temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */
+               mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */
+               datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */
+               0; /* Always disable the sample rate converter for 32MHz */
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+
+    temp |= com_config->rx_dig_ctrl_init;  /* Common portion of RX_DIG_CTRL init */
+    XCVR_RX_DIG->RX_DIG_CTRL = temp;
+
+    /* DCOC_CAL_IIR */
+#if RF_OSC_26MHZ == 1
+    {
+        XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz;
+    }
+#else
+    {
+        XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz;
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+
+    /* DC_RESID_CTRL */
+#if RF_OSC_26MHZ == 1
+    {
+        XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz;
+    }
+#else
+    {
+        XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz;
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+
+    /* DCOC_CTRL_0  & _1 */
+#if RF_OSC_26MHZ == 1
+    {
+        XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */
+        XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */
+#if RADIO_IS_GEN_3P0
+        XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz;
+#endif /* RADIO_IS_GEN_3P0 */
+
+    }
+#else
+    {
+        XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */
+        XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */
+#if RADIO_IS_GEN_3P0
+        XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz;
+#endif /* RADIO_IS_GEN_3P0 */
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+    if (first_init)
+    {
+        /* DCOC_CAL_GAIN */
+        XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init;
+
+        /* DCOC_CAL_RCP */
+        XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init;
+        XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0;
+        XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4;
+        XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8;
+        XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0;
+        XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8;
+
+        /* LNA_GAIN_LIN_VAL */
+        XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init;
+        XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init;
+        XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init;
+        XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init;
+
+        /* BBA_RES_TUNE_LIN_VAL */
+        XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init;
+        XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init;
+        XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init;
+
+        /* BBA_STEP */
+        XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init;
+
+        /* DCOC_TZA_STEP */
+        XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init;
+        XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init;
+
+#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1)
+        /* DCOC_CAL_FAIL and DCOC_CAL_PASS */
+        XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init;
+        XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init;
+#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */
+    }
+
+    /* AGC_CTRL_0 .. _3 */
+    XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init;
+
+#if RF_OSC_26MHZ == 1
+    {
+        XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */
+        XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz;
+    }
+#else
+    {
+        XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */
+        XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz;
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+
+    if (first_init)
+    {
+        XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init;
+
+        /* AGC_GAIN_TBL_** */
+        XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init;
+        XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init;
+        XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init;
+        XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init;
+        XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init;
+        XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init;
+        XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init;
+
+        /* RSSI_CTRL_0 */
+        XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init;
+
+#if RADIO_IS_GEN_3P0
+        XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init;
+#endif /* RADIO_IS_GEN_3P0 */
+
+        /* CCA_ED_LQI_0 and _1 */
+        XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init;
+        XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init;
+    }
+
+    /* Channel filter coefficients */
+#if RF_OSC_26MHZ == 1
+    {
+        XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0;
+        XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1;
+        XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2;
+        XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3;
+        XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4;
+        XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5;
+        XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6;
+        XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7;
+        XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8;
+        XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9;
+        XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10;
+        XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11;
+    }
+#else
+    {
+        XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0;
+        XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1;
+        XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2;
+        XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3;
+        XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4;
+        XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5;
+        XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6;
+        XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7;
+        XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8;
+        XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9;
+        XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10;
+        XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11;
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+
+    XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0;
+    XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1;
+
+    /*******************************************************************************/
+    /* XCVR_TSM configs */
+    /*******************************************************************************/
+    XCVR_TSM->CTRL = com_config->tsm_ctrl;
+
+#if RADIO_IS_GEN_2P0
+    if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE))
+    {
+        XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK;
+    }
+#endif /* RADIO_IS_GEN_2P0 */
+
+    if (first_init)
+    {
+#if !RADIO_IS_GEN_2P1
+        XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */
+#endif /* !RADIO_IS_GEN_2P1 */
+
+        XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init;
+        /* TSM registers and timings - dependent upon clock frequency */
+#if RF_OSC_26MHZ == 1
+        {
+            XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz;
+            XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz;
+            XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz;
+            XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz;
+            XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz;
+            XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz;
+            XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz;
+            XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz;
+            XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz;
+            XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz;
+            XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz;
+            XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz;
+            XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz;
+            XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz;
+            XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz;
+            XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz;
+            XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz;
+            XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz;
+            XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz;
+            XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz;
+            XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz;
+            XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz;
+        }
+#else
+        {
+            XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz;
+            XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz;
+            XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz;
+            XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz;
+            XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz;
+            XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz;
+            XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz;
+            XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz;
+            XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz;
+            XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz;
+            XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz;
+            XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz;
+            XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz;
+            XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz;
+            XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz;
+            XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz;
+            XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz;
+            XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz;
+            XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz;
+            XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz;
+            XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz;
+            XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz;
+        }
+#endif /* RF_OSC_26MHZ == 1 */
+
+        /* TSM timings independent of clock frequency */
+        XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init;
+        XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init;
+        XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init;
+        XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init;
+        XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init;
+        XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init;
+        XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init;
+        XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init;
+        XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init;
+        XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init;
+        XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init;
+        XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init;
+        XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init;
+        XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init;
+        XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init;
+        XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init;
+        XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init;
+        XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init;
+        XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init;
+        XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init;
+        XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init;
+        XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init;
+        XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init;
+        XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init;
+        XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init;
+        XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init;
+        XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init;
+        XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init;
+        XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init;
+        XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init;
+        XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init;
+
+#if RF_OSC_26MHZ == 1
+        {
+            XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) |
+                                   XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) |
+                                   XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) |
+                                   XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ);
+        }
+#else
+        {
+            XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) |
+                                   XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) |
+                                   XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) |
+                                   XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD);
+        }
+#endif /* RF_OSC_26MHZ == 1 */
+
+        XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init;
+        XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init;
+
+#if RADIO_IS_GEN_3P0
+        XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init;
+        XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init;
+
+        /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */
+#if (PA_RAMP_TIME == 4)
+        XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */
+        XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */
+        XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */
+        XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */
+        XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */
+        XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */
+        XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */
+        XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */
+        XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */
+        XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */
+        XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */
+        XCVR_TSM->TIMING20 += B1(2); /*  (sy_pd_en) */
+        XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */
+        XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */
+        XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */
+        XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */
+        XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */
+        XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */
+        XCVR_TSM->TIMING58 += B1(2)  /* (tx_hpm_dac_en) */
+        temp = XCVR_TSM->TIMING14;
+        temp &= 0xFFFF0000;
+        temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */
+        XCVR_TSM->TIMING14 = temp;
+#endif /* (PA_RAMP_TIME == 4) */
+#endif /* RADIO_IS_GEN_3P0 */
+    }
+
+#if RADIO_IS_GEN_3P0
+    if (mode_config->radio_mode == ZIGBEE_MODE)
+    {
+        temp = XCVR_TSM->TIMING35;
+        temp &= ~(B0(0xFF));
+        if (DATA_PADDING_EN == 1)
+        {
+            temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */
+        }
+        else
+        {
+            temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */
+        }
+        XCVR_TSM->TIMING35 = temp;
+    }
+#else
+
+    if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS)))
+    {
+        /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */
+        XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */
+    }
+    else
+    {
+        XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */
+    }
+#endif /* RADIO_IS_GEN_3P0 */
+
+    /*******************************************************************************/
+    /* XCVR_TX_DIG configs */
+    /*******************************************************************************/
+#if RF_OSC_26MHZ == 1
+    {
+        XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */
+        XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz;
+        XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz;
+    }
+#else
+    {
+        XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */
+        XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz;
+        XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz;
+    }
+#endif /* RF_OSC_26MHZ == 1 */
+
+    if (first_init)
+    {
+        XCVR_TX_DIG->CTRL = com_config->tx_ctrl;
+        XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding;
+        XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern;
+
+#if !RADIO_IS_GEN_2P1
+        XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1;
+        XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2;
+#endif /* !RADIO_IS_GEN_2P1 */
+    }
+
+    XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl;
+
+#ifndef SIMULATION
+#if (TRIM_BBA_DCOC_DAC_AT_INIT)
+    if (first_init)
+    {
+        uint32_t end_of_rx_wu = 0;
+        XCVR_ForceRxWu();
+        /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */
+        temp = XCVR_TSM->END_OF_SEQ;
+        end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
+        while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
+
+//        if (!rx_bba_dcoc_dac_trim_shortIQ())
+        if (!rx_bba_dcoc_dac_trim_DCest())
+        {
+            config_status = gXcvrTrimFailure_c;
+        }
+
+        XCVR_ForceRxWd();
+        DCOC_DAC_INIT_Cal(1);
+    }
+#endif /* TRIM_BBA_DCOC_DAC_AT_INIT */
+#endif /* ifndef SIMULATION */
+    return config_status;
+}
+
+void XCVR_Reset(void)
+{
+#if RADIO_IS_GEN_3P0
+#else
+    RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */
+    RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */
+    RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */
+#endif /* RADIO_IS_GEN_3P0 */
+}
+
+xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */
+{
+    xcvrStatus_t status;
+    const xcvr_mode_datarate_config_t * mode_datarate_config;
+    const xcvr_datarate_config_t * datarate_config ;
+    const xcvr_mode_config_t * radio_mode_cfg;
+    const xcvr_common_config_t * radio_common_config;
+
+    status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config );
+
+    if (status == gXcvrSuccess_c)
+    {
+        status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config,
+                                (const xcvr_mode_config_t *)radio_mode_cfg,
+                                (const xcvr_mode_datarate_config_t *)mode_datarate_config,
+                                (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE);
+        current_xcvr_config.radio_mode = new_radio_mode;
+        current_xcvr_config.data_rate = new_data_rate;
+    }
+
+    return status;
+}
+
+void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable )
+{
+    if (IIRnbEnable)
+    {
+        XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK;
+    }
+    else
+    {
+        XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK;
+    }
+}
+
+xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc )
+{
+    double integer_used_in_Hz,
+           integer_used_in_LSB,
+           numerator_fraction,
+           numerator_in_Hz,
+           numerator_in_LSB,
+           numerator_unrounded,
+           real_int_and_fraction,
+           real_fraction,
+           requested_freq_in_LSB,
+           sdm_lsb;
+    uint32_t temp;
+    static uint32_t integer_truncated,
+                    integer_to_use;
+    static int32_t numerator_rounded;
+
+    /* Configure for Coarse Tune */
+    uint32_t coarse_tune_target = freq / 1000000;
+
+    temp = XCVR_PLL_DIG->CTUNE_CTRL;
+    temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK;
+    temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target);
+    XCVR_PLL_DIG->CTUNE_CTRL = temp;
+
+    /* Calculate the Low Port values */
+    sdm_lsb = refOsc / 131072.0;
+
+    real_int_and_fraction = freq / (refOsc * 2.0);
+
+    integer_truncated = (uint32_t) trunc(real_int_and_fraction);
+
+    real_fraction = real_int_and_fraction - integer_truncated;
+
+    if (real_fraction > 0.5)
+    {
+        integer_to_use = integer_truncated + 1;
+    }
+    else
+    {
+        integer_to_use = integer_truncated;
+    }
+
+    numerator_fraction = real_int_and_fraction - integer_to_use;
+
+    integer_used_in_Hz  = integer_to_use * refOsc * 2;
+    integer_used_in_LSB = integer_used_in_Hz / sdm_lsb;
+
+    numerator_in_Hz  = numerator_fraction * refOsc * 2;
+    numerator_in_LSB = numerator_in_Hz    / sdm_lsb;
+
+    requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB;
+
+    numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256;
+
+    numerator_rounded = (int32_t)round(numerator_unrounded);
+
+    /* Write the Low Port Integer and Numerator */
+    temp = XCVR_PLL_DIG->LPM_SDM_CTRL1;
+    temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK;
+    temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) |
+             XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK);
+    XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp;
+
+    XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded;
+
+    return gXcvrSuccess_c;
+}
+
+void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */
+{
+    s_PanicFunctionPtr = fptr;
+}
+
+void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address)
+{
+    if ( s_PanicFunctionPtr != NULL)
+    {
+        s_PanicFunctionPtr(panic_id, panic_address, 0, 0);
+    }
+    else
+    {
+        uint8_t dummy;
+
+        while(1)
+        {
+            dummy = dummy;
+        }
+    }
+}
+
+healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */
+{
+    return (healthStatus_t)NO_ERRORS;
+}
+
+void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control)
+{
+
+}
+
+/* Helper function to map radio mode to LL usage */
+link_layer_t map_mode_to_ll(radio_mode_t mode)
+{
+    link_layer_t llret;
+    switch (mode)
+    {
+        case BLE_MODE:
+            llret = BLE_LL;
+            break;
+        case ZIGBEE_MODE:
+            llret = ZIGBEE_LL;
+            break;
+        case ANT_MODE:
+            llret = ANT_LL;
+            break;
+        case GFSK_BT_0p5_h_0p5:
+        case GFSK_BT_0p5_h_0p32:
+        case GFSK_BT_0p5_h_0p7:
+        case GFSK_BT_0p5_h_1p0:
+        case GFSK_BT_0p3_h_0p5:
+        case GFSK_BT_0p7_h_0p5:
+        case MSK:
+            llret = GENFSK_LL;
+            break;
+        default:
+            llret = UNASSIGNED_LL;
+            break;
+    }
+    return llret;
+}
+
+#if RADIO_IS_GEN_3P0
+void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address)
+{
+    XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address;
+}
+
+uint32_t XCVR_GetBSM_NTW_Address(void)
+{
+    return XCVR_PHY->NTW_ADR_BSM;
+}
+#endif /* RADIO_IS_GEN_3P0 */
+
+/* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */
+xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping)
+{
+    link_layer_t int0 = map_mode_to_ll(irq0_mapping);
+    link_layer_t int1 = map_mode_to_ll(irq1_mapping);
+    xcvrStatus_t statusret;
+    /* Make sure the two LL's requested aren't the same */
+    if (int0 == int1)
+    {
+        statusret = gXcvrInvalidParameters_c;
+    }
+    else
+    {
+        uint32_t temp;
+        temp = XCVR_MISC->XCVR_CTRL;
+        temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK);
+        temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1));
+        XCVR_MISC->XCVR_CTRL = temp;
+        statusret = gXcvrSuccess_c;
+    }
+    return statusret;
+}
+
+/* Get current state of IRQ mapping for either  radio INT0 or INT1 */
+link_layer_t XCVR_GetIRQMapping(uint8_t int_num)
+{
+    if (int_num == 0)
+    {
+        return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT);
+    }
+    else
+    {
+        return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT);
+    }
+}
+
+/* Get current state of radio mode and data rate */
+xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config)
+{
+    xcvrStatus_t status = gXcvrInvalidParameters_c;
+    if (curr_config != NULL)
+    {
+        curr_config->radio_mode = current_xcvr_config.radio_mode;
+        curr_config->data_rate = current_xcvr_config.data_rate;
+        status = gXcvrSuccess_c;
+    }
+    return status;
+}
+
+/* Customer level trim functions */
+xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim)
+{
+    xcvrStatus_t status = gXcvrInvalidParameters_c;
+
+    if ((xtalTrim & 0x80) == 0)
+    {
+        uint32_t temp;
+        temp = RSIM->ANA_TRIM;
+        temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK;
+        RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim);
+        status = gXcvrSuccess_c;
+    }
+    return status;
+}
+
+uint8_t  XCVR_GetXtalTrim(void)
+{
+    uint8_t temp_xtal;
+    temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT);
+    return temp_xtal;
+}
+
+/* RSSI adjustment */
+xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj)
+{
+    XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK;
+    XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj);
+    return gXcvrSuccess_c;
+}
+
+int8_t  XCVR_GetRssiAdjustment(void)
+{
+    int8_t adj;
+    adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT;
+    return adj;
+}
+
+/* Radio debug functions */
+xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel)
+{
+    uint32_t temp;
+
+    if (channel == 0xFF)
+    {
+        /* Clear all of the overrides and restore to LL channel control */
+        temp = XCVR_PLL_DIG->CHAN_MAP;
+        temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
+#if !RADIO_IS_GEN_2P1
+                 | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
+#endif /* !RADIO_IS_GEN_2P1 */
+#if RADIO_IS_GEN_3P0
+                 | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK
+#endif /* RADIO_IS_GEN_3P0 */
+                 );
+
+      XCVR_PLL_DIG->CHAN_MAP = temp;
+
+      /* Stop using the manual frequency setting */
+      XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK;
+
+      return gXcvrSuccess_c;
+    }
+
+    if (channel >= 128)
+    {
+        return gXcvrInvalidParameters_c;
+    }
+
+    if (useMappedChannel)
+    {
+        temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */
+
+        switch (temp)
+        {
+#if !RADIO_IS_GEN_2P1
+            case 0x3: /* ANT protocol */
+                ANT->CHANNEL_NUM = channel;
+                break;
+#endif /* !RADIO_IS_GEN_2P1 */
+            case 0x8: /* GENFSK protocol */
+            case 0x9: /* MSK protocol */
+                GENFSK->CHANNEL_NUM = channel;
+                break;
+            default: /* All other protocols */
+                temp = XCVR_PLL_DIG->CHAN_MAP;
+                temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK
+#if RADIO_IS_GEN_3P0
+                         | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK
+#endif /* RADIO_IS_GEN_3P0 */
+                         );
+                temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
+#if !RADIO_IS_GEN_2P1
+                        | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
+#endif /* !RADIO_IS_GEN_2P1 */
+                        );
+                XCVR_PLL_DIG->CHAN_MAP = temp;
+                break;
+        }
+    }
+    else
+    {
+        XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
+#if !RADIO_IS_GEN_2P1
+                                  | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
+#endif /* !RADIO_IS_GEN_2P1 */
+                                  );
+
+        XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c);
+        XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator);
+
+        temp = XCVR_PLL_DIG->LPM_SDM_CTRL1;
+        temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK;
+        temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer);
+        XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp;
+
+        /* Stop using the LL channel map and use the manual frequency setting */
+        XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK;
+    }
+
+    return gXcvrSuccess_c;
+}
+
+uint32_t XCVR_GetFreq ( void )
+{
+    uint32_t pll_int;
+    uint32_t pll_num_unsigned;
+    int32_t pll_num;
+    uint32_t pll_denom;
+    float freq_float;
+
+    if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */
+    {
+        pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >>
+                   XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT;
+
+        pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2;
+        pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3;
+    }
+    else
+    {
+        /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */
+        pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >>
+                   XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT;
+
+        pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1;
+        pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2;
+    }
+
+    uint32_t freq = 0;
+
+#if RF_OSC_26MHZ == 1
+    uint32_t ref_clk = 26U;
+#else
+    uint32_t ref_clk = 32U;
+#endif /* RF_OSC_26MHZ == 1 */
+
+    /* Check if sign bit is asserted */
+    if (pll_num_unsigned & 0x04000000U)
+    {
+        /* Sign extend the numerator */
+        pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU;
+
+        /* Calculate the frequency in MHz */
+        freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom)));
+    }
+    else
+    {
+        /* Calculate the frequency in MHz */
+        pll_num = pll_num_unsigned;
+        freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom)));
+    }
+
+    freq = (uint32_t)freq_float;
+
+    return freq;
+}
+
+void XCVR_ForceRxWu(void)
+{
+    XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK;
+}
+
+void XCVR_ForceRxWd(void)
+{
+    XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK;
+}
+
+void XCVR_ForceTxWu(void)
+{
+    XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
+}
+
+void XCVR_ForceTxWd(void)
+{
+    XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
+}
+
+xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol)
+{
+    uint32_t temp;
+    if ((protocol != 6) && (protocol != 7))
+    {
+        return gXcvrInvalidParameters_c; /* Failure */
+    }
+
+    if ((rf_channel_freq < 2360) || (rf_channel_freq >2487))
+    {
+        return gXcvrInvalidParameters_c; /* failure */
+    }
+
+    /* Set the DFT Mode */
+    temp  = XCVR_TX_DIG->CTRL;
+    temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK;
+    temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1);
+    XCVR_TX_DIG->CTRL = temp;
+
+    /* Choose Protocol 6 or 7 if using the Channel Number register */
+    temp  = XCVR_MISC->XCVR_CTRL;
+    temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK;
+    temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol);
+    XCVR_MISC->XCVR_CTRL = temp;
+
+    /* Select the RF Channel, using the Channel Number register */
+    XCVR_OverrideChannel(rf_channel_freq-2360,1);
+
+    /* Warm-up the Radio */
+    XCVR_ForceTxWu();
+
+    return gXcvrSuccess_c; /* Success */
+}
+
+xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern)
+{
+    uint32_t temp;
+    uint8_t dft_mode = 0;
+    uint8_t dft_clk_sel = 0;
+    xcvrStatus_t status = gXcvrSuccess_c;
+
+    XCVR_ChangeMode(radio_mode, data_rate);
+
+    /* Select the RF Channel, using the Channel Number register */
+    XCVR_OverrideChannel(channel_num, 1);
+
+    switch (radio_mode)
+    {
+        case ZIGBEE_MODE:
+            dft_mode = 6; /* OQPSK configuration */
+            break;
+        case ANT_MODE:
+        case BLE_MODE:
+        case GFSK_BT_0p5_h_0p5:
+        case GFSK_BT_0p5_h_0p32:
+        case GFSK_BT_0p5_h_0p7:
+        case GFSK_BT_0p5_h_1p0:
+        case GFSK_BT_0p3_h_0p5:
+        case GFSK_BT_0p7_h_0p5:
+            dft_mode = 2; /* GFSK configuration */
+            break;
+        case MSK:
+            dft_mode = 4; /* MSK configuration */
+            break;
+        default:
+            status = gXcvrInvalidParameters_c;
+            break;
+    }
+
+    if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */
+    {
+        switch (data_rate)
+        {
+            case DR_1MBPS:
+                dft_clk_sel = 4;
+                break;
+            case DR_500KBPS:
+                dft_clk_sel = 3;
+                break;
+            case DR_250KBPS:
+                dft_clk_sel = 2;
+                break;
+            default:
+                status = gXcvrInvalidParameters_c;
+                break;
+        }
+    }
+
+    temp = XCVR_TX_DIG->CTRL;
+    temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK);
+    temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) |
+            XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
+            XCVR_TX_DIG_CTRL_TX_DFT_EN(1) |
+            XCVR_TX_DIG_CTRL_LFSR_EN(0);
+    XCVR_TX_DIG->CTRL = temp;
+
+    XCVR_TX_DIG->DFT_PATTERN = tx_pattern;
+
+    if (status == gXcvrSuccess_c)
+    {
+        /* Warm-up the Radio */
+        XCVR_ForceTxWu();
+    }
+
+    return status;
+}
+
+xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length)
+{
+    uint32_t temp;
+    uint8_t dft_mode = 0;
+    uint8_t dft_clk_sel = 0;
+    xcvrStatus_t status = gXcvrSuccess_c;
+    uint8_t bitrate_setting = 0xFF;
+
+    if (lfsr_length > 5)
+    {
+        return gXcvrInvalidParameters_c;
+    }
+
+    XCVR_ChangeMode(radio_mode, data_rate);
+
+    /* Select the RF Channel, using the Channel Number register */
+    XCVR_OverrideChannel(channel_num, 1);
+
+    switch (radio_mode)
+    {
+        case ZIGBEE_MODE:
+            dft_mode = 7; /* OQPSK configuration */
+            break;
+        case ANT_MODE:
+        case BLE_MODE:
+        case GFSK_BT_0p5_h_0p5:
+        case GFSK_BT_0p5_h_0p32:
+        case GFSK_BT_0p5_h_0p7:
+        case GFSK_BT_0p5_h_1p0:
+        case GFSK_BT_0p3_h_0p5:
+        case GFSK_BT_0p7_h_0p5:
+            dft_mode = 3; /* GFSK configuration */
+            bitrate_setting = data_rate;
+            break;
+        case MSK:
+            dft_mode = 5; /* MSK configuration */
+            break;
+
+        default:
+            status = gXcvrInvalidParameters_c;
+            break;
+    }
+
+    if (status == gXcvrSuccess_c)
+    {
+        switch (data_rate)
+        {
+            case DR_1MBPS:
+                dft_clk_sel = 4;
+                break;
+            case DR_500KBPS:
+                dft_clk_sel = 3;
+                break;
+            case DR_250KBPS:
+                dft_clk_sel = 2;
+                break;
+            default:
+                status = gXcvrInvalidParameters_c;
+                break;
+        }
+    }
+
+    if (bitrate_setting < 4)
+    {
+        GENFSK->BITRATE = bitrate_setting;
+    }
+
+    temp = XCVR_TX_DIG->CTRL;
+    temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK |
+              XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK |
+              XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK |
+              XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK |
+              XCVR_TX_DIG_CTRL_LFSR_EN_MASK);
+    temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) |
+            XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) |
+            XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
+            XCVR_TX_DIG_CTRL_TX_DFT_EN(0) |
+            XCVR_TX_DIG_CTRL_LFSR_EN(1);
+    XCVR_TX_DIG->CTRL = temp;
+
+    if (status == gXcvrSuccess_c)
+    {
+        /* Warm-up the Radio */
+        XCVR_ForceTxWu();
+    }
+
+    return status;
+}
+
+void XCVR_DftTxOff(void)
+{
+    XCVR_ForceTxWd();
+    XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */
+    /* Clear the RF Channel over-ride */
+    XCVR_OverrideChannel(0xFF,1);
+    XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */
+                           XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */
+                           XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */
+                           XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */
+}
+
+xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power)
+{
+    if (pa_power > 0x3F)
+    {
+        return gXcvrInvalidParameters_c; /* Failure */
+    }
+
+    if (pa_power != 1)
+    {
+        pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */
+    }
+
+    XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */
+    XCVR_TSM->PA_POWER = pa_power;
+
+    return gXcvrSuccess_c; /* Success */
+}
+
+xcvrStatus_t XCVR_CoexistenceInit(void)
+{
+#if gMWS_UseCoexistence_d
+    uint32_t temp = 0x00U;
+    uint32_t end_of_tx_wu = 0x00U;
+    uint32_t end_of_rx_wu = 0x00U;
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
+    uint32_t tsm_timing47 = 0x00U;
+#else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */
+    uint32_t tsm_timing48 = 0x00U;
+#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
+    uint32_t tsm_timing50 = 0x00U;
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+    // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en)
+    uint32_t tsm_timing48 = 0x00U;
+    // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en)
+    uint32_t tsm_timing47 = 0x00U;
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+
+    uint16_t tsm_timing43_rx = 0x00;
+    uint16_t tsm_timing43_tx = 0x00;
+
+    /* Select GPIO mode for FAD pins */
+    temp = XCVR_MISC->FAD_CTRL;
+    temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK);
+    XCVR_MISC->FAD_CTRL = temp;
+
+    /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */
+    end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
+                    XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
+    end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >>
+                    XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
+
+/*****************
+ *  TX SEQUENCE  *
+ *****************/
+
+    if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d)
+    {
+        temp = end_of_tx_wu;
+    }
+    else
+    {
+        temp = gMWS_CoexRfActiveAssertTime_d;
+    }
+
+    /* Save the TX RF_ACTIVE start time. */
+    tsm_timing43_tx = end_of_tx_wu - temp;
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+    /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
+#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
+    tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
+                                                        XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
+#else
+    tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) &
+                                                        XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK);
+#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
+
+    /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
+    tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) &
+                                                        XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+    /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
+    tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) &
+                                                        XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK);
+
+    /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
+    tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
+                                                        XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+
+/*****************
+ *  RX SEQUENCE  *
+ *****************/
+
+    if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d)
+    {
+        temp = end_of_rx_wu;
+    }
+    else
+    {
+        temp = gMWS_CoexRfActiveAssertTime_d;
+    }
+
+    /* Save the RX RF_ACTIVE start time. */
+    tsm_timing43_rx = end_of_rx_wu - temp;
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+    /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */
+#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
+    tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
+                                                         XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
+#else
+    tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) &
+                                                         XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
+#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
+
+    /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */
+    tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) &
+                                                          XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
+                     (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) &
+                                                                             XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
+
+#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
+    temp = XCVR_TSM->TIMING47;
+    temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
+    temp |= tsm_timing47;
+    XCVR_TSM->TIMING47 = temp;
+#else
+    temp = XCVR_TSM->TIMING48;
+    temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
+    temp |= tsm_timing48;
+    XCVR_TSM->TIMING48 = temp;
+#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
+
+    temp = XCVR_TSM->TIMING50;
+    temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK |
+              XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK |
+              XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK);
+    temp |= tsm_timing50;
+    XCVR_TSM->TIMING50 = temp;
+
+#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
+    GPIOC->PDDR |= 0x18;
+    PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
+    PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
+#else
+    GPIOC->PDDR |= 0x0A;
+    PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
+    PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
+#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+    /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */
+    tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) &
+                                                         XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
+
+    /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */
+    tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
+                                                          XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
+
+    /* RF_ACTIVE */
+    temp = XCVR_TSM->TIMING48;
+    temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
+    temp |= tsm_timing48;
+    XCVR_TSM->TIMING48 = temp;
+
+    /* RF_PRIORITY */
+    temp = XCVR_TSM->TIMING47;
+    temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
+    temp |= tsm_timing47;
+    XCVR_TSM->TIMING47 = temp;
+
+    /* Overwrite pins settings */
+    GPIOC->PDDR |= 0x12;
+    PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
+    PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+
+    tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d;
+
+    if (tsm_timing43_tx > end_of_tx_wu - 1)
+    {
+        tsm_timing43_tx = end_of_tx_wu - 1;
+    }
+
+    tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d;
+
+    if (tsm_timing43_rx > end_of_rx_wu - 1)
+    {
+        tsm_timing43_rx = end_of_rx_wu - 1;
+    }
+
+    XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) |
+                          (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) |
+                          (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) |
+                          (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK));
+
+    BTLE_RF->MISC_CTRL = 0x02;
+
+    XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK;
+
+    /* Save the updated registers values. */
+    XCVR_CoexistenceSaveRestoreTimings(1);
+#endif /* gMWS_UseCoexistence_d */
+
+    return gXcvrSuccess_c;
+}
+
+xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority)
+{
+#if gMWS_UseCoexistence_d
+    uint32_t temp = 0x00U;
+    uint32_t end_of_tx_wu = 0x00U;
+    uint32_t end_of_rx_wu = 0x00U;
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+    uint32_t tsm_timing50 = 0x00U;
+#endif
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+    uint32_t tsm_timing47 = 0x00U;
+#endif
+
+    /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */
+    end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
+                    XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
+    end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >>
+                    XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
+
+/*****************
+ *      RX       *
+ *****************/
+
+    if (XCVR_COEX_HIGH_PRIO == rxPriority)
+    {
+        if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d)
+        {
+            temp = end_of_rx_wu;
+        }
+        else
+        {
+            temp = gMWS_CoexRfActiveAssertTime_d;
+        }
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+        /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */
+        tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) &
+                                                             XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
+                        (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) &
+                                                                                  XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+     /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */
+        tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
+                                                            XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+    }
+    else
+    {
+        /* Low priority RX */
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+        tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) &
+                                   XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
+                        ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) &
+                                   XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+        tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) &
+                                   XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) |
+                        ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) &
+                                   XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK));
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+    }
+
+/*****************
+ *      TX       *
+ *****************/
+    if (XCVR_COEX_HIGH_PRIO == txPriority)
+    {
+        if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d)
+        {
+            temp = end_of_tx_wu;
+        }
+        else
+        {
+            temp = gMWS_CoexRfActiveAssertTime_d;
+        }
+
+        /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+        tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) &
+                                                             XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+        tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
+                                                             XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+    }
+    else
+    {
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+        /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */
+        tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) &
+                                                      XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+        /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */
+        tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) &
+                                   XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) |
+                        ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) &
+                                   XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK));
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+    }
+
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+    temp = XCVR_TSM->TIMING50;
+    temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK |
+              XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK |
+              XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK);
+    temp |= tsm_timing50;
+    XCVR_TSM->TIMING50 = temp;
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
+#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
+    temp = XCVR_TSM->TIMING47;
+    temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK |
+              XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK |
+              XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK |
+              XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK);
+    temp |= tsm_timing47;
+    XCVR_TSM->TIMING47 = temp;
+#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
+
+    /* Save the updated registers values. */
+    XCVR_CoexistenceSaveRestoreTimings(1);
+#endif /* gMWS_UseCoexistence_d */
+
+    return gXcvrSuccess_c;
+}
+
+xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings)
+{
+#if gMWS_UseCoexistence_d
+    static uint32_t tsm_ovrd0_saved = 0x00;
+    static uint32_t tsm_ovrd1_saved = 0x00;
+    static uint32_t tsm_ovrd2_saved = 0x00;
+    static uint32_t tsm_ovrd3_saved = 0x00;
+    static uint32_t tsm_timing47_saved = 0x00;
+    static uint32_t tsm_timing48_saved = 0x00;
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+    static uint32_t tsm_timing49_saved = 0x00;
+    static uint32_t tsm_timing50_saved = 0x00;
+#endif
+
+    if (saveTimings == 0)
+    {
+        /* Restore registers values. */
+        XCVR_TSM->OVRD0 = tsm_ovrd0_saved;
+        XCVR_TSM->OVRD1 = tsm_ovrd1_saved;
+        XCVR_TSM->OVRD2 = tsm_ovrd2_saved;
+        XCVR_TSM->OVRD3 = tsm_ovrd3_saved;
+
+        XCVR_TSM->TIMING47 = tsm_timing47_saved;
+        XCVR_TSM->TIMING48 = tsm_timing48_saved;
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+        XCVR_TSM->TIMING49 = tsm_timing49_saved;
+        XCVR_TSM->TIMING50 = tsm_timing50_saved;
+#endif
+    }
+    else
+    {
+        /* Save registers values. */
+        tsm_ovrd0_saved = XCVR_TSM->OVRD0;
+        tsm_ovrd1_saved = XCVR_TSM->OVRD1;
+        tsm_ovrd2_saved = XCVR_TSM->OVRD2;
+        tsm_ovrd3_saved = XCVR_TSM->OVRD3;
+        tsm_timing47_saved = XCVR_TSM->TIMING47;
+        tsm_timing48_saved = XCVR_TSM->TIMING48;
+#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
+        tsm_timing49_saved = XCVR_TSM->TIMING49;
+        tsm_timing50_saved = XCVR_TSM->TIMING50;
+#endif
+    }
+#endif /* gMWS_UseCoexistence_d */
+
+    return gXcvrSuccess_c;
+}
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h
new file mode 100644
index 0000000000000..0233af3245441
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h
@@ -0,0 +1,1236 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_XCVR_H_
+/* clang-format off */
+#define _FSL_XCVR_H_
+/* clang-format on */
+
+#include "cpu.h"
+#include "fsl_xcvr_trim.h"
+
+#if gMWS_UseCoexistence_d
+#include "MWS.h"
+#endif /* gMWS_UseCoexistence_d */
+/*!
+ * @addtogroup xcvr
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* KW4xZ/KW3xZ/KW2xZ Radio type */
+#define RADIO_IS_GEN_2P0  (1)
+
+/* Default RF OSC definition. Allows for compile time clock frequency definition */
+#ifdef CLOCK_MAIN
+
+#else
+#if RF_OSC_26MHZ == 1
+#define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */
+#else
+#define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */
+#endif /* RF_OSC_26MHZ == 1 */
+#endif /* CLOCK_MAIN */
+
+#define TBD_ZERO                (0)
+#define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0))
+
+#define B0(x)   (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU)
+#define B1(x)   (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U)
+#define B2(x)   (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U)
+#define B3(x)   (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U)
+
+#define USE_DEFAULT_PRE_REF             (0)
+#define TRIM_BBA_DCOC_DAC_AT_INIT       (1)
+#define PRESLOW_ENA                     (1)
+
+/* GEN3 TSM defines */
+#if RADIO_IS_GEN_3P0
+
+/* TSM timings initializations for Gen3 radio */
+/* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */
+/* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */
+/* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */
+#if RF_OSC_26MHZ == 1
+#define TSM_TIMING00init  (0x6d006f00U) /* (bb_ldo_hf_en) */
+#define TSM_TIMING01init  (0x6d006f00U) /* (bb_ldo_adcdac_en) */
+#define TSM_TIMING02init  (0x6d00ffffU) /* (bb_ldo_bba_en) */
+#define TSM_TIMING03init  (0x6d006f00U) /* (bb_ldo_pd_en) */
+#define TSM_TIMING04init  (0x6d006f00U) /* (bb_ldo_fdbk_en) */
+#define TSM_TIMING05init  (0x6d006f00U) /* (bb_ldo_vcolo_en) */
+#define TSM_TIMING06init  (0x6d006f00U) /* (bb_ldo_vtref_en) */
+#define TSM_TIMING07init  (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */
+#define TSM_TIMING08init  (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */
+#define TSM_TIMING09init  (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */
+#define TSM_TIMING10init  (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */
+#define TSM_TIMING11init  (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */
+#define TSM_TIMING12init  (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */
+#define TSM_TIMING13init  (0x18004c00U) /* (sy_vco_autotune_en) */
+#define TSM_TIMING14init  (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */
+#define TSM_TIMING15init  (0x6d036f03U) /* (sy_vco_en) */
+#define TSM_TIMING16init  (0x6d20ffffU) /* (sy_lo_rx_buf_en) */
+#define TSM_TIMING17init  (0xffff6f58U) /* (sy_lo_tx_buf_en) */
+#define TSM_TIMING18init  (0x6d056f05U) /* (sy_divn_en) */
+#define TSM_TIMING19init  (0x18034c03U) /* (sy_pd_filter_charge_en) */
+#define TSM_TIMING20init  (0x6d036f03U) /* (sy_pd_en) */
+#define TSM_TIMING21init  (0x6d046f04U) /* (sy_lo_divn_en) */
+#define TSM_TIMING22init  (0x6d04ffffU) /* (sy_lo_rx_en) */
+#define TSM_TIMING23init  (0xffff6f04U) /* (sy_lo_tx_en) */
+#define TSM_TIMING24init  (0x18004c00U) /* (sy_divn_cal_en) */
+#define TSM_TIMING25init  (0x6d21ffffU) /* (rx_lna_mixer_en) */
+#define TSM_TIMING26init  (0xffff6e58U) /* (tx_pa_en) */
+#define TSM_TIMING27init  (0x6d24ffffU) /* (rx_adc_i_q_en) */
+#define TSM_TIMING28init  (0x2524ffffU) /* (rx_adc_reset_en) */
+#define TSM_TIMING29init  (0x6d22ffffU) /* (rx_bba_i_q_en) */
+#define TSM_TIMING30init  (0x6d24ffffU) /* (rx_bba_pdet_en) */
+#define TSM_TIMING31init  (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */
+#define TSM_TIMING32init  (0x6d21ffffU) /* (rx_tza_i_q_en) */
+#define TSM_TIMING33init  (0x6d24ffffU) /* (rx_tza_pdet_en) */
+#define TSM_TIMING34init  (0x6d076f07U) /* (pll_dig_en) */
+#define TSM_TIMING35init  (0xffff6f5fU) /* (tx_dig_en) */
+#define TSM_TIMING36init  (0x6d6affffU) /* (rx_dig_en) */
+#define TSM_TIMING37init  (0x6b6affffU) /* (rx_init) */
+#define TSM_TIMING38init  (0x6d0e6f42U) /* (sigma_delta_en) */
+#define TSM_TIMING39init  (0x6d6affffU) /* (rx_phy_en) */
+#define TSM_TIMING40init  (0x6d2affffU) /* (dcoc_en) */
+#define TSM_TIMING41init  (0x2b2affffU) /* (dcoc_init) */
+#define TSM_TIMING42init  (0xffffffffU) /* (sar_adc_trig_en) */
+#define TSM_TIMING43init  (0xffffffffU) /* (tsm_spare0_en) */
+#define TSM_TIMING44init  (0xffffffffU) /* (tsm_spare1_en) */
+#define TSM_TIMING45init  (0xffffffffU) /* (tsm_spare2_en) */
+#define TSM_TIMING46init  (0xffffffffU) /* (tsm_spare3_en) */
+#define TSM_TIMING47init  (0xffffffffU) /* (gpio0_trig_en) */
+#define TSM_TIMING48init  (0xffffffffU) /* (gpio1_trig_en) */
+#define TSM_TIMING49init  (0xffffffffU) /* (gpio2_trig_en) */
+#define TSM_TIMING50init  (0xffffffffU) /* (gpio3_trig_en) */
+#define TSM_TIMING51init  (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */
+#define TSM_TIMING52init  (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */
+#define TSM_TIMING53init  (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */
+#define TSM_TIMING54init  (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */
+#define TSM_TIMING55init  (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */
+#define TSM_TIMING56init  (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */
+#define TSM_TIMING57init  (0x1a03ffffU) /* (rxtx_rccal_en) */
+#define TSM_TIMING58init  (0xffff6f03U) /* (tx_hpm_dac_en) */
+#define END_OF_SEQinit    (0x6d6c6f67U) /*  */
+#define TX_RX_ON_DELinit  (0x00008a86U) /*  */
+#define TX_RX_SYNTH_init  (0x00002318U) /*  */
+#else
+#define TSM_TIMING00init  (0x69006f00U) /* (bb_ldo_hf_en) */
+#define TSM_TIMING01init  (0x69006f00U) /* (bb_ldo_adcdac_en) */
+#define TSM_TIMING02init  (0x6900ffffU) /* (bb_ldo_bba_en) */
+#define TSM_TIMING03init  (0x69006f00U) /* (bb_ldo_pd_en) */
+#define TSM_TIMING04init  (0x69006f00U) /* (bb_ldo_fdbk_en) */
+#define TSM_TIMING05init  (0x69006f00U) /* (bb_ldo_vcolo_en) */
+#define TSM_TIMING06init  (0x69006f00U) /* (bb_ldo_vtref_en) */
+#define TSM_TIMING07init  (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */
+#define TSM_TIMING08init  (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */
+#define TSM_TIMING09init  (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */
+#define TSM_TIMING10init  (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */
+#define TSM_TIMING11init  (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */
+#define TSM_TIMING12init  (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */
+#define TSM_TIMING13init  (0x18004c00U) /* (sy_vco_autotune_en) */
+#define TSM_TIMING14init  (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */
+#define TSM_TIMING15init  (0x69036f03U) /* (sy_vco_en) */
+#define TSM_TIMING16init  (0x691cffffU) /* (sy_lo_rx_buf_en) */
+#define TSM_TIMING17init  (0xffff6f58U) /* (sy_lo_tx_buf_en) */
+#define TSM_TIMING18init  (0x69056f05U) /* (sy_divn_en) */
+#define TSM_TIMING19init  (0x18034c03U) /* (sy_pd_filter_charge_en) */
+#define TSM_TIMING20init  (0x69036f03U) /* (sy_pd_en) */
+#define TSM_TIMING21init  (0x69046f04U) /* (sy_lo_divn_en) */
+#define TSM_TIMING22init  (0x6904ffffU) /* (sy_lo_rx_en) */
+#define TSM_TIMING23init  (0xffff6f04U) /* (sy_lo_tx_en) */
+#define TSM_TIMING24init  (0x18004c00U) /* (sy_divn_cal_en) */
+#define TSM_TIMING25init  (0x691dffffU) /* (rx_lna_mixer_en) */
+#define TSM_TIMING26init  (0xffff6e58U) /* (tx_pa_en) */
+#define TSM_TIMING27init  (0x6920ffffU) /* (rx_adc_i_q_en) */
+#define TSM_TIMING28init  (0x2120ffffU) /* (rx_adc_reset_en) */
+#define TSM_TIMING29init  (0x691effffU) /* (rx_bba_i_q_en) */
+#define TSM_TIMING30init  (0x6920ffffU) /* (rx_bba_pdet_en) */
+#define TSM_TIMING31init  (0x691fffffU) /* (rx_bba_tza_dcoc_en) */
+#define TSM_TIMING32init  (0x691dffffU) /* (rx_tza_i_q_en) */
+#define TSM_TIMING33init  (0x6920ffffU) /* (rx_tza_pdet_en) */
+#define TSM_TIMING34init  (0x69076f07U) /* (pll_dig_en) */
+#define TSM_TIMING35init  (0xffff6f5fU) /* (tx_dig_en) */
+#define TSM_TIMING36init  (0x6966ffffU) /* (rx_dig_en) */
+#define TSM_TIMING37init  (0x6766ffffU) /* (rx_init) */
+#define TSM_TIMING38init  (0x690e6f42U) /* (sigma_delta_en) */
+#define TSM_TIMING39init  (0x6966ffffU) /* (rx_phy_en) */
+#define TSM_TIMING40init  (0x6926ffffU) /* (dcoc_en) */
+#define TSM_TIMING41init  (0x2726ffffU) /* (dcoc_init) */
+#define TSM_TIMING42init  (0xffffffffU) /* (sar_adc_trig_en) */
+#define TSM_TIMING43init  (0xffffffffU) /* (tsm_spare0_en) */
+#define TSM_TIMING44init  (0xffffffffU) /* (tsm_spare1_en) */
+#define TSM_TIMING45init  (0xffffffffU) /* (tsm_spare2_en) */
+#define TSM_TIMING46init  (0xffffffffU) /* (tsm_spare3_en) */
+#define TSM_TIMING47init  (0xffffffffU) /* (gpio0_trig_en) */
+#define TSM_TIMING48init  (0xffffffffU) /* (gpio1_trig_en) */
+#define TSM_TIMING49init  (0xffffffffU) /* (gpio2_trig_en) */
+#define TSM_TIMING50init  (0xffffffffU) /* (gpio3_trig_en) */
+#define TSM_TIMING51init  (0x6903ffffU) /* (rxtx_auxpll_bias_en) */
+#define TSM_TIMING52init  (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */
+#define TSM_TIMING53init  (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */
+#define TSM_TIMING54init  (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */
+#define TSM_TIMING55init  (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */
+#define TSM_TIMING56init  (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */
+#define TSM_TIMING57init  (0x1a03ffffU) /* (rxtx_rccal_en) */
+#define TSM_TIMING58init  (0xffff6f03U) /* (tx_hpm_dac_en) */
+#define END_OF_SEQinit    (0x69686f67U) /*  */
+#define TX_RX_ON_DELinit  (0x00008a86U) /*  */
+#define TX_RX_SYNTH_init  (0x00002318U) /*  */
+#endif /* RF_OSC_26MHZ == 1 */
+
+#define AUX_PLL_DELAY       (0)
+/* TSM bitfield shift and value definitions */
+#define TX_DIG_EN_ASSERT    (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */
+#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */
+/* EDIT THIS LINE TO CONTROL PA_RAMP! */
+#define PA_RAMP_TIME        (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */
+#define PA_RAMP_SEL_0US     (0)
+#define PA_RAMP_SEL_1US     (1)
+#define PA_RAMP_SEL_2US     (2)
+#define PA_RAMP_SEL_4US     (3)
+#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4))
+#error "Invalid value for PA_RAMP_TIME macro"
+#endif /* Error check of PA RAMP TIME */
+
+#define ADD_FOR_26MHZ           (4)
+#define END_OF_TX_WU_NORAMP     (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
+#define END_OF_TX_WD_NORAMP     (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
+/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */
+/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */
+#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2))
+    #define END_OF_TX_WU   (END_OF_TX_WU_NORAMP)
+    #define END_OF_TX_WD   (END_OF_TX_WD_NORAMP)
+    #if (PA_RAMP_TIME == 0)
+        #define PA_RAMP_SEL PA_RAMP_SEL_0US
+        #define DATA_PADDING_EN (0)
+    #else
+        #define DATA_PADDING_EN (1)
+        #if (PA_RAMP_TIME == 1)
+            #define PA_RAMP_SEL PA_RAMP_SEL_1US
+        #else
+            #define PA_RAMP_SEL PA_RAMP_SEL_2US
+        #endif /* (PA_RAMP_TIME == 1) */
+    #endif /* (PA_RAMP_TIME == 0) */
+#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) */
+    #if (PA_RAMP_TIME == 4)
+        #define END_OF_TX_WU    (END_OF_TX_WU_NORAMP + 2)
+        #define END_OF_TX_WD    (END_OF_TX_WD_NORAMP + 4)
+        #define PA_RAMP_SEL PA_RAMP_SEL_4US
+        #define DATA_PADDING_EN (1)
+    #else /* (PA_RAMP_TIME == 4) */
+        #error "Invalid value for PA_RAMP_TIME macro"
+    #endif /* (PA_RAMP_TIME == 4) */
+#endif/* (PA_RAMP_TIME == 4) */
+
+#define END_OF_RX_WU    (104 + AUX_PLL_DELAY)
+
+#if RF_OSC_26MHZ == 1
+#define END_OF_RX_WD    (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */
+#else
+#define END_OF_RX_WD    (END_OF_RX_WU + 1)
+#endif /* RF_OSC_26MHZ == 1 */
+
+#define END_OF_RX_WU_26MHZ  (END_OF_RX_WU + ADD_FOR_26MHZ)
+#define END_OF_RX_WD_26MHZ  (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)
+
+/* PA Bias Table - Gen3 version */
+#define PA_RAMP_0 0x1
+#define PA_RAMP_1 0x2
+#define PA_RAMP_2 0x4
+#define PA_RAMP_3 0x6
+#define PA_RAMP_4 0x8
+#define PA_RAMP_5 0xc
+#define PA_RAMP_6 0x10
+#define PA_RAMP_7 0x14
+#define PA_RAMP_8 0x18
+#define PA_RAMP_9 0x1c
+#define PA_RAMP_10 0x22
+#define PA_RAMP_11 0x28
+#define PA_RAMP_12 0x2c
+#define PA_RAMP_13 0x30
+#define PA_RAMP_14 0x36
+#define PA_RAMP_15 0x3c
+
+#else /* Gen2 TSM definitions */
+/* GEN2 TSM defines */
+#define AUX_PLL_DELAY       (0)
+/* TSM bitfield shift and value definitions */
+#define TX_DIG_EN_ASSERT    (95)
+#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */
+/* EDIT THIS LINE TO CONTROL PA_RAMP! */
+#define PA_RAMP_TIME        (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */
+#define PA_RAMP_SEL_0US     (0)
+#define PA_RAMP_SEL_2US     (1)
+#define PA_RAMP_SEL_4US     (2)
+#define PA_RAMP_SEL_8US     (3)
+
+#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4) || (PA_RAMP_TIME == 8))
+#error "Invalid value for PA_RAMP_TIME macro"
+#endif /* Error check of PA RAMP TIME */
+#define ADD_FOR_26MHZ           (4)
+#define END_OF_TX_WU_NORAMP     (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
+#define END_OF_TX_WD_NORAMP     (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
+/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */
+/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */
+#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2))
+    #define END_OF_TX_WU   (END_OF_TX_WU_NORAMP)
+    #define END_OF_TX_WD   (END_OF_TX_WD_NORAMP)
+    #define TX_SYNTH_DELAY_ADJ       (0)
+    #define PD_CYCLE_SLIP_TX_HI_ADJ  (0)
+    #define PD_CYCLE_SLIP_TX_LO_ADJ  (1)
+    #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */
+    #if (PA_RAMP_TIME == 0)
+        #define PA_RAMP_SEL PA_RAMP_SEL_0US
+        #define DATA_PADDING_EN     (0)
+        #define TX_DIG_EN_TX_HI_ADJ (-2)
+    #else
+        #define DATA_PADDING_EN     (1)
+        #define TX_DIG_EN_TX_HI_ADJ (0)
+        #define PA_RAMP_SEL PA_RAMP_SEL_2US
+    #endif /* (PA_RAMP_TIME == 0) */
+#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */
+    #if (PA_RAMP_TIME == 4)
+        #define END_OF_TX_WU    (END_OF_TX_WU_NORAMP + 2)
+        #define END_OF_TX_WD    (END_OF_TX_WD_NORAMP + 4)
+        #define TX_SYNTH_DELAY_ADJ       (2)
+        #define PD_CYCLE_SLIP_TX_HI_ADJ  (2)
+        #define PD_CYCLE_SLIP_TX_LO_ADJ  (1)
+        #define TX_DIG_EN_TX_HI_ADJ      (0)
+        #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */
+        #define PA_RAMP_SEL PA_RAMP_SEL_4US
+        #define DATA_PADDING_EN (1)
+    #else /* (PA_RAMP_TIME==4) */
+        #if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0))
+            #define END_OF_TX_WU    (END_OF_TX_WU_NORAMP + 6)
+            #define END_OF_TX_WD    (END_OF_TX_WD_NORAMP + 12)
+            #define TX_SYNTH_DELAY_ADJ       (6)
+            #define PD_CYCLE_SLIP_TX_HI_ADJ  (6)
+            #define PD_CYCLE_SLIP_TX_LO_ADJ  (1)
+            #define TX_DIG_EN_TX_HI_ADJ      (4)
+            #define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */
+            #define PA_RAMP_SEL PA_RAMP_SEL_8US
+            #define DATA_PADDING_EN (1)
+        #else /* (PA_RAMP_TIME == 8) */
+            #error "Invalid value for PA_RAMP_TIME macro"
+        #endif /* (PA_RAMP_TIME == 8) */
+    #endif/* (PA_RAMP_TIME == 4) */
+#endif /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */
+
+#define TX_DIG_EN_ASSERT_MSK500    (END_OF_TX_WU - 3)
+
+#define END_OF_RX_WU    (104 + AUX_PLL_DELAY)
+#if RF_OSC_26MHZ == 1
+#define END_OF_RX_WD    (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)  /* Need to handle normal signals extending when 26MHZ warmdown is extended */
+#else
+#define END_OF_RX_WD    (END_OF_RX_WU + 1)
+#endif /* RF_OSC_26MHZ == 1 */
+#define END_OF_RX_WU_26MHZ  (END_OF_RX_WU + ADD_FOR_26MHZ)
+#define END_OF_RX_WD_26MHZ  (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)
+
+/* PA Bias Table */
+#define PA_RAMP_0 0x1
+#define PA_RAMP_1 0x2
+#define PA_RAMP_2 0x4
+#define PA_RAMP_3 0x8
+#define PA_RAMP_4 0xe
+#define PA_RAMP_5 0x16
+#define PA_RAMP_6 0x22
+#define PA_RAMP_7 0x2e
+
+/* BLE LL timing definitions */
+#define TX_ON_DELAY     (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */
+#define RX_ON_DELAY     (29 + END_OF_RX_WU)
+#define RX_ON_DELAY_26MHZ     (29 + END_OF_RX_WU_26MHZ)
+#define TX_RX_ON_DELAY_VAL  (TX_ON_DELAY << 8 | RX_ON_DELAY)
+#define TX_RX_ON_DELAY_VAL_26MHZ  (TX_ON_DELAY << 8 | RX_ON_DELAY_26MHZ)
+#define TX_SYNTH_DELAY  (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */
+#define RX_SYNTH_DELAY  (0x18)
+#define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 | RX_SYNTH_DELAY)
+
+/* PHY reference waveform assembly */
+#define RW0PS(loc, val)      (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */
+#define RW1PS(loc, val)      (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */
+#define RW2PS(loc, val)      (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */
+#endif /* RADIO_IS_GEN_3P0 */
+
+/*! @brief  Error codes for the XCVR driver. */
+typedef enum _xcvrStatus
+{
+    gXcvrSuccess_c = 0,
+    gXcvrInvalidParameters_c,
+    gXcvrUnsupportedOperation_c,
+    gXcvrTrimFailure_c
+} xcvrStatus_t;
+
+/*! @brief  Health status returned from PHY upon status check function return. */
+typedef enum _healthStatus
+{
+    NO_ERRORS = 0,
+    PLL_CTUNE_FAIL = 1,
+    PLL_CYCLE_SLIP_FAIL = 2,
+    PLL_FREQ_TARG_FAIL = 4,
+    PLL_TSM_ABORT_FAIL = 8,
+} healthStatus_t;
+
+/*! @brief  Health status returned from PHY upon status check function return. */
+typedef enum _ext_clock_config
+{
+    EXT_CLK_32_MHZ = 0,
+    EXT_CLK_26_MHZ = 1,
+} ext_clock_config_t;
+
+/*! @brief  Radio operating mode setting types. */
+typedef enum _radio_mode
+{
+    BLE_MODE = 0,
+    ZIGBEE_MODE = 1,
+    ANT_MODE = 2,
+
+    /* BT=0.5, h=** */
+    GFSK_BT_0p5_h_0p5  = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */
+    GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/
+    GFSK_BT_0p5_h_0p7  = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */
+    GFSK_BT_0p5_h_1p0  = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */
+
+    /* BT=** h=0.5 */
+    GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */
+    GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */
+
+    MSK = 9,
+    NUM_RADIO_MODES = 10,
+} radio_mode_t;
+
+/*! @brief  Link layer types. */
+typedef enum _link_layer
+{
+    BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */
+    ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */
+    ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */
+    GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */
+    UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */
+} link_layer_t;
+
+/*! @brief  Data rate selections. */
+typedef enum _data_rate
+{
+    DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */
+    DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */
+    DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */
+#if RADIO_IS_GEN_3P0
+    DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */
+#endif /* RADIO_IS_GEN_3P0 */
+    DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */
+} data_rate_t;
+
+/*! @brief  Control settings for Fast Antenna Diversity */
+typedef enum  _FAD_LPPS_CTRL
+{
+    NONE = 0,
+    FAD_ENABLED = 1,
+    LPPS_ENABLED = 2
+} FAD_LPPS_CTRL_T;
+
+/*! @brief  XCVR XCVR Panic codes for indicating panic reason. */
+typedef enum _XCVR_PANIC_ID
+{
+    WRONG_RADIO_ID_DETECTED = 1,
+    CALIBRATION_INVALID = 2,
+} XCVR_PANIC_ID_T;
+
+/*! @brief  Initialization or mode change selection for config routine. */
+typedef enum _XCVR_INIT_MODE_CHG
+{
+    XCVR_MODE_CHANGE = 0,
+    XCVR_FIRST_INIT = 1,
+} XCVR_INIT_MODE_CHG_T;
+
+typedef enum _XCVR_COEX_PRIORITY
+{
+    XCVR_COEX_LOW_PRIO = 0,
+    XCVR_COEX_HIGH_PRIO = 1
+}   XCVR_COEX_PRIORITY_T;
+
+/*! @brief Current configuration of the radio. */
+typedef struct xcvr_currConfig_tag
+{
+    radio_mode_t radio_mode;
+    data_rate_t data_rate;
+} xcvr_currConfig_t;
+
+/*!
+ * @brief XCVR RX_DIG channel filter coefficient storage
+ * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage.
+ */
+typedef struct _xcvr_rx_chf_coeffs
+{
+    uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */
+    uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */
+} xcvr_rx_chf_coeffs_t;
+
+/*!
+ * @brief XCVR masked init type for 32 bit registers
+ * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position.
+ */
+typedef struct _xcvr_masked_init_32
+{
+    uint32_t mask;
+    uint32_t init;
+} xcvr_masked_init_32_t;
+
+/*!
+ * @brief XCVR common configure structure
+ */
+typedef struct _xcvr_common_config
+{
+    /* XCVR_ANA configs */
+    xcvr_masked_init_32_t ana_sy_ctrl1;
+
+    /* XCVR_PLL_DIG configs */
+    uint32_t pll_hpm_bump;
+    uint32_t pll_mod_ctrl;
+    uint32_t pll_chan_map;
+    uint32_t pll_lock_detect;
+    uint32_t pll_hpm_ctrl;
+#if !RADIO_IS_GEN_2P1
+    uint32_t pll_hpmcal_ctrl;
+#endif /* !RADIO_IS_GEN_2P1 */
+    uint32_t pll_hpm_sdm_res;
+    uint32_t pll_lpm_ctrl;
+    uint32_t pll_lpm_sdm_ctrl1;
+    uint32_t pll_delay_match;
+    uint32_t pll_ctune_ctrl;
+
+    /* XCVR_RX_DIG configs */
+    uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
+    uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */
+    uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */
+    uint32_t dcoc_ctrl_1_init;
+    uint32_t dcoc_cal_gain_init;
+    uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */
+    uint32_t dcoc_cal_rcp_init;
+    uint32_t lna_gain_val_3_0;
+    uint32_t lna_gain_val_7_4;
+    uint32_t lna_gain_val_8;
+    uint32_t bba_res_tune_val_7_0;
+    uint32_t bba_res_tune_val_10_8;
+    uint32_t lna_gain_lin_val_2_0_init;
+    uint32_t lna_gain_lin_val_5_3_init;
+    uint32_t lna_gain_lin_val_8_6_init;
+    uint32_t lna_gain_lin_val_9_init;
+    uint32_t bba_res_tune_lin_val_3_0_init;
+    uint32_t bba_res_tune_lin_val_7_4_init;
+    uint32_t bba_res_tune_lin_val_10_8_init;
+    uint32_t dcoc_bba_step_init;
+    uint32_t dcoc_tza_step_00_init;
+    uint32_t dcoc_tza_step_01_init;
+    uint32_t dcoc_tza_step_02_init;
+    uint32_t dcoc_tza_step_03_init;
+    uint32_t dcoc_tza_step_04_init;
+    uint32_t dcoc_tza_step_05_init;
+    uint32_t dcoc_tza_step_06_init;
+    uint32_t dcoc_tza_step_07_init;
+    uint32_t dcoc_tza_step_08_init;
+    uint32_t dcoc_tza_step_09_init;
+    uint32_t dcoc_tza_step_10_init;
+#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1)
+    uint32_t dcoc_cal_fail_th_init;
+    uint32_t dcoc_cal_pass_th_init;
+#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */
+    uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */
+    uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */
+    uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */
+    uint32_t agc_ctrl_3_init;
+    /* Other agc config inits moved to modeXdatarate config table */
+    uint32_t agc_gain_tbl_03_00_init;
+    uint32_t agc_gain_tbl_07_04_init;
+    uint32_t agc_gain_tbl_11_08_init;
+    uint32_t agc_gain_tbl_15_12_init;
+    uint32_t agc_gain_tbl_19_16_init;
+    uint32_t agc_gain_tbl_23_20_init;
+    uint32_t agc_gain_tbl_26_24_init;
+    uint32_t rssi_ctrl_0_init;
+#if RADIO_IS_GEN_3P0
+    uint32_t rssi_ctrl_1_init;
+#endif /* RADIO_IS_GEN_3P0 */
+    uint32_t cca_ed_lqi_ctrl_0_init;
+    uint32_t cca_ed_lqi_ctrl_1_init;
+
+    /* XCVR_TSM configs */
+    uint32_t tsm_ctrl;
+    uint32_t tsm_ovrd2_init;
+    uint32_t end_of_seq_init_26mhz;
+    uint32_t end_of_seq_init_32mhz;
+#if !RADIO_IS_GEN_2P1
+    uint32_t lpps_ctrl_init;
+#endif /* !RADIO_IS_GEN_2P1 */
+    uint32_t tsm_fast_ctrl2_init_26mhz;
+    uint32_t tsm_fast_ctrl2_init_32mhz;
+    uint32_t recycle_count_init_26mhz;
+    uint32_t recycle_count_init_32mhz;
+    uint32_t pa_ramp_tbl_0_init;
+    uint32_t pa_ramp_tbl_1_init;
+#if RADIO_IS_GEN_3P0
+    uint32_t pa_ramp_tbl_2_init;
+    uint32_t pa_ramp_tbl_3_init;
+#endif /* RADIO_IS_GEN_3P0 */
+    uint32_t tsm_timing_00_init;
+    uint32_t tsm_timing_01_init;
+    uint32_t tsm_timing_02_init;
+    uint32_t tsm_timing_03_init;
+    uint32_t tsm_timing_04_init;
+    uint32_t tsm_timing_05_init;
+    uint32_t tsm_timing_06_init;
+    uint32_t tsm_timing_07_init;
+    uint32_t tsm_timing_08_init;
+    uint32_t tsm_timing_09_init;
+    uint32_t tsm_timing_10_init;
+    uint32_t tsm_timing_11_init;
+    uint32_t tsm_timing_12_init;
+    uint32_t tsm_timing_13_init;
+    uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */
+    uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */
+    uint32_t tsm_timing_15_init;
+    uint32_t tsm_timing_16_init_26mhz;
+    uint32_t tsm_timing_16_init_32mhz;
+    uint32_t tsm_timing_17_init;
+    uint32_t tsm_timing_18_init;
+    uint32_t tsm_timing_19_init;
+    uint32_t tsm_timing_20_init;
+    uint32_t tsm_timing_21_init;
+    uint32_t tsm_timing_22_init;
+    uint32_t tsm_timing_23_init;
+    uint32_t tsm_timing_24_init;
+    uint32_t tsm_timing_25_init_26mhz;
+    uint32_t tsm_timing_25_init_32mhz;
+    uint32_t tsm_timing_26_init;
+    uint32_t tsm_timing_27_init_26mhz;
+    uint32_t tsm_timing_27_init_32mhz;
+    uint32_t tsm_timing_28_init_26mhz;
+    uint32_t tsm_timing_28_init_32mhz;
+    uint32_t tsm_timing_29_init_26mhz;
+    uint32_t tsm_timing_29_init_32mhz;
+    uint32_t tsm_timing_30_init_26mhz;
+    uint32_t tsm_timing_30_init_32mhz;
+    uint32_t tsm_timing_31_init_26mhz;
+    uint32_t tsm_timing_31_init_32mhz;
+    uint32_t tsm_timing_32_init_26mhz;
+    uint32_t tsm_timing_32_init_32mhz;
+    uint32_t tsm_timing_33_init_26mhz;
+    uint32_t tsm_timing_33_init_32mhz;
+    uint32_t tsm_timing_34_init;
+    uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/
+    uint32_t tsm_timing_36_init_26mhz;
+    uint32_t tsm_timing_36_init_32mhz;
+    uint32_t tsm_timing_37_init_26mhz;
+    uint32_t tsm_timing_37_init_32mhz;
+    uint32_t tsm_timing_38_init;
+    uint32_t tsm_timing_39_init_26mhz;
+    uint32_t tsm_timing_39_init_32mhz;
+    uint32_t tsm_timing_40_init_26mhz;
+    uint32_t tsm_timing_40_init_32mhz;
+    uint32_t tsm_timing_41_init_26mhz;
+    uint32_t tsm_timing_41_init_32mhz;
+    uint32_t tsm_timing_51_init;
+    uint32_t tsm_timing_52_init_26mhz;
+    uint32_t tsm_timing_52_init_32mhz;
+    uint32_t tsm_timing_53_init;
+    uint32_t tsm_timing_54_init_26mhz;
+    uint32_t tsm_timing_54_init_32mhz;
+    uint32_t tsm_timing_55_init_26mhz;
+    uint32_t tsm_timing_55_init_32mhz;
+    uint32_t tsm_timing_56_init_26mhz;
+    uint32_t tsm_timing_56_init_32mhz;
+    uint32_t tsm_timing_57_init;
+    uint32_t tsm_timing_58_init;
+
+    /* XCVR_TX_DIG configs */
+    uint32_t tx_ctrl;
+    uint32_t tx_data_padding;
+     uint32_t tx_dft_pattern;
+#if !RADIO_IS_GEN_2P1
+    uint32_t rf_dft_bist_1;
+    uint32_t rf_dft_bist_2;
+#endif /* !RADIO_IS_GEN_2P1 */
+} xcvr_common_config_t;
+
+/*! @brief XCVR mode specific configure structure (varies by radio mode) */
+typedef struct _xcvr_mode_config
+{
+    radio_mode_t radio_mode;
+    uint32_t scgc5_clock_ena_bits;
+
+    /* XCVR_MISC configs */
+    xcvr_masked_init_32_t xcvr_ctrl;
+
+    /* XCVR_PHY configs */
+#if RADIO_IS_GEN_3P0
+    uint32_t phy_fsk_pd_cfg0;
+    uint32_t phy_fsk_pd_cfg1;
+    uint32_t phy_fsk_cfg;
+    uint32_t phy_fsk_misc;
+    uint32_t phy_fad_ctrl;
+#else
+    uint32_t phy_pre_ref0_init;
+    uint32_t phy_pre_ref1_init;
+    uint32_t phy_pre_ref2_init;
+    uint32_t phy_cfg1_init;
+    uint32_t phy_el_cfg_init; /* Should leave EL_WIN_SIZE and EL_INTERVAL to the data_rate specific configuration */
+#endif /* RADIO_IS_GEN_3P0 */
+
+    /* XCVR_RX_DIG configs */
+    uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
+    uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
+    uint32_t agc_ctrl_0_init; /* NOTE:  Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */
+
+    /* XCVR_TSM configs */
+#if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1)
+    uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */
+#endif /* (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) */
+
+    /* XCVR_TX_DIG configs */
+    uint32_t tx_gfsk_ctrl;
+    uint32_t tx_gfsk_coeff1_26mhz;
+    uint32_t tx_gfsk_coeff2_26mhz;
+    uint32_t tx_gfsk_coeff1_32mhz;
+    uint32_t tx_gfsk_coeff2_32mhz;
+} xcvr_mode_config_t;
+
+/*!
+ * @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate)
+ * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay
+ * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate.
+ */
+typedef struct _xcvr_mode_datarate_config
+{
+    radio_mode_t radio_mode;
+    data_rate_t data_rate;
+
+    /* XCVR_ANA configs */
+    xcvr_masked_init_32_t ana_sy_ctrl2;
+    xcvr_masked_init_32_t ana_rx_bba;
+    xcvr_masked_init_32_t ana_rx_tza;
+
+    /* XCVR_PHY configs */
+#if RADIO_IS_GEN_3P0
+    uint32_t phy_fsk_misc_mode_datarate;
+#else
+    uint32_t phy_cfg2_init;
+#endif /* RADIO_IS_GEN_3P0 */
+
+    uint32_t agc_ctrl_2_init_26mhz;
+    uint32_t agc_ctrl_2_init_32mhz;
+    xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */
+    xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */
+    uint32_t rx_rccal_ctrl_0;
+    uint32_t rx_rccal_ctrl_1;
+
+    /* XCVR_TX_DIG configs */
+    uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */
+    uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */
+} xcvr_mode_datarate_config_t;
+
+/*!
+ * @brief XCVR datarate specific configure structure (varies by data rate)
+ * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay
+ * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate.
+ */
+typedef struct _xcvr_datarate_config
+{
+    data_rate_t data_rate;
+
+    /* XCVR_PHY configs */
+    uint32_t phy_el_cfg_init; /* Note: EL_ENABLE  is set in xcvr_mode_config_t settings */
+
+    /* XCVR_RX_DIG configs */
+    uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
+    uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
+    uint32_t agc_ctrl_1_init_26mhz;
+    uint32_t agc_ctrl_1_init_32mhz;
+    uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */
+    uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */
+    uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */
+    uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */
+    uint32_t dcoc_ctrl_2_init_26mhz;
+    uint32_t dcoc_ctrl_2_init_32mhz;
+    uint32_t dcoc_cal_iir_init_26mhz;
+    uint32_t dcoc_cal_iir_init_32mhz;
+    uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */
+    uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */
+} xcvr_datarate_config_t;
+
+/*!
+ * @brief LPUART callback function type
+ *
+ * The panic callback function is defined by system if system need to be informed of XCVR fatal errors.
+ * refer to #XCVR_RegisterPanicCb
+ */
+typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2);
+
+/* Make available const structures from config files */
+extern const xcvr_common_config_t xcvr_common_config;
+extern const xcvr_mode_config_t zgbe_mode_config;
+extern const xcvr_mode_config_t ble_mode_config;
+extern const xcvr_mode_config_t ant_mode_config;
+extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config;
+extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config;
+extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config;
+extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config;
+extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config;
+extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config;
+extern const xcvr_mode_config_t msk_mode_config;
+
+#if RADIO_IS_GEN_3P0
+extern const xcvr_datarate_config_t xcvr_2mbps_config;
+#endif /* RADIO_IS_GEN_3P0 */
+extern const xcvr_datarate_config_t xcvr_1mbps_config;
+extern const xcvr_datarate_config_t xcvr_500kbps_config;
+extern const xcvr_datarate_config_t xcvr_250kbps_config;
+extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */
+
+#if RADIO_IS_GEN_3P0
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config;
+#endif /* RADIO_IS_GEN_3P0 */
+extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config;
+extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name XCVR functional Operation
+ * @{
+ */
+
+/*!
+ * @brief  Initializes an XCVR instance.
+ *
+ * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to
+ * start up the XCVR in most situations.
+ *
+ * @param radio_mode The radio mode for which the XCVR should be configured.
+ * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
+ * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions.
+ */
+xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate);
+
+/*!
+ * @brief  Deinitializes an XCVR instance.
+ *
+ * This function gate the XCVR module clock and set all register value to reset value.
+ *
+ */
+void XCVR_Deinit(void);
+
+/*!
+ * @brief  Initializes XCVR configure structure.
+ *
+ * This function updates pointers to the XCVR configure structures with default values.
+ * The configurations are divided into a common structure, a set of radio mode specific
+ * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at
+ * each datarate), and a set of data rate specific structures.
+ * The pointers provided by this routine point to const structures which can be
+ * copied to variable structures if changes to settings are required.
+ *
+ * @param radio_mode [in] The radio mode for which the configuration structures are requested.
+ * @param data_rate [in] The data rate for which the configuration structures are requested.
+ * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure.
+ * @param mode_config  [in,out] Pointer to a pointer to the mode specific configuration settings structure.
+ * @param mode_datarate_config  [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure.
+ * @param datarate_config  [in,out] Pointer to a pointer to the data rate specific configuration settings structure.
+ * @return 0 success, others failure
+ * @see XCVR_Configure
+ */
+xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode,
+                                   data_rate_t data_rate,
+                                   const xcvr_common_config_t ** com_config,
+                                   const xcvr_mode_config_t ** mode_config,
+                                   const xcvr_mode_datarate_config_t ** mode_datarate_config,
+                                   const xcvr_datarate_config_t ** datarate_config);
+
+/*!
+ * @brief  Initializes an XCVR instance.
+ *
+ * This function initializes the XCVR module with user-defined settings.
+ *
+ * @param com_config Pointer to the common configuration settings structure.
+ * @param mode_config Pointer to the mode specific configuration settings structure.
+ * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure.
+ * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure.
+ * @param tempDegC temperature of the die in degrees C.
+ * @param ext_clk indicates the external clock setting, 32MHz or 26MHz.
+ * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0)
+ * @return 0 succeed, others failed
+ */
+xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config,
+                            const xcvr_mode_config_t *mode_config,
+                            const xcvr_mode_datarate_config_t *mode_datarate_config,
+                            const xcvr_datarate_config_t *datarate_config,
+                            int16_t tempDegC,
+                            XCVR_INIT_MODE_CHG_T first_init);
+
+/*!
+ * @brief Set XCVR register to reset value.
+ *
+ * This function set XCVR register to the reset value.
+ *
+ */
+void XCVR_Reset(void);
+
+/*!
+ * @brief  Change the operating mode of the radio.
+ *
+ * This function changes the XCVR to a new radio operating mode.
+ *
+ * @param new_radio_mode The radio mode for which the XCVR should be configured.
+ * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
+ * @return status of the mode change.
+ */
+ xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate);
+
+/*!
+ * @brief  Enable Narrowband RSSI measurement.
+ *
+ * This function enables the narrowband RSSI measurement
+ *
+ * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled.
+ */
+void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable);
+
+/*!
+ * @brief  Set an arbitrary frequency for RX and TX for the radio.
+ *
+ * This function sets the radio frequency used for RX and RX..
+ *
+ * @param freq target frequency setting in Hz.
+ * @param refOsc reference oscillator setting in Hz.
+ * @return status of the frequency change.
+ * @details
+ */
+ xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc);
+
+/*!
+ * @brief  Register a callback from upper layers.
+ *
+ * This function registers a callback from the upper layers for the radio to call in case of fatal errors.
+ *
+ * @param fptr The function pointer to a panic callback.
+ */
+void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */
+
+/*!
+ * @brief  Read the health status of the XCVR to detect errors.
+ *
+ * This function enables the upper layers to request the current radio health.
+ *
+ * @return The health status of the radio..
+ */
+healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */
+
+/*!
+ * @brief  Control FAD and LPPS features.
+ *
+ * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search.
+ *
+ * @param fptr control the FAD and LPPS settings.
+ *
+ */
+ void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control);
+
+/*!
+ * @brief  Change the mapping of the radio IRQs.
+ *
+ * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines.
+ *
+ * @param irq0_mapping  the LL which should be mapped to the INT0 line.
+ * @param irq1_mapping  the LL which should be mapped to the INT1 line.
+ * @return status of the mapping request.
+ * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line.
+ * @warning
+ *  The same LL must NOT be mapped to both INT lines.
+ */
+ xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping);
+
+#if RADIO_IS_GEN_3P0
+/*!
+ * @brief  Sets the network address used by the PHY during BLE Bit Streaming Mode.
+ *
+ * This function programs the register in the PHY which contains the network address used during BSM.
+ *
+ * @param bsm_ntw_address  the address to be used during BSM.
+ * @ note This routine does NOT enable BSM.
+ */
+void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address);
+
+/*!
+ * @brief  Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode.
+ *
+ * This function reads the register in the PHY which contains the network address used during BSM.
+ *
+ * @return bsm_ntw_address  the address to be used during BSM.
+ * @ note This routine does NOT enable BSM.
+ */
+uint32_t XCVR_GetBSM_NTW_Address(void);
+#endif /* RADIO_IS_GEN_3P0 */
+
+/*!
+ * @brief  Get the mapping of the one of the radio IRQs.
+ *
+ * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines.
+ *
+ * @param int_num the number, 0 or 1, of the INT line to fetched.
+ * @return the mapping setting of the specified line.
+ * @note Any value passed into this routine other than 0 will be treated as a 1.
+ */
+ link_layer_t XCVR_GetIRQMapping(uint8_t int_num);
+
+/*!
+ * @brief  Get the current configuration of the XCVR.
+ *
+ * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc
+ *
+ * @param curr_config pointer to a structure to be updated with the current mode and data rate.
+ * @return the status of the request, success or invalid parameter (null pointer).
+ * @note This API will return meaningless results if called before the radio is initialized...
+ */
+xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config);
+
+/*******************************************************************************
+ * Customer level trim functions
+ ******************************************************************************/
+/*!
+ * @brief  Controls setting the XTAL trim value..
+ *
+ * This function enables the upper layers set a crystal trim compensation facor
+ *
+ * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error.
+ * @return The health status of the radio..
+ */
+xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim);
+
+/*!
+ * @brief  Controls getting the XTAL trim value..
+ *
+ * This function enables the upper layers to read the current XTAL compensation factors.
+ * The returned value is in the range 0..127 (7 bits).
+ *
+ * @return The XTAL trim compensation factors..
+ */
+uint8_t  XCVR_GetXtalTrim(void);
+
+/*!
+ * @brief  Controls setting the RSSI adjustment..
+ *
+ * This function enables the upper layers to set an RSSI adjustment value.
+ *
+ * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step.
+ * @return The health status of the radio..
+ */
+xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj);
+
+/*!
+ * @brief  Controls getting the RSSI adjustment..
+ *
+ * This function enables the upper layers to read the current XCVR RSSI adjustment value.
+ * The returned value is a signed 8-bit value, in 1/4 dBm step.
+ *
+ * @return The RSSI adjustment value..
+ */
+int8_t  XCVR_GetRssiAdjustment(void);
+
+/*!
+ * @brief  Controls setting the PLL to a particular channel.
+ *
+ * This function enables setting the radio channel for TX and RX.
+ *
+ * @param channel the channel number to set
+ * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list..
+ * @return The status of the channel over-ride.
+ */
+xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel);
+
+/*!
+ * @brief  Reads the current frequency for RX and TX for the radio.
+ *
+ * This function reads the radio frequency used for RX and RX..
+ *
+ * @return Current radio frequency setting.
+ */
+uint32_t XCVR_GetFreq(void);
+
+/*!
+ * @brief  Force receiver warmup.
+ *
+ * This function forces the initiation of a receiver warmup sequence.
+ *
+ */
+void XCVR_ForceRxWu(void);
+
+/*!
+ * @brief  Force receiver warmdown.
+ *
+ * This function forces the initiation of a receiver warmdown sequence.
+ *
+ */
+ void XCVR_ForceRxWd(void);
+
+/*!
+ * @brief  Force transmitter warmup.
+ *
+ * This function forces the initiation of a transmit warmup sequence.
+ *
+ */
+void XCVR_ForceTxWu(void);
+
+/*!
+ * @brief  Force transmitter warmdown.
+ *
+ * This function forces the initiation of a transmit warmdown sequence.
+ *
+ */
+void XCVR_ForceTxWd(void);
+
+/*!
+ * @brief  Starts transmit with a TX pattern register data sequence.
+ *
+ * This function starts transmitting using the DFT pattern register mode.
+ *
+ * @param channel_num -  the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation.
+ * @param radio_mode The radio mode for which the XCVR should be configured.
+ * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
+ * @param tx_pattern -  the data pattern to transmit on.
+ * @return The status of the pattern reg transmit.
+ * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode
+ *   and data rate.
+ */
+xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern);
+
+/*!
+ * @brief  Starts transmit with a TX LFSR register data sequence.
+ *
+ * This function starts transmitting using the DFT LFSR register mode.
+ *
+ * @param channel_num -  the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation.
+ * @param radio_mode The radio mode for which the XCVR should be configured.
+ * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
+ * @param lfsr_length -  the length of the LFSR sequence to use.
+ * @return The status of the LFSR reg transmit.
+ * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode
+ *   and data rate.
+ */
+xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length);
+
+/*!
+ * @brief Controls clearing all TX DFT settings.
+ *
+ * This function reverts all TX DFT settings from the test modes to normal operating mode.
+ *
+ */
+void XCVR_DftTxOff(void);
+
+/*!
+ * @brief  Controls setting the PA power level.
+ *
+ * This function enables setting the PA power level to a specific setting, overriding any link layer settings.
+ *
+ * @param pa_power -  the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive.
+ * @return The status of the PA power over-ride.
+ */
+xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power);
+
+/*!
+ * @brief Starts CW TX.
+ *
+ * This function starts transmitting CW (no modulation).
+ *
+ * @param rf_channel_freq -  the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive.
+ * @param protocol -  the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK).
+ * @return The status of the CW transmit.
+ */
+xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol);
+
+xcvrStatus_t XCVR_CoexistenceInit(void);
+xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority);
+xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_XCVR_H_ */
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c
new file mode 100644
index 0000000000000..319a104a0e8bc
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+const xcvr_mode_config_t ant_mode_config =
+{
+    .radio_mode = ANT_MODE,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK 
+#if !RADIO_IS_GEN_2P1
+    | SIM_SCGC5_ANT_MASK
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = RW0PS(0, 0x1B) |
+                         RW0PS(1, 0x1CU) |
+                         RW0PS(2, 0x1CU) |
+                         RW0PS(3, 0x1CU) |
+                         RW0PS(4, 0x1DU) |
+                         RW0PS(5, 0x1DU) |
+                         RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/
+    .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words  - manually compute the shift */
+                         RW1PS(7, 0x1EU) |
+                         RW1PS(8, 0x1EU) |
+                         RW1PS(9, 0x1EU) |
+                         RW1PS(10, 0x1EU) |
+                         RW1PS(11, 0x1DU) |
+                         RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */
+    .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */
+                         RW2PS(13, 0x1CU) |
+                         RW2PS(14, 0x1CU) |
+                         RW2PS(15, 0x1CU),
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(0xF8) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) 
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config =
+{
+    .radio_mode = ANT_MODE,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069,
+
+     /* ANT 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c
new file mode 100644
index 0000000000000..054b0ccfeaa06
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+const xcvr_mode_config_t ble_mode_config =
+{
+    .radio_mode = BLE_MODE,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = RW0PS(0, 0x19) |
+                         RW0PS(1, 0x19U) |
+                         RW0PS(2, 0x1AU) |
+                         RW0PS(3, 0x1BU) |
+                         RW0PS(4, 0x1CU) |
+                         RW0PS(5, 0x1CU) |
+                         RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */
+    .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/
+                         RW1PS(7, 0x1EU) |
+                         RW1PS(8, 0x1EU) |
+                         RW1PS(9, 0x1EU) |
+                         RW1PS(10, 0x1DU) |
+                         RW1PS(11, 0x1CU) |
+                         RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */
+    .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/
+                         RW2PS(13, 0x1BU) |
+                         RW2PS(14, 0x1AU) |
+                         RW2PS(15, 0x19U),
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(220) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz =  XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config =
+{
+    .radio_mode = BLE_MODE,
+    .data_rate = DR_1MBPS,
+    
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* BLE 26MHz Channel Filter */
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063,
+
+    /* BLE 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c
new file mode 100644
index 0000000000000..4277d3a1f74ff
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c
@@ -0,0 +1,623 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+const xcvr_common_config_t xcvr_common_config =
+{
+    /* XCVR_ANA configs */
+    .ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK,
+    .ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */
+
+#define hpm_vcm_tx 0
+#define hpm_vcm_cal 1
+#define hpm_fdb_res_tx 0
+#define hpm_fdb_res_cal 1
+#define modulation_word_manual 0
+#define mod_disable 0
+#define hpm_mod_manual 0
+#define hpm_mod_disable 0
+#define hpm_sdm_out_manual 0
+#define hpm_sdm_out_disable 0
+#define channel_num 0
+#define boc 0
+#define bmr 1
+#define zoc 0
+#define ctune_ldf_lev 8
+#define ftf_rx_thrsh 33
+#define ftw_rx 0
+#define ftf_tx_thrsh 6
+#define ftw_tx 0
+#define freq_count_go 0
+#define freq_count_time 0
+#define hpm_sdm_in_manual 0
+#define hpm_sdm_out_invert 0
+#define hpm_sdm_in_disable 0
+#define hpm_lfsr_size 4
+#define hpm_dth_scl 0
+#define hpm_dth_en 1
+#define hpm_integer_scale 0
+#define hpm_integer_invert 0
+#define hpm_cal_invert 1
+#define hpm_mod_in_invert 1
+#define hpm_cal_not_bumped 0
+#define hpm_cal_count_scale 0
+#define hp_cal_disable 0
+#define hpm_cal_factor_manual 0
+#define hpm_cal_array_size 1
+#define hpm_cal_time 0
+#define hpm_sdm_denom 256
+#define hpm_count_adjust 0
+#define pll_ld_manual 0
+#define pll_ld_disable 0
+#define lpm_sdm_inv 0
+#define lpm_disable 0
+#define lpm_dth_scl 8
+#define lpm_d_ctrl 1
+#define lpm_d_ovrd 1
+#define lpm_scale 8
+#define lpm_sdm_use_neg 0
+#define hpm_array_bias 0
+#define lpm_intg 38
+#define sdm_map_disable 0
+#define lpm_sdm_delay 4
+#define hpm_sdm_delay 0
+#define hpm_integer_delay 0
+#define ctune_target_manual 0
+#define ctune_target_disable 0
+#define ctune_adjust 0
+#define ctune_manual 0
+#define ctune_disable 0
+
+/*-------------------------------------------------------------------------------------------------*/
+
+    .pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) |
+                    XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) |
+                    XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) |
+                    XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx),
+
+/*-------------------------------------------------------------------------------------------------*/
+
+    .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) |
+                    XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | 
+                    XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) |
+                    XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) |
+                    XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) |
+                    XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual),
+
+/*-------------------------------------------------------------------------------------------------*/
+
+    .pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) |
+                    XCVR_PLL_DIG_CHAN_MAP_BOC(boc) |
+                    XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num)
+#if !RADIO_IS_GEN_2P1
+                  | XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+/*-------------------------------------------------------------------------------------------------*/
+
+    .pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) |
+                       XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) |
+                       XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) |
+                       XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) |
+                       XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) |
+                       XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) |
+                       XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx),
+
+/*-------------------------------------------------------------------------------------------------*/
+
+    .pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) |
+                    XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert),
+/*-------------------------------------------------------------------------------------------------*/
+#if !RADIO_IS_GEN_2P1
+    .pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) |
+                       XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) |
+                       XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) |
+                       XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) |
+                       XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) |
+                       XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time),
+#endif /* !RADIO_IS_GEN_2P1 */
+/*-------------------------------------------------------------------------------------------------*/
+    .pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) |
+                       XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom),
+/*-------------------------------------------------------------------------------------------------*/
+    .pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) |
+                    XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) |
+                    XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) |
+                    XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) |
+                    XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) |
+                    XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) |
+                    XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) |
+                    XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) |
+                    XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual),
+/*-------------------------------------------------------------------------------------------------*/
+    .pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) |
+                         XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) |
+                         XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable),
+/*-------------------------------------------------------------------------------------------------*/
+    .pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) |
+                       XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) |
+                       XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay),
+/*-------------------------------------------------------------------------------------------------*/
+    .pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) |
+                      XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) |
+                      XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) |
+                      XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) |
+                      XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual),
+/*-------------------------------------------------------------------------------------------------*/
+
+    /* XCVR_RX_DIG configs */
+    /* NOTE: Clock specific settings are embedded in the mode dependent configs */
+    .rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) |
+#if !RADIO_IS_GEN_2P1
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) |
+#endif /* !RADIO_IS_GEN_2P1 */
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) |
+                        XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1),
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) |
+                       XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) |
+                       XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) |
+                       XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) |
+                       XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) |
+                       XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) |
+                       XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) |
+                       XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) |
+                       XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7),
+
+    .agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) |
+                       XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) |
+                       XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) |
+                       XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) |
+                       XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2),    
+
+    /* DCOC configs */
+    .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */
+#if (RADIO_IS_GEN_2P1)
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) |
+#endif /* (RADIO_IS_GEN_2P1) */
+                              XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | 
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1),
+    .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */
+#if (RADIO_IS_GEN_2P1)
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) |
+#endif /* (RADIO_IS_GEN_2P1) */
+                              XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) |  
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1),
+    
+    .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26),
+
+    .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(4) |
+                          XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) |
+                          XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) |
+                          XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26),
+
+    .dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) |
+                          XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) |
+                          XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) |
+                          XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) |
+                          XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) |
+                          XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) ,
+
+    .dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) |
+                         XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711),
+
+    .lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) |
+                        XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) |
+                        XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) |
+                        XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U),
+
+    .lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) |
+                        XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) |
+                        XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) |
+                        XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU),
+    .lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) |
+                      XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U),
+
+    .bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) |
+                            XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) |
+                            XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) |
+                            XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) |
+                            XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) |
+                            XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) |
+                            XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) |
+                            XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF),
+    .bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) |
+                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) |
+                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2),
+
+    .lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) |
+                                 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) |
+                                 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1),
+
+    .lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) |
+                                 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) |
+                                 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7),
+
+    .lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) |
+                                 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) |
+                                 XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50),
+
+    .lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91),
+
+    .bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) |
+                                     XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) |
+                                     XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) |
+                                     XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22),
+
+    .bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) |
+                                     XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) |
+                                     XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) |
+                                     XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */
+
+    .bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) |
+                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) |
+                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288),
+
+    .dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) |
+                          XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279),
+
+    .dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404),
+    .dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439),
+    .dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691),
+    .dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192),
+    .dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835),
+    .dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601),
+    .dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427),
+    .dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310),
+    .dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209),
+    .dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145),
+    .dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) |
+                             XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99),
+#if (RADIO_IS_GEN_2P1)
+    .dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) |
+                             XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10),
+    .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) |
+                             XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2),
+#endif /* (RADIO_IS_GEN_2P1) */
+    /* AGC Configs */    
+    .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | 
+                               XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | 
+                               XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | 
+                               XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2),
+
+    .agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2),
+
+    .agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4),
+
+    .agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5),
+
+    .agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7),
+
+    .agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7),
+
+    .agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) |
+                               XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10),
+    
+    .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) |
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) |
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) |
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) |
+#if !RADIO_IS_GEN_2P1
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) |
+#else
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) |
+#endif /* !RADIO_IS_GEN_2P1 */
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) |
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) |
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) |
+                        XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) ,
+
+    .cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0),
+
+    .cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) |
+#if !RADIO_IS_GEN_2P1
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) |
+#endif /* !RADIO_IS_GEN_2P1 */
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) |
+                              XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2),
+
+    /* XCVR_TSM configs */
+    .tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) |
+                XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) |
+                XCVR_TSM_CTRL_TSM_IRQ0_EN(0) |
+                XCVR_TSM_CTRL_TSM_IRQ1_EN(0) |
+                XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) |
+                XCVR_TSM_CTRL_TX_ABORT_DIS(0) |
+                XCVR_TSM_CTRL_RX_ABORT_DIS(0) |
+                XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) |
+                XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) |
+                XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) |
+                XCVR_TSM_CTRL_BKPT(0xFF) ,
+
+    .tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK,
+    .end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
+    .end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
+
+#if !RADIO_IS_GEN_2P1
+    .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0),
+#endif /* !RADIO_IS_GEN_2P1 */
+
+    .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8),
+    .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8),
+
+    .pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) |
+                          XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3),
+    .pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) |
+                          XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7),
+
+    .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ),
+    .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66),
+
+    .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */
+    .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */
+    .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */
+    .tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */
+    .tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */
+    .tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */
+    .tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */
+    .tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */
+    .tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */
+    .tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */
+
+    .tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */
+    .tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */
+    .tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */
+    .tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */
+    .tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */
+    .tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ),
+    .tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */
+    .tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */
+    .tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */
+    .tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */
+    .tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */
+
+    .tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */
+    .tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */
+    .tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) |           B0(0xFF), /* sy_lo_rx_en */
+    .tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en  */
+    .tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */
+    .tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */
+    .tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */
+    .tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */
+    .tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */
+    .tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */
+    .tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+
+    .tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */
+    .tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */
+    .tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */
+    .tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */
+    .tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */
+    .tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */
+    .tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */
+    .tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */
+    .tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */
+    .tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */
+    .tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+
+    .tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */
+    .tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */
+    .tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */
+    .tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */
+    .tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */
+    .tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */
+    .tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */
+    .tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */
+    .tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
+    .tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en  */
+    .tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */
+
+/* XCVR_TX_DIG configs */
+#define radio_dft_mode 0
+#define lfsr_length 4
+#define lfsr_en 0
+#define dft_clk_sel 4
+#define tx_dft_en 0
+#define soc_test_sel 0
+#define tx_capture_pol 0
+#define freq_word_adj 0
+#define lrm 0
+#define data_padding_pat_1 0x55
+#define data_padding_pat_0 0xAA
+#define gfsk_multiply_table_manual 0
+#define gfsk_mi 1
+#define gfsk_mld 0
+#define gfsk_fld 0
+#define gfsk_mod_index_scaling 0
+#define tx_image_filter_ovrd_en 0
+#define tx_image_filter_0_ovrd 0
+#define tx_image_filter_1_ovrd 0
+#define tx_image_filter_2_ovrd 0
+#define gfsk_filter_coeff_manual2 0xC0630401
+#define gfsk_filter_coeff_manual1 0xBB29960D
+#define fsk_modulation_scale_0 0x1800
+#define fsk_modulation_scale_1 0x0800
+#define dft_mod_patternval 0
+#define ctune_bist_go 0
+#define ctune_bist_thrshld 0
+#define pa_am_mod_freq 0
+#define pa_am_mod_entries 0
+#define pa_am_mod_en 0
+#define syn_bist_go 0
+#define syn_bist_all_channels 0
+#define freq_count_threshold 0
+#define hpm_inl_bist_go 0
+#define hpm_dnl_bist_go 0
+#define dft_max_ram_size 0
+
+    .tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) |
+               XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) |
+               XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) |
+               XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
+               XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) |
+               XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) |
+               XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) |
+               XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj),
+/*-------------------------------------------------------------------------------------------------*/
+    .tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) |
+                       XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) |
+                       XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0),
+/*-------------------------------------------------------------------------------------------------*/
+    .tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval),
+#if !RADIO_IS_GEN_2P1
+/*-------------------------------------------------------------------------------------------------*/
+    .rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) |
+                     XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) |
+                     XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) |
+                     XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) |
+                     XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en),
+/*-------------------------------------------------------------------------------------------------*/
+    .rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) |
+                     XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) |
+                     XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) |
+                     XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) |
+                     XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) |
+                     XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size),
+#endif /* !RADIO_IS_GEN_2P1 */
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c
new file mode 100644
index 0000000000000..8bb5e3637c8ed
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* MODE only configuration */
+const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config =
+{
+    .radio_mode = GFSK_BT_0p3_h_0p5,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = 0x7BCDEB39,
+    .phy_pre_ref1_init = 0xCEF7DEF7,
+    .phy_pre_ref2_init = 0x0000CEB7,
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(0xda) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */
+                            (164U) << 7 | /* coeff 6/9 */
+                            (125U) << 16 | /* coef 3/12 */
+                            (169U) << 23, /* coeff 7/8 */
+    .tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */
+                            (90U) << 8 | /* coeff 1/14 */
+                            (141U) << 16 | /* coeff 4/11 */
+                            (155U) << 24, /* coeff 5/10 */
+    .tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */
+                            (216U) << 7 | /* coeff 6/9 */
+                            (105U) << 16 | /* coef 3/12 */
+                            (233U) << 23, /* coeff 7/8 */
+    .tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */
+                            (44U) << 8 | /* coeff 1/14 */
+                            (145U) << 16 | /* coeff 4/11 */
+                            (184U) << 24, /* coeff 5/10 */
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config =
+{
+    .radio_mode = GFSK_BT_0p3_h_0p5,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config =
+{
+    .radio_mode = GFSK_BT_0p3_h_0p5,
+    .data_rate = DR_500KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config =
+{
+    .radio_mode = GFSK_BT_0p3_h_0p5,
+    .data_rate = DR_250KBPS,
+    
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+             
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1),
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c
new file mode 100644
index 0000000000000..55366cf7498dd
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* MODE only configuration */
+const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p32,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+                     
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = 0xBBDE739B,
+    .phy_pre_ref1_init = 0xDEFBDEF7,
+    .phy_pre_ref2_init = 0x0000E739,
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(0xF0) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p32,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) ,
+                        
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069,
+    
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p32,
+    .data_rate = DR_500KBPS,
+    
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF3,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0025,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0043,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x006B,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0004,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFE,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF6,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFED,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0020,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0044,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0064,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0077,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                   XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p32,
+    .data_rate = DR_250KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c
new file mode 100644
index 0000000000000..d57d0696eb108
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* MODE only configuration */
+const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p5,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+
+    .phy_pre_ref0_init = RW0PS(0, 0x19) |
+                         RW0PS(1, 0x19U) |
+                         RW0PS(2, 0x1AU) |
+                         RW0PS(3, 0x1BU) |
+                         RW0PS(4, 0x1CU) |
+                         RW0PS(5, 0x1CU) |
+                         RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */
+    .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/
+                         RW1PS(7, 0x1EU) |
+                         RW1PS(8, 0x1EU) |
+                         RW1PS(9, 0x1EU) |
+                         RW1PS(10, 0x1DU) |
+                         RW1PS(11, 0x1CU) |
+                         RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */
+    .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/
+                         RW2PS(13, 0x1BU) |
+                         RW2PS(14, 0x1AU) |
+                         RW2PS(15, 0x19U),
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(205) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+/* MODE & DATA RATE combined configuration */
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p5,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* BLE 26MHz Channel Filter */
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063,
+
+    /* BLE 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p5,
+    .data_rate = DR_500KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079,
+    
+    /* 32MHz */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p5,
+    .data_rate = DR_250KBPS,
+    
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c
new file mode 100644
index 0000000000000..cc680b61014ea
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* MODE only configuration */
+const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p7,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = 0x37ACE2F7,
+    .phy_pre_ref1_init = 0xADF3BDEF,
+    .phy_pre_ref2_init = 0x0000BE33,
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(0xCD) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+    
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p7,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p7,
+    .data_rate = DR_500KBPS,
+    
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0005,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x000C,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003D,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008F,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0004,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0006,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFDF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE3,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_0p7,
+    .data_rate = DR_250KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D,
+
+    /* 32MHz Channel Filter */  
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c
new file mode 100644
index 0000000000000..49c6dc75c23d4
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* MODE only configuration */
+const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_1p0,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+
+    /* XCVR_PHY configs */   
+    .phy_pre_ref0_init = 0xF38B5273,
+    .phy_pre_ref1_init = 0x8CEF9CE6,
+    .phy_pre_ref2_init = 0x00009D2D,
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(0xb0) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(3) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_1p0,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0003,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF9,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEB,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE9,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0008,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003A,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0090,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE1,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0034,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009A,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_1p0,
+    .data_rate = DR_500KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFD,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFEA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF3,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0021,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x0013,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFC9,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x005E,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F,
+    
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFE1,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEE,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0034,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFB7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x003B,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x004F,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFF5B,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0xFFB5,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x018B,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config =
+{
+    .radio_mode = GFSK_BT_0p5_h_1p0,
+    .data_rate = DR_250KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x000C,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0011,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000B,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE0,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFF0,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E,
+    
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x000F,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0019,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x000C,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEB,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFCD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFD7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0017,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0075,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00BB,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c
new file mode 100644
index 0000000000000..46f6c85086a9a
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* MODE only configuration */
+const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config =
+{
+    .radio_mode = GFSK_BT_0p7_h_0p5,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+                     
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = 0x79CDEB39,
+    .phy_pre_ref1_init = 0xCE77DEF7,
+    .phy_pre_ref2_init = 0x0000CEB7,
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(0xb0) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */
+                            (276U) << 7 | /* Coeff 6/9 */
+                            (62U) << 16 | /* Coef 3/12 */
+                            (326U) << 23, /* Coeff 7/8 */
+    .tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */
+                            (10U) << 8 | /* Coeff 1/14 */
+                            (121U) << 16 | /* Coeff 4/11 */
+                            (198U) << 24, /* Coeff 5/10 */
+    .tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */
+                            (330U) << 7 | /* Coeff 6/9 */
+                            (7U) << 16 | /* Coef 3/12 */
+                            (510U) << 23, /* Coeff 7/8 */
+    .tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */
+                            (0U) << 8 | /* Coeff 1/14 */
+                            (37U) << 16 | /* Coeff 4/11 */
+                            (138U) << 24, /* Coeff 5/10 */
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config =
+{
+    .radio_mode = GFSK_BT_0p7_h_0p5,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config =
+{
+    .radio_mode = GFSK_BT_0p7_h_0p5,
+    .data_rate = DR_500KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD,
+
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config =
+{
+    .radio_mode = GFSK_BT_0p7_h_0p5,
+    .data_rate = DR_250KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D,
+    
+    /* 32MHz Channel Filter */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c
new file mode 100644
index 0000000000000..dcfc9574758fe
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* ========================= DATA RATE ONLY settings ===============*/
+/*!
+ * @brief XCVR 1Mbps DATA RATE specific configure structure
+ */
+const xcvr_datarate_config_t xcvr_1mbps_config =
+{
+    .data_rate = DR_1MBPS,
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0xF) |
+#if !RADIO_IS_GEN_2P1
+                       XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
+#endif /* !RADIO_IS_GEN_2P1 */
+                       XCVR_PHY_EL_CFG_EL_INTERVAL(0x20) ,
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(0) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+
+    .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+    .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+
+    .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(10) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(21),
+    .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(12) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(26),
+    
+    .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3),
+
+    .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3),
+
+    .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
+    .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(3) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
+
+    .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(33) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(6),
+    .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(7),
+};
+
+/*!
+ * @brief XCVR 500K bps DATA RATE specific configure structure
+ */
+const xcvr_datarate_config_t xcvr_500kbps_config =
+{
+    .data_rate = DR_500KBPS,
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) |
+#if !RADIO_IS_GEN_2P1
+                       XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
+#endif /* !RADIO_IS_GEN_2P1 */
+                       XCVR_PHY_EL_CFG_EL_INTERVAL(0x10),
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+
+    .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+    .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+
+    .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29),
+    .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(36),
+
+    .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
+
+    .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
+
+    .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
+    .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
+
+    .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
+    .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
+};
+
+/*!
+ * @brief XCVR 250K bps DATA RATE specific configure structure
+ */
+const xcvr_datarate_config_t xcvr_250kbps_config =
+{
+    .data_rate = DR_250KBPS,
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x4) |
+#if !RADIO_IS_GEN_2P1
+                       XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
+#endif /* !RADIO_IS_GEN_2P1 */
+                       XCVR_PHY_EL_CFG_EL_INTERVAL(0x8) ,
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(4) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+
+    .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+    .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+
+    .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(34),
+    .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(20) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(42),
+
+    .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
+
+    .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
+
+    .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1),
+    .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1),
+
+    .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(13) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
+    .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c
new file mode 100644
index 0000000000000..44eb38c1f2494
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* MODE only configuration */
+const xcvr_mode_config_t msk_mode_config =
+{
+    .radio_mode = MSK,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
+
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = 0x79CDEB38,
+    .phy_pre_ref1_init = 0xCE77DFF7,
+    .phy_pre_ref2_init = 0x0000CEB7,
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(208U) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                    | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+     ,
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
+#else
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+/* MODE & DATA RATE combined configuration */
+const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config =
+{
+    .radio_mode = MSK,
+    .data_rate = DR_1MBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    /* MSK 1MBPS channel filter  @ 26MHz RF OSC */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C,
+
+    /* MSK 1MBPS channel filter  @ 32MHz RF OSC */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config =
+{
+    .radio_mode = MSK,
+    .data_rate = DR_500KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    /* MSK 500KBPS channel filter @ 26MHz RF OSC */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092,
+
+    /* MSK 500KBPS channel filter @ 32MHz RF OSC */ 
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config =
+{
+    .radio_mode = MSK,
+    .data_rate = DR_250KBPS,
+
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
+
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD,
+
+    /* MSK 250KBPS channel filter @ 32MHz RF OSC */ 
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c
new file mode 100644
index 0000000000000..32faa8bf8e5a1
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c
@@ -0,0 +1,1008 @@
+/*
+* Copyright 2016-2017 NXP
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "cpu.h"
+#include "fsl_xcvr.h"
+#include "fsl_xcvr_trim.h"
+#include "dbg_ram_capture.h"
+#include <math.h>
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a,b) \
+({ __typeof__ (a) _a = (a); \
+    __typeof__ (b) _b = (b); \
+    _a < _b ? _a : _b; })
+#endif
+
+#if !defined(MAX)
+#define MAX(a,b) \
+({ __typeof__ (a) _a = (a); \
+    __typeof__ (b) _b = (b); \
+    _a > _b ? _a : _b; })
+#endif
+/* @} */
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val);
+float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr );
+
+/*******************************************************************************
+* Variables
+******************************************************************************/
+const int8_t TsettleCal = 10;
+static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2];
+static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] =
+{
+    0, /* Baseline entry is first and not used in this table */
+    -16,
+    +16,
+    -4,
+    -4,
+    -4,
+    -4,
+    -4,
+    -4,
+    -4,
+    -4,
+    -4,
+    -4,
+    -4,
+    +4,
+    +4,
+    +4,
+    +4,
+    +4,
+    +4,
+    +4,
+    +4,
+    +4,
+    +4,
+    +4
+};
+
+/*******************************************************************************
+ * Macros
+ ******************************************************************************/
+#define ISIGN(x) !((uint16_t)x & 0x8000)
+#define ABS(x) ((x) > 0 ? (x) : -(x))
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*! *********************************************************************************
+ * \brief  This function performs a trim of the BBA DCOC DAC on the DUT
+ *
+ * \return status - 1 if passed, 0 if failed.
+ *
+ * \ingroup PublicAPIs
+ *
+ * \details
+ *   Requires the RX to be warmed up before this function is called.
+ *
+ ***********************************************************************************/
+uint8_t rx_bba_dcoc_dac_trim_shortIQ(void)
+{
+    uint8_t i;
+    float temp_mi = 0;
+    float temp_mq = 0;
+    float temp_pi = 0;
+    float temp_pq = 0;
+    float temp_step = 0;
+    uint8_t bbf_dacinit_i, bbf_dacinit_q;
+
+    uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only. */
+    uint32_t bbf_dcoc_step;
+    uint32_t bbf_dcoc_step_rcp;
+    TZAdcocstep_t tza_dcoc_step[11];
+    uint8_t status = 0;
+
+    /* Save register values. */
+    uint32_t dcoc_ctrl_0_stack;
+    uint32_t dcoc_ctrl_1_stack;
+    uint32_t agc_ctrl_1_stack;
+    uint32_t rx_dig_ctrl_stack;
+    uint32_t dcoc_cal_gain_state;
+
+    XcvrCalDelay(1000);
+    dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */
+    dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */
+    rx_dig_ctrl_stack =  XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore. */
+    agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */
+    dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore. */
+
+    /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode. */
+    XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(0); /* Turn OFF AGC */
+
+    XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) ; /* Set LNA Manual Gain */
+    XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) ; /* Set BBA Manual Gain */
+
+    XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(0); /* Enable HW DC Calibration -- Disable for SW-DCOC */
+    XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable  Manual DCOC */
+    /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode. */
+    XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) |  XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80);
+    /* Set DCOC Tracking State. */
+    XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(0); /* Disables DCOC Tracking when set to 0 */
+    /* Apply Manual Gain. */
+    XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x02) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x00) ;
+    XcvrCalDelay(TsettleCal);
+
+    dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Capture DC null setting. */
+
+    bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU);
+    bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8;
+
+    DC_Measure_short(I_CHANNEL, NOMINAL2);
+    DC_Measure_short(Q_CHANNEL, NOMINAL2);
+
+    /* SWEEP Q CHANNEL */
+    /* BBF NEG STEP */
+    XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16);
+    XcvrCalDelay(TsettleCal);
+    DC_Measure_short(Q_CHANNEL, BBF_NEG);
+
+    /* BBF POS STEP */
+    XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16);
+    XcvrCalDelay(TsettleCal);
+    DC_Measure_short(Q_CHANNEL, BBF_POS);
+
+    XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */
+    XcvrCalDelay(TsettleCal);
+
+    /* SWEEP I CHANNEL */
+    /* BBF NEG STEP */
+    XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16);
+    XcvrCalDelay(TsettleCal);
+    DC_Measure_short(I_CHANNEL, BBF_NEG);
+    /* BBF POS STEP  */
+    XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16);
+    XcvrCalDelay(TsettleCal);
+    DC_Measure_short(I_CHANNEL, BBF_POS);
+
+    XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DACs to initial. */
+    XcvrCalDelay(TsettleCal);
+
+    /* Calculate BBF DCOC STEPS, RECIPROCALS */
+    temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
+    temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
+    temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
+    temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
+
+    temp_step = (temp_mi+temp_pi + temp_mq+temp_pq) / 4;
+
+    bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U);
+
+    if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305))
+    {
+        bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step);
+
+        /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */
+        for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */
+        {
+            /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */
+            switch(i){
+            case TZA_STEP_N0:
+                temp_step = (bbf_dcoc_step >> 3U) / 3.6F;
+                break;
+            case TZA_STEP_N1:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16);
+                break;
+            case TZA_STEP_N2:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16);
+                break;
+            case TZA_STEP_N3:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16);
+                break;
+            case TZA_STEP_N4:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16);
+                break;
+            case TZA_STEP_N5:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16);
+                break;
+            case TZA_STEP_N6:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16);
+                break;
+            case TZA_STEP_N7:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16);
+                break;
+            case TZA_STEP_N8:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16);
+                break;
+            case TZA_STEP_N9:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16);
+                break;
+            case TZA_STEP_N10:
+                temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16);
+                break;
+            default:
+                break;
+            }
+
+            tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8);
+            tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step);
+        }
+
+        /* Make the trims active. */
+        XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp) ;
+        XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp) ;
+
+        status = 1; /* Success */
+    }
+    else
+    {
+        status = 0; /* Failure */
+    }
+
+    /* Restore Registers. */
+    XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */
+    XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */
+    XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings. */
+    XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting. */
+    XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */
+
+    return status;
+}
+
+/*! *********************************************************************************
+ * \brief  This function performs one point of the DC GAIN calibration process on the DUT
+ *
+ * \param[in] chan - whether the I or Q channel is being tested.
+ * \param[in] stage - whether the BBF or TZA gain stage is being tested.
+ * \param[in] dcoc_init_val - the value being set in the ***DCOC_INIT_* register by the parent.
+ * \param[in] ext_measmt - the external measurement (in milliVolts) captured by the parent after the ***DCOC_INIT_* register was setup.
+ *
+ * \ingroup PublicAPIs
+ *
+ * \details
+ *   Relies on a static array to store each point of data for later processing in ::DC_GainCalc().
+ *
+ ***********************************************************************************/
+void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val)
+{
+    int16_t dc_meas_i = 0;
+    int16_t dc_meas_q = 0;
+    int16_t sum_dc_meas_i = 0;
+    int16_t sum_dc_meas_q = 0;
+
+    {
+        int8_t i;
+        const int8_t iterations = 1;
+        sum_dc_meas_i = 0;
+        sum_dc_meas_q = 0;
+
+        for (i = 0; i < iterations; i++)
+        {
+            rx_dc_sample_average(&dc_meas_i, &dc_meas_q);
+            sum_dc_meas_i = sum_dc_meas_i + dc_meas_i;
+            sum_dc_meas_q = sum_dc_meas_q + dc_meas_q;
+        }
+        sum_dc_meas_i = sum_dc_meas_i / iterations;
+        sum_dc_meas_q = sum_dc_meas_q / iterations;
+    }
+
+    measurement_tbl2[chan][dcoc_init_val].step_value = sweep_step_values2[dcoc_init_val];
+
+    if (chan == I_CHANNEL)
+    {
+        measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_i;
+    }
+    else
+    {
+        measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q;
+    }
+}
+
+/*! *********************************************************************************
+ * \brief  This function calculates one point of DC DAC step based on digital samples of I or Q.
+ *
+ * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement.
+ * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement.
+ *
+ * \return result of the calculation, the measurement DCOC DAC step value for this measurement point.
+ *
+ ***********************************************************************************/
+float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr )
+{
+    static int16_t norm_dc_code;
+    static float dc_step;
+
+    /* Normalize internal measurement */
+    norm_dc_code = meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement;
+    dc_step = (float)(norm_dc_code) / (float)(meas_ptr->step_value);
+    dc_step = (dc_step < 0)? -dc_step: dc_step;
+
+    return dc_step;
+}
+
+/*! *********************************************************************************
+ * \brief  Temporary delay function
+ *
+ * \param[in] none.
+ *
+ * \return none.
+ *
+ * \details
+ *
+ ***********************************************************************************/
+void XcvrCalDelay(uint32_t time)
+{
+    while(time * 32 > 0) /* Time delay is roughly in uSec. */
+    {
+        time--;
+    }
+}
+
+/*! *********************************************************************************
+ * \brief  This function calculates the average (DC value) based on a smaller set of digital samples of I and Q.
+ *
+ * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples.
+ * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples.
+ *
+ ***********************************************************************************/
+void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg)
+{
+    static uint32_t samples[128]; /* 544*2*2 (entire packet ram1/2 size) */
+    uint16_t i;
+    uint32_t rx_sample;
+    uint16_t * sample_ptr;
+    uint32_t temp, end_of_rx_wu;
+    uint32_t num_iq_samples;
+    float avg_i = 0;
+    float avg_q = 0;
+
+    num_iq_samples = 128;
+
+    /* Clear the entire allocated sample buffer */
+    for (i = 0; i < num_iq_samples; i++)
+    {
+        samples[i]=0;
+    }
+
+    /* Assume this has been called *AFTER* RxWu has completed. */
+    /* XCVR_ForceRxWu(); */
+
+    /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */
+    temp = XCVR_TSM->END_OF_SEQ;
+    end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
+    while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
+
+    dbg_ram_init();
+    /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */
+#if RADIO_IS_GEN_3P0
+    dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG);
+    dbg_ram_wait_for_complete();
+    dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]);
+    dbg_ram_release();
+#else
+    (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]);
+#endif /* RADIO_IS_GEN_3P0 */
+
+    /* Sign extend the IQ samples in place in the sample buffer. */
+    sample_ptr = (uint16_t *)(&samples[0]);
+    for (i = 0; i < num_iq_samples * 2; i++)
+    {
+        rx_sample = *sample_ptr;
+        rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
+        *sample_ptr = rx_sample;
+        sample_ptr++;
+    }
+
+    sample_ptr = (uint16_t *)(&samples[0]);
+    for (i = 0; i < num_iq_samples * 2; i += 2)
+    {
+        static int16_t i_value;
+        static int16_t q_value;
+
+        /* Average I & Q channels separately. */
+        i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits. */
+        q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits. */
+        avg_i += ((float)i_value - avg_i) / (float)(i + 1);  /* Rolling average I */
+        avg_q += ((float)q_value - avg_q) / (float)(i + 1);  /* Rolling average Q */
+    }
+    XcvrCalDelay(10);
+    *i_avg = (int16_t)avg_i;
+    *q_avg = (int16_t)avg_q;
+}
+
+/*! *********************************************************************************
+ * \brief  This function calculates the average (DC value) based on a larger set of digital samples of I and Q.
+ *
+ * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples.
+ * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples.
+ *
+ ***********************************************************************************/
+void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg)
+{
+    static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */
+    uint16_t i;
+    uint32_t rx_sample;
+    uint16_t * sample_ptr;
+    uint32_t temp, end_of_rx_wu;
+    uint32_t num_iq_samples;
+    float avg_i = 0;
+    float avg_q = 0;
+
+    num_iq_samples = 512;
+
+    /* Clear the entire allocated sample buffer. */
+    for (i = 0; i < num_iq_samples; i++)
+    {
+        samples[i]=0;
+    }
+
+    /* Assume this has been called *AFTER* RxWu has completed. */
+    /* XCVR_ForceRxWu(); */
+
+    /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */
+    temp = XCVR_TSM->END_OF_SEQ;
+    end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
+    while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
+
+    dbg_ram_init();
+    /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */
+#if RADIO_IS_GEN_3P0
+    dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG);
+    dbg_ram_wait_for_complete();
+    dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ,num_iq_samples * 2 * 2, &samples[0]);
+    dbg_ram_release();
+#else
+    (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]);
+#endif /* RADIO_IS_GEN_3P0 */
+
+    /* Sign extend the IQ samples in place in the sample buffer. */
+
+    sample_ptr = (uint16_t *)(&samples[0]);
+    for (i = 0; i < num_iq_samples * 2; i++)
+    {
+        rx_sample = *sample_ptr;
+        rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
+        *sample_ptr = rx_sample;
+        sample_ptr++;
+    }
+
+    sample_ptr = (uint16_t *)(&samples[0]);
+    for (i = 0; i < num_iq_samples * 2; i += 2)
+    {
+        static int16_t i_value;
+        static int16_t q_value;
+
+        /* Average I & Q channels separately. */
+        i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits */
+        q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits */
+        avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */
+        avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */
+    }
+
+    XcvrCalDelay(10);
+    *i_avg = (int16_t)avg_i;
+    *q_avg = (int16_t)avg_q;
+}
+
+/*! *********************************************************************************
+ * rx_dc_est_average : Get DC EST values and return the Average
+ ***********************************************************************************/
+void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber)
+{
+    float avg_i = 0;
+    float avg_q = 0;
+    uint16_t i = 0;
+    static uint32_t dc_temp, temp;
+    uint32_t end_of_rx_wu = 0;
+    static int16_t dc_meas_i;
+    static int16_t dc_meas_q;
+
+     /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */
+    temp = XCVR_TSM->END_OF_SEQ;
+    end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
+    while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
+
+    /* Read DCOC DC EST register. */
+    for (i = 0; i < SampleNumber; i++)
+    {
+        dc_temp = XCVR_RX_DIG->DCOC_DC_EST;
+        dc_meas_i = dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK;
+        temp = dc_meas_i;
+        temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
+        dc_meas_i = temp;
+        avg_i += (float) dc_meas_i;
+
+        dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT;
+        temp = dc_meas_q;
+        temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
+        dc_meas_q = temp;
+        avg_q += (float) dc_meas_q;
+    }
+
+    avg_i /= (float) SampleNumber;
+    avg_q /= (float) SampleNumber;
+
+    *i_avg = (int16_t)avg_i;
+    *q_avg = (int16_t)avg_q;
+}
+
+/*! *********************************************************************************
+ * \brief  This function performs a trim of the BBA DCOC DAC on the DUT
+ *
+ * \return status - 1 if passed, 0 if failed.
+ *
+ * \ingroup PublicAPIs
+ *
+ * \details
+ *   Requires the RX to be warmed up before this function is called.
+ *
+ ***********************************************************************************/
+uint8_t rx_bba_dcoc_dac_trim_DCest(void)
+{
+    uint8_t i;
+    float temp_mi = 0;
+    float temp_mq = 0;
+    float temp_pi = 0;
+    float temp_pq = 0;
+    float temp_step = 0;
+
+    uint32_t bbf_dcoc_step;
+    uint32_t bbf_dcoc_step_rcp;
+    TZAdcocstep_t tza_dcoc_step[11];
+    uint8_t status = 0;
+
+    uint8_t bbf_dacinit_i, bbf_dacinit_q;
+    uint8_t tza_dacinit_i, tza_dacinit_q;
+    int16_t dc_meas_i;
+    int16_t dc_meas_q;
+    uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only */
+    uint32_t temp;
+
+    uint32_t dcoc_ctrl_0_stack;
+    uint32_t dcoc_ctrl_1_stack;
+    uint32_t agc_ctrl_1_stack;
+    uint32_t rx_dig_ctrl_stack;
+    uint32_t dcoc_cal_gain_state;
+
+    /* Save register */
+    dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */
+    dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */
+    rx_dig_ctrl_stack =  XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */
+    agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */
+    dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */
+
+    /* Register config */
+    /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */
+    temp = XCVR_RX_DIG->RX_DIG_CTRL;
+    temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */
+    temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */
+    temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */
+    XCVR_RX_DIG->RX_DIG_CTRL = temp;
+
+    XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */
+                              XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */
+                              XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */
+                              XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */
+
+    /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */
+    temp = XCVR_RX_DIG->DCOC_CTRL_0;
+    temp |=  XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable  Manual DCOC */
+    temp |=  XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */
+    temp |=  XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */
+    temp |=  XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */
+    XCVR_RX_DIG->DCOC_CTRL_0 = temp;
+
+    XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80);
+
+    XcvrCalDelay(TsettleCal);
+
+    /* Set default DCOC DAC INIT Value */
+    dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */
+    bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU);
+    bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8;
+    tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16;
+    tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24;
+
+    XcvrCalDelay(TsettleCal * 4);
+    rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
+    measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2];
+    measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2];
+    measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i;
+    measurement_tbl2[Q_CHANNEL][NOMINAL2].internal_measurement = dc_meas_q;
+
+    /* SWEEP I/Q CHANNEL */
+    /* BBF NEG STEP */
+    XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q);
+    XcvrCalDelay(TsettleCal * 2);
+
+    rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
+    measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16;
+    measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16;
+    measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i;
+    measurement_tbl2[Q_CHANNEL][BBF_NEG].internal_measurement = dc_meas_q;
+
+
+    /* BBF POS STEP */
+    XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q);
+    XcvrCalDelay(TsettleCal * 2);
+    rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
+    measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16;
+    measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16;
+    measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i;
+    measurement_tbl2[Q_CHANNEL][BBF_POS].internal_measurement = dc_meas_q;
+
+    XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */
+
+    /* Calculate BBF DCOC STEPS, RECIPROCALS */
+    temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
+    temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
+    temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
+    temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
+
+	temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4;
+    bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U);
+
+    if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305))
+    {
+        bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step);
+
+        /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */
+        for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++)
+        {
+            /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */
+            switch(i){
+                case TZA_STEP_N0:
+                    temp_step = (bbf_dcoc_step>>3U) / 3.6F;
+                    break;
+                case TZA_STEP_N1:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16);
+                    break;
+                case TZA_STEP_N2:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16);
+                    break;
+                case TZA_STEP_N3:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16);
+                    break;
+                case TZA_STEP_N4:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16);
+                    break;
+                case TZA_STEP_N5:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16);
+                    break;
+                case TZA_STEP_N6:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16);
+                    break;
+                case TZA_STEP_N7:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16);
+                    break;
+                case TZA_STEP_N8:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16);
+                    break;
+                case TZA_STEP_N9:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16);
+                    break;
+                case TZA_STEP_N10:
+                    temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16);
+                    break;
+                default:
+                    break;
+            }
+
+            tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8);
+            tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step);
+        }
+
+        /* Make the trims active */
+        XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp);
+        XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp);
+
+        status = 1; /* Success */
+    }
+    else
+    {
+        status = 0; /* Failure */
+    }
+
+    /* Restore Registers */
+    XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */
+    XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */
+    XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */
+    XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */
+    XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */
+
+   return status;
+}
+
+/*! *********************************************************************************
+ * DCOC_DAC_INIT_Cal : slope sign seek depending on measure's sign
+ ***********************************************************************************/
+void DCOC_DAC_INIT_Cal(uint8_t standalone_operation)
+{
+    int16_t dc_meas_i = 2000, dc_meas_i_p = 2000;
+    int16_t dc_meas_q = 2000, dc_meas_q_p = 2000;
+    uint8_t curr_tza_dac_i, curr_tza_dac_q;
+    uint8_t curr_bba_dac_i, curr_bba_dac_q;
+    uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0;
+    uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0;
+    uint8_t i = 0;
+    uint8_t bba_gain = 11;
+    bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0;
+
+    uint32_t dcoc_ctrl_0_stack;
+    uint32_t dcoc_ctrl_1_stack;
+    uint32_t agc_ctrl_1_stack;
+    uint32_t rx_dig_ctrl_stack;
+    uint32_t dcoc_cal_gain_state;
+    uint32_t xcvr_ctrl_stack = 0;
+
+    uint32_t temp;
+
+    /* Save registers */
+    dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */
+    dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */
+    rx_dig_ctrl_stack =  XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */
+    agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */
+    dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */
+
+    /* WarmUp */
+    if (standalone_operation)
+    {
+        temp = XCVR_MISC->XCVR_CTRL;
+        xcvr_ctrl_stack = temp;
+        temp &= ~(XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK);
+        temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(0);
+        XCVR_MISC->XCVR_CTRL = temp;
+        XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */
+        XCVR_ForceRxWu();
+        XcvrCalDelay(2000);
+    }
+
+    /* Register config */
+    /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */
+    temp = XCVR_RX_DIG->RX_DIG_CTRL;
+    temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */
+    temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */
+    temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */
+    XCVR_RX_DIG->RX_DIG_CTRL = temp;
+
+    XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */
+                              XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */
+                              XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */
+                              XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */
+
+    /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */
+    temp = XCVR_RX_DIG->DCOC_CTRL_0;
+    temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable  Manual DCOC */
+    temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */
+    temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */
+    temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */
+    XCVR_RX_DIG->DCOC_CTRL_0 = temp;
+
+    XcvrCalDelay(TsettleCal);
+
+    /* Set default DCOC DAC INIT Value */
+    /* LNA and BBA DAC Sweep */
+    curr_bba_dac_i = 0x20;
+    curr_bba_dac_q = 0x20;
+    curr_tza_dac_i = 0x80;
+    curr_tza_dac_q = 0x80;
+
+    /* Perform a first DC measurement to ensure that measurement is not clipping */
+    XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q);
+
+    do
+    {
+        bba_gain--;
+        /* Set DAC user gain */
+        XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) |
+                                  XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */
+                                  XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) |
+                                  XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */
+        XcvrCalDelay(TsettleCal * 2);
+        rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
+    } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900));
+
+    for (i = 0; i < 0x0F; i++)
+    {
+        /* I channel :  */
+        if (!TZA_I_OK)
+        {
+            if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0))
+            {
+                if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p)))
+                {
+                    curr_tza_dac_i = p_tza_dac_i;
+                }
+
+                TZA_I_OK = 1;
+            }
+            else
+            {
+                p_tza_dac_i = curr_tza_dac_i;
+
+                if (ISIGN(dc_meas_i)) /* If positif */
+                {
+                    curr_tza_dac_i--;
+                }
+                else
+                {
+                    curr_tza_dac_i++;
+                }
+            }
+        }
+        else /* Sweep BBA I */
+        {
+            if (!BBA_I_OK)
+            {
+                if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20))
+                {
+                    if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p)))
+                    {
+                        curr_bba_dac_i = p_bba_dac_i;
+                    }
+
+                    BBA_I_OK = 1;
+                }
+                else
+                {
+                    p_bba_dac_i = curr_bba_dac_i;
+                    if (ISIGN(dc_meas_i)) /* If positif */
+                    {
+                        curr_bba_dac_i--;
+                    }
+                    else
+                    {
+                        curr_bba_dac_i++;
+                    }
+                }
+            }
+        }
+
+        /* Q channel : */
+        if (!TZA_Q_OK)
+        {
+            if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0))
+            {
+                if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p)))
+                {
+                    curr_tza_dac_q = p_tza_dac_q;
+                }
+                TZA_Q_OK = 1;
+            }
+            else
+            {
+                p_tza_dac_q = curr_tza_dac_q;
+                if (ISIGN(dc_meas_q)) /* If positif */
+                {
+                    curr_tza_dac_q--;
+                }
+                else
+                {
+                    curr_tza_dac_q++;
+                }
+            }
+        }
+        else  /* Sweep BBA Q */
+        {
+            if (!BBA_Q_OK)
+            {
+                if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20))
+                {
+                    if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p)))
+                    {
+                        curr_bba_dac_q = p_bba_dac_q;
+                    }
+                    BBA_Q_OK = 1;
+                 }
+                 else
+                 {
+                     p_bba_dac_q = curr_bba_dac_q;
+                     if (ISIGN(dc_meas_q)) /* If positif */
+                     {
+                       curr_bba_dac_q--;
+                     }
+                     else
+                     {
+                         curr_bba_dac_q++;
+                     }
+                 }
+            }
+        }
+
+        /* DC OK break : */
+        if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK)
+        {
+            break;
+        }
+
+        dc_meas_i_p = dc_meas_i; /* Store as previous value */
+        dc_meas_q_p = dc_meas_q; /* Store as previous value */
+        XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) |
+                                     XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) |
+                                     XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) |
+                                     XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q);
+        XcvrCalDelay(TsettleCal * 2);
+        rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
+    }
+
+    /* Apply optimized DCOC DAC INIT : */
+    XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) |
+                                 XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q);
+
+    /* WarmDown */
+    if (standalone_operation)
+    {
+        XCVR_ForceRxWd(); /* Don't leave the receiver running. */
+        XcvrCalDelay(200);
+        XCVR_OverrideChannel(0xFF,1); /* Release channel overrides */
+        XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack;
+    }
+
+    /* Restore register */
+    XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */
+    XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */
+    XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */
+    XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */
+    XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */
+}
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h
new file mode 100644
index 0000000000000..eb68fb973ce13
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h
@@ -0,0 +1,129 @@
+/*
+* Copyright 2016-2017 NXP
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef _FSL_XCVR_TRIM_H_
+/* Clang-format off. */
+#define _FSL_XCVR_TRIM_H_
+/* Clang-format on. */
+
+#include <stdint.h>
+/*!
+* @addtogroup xcvr
+* @{
+*/
+
+/*! @file*/
+
+/************************************************************************************
+*************************************************************************************
+* Public constant definitions
+*************************************************************************************
+************************************************************************************/
+
+/************************************************************************************
+*************************************************************************************
+* Public type definitions
+*************************************************************************************
+************************************************************************************/
+
+/* \brief  The enumerations used to define the I & Q channel selections. */
+typedef enum
+{
+    I_CHANNEL = 0,
+    Q_CHANNEL = 1,
+    NUM_I_Q_CHAN = 2
+} IQ_t;
+
+typedef enum /* Enumeration of ADC_GAIN_CAL 2 */
+{
+    NOMINAL2 = 0,
+    BBF_NEG = 1,
+    BBF_POS = 2,
+    TZA_STEP_N0 = 3,
+    TZA_STEP_N1 = 4,
+    TZA_STEP_N2 = 5,
+    TZA_STEP_N3 = 6,
+    TZA_STEP_N4 = 7,
+    TZA_STEP_N5 = 8,
+    TZA_STEP_N6 = 9,
+    TZA_STEP_N7 = 10,
+    TZA_STEP_N8 = 11,
+    TZA_STEP_N9 = 12,
+    TZA_STEP_N10 = 13,
+    TZA_STEP_P0 = 14,
+    TZA_STEP_P1 = 15,
+    TZA_STEP_P2 = 16,
+    TZA_STEP_P3 = 17,
+    TZA_STEP_P4 = 18,
+    TZA_STEP_P5 = 19,
+    TZA_STEP_P6 = 20,
+    TZA_STEP_P7 = 21,
+    TZA_STEP_P8 = 22,
+    TZA_STEP_P9 = 23,
+    TZA_STEP_P10 = 24,
+
+    NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */
+} DAC_SWEEP_STEP2_t;
+
+/* \brief  Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */
+typedef struct
+{
+    uint16_t dcoc_step;
+    uint16_t dcoc_step_rcp;
+//    uint16_t dcoc_step_q;
+//    uint16_t dcoc_step_rcp_q;
+} TZAdcocstep_t;
+
+typedef struct
+{
+    int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */
+    int16_t internal_measurement; /* The value (average code) measured from DMA samples. */
+//    uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */
+} GAIN_CALC_TBL_ENTRY2_T;
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg);
+void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg);
+uint8_t rx_bba_dcoc_dac_trim_shortIQ(void);
+void XcvrCalDelay(uint32_t time);
+void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber);
+uint8_t rx_bba_dcoc_dac_trim_DCest(void);
+void DCOC_DAC_INIT_Cal(uint8_t standalone_operation);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_XCVR_TRIM_H_ */
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c
new file mode 100644
index 0000000000000..47d6f5f0573c7
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_xcvr.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+const xcvr_mode_config_t zgbe_mode_config =
+{
+    .radio_mode = ZIGBEE_MODE,
+    .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK,
+
+    /* XCVR_MISC configs */
+    .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
+    .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) |
+                      XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
+                      XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2),
+
+    /* XCVR_PHY configs */
+    .phy_pre_ref0_init = 0x0, /* Not used in Zigbee */
+    .phy_pre_ref1_init = 0x0, /* Not used in Zigbee */
+    .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */
+
+    .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
+                     XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 
+                     XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
+                     XCVR_PHY_CFG1_BSM_EN_BLE(0) |
+                     XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
+                     XCVR_PHY_CFG1_CTS_THRESH(0xC0) |
+                     XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
+
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
+#if !RADIO_IS_GEN_2P1
+                    | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
+#endif /* !RADIO_IS_GEN_2P1 */
+    ,
+
+    /* XCVR_PLL_DIG configs */
+
+    /* XCVR_RX_DIG configs */
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
+
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
+
+    .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
+    /* XCVR_TSM configs */
+#if (DATA_PADDING_EN)
+    .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ 
+#else
+    .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT),
+#endif /* (DATA_PADDING_EN) */
+
+    /* XCVR_TX_DIG configs */
+    .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
+                    XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) ,
+    .tx_gfsk_coeff1_26mhz = 0,
+    .tx_gfsk_coeff2_26mhz = 0,
+    .tx_gfsk_coeff1_32mhz = 0,
+    .tx_gfsk_coeff2_32mhz = 0,
+};
+
+const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config =
+{
+    .radio_mode = ZIGBEE_MODE,
+    .data_rate = DR_500KBPS,
+    
+    .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
+    .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */
+
+    .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
+    .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ 
+    .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
+    .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ 
+
+    .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
+                     XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
+                       
+    /* AGC configs */
+    .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+    .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
+                             XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) |
+                             XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
+
+    /* All constant values are represented as 16 bits, register writes will remove unused bits */
+    .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075,
+    .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2,
+
+     /* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */
+    .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040,
+    .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124,
+
+    .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
+    .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
+                       XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
+
+    .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
+    .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
+};
+
+/* CUSTOM datarate dependent config structure for ONLY 802.15.4 */
+/*!
+ * @brief  XCVR 500K bps DATA RATE specific configure structure
+ */
+const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config =
+{
+    .data_rate = DR_500KBPS,
+    .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
+                       XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) |
+                       XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) ,
+    .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+    .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) |
+                              XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
+
+    .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+    .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) |
+                             XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
+
+    .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29),
+    .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) |
+                              XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47),
+
+    .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
+
+    .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
+                              XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
+
+    .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
+    .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
+                               XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1),
+
+    .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
+    .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) |
+                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0),
+};
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c
new file mode 100644
index 0000000000000..2732fd19dadb0
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c
@@ -0,0 +1,530 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu.h"
+#include "fsl_xcvr.h"
+#include "ifr_radio.h"
+#include "fsl_os_abstraction.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define IFR_RAM             (0)
+
+#if RADIO_IS_GEN_3P0
+#define RDINDX              (0x41U)
+#define K3_BASE_INDEX       (0x11U) /* Based for read index */
+#else
+#define RDRSRC              (0x03U)
+#define KW4x_512_BASE       (0x20000U)
+#define KW4x_256_BASE       (0x10000U)
+#endif /* RADIO_IS_GEN_3P0 */
+
+#if RADIO_IS_GEN_2P1
+#define FTFA    (FTFE)
+#endif /* RADIO_IS_GEN_2P1 */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+uint32_t read_another_ifr_word(void);
+uint32_t read_first_ifr_word(uint32_t read_addr);
+
+#if RADIO_IS_GEN_3P0
+uint64_t read_index_ifr(uint32_t read_addr);
+#else
+/*! *********************************************************************************
+ * @brief  Reads a location in block 1 IFR for use by the radio.
+ *
+ * This function handles reading IFR data from flash memory for trim loading.
+ *
+ * @param read_addr the address in the IFR to be read.
+ *
+ * @details This function wraps both the Gen2 read_resource command and the Gen2.1 and Gen3 read_index
+***********************************************************************************/
+#if RADIO_IS_GEN_2P1
+uint64_t read_resource_ifr(uint32_t read_addr);
+#else
+uint32_t read_resource_ifr(uint32_t read_addr);
+#endif /* RADIO_IS_GEN_2P1 */
+#endif /* RADIO_IS_GEN_3P0 */
+
+void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static uint32_t ifr_read_addr;
+
+#if RADIO_IS_GEN_3P0
+static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */
+static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */
+const uint32_t BLOCK_1_IFR[]=
+{
+    /* Revised fallback table which should work with untrimmed parts */
+    0xABCDFFFEU, /* Version #FFFE indicates default trim values */
+
+    /* Trim table is empty for Gen3 by default */
+
+    /* No TRIM_STATUS in SW fallback array. */
+    0xFEED0E0FU /* End of File */
+};
+#else
+#if RADIO_IS_GEN_2P0
+const uint32_t BLOCK_1_IFR[]=
+{
+    /* Revised fallback table which should work with untrimmed parts */
+    0xABCDFFFEU, /* Version #FFFE indicates default trim values */
+
+    0x4005912CU, /* RSIM_ANA_TRIM address */
+    0x784B0000U, /* RSIM_ANA_TRIM default value */
+
+    /* No TRIM_STATUS in SW fallback array. */
+    0xFEED0E0FU /* End of File */
+};
+#else
+static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */
+static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */
+const uint32_t BLOCK_1_IFR[]=
+{
+    /* Revised fallback table which should work with untrimmed parts */
+    0xABCDFFFEU, /* Version #FFFE indicates default trim values */
+
+    0x4005912CU, /* RSIM_ANA_TRIM address */
+    0x784B0000U, /* RSIM_ANA_TRIM default value */
+
+    /* No TRIM_STATUS in SW fallback array. */
+    0xFEED0E0FU /* End of File */
+};
+#endif /* RADIO_IS_GEN_2P0 */
+#endif /* RADIO_IS_GEN_3P0 */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*! *********************************************************************************
+ * \brief  Read command for reading the first 32bit word from IFR, encapsulates different
+ *  flash IFR read mechanisms for multiple generations of SOC
+ *
+ * \param read_addr flash address
+ *
+ * \return 8 bytes of packed data containing radio trims only
+ *
+***********************************************************************************/
+uint32_t read_first_ifr_word(uint32_t read_addr)
+{
+    ifr_read_addr = read_addr;
+    return read_another_ifr_word();
+}
+
+/*! *********************************************************************************
+ * \brief  Read command for reading additional 32bit words from IFR. Encapsulates multiple IFR read mechanisms.
+ *
+ * \param read_addr flash address
+ *
+ * \return 8 bytes of packed data containing radio trims only
+ *
+ * \remarks PRE-CONDITIONS:
+ *  The function read_first_ifr_word() must have been called so that the ifr_read_addr variable is setup prior to use.
+ *
+***********************************************************************************/
+uint32_t read_another_ifr_word(void)
+{
+    uint32_t packed_data;
+
+#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1)
+    /* Using some static storage and alternating reads to read_index_ifr to replace read_resource_ifr */
+    if (num_words_avail == 0)
+    {
+#if RADIO_IS_GEN_3P0
+        packed_data_long = read_index_ifr(ifr_read_addr);
+#else /* Use 64 bit return version of read_resource */
+        packed_data_long = read_resource_ifr(ifr_read_addr);
+#endif /* RADIO_IS_GEN_3P0 */
+
+        num_words_avail = 2;
+        ifr_read_addr++; /* Read index addresses increment by 1 */
+    }
+
+    packed_data = (uint32_t)(packed_data_long & 0xFFFFFFFF);
+    packed_data_long = packed_data_long >> 32;
+    num_words_avail--;
+#else
+    packed_data = read_resource_ifr(ifr_read_addr);
+    ifr_read_addr += 4; /* Read resource addresses increment by 4 */
+#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */
+
+    return packed_data;
+}
+
+#if RADIO_IS_GEN_3P0
+/*! *********************************************************************************
+ * \brief  Read command for reading from IFR using RDINDEX command
+ *
+ * \param read_addr flash address
+ *
+ * \return 8 bytes of packed data containing radio trims only
+ *
+***********************************************************************************/
+uint64_t read_index_ifr(uint32_t read_addr)
+{
+    uint8_t rdindex = read_addr;
+    uint64_t read_data;
+    uint8_t i;
+
+    while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */
+
+    if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK )
+    {
+        FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
+    }
+
+    FTFE->FCCOB[0] = RDINDX;
+    FTFE->FCCOB[1] = rdindex;
+
+    OSA_InterrupDisable();
+    FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK;
+    while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
+    OSA_InterruptEnable();
+
+    /* Pack read data back into 64 bit type */
+    read_data = FTFE->FCCOB[11]; /* MSB goes in first, will be shifted left sequentially */
+    for (i = 10; i > 3; i--)
+    {
+        read_data = read_data << 8;
+        read_data |= FTFE->FCCOB[i];
+    }
+
+    return read_data;
+}
+#else
+
+/*! *********************************************************************************
+ * \brief  Read command for reading from IFR
+ *
+ * \param read_addr flash address
+ *
+ * \return packed data containing radio trims only
+ *
+***********************************************************************************/
+#if RADIO_IS_GEN_2P0
+uint32_t read_resource_ifr(uint32_t read_addr)
+{
+
+    uint32_t packed_data;
+    uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0;
+    uint32_t read_data31_24, read_data23_16, read_data15_8, read_data7_0;
+
+    flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16);
+    flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8);
+    flash_addr7_0 = (uint8_t)(read_addr & 0xFF);
+
+    while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */
+
+    if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK) == FTFA_FSTAT_ACCERR_MASK )
+    {
+        FTFA->FSTAT = (1<<FTFA_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
+    }
+
+    FTFA->FCCOB0 = RDRSRC;
+    FTFA->FCCOB1 = flash_addr23_16;
+    FTFA->FCCOB2 = flash_addr15_8;
+    FTFA->FCCOB3 = flash_addr7_0;
+    FTFA->FCCOB8 = 0x00;
+
+    OSA_InterruptDisable();
+    FTFA->FSTAT = FTFA_FSTAT_CCIF_MASK;
+    while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */
+    OSA_InterruptEnable();
+
+    /* Start reading */
+    read_data31_24 = FTFA->FCCOB4; /* FTFA->FCCOB[4] */
+    read_data23_16 = FTFA->FCCOB5; /* FTFA->FCCOB[5] */
+    read_data15_8  = FTFA->FCCOB6; /* FTFA->FCCOB[6] */
+    read_data7_0   = FTFA->FCCOB7; /* FTFA->FCCOB[7] */
+
+    packed_data = (read_data31_24 << 24) | (read_data23_16 << 16) | (read_data15_8 << 8) | (read_data7_0 << 0);
+
+    return packed_data;
+}
+#else
+uint64_t read_resource_ifr(uint32_t read_addr)
+{
+
+    uint64_t packed_data;
+    uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0;
+    uint8_t read_data[8];
+    uint64_t temp_64;
+    uint8_t i;
+
+    flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16);
+    flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8);
+    flash_addr7_0 = (uint8_t)(read_addr & 0xFF);
+    while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
+
+    if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK )
+    {
+        FTFE->FSTAT = (1<<FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
+    }
+
+    FTFE->FCCOB0 = RDRSRC;
+    FTFE->FCCOB1 = flash_addr23_16;
+    FTFE->FCCOB2 = flash_addr15_8;
+    FTFE->FCCOB3 = flash_addr7_0;
+    FTFE->FCCOB4 = 0x00;
+
+    OSA_InterruptDisable();
+    FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK;
+    while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
+    OSA_InterruptEnable();
+
+    /* Start reading */
+    read_data[7] = FTFE->FCCOB4;
+    read_data[6] = FTFE->FCCOB5;
+    read_data[5] = FTFE->FCCOB6;
+    read_data[4] = FTFE->FCCOB7;
+    read_data[3] = FTFE->FCCOB8;
+    read_data[2] = FTFE->FCCOB9;
+    read_data[1] = FTFE->FCCOBA;
+    read_data[0] = FTFE->FCCOBB;
+
+    packed_data = 0;
+    for (i = 0; i < 8; i++)
+    {
+        temp_64 = read_data[i];
+        packed_data |= temp_64 << (i * 8);
+    }
+
+    return packed_data;
+}
+
+#endif /* RADIO_IS_GEN_2P0 */
+#endif /* RADIO_IS_GEN_3P0 */
+
+/*! *********************************************************************************
+ * \brief  Store a SW trim value in the table passed in from calling function.
+ *
+ * \param sw_trim_tbl pointer to the software trim table to hold SW trim values
+ * \param num_entries the number of entries in the SW trim table
+ * \param addr the software trim ID
+ * \param data the value of the software trim
+ *
+***********************************************************************************/
+void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data)
+{
+    uint16_t i;
+
+    if (sw_trim_tbl != NULL)
+    {
+        for (i = 0; i < num_entries; i++)
+        {
+            if (addr == sw_trim_tbl[i].trim_id)
+            {
+                sw_trim_tbl[i].trim_value = data;
+                sw_trim_tbl[i].valid = 1;
+                break; /* Don't need to scan the array any further... */
+            }
+        }
+    }
+}
+
+/*! *********************************************************************************
+ * \brief  Process block 1 IFR data.
+ *
+ * \param sw_trim_tbl pointer to the software trim table to hold SW trim values
+ * \param num_entries the number of entries in the SW trim table
+ *
+ * \remarks
+ *  Uses a IFR v2 formatted default array if the IFR is blank or corrupted.
+ *  Stores SW trim values to an array passed into this function.
+ *
+***********************************************************************************/
+void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries)
+{
+    uint32_t dest_addr;
+    uint32_t read_addr;
+    uint32_t dest_data;
+    uint32_t packed_data;
+    uint32_t *ifr_ptr;
+
+#if RADIO_IS_GEN_3P0
+    num_words_avail = 0; /* Prep for handling 64 bit words from flash */
+#endif /* RADIO_IS_GEN_3P0 */
+
+#if RADIO_IS_GEN_3P0
+    read_addr = K3_BASE_INDEX;
+#else
+#ifdef CPU_MODEL_MKW41Z256VHT4
+    read_addr = KW4x_256_BASE;
+#else
+    read_addr = KW4x_512_BASE;
+#endif /* CPU_MODEL_MKW41Z256VHT4 */
+#endif /* RADIO_IS_GEN_3P0 */
+
+    /* Read first entry in IFR table */
+    packed_data = read_first_ifr_word(read_addr);
+    if ((packed_data&~IFR_VERSION_MASK) == IFR_VERSION_HDR)
+    {
+        /* Valid header was found, process real IFR data */
+        XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK);
+        store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array*/
+        packed_data = read_another_ifr_word();
+
+        while (packed_data !=IFR_EOF_SYMBOL)
+        {
+            if (IS_A_SW_ID(packed_data)) /* SW Trim case (non_reg writes) */
+            {
+                dest_addr = packed_data;
+                packed_data = read_another_ifr_word();
+                dest_data = packed_data;
+                /* Place SW trim in array for driver SW to use */
+                store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data);
+            }
+            else
+            {
+                if (IS_VALID_REG_ADDR(packed_data)) /* Valid register write address */
+                {
+                    dest_addr = packed_data;
+                    packed_data = read_another_ifr_word();
+                    dest_data = packed_data;
+                    *(uint32_t *)(dest_addr) = dest_data;
+                }
+                else
+                { /* Invalid address case */
+
+                }
+            }
+
+        packed_data=read_another_ifr_word();
+        }
+    }
+    else
+    {
+        /* Valid header is not present, use blind IFR trim table */
+        ifr_ptr = (void *)BLOCK_1_IFR;
+        packed_data = *ifr_ptr;
+        XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK);
+        store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array */
+        ifr_ptr++;
+        packed_data= *ifr_ptr;
+
+        while (packed_data != IFR_EOF_SYMBOL)
+        {
+            if (IS_A_SW_ID(packed_data))
+            {
+                /* SW Trim case (non_reg writes) */
+                dest_addr = packed_data;
+                ifr_ptr++;
+                packed_data = *(ifr_ptr);
+                dest_data = packed_data;
+                /* Place SW trim in array for driver SW to use */
+                store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data);
+            }
+            else
+            {
+                dest_addr = packed_data;
+                ifr_ptr++;
+                packed_data = *ifr_ptr;
+                dest_data = packed_data;
+
+                /* Valid register write address */
+                if (IS_VALID_REG_ADDR(dest_addr))
+                {
+                    *(uint32_t *)(dest_addr) = dest_data;
+                }
+                else
+                {
+                    /* Invalid address case */
+                }
+            }
+
+            ifr_ptr++;
+            packed_data= *ifr_ptr;
+        }
+    }
+}
+
+#if RADIO_IS_GEN_3P0
+
+#else
+uint32_t handle_ifr_die_id(void)
+{
+    uint32_t id_x, id_y;
+    uint32_t id;
+
+    id = read_resource_ifr(0x90);
+    id_x = id & 0x00FF0000;
+    id_y = id & 0x000000FF;
+
+    return (id_x | id_y);
+}
+
+uint32_t handle_ifr_die_kw_type(void)
+{
+    uint32_t zb, ble;
+
+    zb = read_resource_ifr(0x80) & 0x8000;
+    ble= read_resource_ifr(0x88) & 0x100000;
+
+    return (zb | ble);
+}
+
+#endif /* RADIO_IS_GEN_3P0 */
+
+/*! *********************************************************************************
+ * \brief  Dumps block 1 IFR data to an array.
+ *
+ * \param dump_tbl pointer to the table to hold the dumped IFR values
+ * \param num_entries the number of entries to dump
+ *
+ * \remarks
+ *  Starts at the first address in IFR and dumps sequential entries.
+ *
+***********************************************************************************/
+void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries)
+{
+#if RADIO_IS_GEN_3P0
+    uint32_t ifr_address = 0x20000;
+#else
+    uint32_t ifr_address = 0x20000;
+#endif /* RADIO_IS_GEN_3P0 */
+    uint32_t * dump_ptr = dump_tbl;
+    uint8_t i;
+
+    *dump_ptr = read_first_ifr_word(ifr_address);
+    dump_ptr++;
+
+    for (i = 0; i < num_entries - 1; i++)
+    {
+        *dump_ptr = read_another_ifr_word();
+        dump_ptr++;
+    }
+}
+
diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h
new file mode 100644
index 0000000000000..96973de715035
--- /dev/null
+++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __IFR_RADIO_H__
+/* clang-format off */
+#define __IFR_RADIO_H__
+/* clang-format on */
+
+#include <stdint.h>
+/* clang-format off */
+#define _FSL_XCVR_H_
+/* clang-format on */
+
+/*!
+ * @addtogroup xcvr
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define IFR_EOF_SYMBOL          (0xFEED0E0FU) /* < Denotes the "End of File" for IFR data */
+#define IFR_VERSION_HDR         (0xABCD0000U) /* < Constant value for upper 16 bits of IFR data header */
+#define IFR_VERSION_MASK        (0x0000FFFFU) /* < Mask for version number (lower 16 bits) of IFR data header */
+#define IFR_SW_ID_MIN           (0x00000000U) /* < Lower limit of SW trim IDs */
+#define IFR_SW_ID_MAX           (0x0000FFFFU) /* < Lower limit of SW trim IDs */
+
+#define IS_A_SW_ID(x)           ((IFR_SW_ID_MIN < (x)) && (IFR_SW_ID_MAX >= (x)))
+
+/* K3 valid registers support */
+#if (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P))
+#define IS_VALID_REG_ADDR(x)    (((x) & 0xFFFF0000U) == 0x41000000U) /* Valid addresses are 0x410xxxxx */
+#endif /* (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) */
+/* KW41 and KW35/36 valid registers support */
+#if (defined(CPU_MODEL_MKW41Z256VHT4) || defined(CPU_MODEL_MKW41Z512VHT4) || \
+     defined(CPU_MODEL_MKW31Z256VHT4) || defined(CPU_MODEL_MKW31Z512VHT4) || \
+     defined(CPU_MODEL_MKW21Z256VHT4) || defined(CPU_MODEL_MKW21Z512VHT4) || \
+     defined(CPU_MODEL_MKW35A512VFP4) || defined(CPU_MODEL_MKW36A512VFP4) )
+
+#define IS_VALID_REG_ADDR(x)    (((x) & 0xFFFF0000U) == 0x40050000U) /* Valid addresses are 0x4005xxxx */
+#endif
+
+#define MAKE_MASK(size)         ((1 << (size)) - 1)
+#define MAKE_MASKSHFT(size, bitpos)  (MAKE_MASK(size) << (bitpos))
+
+#define IFR_TZA_CAP_TUNE_MASK           (0x0000000FU)
+#define IFR_TZA_CAP_TUNE_SHIFT          (0)
+#define IFR_BBF_CAP_TUNE_MASK           (0x000F0000U)
+#define IFR_BBF_CAP_TUNE_SHIFT          (16)
+#define IFR_RES_TUNE2_MASK              (0x00F00000U)
+#define IFR_RES_TUNE2_SHIFT             (20)
+
+/* \var  typedef uint8_t IFR_ERROR_T */
+/* \brief  The IFR error reporting type. */
+/* See #IFR_ERROR_T_enum for the enumeration definitions. */
+typedef uint8_t IFR_ERROR_T;
+
+/* \brief  The enumerations used to describe IFR errors. */
+enum IFR_ERROR_T_enum
+{
+    IFR_SUCCESS = 0,
+    INVALID_POINTER = 1, /* < NULL pointer error */
+    INVALID_DEST_SIZE_SHIFT = 2, /* < the bits won't fit as specified in the destination */
+};
+
+/* \var  typedef uint16_t SW_TRIM_ID_T */
+/* \brief  The SW trim ID type. */
+/* See #SW_TRIM_ID_T_enum for the enumeration definitions. */
+typedef uint16_t SW_TRIM_ID_T;
+
+/* \brief  The enumerations used to define SW trim IDs. */
+enum SW_TRIM_ID_T_enum
+{
+    Q_RELATIVE_GAIN_BY_PART = 0, /* < Q vs I relative gain trim ID */
+    ADC_GAIN = 1, /* < ADC gain trim ID */
+    ZB_FILT_TRIM = 2, /* < Baseband Bandwidth filter trim ID for BLE */
+    BLE_FILT_TRIM = 3, /* < Baseband Bandwidth filter trim ID for BLE */
+    TRIM_STATUS = 4, /* < Status result of the trim process (error indications) */
+    TRIM_VERSION = 0xABCD, /* < Version number of the IFR trim algorithm/format. */
+};
+
+/* \var  typedef uint32_t IFR_TRIM_STATUS_T */
+/* \brief  The definition of failure bits stored in IFR trim status word. */
+/* See #IFR_TRIM_STATUS_T_enum for the enumeration definitions. */
+typedef uint32_t IFR_TRIM_STATUS_T;
+
+/* \brief  The enumerations used to describe trim algorithm failures in the status entry in IFR. */
+/* This enum represents multiple values which can be OR'd together in a single status word. */
+enum IFR_TRIM_STATUS_T_enum
+{
+    TRIM_ALGORITHM_SUCCESS = 0,
+    BGAP_VOLTAGE_TRIM_FAILED = 1, /* < algorithm failure in BGAP voltagetrim */
+    IQMC_GAIN_ADJ_FAILED = 2, /* < algorithm failure in IQMC gain trim */
+    IQMC_PHASE_ADJ_FAILED = 4, /* < algorithm failure in IQMC phase trim */
+    IQMC_DC_GAIN_ADJ_FAILED = 8, /* < */
+    ADC_GAIN_TRIM_FAILED = 10, /* <*/
+    ZB_FILT_TRIM_FAILED = 20, /* < */
+    BLE_FILT_TRIM_FAILED = 40, /* < */
+};
+
+/* \var  typedef struct IFR_SW_TRIM_TBL_ENTRY_T */
+/* \brief  Structure defining an entry in a table used to contain values to be passed back from IFR */
+/*  handling routine to XCVR driver software. */
+typedef struct
+{
+    SW_TRIM_ID_T trim_id; /* < The assigned ID */
+    uint32_t trim_value; /* < The value fetched from IFR.*/
+    uint8_t valid; /* < validity of the trim_value field after IFR processing is complete (TRUE/FALSE).*/
+} IFR_SW_TRIM_TBL_ENTRY_T;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @brief Reads a location in block 1 IFR for use by the radio.
+ *
+ * This function handles reading IFR data from flash memory for trim loading.
+ *
+ * @param read_addr the address in the IFR to be read.
+ */
+uint32_t read_resource_ifr(uint32_t read_addr);
+
+/*!
+ * @brief Reads a location in a simulated data array to support IFR handler testing.
+ *
+ * This function handles reading  data from a const table for testing the trim loading functions.
+ *
+ * @param read_addr the address in the IFR to be read.
+ */
+uint32_t read_resource(uint16_t resource_id);
+
+/*!
+ * @brief Main IFR handler function called by XCVR driver software to process trim table.
+ *
+ * This function handles reading  data from IFR and either loading to registers or storing to a SW trim values table.
+ *
+ * @param sw_trim_tbl pointer to the table used to store software trim values.
+ * @param num_entries the number of entries that can be stored in the SW trim table.
+ */
+void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries);
+
+/*!
+ * @brief Handler function to read die_id from IFR locations..
+ *
+ * This function handles reading die ID value for debug and testing usage.
+ *
+ * @return the value of the die ID field.
+ */
+uint32_t handle_ifr_die_id(void);
+
+/*!
+ * @brief Handler function to read KW chip version from IFR locations..
+ *
+ * This function handles reading KW chip version for debug and testing usage.
+ *
+ * @return the value of the KW version field.
+ */
+uint32_t handle_ifr_die_kw_type(void);
+
+/*!
+ * @brief Debug function to dump the IFR contents to a RAM array.
+ *
+ * This function handles reading  data from IFR and storing to a RAM array for debug.
+ *
+ * @param dump_tbl pointer to the table used to store IFR entry values.
+ * @param num_entries the number of entries that can be stored in the dump table.
+ */
+void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries);
+
+#endif /*__IFR_RADIO_H__ */
+
diff --git a/drivers/Makefile.dep b/drivers/Makefile.dep
index 4813af1e70c93..a49a99b632e63 100644
--- a/drivers/Makefile.dep
+++ b/drivers/Makefile.dep
@@ -129,6 +129,18 @@ ifneq (,$(filter kw2xrf,$(USEMODULE)))
     endif
 endif
 
+ifneq (,$(filter kw41zrf,$(USEMODULE)))
+    USEMODULE += luid
+    USEMODULE += netif
+    USEMODULE += ieee802154
+    USEMODULE += netdev_ieee802154
+    ifneq (,$(filter gnrc_netdev_default,$(USEMODULE)))
+      # XXX: this can be modeled as a dependency for gnrc_netdev_default as soon
+      # as all drivers are ported to netdev
+      USEMODULE += gnrc_netdev
+    endif
+endif
+
 ifneq (,$(filter hd44780,$(USEMODULE)))
     FEATURES_REQUIRED += periph_gpio
     USEMODULE += xtimer
diff --git a/drivers/Makefile.include b/drivers/Makefile.include
index 5ad17a4c32560..77067ecb1f9f8 100644
--- a/drivers/Makefile.include
+++ b/drivers/Makefile.include
@@ -13,6 +13,9 @@ endif
 ifneq (,$(filter kw2xrf,$(USEMODULE)))
     USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw2xrf/include
 endif
+ifneq (,$(filter kw41zrf,$(USEMODULE)))
+    USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw41zrf/include
+endif
 ifneq (,$(filter io1_xplained,$(USEMODULE)))
     USEMODULE_INCLUDES += $(RIOTBASE)/drivers/io1_xplained/include
 endif
diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h
new file mode 100644
index 0000000000000..1ad58280e92f4
--- /dev/null
+++ b/drivers/include/kw41zrf.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup    drivers_kw41zrf KW41Z radio-driver
+ * @ingroup     drivers_netdev
+ * @brief       Device driver for the NXP KW41Z, KW21Z in-cpu transceiver
+ * @{
+ *
+ * @file
+ * @brief       Interface definition for the kw41zrf driver
+ *
+ * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ */
+
+#ifndef KW41ZRF_H
+#define KW41ZRF_H
+
+#include <stdint.h>
+
+#include "board.h"
+#include "periph/spi.h"
+#include "periph/gpio.h"
+#include "net/netdev.h"
+#include "net/netdev/ieee802154.h"
+#include "net/gnrc/nettype.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   Maximum packet length
+ */
+#define KW41ZRF_MAX_PKT_LENGTH           (IEEE802154_FRAME_LEN_MAX)
+
+/**
+ * @brief   Default PAN ID used after initialization
+ */
+#define KW41ZRF_DEFAULT_PANID            (IEEE802154_DEFAULT_PANID)
+
+/**
+ * @brief   Default channel used after initialization
+ *
+ * @{
+ */
+#ifndef KW41ZRF_DEFAULT_CHANNEL
+#define KW41ZRF_DEFAULT_CHANNEL          (IEEE802154_DEFAULT_CHANNEL)
+#endif
+/** @} */
+
+/**
+ * @brief   Allowed range of channels
+ *
+ * @{
+ */
+#define KW41ZRF_MIN_CHANNEL              (11U)
+#define KW41ZRF_MAX_CHANNEL              (26U)
+/** @} */
+
+/**
+ * @brief   Default TX_POWER in dbm used after initialization
+ */
+#define KW41ZRF_DEFAULT_TX_POWER         (IEEE802154_DEFAULT_TXPOWER)
+
+/**
+ * @brief   Maximum output power of the kw41z device in dBm
+ */
+#define KW41ZRF_OUTPUT_POWER_MAX       (2)
+
+/**
+ * @brief   Minimum output power of the kw41z device in dBm
+ */
+#define KW41ZRF_OUTPUT_POWER_MIN       (-19)
+
+/**
+ * @brief   Internal device option flags
+ *
+ * `0x00ff` is reserved for general IEEE 802.15.4 flags
+ * (see @ref netdev_ieee802154_t)
+ *
+ * @{
+ */
+#define KW41ZRF_OPT_SRC_ADDR_LONG    (NETDEV_IEEE802154_SRC_MODE_LONG)  /**< legacy define */
+#define KW41ZRF_OPT_RAWDUMP          (NETDEV_IEEE802154_RAW)            /**< legacy define */
+#define KW41ZRF_OPT_ACK_REQ          (NETDEV_IEEE802154_ACK_REQ)        /**< legacy define */
+
+#define KW41ZRF_OPT_AUTOCCA        (0x0100) /**< CCA before TX active */
+#define KW41ZRF_OPT_PROMISCUOUS    (0x0200) /**< promiscuous mode active */
+#define KW41ZRF_OPT_PRELOADING     (0x0400) /**< preloading enabled */
+#define KW41ZRF_OPT_TELL_TX_START  (0x0800) /**< notify MAC layer on TX start */
+#define KW41ZRF_OPT_TELL_TX_END    (0x1000) /**< notify MAC layer on TX finished */
+#define KW41ZRF_OPT_TELL_RX_START  (0x2000) /**< notify MAC layer on RX start */
+#define KW41ZRF_OPT_TELL_RX_END    (0x4000) /**< notify MAC layer on RX finished */
+#define KW41ZRF_OPT_AUTOACK        (0x8000) /**< enable automatic sending of
+                                             *   ACKs for incoming packet */
+/** @} */
+
+/**
+ * @brief   Device descriptor for KW41ZRF radio devices
+ *
+ * @extends netdev_ieee802154_t
+ */
+typedef struct {
+    netdev_ieee802154_t netdev; /**< netdev parent struct */
+    /**
+     * @brief   device specific fields
+     * @{
+     */
+    uint32_t tx_warmup_time;    /**< TX warmup time, in event timer ticks */
+    uint32_t rx_warmup_time;    /**< RX warmup time, in event timer ticks */
+    int16_t tx_power;           /**< The current tx-power setting of the device */
+    uint8_t state;              /**< current state of the radio */
+    uint8_t idle_state;         /**< state to return to after sending */
+    /** @} */
+} kw41zrf_t;
+
+/**
+ * @brief   Setup an KW41ZRF based device state
+ *
+ * @param[out] dev          device descriptor
+ * @param[in]  params       parameters for device initialization
+ */
+void kw41zrf_setup(kw41zrf_t *dev);
+
+/**
+ * @brief   Initialize the given KW41ZRF device
+ *
+ * @param[out] dev          device descriptor
+ * @param[in] cb            irq callback
+ *
+ * @return                  0 on success
+ * @return                  <0 on error
+ */
+int kw41zrf_init(kw41zrf_t *dev, gpio_cb_t cb);
+
+/**
+ * @brief   Configure radio with default values
+ *
+ * @param[in] dev           device to reset
+ */
+void kw41zrf_reset_phy(kw41zrf_t *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* KW41ZRF_H */
+/** @} */
diff --git a/drivers/kw41zrf/Makefile b/drivers/kw41zrf/Makefile
new file mode 100644
index 0000000000000..48422e909a47d
--- /dev/null
+++ b/drivers/kw41zrf/Makefile
@@ -0,0 +1 @@
+include $(RIOTBASE)/Makefile.base
diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h
new file mode 100644
index 0000000000000..dff93632a9d30
--- /dev/null
+++ b/drivers/kw41zrf/include/kw41zrf_getset.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ * Copyright (C) 2016 Phytec Messtechnik GmbH
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     drivers_kw41zrf
+ * @{
+ *
+ * @file
+ * @brief       get/set interfaces for kw41zrf driver
+ *
+ * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ */
+
+#ifndef KW41ZRF_GETSET_H
+#define KW41ZRF_GETSET_H
+
+#include "kw41zrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief Transceiver sequence identifiers */
+enum kw41zrf_xcvseq {
+    XCVSEQ_IDLE           = 0b000,
+    XCVSEQ_RECEIVE        = 0b001,
+    XCVSEQ_TRANSMIT       = 0b010,
+    XCVSEQ_CCA            = 0b011,
+    XCVSEQ_TX_RX          = 0b100,
+    XCVSEQ_CONTINUOUS_CCA = 0b101,
+    /* Other values are reserved */
+};
+
+/**
+ * @brief   Set tx power of given device
+ *
+ * @param[in] dev        kw41zrf device descriptor
+ * @param[in] txpower    transmit power in dBm
+ */
+void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower);
+
+/**
+ * @brief   Get tx power value of given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ *
+ * @return              current tx power value
+ */
+uint16_t kw41zrf_get_txpower(kw41zrf_t *dev);
+
+/**
+ * @brief   Set channel of given  device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] val       channel
+ */
+int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t val);
+
+/**
+ * @brief   Get channel of given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ *
+ * @return              current channel
+ */
+uint8_t kw41zrf_get_channel(kw41zrf_t *dev);
+
+/**
+ * @brief   Abort current sequence of device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_abort_sequence(kw41zrf_t *dev);
+
+/**
+ * @brief   Set idle sequence state of device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+// void kw41zrf_set_idle_sequence(kw41zrf_t *dev);
+
+/**
+ * @brief   Set sequence state of device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] seq       sequence
+ */
+void kw41zrf_set_sequence(kw41zrf_t *dev, uint8_t seq);
+
+/**
+ * @brief   Set PAN ID of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] pan       PAN ID value
+ */
+void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan);
+
+/**
+ * @brief   Set short address of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] addr      short address
+ */
+void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr);
+
+/**
+ * @brief   Set long address of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] addr      long address
+ */
+void kw41zrf_set_addr_long(kw41zrf_t *dev, uint64_t addr);
+
+/**
+ * @brief   Get short address of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @return              current short address
+ */
+uint16_t kw41zrf_get_addr_short(kw41zrf_t *dev);
+
+/**
+ * @brief   Get long address of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @return              current long address
+ */
+uint64_t kw41zrf_get_addr_long(kw41zrf_t *dev);
+
+/**
+ * @brief   Get CCA threshhold of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @return              current CCA threshhold
+ */
+int8_t kw41zrf_get_cca_threshold(kw41zrf_t *dev);
+
+/**
+ * @brief   Set CCA threshold of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] value     CCA threshold
+ */
+void kw41zrf_set_cca_threshold(kw41zrf_t *dev, int8_t value);
+
+/**
+ * @brief   Set CCA mode of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] mode      CCA mode
+ */
+void kw41zrf_set_cca_mode(kw41zrf_t *dev, uint8_t mode);
+
+/**
+ * @brief   Get CCA mode of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @return              current CCA mode
+ */
+uint8_t kw41zrf_get_cca_mode(kw41zrf_t *dev);
+
+/**
+ * @brief   Get state of a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @return              current state
+ */
+netopt_state_t kw41zrf_get_status(kw41zrf_t *dev);
+
+/**
+ * @brief               Enable continous CCA
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ *
+ * @return              CCA value
+ */
+int kw41zrf_cca(kw41zrf_t *dev);
+
+/**
+ * @brief Set receive watermark
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] value     watermark
+ */
+void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value);
+
+/**
+ * @brief   Set netopt a given device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] option    Netopt option type
+ * @param[in] state     state
+ */
+void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* KW41ZRF_GETSET_H */
+/** @} */
diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h
new file mode 100644
index 0000000000000..49657236ae7f7
--- /dev/null
+++ b/drivers/kw41zrf/include/kw41zrf_intern.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ * Copyright (C) 2016 Phytec Messtechnik GmbH
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     drivers_kw41zrf
+ * @{
+ *
+ * @file
+ * @brief       Internal function interfaces for kw41zrf driver
+ *
+ * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ */
+
+#ifndef KW2XRF_INTERN_H
+#define KW2XRF_INTERN_H
+
+#include <stdint.h>
+#include "kw41zrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   KW41Z transceiver power modes
+ */
+typedef enum {
+    KW41ZRF_POWER_IDLE = 0, /**< All parts powered */
+    KW41ZRF_POWER_DSM, /**< Deep sleep mode */
+} kw41zrf_powermode_t;
+
+/**
+ * @brief   Timebase settings
+ */
+typedef enum kw41zrf_timer_timebase {
+    KW41ZRF_TIMEBASE_500000HZ = 0b010,
+    KW41ZRF_TIMEBASE_250000HZ = 0b011,
+    KW41ZRF_TIMEBASE_125000HZ = 0b100,
+    KW41ZRF_TIMEBASE_62500HZ  = 0b101,
+    KW41ZRF_TIMEBASE_31250HZ  = 0b110,
+    KW41ZRF_TIMEBASE_15625HZ  = 0b111,
+} kw41zrf_timer_timebase_t;
+
+/**
+ * @brief   Mask all transceiver interrupts
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+static inline void kw41zrf_mask_irqs(void)
+{
+    bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TRCV_MSK_SHIFT);
+}
+
+/**
+ * @brief   Allow transceiver interrupts
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+static inline void kw41zrf_unmask_irqs(void)
+{
+    bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TRCV_MSK_SHIFT);
+}
+
+/**
+ * @brief   Set the callback function for the radio ISR
+ *
+ * This callback will be called from ISR context when a radio_1 interrupt occurs
+ *
+ * @param[in]  cb   Pointer to callback function
+ * @param[in]  arg  Argument that will be passed to the callback
+ */
+void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg);
+
+/**
+ * @brief   Disable all interrupts on transceiver
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_disable_interrupts(kw41zrf_t *dev);
+
+/**
+ * @brief   Set power mode for device
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] pm        power mode value
+ */
+void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm);
+
+/**
+ * @brief
+ *
+ * @param[in] dev
+ *
+ * @return
+ */
+int kw41zrf_can_switch_to_idle(kw41zrf_t *dev);
+
+/**
+ * @brief   Initialize the Event Timer Block (up counter)
+ *
+ * The Event Timer Block provides:
+ *   - Abort an RX and CCA sequence at pre-determined time
+ *   - Latches "timestamp" value during packet reception
+ *   - Initiates timer-triggered sequences
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] tb        timer base value
+ */
+void kw41zrf_timer_init(kw41zrf_t *dev, kw41zrf_timer_timebase_t tb);
+
+/**
+ * @brief   Enable start sequence time
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_timer2_seq_start_on(kw41zrf_t *dev);
+
+/**
+ * @brief   Disable start sequence timer
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_timer2_seq_start_off(kw41zrf_t *dev);
+
+/**
+ * @brief   Enable abort sequence timer
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_timer3_seq_abort_on(kw41zrf_t *dev);
+
+/**
+ * @brief   Disable abort sequence timer
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_timer3_seq_abort_off(kw41zrf_t *dev);
+
+/**
+ * @brief   Use T2CMP or T2PRIMECMP to Trigger Transceiver Operations
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] timeout   timeout value
+ */
+void kw41zrf_trigger_tx_ops_enable(kw41zrf_t *dev, uint32_t timeout);
+
+/**
+ * @brief   Disable Trigger for Transceiver Operations
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_trigger_tx_ops_disable(kw41zrf_t *dev);
+
+/**
+ * @brief   Use T3CMP to Abort an RX operation
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ * @param[in] timeout   timeout value
+ */
+void kw41zrf_abort_rx_ops_enable(kw41zrf_t *dev, uint32_t timeout);
+
+/**
+ * @brief   Disable Trigger to Abort an RX operation
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ */
+void kw41zrf_abort_rx_ops_disable(kw41zrf_t *dev);
+
+/**
+ * @brief   Returns Timestamp of the actual received packet
+ *
+ * @param[in] dev       kw41zrf device descriptor
+ *
+ * @return              timestamp value
+ */
+uint32_t kw41zrf_get_timestamp(kw41zrf_t *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* KW2XRF_INTERN_H */
+/** @} */
diff --git a/drivers/kw41zrf/include/kw41zrf_netdev.h b/drivers/kw41zrf/include/kw41zrf_netdev.h
new file mode 100644
index 0000000000000..59af06d740d10
--- /dev/null
+++ b/drivers/kw41zrf/include/kw41zrf_netdev.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     drivers_kw41zrf
+ * @{
+ *
+ * @file
+ * @brief       Netdev interface for kw41zrf driver
+ *
+ * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ */
+
+#ifndef KW41ZRF_NETDEV_H
+#define KW41ZRF_NETDEV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   Reference to the netdev device driver struct
+ */
+extern const netdev_driver_t kw41zrf_driver;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* KW41ZRF_NETDEV_H */
+/** @} */
diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c
new file mode 100644
index 0000000000000..c05cce2db4ca4
--- /dev/null
+++ b/drivers/kw41zrf/kw41zrf.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     drivers_kw41zrf
+ * @{
+ * @file
+ * @brief       Basic functionality of kw41zrf driver
+ *
+ * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ * @}
+ */
+#include <stdint.h>
+#include <string.h>
+
+#include "log.h"
+#include "mutex.h"
+#include "msg.h"
+#include "net/gnrc.h"
+#include "net/ieee802154.h"
+#include "luid.h"
+
+#include "kw41zrf.h"
+#include "kw41zrf_netdev.h"
+#include "kw41zrf_getset.h"
+#include "kw41zrf_intern.h"
+#include "fsl_xcvr.h"
+
+#define ENABLE_DEBUG    (0)
+#include "debug.h"
+
+enum {
+    KW41Z_CCA_ED,
+    KW41Z_CCA_MODE1,
+    KW41Z_CCA_MODE2,
+    KW41Z_CCA_MODE3
+};
+
+enum {
+    KW41Z_STATE_IDLE,
+    KW41Z_STATE_RX,
+    KW41Z_STATE_TX,
+    KW41Z_STATE_CCA,
+    KW41Z_STATE_TXRX,
+    KW41Z_STATE_CCCA
+};
+
+static void kw41zrf_set_address(kw41zrf_t *dev)
+{
+    DEBUG("[kw41zrf] Set MAC address\n");
+    eui64_t addr_long;
+    /* get an 8-byte unique ID to use as hardware address */
+    luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
+    /* make sure we mark the address as non-multicast and not globally unique */
+    addr_long.uint8[0] &= ~(0x01);
+    addr_long.uint8[0] |=  (0x02);
+    /* set short and long address */
+    kw41zrf_set_addr_long(dev, ntohll(addr_long.uint64.u64));
+    kw41zrf_set_addr_short(dev, ntohs(addr_long.uint16[0].u16));
+}
+
+void kw41zrf_setup(kw41zrf_t *dev)
+{
+    netdev_t *netdev = (netdev_t *)dev;
+
+    netdev->driver = &kw41zrf_driver;
+    /* initialize device descriptor */
+    dev->idle_state = XCVSEQ_RECEIVE;
+    dev->state = 0;
+//     kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE);
+    DEBUG("[kw41zrf] setup finished\n");
+}
+
+int kw41zrf_init(kw41zrf_t *dev, gpio_cb_t cb)
+{
+    if (dev == NULL) {
+        return -ENODEV;
+    }
+
+    xcvrStatus_t xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS);
+    if (xcvrStatus != gXcvrSuccess_c) {
+        return -EIO;
+    }
+
+    /* Software reset of most settings */
+    kw41zrf_reset_phy(dev);
+
+    /* Compute warmup times (scaled to 16us) */
+    dev->rx_warmup_time =
+        (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >>
+        XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
+    dev->tx_warmup_time =
+        (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
+        XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
+
+    /* divide by 16 and round up */
+    dev->rx_warmup_time = (dev->rx_warmup_time + 15) / 16;
+    dev->tx_warmup_time = (dev->tx_warmup_time + 15) / 16;
+
+    /* Configre Radio IRQ */
+    kw41zrf_set_irq_callback(cb, dev);
+    NVIC_ClearPendingIRQ(Radio_1_IRQn);
+    NVIC_EnableIRQ(Radio_1_IRQn);
+
+    kw41zrf_abort_sequence(dev);
+    kw41zrf_unmask_irqs();
+
+    DEBUG("[kw41zrf] init finished\n");
+
+    return 0;
+}
+
+void kw41zrf_reset_phy(kw41zrf_t *dev)
+{
+    /* reset options and sequence number */
+    dev->netdev.seq = 0;
+    dev->netdev.flags = 0;
+
+    /* set default protocol */
+#ifdef MODULE_GNRC_SIXLOWPAN
+    dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN;
+#elif MODULE_GNRC
+    dev->netdev.proto = GNRC_NETTYPE_UNDEF;
+#endif
+
+    /* Reset PHY_CTRL to the default value of mask all interrupts and all other
+     * settings disabled */
+    ZLL->PHY_CTRL =
+        ZLL_PHY_CTRL_CCATYPE(1) |
+        ZLL_PHY_CTRL_TSM_MSK_MASK |
+        ZLL_PHY_CTRL_WAKE_MSK_MASK |
+        ZLL_PHY_CTRL_CRC_MSK_MASK |
+        ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK |
+        ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |
+        ZLL_PHY_CTRL_RX_WMRK_MSK_MASK |
+        ZLL_PHY_CTRL_CCAMSK_MASK |
+        ZLL_PHY_CTRL_RXMSK_MASK |
+        ZLL_PHY_CTRL_TXMSK_MASK |
+        ZLL_PHY_CTRL_SEQMSK_MASK;
+
+    /* Clear and disable all interrupts */
+    kw41zrf_disable_interrupts(dev);
+
+    /* Clear source address cache */
+    ZLL->SAM_TABLE |= ZLL_SAM_TABLE_INVALIDATE_ALL_MASK;
+
+    /* Accept FrameVersion 0 and 1 packets, reject all others */
+    ZLL->RX_FRAME_FILTER = ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(3) |
+        ZLL_RX_FRAME_FILTER_ACK_FT_MASK |
+        ZLL_RX_FRAME_FILTER_DATA_FT_MASK;
+
+    /* Set prescaler to obtain 1 symbol (16us) timebase */
+    kw41zrf_timer_init(dev, KW41ZRF_TIMEBASE_62500HZ);
+
+    /* Set CCA threshold to -75 dBm */
+    ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) |
+        ZLL_CCA_LQI_CTRL_CCA1_THRESH(0xB5);
+
+    /* Adjust ACK delay to fulfill the 802.15.4 turnaround requirements */
+    ZLL->ACKDELAY = (ZLL->ACKDELAY & ~ZLL_ACKDELAY_ACKDELAY_MASK) | ZLL_ACKDELAY_ACKDELAY(-8);
+
+    /* Adjust LQI compensation */
+    /* Hardware reset default is 102 */
+    ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK) |
+        ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(96);
+
+    dev->tx_power = KW41ZRF_DEFAULT_TX_POWER;
+    kw41zrf_set_tx_power(dev, dev->tx_power);
+
+    kw41zrf_set_channel(dev, KW41ZRF_DEFAULT_CHANNEL);
+
+    kw41zrf_set_pan(dev, KW41ZRF_DEFAULT_PANID);
+    kw41zrf_set_address(dev);
+
+    kw41zrf_set_cca_mode(dev, 1);
+
+    kw41zrf_set_rx_watermark(dev, 1);
+
+    kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, true);
+    kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, true);
+    kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOCCA, true);
+
+    kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE);
+    kw41zrf_set_sequence(dev, dev->idle_state);
+
+    kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START, true);
+    kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, true);
+    kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, true);
+    bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_SEQMSK_SHIFT);
+
+    DEBUG("[kw41zrf] reset PHY and (re)set to channel %d and pan %d.\n",
+          KW41ZRF_DEFAULT_CHANNEL, KW41ZRF_DEFAULT_PANID);
+}
diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c
new file mode 100644
index 0000000000000..a10d91239d36a
--- /dev/null
+++ b/drivers/kw41zrf/kw41zrf_getset.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup     drivers_kw41zrf
+ * @{
+ * @file
+ * @brief       get/set functionality of kw41zrf driver
+ *
+ * @author  Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ * @}
+ */
+
+#include <errno.h>
+#include "log.h"
+#include "cpu.h"
+#include "byteorder.h"
+#include "kw41zrf.h"
+#include "kw41zrf_intern.h"
+#include "kw41zrf_getset.h"
+
+#define ENABLE_DEBUG (0)
+#include "debug.h"
+
+#define KW41ZRF_NUM_CHANNEL      (KW41ZRF_MAX_CHANNEL - KW41ZRF_MIN_CHANNEL + 1)
+
+/* Lookup table for PA_PWR register */
+static const uint8_t pa_pwr_lt[22] = {
+    2, 2, 2, 2, 2, 2,  /* -19:-14 dBm */
+    4, 4, 4,           /* -13:-11 dBm */
+    6, 6, 6,           /* -10:-8 dBm */
+    8, 8,              /* -7:-6 dBm */
+    10, 10,            /* -5:-4 dBm */
+    12,                /* -3 dBm */
+    14, 14,            /* -2:-1 dBm */
+    18, 18,            /* 0:1 dBm */
+    24                 /* 2 dBm */
+};
+
+void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower_dbm)
+{
+    if (txpower_dbm < KW41ZRF_OUTPUT_POWER_MIN) {
+        ZLL->PA_PWR = 0;
+    }
+    else if (txpower_dbm > KW41ZRF_OUTPUT_POWER_MAX) {
+        ZLL->PA_PWR = 30;
+    }
+    else {
+        ZLL->PA_PWR = pa_pwr_lt[txpower_dbm - KW41ZRF_OUTPUT_POWER_MIN];
+    }
+
+    LOG_DEBUG("[kw41zrf] set txpower to: %d\n", txpower_dbm);
+    dev->tx_power = txpower_dbm;
+}
+
+uint16_t kw41zrf_get_txpower(kw41zrf_t *dev)
+{
+    return dev->tx_power;
+}
+
+uint8_t kw41zrf_get_channel(kw41zrf_t *dev)
+{
+    return (ZLL->CHANNEL_NUM0 & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK);
+}
+
+int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t channel)
+{
+    if (channel < KW41ZRF_MIN_CHANNEL || channel > KW41ZRF_MAX_CHANNEL) {
+        LOG_ERROR("[kw41zrf] Invalid channel %u\n", channel);
+        return -EINVAL;
+    }
+
+    ZLL->CHANNEL_NUM0 = channel;
+    dev->netdev.chan = channel;
+
+    LOG_DEBUG("[kw41zrf] set channel to %u\n", channel);
+    return 0;
+}
+
+inline void kw41zrf_abort_sequence(kw41zrf_t *dev)
+{
+    /* Writing IDLE to XCVSEQ aborts any ongoing sequence */
+    ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_XCVSEQ_MASK) | ZLL_PHY_CTRL_XCVSEQ(XCVSEQ_IDLE);
+    /* Clear interrupt flags */
+    ZLL->IRQSTS = ZLL->IRQSTS;
+}
+
+void kw41zrf_set_sequence(kw41zrf_t *dev, uint8_t seq)
+{
+    kw41zrf_abort_sequence(dev);
+
+    switch (seq) {
+        case XCVSEQ_IDLE:
+        case XCVSEQ_RECEIVE:
+            /* TODO why is RX == IDLE??? */
+            dev->state = NETOPT_STATE_IDLE;
+            break;
+
+        case XCVSEQ_CONTINUOUS_CCA:
+        case XCVSEQ_CCA:
+            dev->state = NETOPT_STATE_RX;
+            break;
+
+        case XCVSEQ_TRANSMIT:
+        case XCVSEQ_TX_RX:
+            dev->state = NETOPT_STATE_TX;
+            break;
+
+        default:
+            DEBUG("[kw41zrf] undefined state assigned to phy\n");
+            dev->state = NETOPT_STATE_IDLE;
+    }
+
+    DEBUG("[kw41zrf] set sequence to %u\n", (unsigned int)seq);
+    ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_XCVSEQ_MASK) | ZLL_PHY_CTRL_XCVSEQ(seq);
+    /* clear all IRQ flags */
+    ZLL->IRQSTS = ZLL->IRQSTS;
+}
+
+void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan)
+{
+    dev->netdev.pan = pan;
+
+    ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACPANID0_MASK) |
+        ZLL_MACSHORTADDRS0_MACPANID0(pan);
+
+    LOG_DEBUG("[kw41zrf] set pan to: 0x%x\n", pan);
+    dev->netdev.pan = pan;
+}
+
+void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr)
+{
+#ifdef MODULE_SIXLOWPAN
+    /* https://tools.ietf.org/html/rfc4944#section-12 requires the first bit to
+     * 0 for unicast addresses */
+    addr &= 0x7fff;
+#endif
+    /* Network byte order */
+    /* TODO use byteorder.h */
+    dev->netdev.short_addr[0] = (addr & 0xff);
+    dev->netdev.short_addr[1] = (addr >> 8);
+    ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) |
+        ZLL_MACSHORTADDRS0_MACSHORTADDRS0(addr);
+}
+
+void kw41zrf_set_addr_long(kw41zrf_t *dev, uint64_t addr)
+{
+    (void) dev;
+    for (unsigned i = 0; i < IEEE802154_LONG_ADDRESS_LEN; i++) {
+        dev->netdev.long_addr[i] = (uint8_t)(addr >> (i * 8));
+    }
+    /* Network byte order */
+    addr = byteorder_swapll(addr);
+    ZLL->MACLONGADDRS0_LSB = (uint32_t)addr;
+    ZLL->MACLONGADDRS0_MSB = (addr >> 32);
+}
+
+uint16_t kw41zrf_get_addr_short(kw41zrf_t *dev)
+{
+    (void) dev;
+    return (ZLL->MACSHORTADDRS0 & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) >>
+        ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT;
+}
+
+uint64_t kw41zrf_get_addr_long(kw41zrf_t *dev)
+{
+    (void) dev;
+    uint64_t addr = ((uint64_t)ZLL->MACLONGADDRS0_MSB << 32) | ZLL->MACLONGADDRS0_LSB;
+    /* Network byte order */
+    addr = byteorder_swapll(addr);
+
+    return addr;
+}
+
+int8_t kw41zrf_get_cca_threshold(kw41zrf_t *dev)
+{
+    (void) dev;
+    uint8_t tmp = (ZLL->CCA_LQI_CTRL & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK);
+    return (int8_t)tmp;
+}
+
+void kw41zrf_set_cca_threshold(kw41zrf_t *dev, int8_t value)
+{
+    (void) dev;
+    ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) |
+        ZLL_CCA_LQI_CTRL_CCA1_THRESH(value);
+}
+
+void kw41zrf_set_cca_mode(kw41zrf_t *dev, uint8_t mode)
+{
+    (void) dev;
+    ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_CCATYPE_MASK) |
+        ZLL_PHY_CTRL_CCATYPE(mode);
+}
+
+uint8_t kw41zrf_get_cca_mode(kw41zrf_t *dev)
+{
+    (void) dev;
+    return (ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCATYPE_MASK) >> ZLL_PHY_CTRL_CCATYPE_SHIFT;
+}
+
+void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state)
+{
+    DEBUG("[kw41zrf] set option 0x%04x to %x\n", option, state);
+
+    /* set option field */
+    if (state) {
+        dev->netdev.flags |= option;
+
+        /* trigger option specific actions */
+        switch (option) {
+            case KW41ZRF_OPT_AUTOCCA:
+                LOG_DEBUG("[kw41zrf] enable: AUTOCCA\n");
+                bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_PROMISCUOUS:
+                LOG_DEBUG("[kw41zrf] enable: PROMISCUOUS\n");
+                /* enable promiscuous mode */
+                bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT);
+                /* auto ACK is always disabled in promiscuous mode by the hardware */
+                break;
+
+            case KW41ZRF_OPT_AUTOACK:
+                LOG_DEBUG("[kw41zrf] enable: AUTOACK\n");
+                bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_ACK_REQ:
+                LOG_DEBUG("[kw41zrf] enable: ACK_REQ\n");
+                bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_TELL_RX_START:
+                LOG_DEBUG("[kw41zrf] enable: TELL_RX_START\n");
+                bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_TELL_RX_END:
+                LOG_DEBUG("[kw41zrf] enable: TELL_RX_END\n");
+                break;
+
+            case KW41ZRF_OPT_TELL_TX_END:
+                LOG_DEBUG("[kw41zrf] enable: TELL_TX_END\n");
+                break;
+
+            case KW41ZRF_OPT_TELL_TX_START:
+                LOG_DEBUG("[kw41zrf] enable: TELL_TX_START (ignored)\n");
+            default:
+                /* do nothing */
+                break;
+        }
+    }
+    else {
+        dev->netdev.flags &= ~(option);
+        /* trigger option specific actions */
+        switch (option) {
+            case KW41ZRF_OPT_AUTOCCA:
+                LOG_DEBUG("[kw41zrf] disable: AUTOCCA\n");
+                bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_PROMISCUOUS:
+                LOG_DEBUG("[kw41zrf] disable: PROMISCUOUS\n");
+                /* disable promiscuous mode */
+                bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_AUTOACK:
+                LOG_DEBUG("[kw41zrf] disable: AUTOACK\n");
+                bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_ACK_REQ:
+                LOG_DEBUG("[kw41zrf] disable: ACK_REQ\n");
+                bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_TELL_RX_START:
+                LOG_DEBUG("[kw41zrf] disable: TELL_RX_START\n");
+                bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT);
+                break;
+
+            case KW41ZRF_OPT_TELL_RX_END:
+                LOG_DEBUG("[kw41zrf] disable: TELL_RX_END\n");
+                break;
+
+            case KW41ZRF_OPT_TELL_TX_END:
+                LOG_DEBUG("[kw41zrf] disable: TELL_TX_END\n");
+                break;
+
+            case KW41ZRF_OPT_TELL_TX_START:
+                LOG_DEBUG("[kw41zrf] disable: TELL_TX_START (ignored)\n");
+            default:
+                /* do nothing */
+                break;
+        }
+    }
+}
+
+netopt_state_t kw41zrf_get_status(kw41zrf_t *dev)
+{
+    uint32_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT;
+
+    switch (seq) {
+        case XCVSEQ_IDLE:
+            return NETOPT_STATE_IDLE;
+
+        case XCVSEQ_RECEIVE:
+            return NETOPT_STATE_RX;
+
+        case XCVSEQ_TRANSMIT:
+            return NETOPT_STATE_TX;
+
+        case XCVSEQ_CCA:
+            return NETOPT_STATE_RX;
+
+        case XCVSEQ_TX_RX:
+            return NETOPT_STATE_TX;
+
+        case XCVSEQ_CONTINUOUS_CCA:
+            return NETOPT_STATE_RX;
+
+        default:
+            LOG_ERROR("[kw41zrf] XCVSEQ = %u is reserved!", (unsigned int) seq);
+            break;
+    }
+    return NETOPT_STATE_IDLE;
+}
+
+int kw41zrf_cca(kw41zrf_t *dev)
+{
+    /* TODO: add Standalone CCA here */
+    kw41zrf_set_sequence(dev, XCVSEQ_CCA);
+    /* using CCA mode 1, this takes exactly RX warmup time + 128 µs, which is
+     * short enough to just spin */
+    while (((ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT) == XCVSEQ_CCA) {}
+    DEBUG("[kw41zrf] kw41zrf_cca done\n");
+    if (ZLL->IRQSTS & ZLL_IRQSTS_CCA_MASK) {
+        DEBUG("[kw41zrf] Channel busy\n");
+        return 1;
+    }
+    DEBUG("[kw41zrf] Channel free\n");
+    return 0;
+}
+
+void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value)
+{
+    ZLL->RX_WTR_MARK = ZLL_RX_WTR_MARK_RX_WTR_MARK(value);
+}
diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c
new file mode 100644
index 0000000000000..49410cf7c6acb
--- /dev/null
+++ b/drivers/kw41zrf/kw41zrf_intern.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup     drivers_kw41zrf
+ * @{
+ * @file
+ * @brief       Internal function of kw41zrf driver
+ *
+ * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ * @}
+ */
+
+#include "irq.h"
+#include "panic.h"
+#include "kw41zrf.h"
+#include "kw41zrf_getset.h"
+#include "kw41zrf_intern.h"
+
+#define ENABLE_DEBUG (0)
+#include "debug.h"
+
+struct {
+    void (*cb)(void *arg); /**< Callback function called from radio ISR */
+    void *arg;             /**< Argument to callback */
+} isr_config;
+
+void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg)
+{
+    unsigned int mask = irq_disable();
+    isr_config.cb = cb;
+    isr_config.arg = arg;
+    irq_restore(mask);
+}
+
+void kw41zrf_disable_interrupts(kw41zrf_t *dev)
+{
+    DEBUG("[kw41zrf] disable interrupts\n");
+    /* Clear and disable all interrupts */
+    ZLL->PHY_CTRL |=
+        ZLL_PHY_CTRL_TSM_MSK_MASK |
+        ZLL_PHY_CTRL_WAKE_MSK_MASK |
+        ZLL_PHY_CTRL_CRC_MSK_MASK |
+        ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK |
+        ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |
+        ZLL_PHY_CTRL_RX_WMRK_MSK_MASK |
+        ZLL_PHY_CTRL_CCAMSK_MASK |
+        ZLL_PHY_CTRL_RXMSK_MASK |
+        ZLL_PHY_CTRL_TXMSK_MASK |
+        ZLL_PHY_CTRL_SEQMSK_MASK;
+
+    /* Mask all timer interrupts and clear all interrupt flags */
+    ZLL->IRQSTS =
+        ZLL_IRQSTS_TMR1MSK_MASK |
+        ZLL_IRQSTS_TMR2MSK_MASK |
+        ZLL_IRQSTS_TMR3MSK_MASK |
+        ZLL_IRQSTS_TMR4MSK_MASK |
+        ZLL_IRQSTS_TMR1IRQ_MASK |
+        ZLL_IRQSTS_TMR2IRQ_MASK |
+        ZLL_IRQSTS_TMR3IRQ_MASK |
+        ZLL_IRQSTS_TMR4IRQ_MASK |
+        ZLL_IRQSTS_WAKE_IRQ_MASK |
+        ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK |
+        ZLL_IRQSTS_FILTERFAIL_IRQ_MASK |
+        ZLL_IRQSTS_RXWTRMRKIRQ_MASK |
+        ZLL_IRQSTS_CCAIRQ_MASK |
+        ZLL_IRQSTS_RXIRQ_MASK |
+        ZLL_IRQSTS_TXIRQ_MASK |
+        ZLL_IRQSTS_SEQIRQ_MASK;
+}
+
+void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm)
+{
+    DEBUG("[kw41zrf] set power mode to %u\n", pm);
+    /* TODO handle event timer */
+    switch (pm) {
+        case KW41ZRF_POWER_IDLE:
+            bit_clear32(&ZLL->DSM_CTRL, ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT);
+            break;
+        case KW41ZRF_POWER_DSM:
+            bit_set32(&ZLL->DSM_CTRL, ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT);
+            break;
+        default:
+            DEBUG("[kw41zrf] Unknown power mode %u\n", pm);
+            return;
+    }
+}
+
+int kw41zrf_can_switch_to_idle(kw41zrf_t *dev)
+{
+    uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT;
+    uint8_t actual = (ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT;
+
+    DEBUG("[kw41zrf] XCVSEQ_ACTUAL=0x%x, XCVSEQ=0x%x, SEQ_STATE=0x%" PRIx32 "\n", actual, seq,
+        (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) >> ZLL_SEQ_STATE_SEQ_STATE_SHIFT);
+
+    switch (seq)
+    {
+        case XCVSEQ_TRANSMIT:
+        case XCVSEQ_TX_RX:
+            return 0;
+
+        default:
+            break;
+    }
+    switch (actual)
+    {
+        case XCVSEQ_TRANSMIT:
+        case XCVSEQ_TX_RX:
+            return 0;
+
+        default:
+            break;
+    }
+
+    return 1;
+}
+
+/** Load the timer value (Setting Current Time) */
+static inline void kw41zrf_timer_load(kw41zrf_t *dev, uint32_t value)
+{
+    (void) dev;
+    ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR(value) | ZLL_EVENT_TMR_EVENT_TMR_LD_MASK;
+}
+
+static inline uint32_t kw41zrf_timer_get(kw41zrf_t *dev)
+{
+    (void) dev;
+    return (ZLL->EVENT_TMR & ZLL_EVENT_TMR_EVENT_TMR_MASK) >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT;
+}
+
+/** Set a timeout value for the given compare register of the Event Timer */
+static inline void kw41zrf_timer_set(kw41zrf_t *dev, volatile uint32_t *cmp_reg, uint32_t timeout)
+{
+    uint32_t now = kw41zrf_timer_get(dev);
+
+    DEBUG("[kw41zrf] timer now: %" PRIx32 ", set %" PRIx32 "\n", now, now + timeout);
+    *cmp_reg = now + timeout;
+}
+
+void kw41zrf_timer_init(kw41zrf_t *dev, kw41zrf_timer_timebase_t tb)
+{
+    ZLL->TMR_PRESCALE = (ZLL->TMR_PRESCALE & ~ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK) |
+        ZLL_TMR_PRESCALE_TMR_PRESCALE(tb);
+    kw41zrf_timer_load(dev, 0);
+}
+
+void kw41zrf_timer2_seq_start_on(kw41zrf_t *dev)
+{
+    bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT);
+}
+
+void kw41zrf_timer2_seq_start_off(kw41zrf_t *dev)
+{
+    bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT);
+}
+
+void kw41zrf_timer3_seq_abort_on(kw41zrf_t *dev)
+{
+    bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TC3TMOUT_SHIFT);
+}
+
+void kw41zrf_timer3_seq_abort_off(kw41zrf_t *dev)
+{
+    bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TC3TMOUT_SHIFT);
+}
+
+void kw41zrf_trigger_tx_ops_enable(kw41zrf_t *dev, uint32_t timeout)
+{
+    kw41zrf_timer_set(dev, &ZLL->T2CMP, timeout);
+    bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT);
+}
+
+void kw41zrf_trigger_tx_ops_disable(kw41zrf_t *dev)
+{
+    bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT);
+    DEBUG("[kw41zrf] trigger_tx_ops_disable, now: %" PRIx32 "\n", kw41zrf_timer_get(dev));
+}
+
+void kw41zrf_abort_rx_ops_enable(kw41zrf_t *dev, uint32_t timeout)
+{
+    kw41zrf_timer_set(dev, &ZLL->T3CMP, timeout);
+    bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT);
+}
+
+void kw41zrf_abort_rx_ops_disable(kw41zrf_t *dev)
+{
+    bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT);
+    DEBUG("[kw41zrf] abort_rx_ops_disable, now: %" PRIx32 "\n", kw41zrf_timer_get(dev));
+}
+
+uint32_t kw41zrf_get_timestamp(kw41zrf_t *dev)
+{
+    return ZLL->TIMESTAMP;
+}
+
+void isr_radio_int1(void)
+{
+    DEBUG("[kw41zrf] INT1\n");
+    if (isr_config.cb != NULL) {
+        isr_config.cb(isr_config.arg);
+    }
+    cortexm_isr_end();
+}
diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c
new file mode 100644
index 0000000000000..60d8d56cd161f
--- /dev/null
+++ b/drivers/kw41zrf/kw41zrf_netdev.c
@@ -0,0 +1,812 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     drivers_kw41zrf
+ * @{
+ *
+ * @file
+ * @brief       Netdev interface for kw41zrf drivers
+ *
+ * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+
+#include "log.h"
+#include "od.h"
+#include "net/eui64.h"
+#include "net/ieee802154.h"
+#include "net/netdev.h"
+#include "net/netdev/ieee802154.h"
+
+#include "kw41zrf.h"
+#include "kw41zrf_netdev.h"
+#include "kw41zrf_intern.h"
+#include "kw41zrf_getset.h"
+
+#define ENABLE_DEBUG (0)
+#include "debug.h"
+
+#define _MAX_MHR_OVERHEAD           (25)
+
+/* Timing */
+#define KW41ZRF_CCA_TIME               8
+#define KW41ZRF_SHR_PHY_TIME          12
+#define KW41ZRF_PER_BYTE_TIME          2
+#define KW41ZRF_ACK_WAIT_TIME         54
+
+static void kw41zrf_irq_handler(void *arg)
+{
+    netdev_t *dev = (netdev_t *) arg;
+
+    kw41zrf_mask_irqs();
+
+    if (dev->event_callback) {
+        dev->event_callback(dev, NETDEV_EVENT_ISR);
+    }
+}
+
+static int kw41zrf_netdev_init(netdev_t *netdev)
+{
+    kw41zrf_t *dev = (kw41zrf_t *)netdev;
+
+    /* initialise SPI and GPIOs */
+    if (kw41zrf_init(dev, &kw41zrf_irq_handler)) {
+        LOG_ERROR("[kw41zrf] unable to initialize device\n");
+        return -1;
+    }
+
+#ifdef MODULE_NETSTATS_L2
+    memset(&netdev->stats, 0, sizeof(netstats_t));
+#endif
+
+    /* reset device to default values and put it into RX state */
+    kw41zrf_reset_phy(dev);
+
+    /* Use TC3 for RX timeouts */
+    kw41zrf_timer3_seq_abort_on(dev);
+
+    return 0;
+}
+
+static inline size_t kw41zrf_tx_load(const void *buf, size_t len, size_t offset)
+{
+    /* Array bounds are checked in the kw41zrf_netdev_send loop */
+    /* offset + 1 is used because buf[0] contains the frame length byte */
+    memcpy(((uint8_t *)&ZLL->PKT_BUFFER_TX[0]) + offset + 1, buf, len);
+    return offset + len;
+}
+
+static void kw41zrf_tx_exec(kw41zrf_t *dev)
+{
+    uint16_t len_fcf = ZLL->PKT_BUFFER_TX[0];
+    DEBUG("[kw41zrf] len_fcf=0x%04x\n", len_fcf);
+    /* Check FCF field in the TX buffer to see if the ACK_REQ flag was set in
+     * the packet that is queued for transmission */
+    uint8_t fcf = (len_fcf >> 8) & 0xff;
+    if ((dev->netdev.flags & KW41ZRF_OPT_ACK_REQ) &&
+        (fcf & IEEE802154_FCF_ACK_REQ)) {
+        uint8_t payload_len = len_fcf & 0xff;
+        uint32_t tx_timeout = dev->tx_warmup_time + KW41ZRF_SHR_PHY_TIME +
+            payload_len * KW41ZRF_PER_BYTE_TIME + KW41ZRF_ACK_WAIT_TIME;
+        DEBUG("[kw41zrf] Start TR\n");
+        kw41zrf_set_sequence(dev, XCVSEQ_TX_RX);
+        /* Set timeout for RX ACK */
+        kw41zrf_abort_rx_ops_enable(dev, tx_timeout);
+    }
+    else {
+        DEBUG("[kw41zrf] Start T\n");
+        kw41zrf_set_sequence(dev, XCVSEQ_TRANSMIT);
+    }
+}
+
+static int kw41zrf_netdev_send(netdev_t *netdev, const struct iovec *vector, unsigned count)
+{
+    kw41zrf_t *dev = (kw41zrf_t *)netdev;
+    const struct iovec *ptr = vector;
+    size_t len = 0;
+
+    /* make sure ongoing T or TR sequence are finished */
+    if (kw41zrf_can_switch_to_idle(dev) == 0) {
+        /* TX in progress */
+        return -ENOBUFS;
+    }
+
+    /* load packet data into buffer */
+    for (unsigned i = 0; i < count; i++, ptr++) {
+        /* current packet data + FCS too long */
+        if ((len + ptr->iov_len + IEEE802154_FCS_LEN) > KW41ZRF_MAX_PKT_LENGTH) {
+            LOG_ERROR("[kw41zrf] packet too large (%u byte) to fit\n",
+                  (unsigned)len + IEEE802154_FCS_LEN);
+            return -EOVERFLOW;
+        }
+        len = kw41zrf_tx_load(ptr->iov_base, ptr->iov_len, len);
+    }
+
+    /* Abort what is going on */
+    kw41zrf_set_sequence(dev, XCVSEQ_IDLE);
+
+    DEBUG("[kw41zrf] TX %u bytes\n", len);
+
+    /*
+     * First octet in the TX buffer contains the frame length.
+     * Nbytes = FRAME_LEN - 2 -> FRAME_LEN = Nbytes + 2
+     * MKW41Z ref. man. 44.6.2.6.3.1.3 Sequence T (Transmit), p. 2147
+     */
+    *((volatile uint8_t *)&ZLL->PKT_BUFFER_TX[0]) = len + IEEE802154_FCS_LEN;
+#if defined(MODULE_OD) && ENABLE_DEBUG
+    DEBUG("[kw41zrf] send:\n");
+    od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_TX, len, OD_WIDTH_DEFAULT);
+#endif
+
+#ifdef MODULE_NETSTATS_L2
+    netdev->stats.tx_bytes += len;
+#endif
+
+    /* send data out directly if pre-loading is disabled */
+    if (!(dev->netdev.flags & KW41ZRF_OPT_PRELOADING)) {
+        kw41zrf_tx_exec(dev);
+    }
+
+    return (int)len;
+}
+
+static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *info)
+{
+    /* get size of the received packet */
+    uint8_t pkt_len = (ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT;
+    /* skip FCS */
+    pkt_len -= IEEE802154_FCS_LEN;
+    DEBUG("[kw41zrf] RX %u bytes\n", pkt_len);
+
+    /* just return length when buf == NULL */
+    if (buf == NULL) {
+        return pkt_len;
+    }
+
+//     DEBUG("[kw41zrf] buf len: %3u\n", (unsigned int)pkt_len);
+#if defined(MODULE_OD) && ENABLE_DEBUG
+    DEBUG("[kw41zrf] recv:\n");
+    od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_RX, pkt_len, OD_WIDTH_DEFAULT);
+#endif
+
+#ifdef MODULE_NETSTATS_L2
+    netdev->stats.rx_count++;
+    netdev->stats.rx_bytes += pkt_len;
+#else
+    (void)netdev;
+#endif
+
+    if (pkt_len > len) {
+        /* not enough space in buf */
+        return -ENOBUFS;
+    }
+    memcpy(buf, (const void *)&ZLL->PKT_BUFFER_RX[0], pkt_len);
+
+    if (info != NULL) {
+        netdev_ieee802154_rx_info_t *radio_info = info;
+        uint8_t hw_lqi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >>
+            ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT;
+        if (hw_lqi >= 220) {
+            radio_info->lqi = 255;
+        } else {
+            radio_info->lqi = (51 * hw_lqi) / 44;
+        }
+        radio_info->rssi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_RSSI_MASK) >> ZLL_LQI_AND_RSSI_RSSI_SHIFT;
+    }
+
+    return pkt_len;
+}
+
+static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state)
+{
+    switch (state) {
+        case NETOPT_STATE_OFF:
+        case NETOPT_STATE_SLEEP:
+            kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM);
+            break;
+        case NETOPT_STATE_IDLE:
+            kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE);
+            kw41zrf_set_sequence(dev, dev->idle_state);
+            break;
+        case NETOPT_STATE_TX:
+            if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) {
+                kw41zrf_tx_exec(dev);
+            }
+            break;
+        case NETOPT_STATE_RESET:
+            kw41zrf_reset_phy(dev);
+            break;
+        default:
+            return -ENOTSUP;
+    }
+    return sizeof(netopt_state_t);
+}
+
+int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len)
+{
+    kw41zrf_t *dev = (kw41zrf_t *)netdev;
+
+    if (dev == NULL) {
+        return -ENODEV;
+    }
+
+    switch (opt) {
+        case NETOPT_MAX_PACKET_SIZE:
+            if (len < sizeof(int16_t)) {
+                return -EOVERFLOW;
+            }
+
+            *((uint16_t *)value) = KW41ZRF_MAX_PKT_LENGTH - _MAX_MHR_OVERHEAD;
+            return sizeof(uint16_t);
+
+        case NETOPT_STATE:
+            if (len < sizeof(netopt_state_t)) {
+                return -EOVERFLOW;
+            }
+            *((netopt_state_t *)value) = dev->state;
+            return sizeof(netopt_state_t);
+
+        case NETOPT_PRELOADING:
+            if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) {
+                *((netopt_enable_t *)value) = NETOPT_ENABLE;
+            }
+            else {
+                *((netopt_enable_t *)value) = NETOPT_DISABLE;
+            }
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_PROMISCUOUSMODE:
+            if (dev->netdev.flags & KW41ZRF_OPT_PROMISCUOUS) {
+                *((netopt_enable_t *)value) = NETOPT_ENABLE;
+            }
+            else {
+                *((netopt_enable_t *)value) = NETOPT_DISABLE;
+            }
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_RX_START_IRQ:
+            *((netopt_enable_t *)value) =
+                !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START);
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_RX_END_IRQ:
+            *((netopt_enable_t *)value) =
+                !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END);
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_TX_START_IRQ:
+            *((netopt_enable_t *)value) =
+                !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START);
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_TX_END_IRQ:
+            *((netopt_enable_t *)value) =
+                !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END);
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_AUTOCCA:
+            *((netopt_enable_t *)value) =
+                !!(dev->netdev.flags & KW41ZRF_OPT_AUTOCCA);
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_TX_POWER:
+            if (len < sizeof(int16_t)) {
+                return -EOVERFLOW;
+            }
+            *((uint16_t *)value) = kw41zrf_get_txpower(dev);
+            return sizeof(uint16_t);
+
+        case NETOPT_IS_CHANNEL_CLR:
+            if (kw41zrf_cca(dev)) {
+                *((netopt_enable_t *)value) = NETOPT_ENABLE;
+            }
+            else {
+                *((netopt_enable_t *)value) = NETOPT_DISABLE;
+            }
+            return sizeof(netopt_enable_t);
+
+        case NETOPT_CCA_THRESHOLD:
+            if (len < sizeof(uint8_t)) {
+                return -EOVERFLOW;
+            }
+            else {
+                *(int8_t *)value = kw41zrf_get_cca_threshold(dev);
+            }
+            return sizeof(int8_t);
+
+        case NETOPT_CCA_MODE:
+            if (len < sizeof(uint8_t)) {
+                return -EOVERFLOW;
+            }
+            else {
+                *(uint8_t *)value = kw41zrf_get_cca_mode(dev);
+                switch (*((int8_t *)value)) {
+                    case NETDEV_IEEE802154_CCA_MODE_1:
+                    case NETDEV_IEEE802154_CCA_MODE_2:
+                    case NETDEV_IEEE802154_CCA_MODE_3:
+                        return sizeof(uint8_t);
+                    default:
+                        break;
+                }
+                return -EOVERFLOW;
+            }
+            break;
+
+        case NETOPT_CHANNEL_PAGE:
+        default:
+            break;
+    }
+
+    return netdev_ieee802154_get((netdev_ieee802154_t *)netdev, opt, value, len);
+}
+
+static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, void *value, size_t len)
+{
+    kw41zrf_t *dev = (kw41zrf_t *)netdev;
+    int res = -ENOTSUP;
+
+    if (dev == NULL) {
+        return -ENODEV;
+    }
+
+    switch (opt) {
+        case NETOPT_ADDRESS:
+            if (len > sizeof(uint16_t)) {
+                res = -EOVERFLOW;
+            }
+            else {
+                kw41zrf_set_addr_short(dev, *((uint16_t *)value));
+                /* don't set res to set netdev_ieee802154_t::short_addr */
+            }
+            break;
+
+        case NETOPT_ADDRESS_LONG:
+            if (len > sizeof(uint64_t)) {
+                return -EOVERFLOW;
+            }
+            else {
+                kw41zrf_set_addr_long(dev, *((uint64_t *)value));
+                /* don't set res to set netdev_ieee802154_t::short_addr */
+            }
+            break;
+
+        case NETOPT_NID:
+            if (len > sizeof(uint16_t)) {
+                return -EOVERFLOW;
+            }
+
+            else {
+                kw41zrf_set_pan(dev, *((uint16_t *)value));
+                /* don't set res to set netdev_ieee802154_t::pan */
+            }
+            break;
+
+        case NETOPT_CHANNEL:
+            if (len != sizeof(uint16_t)) {
+                res = -EINVAL;
+            }
+            else {
+                uint8_t chan = ((uint8_t *)value)[0];
+                if (kw41zrf_set_channel(dev, chan)) {
+                    res = -EINVAL;
+                    break;
+                }
+                /* don't set res to set netdev_ieee802154_t::chan */
+            }
+            break;
+
+        case NETOPT_CHANNEL_PAGE:
+            res = -EINVAL;
+            break;
+
+        case NETOPT_TX_POWER:
+            if (len < sizeof(uint16_t)) {
+                res = -EOVERFLOW;
+            }
+            else {
+                kw41zrf_set_tx_power(dev, *(int16_t *)value);
+                res = sizeof(uint16_t);
+            }
+            break;
+
+        case NETOPT_STATE:
+            if (len > sizeof(netopt_state_t)) {
+                res = -EOVERFLOW;
+            }
+            else {
+                res = kw41zrf_netdev_set_state(dev, *((netopt_state_t *)value));
+            }
+            break;
+
+        case NETOPT_AUTOACK:
+            /* Set up HW generated automatic ACK after Receive */
+            kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK,
+                              ((bool *)value)[0]);
+            break;
+
+        case NETOPT_ACK_REQ:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ,
+                              ((bool *)value)[0]);
+            break;
+
+        case NETOPT_PRELOADING:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_PRELOADING,
+                              ((bool *)value)[0]);
+            res = sizeof(netopt_enable_t);
+            break;
+
+        case NETOPT_PROMISCUOUSMODE:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_PROMISCUOUS,
+                              ((bool *)value)[0]);
+            res = sizeof(netopt_enable_t);
+            break;
+
+        case NETOPT_RX_START_IRQ:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START,
+                                 ((bool *)value)[0]);
+            res = sizeof(netopt_enable_t);
+            break;
+
+        case NETOPT_RX_END_IRQ:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END,
+                                 ((bool *)value)[0]);
+            res = sizeof(netopt_enable_t);
+            break;
+
+        case NETOPT_TX_START_IRQ:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_START,
+                                 ((bool *)value)[0]);
+            res = sizeof(netopt_enable_t);
+            break;
+
+        case NETOPT_TX_END_IRQ:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END,
+                                 ((bool *)value)[0]);
+            res = sizeof(netopt_enable_t);
+            break;
+
+        case NETOPT_AUTOCCA:
+            kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOCCA,
+                                 ((bool *)value)[0]);
+            res = sizeof(netopt_enable_t);
+            break;
+
+        case NETOPT_CCA_THRESHOLD:
+            if (len < sizeof(uint8_t)) {
+                res = -EOVERFLOW;
+            }
+            else {
+                kw41zrf_set_cca_threshold(dev, *((int8_t*)value));
+                res = sizeof(uint8_t);
+            }
+            break;
+
+        case NETOPT_CCA_MODE:
+            if (len < sizeof(uint8_t)) {
+                res = -EOVERFLOW;
+            }
+            else {
+                switch (*((int8_t*)value)) {
+                    case NETDEV_IEEE802154_CCA_MODE_1:
+                    case NETDEV_IEEE802154_CCA_MODE_2:
+                    case NETDEV_IEEE802154_CCA_MODE_3:
+                        kw41zrf_set_cca_mode(dev, *((int8_t*)value));
+                        res = sizeof(uint8_t);
+                        break;
+                    case NETDEV_IEEE802154_CCA_MODE_4:
+                    case NETDEV_IEEE802154_CCA_MODE_5:
+                    case NETDEV_IEEE802154_CCA_MODE_6:
+                    default:
+                        break;
+                }
+            }
+            break;
+
+        case NETOPT_RF_TESTMODE:
+#ifdef KW41ZRF_TESTMODE
+            if (len < sizeof(uint8_t)) {
+                res = -EOVERFLOW;
+            }
+            else {
+                kw41zrf_set_test_mode(dev, *((uint8_t *)value));
+                res = sizeof(uint8_t);
+            }
+#endif
+            break;
+
+        default:
+            break;
+    }
+
+    if (res == -ENOTSUP) {
+        res = netdev_ieee802154_set((netdev_ieee802154_t *)netdev, opt,
+                                     value, len);
+    }
+
+    return res;
+}
+
+/* Common CCA check handler code for sequences T and TR */
+static uint32_t _isr_event_seq_t_ccairq(kw41zrf_t *dev, uint32_t irqsts)
+{
+    uint32_t handled_irqs = 0;
+    if (irqsts & ZLL_IRQSTS_CCAIRQ_MASK) {
+        /* CCA before TX has completed */
+        handled_irqs |= ZLL_IRQSTS_CCAIRQ_MASK;
+        if (irqsts & ZLL_IRQSTS_CCA_MASK) {
+            /* Channel was determined busy */
+            DEBUG("[kw41zrf] CCA ch busy (RSSI: %d)\n",
+                  (int8_t)((ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >>
+                  ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT));
+            if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) {
+                dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY);
+            }
+        }
+        else {
+            /* Channel is idle */
+            DEBUG("[kw41zrf] CCA ch idle (RSSI: %d)\n",
+                  (int8_t)((ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >>
+                  ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT));
+            if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START) {
+                /* TX will start after CCA check succeeded */
+                dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_STARTED);
+            }
+        }
+    }
+    return handled_irqs;
+}
+
+static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts)
+{
+    uint32_t handled_irqs = 0;
+
+    if (irqsts & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) {
+        DEBUG("[kw41zrf] RXWTRMRKIRQ (R)\n");
+        handled_irqs |= ZLL_IRQSTS_RXWTRMRKIRQ_MASK;
+        if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START) {
+            dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_STARTED);
+        }
+    }
+
+    if (irqsts & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) {
+        DEBUG("[kw41zrf] FILTERFAILIRQ: %04"PRIx32"\n", ZLL->FILTERFAIL_CODE);
+        handled_irqs |= ZLL_IRQSTS_FILTERFAIL_IRQ_MASK;
+    }
+
+    if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) {
+        DEBUG("[kw41zrf] finished RX\n");
+        handled_irqs |= ZLL_IRQSTS_RXIRQ_MASK;
+        DEBUG("[kw41zrf] RX len: %3u\n",
+            (unsigned int)((ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >>
+            ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT));
+        if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_AUTOACK_MASK) {
+            DEBUG("[kw41zrf] perform TXACK\n");
+        }
+    }
+
+    if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) {
+        DEBUG("[kw41zrf] finished TXACK\n");
+        handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK;
+    }
+
+    if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) {
+        uint32_t seq_ctrl_sts = ZLL->SEQ_CTRL_STS;
+        DEBUG("[kw41zrf] SEQIRQ (R)\n");
+        handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK;
+        if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) {
+            DEBUG("[kw41zrf] RX timeout (R)\n");
+        }
+        else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) {
+            DEBUG("[kw41zrf] PLL unlock (R)\n");
+        }
+        else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) {
+            DEBUG("[kw41zrf] SW abort (R)\n");
+        }
+        else {
+            /* No error reported */
+            DEBUG("[kw41zrf] success (R)\n");
+            if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END) {
+                dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_COMPLETE);
+            }
+        }
+        kw41zrf_set_sequence(dev, dev->idle_state);
+    }
+
+    return handled_irqs;
+}
+
+static uint32_t _isr_event_seq_t(kw41zrf_t *dev, uint32_t irqsts)
+{
+    uint32_t handled_irqs = 0;
+    if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) {
+        DEBUG("[kw41zrf] finished TX (T)\n");
+        handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK;
+    }
+    if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) {
+        /* Finished T sequence */
+        DEBUG("[kw41zrf] SEQIRQ (T)\n");
+        handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK;
+        if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) {
+            dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE);
+        }
+        /* Go back to being idle */
+        kw41zrf_set_sequence(dev, dev->idle_state);
+    }
+
+    return handled_irqs;
+}
+
+/* Standalone CCA */
+static uint32_t _isr_event_seq_cca(kw41zrf_t *dev, uint32_t irqsts)
+{
+    uint32_t handled_irqs = 0;
+
+    if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) {
+        /* Finished CCA sequence */
+        DEBUG("[kw41zrf] SEQIRQ (C)\n");
+        handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK;
+        if (irqsts & ZLL_IRQSTS_CCA_MASK) {
+            DEBUG("[kw41zrf] CCA ch busy\n");
+        }
+        else {
+            DEBUG("[kw41zrf] CCA ch idle\n");
+        }
+        kw41zrf_set_sequence(dev, dev->idle_state);
+    }
+
+    return handled_irqs;
+}
+
+static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts)
+{
+    uint32_t handled_irqs = 0;
+    if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) {
+        DEBUG("[kw41zrf] finished TX (TR)\n");
+        handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK;
+        if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_RXACKRQD_MASK) {
+            DEBUG("[kw41zrf] wait for RX ACK\n");
+        }
+    }
+
+    if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) {
+        DEBUG("[kw41zrf] got RX ACK\n");
+        handled_irqs |= ZLL_IRQSTS_RXIRQ_MASK;
+    }
+
+    if (irqsts & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) {
+        DEBUG("[kw41zrf] FILTERFAILIRQ (TR): %04"PRIx32"\n", ZLL->FILTERFAIL_CODE);
+        handled_irqs |= ZLL_IRQSTS_FILTERFAIL_IRQ_MASK;
+    }
+
+    if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) {
+        uint32_t seq_ctrl_sts = ZLL->SEQ_CTRL_STS;
+        DEBUG("[kw41zrf] SEQIRQ (TR)\n");
+
+        handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK;
+        if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) {
+            if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) {
+                DEBUG("[kw41zrf] RXACK timeout (TR)\n");
+                dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_NOACK);
+                /* Clear TMR3 IRQ flag */
+                handled_irqs |= ZLL_IRQSTS_TMR3IRQ_MASK;
+            }
+            else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) {
+                DEBUG("[kw41zrf] PLL unlock (TR)\n");
+                /* TODO: there is no other error event for TX failures */
+                dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY);
+            }
+            else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) {
+                DEBUG("[kw41zrf] SW abort (TR)\n");
+                /* TODO: there is no other error event for TX failures */
+                dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY);
+            }
+            else {
+                /* No error reported */
+                DEBUG("[kw41zrf] TX success (TR)\n");
+                dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE);
+            }
+        }
+        kw41zrf_abort_rx_ops_disable(dev);
+        kw41zrf_set_sequence(dev, dev->idle_state);
+    }
+
+    return handled_irqs;
+}
+
+static uint32_t _isr_event_seq_ccca(kw41zrf_t *dev, uint32_t irqsts)
+{
+    uint32_t handled_irqs = 0;
+    if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) {
+        DEBUG("[kw41zrf] SEQIRQ (CCCA)\n");
+        handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK;
+        if (irqsts & ZLL_IRQSTS_CCA_MASK) {
+            DEBUG("[kw41zrf] CCCA ch busy\n");
+        }
+        else {
+            DEBUG("[kw41zrf] CCCA ch idle\n");
+        }
+        kw41zrf_abort_rx_ops_disable(dev);
+        kw41zrf_set_sequence(dev, dev->idle_state);
+    }
+
+    return handled_irqs;
+}
+
+static void kw41zrf_netdev_isr(netdev_t *netdev)
+{
+    kw41zrf_t *dev = (kw41zrf_t *)netdev;
+    uint32_t irqsts = ZLL->IRQSTS;
+    uint32_t handled_irqs = 0;
+    DEBUG("[kw41zrf] CTRL %08" PRIx32 ", IRQSTS %08" PRIx32 ", FILTERFAIL %08" PRIx32 "\n",
+          ZLL->PHY_CTRL, irqsts, ZLL->FILTERFAIL_CODE);
+
+    uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT;
+
+    switch (seq) {
+        case XCVSEQ_RECEIVE:
+            handled_irqs |= _isr_event_seq_r(dev, irqsts);
+            break;
+
+        case XCVSEQ_TRANSMIT:
+            /* First check CCA flags */
+            handled_irqs |= _isr_event_seq_t_ccairq(dev, irqsts);
+            /* Then TX flags */
+            handled_irqs |= _isr_event_seq_t(dev, irqsts);
+            break;
+
+        case XCVSEQ_CCA:
+            handled_irqs |= _isr_event_seq_cca(dev, irqsts);
+            break;
+
+        case XCVSEQ_TX_RX:
+            /* First check CCA flags */
+            handled_irqs |= _isr_event_seq_t_ccairq(dev, irqsts);
+            /* Then TX/RX flags */
+            handled_irqs |= _isr_event_seq_tr(dev, irqsts);
+            break;
+
+        case XCVSEQ_CONTINUOUS_CCA:
+            handled_irqs |= _isr_event_seq_ccca(dev, irqsts);
+            break;
+
+        case XCVSEQ_IDLE:
+            DEBUG("[kw41zrf] IRQ while IDLE\n");
+            break;
+
+        default:
+            DEBUG("[kw41zrf] undefined seq state in isr\n");
+            break;
+    }
+
+    /* Clear all IRQ flags now */
+    ZLL->IRQSTS = irqsts;
+
+    irqsts &= ~handled_irqs;
+
+    if (irqsts & 0x000f017f) {
+        DEBUG("[kw41zrf] Unhandled IRQs: 0x%08"PRIx32"\n",
+              (irqsts & 0x000f017f));
+    }
+
+    kw41zrf_unmask_irqs();
+}
+
+const netdev_driver_t kw41zrf_driver = {
+    .init = kw41zrf_netdev_init,
+    .send = kw41zrf_netdev_send,
+    .recv = kw41zrf_netdev_recv,
+    .get  = kw41zrf_netdev_get,
+    .set  = kw41zrf_netdev_set,
+    .isr  = kw41zrf_netdev_isr,
+};
+
+/** @} */
diff --git a/sys/auto_init/auto_init.c b/sys/auto_init/auto_init.c
index 30fc3be9de854..facce344d5a36 100644
--- a/sys/auto_init/auto_init.c
+++ b/sys/auto_init/auto_init.c
@@ -208,6 +208,11 @@ void auto_init(void)
     auto_init_kw2xrf();
 #endif
 
+#ifdef MODULE_KW41ZRF
+    extern void auto_init_kw41zrf(void);
+    auto_init_kw41zrf();
+#endif
+
 #ifdef MODULE_NETDEV_TAP
     extern void auto_init_netdev_tap(void);
     auto_init_netdev_tap();
diff --git a/sys/auto_init/netif/auto_init_kw41zrf.c b/sys/auto_init/netif/auto_init_kw41zrf.c
new file mode 100644
index 0000000000000..b90c526c5f10b
--- /dev/null
+++ b/sys/auto_init/netif/auto_init_kw41zrf.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2017 SKF AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+
+/*
+ * @ingroup auto_init_gnrc_netif
+ * @{
+ *
+ * @file
+ * @brief   Auto initialization for kw41zrf network interfaces
+ *
+ * @author  Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ */
+
+#ifdef MODULE_KW41ZRF
+
+#include "log.h"
+#include "board.h"
+#include "net/gnrc/netdev.h"
+#include "net/gnrc/netdev/ieee802154.h"
+#include "net/gnrc.h"
+
+#include "kw41zrf.h"
+
+/**
+ * @brief   Define stack parameters for the MAC layer thread
+ * @{
+ */
+#define KW41ZRF_MAC_STACKSIZE     (THREAD_STACKSIZE_DEFAULT)
+#ifndef KW41ZRF_MAC_PRIO
+#define KW41ZRF_MAC_PRIO          (GNRC_NETDEV_MAC_PRIO)
+#endif
+
+/* There is only one memory mapped transceiver in the supported SoCs, the driver
+ * does not try to take into account multiple instances of the hardware module */
+#define KW41ZRF_NUMOF 1
+
+static kw41zrf_t kw41zrf_devs[KW41ZRF_NUMOF];
+static gnrc_netdev_t gnrc_adpt[KW41ZRF_NUMOF];
+static char _kw41zrf_stacks[KW41ZRF_NUMOF][KW41ZRF_MAC_STACKSIZE];
+
+void auto_init_kw41zrf(void)
+{
+    for (unsigned i = 0; i < KW41ZRF_NUMOF; i++) {
+        LOG_DEBUG("[auto_init_netif] initializing kw41zrf #%u\n", i);
+        kw41zrf_setup(&kw41zrf_devs[i]);
+        if (gnrc_netdev_ieee802154_init(&gnrc_adpt[i], (netdev_ieee802154_t *)&kw41zrf_devs[i]) < 0) {
+            LOG_ERROR("[auto_init_netif] error initializing kw41zrf #%u\n", i);
+        }
+        else {
+            gnrc_netdev_init(_kw41zrf_stacks[i], KW41ZRF_MAC_STACKSIZE,
+                             KW41ZRF_MAC_PRIO, "kw41zrf", &gnrc_adpt[i]);
+        }
+    }
+}
+#else
+typedef int dont_be_pedantic;
+#endif /* MODULE_KW41ZRF */
+
+/** @} */