From 9725d9cf5b2d7e45f100a451d9b5ac4917cde5e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 2 May 2017 19:33:05 +0200 Subject: [PATCH] drivers/kw41zrf: Transceiver driver for the KW41Z radio This is the radio found in NXP Kinetis KW41Z, KW21Z. Only 802.15.4 mode is implemented (KW41Z also supports BLE on the same transceiver). The driver uses vendor supplied initialization code for the low level XCVR hardware, these files were imported from Kinetis Connectivity Software version 1.0.2 (framework_5.3.2) --- boards/frdm-kw41z/Makefile.dep | 4 + cpu/k60/include/vendor/MK60D10.h | 21101 +++++++--------- cpu/kw41z/Makefile | 5 +- cpu/kw41z/Makefile.include | 7 + cpu/kw41z/include/vendor/MKW21Z4.h | 198 +- cpu/kw41z/include/vendor/MKW21Z4_features.h | 1781 ++ cpu/kw41z/include/vendor/MKW31Z4.h | 201 +- cpu/kw41z/include/vendor/MKW31Z4_features.h | 2016 ++ cpu/kw41z/include/vendor/MKW41Z4.h | 200 +- cpu/kw41z/include/vendor/MKW41Z4_features.h | 2020 ++ cpu/kw41z/vendor/Common/EmbeddedTypes.h | 181 + .../Interface/fsl_os_abstraction.h | 608 + .../Interface/fsl_os_abstraction_config.h | 63 + cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile | 3 + .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c | 212 + .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h | 157 + .../vendor/XCVR/MKW41Z4/dbg_ram_capture.c | 160 + .../vendor/XCVR/MKW41Z4/dbg_ram_capture.h | 205 + .../XCVR/MKW41Z4/fsl_os_abstraction_riot.c | 27 + cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 2121 ++ cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h | 1236 + .../vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c | 207 + .../vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c | 201 + .../XCVR/MKW41Z4/fsl_xcvr_common_config.c | 623 + .../fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c | 353 + .../fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c | 341 + .../fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c | 356 + .../fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c | 341 + .../fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c | 340 + .../fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c | 353 + .../MKW41Z4/fsl_xcvr_mode_datarate_config.c | 212 + .../vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c | 343 + cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 1008 + cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 129 + .../XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c | 244 + cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c | 530 + cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h | 199 + drivers/Makefile.dep | 12 + drivers/Makefile.include | 3 + drivers/include/kw41zrf.h | 154 + drivers/kw41zrf/Makefile | 1 + drivers/kw41zrf/include/kw41zrf_getset.h | 207 + drivers/kw41zrf/include/kw41zrf_intern.h | 189 + drivers/kw41zrf/include/kw41zrf_netdev.h | 36 + drivers/kw41zrf/kw41zrf.c | 198 + drivers/kw41zrf/kw41zrf_getset.c | 355 + drivers/kw41zrf/kw41zrf_intern.c | 209 + drivers/kw41zrf/kw41zrf_netdev.c | 812 + sys/auto_init/auto_init.c | 5 + sys/auto_init/netif/auto_init_kw41zrf.c | 65 + 50 files changed, 29149 insertions(+), 11383 deletions(-) create mode 100644 cpu/kw41z/include/vendor/MKW21Z4_features.h create mode 100644 cpu/kw41z/include/vendor/MKW31Z4_features.h create mode 100644 cpu/kw41z/include/vendor/MKW41Z4_features.h create mode 100644 cpu/kw41z/vendor/Common/EmbeddedTypes.h create mode 100644 cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction.h create mode 100644 cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.h create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c create mode 100644 cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h create mode 100644 drivers/include/kw41zrf.h create mode 100644 drivers/kw41zrf/Makefile create mode 100644 drivers/kw41zrf/include/kw41zrf_getset.h create mode 100644 drivers/kw41zrf/include/kw41zrf_intern.h create mode 100644 drivers/kw41zrf/include/kw41zrf_netdev.h create mode 100644 drivers/kw41zrf/kw41zrf.c create mode 100644 drivers/kw41zrf/kw41zrf_getset.c create mode 100644 drivers/kw41zrf/kw41zrf_intern.c create mode 100644 drivers/kw41zrf/kw41zrf_netdev.c create mode 100644 sys/auto_init/netif/auto_init_kw41zrf.c diff --git a/boards/frdm-kw41z/Makefile.dep b/boards/frdm-kw41z/Makefile.dep index 9290d7a8d2773..82ce32f23ea01 100644 --- a/boards/frdm-kw41z/Makefile.dep +++ b/boards/frdm-kw41z/Makefile.dep @@ -5,3 +5,7 @@ ifneq (,$(filter saul_default,$(USEMODULE))) # USEMODULE += saul_gpio USEMODULE += saul_adc endif + +ifneq (,$(filter netdev_default gnrc_netdev_default,$(USEMODULE))) + USEMODULE += kw41zrf +endif diff --git a/cpu/k60/include/vendor/MK60D10.h b/cpu/k60/include/vendor/MK60D10.h index 0500f52ba8701..997a76dc1c1b5 100644 --- a/cpu/k60/include/vendor/MK60D10.h +++ b/cpu/k60/include/vendor/MK60D10.h @@ -1,21 +1,33 @@ /* ** ################################################################### +** Processors: MK60DN256VLL10 +** MK60DN256VLQ10 +** MK60DN256VMC10 +** MK60DN256VMD10 +** MK60DN512VLL10 +** MK60DN512VLQ10 +** MK60DN512VMC10 +** MK60DN512VMD10 +** MK60DX256VLL10 +** MK60DX256VLQ10 +** MK60DX256VMC10 +** MK60DX256VMD10 +** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** ** Reference manual: K60P144M100SF2V2RM Rev. 2, Jun 2012 -** Version: rev. 1.8, 2014-10-14 -** Build: b141015 +** Version: rev. 1.9, 2015-07-29 +** Build: b170112 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK60D10 ** -** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -26,7 +38,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -41,8 +53,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2012-01-03) @@ -68,48 +80,29 @@ ** Update of startup files - possibility to override DefaultISR added. ** - rev. 1.8 (2014-10-14) ** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0 -** - rev. 1.8-jg (2015-05-18) -** Removed BITBAND_REG macro. +** - rev. 1.9 (2015-07-29) +** Correction of backward compatibility. ** ** ################################################################### */ /*! * @file MK60D10.h - * @version 1.8-jg - * @date 2015-05-18 + * @version 1.9 + * @date 2015-07-29 * @brief CMSIS Peripheral Access Layer for MK60D10 * * CMSIS Peripheral Access Layer for MK60D10 */ -#ifdef __cplusplus -extern "C" -{ -#endif - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK60D10_H_) /* Check if memory map has not been already included */ -#define MK60D10_H_ -#define MCU_MK60D10 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK60D10 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include +#ifndef _MK60D10_H_ +#define _MK60D10_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0008u +#define MCU_MEM_MAP_VERSION_MINOR 0x0009U /** * @brief Macro to calculate address of an aliased word in the peripheral @@ -128,7 +121,8 @@ extern "C" * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -137,7 +131,7 @@ extern "C" * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -146,7 +140,7 @@ extern "C" * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers @@ -197,7 +191,7 @@ typedef enum IRQn { FTFL_IRQn = 18, /**< FTFL command complete */ Read_Collision_IRQn = 19, /**< FTFL read collision */ LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */ - LLW_IRQn = 21, /**< Low leakage wakeup */ + LLWU_IRQn = 21, /**< Low leakage wakeup */ WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */ RNG_IRQn = 23, /**< Randon number generator */ I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */ @@ -308,6 +302,108 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< Disable */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 receive complete */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 transmit complete */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 receive complete */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 transmit complete */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 receive complete */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 transmit complete */ + kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 receive complete */ + kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 transmit complete */ + kDmaRequestMux0UART4Rx = 10|0x100U, /**< UART4 receive complete */ + kDmaRequestMux0UART4Tx = 11|0x100U, /**< UART4 transmit complete */ + kDmaRequestMux0UART5Rx = 12|0x100U, /**< UART5 receive complete */ + kDmaRequestMux0UART5Tx = 13|0x100U, /**< UART5 transmit complete */ + kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 receive complete */ + kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 transmit complete */ + kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 receive complete */ + kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 transmit complete */ + kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 receive complete */ + kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 transmit complete */ + kDmaRequestMux0SPI2Rx = 20|0x100U, /**< SPI2 receive complete */ + kDmaRequestMux0SPI2Tx = 21|0x100U, /**< SPI2 transmit complete */ + kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0 transmission complete */ + kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1 transmission complete */ + kDmaRequestMux0FTM0Channel0 = 24|0x100U, /**< FTM0 channel 0 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel1 = 25|0x100U, /**< FTM0 channel 1 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel2 = 26|0x100U, /**< FTM0 channel 2 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel3 = 27|0x100U, /**< FTM0 channel 3 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel4 = 28|0x100U, /**< FTM0 channel 4 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel5 = 29|0x100U, /**< FTM0 channel 5 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel6 = 30|0x100U, /**< FTM0 channel 6 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel7 = 31|0x100U, /**< FTM0 channel 7 event (CMP or CAP) */ + kDmaRequestMux0FTM1Channel0 = 32|0x100U, /**< FTM1 channel 0 event (CMP or CAP) */ + kDmaRequestMux0FTM1Channel1 = 33|0x100U, /**< FTM1 channel 1 event (CMP or CAP) */ + kDmaRequestMux0FTM2Channel0 = 34|0x100U, /**< FTM2 channel 0 event (CMP or CAP) */ + kDmaRequestMux0FTM2Channel1 = 35|0x100U, /**< FTM2 channel 1 event (CMP or CAP) */ + kDmaRequestMux0IEEE1588Timer0 = 36|0x100U, /**< Ethernet IEEE 1588 timer 0 */ + kDmaRequestMux0IEEE1588Timer1 = 37|0x100U, /**< Ethernet IEEE 1588 timer 1 */ + kDmaRequestMux0IEEE1588Timer2 = 38|0x100U, /**< Ethernet IEEE 1588 timer 2 */ + kDmaRequestMux0IEEE1588Timer3 = 39|0x100U, /**< Ethernet IEEE 1588 timer 3 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0 conversion complete */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1 conversion complete */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0 Output */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1 Output */ + kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 Output */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0 buffer pointer reaches upper or lower limit */ + kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1 buffer pointer reaches upper or lower limit */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT end of modulation cycle event */ + kDmaRequestMux0PDB0 = 48|0x100U, /**< PDB0 programmable interrupt delay event */ + kDmaRequestMux0PortA = 49|0x100U, /**< PORTA rising, falling or both edges */ + kDmaRequestMux0PortB = 50|0x100U, /**< PORTB rising, falling or both edges */ + kDmaRequestMux0PortC = 51|0x100U, /**< PORTC rising, falling or both edges */ + kDmaRequestMux0PortD = 52|0x100U, /**< PORTD rising, falling or both edges */ + kDmaRequestMux0PortE = 53|0x100U, /**< PORTE rising, falling or both edges */ + kDmaRequestMux0AlwaysOn54 = 54|0x100U, /**< Always enabled 54 */ + kDmaRequestMux0AlwaysOn55 = 55|0x100U, /**< Always enabled 55 */ + kDmaRequestMux0AlwaysOn56 = 56|0x100U, /**< Always enabled 56 */ + kDmaRequestMux0AlwaysOn57 = 57|0x100U, /**< Always enabled 57 */ + kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< Always enabled 58 */ + kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< Always enabled 59 */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< Always enabled 60 */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< Always enabled 61 */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< Always enabled 62 */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< Always enabled 63 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -373,50 +469,7 @@ typedef struct { __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_PGA_REG(base) ((base)->PGA) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - +} ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks @@ -427,156 +480,208 @@ typedef struct { * @{ */ -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA) -#define AIPS_PACRA_REG(base) ((base)->PACRA) -#define AIPS_PACRB_REG(base) ((base)->PACRB) -#define AIPS_PACRC_REG(base) ((base)->PACRC) -#define AIPS_PACRD_REG(base) ((base)->PACRD) -#define AIPS_PACRE_REG(base) ((base)->PACRE) -#define AIPS_PACRF_REG(base) ((base)->PACRF) -#define AIPS_PACRG_REG(base) ((base)->PACRG) -#define AIPS_PACRH_REG(base) ((base)->PACRH) -#define AIPS_PACRI_REG(base) ((base)->PACRI) -#define AIPS_PACRJ_REG(base) ((base)->PACRJ) -#define AIPS_PACRK_REG(base) ((base)->PACRK) -#define AIPS_PACRL_REG(base) ((base)->PACRL) -#define AIPS_PACRM_REG(base) ((base)->PACRM) -#define AIPS_PACRN_REG(base) ((base)->PACRN) -#define AIPS_PACRO_REG(base) ((base)->PACRO) -#define AIPS_PACRP_REG(base) ((base)->PACRP) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - +} AIPS_Type; /* ---------------------------------------------------------------------------- -- AIPS Register Masks @@ -762,827 +750,1246 @@ typedef struct { * @{ */ -/* MPRA Bit Fields */ -#define AIPS_MPRA_MPL5_MASK 0x100u -#define AIPS_MPRA_MPL5_SHIFT 8 -#define AIPS_MPRA_MTW5_MASK 0x200u -#define AIPS_MPRA_MTW5_SHIFT 9 -#define AIPS_MPRA_MTR5_MASK 0x400u -#define AIPS_MPRA_MTR5_SHIFT 10 -#define AIPS_MPRA_MPL4_MASK 0x1000u -#define AIPS_MPRA_MPL4_SHIFT 12 -#define AIPS_MPRA_MTW4_MASK 0x2000u -#define AIPS_MPRA_MTW4_SHIFT 13 -#define AIPS_MPRA_MTR4_MASK 0x4000u -#define AIPS_MPRA_MTR4_SHIFT 14 -#define AIPS_MPRA_MPL3_MASK 0x10000u -#define AIPS_MPRA_MPL3_SHIFT 16 -#define AIPS_MPRA_MTW3_MASK 0x20000u -#define AIPS_MPRA_MTW3_SHIFT 17 -#define AIPS_MPRA_MTR3_MASK 0x40000u -#define AIPS_MPRA_MTR3_SHIFT 18 -#define AIPS_MPRA_MPL2_MASK 0x100000u -#define AIPS_MPRA_MPL2_SHIFT 20 -#define AIPS_MPRA_MTW2_MASK 0x200000u -#define AIPS_MPRA_MTW2_SHIFT 21 -#define AIPS_MPRA_MTR2_MASK 0x400000u -#define AIPS_MPRA_MTR2_SHIFT 22 -#define AIPS_MPRA_MPL1_MASK 0x1000000u -#define AIPS_MPRA_MPL1_SHIFT 24 -#define AIPS_MPRA_MTW1_MASK 0x2000000u -#define AIPS_MPRA_MTW1_SHIFT 25 -#define AIPS_MPRA_MTR1_MASK 0x4000000u -#define AIPS_MPRA_MTR1_SHIFT 26 -#define AIPS_MPRA_MPL0_MASK 0x10000000u -#define AIPS_MPRA_MPL0_SHIFT 28 -#define AIPS_MPRA_MTW0_MASK 0x20000000u -#define AIPS_MPRA_MTW0_SHIFT 29 -#define AIPS_MPRA_MTR0_MASK 0x40000000u -#define AIPS_MPRA_MTR0_SHIFT 30 -/* PACRA Bit Fields */ -#define AIPS_PACRA_TP7_MASK 0x1u -#define AIPS_PACRA_TP7_SHIFT 0 -#define AIPS_PACRA_WP7_MASK 0x2u -#define AIPS_PACRA_WP7_SHIFT 1 -#define AIPS_PACRA_SP7_MASK 0x4u -#define AIPS_PACRA_SP7_SHIFT 2 -#define AIPS_PACRA_TP6_MASK 0x10u -#define AIPS_PACRA_TP6_SHIFT 4 -#define AIPS_PACRA_WP6_MASK 0x20u -#define AIPS_PACRA_WP6_SHIFT 5 -#define AIPS_PACRA_SP6_MASK 0x40u -#define AIPS_PACRA_SP6_SHIFT 6 -#define AIPS_PACRA_TP5_MASK 0x100u -#define AIPS_PACRA_TP5_SHIFT 8 -#define AIPS_PACRA_WP5_MASK 0x200u -#define AIPS_PACRA_WP5_SHIFT 9 -#define AIPS_PACRA_SP5_MASK 0x400u -#define AIPS_PACRA_SP5_SHIFT 10 -#define AIPS_PACRA_TP4_MASK 0x1000u -#define AIPS_PACRA_TP4_SHIFT 12 -#define AIPS_PACRA_WP4_MASK 0x2000u -#define AIPS_PACRA_WP4_SHIFT 13 -#define AIPS_PACRA_SP4_MASK 0x4000u -#define AIPS_PACRA_SP4_SHIFT 14 -#define AIPS_PACRA_TP3_MASK 0x10000u -#define AIPS_PACRA_TP3_SHIFT 16 -#define AIPS_PACRA_WP3_MASK 0x20000u -#define AIPS_PACRA_WP3_SHIFT 17 -#define AIPS_PACRA_SP3_MASK 0x40000u -#define AIPS_PACRA_SP3_SHIFT 18 -#define AIPS_PACRA_TP2_MASK 0x100000u -#define AIPS_PACRA_TP2_SHIFT 20 -#define AIPS_PACRA_WP2_MASK 0x200000u -#define AIPS_PACRA_WP2_SHIFT 21 -#define AIPS_PACRA_SP2_MASK 0x400000u -#define AIPS_PACRA_SP2_SHIFT 22 -#define AIPS_PACRA_TP1_MASK 0x1000000u -#define AIPS_PACRA_TP1_SHIFT 24 -#define AIPS_PACRA_WP1_MASK 0x2000000u -#define AIPS_PACRA_WP1_SHIFT 25 -#define AIPS_PACRA_SP1_MASK 0x4000000u -#define AIPS_PACRA_SP1_SHIFT 26 -#define AIPS_PACRA_TP0_MASK 0x10000000u -#define AIPS_PACRA_TP0_SHIFT 28 -#define AIPS_PACRA_WP0_MASK 0x20000000u -#define AIPS_PACRA_WP0_SHIFT 29 -#define AIPS_PACRA_SP0_MASK 0x40000000u -#define AIPS_PACRA_SP0_SHIFT 30 -/* PACRB Bit Fields */ -#define AIPS_PACRB_TP7_MASK 0x1u -#define AIPS_PACRB_TP7_SHIFT 0 -#define AIPS_PACRB_WP7_MASK 0x2u -#define AIPS_PACRB_WP7_SHIFT 1 -#define AIPS_PACRB_SP7_MASK 0x4u -#define AIPS_PACRB_SP7_SHIFT 2 -#define AIPS_PACRB_TP6_MASK 0x10u -#define AIPS_PACRB_TP6_SHIFT 4 -#define AIPS_PACRB_WP6_MASK 0x20u -#define AIPS_PACRB_WP6_SHIFT 5 -#define AIPS_PACRB_SP6_MASK 0x40u -#define AIPS_PACRB_SP6_SHIFT 6 -#define AIPS_PACRB_TP5_MASK 0x100u -#define AIPS_PACRB_TP5_SHIFT 8 -#define AIPS_PACRB_WP5_MASK 0x200u -#define AIPS_PACRB_WP5_SHIFT 9 -#define AIPS_PACRB_SP5_MASK 0x400u -#define AIPS_PACRB_SP5_SHIFT 10 -#define AIPS_PACRB_TP4_MASK 0x1000u -#define AIPS_PACRB_TP4_SHIFT 12 -#define AIPS_PACRB_WP4_MASK 0x2000u -#define AIPS_PACRB_WP4_SHIFT 13 -#define AIPS_PACRB_SP4_MASK 0x4000u -#define AIPS_PACRB_SP4_SHIFT 14 -#define AIPS_PACRB_TP3_MASK 0x10000u -#define AIPS_PACRB_TP3_SHIFT 16 -#define AIPS_PACRB_WP3_MASK 0x20000u -#define AIPS_PACRB_WP3_SHIFT 17 -#define AIPS_PACRB_SP3_MASK 0x40000u -#define AIPS_PACRB_SP3_SHIFT 18 -#define AIPS_PACRB_TP2_MASK 0x100000u -#define AIPS_PACRB_TP2_SHIFT 20 -#define AIPS_PACRB_WP2_MASK 0x200000u -#define AIPS_PACRB_WP2_SHIFT 21 -#define AIPS_PACRB_SP2_MASK 0x400000u -#define AIPS_PACRB_SP2_SHIFT 22 -#define AIPS_PACRB_TP1_MASK 0x1000000u -#define AIPS_PACRB_TP1_SHIFT 24 -#define AIPS_PACRB_WP1_MASK 0x2000000u -#define AIPS_PACRB_WP1_SHIFT 25 -#define AIPS_PACRB_SP1_MASK 0x4000000u -#define AIPS_PACRB_SP1_SHIFT 26 -#define AIPS_PACRB_TP0_MASK 0x10000000u -#define AIPS_PACRB_TP0_SHIFT 28 -#define AIPS_PACRB_WP0_MASK 0x20000000u -#define AIPS_PACRB_WP0_SHIFT 29 -#define AIPS_PACRB_SP0_MASK 0x40000000u -#define AIPS_PACRB_SP0_SHIFT 30 -/* PACRC Bit Fields */ -#define AIPS_PACRC_TP7_MASK 0x1u -#define AIPS_PACRC_TP7_SHIFT 0 -#define AIPS_PACRC_WP7_MASK 0x2u -#define AIPS_PACRC_WP7_SHIFT 1 -#define AIPS_PACRC_SP7_MASK 0x4u -#define AIPS_PACRC_SP7_SHIFT 2 -#define AIPS_PACRC_TP6_MASK 0x10u -#define AIPS_PACRC_TP6_SHIFT 4 -#define AIPS_PACRC_WP6_MASK 0x20u -#define AIPS_PACRC_WP6_SHIFT 5 -#define AIPS_PACRC_SP6_MASK 0x40u -#define AIPS_PACRC_SP6_SHIFT 6 -#define AIPS_PACRC_TP5_MASK 0x100u -#define AIPS_PACRC_TP5_SHIFT 8 -#define AIPS_PACRC_WP5_MASK 0x200u -#define AIPS_PACRC_WP5_SHIFT 9 -#define AIPS_PACRC_SP5_MASK 0x400u -#define AIPS_PACRC_SP5_SHIFT 10 -#define AIPS_PACRC_TP4_MASK 0x1000u -#define AIPS_PACRC_TP4_SHIFT 12 -#define AIPS_PACRC_WP4_MASK 0x2000u -#define AIPS_PACRC_WP4_SHIFT 13 -#define AIPS_PACRC_SP4_MASK 0x4000u -#define AIPS_PACRC_SP4_SHIFT 14 -#define AIPS_PACRC_TP3_MASK 0x10000u -#define AIPS_PACRC_TP3_SHIFT 16 -#define AIPS_PACRC_WP3_MASK 0x20000u -#define AIPS_PACRC_WP3_SHIFT 17 -#define AIPS_PACRC_SP3_MASK 0x40000u -#define AIPS_PACRC_SP3_SHIFT 18 -#define AIPS_PACRC_TP2_MASK 0x100000u -#define AIPS_PACRC_TP2_SHIFT 20 -#define AIPS_PACRC_WP2_MASK 0x200000u -#define AIPS_PACRC_WP2_SHIFT 21 -#define AIPS_PACRC_SP2_MASK 0x400000u -#define AIPS_PACRC_SP2_SHIFT 22 -#define AIPS_PACRC_TP1_MASK 0x1000000u -#define AIPS_PACRC_TP1_SHIFT 24 -#define AIPS_PACRC_WP1_MASK 0x2000000u -#define AIPS_PACRC_WP1_SHIFT 25 -#define AIPS_PACRC_SP1_MASK 0x4000000u -#define AIPS_PACRC_SP1_SHIFT 26 -#define AIPS_PACRC_TP0_MASK 0x10000000u -#define AIPS_PACRC_TP0_SHIFT 28 -#define AIPS_PACRC_WP0_MASK 0x20000000u -#define AIPS_PACRC_WP0_SHIFT 29 -#define AIPS_PACRC_SP0_MASK 0x40000000u -#define AIPS_PACRC_SP0_SHIFT 30 -/* PACRD Bit Fields */ -#define AIPS_PACRD_TP7_MASK 0x1u -#define AIPS_PACRD_TP7_SHIFT 0 -#define AIPS_PACRD_WP7_MASK 0x2u -#define AIPS_PACRD_WP7_SHIFT 1 -#define AIPS_PACRD_SP7_MASK 0x4u -#define AIPS_PACRD_SP7_SHIFT 2 -#define AIPS_PACRD_TP6_MASK 0x10u -#define AIPS_PACRD_TP6_SHIFT 4 -#define AIPS_PACRD_WP6_MASK 0x20u -#define AIPS_PACRD_WP6_SHIFT 5 -#define AIPS_PACRD_SP6_MASK 0x40u -#define AIPS_PACRD_SP6_SHIFT 6 -#define AIPS_PACRD_TP5_MASK 0x100u -#define AIPS_PACRD_TP5_SHIFT 8 -#define AIPS_PACRD_WP5_MASK 0x200u -#define AIPS_PACRD_WP5_SHIFT 9 -#define AIPS_PACRD_SP5_MASK 0x400u -#define AIPS_PACRD_SP5_SHIFT 10 -#define AIPS_PACRD_TP4_MASK 0x1000u -#define AIPS_PACRD_TP4_SHIFT 12 -#define AIPS_PACRD_WP4_MASK 0x2000u -#define AIPS_PACRD_WP4_SHIFT 13 -#define AIPS_PACRD_SP4_MASK 0x4000u -#define AIPS_PACRD_SP4_SHIFT 14 -#define AIPS_PACRD_TP3_MASK 0x10000u -#define AIPS_PACRD_TP3_SHIFT 16 -#define AIPS_PACRD_WP3_MASK 0x20000u -#define AIPS_PACRD_WP3_SHIFT 17 -#define AIPS_PACRD_SP3_MASK 0x40000u -#define AIPS_PACRD_SP3_SHIFT 18 -#define AIPS_PACRD_TP2_MASK 0x100000u -#define AIPS_PACRD_TP2_SHIFT 20 -#define AIPS_PACRD_WP2_MASK 0x200000u -#define AIPS_PACRD_WP2_SHIFT 21 -#define AIPS_PACRD_SP2_MASK 0x400000u -#define AIPS_PACRD_SP2_SHIFT 22 -#define AIPS_PACRD_TP1_MASK 0x1000000u -#define AIPS_PACRD_TP1_SHIFT 24 -#define AIPS_PACRD_WP1_MASK 0x2000000u -#define AIPS_PACRD_WP1_SHIFT 25 -#define AIPS_PACRD_SP1_MASK 0x4000000u -#define AIPS_PACRD_SP1_SHIFT 26 -#define AIPS_PACRD_TP0_MASK 0x10000000u -#define AIPS_PACRD_TP0_SHIFT 28 -#define AIPS_PACRD_WP0_MASK 0x20000000u -#define AIPS_PACRD_WP0_SHIFT 29 -#define AIPS_PACRD_SP0_MASK 0x40000000u -#define AIPS_PACRD_SP0_SHIFT 30 -/* PACRE Bit Fields */ -#define AIPS_PACRE_TP7_MASK 0x1u -#define AIPS_PACRE_TP7_SHIFT 0 -#define AIPS_PACRE_WP7_MASK 0x2u -#define AIPS_PACRE_WP7_SHIFT 1 -#define AIPS_PACRE_SP7_MASK 0x4u -#define AIPS_PACRE_SP7_SHIFT 2 -#define AIPS_PACRE_TP6_MASK 0x10u -#define AIPS_PACRE_TP6_SHIFT 4 -#define AIPS_PACRE_WP6_MASK 0x20u -#define AIPS_PACRE_WP6_SHIFT 5 -#define AIPS_PACRE_SP6_MASK 0x40u -#define AIPS_PACRE_SP6_SHIFT 6 -#define AIPS_PACRE_TP5_MASK 0x100u -#define AIPS_PACRE_TP5_SHIFT 8 -#define AIPS_PACRE_WP5_MASK 0x200u -#define AIPS_PACRE_WP5_SHIFT 9 -#define AIPS_PACRE_SP5_MASK 0x400u -#define AIPS_PACRE_SP5_SHIFT 10 -#define AIPS_PACRE_TP4_MASK 0x1000u -#define AIPS_PACRE_TP4_SHIFT 12 -#define AIPS_PACRE_WP4_MASK 0x2000u -#define AIPS_PACRE_WP4_SHIFT 13 -#define AIPS_PACRE_SP4_MASK 0x4000u -#define AIPS_PACRE_SP4_SHIFT 14 -#define AIPS_PACRE_TP3_MASK 0x10000u -#define AIPS_PACRE_TP3_SHIFT 16 -#define AIPS_PACRE_WP3_MASK 0x20000u -#define AIPS_PACRE_WP3_SHIFT 17 -#define AIPS_PACRE_SP3_MASK 0x40000u -#define AIPS_PACRE_SP3_SHIFT 18 -#define AIPS_PACRE_TP2_MASK 0x100000u -#define AIPS_PACRE_TP2_SHIFT 20 -#define AIPS_PACRE_WP2_MASK 0x200000u -#define AIPS_PACRE_WP2_SHIFT 21 -#define AIPS_PACRE_SP2_MASK 0x400000u -#define AIPS_PACRE_SP2_SHIFT 22 -#define AIPS_PACRE_TP1_MASK 0x1000000u -#define AIPS_PACRE_TP1_SHIFT 24 -#define AIPS_PACRE_WP1_MASK 0x2000000u -#define AIPS_PACRE_WP1_SHIFT 25 -#define AIPS_PACRE_SP1_MASK 0x4000000u -#define AIPS_PACRE_SP1_SHIFT 26 -#define AIPS_PACRE_TP0_MASK 0x10000000u -#define AIPS_PACRE_TP0_SHIFT 28 -#define AIPS_PACRE_WP0_MASK 0x20000000u -#define AIPS_PACRE_WP0_SHIFT 29 -#define AIPS_PACRE_SP0_MASK 0x40000000u -#define AIPS_PACRE_SP0_SHIFT 30 -/* PACRF Bit Fields */ -#define AIPS_PACRF_TP7_MASK 0x1u -#define AIPS_PACRF_TP7_SHIFT 0 -#define AIPS_PACRF_WP7_MASK 0x2u -#define AIPS_PACRF_WP7_SHIFT 1 -#define AIPS_PACRF_SP7_MASK 0x4u -#define AIPS_PACRF_SP7_SHIFT 2 -#define AIPS_PACRF_TP6_MASK 0x10u -#define AIPS_PACRF_TP6_SHIFT 4 -#define AIPS_PACRF_WP6_MASK 0x20u -#define AIPS_PACRF_WP6_SHIFT 5 -#define AIPS_PACRF_SP6_MASK 0x40u -#define AIPS_PACRF_SP6_SHIFT 6 -#define AIPS_PACRF_TP5_MASK 0x100u -#define AIPS_PACRF_TP5_SHIFT 8 -#define AIPS_PACRF_WP5_MASK 0x200u -#define AIPS_PACRF_WP5_SHIFT 9 -#define AIPS_PACRF_SP5_MASK 0x400u -#define AIPS_PACRF_SP5_SHIFT 10 -#define AIPS_PACRF_TP4_MASK 0x1000u -#define AIPS_PACRF_TP4_SHIFT 12 -#define AIPS_PACRF_WP4_MASK 0x2000u -#define AIPS_PACRF_WP4_SHIFT 13 -#define AIPS_PACRF_SP4_MASK 0x4000u -#define AIPS_PACRF_SP4_SHIFT 14 -#define AIPS_PACRF_TP3_MASK 0x10000u -#define AIPS_PACRF_TP3_SHIFT 16 -#define AIPS_PACRF_WP3_MASK 0x20000u -#define AIPS_PACRF_WP3_SHIFT 17 -#define AIPS_PACRF_SP3_MASK 0x40000u -#define AIPS_PACRF_SP3_SHIFT 18 -#define AIPS_PACRF_TP2_MASK 0x100000u -#define AIPS_PACRF_TP2_SHIFT 20 -#define AIPS_PACRF_WP2_MASK 0x200000u -#define AIPS_PACRF_WP2_SHIFT 21 -#define AIPS_PACRF_SP2_MASK 0x400000u -#define AIPS_PACRF_SP2_SHIFT 22 -#define AIPS_PACRF_TP1_MASK 0x1000000u -#define AIPS_PACRF_TP1_SHIFT 24 -#define AIPS_PACRF_WP1_MASK 0x2000000u -#define AIPS_PACRF_WP1_SHIFT 25 -#define AIPS_PACRF_SP1_MASK 0x4000000u -#define AIPS_PACRF_SP1_SHIFT 26 -#define AIPS_PACRF_TP0_MASK 0x10000000u -#define AIPS_PACRF_TP0_SHIFT 28 -#define AIPS_PACRF_WP0_MASK 0x20000000u -#define AIPS_PACRF_WP0_SHIFT 29 -#define AIPS_PACRF_SP0_MASK 0x40000000u -#define AIPS_PACRF_SP0_SHIFT 30 -/* PACRG Bit Fields */ -#define AIPS_PACRG_TP7_MASK 0x1u -#define AIPS_PACRG_TP7_SHIFT 0 -#define AIPS_PACRG_WP7_MASK 0x2u -#define AIPS_PACRG_WP7_SHIFT 1 -#define AIPS_PACRG_SP7_MASK 0x4u -#define AIPS_PACRG_SP7_SHIFT 2 -#define AIPS_PACRG_TP6_MASK 0x10u -#define AIPS_PACRG_TP6_SHIFT 4 -#define AIPS_PACRG_WP6_MASK 0x20u -#define AIPS_PACRG_WP6_SHIFT 5 -#define AIPS_PACRG_SP6_MASK 0x40u -#define AIPS_PACRG_SP6_SHIFT 6 -#define AIPS_PACRG_TP5_MASK 0x100u -#define AIPS_PACRG_TP5_SHIFT 8 -#define AIPS_PACRG_WP5_MASK 0x200u -#define AIPS_PACRG_WP5_SHIFT 9 -#define AIPS_PACRG_SP5_MASK 0x400u -#define AIPS_PACRG_SP5_SHIFT 10 -#define AIPS_PACRG_TP4_MASK 0x1000u -#define AIPS_PACRG_TP4_SHIFT 12 -#define AIPS_PACRG_WP4_MASK 0x2000u -#define AIPS_PACRG_WP4_SHIFT 13 -#define AIPS_PACRG_SP4_MASK 0x4000u -#define AIPS_PACRG_SP4_SHIFT 14 -#define AIPS_PACRG_TP3_MASK 0x10000u -#define AIPS_PACRG_TP3_SHIFT 16 -#define AIPS_PACRG_WP3_MASK 0x20000u -#define AIPS_PACRG_WP3_SHIFT 17 -#define AIPS_PACRG_SP3_MASK 0x40000u -#define AIPS_PACRG_SP3_SHIFT 18 -#define AIPS_PACRG_TP2_MASK 0x100000u -#define AIPS_PACRG_TP2_SHIFT 20 -#define AIPS_PACRG_WP2_MASK 0x200000u -#define AIPS_PACRG_WP2_SHIFT 21 -#define AIPS_PACRG_SP2_MASK 0x400000u -#define AIPS_PACRG_SP2_SHIFT 22 -#define AIPS_PACRG_TP1_MASK 0x1000000u -#define AIPS_PACRG_TP1_SHIFT 24 -#define AIPS_PACRG_WP1_MASK 0x2000000u -#define AIPS_PACRG_WP1_SHIFT 25 -#define AIPS_PACRG_SP1_MASK 0x4000000u -#define AIPS_PACRG_SP1_SHIFT 26 -#define AIPS_PACRG_TP0_MASK 0x10000000u -#define AIPS_PACRG_TP0_SHIFT 28 -#define AIPS_PACRG_WP0_MASK 0x20000000u -#define AIPS_PACRG_WP0_SHIFT 29 -#define AIPS_PACRG_SP0_MASK 0x40000000u -#define AIPS_PACRG_SP0_SHIFT 30 -/* PACRH Bit Fields */ -#define AIPS_PACRH_TP7_MASK 0x1u -#define AIPS_PACRH_TP7_SHIFT 0 -#define AIPS_PACRH_WP7_MASK 0x2u -#define AIPS_PACRH_WP7_SHIFT 1 -#define AIPS_PACRH_SP7_MASK 0x4u -#define AIPS_PACRH_SP7_SHIFT 2 -#define AIPS_PACRH_TP6_MASK 0x10u -#define AIPS_PACRH_TP6_SHIFT 4 -#define AIPS_PACRH_WP6_MASK 0x20u -#define AIPS_PACRH_WP6_SHIFT 5 -#define AIPS_PACRH_SP6_MASK 0x40u -#define AIPS_PACRH_SP6_SHIFT 6 -#define AIPS_PACRH_TP5_MASK 0x100u -#define AIPS_PACRH_TP5_SHIFT 8 -#define AIPS_PACRH_WP5_MASK 0x200u -#define AIPS_PACRH_WP5_SHIFT 9 -#define AIPS_PACRH_SP5_MASK 0x400u -#define AIPS_PACRH_SP5_SHIFT 10 -#define AIPS_PACRH_TP4_MASK 0x1000u -#define AIPS_PACRH_TP4_SHIFT 12 -#define AIPS_PACRH_WP4_MASK 0x2000u -#define AIPS_PACRH_WP4_SHIFT 13 -#define AIPS_PACRH_SP4_MASK 0x4000u -#define AIPS_PACRH_SP4_SHIFT 14 -#define AIPS_PACRH_TP3_MASK 0x10000u -#define AIPS_PACRH_TP3_SHIFT 16 -#define AIPS_PACRH_WP3_MASK 0x20000u -#define AIPS_PACRH_WP3_SHIFT 17 -#define AIPS_PACRH_SP3_MASK 0x40000u -#define AIPS_PACRH_SP3_SHIFT 18 -#define AIPS_PACRH_TP2_MASK 0x100000u -#define AIPS_PACRH_TP2_SHIFT 20 -#define AIPS_PACRH_WP2_MASK 0x200000u -#define AIPS_PACRH_WP2_SHIFT 21 -#define AIPS_PACRH_SP2_MASK 0x400000u -#define AIPS_PACRH_SP2_SHIFT 22 -#define AIPS_PACRH_TP1_MASK 0x1000000u -#define AIPS_PACRH_TP1_SHIFT 24 -#define AIPS_PACRH_WP1_MASK 0x2000000u -#define AIPS_PACRH_WP1_SHIFT 25 -#define AIPS_PACRH_SP1_MASK 0x4000000u -#define AIPS_PACRH_SP1_SHIFT 26 -#define AIPS_PACRH_TP0_MASK 0x10000000u -#define AIPS_PACRH_TP0_SHIFT 28 -#define AIPS_PACRH_WP0_MASK 0x20000000u -#define AIPS_PACRH_WP0_SHIFT 29 -#define AIPS_PACRH_SP0_MASK 0x40000000u -#define AIPS_PACRH_SP0_SHIFT 30 -/* PACRI Bit Fields */ -#define AIPS_PACRI_TP7_MASK 0x1u -#define AIPS_PACRI_TP7_SHIFT 0 -#define AIPS_PACRI_WP7_MASK 0x2u -#define AIPS_PACRI_WP7_SHIFT 1 -#define AIPS_PACRI_SP7_MASK 0x4u -#define AIPS_PACRI_SP7_SHIFT 2 -#define AIPS_PACRI_TP6_MASK 0x10u -#define AIPS_PACRI_TP6_SHIFT 4 -#define AIPS_PACRI_WP6_MASK 0x20u -#define AIPS_PACRI_WP6_SHIFT 5 -#define AIPS_PACRI_SP6_MASK 0x40u -#define AIPS_PACRI_SP6_SHIFT 6 -#define AIPS_PACRI_TP5_MASK 0x100u -#define AIPS_PACRI_TP5_SHIFT 8 -#define AIPS_PACRI_WP5_MASK 0x200u -#define AIPS_PACRI_WP5_SHIFT 9 -#define AIPS_PACRI_SP5_MASK 0x400u -#define AIPS_PACRI_SP5_SHIFT 10 -#define AIPS_PACRI_TP4_MASK 0x1000u -#define AIPS_PACRI_TP4_SHIFT 12 -#define AIPS_PACRI_WP4_MASK 0x2000u -#define AIPS_PACRI_WP4_SHIFT 13 -#define AIPS_PACRI_SP4_MASK 0x4000u -#define AIPS_PACRI_SP4_SHIFT 14 -#define AIPS_PACRI_TP3_MASK 0x10000u -#define AIPS_PACRI_TP3_SHIFT 16 -#define AIPS_PACRI_WP3_MASK 0x20000u -#define AIPS_PACRI_WP3_SHIFT 17 -#define AIPS_PACRI_SP3_MASK 0x40000u -#define AIPS_PACRI_SP3_SHIFT 18 -#define AIPS_PACRI_TP2_MASK 0x100000u -#define AIPS_PACRI_TP2_SHIFT 20 -#define AIPS_PACRI_WP2_MASK 0x200000u -#define AIPS_PACRI_WP2_SHIFT 21 -#define AIPS_PACRI_SP2_MASK 0x400000u -#define AIPS_PACRI_SP2_SHIFT 22 -#define AIPS_PACRI_TP1_MASK 0x1000000u -#define AIPS_PACRI_TP1_SHIFT 24 -#define AIPS_PACRI_WP1_MASK 0x2000000u -#define AIPS_PACRI_WP1_SHIFT 25 -#define AIPS_PACRI_SP1_MASK 0x4000000u -#define AIPS_PACRI_SP1_SHIFT 26 -#define AIPS_PACRI_TP0_MASK 0x10000000u -#define AIPS_PACRI_TP0_SHIFT 28 -#define AIPS_PACRI_WP0_MASK 0x20000000u -#define AIPS_PACRI_WP0_SHIFT 29 -#define AIPS_PACRI_SP0_MASK 0x40000000u -#define AIPS_PACRI_SP0_SHIFT 30 -/* PACRJ Bit Fields */ -#define AIPS_PACRJ_TP7_MASK 0x1u -#define AIPS_PACRJ_TP7_SHIFT 0 -#define AIPS_PACRJ_WP7_MASK 0x2u -#define AIPS_PACRJ_WP7_SHIFT 1 -#define AIPS_PACRJ_SP7_MASK 0x4u -#define AIPS_PACRJ_SP7_SHIFT 2 -#define AIPS_PACRJ_TP6_MASK 0x10u -#define AIPS_PACRJ_TP6_SHIFT 4 -#define AIPS_PACRJ_WP6_MASK 0x20u -#define AIPS_PACRJ_WP6_SHIFT 5 -#define AIPS_PACRJ_SP6_MASK 0x40u -#define AIPS_PACRJ_SP6_SHIFT 6 -#define AIPS_PACRJ_TP5_MASK 0x100u -#define AIPS_PACRJ_TP5_SHIFT 8 -#define AIPS_PACRJ_WP5_MASK 0x200u -#define AIPS_PACRJ_WP5_SHIFT 9 -#define AIPS_PACRJ_SP5_MASK 0x400u -#define AIPS_PACRJ_SP5_SHIFT 10 -#define AIPS_PACRJ_TP4_MASK 0x1000u -#define AIPS_PACRJ_TP4_SHIFT 12 -#define AIPS_PACRJ_WP4_MASK 0x2000u -#define AIPS_PACRJ_WP4_SHIFT 13 -#define AIPS_PACRJ_SP4_MASK 0x4000u -#define AIPS_PACRJ_SP4_SHIFT 14 -#define AIPS_PACRJ_TP3_MASK 0x10000u -#define AIPS_PACRJ_TP3_SHIFT 16 -#define AIPS_PACRJ_WP3_MASK 0x20000u -#define AIPS_PACRJ_WP3_SHIFT 17 -#define AIPS_PACRJ_SP3_MASK 0x40000u -#define AIPS_PACRJ_SP3_SHIFT 18 -#define AIPS_PACRJ_TP2_MASK 0x100000u -#define AIPS_PACRJ_TP2_SHIFT 20 -#define AIPS_PACRJ_WP2_MASK 0x200000u -#define AIPS_PACRJ_WP2_SHIFT 21 -#define AIPS_PACRJ_SP2_MASK 0x400000u -#define AIPS_PACRJ_SP2_SHIFT 22 -#define AIPS_PACRJ_TP1_MASK 0x1000000u -#define AIPS_PACRJ_TP1_SHIFT 24 -#define AIPS_PACRJ_WP1_MASK 0x2000000u -#define AIPS_PACRJ_WP1_SHIFT 25 -#define AIPS_PACRJ_SP1_MASK 0x4000000u -#define AIPS_PACRJ_SP1_SHIFT 26 -#define AIPS_PACRJ_TP0_MASK 0x10000000u -#define AIPS_PACRJ_TP0_SHIFT 28 -#define AIPS_PACRJ_WP0_MASK 0x20000000u -#define AIPS_PACRJ_WP0_SHIFT 29 -#define AIPS_PACRJ_SP0_MASK 0x40000000u -#define AIPS_PACRJ_SP0_SHIFT 30 -/* PACRK Bit Fields */ -#define AIPS_PACRK_TP7_MASK 0x1u -#define AIPS_PACRK_TP7_SHIFT 0 -#define AIPS_PACRK_WP7_MASK 0x2u -#define AIPS_PACRK_WP7_SHIFT 1 -#define AIPS_PACRK_SP7_MASK 0x4u -#define AIPS_PACRK_SP7_SHIFT 2 -#define AIPS_PACRK_TP6_MASK 0x10u -#define AIPS_PACRK_TP6_SHIFT 4 -#define AIPS_PACRK_WP6_MASK 0x20u -#define AIPS_PACRK_WP6_SHIFT 5 -#define AIPS_PACRK_SP6_MASK 0x40u -#define AIPS_PACRK_SP6_SHIFT 6 -#define AIPS_PACRK_TP5_MASK 0x100u -#define AIPS_PACRK_TP5_SHIFT 8 -#define AIPS_PACRK_WP5_MASK 0x200u -#define AIPS_PACRK_WP5_SHIFT 9 -#define AIPS_PACRK_SP5_MASK 0x400u -#define AIPS_PACRK_SP5_SHIFT 10 -#define AIPS_PACRK_TP4_MASK 0x1000u -#define AIPS_PACRK_TP4_SHIFT 12 -#define AIPS_PACRK_WP4_MASK 0x2000u -#define AIPS_PACRK_WP4_SHIFT 13 -#define AIPS_PACRK_SP4_MASK 0x4000u -#define AIPS_PACRK_SP4_SHIFT 14 -#define AIPS_PACRK_TP3_MASK 0x10000u -#define AIPS_PACRK_TP3_SHIFT 16 -#define AIPS_PACRK_WP3_MASK 0x20000u -#define AIPS_PACRK_WP3_SHIFT 17 -#define AIPS_PACRK_SP3_MASK 0x40000u -#define AIPS_PACRK_SP3_SHIFT 18 -#define AIPS_PACRK_TP2_MASK 0x100000u -#define AIPS_PACRK_TP2_SHIFT 20 -#define AIPS_PACRK_WP2_MASK 0x200000u -#define AIPS_PACRK_WP2_SHIFT 21 -#define AIPS_PACRK_SP2_MASK 0x400000u -#define AIPS_PACRK_SP2_SHIFT 22 -#define AIPS_PACRK_TP1_MASK 0x1000000u -#define AIPS_PACRK_TP1_SHIFT 24 -#define AIPS_PACRK_WP1_MASK 0x2000000u -#define AIPS_PACRK_WP1_SHIFT 25 -#define AIPS_PACRK_SP1_MASK 0x4000000u -#define AIPS_PACRK_SP1_SHIFT 26 -#define AIPS_PACRK_TP0_MASK 0x10000000u -#define AIPS_PACRK_TP0_SHIFT 28 -#define AIPS_PACRK_WP0_MASK 0x20000000u -#define AIPS_PACRK_WP0_SHIFT 29 -#define AIPS_PACRK_SP0_MASK 0x40000000u -#define AIPS_PACRK_SP0_SHIFT 30 -/* PACRL Bit Fields */ -#define AIPS_PACRL_TP7_MASK 0x1u -#define AIPS_PACRL_TP7_SHIFT 0 -#define AIPS_PACRL_WP7_MASK 0x2u -#define AIPS_PACRL_WP7_SHIFT 1 -#define AIPS_PACRL_SP7_MASK 0x4u -#define AIPS_PACRL_SP7_SHIFT 2 -#define AIPS_PACRL_TP6_MASK 0x10u -#define AIPS_PACRL_TP6_SHIFT 4 -#define AIPS_PACRL_WP6_MASK 0x20u -#define AIPS_PACRL_WP6_SHIFT 5 -#define AIPS_PACRL_SP6_MASK 0x40u -#define AIPS_PACRL_SP6_SHIFT 6 -#define AIPS_PACRL_TP5_MASK 0x100u -#define AIPS_PACRL_TP5_SHIFT 8 -#define AIPS_PACRL_WP5_MASK 0x200u -#define AIPS_PACRL_WP5_SHIFT 9 -#define AIPS_PACRL_SP5_MASK 0x400u -#define AIPS_PACRL_SP5_SHIFT 10 -#define AIPS_PACRL_TP4_MASK 0x1000u -#define AIPS_PACRL_TP4_SHIFT 12 -#define AIPS_PACRL_WP4_MASK 0x2000u -#define AIPS_PACRL_WP4_SHIFT 13 -#define AIPS_PACRL_SP4_MASK 0x4000u -#define AIPS_PACRL_SP4_SHIFT 14 -#define AIPS_PACRL_TP3_MASK 0x10000u -#define AIPS_PACRL_TP3_SHIFT 16 -#define AIPS_PACRL_WP3_MASK 0x20000u -#define AIPS_PACRL_WP3_SHIFT 17 -#define AIPS_PACRL_SP3_MASK 0x40000u -#define AIPS_PACRL_SP3_SHIFT 18 -#define AIPS_PACRL_TP2_MASK 0x100000u -#define AIPS_PACRL_TP2_SHIFT 20 -#define AIPS_PACRL_WP2_MASK 0x200000u -#define AIPS_PACRL_WP2_SHIFT 21 -#define AIPS_PACRL_SP2_MASK 0x400000u -#define AIPS_PACRL_SP2_SHIFT 22 -#define AIPS_PACRL_TP1_MASK 0x1000000u -#define AIPS_PACRL_TP1_SHIFT 24 -#define AIPS_PACRL_WP1_MASK 0x2000000u -#define AIPS_PACRL_WP1_SHIFT 25 -#define AIPS_PACRL_SP1_MASK 0x4000000u -#define AIPS_PACRL_SP1_SHIFT 26 -#define AIPS_PACRL_TP0_MASK 0x10000000u -#define AIPS_PACRL_TP0_SHIFT 28 -#define AIPS_PACRL_WP0_MASK 0x20000000u -#define AIPS_PACRL_WP0_SHIFT 29 -#define AIPS_PACRL_SP0_MASK 0x40000000u -#define AIPS_PACRL_SP0_SHIFT 30 -/* PACRM Bit Fields */ -#define AIPS_PACRM_TP7_MASK 0x1u -#define AIPS_PACRM_TP7_SHIFT 0 -#define AIPS_PACRM_WP7_MASK 0x2u -#define AIPS_PACRM_WP7_SHIFT 1 -#define AIPS_PACRM_SP7_MASK 0x4u -#define AIPS_PACRM_SP7_SHIFT 2 -#define AIPS_PACRM_TP6_MASK 0x10u -#define AIPS_PACRM_TP6_SHIFT 4 -#define AIPS_PACRM_WP6_MASK 0x20u -#define AIPS_PACRM_WP6_SHIFT 5 -#define AIPS_PACRM_SP6_MASK 0x40u -#define AIPS_PACRM_SP6_SHIFT 6 -#define AIPS_PACRM_TP5_MASK 0x100u -#define AIPS_PACRM_TP5_SHIFT 8 -#define AIPS_PACRM_WP5_MASK 0x200u -#define AIPS_PACRM_WP5_SHIFT 9 -#define AIPS_PACRM_SP5_MASK 0x400u -#define AIPS_PACRM_SP5_SHIFT 10 -#define AIPS_PACRM_TP4_MASK 0x1000u -#define AIPS_PACRM_TP4_SHIFT 12 -#define AIPS_PACRM_WP4_MASK 0x2000u -#define AIPS_PACRM_WP4_SHIFT 13 -#define AIPS_PACRM_SP4_MASK 0x4000u -#define AIPS_PACRM_SP4_SHIFT 14 -#define AIPS_PACRM_TP3_MASK 0x10000u -#define AIPS_PACRM_TP3_SHIFT 16 -#define AIPS_PACRM_WP3_MASK 0x20000u -#define AIPS_PACRM_WP3_SHIFT 17 -#define AIPS_PACRM_SP3_MASK 0x40000u -#define AIPS_PACRM_SP3_SHIFT 18 -#define AIPS_PACRM_TP2_MASK 0x100000u -#define AIPS_PACRM_TP2_SHIFT 20 -#define AIPS_PACRM_WP2_MASK 0x200000u -#define AIPS_PACRM_WP2_SHIFT 21 -#define AIPS_PACRM_SP2_MASK 0x400000u -#define AIPS_PACRM_SP2_SHIFT 22 -#define AIPS_PACRM_TP1_MASK 0x1000000u -#define AIPS_PACRM_TP1_SHIFT 24 -#define AIPS_PACRM_WP1_MASK 0x2000000u -#define AIPS_PACRM_WP1_SHIFT 25 -#define AIPS_PACRM_SP1_MASK 0x4000000u -#define AIPS_PACRM_SP1_SHIFT 26 -#define AIPS_PACRM_TP0_MASK 0x10000000u -#define AIPS_PACRM_TP0_SHIFT 28 -#define AIPS_PACRM_WP0_MASK 0x20000000u -#define AIPS_PACRM_WP0_SHIFT 29 -#define AIPS_PACRM_SP0_MASK 0x40000000u -#define AIPS_PACRM_SP0_SHIFT 30 -/* PACRN Bit Fields */ -#define AIPS_PACRN_TP7_MASK 0x1u -#define AIPS_PACRN_TP7_SHIFT 0 -#define AIPS_PACRN_WP7_MASK 0x2u -#define AIPS_PACRN_WP7_SHIFT 1 -#define AIPS_PACRN_SP7_MASK 0x4u -#define AIPS_PACRN_SP7_SHIFT 2 -#define AIPS_PACRN_TP6_MASK 0x10u -#define AIPS_PACRN_TP6_SHIFT 4 -#define AIPS_PACRN_WP6_MASK 0x20u -#define AIPS_PACRN_WP6_SHIFT 5 -#define AIPS_PACRN_SP6_MASK 0x40u -#define AIPS_PACRN_SP6_SHIFT 6 -#define AIPS_PACRN_TP5_MASK 0x100u -#define AIPS_PACRN_TP5_SHIFT 8 -#define AIPS_PACRN_WP5_MASK 0x200u -#define AIPS_PACRN_WP5_SHIFT 9 -#define AIPS_PACRN_SP5_MASK 0x400u -#define AIPS_PACRN_SP5_SHIFT 10 -#define AIPS_PACRN_TP4_MASK 0x1000u -#define AIPS_PACRN_TP4_SHIFT 12 -#define AIPS_PACRN_WP4_MASK 0x2000u -#define AIPS_PACRN_WP4_SHIFT 13 -#define AIPS_PACRN_SP4_MASK 0x4000u -#define AIPS_PACRN_SP4_SHIFT 14 -#define AIPS_PACRN_TP3_MASK 0x10000u -#define AIPS_PACRN_TP3_SHIFT 16 -#define AIPS_PACRN_WP3_MASK 0x20000u -#define AIPS_PACRN_WP3_SHIFT 17 -#define AIPS_PACRN_SP3_MASK 0x40000u -#define AIPS_PACRN_SP3_SHIFT 18 -#define AIPS_PACRN_TP2_MASK 0x100000u -#define AIPS_PACRN_TP2_SHIFT 20 -#define AIPS_PACRN_WP2_MASK 0x200000u -#define AIPS_PACRN_WP2_SHIFT 21 -#define AIPS_PACRN_SP2_MASK 0x400000u -#define AIPS_PACRN_SP2_SHIFT 22 -#define AIPS_PACRN_TP1_MASK 0x1000000u -#define AIPS_PACRN_TP1_SHIFT 24 -#define AIPS_PACRN_WP1_MASK 0x2000000u -#define AIPS_PACRN_WP1_SHIFT 25 -#define AIPS_PACRN_SP1_MASK 0x4000000u -#define AIPS_PACRN_SP1_SHIFT 26 -#define AIPS_PACRN_TP0_MASK 0x10000000u -#define AIPS_PACRN_TP0_SHIFT 28 -#define AIPS_PACRN_WP0_MASK 0x20000000u -#define AIPS_PACRN_WP0_SHIFT 29 -#define AIPS_PACRN_SP0_MASK 0x40000000u -#define AIPS_PACRN_SP0_SHIFT 30 -/* PACRO Bit Fields */ -#define AIPS_PACRO_TP7_MASK 0x1u -#define AIPS_PACRO_TP7_SHIFT 0 -#define AIPS_PACRO_WP7_MASK 0x2u -#define AIPS_PACRO_WP7_SHIFT 1 -#define AIPS_PACRO_SP7_MASK 0x4u -#define AIPS_PACRO_SP7_SHIFT 2 -#define AIPS_PACRO_TP6_MASK 0x10u -#define AIPS_PACRO_TP6_SHIFT 4 -#define AIPS_PACRO_WP6_MASK 0x20u -#define AIPS_PACRO_WP6_SHIFT 5 -#define AIPS_PACRO_SP6_MASK 0x40u -#define AIPS_PACRO_SP6_SHIFT 6 -#define AIPS_PACRO_TP5_MASK 0x100u -#define AIPS_PACRO_TP5_SHIFT 8 -#define AIPS_PACRO_WP5_MASK 0x200u -#define AIPS_PACRO_WP5_SHIFT 9 -#define AIPS_PACRO_SP5_MASK 0x400u -#define AIPS_PACRO_SP5_SHIFT 10 -#define AIPS_PACRO_TP4_MASK 0x1000u -#define AIPS_PACRO_TP4_SHIFT 12 -#define AIPS_PACRO_WP4_MASK 0x2000u -#define AIPS_PACRO_WP4_SHIFT 13 -#define AIPS_PACRO_SP4_MASK 0x4000u -#define AIPS_PACRO_SP4_SHIFT 14 -#define AIPS_PACRO_TP3_MASK 0x10000u -#define AIPS_PACRO_TP3_SHIFT 16 -#define AIPS_PACRO_WP3_MASK 0x20000u -#define AIPS_PACRO_WP3_SHIFT 17 -#define AIPS_PACRO_SP3_MASK 0x40000u -#define AIPS_PACRO_SP3_SHIFT 18 -#define AIPS_PACRO_TP2_MASK 0x100000u -#define AIPS_PACRO_TP2_SHIFT 20 -#define AIPS_PACRO_WP2_MASK 0x200000u -#define AIPS_PACRO_WP2_SHIFT 21 -#define AIPS_PACRO_SP2_MASK 0x400000u -#define AIPS_PACRO_SP2_SHIFT 22 -#define AIPS_PACRO_TP1_MASK 0x1000000u -#define AIPS_PACRO_TP1_SHIFT 24 -#define AIPS_PACRO_WP1_MASK 0x2000000u -#define AIPS_PACRO_WP1_SHIFT 25 -#define AIPS_PACRO_SP1_MASK 0x4000000u -#define AIPS_PACRO_SP1_SHIFT 26 -#define AIPS_PACRO_TP0_MASK 0x10000000u -#define AIPS_PACRO_TP0_SHIFT 28 -#define AIPS_PACRO_WP0_MASK 0x20000000u -#define AIPS_PACRO_WP0_SHIFT 29 -#define AIPS_PACRO_SP0_MASK 0x40000000u -#define AIPS_PACRO_SP0_SHIFT 30 -/* PACRP Bit Fields */ -#define AIPS_PACRP_TP7_MASK 0x1u -#define AIPS_PACRP_TP7_SHIFT 0 -#define AIPS_PACRP_WP7_MASK 0x2u -#define AIPS_PACRP_WP7_SHIFT 1 -#define AIPS_PACRP_SP7_MASK 0x4u -#define AIPS_PACRP_SP7_SHIFT 2 -#define AIPS_PACRP_TP6_MASK 0x10u -#define AIPS_PACRP_TP6_SHIFT 4 -#define AIPS_PACRP_WP6_MASK 0x20u -#define AIPS_PACRP_WP6_SHIFT 5 -#define AIPS_PACRP_SP6_MASK 0x40u -#define AIPS_PACRP_SP6_SHIFT 6 -#define AIPS_PACRP_TP5_MASK 0x100u -#define AIPS_PACRP_TP5_SHIFT 8 -#define AIPS_PACRP_WP5_MASK 0x200u -#define AIPS_PACRP_WP5_SHIFT 9 -#define AIPS_PACRP_SP5_MASK 0x400u -#define AIPS_PACRP_SP5_SHIFT 10 -#define AIPS_PACRP_TP4_MASK 0x1000u -#define AIPS_PACRP_TP4_SHIFT 12 -#define AIPS_PACRP_WP4_MASK 0x2000u -#define AIPS_PACRP_WP4_SHIFT 13 -#define AIPS_PACRP_SP4_MASK 0x4000u -#define AIPS_PACRP_SP4_SHIFT 14 -#define AIPS_PACRP_TP3_MASK 0x10000u -#define AIPS_PACRP_TP3_SHIFT 16 -#define AIPS_PACRP_WP3_MASK 0x20000u -#define AIPS_PACRP_WP3_SHIFT 17 -#define AIPS_PACRP_SP3_MASK 0x40000u -#define AIPS_PACRP_SP3_SHIFT 18 -#define AIPS_PACRP_TP2_MASK 0x100000u -#define AIPS_PACRP_TP2_SHIFT 20 -#define AIPS_PACRP_WP2_MASK 0x200000u -#define AIPS_PACRP_WP2_SHIFT 21 -#define AIPS_PACRP_SP2_MASK 0x400000u -#define AIPS_PACRP_SP2_SHIFT 22 -#define AIPS_PACRP_TP1_MASK 0x1000000u -#define AIPS_PACRP_TP1_SHIFT 24 -#define AIPS_PACRP_WP1_MASK 0x2000000u -#define AIPS_PACRP_WP1_SHIFT 25 -#define AIPS_PACRP_SP1_MASK 0x4000000u -#define AIPS_PACRP_SP1_SHIFT 26 -#define AIPS_PACRP_TP0_MASK 0x10000000u -#define AIPS_PACRP_TP0_SHIFT 28 -#define AIPS_PACRP_WP0_MASK 0x20000000u -#define AIPS_PACRP_WP0_SHIFT 29 -#define AIPS_PACRP_SP0_MASK 0x40000000u -#define AIPS_PACRP_SP0_SHIFT 30 +/*! @name MPRA - Master Privilege Register A */ +#define AIPS_MPRA_MPL5_MASK (0x100U) +#define AIPS_MPRA_MPL5_SHIFT (8U) +#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) +#define AIPS_MPRA_MTW5_MASK (0x200U) +#define AIPS_MPRA_MTW5_SHIFT (9U) +#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) +#define AIPS_MPRA_MTR5_MASK (0x400U) +#define AIPS_MPRA_MTR5_SHIFT (10U) +#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) +#define AIPS_MPRA_MPL4_MASK (0x1000U) +#define AIPS_MPRA_MPL4_SHIFT (12U) +#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) +#define AIPS_MPRA_MTW4_MASK (0x2000U) +#define AIPS_MPRA_MTW4_SHIFT (13U) +#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) +#define AIPS_MPRA_MTR4_MASK (0x4000U) +#define AIPS_MPRA_MTR4_SHIFT (14U) +#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) +#define AIPS_MPRA_MPL3_MASK (0x10000U) +#define AIPS_MPRA_MPL3_SHIFT (16U) +#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) +#define AIPS_MPRA_MTW3_MASK (0x20000U) +#define AIPS_MPRA_MTW3_SHIFT (17U) +#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) +#define AIPS_MPRA_MTR3_MASK (0x40000U) +#define AIPS_MPRA_MTR3_SHIFT (18U) +#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) +#define AIPS_MPRA_MPL2_MASK (0x100000U) +#define AIPS_MPRA_MPL2_SHIFT (20U) +#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) +#define AIPS_MPRA_MTW2_MASK (0x200000U) +#define AIPS_MPRA_MTW2_SHIFT (21U) +#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) +#define AIPS_MPRA_MTR2_MASK (0x400000U) +#define AIPS_MPRA_MTR2_SHIFT (22U) +#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) +#define AIPS_MPRA_MPL1_MASK (0x1000000U) +#define AIPS_MPRA_MPL1_SHIFT (24U) +#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) +#define AIPS_MPRA_MTW1_MASK (0x2000000U) +#define AIPS_MPRA_MTW1_SHIFT (25U) +#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) +#define AIPS_MPRA_MTR1_MASK (0x4000000U) +#define AIPS_MPRA_MTR1_SHIFT (26U) +#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) +#define AIPS_MPRA_MPL0_MASK (0x10000000U) +#define AIPS_MPRA_MPL0_SHIFT (28U) +#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) +#define AIPS_MPRA_MTW0_MASK (0x20000000U) +#define AIPS_MPRA_MTW0_SHIFT (29U) +#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) +#define AIPS_MPRA_MTR0_MASK (0x40000000U) +#define AIPS_MPRA_MTR0_SHIFT (30U) +#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) + +/*! @name PACRA - Peripheral Access Control Register */ +#define AIPS_PACRA_TP7_MASK (0x1U) +#define AIPS_PACRA_TP7_SHIFT (0U) +#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) +#define AIPS_PACRA_WP7_MASK (0x2U) +#define AIPS_PACRA_WP7_SHIFT (1U) +#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) +#define AIPS_PACRA_SP7_MASK (0x4U) +#define AIPS_PACRA_SP7_SHIFT (2U) +#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) +#define AIPS_PACRA_TP6_MASK (0x10U) +#define AIPS_PACRA_TP6_SHIFT (4U) +#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) +#define AIPS_PACRA_WP6_MASK (0x20U) +#define AIPS_PACRA_WP6_SHIFT (5U) +#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) +#define AIPS_PACRA_SP6_MASK (0x40U) +#define AIPS_PACRA_SP6_SHIFT (6U) +#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) +#define AIPS_PACRA_TP5_MASK (0x100U) +#define AIPS_PACRA_TP5_SHIFT (8U) +#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) +#define AIPS_PACRA_WP5_MASK (0x200U) +#define AIPS_PACRA_WP5_SHIFT (9U) +#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) +#define AIPS_PACRA_SP5_MASK (0x400U) +#define AIPS_PACRA_SP5_SHIFT (10U) +#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) +#define AIPS_PACRA_TP4_MASK (0x1000U) +#define AIPS_PACRA_TP4_SHIFT (12U) +#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) +#define AIPS_PACRA_WP4_MASK (0x2000U) +#define AIPS_PACRA_WP4_SHIFT (13U) +#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) +#define AIPS_PACRA_SP4_MASK (0x4000U) +#define AIPS_PACRA_SP4_SHIFT (14U) +#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) +#define AIPS_PACRA_TP3_MASK (0x10000U) +#define AIPS_PACRA_TP3_SHIFT (16U) +#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) +#define AIPS_PACRA_WP3_MASK (0x20000U) +#define AIPS_PACRA_WP3_SHIFT (17U) +#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) +#define AIPS_PACRA_SP3_MASK (0x40000U) +#define AIPS_PACRA_SP3_SHIFT (18U) +#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) +#define AIPS_PACRA_TP2_MASK (0x100000U) +#define AIPS_PACRA_TP2_SHIFT (20U) +#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) +#define AIPS_PACRA_WP2_MASK (0x200000U) +#define AIPS_PACRA_WP2_SHIFT (21U) +#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) +#define AIPS_PACRA_SP2_MASK (0x400000U) +#define AIPS_PACRA_SP2_SHIFT (22U) +#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) +#define AIPS_PACRA_TP1_MASK (0x1000000U) +#define AIPS_PACRA_TP1_SHIFT (24U) +#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) +#define AIPS_PACRA_WP1_MASK (0x2000000U) +#define AIPS_PACRA_WP1_SHIFT (25U) +#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) +#define AIPS_PACRA_SP1_MASK (0x4000000U) +#define AIPS_PACRA_SP1_SHIFT (26U) +#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) +#define AIPS_PACRA_TP0_MASK (0x10000000U) +#define AIPS_PACRA_TP0_SHIFT (28U) +#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) +#define AIPS_PACRA_WP0_MASK (0x20000000U) +#define AIPS_PACRA_WP0_SHIFT (29U) +#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) +#define AIPS_PACRA_SP0_MASK (0x40000000U) +#define AIPS_PACRA_SP0_SHIFT (30U) +#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) + +/*! @name PACRB - Peripheral Access Control Register */ +#define AIPS_PACRB_TP7_MASK (0x1U) +#define AIPS_PACRB_TP7_SHIFT (0U) +#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) +#define AIPS_PACRB_WP7_MASK (0x2U) +#define AIPS_PACRB_WP7_SHIFT (1U) +#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) +#define AIPS_PACRB_SP7_MASK (0x4U) +#define AIPS_PACRB_SP7_SHIFT (2U) +#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) +#define AIPS_PACRB_TP6_MASK (0x10U) +#define AIPS_PACRB_TP6_SHIFT (4U) +#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) +#define AIPS_PACRB_WP6_MASK (0x20U) +#define AIPS_PACRB_WP6_SHIFT (5U) +#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) +#define AIPS_PACRB_SP6_MASK (0x40U) +#define AIPS_PACRB_SP6_SHIFT (6U) +#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) +#define AIPS_PACRB_TP5_MASK (0x100U) +#define AIPS_PACRB_TP5_SHIFT (8U) +#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) +#define AIPS_PACRB_WP5_MASK (0x200U) +#define AIPS_PACRB_WP5_SHIFT (9U) +#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) +#define AIPS_PACRB_SP5_MASK (0x400U) +#define AIPS_PACRB_SP5_SHIFT (10U) +#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) +#define AIPS_PACRB_TP4_MASK (0x1000U) +#define AIPS_PACRB_TP4_SHIFT (12U) +#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) +#define AIPS_PACRB_WP4_MASK (0x2000U) +#define AIPS_PACRB_WP4_SHIFT (13U) +#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) +#define AIPS_PACRB_SP4_MASK (0x4000U) +#define AIPS_PACRB_SP4_SHIFT (14U) +#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) +#define AIPS_PACRB_TP3_MASK (0x10000U) +#define AIPS_PACRB_TP3_SHIFT (16U) +#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) +#define AIPS_PACRB_WP3_MASK (0x20000U) +#define AIPS_PACRB_WP3_SHIFT (17U) +#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) +#define AIPS_PACRB_SP3_MASK (0x40000U) +#define AIPS_PACRB_SP3_SHIFT (18U) +#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) +#define AIPS_PACRB_TP2_MASK (0x100000U) +#define AIPS_PACRB_TP2_SHIFT (20U) +#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) +#define AIPS_PACRB_WP2_MASK (0x200000U) +#define AIPS_PACRB_WP2_SHIFT (21U) +#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) +#define AIPS_PACRB_SP2_MASK (0x400000U) +#define AIPS_PACRB_SP2_SHIFT (22U) +#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) +#define AIPS_PACRB_TP1_MASK (0x1000000U) +#define AIPS_PACRB_TP1_SHIFT (24U) +#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) +#define AIPS_PACRB_WP1_MASK (0x2000000U) +#define AIPS_PACRB_WP1_SHIFT (25U) +#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) +#define AIPS_PACRB_SP1_MASK (0x4000000U) +#define AIPS_PACRB_SP1_SHIFT (26U) +#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) +#define AIPS_PACRB_TP0_MASK (0x10000000U) +#define AIPS_PACRB_TP0_SHIFT (28U) +#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) +#define AIPS_PACRB_WP0_MASK (0x20000000U) +#define AIPS_PACRB_WP0_SHIFT (29U) +#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) +#define AIPS_PACRB_SP0_MASK (0x40000000U) +#define AIPS_PACRB_SP0_SHIFT (30U) +#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) + +/*! @name PACRC - Peripheral Access Control Register */ +#define AIPS_PACRC_TP7_MASK (0x1U) +#define AIPS_PACRC_TP7_SHIFT (0U) +#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) +#define AIPS_PACRC_WP7_MASK (0x2U) +#define AIPS_PACRC_WP7_SHIFT (1U) +#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) +#define AIPS_PACRC_SP7_MASK (0x4U) +#define AIPS_PACRC_SP7_SHIFT (2U) +#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) +#define AIPS_PACRC_TP6_MASK (0x10U) +#define AIPS_PACRC_TP6_SHIFT (4U) +#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) +#define AIPS_PACRC_WP6_MASK (0x20U) +#define AIPS_PACRC_WP6_SHIFT (5U) +#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) +#define AIPS_PACRC_SP6_MASK (0x40U) +#define AIPS_PACRC_SP6_SHIFT (6U) +#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) +#define AIPS_PACRC_TP5_MASK (0x100U) +#define AIPS_PACRC_TP5_SHIFT (8U) +#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) +#define AIPS_PACRC_WP5_MASK (0x200U) +#define AIPS_PACRC_WP5_SHIFT (9U) +#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) +#define AIPS_PACRC_SP5_MASK (0x400U) +#define AIPS_PACRC_SP5_SHIFT (10U) +#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) +#define AIPS_PACRC_TP4_MASK (0x1000U) +#define AIPS_PACRC_TP4_SHIFT (12U) +#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) +#define AIPS_PACRC_WP4_MASK (0x2000U) +#define AIPS_PACRC_WP4_SHIFT (13U) +#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) +#define AIPS_PACRC_SP4_MASK (0x4000U) +#define AIPS_PACRC_SP4_SHIFT (14U) +#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) +#define AIPS_PACRC_TP3_MASK (0x10000U) +#define AIPS_PACRC_TP3_SHIFT (16U) +#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) +#define AIPS_PACRC_WP3_MASK (0x20000U) +#define AIPS_PACRC_WP3_SHIFT (17U) +#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) +#define AIPS_PACRC_SP3_MASK (0x40000U) +#define AIPS_PACRC_SP3_SHIFT (18U) +#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) +#define AIPS_PACRC_TP2_MASK (0x100000U) +#define AIPS_PACRC_TP2_SHIFT (20U) +#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) +#define AIPS_PACRC_WP2_MASK (0x200000U) +#define AIPS_PACRC_WP2_SHIFT (21U) +#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) +#define AIPS_PACRC_SP2_MASK (0x400000U) +#define AIPS_PACRC_SP2_SHIFT (22U) +#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) +#define AIPS_PACRC_TP1_MASK (0x1000000U) +#define AIPS_PACRC_TP1_SHIFT (24U) +#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) +#define AIPS_PACRC_WP1_MASK (0x2000000U) +#define AIPS_PACRC_WP1_SHIFT (25U) +#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) +#define AIPS_PACRC_SP1_MASK (0x4000000U) +#define AIPS_PACRC_SP1_SHIFT (26U) +#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) +#define AIPS_PACRC_TP0_MASK (0x10000000U) +#define AIPS_PACRC_TP0_SHIFT (28U) +#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) +#define AIPS_PACRC_WP0_MASK (0x20000000U) +#define AIPS_PACRC_WP0_SHIFT (29U) +#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) +#define AIPS_PACRC_SP0_MASK (0x40000000U) +#define AIPS_PACRC_SP0_SHIFT (30U) +#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) + +/*! @name PACRD - Peripheral Access Control Register */ +#define AIPS_PACRD_TP7_MASK (0x1U) +#define AIPS_PACRD_TP7_SHIFT (0U) +#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) +#define AIPS_PACRD_WP7_MASK (0x2U) +#define AIPS_PACRD_WP7_SHIFT (1U) +#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) +#define AIPS_PACRD_SP7_MASK (0x4U) +#define AIPS_PACRD_SP7_SHIFT (2U) +#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) +#define AIPS_PACRD_TP6_MASK (0x10U) +#define AIPS_PACRD_TP6_SHIFT (4U) +#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) +#define AIPS_PACRD_WP6_MASK (0x20U) +#define AIPS_PACRD_WP6_SHIFT (5U) +#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) +#define AIPS_PACRD_SP6_MASK (0x40U) +#define AIPS_PACRD_SP6_SHIFT (6U) +#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) +#define AIPS_PACRD_TP5_MASK (0x100U) +#define AIPS_PACRD_TP5_SHIFT (8U) +#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) +#define AIPS_PACRD_WP5_MASK (0x200U) +#define AIPS_PACRD_WP5_SHIFT (9U) +#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) +#define AIPS_PACRD_SP5_MASK (0x400U) +#define AIPS_PACRD_SP5_SHIFT (10U) +#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) +#define AIPS_PACRD_TP4_MASK (0x1000U) +#define AIPS_PACRD_TP4_SHIFT (12U) +#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) +#define AIPS_PACRD_WP4_MASK (0x2000U) +#define AIPS_PACRD_WP4_SHIFT (13U) +#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) +#define AIPS_PACRD_SP4_MASK (0x4000U) +#define AIPS_PACRD_SP4_SHIFT (14U) +#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) +#define AIPS_PACRD_TP3_MASK (0x10000U) +#define AIPS_PACRD_TP3_SHIFT (16U) +#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) +#define AIPS_PACRD_WP3_MASK (0x20000U) +#define AIPS_PACRD_WP3_SHIFT (17U) +#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) +#define AIPS_PACRD_SP3_MASK (0x40000U) +#define AIPS_PACRD_SP3_SHIFT (18U) +#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) +#define AIPS_PACRD_TP2_MASK (0x100000U) +#define AIPS_PACRD_TP2_SHIFT (20U) +#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) +#define AIPS_PACRD_WP2_MASK (0x200000U) +#define AIPS_PACRD_WP2_SHIFT (21U) +#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) +#define AIPS_PACRD_SP2_MASK (0x400000U) +#define AIPS_PACRD_SP2_SHIFT (22U) +#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) +#define AIPS_PACRD_TP1_MASK (0x1000000U) +#define AIPS_PACRD_TP1_SHIFT (24U) +#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) +#define AIPS_PACRD_WP1_MASK (0x2000000U) +#define AIPS_PACRD_WP1_SHIFT (25U) +#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) +#define AIPS_PACRD_SP1_MASK (0x4000000U) +#define AIPS_PACRD_SP1_SHIFT (26U) +#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) +#define AIPS_PACRD_TP0_MASK (0x10000000U) +#define AIPS_PACRD_TP0_SHIFT (28U) +#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) +#define AIPS_PACRD_WP0_MASK (0x20000000U) +#define AIPS_PACRD_WP0_SHIFT (29U) +#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) +#define AIPS_PACRD_SP0_MASK (0x40000000U) +#define AIPS_PACRD_SP0_SHIFT (30U) +#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) + +/*! @name PACRE - Peripheral Access Control Register */ +#define AIPS_PACRE_TP7_MASK (0x1U) +#define AIPS_PACRE_TP7_SHIFT (0U) +#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) +#define AIPS_PACRE_WP7_MASK (0x2U) +#define AIPS_PACRE_WP7_SHIFT (1U) +#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) +#define AIPS_PACRE_SP7_MASK (0x4U) +#define AIPS_PACRE_SP7_SHIFT (2U) +#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) +#define AIPS_PACRE_TP6_MASK (0x10U) +#define AIPS_PACRE_TP6_SHIFT (4U) +#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) +#define AIPS_PACRE_WP6_MASK (0x20U) +#define AIPS_PACRE_WP6_SHIFT (5U) +#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) +#define AIPS_PACRE_SP6_MASK (0x40U) +#define AIPS_PACRE_SP6_SHIFT (6U) +#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) +#define AIPS_PACRE_TP5_MASK (0x100U) +#define AIPS_PACRE_TP5_SHIFT (8U) +#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) +#define AIPS_PACRE_WP5_MASK (0x200U) +#define AIPS_PACRE_WP5_SHIFT (9U) +#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) +#define AIPS_PACRE_SP5_MASK (0x400U) +#define AIPS_PACRE_SP5_SHIFT (10U) +#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) +#define AIPS_PACRE_TP4_MASK (0x1000U) +#define AIPS_PACRE_TP4_SHIFT (12U) +#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) +#define AIPS_PACRE_WP4_MASK (0x2000U) +#define AIPS_PACRE_WP4_SHIFT (13U) +#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) +#define AIPS_PACRE_SP4_MASK (0x4000U) +#define AIPS_PACRE_SP4_SHIFT (14U) +#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) +#define AIPS_PACRE_TP3_MASK (0x10000U) +#define AIPS_PACRE_TP3_SHIFT (16U) +#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) +#define AIPS_PACRE_WP3_MASK (0x20000U) +#define AIPS_PACRE_WP3_SHIFT (17U) +#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) +#define AIPS_PACRE_SP3_MASK (0x40000U) +#define AIPS_PACRE_SP3_SHIFT (18U) +#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) +#define AIPS_PACRE_TP2_MASK (0x100000U) +#define AIPS_PACRE_TP2_SHIFT (20U) +#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) +#define AIPS_PACRE_WP2_MASK (0x200000U) +#define AIPS_PACRE_WP2_SHIFT (21U) +#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) +#define AIPS_PACRE_SP2_MASK (0x400000U) +#define AIPS_PACRE_SP2_SHIFT (22U) +#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) +#define AIPS_PACRE_TP1_MASK (0x1000000U) +#define AIPS_PACRE_TP1_SHIFT (24U) +#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) +#define AIPS_PACRE_WP1_MASK (0x2000000U) +#define AIPS_PACRE_WP1_SHIFT (25U) +#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) +#define AIPS_PACRE_SP1_MASK (0x4000000U) +#define AIPS_PACRE_SP1_SHIFT (26U) +#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) +#define AIPS_PACRE_TP0_MASK (0x10000000U) +#define AIPS_PACRE_TP0_SHIFT (28U) +#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) +#define AIPS_PACRE_WP0_MASK (0x20000000U) +#define AIPS_PACRE_WP0_SHIFT (29U) +#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) +#define AIPS_PACRE_SP0_MASK (0x40000000U) +#define AIPS_PACRE_SP0_SHIFT (30U) +#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) + +/*! @name PACRF - Peripheral Access Control Register */ +#define AIPS_PACRF_TP7_MASK (0x1U) +#define AIPS_PACRF_TP7_SHIFT (0U) +#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) +#define AIPS_PACRF_WP7_MASK (0x2U) +#define AIPS_PACRF_WP7_SHIFT (1U) +#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) +#define AIPS_PACRF_SP7_MASK (0x4U) +#define AIPS_PACRF_SP7_SHIFT (2U) +#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) +#define AIPS_PACRF_TP6_MASK (0x10U) +#define AIPS_PACRF_TP6_SHIFT (4U) +#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) +#define AIPS_PACRF_WP6_MASK (0x20U) +#define AIPS_PACRF_WP6_SHIFT (5U) +#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) +#define AIPS_PACRF_SP6_MASK (0x40U) +#define AIPS_PACRF_SP6_SHIFT (6U) +#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) +#define AIPS_PACRF_TP5_MASK (0x100U) +#define AIPS_PACRF_TP5_SHIFT (8U) +#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) +#define AIPS_PACRF_WP5_MASK (0x200U) +#define AIPS_PACRF_WP5_SHIFT (9U) +#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) +#define AIPS_PACRF_SP5_MASK (0x400U) +#define AIPS_PACRF_SP5_SHIFT (10U) +#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) +#define AIPS_PACRF_TP4_MASK (0x1000U) +#define AIPS_PACRF_TP4_SHIFT (12U) +#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) +#define AIPS_PACRF_WP4_MASK (0x2000U) +#define AIPS_PACRF_WP4_SHIFT (13U) +#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) +#define AIPS_PACRF_SP4_MASK (0x4000U) +#define AIPS_PACRF_SP4_SHIFT (14U) +#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) +#define AIPS_PACRF_TP3_MASK (0x10000U) +#define AIPS_PACRF_TP3_SHIFT (16U) +#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) +#define AIPS_PACRF_WP3_MASK (0x20000U) +#define AIPS_PACRF_WP3_SHIFT (17U) +#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) +#define AIPS_PACRF_SP3_MASK (0x40000U) +#define AIPS_PACRF_SP3_SHIFT (18U) +#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) +#define AIPS_PACRF_TP2_MASK (0x100000U) +#define AIPS_PACRF_TP2_SHIFT (20U) +#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) +#define AIPS_PACRF_WP2_MASK (0x200000U) +#define AIPS_PACRF_WP2_SHIFT (21U) +#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) +#define AIPS_PACRF_SP2_MASK (0x400000U) +#define AIPS_PACRF_SP2_SHIFT (22U) +#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) +#define AIPS_PACRF_TP1_MASK (0x1000000U) +#define AIPS_PACRF_TP1_SHIFT (24U) +#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) +#define AIPS_PACRF_WP1_MASK (0x2000000U) +#define AIPS_PACRF_WP1_SHIFT (25U) +#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) +#define AIPS_PACRF_SP1_MASK (0x4000000U) +#define AIPS_PACRF_SP1_SHIFT (26U) +#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) +#define AIPS_PACRF_TP0_MASK (0x10000000U) +#define AIPS_PACRF_TP0_SHIFT (28U) +#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) +#define AIPS_PACRF_WP0_MASK (0x20000000U) +#define AIPS_PACRF_WP0_SHIFT (29U) +#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) +#define AIPS_PACRF_SP0_MASK (0x40000000U) +#define AIPS_PACRF_SP0_SHIFT (30U) +#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) + +/*! @name PACRG - Peripheral Access Control Register */ +#define AIPS_PACRG_TP7_MASK (0x1U) +#define AIPS_PACRG_TP7_SHIFT (0U) +#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) +#define AIPS_PACRG_WP7_MASK (0x2U) +#define AIPS_PACRG_WP7_SHIFT (1U) +#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) +#define AIPS_PACRG_SP7_MASK (0x4U) +#define AIPS_PACRG_SP7_SHIFT (2U) +#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) +#define AIPS_PACRG_TP6_MASK (0x10U) +#define AIPS_PACRG_TP6_SHIFT (4U) +#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) +#define AIPS_PACRG_WP6_MASK (0x20U) +#define AIPS_PACRG_WP6_SHIFT (5U) +#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) +#define AIPS_PACRG_SP6_MASK (0x40U) +#define AIPS_PACRG_SP6_SHIFT (6U) +#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) +#define AIPS_PACRG_TP5_MASK (0x100U) +#define AIPS_PACRG_TP5_SHIFT (8U) +#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) +#define AIPS_PACRG_WP5_MASK (0x200U) +#define AIPS_PACRG_WP5_SHIFT (9U) +#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) +#define AIPS_PACRG_SP5_MASK (0x400U) +#define AIPS_PACRG_SP5_SHIFT (10U) +#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) +#define AIPS_PACRG_TP4_MASK (0x1000U) +#define AIPS_PACRG_TP4_SHIFT (12U) +#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) +#define AIPS_PACRG_WP4_MASK (0x2000U) +#define AIPS_PACRG_WP4_SHIFT (13U) +#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) +#define AIPS_PACRG_SP4_MASK (0x4000U) +#define AIPS_PACRG_SP4_SHIFT (14U) +#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) +#define AIPS_PACRG_TP3_MASK (0x10000U) +#define AIPS_PACRG_TP3_SHIFT (16U) +#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) +#define AIPS_PACRG_WP3_MASK (0x20000U) +#define AIPS_PACRG_WP3_SHIFT (17U) +#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) +#define AIPS_PACRG_SP3_MASK (0x40000U) +#define AIPS_PACRG_SP3_SHIFT (18U) +#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) +#define AIPS_PACRG_TP2_MASK (0x100000U) +#define AIPS_PACRG_TP2_SHIFT (20U) +#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) +#define AIPS_PACRG_WP2_MASK (0x200000U) +#define AIPS_PACRG_WP2_SHIFT (21U) +#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) +#define AIPS_PACRG_SP2_MASK (0x400000U) +#define AIPS_PACRG_SP2_SHIFT (22U) +#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) +#define AIPS_PACRG_TP1_MASK (0x1000000U) +#define AIPS_PACRG_TP1_SHIFT (24U) +#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) +#define AIPS_PACRG_WP1_MASK (0x2000000U) +#define AIPS_PACRG_WP1_SHIFT (25U) +#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) +#define AIPS_PACRG_SP1_MASK (0x4000000U) +#define AIPS_PACRG_SP1_SHIFT (26U) +#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) +#define AIPS_PACRG_TP0_MASK (0x10000000U) +#define AIPS_PACRG_TP0_SHIFT (28U) +#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) +#define AIPS_PACRG_WP0_MASK (0x20000000U) +#define AIPS_PACRG_WP0_SHIFT (29U) +#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) +#define AIPS_PACRG_SP0_MASK (0x40000000U) +#define AIPS_PACRG_SP0_SHIFT (30U) +#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) + +/*! @name PACRH - Peripheral Access Control Register */ +#define AIPS_PACRH_TP7_MASK (0x1U) +#define AIPS_PACRH_TP7_SHIFT (0U) +#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) +#define AIPS_PACRH_WP7_MASK (0x2U) +#define AIPS_PACRH_WP7_SHIFT (1U) +#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) +#define AIPS_PACRH_SP7_MASK (0x4U) +#define AIPS_PACRH_SP7_SHIFT (2U) +#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) +#define AIPS_PACRH_TP6_MASK (0x10U) +#define AIPS_PACRH_TP6_SHIFT (4U) +#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) +#define AIPS_PACRH_WP6_MASK (0x20U) +#define AIPS_PACRH_WP6_SHIFT (5U) +#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) +#define AIPS_PACRH_SP6_MASK (0x40U) +#define AIPS_PACRH_SP6_SHIFT (6U) +#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) +#define AIPS_PACRH_TP5_MASK (0x100U) +#define AIPS_PACRH_TP5_SHIFT (8U) +#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) +#define AIPS_PACRH_WP5_MASK (0x200U) +#define AIPS_PACRH_WP5_SHIFT (9U) +#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) +#define AIPS_PACRH_SP5_MASK (0x400U) +#define AIPS_PACRH_SP5_SHIFT (10U) +#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) +#define AIPS_PACRH_TP4_MASK (0x1000U) +#define AIPS_PACRH_TP4_SHIFT (12U) +#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) +#define AIPS_PACRH_WP4_MASK (0x2000U) +#define AIPS_PACRH_WP4_SHIFT (13U) +#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) +#define AIPS_PACRH_SP4_MASK (0x4000U) +#define AIPS_PACRH_SP4_SHIFT (14U) +#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) +#define AIPS_PACRH_TP3_MASK (0x10000U) +#define AIPS_PACRH_TP3_SHIFT (16U) +#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) +#define AIPS_PACRH_WP3_MASK (0x20000U) +#define AIPS_PACRH_WP3_SHIFT (17U) +#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) +#define AIPS_PACRH_SP3_MASK (0x40000U) +#define AIPS_PACRH_SP3_SHIFT (18U) +#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) +#define AIPS_PACRH_TP2_MASK (0x100000U) +#define AIPS_PACRH_TP2_SHIFT (20U) +#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) +#define AIPS_PACRH_WP2_MASK (0x200000U) +#define AIPS_PACRH_WP2_SHIFT (21U) +#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) +#define AIPS_PACRH_SP2_MASK (0x400000U) +#define AIPS_PACRH_SP2_SHIFT (22U) +#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) +#define AIPS_PACRH_TP1_MASK (0x1000000U) +#define AIPS_PACRH_TP1_SHIFT (24U) +#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) +#define AIPS_PACRH_WP1_MASK (0x2000000U) +#define AIPS_PACRH_WP1_SHIFT (25U) +#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) +#define AIPS_PACRH_SP1_MASK (0x4000000U) +#define AIPS_PACRH_SP1_SHIFT (26U) +#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) +#define AIPS_PACRH_TP0_MASK (0x10000000U) +#define AIPS_PACRH_TP0_SHIFT (28U) +#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) +#define AIPS_PACRH_WP0_MASK (0x20000000U) +#define AIPS_PACRH_WP0_SHIFT (29U) +#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) +#define AIPS_PACRH_SP0_MASK (0x40000000U) +#define AIPS_PACRH_SP0_SHIFT (30U) +#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) + +/*! @name PACRI - Peripheral Access Control Register */ +#define AIPS_PACRI_TP7_MASK (0x1U) +#define AIPS_PACRI_TP7_SHIFT (0U) +#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) +#define AIPS_PACRI_WP7_MASK (0x2U) +#define AIPS_PACRI_WP7_SHIFT (1U) +#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) +#define AIPS_PACRI_SP7_MASK (0x4U) +#define AIPS_PACRI_SP7_SHIFT (2U) +#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) +#define AIPS_PACRI_TP6_MASK (0x10U) +#define AIPS_PACRI_TP6_SHIFT (4U) +#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) +#define AIPS_PACRI_WP6_MASK (0x20U) +#define AIPS_PACRI_WP6_SHIFT (5U) +#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) +#define AIPS_PACRI_SP6_MASK (0x40U) +#define AIPS_PACRI_SP6_SHIFT (6U) +#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) +#define AIPS_PACRI_TP5_MASK (0x100U) +#define AIPS_PACRI_TP5_SHIFT (8U) +#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) +#define AIPS_PACRI_WP5_MASK (0x200U) +#define AIPS_PACRI_WP5_SHIFT (9U) +#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) +#define AIPS_PACRI_SP5_MASK (0x400U) +#define AIPS_PACRI_SP5_SHIFT (10U) +#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) +#define AIPS_PACRI_TP4_MASK (0x1000U) +#define AIPS_PACRI_TP4_SHIFT (12U) +#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) +#define AIPS_PACRI_WP4_MASK (0x2000U) +#define AIPS_PACRI_WP4_SHIFT (13U) +#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) +#define AIPS_PACRI_SP4_MASK (0x4000U) +#define AIPS_PACRI_SP4_SHIFT (14U) +#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) +#define AIPS_PACRI_TP3_MASK (0x10000U) +#define AIPS_PACRI_TP3_SHIFT (16U) +#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) +#define AIPS_PACRI_WP3_MASK (0x20000U) +#define AIPS_PACRI_WP3_SHIFT (17U) +#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) +#define AIPS_PACRI_SP3_MASK (0x40000U) +#define AIPS_PACRI_SP3_SHIFT (18U) +#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) +#define AIPS_PACRI_TP2_MASK (0x100000U) +#define AIPS_PACRI_TP2_SHIFT (20U) +#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) +#define AIPS_PACRI_WP2_MASK (0x200000U) +#define AIPS_PACRI_WP2_SHIFT (21U) +#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) +#define AIPS_PACRI_SP2_MASK (0x400000U) +#define AIPS_PACRI_SP2_SHIFT (22U) +#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) +#define AIPS_PACRI_TP1_MASK (0x1000000U) +#define AIPS_PACRI_TP1_SHIFT (24U) +#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) +#define AIPS_PACRI_WP1_MASK (0x2000000U) +#define AIPS_PACRI_WP1_SHIFT (25U) +#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) +#define AIPS_PACRI_SP1_MASK (0x4000000U) +#define AIPS_PACRI_SP1_SHIFT (26U) +#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) +#define AIPS_PACRI_TP0_MASK (0x10000000U) +#define AIPS_PACRI_TP0_SHIFT (28U) +#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) +#define AIPS_PACRI_WP0_MASK (0x20000000U) +#define AIPS_PACRI_WP0_SHIFT (29U) +#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) +#define AIPS_PACRI_SP0_MASK (0x40000000U) +#define AIPS_PACRI_SP0_SHIFT (30U) +#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) + +/*! @name PACRJ - Peripheral Access Control Register */ +#define AIPS_PACRJ_TP7_MASK (0x1U) +#define AIPS_PACRJ_TP7_SHIFT (0U) +#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) +#define AIPS_PACRJ_WP7_MASK (0x2U) +#define AIPS_PACRJ_WP7_SHIFT (1U) +#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) +#define AIPS_PACRJ_SP7_MASK (0x4U) +#define AIPS_PACRJ_SP7_SHIFT (2U) +#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) +#define AIPS_PACRJ_TP6_MASK (0x10U) +#define AIPS_PACRJ_TP6_SHIFT (4U) +#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) +#define AIPS_PACRJ_WP6_MASK (0x20U) +#define AIPS_PACRJ_WP6_SHIFT (5U) +#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) +#define AIPS_PACRJ_SP6_MASK (0x40U) +#define AIPS_PACRJ_SP6_SHIFT (6U) +#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) +#define AIPS_PACRJ_TP5_MASK (0x100U) +#define AIPS_PACRJ_TP5_SHIFT (8U) +#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) +#define AIPS_PACRJ_WP5_MASK (0x200U) +#define AIPS_PACRJ_WP5_SHIFT (9U) +#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) +#define AIPS_PACRJ_SP5_MASK (0x400U) +#define AIPS_PACRJ_SP5_SHIFT (10U) +#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) +#define AIPS_PACRJ_TP4_MASK (0x1000U) +#define AIPS_PACRJ_TP4_SHIFT (12U) +#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) +#define AIPS_PACRJ_WP4_MASK (0x2000U) +#define AIPS_PACRJ_WP4_SHIFT (13U) +#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) +#define AIPS_PACRJ_SP4_MASK (0x4000U) +#define AIPS_PACRJ_SP4_SHIFT (14U) +#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) +#define AIPS_PACRJ_TP3_MASK (0x10000U) +#define AIPS_PACRJ_TP3_SHIFT (16U) +#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) +#define AIPS_PACRJ_WP3_MASK (0x20000U) +#define AIPS_PACRJ_WP3_SHIFT (17U) +#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) +#define AIPS_PACRJ_SP3_MASK (0x40000U) +#define AIPS_PACRJ_SP3_SHIFT (18U) +#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) +#define AIPS_PACRJ_TP2_MASK (0x100000U) +#define AIPS_PACRJ_TP2_SHIFT (20U) +#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) +#define AIPS_PACRJ_WP2_MASK (0x200000U) +#define AIPS_PACRJ_WP2_SHIFT (21U) +#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) +#define AIPS_PACRJ_SP2_MASK (0x400000U) +#define AIPS_PACRJ_SP2_SHIFT (22U) +#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) +#define AIPS_PACRJ_TP1_MASK (0x1000000U) +#define AIPS_PACRJ_TP1_SHIFT (24U) +#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) +#define AIPS_PACRJ_WP1_MASK (0x2000000U) +#define AIPS_PACRJ_WP1_SHIFT (25U) +#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) +#define AIPS_PACRJ_SP1_MASK (0x4000000U) +#define AIPS_PACRJ_SP1_SHIFT (26U) +#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) +#define AIPS_PACRJ_TP0_MASK (0x10000000U) +#define AIPS_PACRJ_TP0_SHIFT (28U) +#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) +#define AIPS_PACRJ_WP0_MASK (0x20000000U) +#define AIPS_PACRJ_WP0_SHIFT (29U) +#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) +#define AIPS_PACRJ_SP0_MASK (0x40000000U) +#define AIPS_PACRJ_SP0_SHIFT (30U) +#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) + +/*! @name PACRK - Peripheral Access Control Register */ +#define AIPS_PACRK_TP7_MASK (0x1U) +#define AIPS_PACRK_TP7_SHIFT (0U) +#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) +#define AIPS_PACRK_WP7_MASK (0x2U) +#define AIPS_PACRK_WP7_SHIFT (1U) +#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) +#define AIPS_PACRK_SP7_MASK (0x4U) +#define AIPS_PACRK_SP7_SHIFT (2U) +#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) +#define AIPS_PACRK_TP6_MASK (0x10U) +#define AIPS_PACRK_TP6_SHIFT (4U) +#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) +#define AIPS_PACRK_WP6_MASK (0x20U) +#define AIPS_PACRK_WP6_SHIFT (5U) +#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) +#define AIPS_PACRK_SP6_MASK (0x40U) +#define AIPS_PACRK_SP6_SHIFT (6U) +#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) +#define AIPS_PACRK_TP5_MASK (0x100U) +#define AIPS_PACRK_TP5_SHIFT (8U) +#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) +#define AIPS_PACRK_WP5_MASK (0x200U) +#define AIPS_PACRK_WP5_SHIFT (9U) +#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) +#define AIPS_PACRK_SP5_MASK (0x400U) +#define AIPS_PACRK_SP5_SHIFT (10U) +#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) +#define AIPS_PACRK_TP4_MASK (0x1000U) +#define AIPS_PACRK_TP4_SHIFT (12U) +#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) +#define AIPS_PACRK_WP4_MASK (0x2000U) +#define AIPS_PACRK_WP4_SHIFT (13U) +#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) +#define AIPS_PACRK_SP4_MASK (0x4000U) +#define AIPS_PACRK_SP4_SHIFT (14U) +#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) +#define AIPS_PACRK_TP3_MASK (0x10000U) +#define AIPS_PACRK_TP3_SHIFT (16U) +#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) +#define AIPS_PACRK_WP3_MASK (0x20000U) +#define AIPS_PACRK_WP3_SHIFT (17U) +#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) +#define AIPS_PACRK_SP3_MASK (0x40000U) +#define AIPS_PACRK_SP3_SHIFT (18U) +#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) +#define AIPS_PACRK_TP2_MASK (0x100000U) +#define AIPS_PACRK_TP2_SHIFT (20U) +#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) +#define AIPS_PACRK_WP2_MASK (0x200000U) +#define AIPS_PACRK_WP2_SHIFT (21U) +#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) +#define AIPS_PACRK_SP2_MASK (0x400000U) +#define AIPS_PACRK_SP2_SHIFT (22U) +#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) +#define AIPS_PACRK_TP1_MASK (0x1000000U) +#define AIPS_PACRK_TP1_SHIFT (24U) +#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) +#define AIPS_PACRK_WP1_MASK (0x2000000U) +#define AIPS_PACRK_WP1_SHIFT (25U) +#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) +#define AIPS_PACRK_SP1_MASK (0x4000000U) +#define AIPS_PACRK_SP1_SHIFT (26U) +#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) +#define AIPS_PACRK_TP0_MASK (0x10000000U) +#define AIPS_PACRK_TP0_SHIFT (28U) +#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) +#define AIPS_PACRK_WP0_MASK (0x20000000U) +#define AIPS_PACRK_WP0_SHIFT (29U) +#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) +#define AIPS_PACRK_SP0_MASK (0x40000000U) +#define AIPS_PACRK_SP0_SHIFT (30U) +#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) + +/*! @name PACRL - Peripheral Access Control Register */ +#define AIPS_PACRL_TP7_MASK (0x1U) +#define AIPS_PACRL_TP7_SHIFT (0U) +#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) +#define AIPS_PACRL_WP7_MASK (0x2U) +#define AIPS_PACRL_WP7_SHIFT (1U) +#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) +#define AIPS_PACRL_SP7_MASK (0x4U) +#define AIPS_PACRL_SP7_SHIFT (2U) +#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) +#define AIPS_PACRL_TP6_MASK (0x10U) +#define AIPS_PACRL_TP6_SHIFT (4U) +#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) +#define AIPS_PACRL_WP6_MASK (0x20U) +#define AIPS_PACRL_WP6_SHIFT (5U) +#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) +#define AIPS_PACRL_SP6_MASK (0x40U) +#define AIPS_PACRL_SP6_SHIFT (6U) +#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) +#define AIPS_PACRL_TP5_MASK (0x100U) +#define AIPS_PACRL_TP5_SHIFT (8U) +#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) +#define AIPS_PACRL_WP5_MASK (0x200U) +#define AIPS_PACRL_WP5_SHIFT (9U) +#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) +#define AIPS_PACRL_SP5_MASK (0x400U) +#define AIPS_PACRL_SP5_SHIFT (10U) +#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) +#define AIPS_PACRL_TP4_MASK (0x1000U) +#define AIPS_PACRL_TP4_SHIFT (12U) +#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) +#define AIPS_PACRL_WP4_MASK (0x2000U) +#define AIPS_PACRL_WP4_SHIFT (13U) +#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) +#define AIPS_PACRL_SP4_MASK (0x4000U) +#define AIPS_PACRL_SP4_SHIFT (14U) +#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) +#define AIPS_PACRL_TP3_MASK (0x10000U) +#define AIPS_PACRL_TP3_SHIFT (16U) +#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) +#define AIPS_PACRL_WP3_MASK (0x20000U) +#define AIPS_PACRL_WP3_SHIFT (17U) +#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) +#define AIPS_PACRL_SP3_MASK (0x40000U) +#define AIPS_PACRL_SP3_SHIFT (18U) +#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) +#define AIPS_PACRL_TP2_MASK (0x100000U) +#define AIPS_PACRL_TP2_SHIFT (20U) +#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) +#define AIPS_PACRL_WP2_MASK (0x200000U) +#define AIPS_PACRL_WP2_SHIFT (21U) +#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) +#define AIPS_PACRL_SP2_MASK (0x400000U) +#define AIPS_PACRL_SP2_SHIFT (22U) +#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) +#define AIPS_PACRL_TP1_MASK (0x1000000U) +#define AIPS_PACRL_TP1_SHIFT (24U) +#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) +#define AIPS_PACRL_WP1_MASK (0x2000000U) +#define AIPS_PACRL_WP1_SHIFT (25U) +#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) +#define AIPS_PACRL_SP1_MASK (0x4000000U) +#define AIPS_PACRL_SP1_SHIFT (26U) +#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) +#define AIPS_PACRL_TP0_MASK (0x10000000U) +#define AIPS_PACRL_TP0_SHIFT (28U) +#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) +#define AIPS_PACRL_WP0_MASK (0x20000000U) +#define AIPS_PACRL_WP0_SHIFT (29U) +#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) +#define AIPS_PACRL_SP0_MASK (0x40000000U) +#define AIPS_PACRL_SP0_SHIFT (30U) +#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) + +/*! @name PACRM - Peripheral Access Control Register */ +#define AIPS_PACRM_TP7_MASK (0x1U) +#define AIPS_PACRM_TP7_SHIFT (0U) +#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) +#define AIPS_PACRM_WP7_MASK (0x2U) +#define AIPS_PACRM_WP7_SHIFT (1U) +#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) +#define AIPS_PACRM_SP7_MASK (0x4U) +#define AIPS_PACRM_SP7_SHIFT (2U) +#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) +#define AIPS_PACRM_TP6_MASK (0x10U) +#define AIPS_PACRM_TP6_SHIFT (4U) +#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) +#define AIPS_PACRM_WP6_MASK (0x20U) +#define AIPS_PACRM_WP6_SHIFT (5U) +#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) +#define AIPS_PACRM_SP6_MASK (0x40U) +#define AIPS_PACRM_SP6_SHIFT (6U) +#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) +#define AIPS_PACRM_TP5_MASK (0x100U) +#define AIPS_PACRM_TP5_SHIFT (8U) +#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) +#define AIPS_PACRM_WP5_MASK (0x200U) +#define AIPS_PACRM_WP5_SHIFT (9U) +#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) +#define AIPS_PACRM_SP5_MASK (0x400U) +#define AIPS_PACRM_SP5_SHIFT (10U) +#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) +#define AIPS_PACRM_TP4_MASK (0x1000U) +#define AIPS_PACRM_TP4_SHIFT (12U) +#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) +#define AIPS_PACRM_WP4_MASK (0x2000U) +#define AIPS_PACRM_WP4_SHIFT (13U) +#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) +#define AIPS_PACRM_SP4_MASK (0x4000U) +#define AIPS_PACRM_SP4_SHIFT (14U) +#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) +#define AIPS_PACRM_TP3_MASK (0x10000U) +#define AIPS_PACRM_TP3_SHIFT (16U) +#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) +#define AIPS_PACRM_WP3_MASK (0x20000U) +#define AIPS_PACRM_WP3_SHIFT (17U) +#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) +#define AIPS_PACRM_SP3_MASK (0x40000U) +#define AIPS_PACRM_SP3_SHIFT (18U) +#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) +#define AIPS_PACRM_TP2_MASK (0x100000U) +#define AIPS_PACRM_TP2_SHIFT (20U) +#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) +#define AIPS_PACRM_WP2_MASK (0x200000U) +#define AIPS_PACRM_WP2_SHIFT (21U) +#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) +#define AIPS_PACRM_SP2_MASK (0x400000U) +#define AIPS_PACRM_SP2_SHIFT (22U) +#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) +#define AIPS_PACRM_TP1_MASK (0x1000000U) +#define AIPS_PACRM_TP1_SHIFT (24U) +#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) +#define AIPS_PACRM_WP1_MASK (0x2000000U) +#define AIPS_PACRM_WP1_SHIFT (25U) +#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) +#define AIPS_PACRM_SP1_MASK (0x4000000U) +#define AIPS_PACRM_SP1_SHIFT (26U) +#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) +#define AIPS_PACRM_TP0_MASK (0x10000000U) +#define AIPS_PACRM_TP0_SHIFT (28U) +#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) +#define AIPS_PACRM_WP0_MASK (0x20000000U) +#define AIPS_PACRM_WP0_SHIFT (29U) +#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) +#define AIPS_PACRM_SP0_MASK (0x40000000U) +#define AIPS_PACRM_SP0_SHIFT (30U) +#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) + +/*! @name PACRN - Peripheral Access Control Register */ +#define AIPS_PACRN_TP7_MASK (0x1U) +#define AIPS_PACRN_TP7_SHIFT (0U) +#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) +#define AIPS_PACRN_WP7_MASK (0x2U) +#define AIPS_PACRN_WP7_SHIFT (1U) +#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) +#define AIPS_PACRN_SP7_MASK (0x4U) +#define AIPS_PACRN_SP7_SHIFT (2U) +#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) +#define AIPS_PACRN_TP6_MASK (0x10U) +#define AIPS_PACRN_TP6_SHIFT (4U) +#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) +#define AIPS_PACRN_WP6_MASK (0x20U) +#define AIPS_PACRN_WP6_SHIFT (5U) +#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) +#define AIPS_PACRN_SP6_MASK (0x40U) +#define AIPS_PACRN_SP6_SHIFT (6U) +#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) +#define AIPS_PACRN_TP5_MASK (0x100U) +#define AIPS_PACRN_TP5_SHIFT (8U) +#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) +#define AIPS_PACRN_WP5_MASK (0x200U) +#define AIPS_PACRN_WP5_SHIFT (9U) +#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) +#define AIPS_PACRN_SP5_MASK (0x400U) +#define AIPS_PACRN_SP5_SHIFT (10U) +#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) +#define AIPS_PACRN_TP4_MASK (0x1000U) +#define AIPS_PACRN_TP4_SHIFT (12U) +#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) +#define AIPS_PACRN_WP4_MASK (0x2000U) +#define AIPS_PACRN_WP4_SHIFT (13U) +#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) +#define AIPS_PACRN_SP4_MASK (0x4000U) +#define AIPS_PACRN_SP4_SHIFT (14U) +#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) +#define AIPS_PACRN_TP3_MASK (0x10000U) +#define AIPS_PACRN_TP3_SHIFT (16U) +#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) +#define AIPS_PACRN_WP3_MASK (0x20000U) +#define AIPS_PACRN_WP3_SHIFT (17U) +#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) +#define AIPS_PACRN_SP3_MASK (0x40000U) +#define AIPS_PACRN_SP3_SHIFT (18U) +#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) +#define AIPS_PACRN_TP2_MASK (0x100000U) +#define AIPS_PACRN_TP2_SHIFT (20U) +#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) +#define AIPS_PACRN_WP2_MASK (0x200000U) +#define AIPS_PACRN_WP2_SHIFT (21U) +#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) +#define AIPS_PACRN_SP2_MASK (0x400000U) +#define AIPS_PACRN_SP2_SHIFT (22U) +#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) +#define AIPS_PACRN_TP1_MASK (0x1000000U) +#define AIPS_PACRN_TP1_SHIFT (24U) +#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) +#define AIPS_PACRN_WP1_MASK (0x2000000U) +#define AIPS_PACRN_WP1_SHIFT (25U) +#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) +#define AIPS_PACRN_SP1_MASK (0x4000000U) +#define AIPS_PACRN_SP1_SHIFT (26U) +#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) +#define AIPS_PACRN_TP0_MASK (0x10000000U) +#define AIPS_PACRN_TP0_SHIFT (28U) +#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) +#define AIPS_PACRN_WP0_MASK (0x20000000U) +#define AIPS_PACRN_WP0_SHIFT (29U) +#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) +#define AIPS_PACRN_SP0_MASK (0x40000000U) +#define AIPS_PACRN_SP0_SHIFT (30U) +#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) + +/*! @name PACRO - Peripheral Access Control Register */ +#define AIPS_PACRO_TP7_MASK (0x1U) +#define AIPS_PACRO_TP7_SHIFT (0U) +#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) +#define AIPS_PACRO_WP7_MASK (0x2U) +#define AIPS_PACRO_WP7_SHIFT (1U) +#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) +#define AIPS_PACRO_SP7_MASK (0x4U) +#define AIPS_PACRO_SP7_SHIFT (2U) +#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) +#define AIPS_PACRO_TP6_MASK (0x10U) +#define AIPS_PACRO_TP6_SHIFT (4U) +#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) +#define AIPS_PACRO_WP6_MASK (0x20U) +#define AIPS_PACRO_WP6_SHIFT (5U) +#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) +#define AIPS_PACRO_SP6_MASK (0x40U) +#define AIPS_PACRO_SP6_SHIFT (6U) +#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) +#define AIPS_PACRO_TP5_MASK (0x100U) +#define AIPS_PACRO_TP5_SHIFT (8U) +#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) +#define AIPS_PACRO_WP5_MASK (0x200U) +#define AIPS_PACRO_WP5_SHIFT (9U) +#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) +#define AIPS_PACRO_SP5_MASK (0x400U) +#define AIPS_PACRO_SP5_SHIFT (10U) +#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) +#define AIPS_PACRO_TP4_MASK (0x1000U) +#define AIPS_PACRO_TP4_SHIFT (12U) +#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) +#define AIPS_PACRO_WP4_MASK (0x2000U) +#define AIPS_PACRO_WP4_SHIFT (13U) +#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) +#define AIPS_PACRO_SP4_MASK (0x4000U) +#define AIPS_PACRO_SP4_SHIFT (14U) +#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) +#define AIPS_PACRO_TP3_MASK (0x10000U) +#define AIPS_PACRO_TP3_SHIFT (16U) +#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) +#define AIPS_PACRO_WP3_MASK (0x20000U) +#define AIPS_PACRO_WP3_SHIFT (17U) +#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) +#define AIPS_PACRO_SP3_MASK (0x40000U) +#define AIPS_PACRO_SP3_SHIFT (18U) +#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) +#define AIPS_PACRO_TP2_MASK (0x100000U) +#define AIPS_PACRO_TP2_SHIFT (20U) +#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) +#define AIPS_PACRO_WP2_MASK (0x200000U) +#define AIPS_PACRO_WP2_SHIFT (21U) +#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) +#define AIPS_PACRO_SP2_MASK (0x400000U) +#define AIPS_PACRO_SP2_SHIFT (22U) +#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) +#define AIPS_PACRO_TP1_MASK (0x1000000U) +#define AIPS_PACRO_TP1_SHIFT (24U) +#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) +#define AIPS_PACRO_WP1_MASK (0x2000000U) +#define AIPS_PACRO_WP1_SHIFT (25U) +#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) +#define AIPS_PACRO_SP1_MASK (0x4000000U) +#define AIPS_PACRO_SP1_SHIFT (26U) +#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) +#define AIPS_PACRO_TP0_MASK (0x10000000U) +#define AIPS_PACRO_TP0_SHIFT (28U) +#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) +#define AIPS_PACRO_WP0_MASK (0x20000000U) +#define AIPS_PACRO_WP0_SHIFT (29U) +#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) +#define AIPS_PACRO_SP0_MASK (0x40000000U) +#define AIPS_PACRO_SP0_SHIFT (30U) +#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) + +/*! @name PACRP - Peripheral Access Control Register */ +#define AIPS_PACRP_TP7_MASK (0x1U) +#define AIPS_PACRP_TP7_SHIFT (0U) +#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) +#define AIPS_PACRP_WP7_MASK (0x2U) +#define AIPS_PACRP_WP7_SHIFT (1U) +#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) +#define AIPS_PACRP_SP7_MASK (0x4U) +#define AIPS_PACRP_SP7_SHIFT (2U) +#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) +#define AIPS_PACRP_TP6_MASK (0x10U) +#define AIPS_PACRP_TP6_SHIFT (4U) +#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) +#define AIPS_PACRP_WP6_MASK (0x20U) +#define AIPS_PACRP_WP6_SHIFT (5U) +#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) +#define AIPS_PACRP_SP6_MASK (0x40U) +#define AIPS_PACRP_SP6_SHIFT (6U) +#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) +#define AIPS_PACRP_TP5_MASK (0x100U) +#define AIPS_PACRP_TP5_SHIFT (8U) +#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) +#define AIPS_PACRP_WP5_MASK (0x200U) +#define AIPS_PACRP_WP5_SHIFT (9U) +#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) +#define AIPS_PACRP_SP5_MASK (0x400U) +#define AIPS_PACRP_SP5_SHIFT (10U) +#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) +#define AIPS_PACRP_TP4_MASK (0x1000U) +#define AIPS_PACRP_TP4_SHIFT (12U) +#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) +#define AIPS_PACRP_WP4_MASK (0x2000U) +#define AIPS_PACRP_WP4_SHIFT (13U) +#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) +#define AIPS_PACRP_SP4_MASK (0x4000U) +#define AIPS_PACRP_SP4_SHIFT (14U) +#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) +#define AIPS_PACRP_TP3_MASK (0x10000U) +#define AIPS_PACRP_TP3_SHIFT (16U) +#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) +#define AIPS_PACRP_WP3_MASK (0x20000U) +#define AIPS_PACRP_WP3_SHIFT (17U) +#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) +#define AIPS_PACRP_SP3_MASK (0x40000U) +#define AIPS_PACRP_SP3_SHIFT (18U) +#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) +#define AIPS_PACRP_TP2_MASK (0x100000U) +#define AIPS_PACRP_TP2_SHIFT (20U) +#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) +#define AIPS_PACRP_WP2_MASK (0x200000U) +#define AIPS_PACRP_WP2_SHIFT (21U) +#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) +#define AIPS_PACRP_SP2_MASK (0x400000U) +#define AIPS_PACRP_SP2_SHIFT (22U) +#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) +#define AIPS_PACRP_TP1_MASK (0x1000000U) +#define AIPS_PACRP_TP1_SHIFT (24U) +#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) +#define AIPS_PACRP_WP1_MASK (0x2000000U) +#define AIPS_PACRP_WP1_SHIFT (25U) +#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) +#define AIPS_PACRP_SP1_MASK (0x4000000U) +#define AIPS_PACRP_SP1_SHIFT (26U) +#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) +#define AIPS_PACRP_TP0_MASK (0x10000000U) +#define AIPS_PACRP_TP0_SHIFT (28U) +#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) +#define AIPS_PACRP_WP0_MASK (0x20000000U) +#define AIPS_PACRP_WP0_SHIFT (29U) +#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) +#define AIPS_PACRP_SP0_MASK (0x40000000U) +#define AIPS_PACRP_SP0_SHIFT (30U) +#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) + /*! * @} @@ -1594,70 +2001,15 @@ typedef struct { #define AIPS0_BASE (0x40000000u) /** Peripheral AIPS0 base pointer */ #define AIPS0 ((AIPS_Type *)AIPS0_BASE) -#define AIPS0_BASE_PTR (AIPS0) /** Peripheral AIPS1 base address */ #define AIPS1_BASE (0x40080000u) /** Peripheral AIPS1 base pointer */ #define AIPS1 ((AIPS_Type *)AIPS1_BASE) -#define AIPS1_BASE_PTR (AIPS1) /** Array initializer of AIPS peripheral base addresses */ #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } /** Array initializer of AIPS peripheral base pointers */ #define AIPS_BASE_PTRS { AIPS0, AIPS1 } -/* ---------------------------------------------------------------------------- - -- AIPS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros - * @{ - */ - - -/* AIPS - Register instance definitions */ -/* AIPS0 */ -#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0) -#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0) -#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0) -#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0) -#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0) -#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0) -#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0) -#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0) -#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0) -#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0) -#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0) -#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0) -#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0) -#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0) -#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0) -#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0) -#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0) -/* AIPS1 */ -#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1) -#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1) -#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1) -#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1) -#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1) -#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1) -#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1) -#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1) -#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1) -#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1) -#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1) -#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1) -#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1) -#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1) -#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1) -#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1) -#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - - /*! * @} */ /* end of group AIPS_Peripheral_Access_Layer */ @@ -1692,32 +2044,7 @@ typedef struct { __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ uint8_t RESERVED_5[252]; __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ -} AXBS_Type, *AXBS_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- AXBS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros - * @{ - */ - - -/* AXBS - Register accessors */ -#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) -#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) -#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) -#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) -#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) -#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3) -#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) -#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) - -/*! - * @} - */ /* end of group AXBS_Register_Accessor_Macros */ - +} AXBS_Type; /* ---------------------------------------------------------------------------- -- AXBS Register Masks @@ -1728,63 +2055,79 @@ typedef struct { * @{ */ -/* PRS Bit Fields */ -#define AXBS_PRS_M0_MASK 0x7u -#define AXBS_PRS_M0_SHIFT 0 -#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define CAN_CTRL1_REG(base) ((base)->CTRL1) -#define CAN_TIMER_REG(base) ((base)->TIMER) -#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) -#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) -#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) -#define CAN_ECR_REG(base) ((base)->ECR) -#define CAN_ESR1_REG(base) ((base)->ESR1) -#define CAN_IMASK1_REG(base) ((base)->IMASK1) -#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) -#define CAN_CTRL2_REG(base) ((base)->CTRL2) -#define CAN_ESR2_REG(base) ((base)->ESR2) -#define CAN_CRCR_REG(base) ((base)->CRCR) -#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) -#define CAN_RXFIR_REG(base) ((base)->RXFIR) -#define CAN_CS_REG(base,index) ((base)->MB[index].CS) -#define CAN_ID_REG(base,index) ((base)->MB[index].ID) -#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) -#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) -#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) - -/*! - * @} - */ /* end of group CAN_Register_Accessor_Macros */ - +} CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks @@ -1932,257 +2199,349 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define CAN_MCR_MAXMB_MASK 0x7Fu -#define CAN_MCR_MAXMB_SHIFT 0 -#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<DIRECT[index]) -#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR) -#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA) -#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index]) -#define CAU_STR_CASR_REG(base) ((base)->STR_CASR) -#define CAU_STR_CAA_REG(base) ((base)->STR_CAA) -#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index]) -#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR) -#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA) -#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index]) -#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR) -#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA) -#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index]) -#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR) -#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA) -#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index]) -#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR) -#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA) -#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index]) -#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR) -#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA) -#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index]) -#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR) -#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA) -#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index]) - -/*! - * @} - */ /* end of group CAU_Register_Accessor_Macros */ - +} CAU_Type; /* ---------------------------------------------------------------------------- -- CAU Register Masks @@ -2535,375 +2629,443 @@ typedef struct { * @{ */ -/* DIRECT Bit Fields */ -#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu -#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0 -#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - +} CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks @@ -3110,62 +3115,84 @@ typedef struct { * @{ */ -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1) -#define CMT_CGL1_REG(base) ((base)->CGL1) -#define CMT_CGH2_REG(base) ((base)->CGH2) -#define CMT_CGL2_REG(base) ((base)->CGL2) -#define CMT_OC_REG(base) ((base)->OC) -#define CMT_MSC_REG(base) ((base)->MSC) -#define CMT_CMD1_REG(base) ((base)->CMD1) -#define CMT_CMD2_REG(base) ((base)->CMD2) -#define CMT_CMD3_REG(base) ((base)->CMD3) -#define CMT_CMD4_REG(base) ((base)->CMD4) -#define CMT_PPS_REG(base) ((base)->PPS) -#define CMT_DMA_REG(base) ((base)->DMA) - -/*! - * @} - */ /* end of group CMT_Register_Accessor_Macros */ - +} CMT_Type; /* ---------------------------------------------------------------------------- -- CMT Register Masks @@ -3301,68 +3258,90 @@ typedef struct { * @{ */ -/* CGH1 Bit Fields */ -#define CMT_CGH1_PH_MASK 0xFFu -#define CMT_CGH1_PH_SHIFT 0 -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.CRCL) -#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH) -#define CRC_CRC_REG(base) ((base)->CRC) -#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL) -#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU) -#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL) -#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - +} CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks @@ -3505,100 +3420,122 @@ typedef struct { * @{ */ -/* CRCL Bit Fields */ -#define CRC_CRCL_CRCL_MASK 0xFFFFu -#define CRC_CRCL_CRCL_SHIFT 0 -#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) /*! * @} - */ /* end of group DAC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Register_Masks DAC Register Masks - * @{ - */ - -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - +} DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks @@ -4030,519 +3772,773 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - +} DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks @@ -4915,14 +4586,20 @@ typedef struct { * @{ */ -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<EIR) -#define ENET_EIMR_REG(base) ((base)->EIMR) -#define ENET_RDAR_REG(base) ((base)->RDAR) -#define ENET_TDAR_REG(base) ((base)->TDAR) -#define ENET_ECR_REG(base) ((base)->ECR) -#define ENET_MMFR_REG(base) ((base)->MMFR) -#define ENET_MSCR_REG(base) ((base)->MSCR) -#define ENET_MIBC_REG(base) ((base)->MIBC) -#define ENET_RCR_REG(base) ((base)->RCR) -#define ENET_TCR_REG(base) ((base)->TCR) -#define ENET_PALR_REG(base) ((base)->PALR) -#define ENET_PAUR_REG(base) ((base)->PAUR) -#define ENET_OPD_REG(base) ((base)->OPD) -#define ENET_IAUR_REG(base) ((base)->IAUR) -#define ENET_IALR_REG(base) ((base)->IALR) -#define ENET_GAUR_REG(base) ((base)->GAUR) -#define ENET_GALR_REG(base) ((base)->GALR) -#define ENET_TFWR_REG(base) ((base)->TFWR) -#define ENET_RDSR_REG(base) ((base)->RDSR) -#define ENET_TDSR_REG(base) ((base)->TDSR) -#define ENET_MRBR_REG(base) ((base)->MRBR) -#define ENET_RSFL_REG(base) ((base)->RSFL) -#define ENET_RSEM_REG(base) ((base)->RSEM) -#define ENET_RAEM_REG(base) ((base)->RAEM) -#define ENET_RAFL_REG(base) ((base)->RAFL) -#define ENET_TSEM_REG(base) ((base)->TSEM) -#define ENET_TAEM_REG(base) ((base)->TAEM) -#define ENET_TAFL_REG(base) ((base)->TAFL) -#define ENET_TIPG_REG(base) ((base)->TIPG) -#define ENET_FTRL_REG(base) ((base)->FTRL) -#define ENET_TACC_REG(base) ((base)->TACC) -#define ENET_RACC_REG(base) ((base)->RACC) -#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) -#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) -#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) -#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) -#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) -#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) -#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) -#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) -#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) -#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) -#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) -#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) -#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) -#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) -#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) -#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) -#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) -#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) -#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) -#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) -#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) -#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) -#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) -#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) -#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) -#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) -#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) -#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) -#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) -#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) -#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) -#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) -#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) -#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) -#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) -#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) -#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) -#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) -#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) -#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) -#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) -#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) -#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) -#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) -#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) -#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) -#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) -#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) -#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) -#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) -#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) -#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) -#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) -#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) -#define ENET_ATCR_REG(base) ((base)->ATCR) -#define ENET_ATVR_REG(base) ((base)->ATVR) -#define ENET_ATOFF_REG(base) ((base)->ATOFF) -#define ENET_ATPER_REG(base) ((base)->ATPER) -#define ENET_ATCOR_REG(base) ((base)->ATCOR) -#define ENET_ATINC_REG(base) ((base)->ATINC) -#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) -#define ENET_TGSR_REG(base) ((base)->TGSR) -#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) -#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) - -/*! - * @} - */ /* end of group ENET_Register_Accessor_Macros */ - +} ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks @@ -5232,551 +4758,739 @@ typedef struct { * @{ */ -/* EIR Bit Fields */ -#define ENET_EIR_TS_TIMER_MASK 0x8000u -#define ENET_EIR_TS_TIMER_SHIFT 15 -#define ENET_EIR_TS_AVAIL_MASK 0x10000u -#define ENET_EIR_TS_AVAIL_SHIFT 16 -#define ENET_EIR_WAKEUP_MASK 0x20000u -#define ENET_EIR_WAKEUP_SHIFT 17 -#define ENET_EIR_PLR_MASK 0x40000u -#define ENET_EIR_PLR_SHIFT 18 -#define ENET_EIR_UN_MASK 0x80000u -#define ENET_EIR_UN_SHIFT 19 -#define ENET_EIR_RL_MASK 0x100000u -#define ENET_EIR_RL_SHIFT 20 -#define ENET_EIR_LC_MASK 0x200000u -#define ENET_EIR_LC_SHIFT 21 -#define ENET_EIR_EBERR_MASK 0x400000u -#define ENET_EIR_EBERR_SHIFT 22 -#define ENET_EIR_MII_MASK 0x800000u -#define ENET_EIR_MII_SHIFT 23 -#define ENET_EIR_RXB_MASK 0x1000000u -#define ENET_EIR_RXB_SHIFT 24 -#define ENET_EIR_RXF_MASK 0x2000000u -#define ENET_EIR_RXF_SHIFT 25 -#define ENET_EIR_TXB_MASK 0x4000000u -#define ENET_EIR_TXB_SHIFT 26 -#define ENET_EIR_TXF_MASK 0x8000000u -#define ENET_EIR_TXF_SHIFT 27 -#define ENET_EIR_GRA_MASK 0x10000000u -#define ENET_EIR_GRA_SHIFT 28 -#define ENET_EIR_BABT_MASK 0x20000000u -#define ENET_EIR_BABT_SHIFT 29 -#define ENET_EIR_BABR_MASK 0x40000000u -#define ENET_EIR_BABR_SHIFT 30 -/* EIMR Bit Fields */ -#define ENET_EIMR_TS_TIMER_MASK 0x8000u -#define ENET_EIMR_TS_TIMER_SHIFT 15 -#define ENET_EIMR_TS_AVAIL_MASK 0x10000u -#define ENET_EIMR_TS_AVAIL_SHIFT 16 -#define ENET_EIMR_WAKEUP_MASK 0x20000u -#define ENET_EIMR_WAKEUP_SHIFT 17 -#define ENET_EIMR_PLR_MASK 0x40000u -#define ENET_EIMR_PLR_SHIFT 18 -#define ENET_EIMR_UN_MASK 0x80000u -#define ENET_EIMR_UN_SHIFT 19 -#define ENET_EIMR_RL_MASK 0x100000u -#define ENET_EIMR_RL_SHIFT 20 -#define ENET_EIMR_LC_MASK 0x200000u -#define ENET_EIMR_LC_SHIFT 21 -#define ENET_EIMR_EBERR_MASK 0x400000u -#define ENET_EIMR_EBERR_SHIFT 22 -#define ENET_EIMR_MII_MASK 0x800000u -#define ENET_EIMR_MII_SHIFT 23 -#define ENET_EIMR_RXB_MASK 0x1000000u -#define ENET_EIMR_RXB_SHIFT 24 -#define ENET_EIMR_RXF_MASK 0x2000000u -#define ENET_EIMR_RXF_SHIFT 25 -#define ENET_EIMR_TXB_MASK 0x4000000u -#define ENET_EIMR_TXB_SHIFT 26 -#define ENET_EIMR_TXF_MASK 0x8000000u -#define ENET_EIMR_TXF_SHIFT 27 -#define ENET_EIMR_GRA_MASK 0x10000000u -#define ENET_EIMR_GRA_SHIFT 28 -#define ENET_EIMR_BABT_MASK 0x20000000u -#define ENET_EIMR_BABT_SHIFT 29 -#define ENET_EIMR_BABR_MASK 0x40000000u -#define ENET_EIMR_BABR_SHIFT 30 -/* RDAR Bit Fields */ -#define ENET_RDAR_RDAR_MASK 0x1000000u -#define ENET_RDAR_RDAR_SHIFT 24 -/* TDAR Bit Fields */ -#define ENET_TDAR_TDAR_MASK 0x1000000u -#define ENET_TDAR_TDAR_SHIFT 24 -/* ECR Bit Fields */ -#define ENET_ECR_RESET_MASK 0x1u -#define ENET_ECR_RESET_SHIFT 0 -#define ENET_ECR_ETHEREN_MASK 0x2u -#define ENET_ECR_ETHEREN_SHIFT 1 -#define ENET_ECR_MAGICEN_MASK 0x4u -#define ENET_ECR_MAGICEN_SHIFT 2 -#define ENET_ECR_SLEEP_MASK 0x8u -#define ENET_ECR_SLEEP_SHIFT 3 -#define ENET_ECR_EN1588_MASK 0x10u -#define ENET_ECR_EN1588_SHIFT 4 -#define ENET_ECR_DBGEN_MASK 0x40u -#define ENET_ECR_DBGEN_SHIFT 6 -#define ENET_ECR_STOPEN_MASK 0x80u -#define ENET_ECR_STOPEN_SHIFT 7 -#define ENET_ECR_DBSWP_MASK 0x100u -#define ENET_ECR_DBSWP_SHIFT 8 -/* MMFR Bit Fields */ -#define ENET_MMFR_DATA_MASK 0xFFFFu -#define ENET_MMFR_DATA_SHIFT 0 -#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))< MAX_FL bytes, good CRC (RMON_T_OVERSIZE) */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_FRAG - RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG) */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) + +/*! @name RMON_T_JAB - RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB) */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) + +/*! @name RMON_T_COL - RMON Tx collision count (RMON_T_COL) */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) + +/*! @name RMON_T_P64 - RMON Tx 64 byte packets (RMON_T_P64) */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) + +/*! @name RMON_T_P65TO127 - RMON Tx 65 to 127 byte packets (RMON_T_P65TO127) */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) + +/*! @name RMON_T_P128TO255 - RMON Tx 128 to 255 byte packets (RMON_T_P128TO255) */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) + +/*! @name RMON_T_P256TO511 - RMON Tx 256 to 511 byte packets (RMON_T_P256TO511) */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) + +/*! @name RMON_T_P512TO1023 - RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023) */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) + +/*! @name RMON_T_P1024TO2047 - RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047) */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) + +/*! @name RMON_T_P_GTE2048 - RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048) */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) + +/*! @name RMON_T_OCTETS - RMON Tx Octets (RMON_T_OCTETS) */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK (IEEE_T_FRAME_OK) */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision (IEEE_T_1COL) */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions (IEEE_T_MCOL) */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay (IEEE_T_DEF) */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision (IEEE_T_LCOL) */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL) */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR) */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR) */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) + +/*! @name IEEE_T_FDXFC - Flow Control Pause frames transmitted (IEEE_T_FDXFC) */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) + +/*! @name IEEE_T_OCTETS_OK - Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields). */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) + +/*! @name RMON_R_PACKETS - RMON Rx packet count (RMON_R_PACKETS) */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) + +/*! @name RMON_R_BC_PKT - RMON Rx Broadcast Packets (RMON_R_BC_PKT) */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) + +/*! @name RMON_R_MC_PKT - RMON Rx Multicast Packets (RMON_R_MC_PKT) */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) + +/*! @name RMON_R_CRC_ALIGN - RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN) */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) + +/*! @name RMON_R_UNDERSIZE - RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE) */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) + +/*! @name RMON_R_OVERSIZE - RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE) */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) + +/*! @name RMON_R_FRAG - RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG) */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) + +/*! @name RMON_R_JAB - RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB) */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) + +/*! @name RMON_R_P64 - RMON Rx 64 byte packets (RMON_R_P64) */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) + +/*! @name RMON_R_P65TO127 - RMON Rx 65 to 127 byte packets (RMON_R_P65TO127) */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) + +/*! @name RMON_R_P128TO255 - RMON Rx 128 to 255 byte packets (RMON_R_P128TO255) */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) + +/*! @name RMON_R_P256TO511 - RMON Rx 256 to 511 byte packets (RMON_R_P256TO511) */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) + +/*! @name RMON_R_P512TO1023 - RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023) */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) + +/*! @name RMON_R_P1024TO2047 - RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047) */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) + +/*! @name RMON_R_P_GTE2048 - RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048) */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) + +/*! @name RMON_R_OCTETS - RMON Rx Octets (RMON_R_OCTETS) */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) + +/*! @name IEEE_R_DROP - Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments. */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) + +/*! @name IEEE_R_FRAME_OK - Frames Received OK (IEEE_R_FRAME_OK) */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_R_CRC - Frames Received with CRC Error (IEEE_R_CRC) */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error (IEEE_R_ALIGN) */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) + +/*! @name IEEE_R_MACERR - Receive Fifo Overflow count (IEEE_R_MACERR) */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) + +/*! @name IEEE_R_FDXFC - Flow Control Pause frames received (IEEE_R_FDXFC) */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) + +/*! @name IEEE_R_OCTETS_OK - Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields). */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) + +/*! @name ATCR - Timer Control Register */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) + +/*! @name ATVR - Timer Value Register */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) + +/*! @name ATOFF - Timer Offset Register */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) + +/*! @name ATPER - Timer Period Register */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) + +/*! @name ATCOR - Timer Correction Register */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) + +/*! @name ATINC - Time-Stamping Clock Period Register */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) + +/*! @name TGSR - Timer Global Status Register */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) + +/*! @name TCSR - Timer Control Status Register */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + /*! * @} @@ -5788,7 +5502,6 @@ typedef struct { #define ENET_BASE (0x400C0000u) /** Peripheral ENET base pointer */ #define ENET ((ENET_Type *)ENET_BASE) -#define ENET_BASE_PTR (ENET) /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ @@ -5798,129 +5511,8 @@ typedef struct { #define ENET_Receive_IRQS { ENET_Receive_IRQn } #define ENET_Error_IRQS { ENET_Error_IRQn } #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } - -/* ---------------------------------------------------------------------------- - -- ENET - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros - * @{ - */ - - -/* ENET - Register instance definitions */ -/* ENET */ -#define ENET_EIR ENET_EIR_REG(ENET) -#define ENET_EIMR ENET_EIMR_REG(ENET) -#define ENET_RDAR ENET_RDAR_REG(ENET) -#define ENET_TDAR ENET_TDAR_REG(ENET) -#define ENET_ECR ENET_ECR_REG(ENET) -#define ENET_MMFR ENET_MMFR_REG(ENET) -#define ENET_MSCR ENET_MSCR_REG(ENET) -#define ENET_MIBC ENET_MIBC_REG(ENET) -#define ENET_RCR ENET_RCR_REG(ENET) -#define ENET_TCR ENET_TCR_REG(ENET) -#define ENET_PALR ENET_PALR_REG(ENET) -#define ENET_PAUR ENET_PAUR_REG(ENET) -#define ENET_OPD ENET_OPD_REG(ENET) -#define ENET_IAUR ENET_IAUR_REG(ENET) -#define ENET_IALR ENET_IALR_REG(ENET) -#define ENET_GAUR ENET_GAUR_REG(ENET) -#define ENET_GALR ENET_GALR_REG(ENET) -#define ENET_TFWR ENET_TFWR_REG(ENET) -#define ENET_RDSR ENET_RDSR_REG(ENET) -#define ENET_TDSR ENET_TDSR_REG(ENET) -#define ENET_MRBR ENET_MRBR_REG(ENET) -#define ENET_RSFL ENET_RSFL_REG(ENET) -#define ENET_RSEM ENET_RSEM_REG(ENET) -#define ENET_RAEM ENET_RAEM_REG(ENET) -#define ENET_RAFL ENET_RAFL_REG(ENET) -#define ENET_TSEM ENET_TSEM_REG(ENET) -#define ENET_TAEM ENET_TAEM_REG(ENET) -#define ENET_TAFL ENET_TAFL_REG(ENET) -#define ENET_TIPG ENET_TIPG_REG(ENET) -#define ENET_FTRL ENET_FTRL_REG(ENET) -#define ENET_TACC ENET_TACC_REG(ENET) -#define ENET_RACC ENET_RACC_REG(ENET) -#define ENET_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET) -#define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET) -#define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET) -#define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET) -#define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET) -#define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET) -#define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET) -#define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET) -#define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET) -#define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET) -#define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET) -#define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET) -#define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET) -#define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET) -#define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET) -#define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET) -#define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET) -#define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET) -#define ENET_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET) -#define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET) -#define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET) -#define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET) -#define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET) -#define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET) -#define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET) -#define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET) -#define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET) -#define ENET_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET) -#define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET) -#define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET) -#define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET) -#define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET) -#define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET) -#define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET) -#define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET) -#define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET) -#define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET) -#define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET) -#define ENET_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET) -#define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET) -#define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET) -#define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET) -#define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET) -#define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET) -#define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET) -#define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET) -#define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET) -#define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET) -#define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET) -#define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET) -#define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET) -#define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET) -#define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET) -#define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET) -#define ENET_ATCR ENET_ATCR_REG(ENET) -#define ENET_ATVR ENET_ATVR_REG(ENET) -#define ENET_ATOFF ENET_ATOFF_REG(ENET) -#define ENET_ATPER ENET_ATPER_REG(ENET) -#define ENET_ATCOR ENET_ATCOR_REG(ENET) -#define ENET_ATINC ENET_ATINC_REG(ENET) -#define ENET_ATSTMP ENET_ATSTMP_REG(ENET) -#define ENET_TGSR ENET_TGSR_REG(ENET) -#define ENET_TCSR0 ENET_TCSR_REG(ENET,0) -#define ENET_TCCR0 ENET_TCCR_REG(ENET,0) -#define ENET_TCSR1 ENET_TCSR_REG(ENET,1) -#define ENET_TCCR1 ENET_TCCR_REG(ENET,1) -#define ENET_TCSR2 ENET_TCSR_REG(ENET,2) -#define ENET_TCCR2 ENET_TCCR_REG(ENET,2) -#define ENET_TCSR3 ENET_TCSR_REG(ENET,3) -#define ENET_TCCR3 ENET_TCCR_REG(ENET,3) - -/* ENET - Register array accessors */ -#define ENET_TCSR(index) ENET_TCSR_REG(ENET,index) -#define ENET_TCCR(index) ENET_TCCR_REG(ENET,index) - -/*! - * @} - */ /* end of group ENET_Register_Accessor_Macros */ +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (16U) /*! @@ -5945,64 +5537,51 @@ typedef struct { __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ uint8_t RESERVED_0[1]; __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ -} EWM_Type, *EWM_MemMapPtr; +} EWM_Type; /* ---------------------------------------------------------------------------- - -- EWM - Register accessor macros + -- EWM Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros + * @addtogroup EWM_Register_Masks EWM Register Masks * @{ */ +/*! @name CTRL - Control Register */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) -/* EWM - Register accessors */ -#define EWM_CTRL_REG(base) ((base)->CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) -#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ +/*! @name SERV - Service Register */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @name CMPL - Compare Low Register */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ +/*! @name CMPH - Compare High Register */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ +/*! @name CLKPRESCALER - Clock Prescaler Register */ +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_ASSIN_MASK 0x2u -#define EWM_CTRL_ASSIN_SHIFT 1 -#define EWM_CTRL_INEN_MASK 0x4u -#define EWM_CTRL_INEN_SHIFT 2 -#define EWM_CTRL_INTEN_MASK 0x8u -#define EWM_CTRL_INTEN_SHIFT 3 -/* SERV Bit Fields */ -#define EWM_SERV_SERVICE_MASK 0xFFu -#define EWM_SERV_SERVICE_SHIFT 0 -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) -#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) -#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) -#define FB_CSPMCR_REG(base) ((base)->CSPMCR) - -/*! - * @} - */ /* end of group FB_Register_Accessor_Macros */ - +} FB_Type; /* ---------------------------------------------------------------------------- -- FB Register Masks @@ -6100,67 +5634,89 @@ typedef struct { * @{ */ -/* CSAR Bit Fields */ -#define FB_CSAR_BA_MASK 0xFFFF0000u -#define FB_CSAR_BA_SHIFT 16 -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2]) -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - +} FMC_Type; /* ---------------------------------------------------------------------------- -- FMC Register Masks @@ -6280,106 +5770,150 @@ typedef struct { * @{ */ -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFL_FCNFG_REG(base) ((base)->FCNFG) -#define FTFL_FSEC_REG(base) ((base)->FSEC) -#define FTFL_FOPT_REG(base) ((base)->FOPT) -#define FTFL_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFL_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFL_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFL_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFL_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFL_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFL_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFL_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFL_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFL_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFL_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFL_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFL_FPROT3_REG(base) ((base)->FPROT3) -#define FTFL_FPROT2_REG(base) ((base)->FPROT2) -#define FTFL_FPROT1_REG(base) ((base)->FPROT1) -#define FTFL_FPROT0_REG(base) ((base)->FPROT0) -#define FTFL_FEPROT_REG(base) ((base)->FEPROT) -#define FTFL_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group FTFL_Register_Accessor_Macros */ - +} FTFL_Type; /* ---------------------------------------------------------------------------- -- FTFL Register Masks @@ -6608,123 +5980,158 @@ typedef struct { * @{ */ -/* FSTAT Bit Fields */ -#define FTFL_FSTAT_MGSTAT0_MASK 0x1u -#define FTFL_FSTAT_MGSTAT0_SHIFT 0 -#define FTFL_FSTAT_FPVIOL_MASK 0x10u -#define FTFL_FSTAT_FPVIOL_SHIFT 4 -#define FTFL_FSTAT_ACCERR_MASK 0x20u -#define FTFL_FSTAT_ACCERR_SHIFT 5 -#define FTFL_FSTAT_RDCOLERR_MASK 0x40u -#define FTFL_FSTAT_RDCOLERR_SHIFT 6 -#define FTFL_FSTAT_CCIF_MASK 0x80u -#define FTFL_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFL_FCNFG_EEERDY_MASK 0x1u -#define FTFL_FCNFG_EEERDY_SHIFT 0 -#define FTFL_FCNFG_RAMRDY_MASK 0x2u -#define FTFL_FCNFG_RAMRDY_SHIFT 1 -#define FTFL_FCNFG_PFLSH_MASK 0x4u -#define FTFL_FCNFG_PFLSH_SHIFT 2 -#define FTFL_FCNFG_SWAP_MASK 0x8u -#define FTFL_FCNFG_SWAP_SHIFT 3 -#define FTFL_FCNFG_ERSSUSP_MASK 0x10u -#define FTFL_FCNFG_ERSSUSP_SHIFT 4 -#define FTFL_FCNFG_ERSAREQ_MASK 0x20u -#define FTFL_FCNFG_ERSAREQ_SHIFT 5 -#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFL_FCNFG_CCIE_MASK 0x80u -#define FTFL_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFL_FSEC_SEC_MASK 0x3u -#define FTFL_FSEC_SEC_SHIFT 0 -#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - +} FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks @@ -6881,409 +6205,605 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) +/*! @name PSOR - Port Set Output Register */ +#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) +#define GPIO_PSOR_PTSO_SHIFT (0U) +#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ +/*! @name PCOR - Port Clear Output Register */ +#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) +#define GPIO_PCOR_PTCO_SHIFT (0U) +#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) +/*! @name PTOR - Port Toggle Output Register */ +#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) +#define GPIO_PTOR_PTTO_SHIFT (0U) +#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ +/*! @name PDIR - Port Data Input Register */ +#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) +#define GPIO_PDIR_PDI_SHIFT (0U) +#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ +/*! @name PDDR - Port Data Direction Register */ +#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) +#define GPIO_PDDR_PDD_SHIFT (0U) +#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - +} I2C_Type; /* ---------------------------------------------------------------------------- -- I2C Register Masks @@ -7671,106 +6964,147 @@ typedef struct { * @{ */ -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - +} I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks @@ -7930,233 +7182,319 @@ typedef struct { * @{ */ -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FRIE_MASK 0x100u -#define I2S_TCSR_FRIE_SHIFT 8 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FRF_MASK 0x10000u -#define I2S_TCSR_FRF_SHIFT 16 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR1 Bit Fields */ -#define I2S_TCR1_TFW_MASK 0x7u -#define I2S_TCR1_TFW_SHIFT 0 -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) -#define LLWU_RST_REG(base) ((base)->RST) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - +} LLWU_Type; /* ---------------------------------------------------------------------------- -- LLWU Register Masks @@ -8291,149 +7552,196 @@ typedef struct { * @{ */ -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - +} LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks @@ -8534,39 +7791,50 @@ typedef struct { * @{ */ -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) -#define MCG_C9_REG(base) ((base)->C9) -#define MCG_C10_REG(base) ((base)->C10) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - +} MCG_Type; /* ---------------------------------------------------------------------------- -- MCG Register Masks @@ -8682,116 +7896,159 @@ typedef struct { * @{ */ -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_IREFS_MASK 0x4u -#define MCG_C1_IREFS_SHIFT 2 -#define MCG_C1_FRDIV_MASK 0x38u -#define MCG_C1_FRDIV_SHIFT 3 -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_CR_REG(base) ((base)->CR) -#define MCM_ISR_REG(base) ((base)->ISR) -#define MCM_ETBCC_REG(base) ((base)->ETBCC) -#define MCM_ETBRL_REG(base) ((base)->ETBRL) -#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) -#define MCM_PID_REG(base) ((base)->PID) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - +} MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks @@ -8903,56 +8128,73 @@ typedef struct { * @{ */ -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR) -#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) -#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) -#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) -#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) - -/*! - * @} - */ /* end of group MPU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MPU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MPU_Register_Masks MPU Register Masks - * @{ - */ - -/* CESR Bit Fields */ -#define MPU_CESR_VLD_MASK 0x1u -#define MPU_CESR_VLD_SHIFT 0 -#define MPU_CESR_NRGD_MASK 0xF00u -#define MPU_CESR_NRGD_SHIFT 8 -#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) -#define NV_FEPROT_REG(base) ((base)->FEPROT) -#define NV_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - +} NV_Type; /* ---------------------------------------------------------------------------- -- NV Register Masks @@ -9364,82 +8256,101 @@ typedef struct { * @{ */ -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - +} OSC_Type; /* ---------------------------------------------------------------------------- -- OSC Register Masks @@ -9537,19 +8395,26 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 +/*! @name CR - OSC Control Register */ +#define OSC_CR_SC16P_MASK (0x1U) +#define OSC_CR_SC16P_SHIFT (0U) +#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) +#define OSC_CR_SC8P_MASK (0x2U) +#define OSC_CR_SC8P_SHIFT (1U) +#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) +#define OSC_CR_SC4P_MASK (0x4U) +#define OSC_CR_SC4P_SHIFT (2U) +#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) +#define OSC_CR_SC2P_MASK (0x8U) +#define OSC_CR_SC2P_SHIFT (3U) +#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) +#define OSC_CR_EREFSTEN_MASK (0x20U) +#define OSC_CR_EREFSTEN_SHIFT (5U) +#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) +#define OSC_CR_ERCLKEN_MASK (0x80U) +#define OSC_CR_ERCLKEN_SHIFT (7U) +#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) + /*! * @} @@ -9561,31 +8426,11 @@ typedef struct { #define OSC_BASE (0x40065000u) /** Peripheral OSC base pointer */ #define OSC ((OSC_Type *)OSC_BASE) -#define OSC_BASE_PTR (OSC) /** Array initializer of OSC peripheral base addresses */ #define OSC_BASE_ADDRS { OSC_BASE } /** Array initializer of OSC peripheral base pointers */ #define OSC_BASE_PTRS { OSC } -/* ---------------------------------------------------------------------------- - -- OSC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros - * @{ - */ - - -/* OSC - Register instance definitions */ -/* OSC */ -#define OSC_CR OSC_CR_REG(OSC) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - /*! * @} */ /* end of group OSC_Peripheral_Access_Layer */ @@ -9620,35 +8465,7 @@ typedef struct { uint8_t RESERVED_1[48]; __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ -} PDB_Type, *PDB_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- PDB - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros - * @{ - */ - - -/* PDB - Register accessors */ -#define PDB_SC_REG(base) ((base)->SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - +} PDB_Type; /* ---------------------------------------------------------------------------- -- PDB Register Masks @@ -9659,88 +8476,130 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_CONT_MASK 0x2u -#define PDB_SC_CONT_SHIFT 1 -#define PDB_SC_MULT_MASK 0xCu -#define PDB_SC_MULT_SHIFT 2 -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) +/*! @name LDVAL - Timer Load Value Register */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) +/*! @name CVAL - Current Timer Value Register */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ +/*! @name TCTRL - Timer Control Register */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - +} PMC_Type; /* ---------------------------------------------------------------------------- -- PMC Register Masks @@ -9996,37 +8747,51 @@ typedef struct { * @{ */ -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - +} PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks @@ -10127,58 +8846,77 @@ typedef struct { * @{ */ -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_ODE_MASK 0x20u -#define PORT_PCR_ODE_SHIFT 5 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - +} RCM_Type; /* ---------------------------------------------------------------------------- -- RCM Register Masks @@ -10493,47 +8985,67 @@ typedef struct { * @{ */ -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_LOC_MASK 0x4u -#define RCM_SRS0_LOC_SHIFT 2 -#define RCM_SRS0_LOL_MASK 0x8u -#define RCM_SRS0_LOL_SHIFT 3 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_JTAG_MASK 0x1u -#define RCM_SRS1_JTAG_SHIFT 0 -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_EZPT_MASK 0x10u -#define RCM_SRS1_EZPT_SHIFT 4 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - +} RFSYS_Type; /* ---------------------------------------------------------------------------- -- RFSYS Register Masks @@ -10620,19 +9090,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - +} RFVBAT_Type; /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks @@ -10725,19 +9151,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) -#define RNG_SR_REG(base) ((base)->SR) -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_OR_REG(base) ((base)->OR) - -/*! - * @} - */ /* end of group RNG_Register_Accessor_Macros */ - +} RNG_Type; /* ---------------------------------------------------------------------------- -- RNG Register Masks @@ -10836,42 +9215,56 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define RNG_CR_GO_MASK 0x1u -#define RNG_CR_GO_SHIFT 0 -#define RNG_CR_HA_MASK 0x2u -#define RNG_CR_HA_SHIFT 1 -#define RNG_CR_INTM_MASK 0x4u -#define RNG_CR_INTM_SHIFT 2 -#define RNG_CR_CLRI_MASK 0x8u -#define RNG_CR_CLRI_SHIFT 3 -#define RNG_CR_SLP_MASK 0x10u -#define RNG_CR_SLP_SHIFT 4 -/* SR Bit Fields */ -#define RNG_SR_SECV_MASK 0x1u -#define RNG_SR_SECV_SHIFT 0 -#define RNG_SR_LRS_MASK 0x2u -#define RNG_SR_LRS_SHIFT 1 -#define RNG_SR_ORU_MASK 0x4u -#define RNG_SR_ORU_SHIFT 2 -#define RNG_SR_ERRI_MASK 0x8u -#define RNG_SR_ERRI_SHIFT 3 -#define RNG_SR_SLP_MASK 0x10u -#define RNG_SR_SLP_SHIFT 4 -#define RNG_SR_OREG_LVL_MASK 0xFF00u -#define RNG_SR_OREG_LVL_SHIFT 8 -#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - +} RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks @@ -10978,115 +9321,164 @@ typedef struct { * @{ */ -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<DSADDR) -#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) -#define SDHC_CMDARG_REG(base) ((base)->CMDARG) -#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) -#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) -#define SDHC_DATPORT_REG(base) ((base)->DATPORT) -#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) -#define SDHC_PROCTL_REG(base) ((base)->PROCTL) -#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) -#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) -#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) -#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) -#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) -#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) -#define SDHC_WML_REG(base) ((base)->WML) -#define SDHC_FEVT_REG(base) ((base)->FEVT) -#define SDHC_ADMAES_REG(base) ((base)->ADMAES) -#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) -#define SDHC_VENDOR_REG(base) ((base)->VENDOR) -#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) -#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) - -/*! - * @} - */ /* end of group SDHC_Register_Accessor_Macros */ - +} SDHC_Type; /* ---------------------------------------------------------------------------- -- SDHC Register Masks @@ -11224,378 +9549,534 @@ typedef struct { * @{ */ -/* DSADDR Bit Fields */ -#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu -#define SDHC_DSADDR_DSADDR_SHIFT 2 -#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC1_REG(base) ((base)->SCGC1) -#define SIM_SCGC2_REG(base) ((base)->SCGC2) -#define SIM_SCGC3_REG(base) ((base)->SCGC3) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - +} SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks @@ -11752,280 +10148,380 @@ typedef struct { * @{ */ -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - +} SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks @@ -12135,34 +10569,44 @@ typedef struct { * @{ */ -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - +} SPI_Type; /* ---------------------------------------------------------------------------- -- SPI Register Masks @@ -12287,202 +10674,262 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_SMPL_PT_MASK 0x300u -#define SPI_MCR_SMPL_PT_SHIFT 8 -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<GENCS) -#define TSI_SCANC_REG(base) ((base)->SCANC) -#define TSI_PEN_REG(base) ((base)->PEN) -#define TSI_WUCNTR_REG(base) ((base)->WUCNTR) -#define TSI_CNTR1_REG(base) ((base)->CNTR1) -#define TSI_CNTR3_REG(base) ((base)->CNTR3) -#define TSI_CNTR5_REG(base) ((base)->CNTR5) -#define TSI_CNTR7_REG(base) ((base)->CNTR7) -#define TSI_CNTR9_REG(base) ((base)->CNTR9) -#define TSI_CNTR11_REG(base) ((base)->CNTR11) -#define TSI_CNTR13_REG(base) ((base)->CNTR13) -#define TSI_CNTR15_REG(base) ((base)->CNTR15) -#define TSI_THRESHOLD_REG(base) ((base)->THRESHOLD) - -/*! - * @} - */ /* end of group TSI_Register_Accessor_Macros */ - +} TSI_Type; /* ---------------------------------------------------------------------------- -- TSI Register Masks @@ -12665,161 +11210,203 @@ typedef struct { * @{ */ -/* GENCS Bit Fields */ -#define TSI_GENCS_STPE_MASK 0x1u -#define TSI_GENCS_STPE_SHIFT 0 -#define TSI_GENCS_STM_MASK 0x2u -#define TSI_GENCS_STM_SHIFT 1 -#define TSI_GENCS_ESOR_MASK 0x10u -#define TSI_GENCS_ESOR_SHIFT 4 -#define TSI_GENCS_ERIE_MASK 0x20u -#define TSI_GENCS_ERIE_SHIFT 5 -#define TSI_GENCS_TSIIE_MASK 0x40u -#define TSI_GENCS_TSIIE_SHIFT 6 -#define TSI_GENCS_TSIEN_MASK 0x80u -#define TSI_GENCS_TSIEN_SHIFT 7 -#define TSI_GENCS_SWTS_MASK 0x100u -#define TSI_GENCS_SWTS_SHIFT 8 -#define TSI_GENCS_SCNIP_MASK 0x200u -#define TSI_GENCS_SCNIP_SHIFT 9 -#define TSI_GENCS_OVRF_MASK 0x1000u -#define TSI_GENCS_OVRF_SHIFT 12 -#define TSI_GENCS_EXTERF_MASK 0x2000u -#define TSI_GENCS_EXTERF_SHIFT 13 -#define TSI_GENCS_OUTRGF_MASK 0x4000u -#define TSI_GENCS_OUTRGF_SHIFT 14 -#define TSI_GENCS_EOSF_MASK 0x8000u -#define TSI_GENCS_EOSF_SHIFT 15 -#define TSI_GENCS_PS_MASK 0x70000u -#define TSI_GENCS_PS_SHIFT 16 -#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816T0_REG(base) ((base)->WP7816T0) -#define UART_WP7816T1_REG(base) ((base)->WP7816T1) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_C6_REG(base) ((base)->C6) -#define UART_PCTH_REG(base) ((base)->PCTH) -#define UART_PCTL_REG(base) ((base)->PCTL) -#define UART_B1T_REG(base) ((base)->B1T) -#define UART_SDTH_REG(base) ((base)->SDTH) -#define UART_SDTL_REG(base) ((base)->SDTL) -#define UART_PRE_REG(base) ((base)->PRE) -#define UART_TPL_REG(base) ((base)->TPL) -#define UART_IE_REG(base) ((base)->IE) -#define UART_WB_REG(base) ((base)->WB) -#define UART_S3_REG(base) ((base)->S3) -#define UART_S4_REG(base) ((base)->S4) -#define UART_RPL_REG(base) ((base)->RPL) -#define UART_RPREL_REG(base) ((base)->RPREL) -#define UART_CPW_REG(base) ((base)->CPW) -#define UART_RIDT_REG(base) ((base)->RIDT) -#define UART_TIDT_REG(base) ((base)->TIDT) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - +} UART_Type; /* ---------------------------------------------------------------------------- -- UART Register Masks @@ -13015,373 +11505,528 @@ typedef struct { * @{ */ -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - +} USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks @@ -13738,241 +12151,353 @@ typedef struct { * @{ */ -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL) -#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) -#define USBDCD_STATUS_REG(base) ((base)->STATUS) -#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) -#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) -#define USBDCD_TIMER2_REG(base) ((base)->TIMER2) - -/*! - * @} - */ /* end of group USBDCD_Register_Accessor_Macros */ - +} USBDCD_Type; /* ---------------------------------------------------------------------------- -- USBDCD Register Masks @@ -14113,57 +12550,72 @@ typedef struct { * @{ */ -/* CONTROL Bit Fields */ -#define USBDCD_CONTROL_IACK_MASK 0x1u -#define USBDCD_CONTROL_IACK_SHIFT 0 -#define USBDCD_CONTROL_IF_MASK 0x100u -#define USBDCD_CONTROL_IF_SHIFT 8 -#define USBDCD_CONTROL_IE_MASK 0x10000u -#define USBDCD_CONTROL_IE_SHIFT 16 -#define USBDCD_CONTROL_START_MASK 0x1000000u -#define USBDCD_CONTROL_START_SHIFT 24 -#define USBDCD_CONTROL_SR_MASK 0x2000000u -#define USBDCD_CONTROL_SR_SHIFT 25 -/* CLOCK Bit Fields */ -#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u -#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 -#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu -#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 -#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - +} VREF_Type; /* ---------------------------------------------------------------------------- -- VREF Register Masks @@ -14255,24 +12663,31 @@ typedef struct { * @{ */ -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - +} WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks @@ -14378,75 +12743,99 @@ typedef struct { * @{ */ -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_CLKSRC_MASK 0x2u -#define WDOG_STCTRLH_CLKSRC_SHIFT 1 -#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u -#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 -#define WDOG_STCTRLH_WINEN_MASK 0x8u -#define WDOG_STCTRLH_WINEN_SHIFT 3 -#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 -#define WDOG_STCTRLH_DBGEN_MASK 0x20u -#define WDOG_STCTRLH_DBGEN_SHIFT 5 -#define WDOG_STCTRLH_STOPEN_MASK 0x40u -#define WDOG_STCTRLH_STOPEN_SHIFT 6 -#define WDOG_STCTRLH_WAITEN_MASK 0x80u -#define WDOG_STCTRLH_WAITEN_SHIFT 7 -#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u -#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 -#define WDOG_STCTRLH_TESTSEL_MASK 0x800u -#define WDOG_STCTRLH_TESTSEL_SHIFT 11 -#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u -#define WDOG_STCTRLH_BYTESEL_SHIFT 12 -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! - * @addtogroup Backward_Compatibility_Symbols Backward Compatibility + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define DSPI2 SPI2 +#define FLEXCAN0 CAN0 +#define FLEXCAN1 CAN1 #define PTA_BASE GPIOA_BASE #define PTA GPIOA #define PTB_BASE GPIOB_BASE @@ -14541,6 +12941,7 @@ typedef struct { #define PTD GPIOD #define PTE_BASE GPIOE_BASE #define PTE GPIOE +#define DMAMUX0 DMAMUX #define WP7816_T_TYPE0 WP7816T0 #define WP7816_T_TYPE1 WP7816T1 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK @@ -14567,14 +12968,14 @@ typedef struct { #define DAC_DATH_DATA_MASK DAC_DATH_DATA1_MASK #define DAC_DATH_DATA_SHIFT DAC_DATH_DATA1_SHIFT #define DAC_DATH_DATA(x) DAC_DATH_DATA1(x) -#define MCG_S_LOLS0_MASK MCG_S_LOLS_MASK -#define MCG_S_LOLS0_SHIFT MCG_S_LOLS_SHIFT #define SIM_SCGC6_RNGA_MASK This_symbol_has_been_deprecated #define SIM_SCGC6_RNGA_SHIFT This_symbol_has_been_deprecated #define Watchdog_IRQn WDOG_EWM_IRQn #define Watchdog_IRQHandler WDOG_EWM_IRQHandler #define LPTimer_IRQn LPTMR0_IRQn #define LPTimer_IRQHandler LPTMR0_IRQHandler +#define LLW_IRQn LLWU_IRQn +#define LLW_IRQHandler LLWU_IRQHandler /* Compatibility defines for compatibility with differing module names between * MK60 and MKW22 headers */ @@ -14584,20 +12985,8 @@ typedef struct { /*! * @} - */ /* end of group Backward_Compatibility_Symbols */ + */ /* end of group SDK_Compatibility_Symbols */ -#else /* #if !defined(MK60D10_H_) */ - /* There is already included the same memory map. Check if it is compatible (has the same major version) */ - #if (MCU_MEM_MAP_VERSION != 0x0100u) - #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) - #warning There are included two not compatible versions of memory maps. Please check possible differences. - #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ - #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MK60D10_H_) */ - -#ifdef __cplusplus -} -#endif +#endif /* _MK60D10_H_ */ -/* MK60D10.h, eof. */ diff --git a/cpu/kw41z/Makefile b/cpu/kw41z/Makefile index 68605a469b55f..b478eba931af9 100644 --- a/cpu/kw41z/Makefile +++ b/cpu/kw41z/Makefile @@ -1,8 +1,9 @@ # define the module that is build MODULE = cpu -# add a list of subdirectories, that should also be build -DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON) +# add a list of directories that should also be built +DIRS += periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON) +DIRS += vendor/XCVR/MKW41Z4 # (file triggers compiler bug. see #5775) SRC_NOLTO += vectors.c diff --git a/cpu/kw41z/Makefile.include b/cpu/kw41z/Makefile.include index f5dd10f9178d3..ea91063aba79b 100644 --- a/cpu/kw41z/Makefile.include +++ b/cpu/kw41z/Makefile.include @@ -21,4 +21,11 @@ export COMMON_STARTUP = $(KINETIS_COMMON) # add the CPU specific system calls implementations for the linker export UNDEF += $(BINDIR)/cpu/vectors.o +# Vendor supplied transceiver driver +export INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/Common +export INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/OSAbstraction/Interface +export INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/XCVR/MKW41Z4 + +export USEMODULE += mcux_xcvr + include $(RIOTMAKE)/arch/cortexm.inc.mk diff --git a/cpu/kw41z/include/vendor/MKW21Z4.h b/cpu/kw41z/include/vendor/MKW21Z4.h index c37f661c67e03..018e3e142028e 100644 --- a/cpu/kw41z/include/vendor/MKW21Z4.h +++ b/cpu/kw41z/include/vendor/MKW21Z4.h @@ -5,19 +5,18 @@ ** ** Compilers: Keil ARM C/C++ Compiler ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** ** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 ** Version: rev. 1.0, 2015-09-23 -** Build: b160720 +** Build: b170112 ** ** Abstract: ** CMSIS Peripheral Access Layer for MKW21Z4 ** ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright 2016 - 2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -28,7 +27,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -43,8 +42,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2015-09-23) @@ -85,6 +84,9 @@ #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ @@ -148,13 +150,114 @@ typedef enum IRQn { #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_MKW21Z4.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0Reserved4 = 4|0x100U, /**< Reserved4 */ + kDmaRequestMux0Reserved5 = 5|0x100U, /**< Reserved5 */ + kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */ + kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ + kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ + kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ + kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ + kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ + kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ + kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ + kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ + kDmaRequestMux0LTC0InputFIFO = 20|0x100U, /**< LTC0 Input FIFO. */ + kDmaRequestMux0LTC0OutputFIFO = 21|0x100U, /**< LTC0 Output FIFO. */ + kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ + kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ + kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ + kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ + kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ + kDmaRequestMux0Reserved28 = 28|0x100U, /**< Reserved28 */ + kDmaRequestMux0Reserved29 = 29|0x100U, /**< Reserved29 */ + kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ + kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ + kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ + kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ + kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ + kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ + kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ + kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ + kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ + kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ + kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0Reserved52 = 52|0x100U, /**< Reserved52 */ + kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ + kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ + kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ + kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ + kDmaRequestMux0TSI0 = 57|0x100U, /**< TSI0. */ + kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ + kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -434,6 +537,8 @@ typedef struct { #define ADC_BASE_ADDRS { ADC0_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } /*! * @} @@ -902,6 +1007,8 @@ typedef struct { #define CMP_BASE_ADDRS { CMP0_BASE } /** Array initializer of CMP peripheral base pointers */ #define CMP_BASE_PTRS { CMP0 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn } /*! * @} @@ -1041,6 +1148,8 @@ typedef struct { #define CMT_BASE_ADDRS { CMT_BASE } /** Array initializer of CMT peripheral base pointers */ #define CMT_BASE_PTRS { CMT } +/** Interrupt vectors for the CMT peripheral type */ +#define CMT_IRQS { CMT_IRQn } /*! * @} @@ -1168,6 +1277,8 @@ typedef struct { #define DAC_BASE_ADDRS { DAC0_BASE } /** Array initializer of DAC peripheral base pointers */ #define DAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC0_IRQn } /*! * @} @@ -1946,6 +2057,8 @@ typedef struct { #define DMA_BASE_ADDRS { DMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } } /*! * @} @@ -2394,6 +2507,8 @@ typedef struct { #define FTFA_BASE_ADDRS { FTFA_BASE } /** Array initializer of FTFA peripheral base pointers */ #define FTFA_BASE_PTRS { FTFA } +/** Interrupt vectors for the FTFA peripheral type */ +#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } /*! * @} @@ -3184,6 +3299,8 @@ typedef struct { #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } /** Array initializer of I2C peripheral base pointers */ #define I2C_BASE_PTRS { I2C0, I2C1 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } /*! * @} @@ -3419,6 +3536,8 @@ typedef struct { #define LLWU_BASE_ADDRS { LLWU_BASE } /** Array initializer of LLWU peripheral base pointers */ #define LLWU_BASE_PTRS { LLWU } +/** Interrupt vectors for the LLWU peripheral type */ +#define LLWU_IRQS { LLWU_IRQn } /*! * @} @@ -3510,6 +3629,8 @@ typedef struct { #define LPTMR_BASE_ADDRS { LPTMR0_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } /*! * @} @@ -3820,6 +3941,9 @@ typedef struct { #define LPUART_BASE_ADDRS { LPUART0_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn } /*! * @} @@ -4089,6 +4213,8 @@ typedef struct { #define LTC_BASE_ADDRS { LTC0_BASE } /** Array initializer of LTC peripheral base pointers */ #define LTC_BASE_PTRS { LTC0 } +/** Interrupt vectors for the LTC peripheral type */ +#define LTC_IRQS { LTC0_IRQn } /*! * @} @@ -4270,6 +4396,8 @@ typedef struct { #define MCG_BASE_ADDRS { MCG_BASE } /** Array initializer of MCG peripheral base pointers */ #define MCG_BASE_PTRS { MCG } +/** Interrupt vectors for the MCG peripheral type */ +#define MCG_IRQS { MCG_IRQn } /*! * @} @@ -5020,6 +5148,8 @@ typedef struct { #define PIT_BASE_ADDRS { PIT_BASE } /** Array initializer of PIT peripheral base pointers */ #define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn } } /*! * @} @@ -5111,6 +5241,8 @@ typedef struct { #define PMC_BASE_ADDRS { PMC_BASE } /** Array initializer of PMC peripheral base pointers */ #define PMC_BASE_PTRS { PMC } +/** Interrupt vectors for the PMC peripheral type */ +#define PMC_IRQS { LVD_LVW_DCDC_IRQn } /*! * @} @@ -5217,6 +5349,8 @@ typedef struct { #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORTA, PORTB, PORTC } +/** Interrupt vectors for the PORT peripheral type */ +#define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn } /*! * @} @@ -6041,6 +6175,9 @@ typedef struct { #define RTC_BASE_ADDRS { RTC_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } /*! * @} @@ -6774,6 +6911,8 @@ typedef struct { #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } /** Array initializer of SPI peripheral base pointers */ #define SPI_BASE_PTRS { SPI0, SPI1 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } /*! * @} @@ -7015,6 +7154,8 @@ typedef struct { #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } /** Array initializer of TPM peripheral base pointers */ #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } +/** Interrupt vectors for the TPM peripheral type */ +#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } /*! * @} @@ -7524,6 +7665,8 @@ typedef struct { #define TRNG_BASE_ADDRS { TRNG0_BASE } /** Array initializer of TRNG peripheral base pointers */ #define TRNG_BASE_PTRS { TRNG0 } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG0_IRQn } /*! * @} @@ -7639,6 +7782,8 @@ typedef struct { #define TSI_BASE_ADDRS { TSI0_BASE } /** Array initializer of TSI peripheral base pointers */ #define TSI_BASE_PTRS { TSI0 } +/** Interrupt vectors for the TSI peripheral type */ +#define TSI_IRQS { TSI0_IRQn } /*! * @} @@ -12741,6 +12886,43 @@ typedef struct { */ /* end of group Peripheral_access_layer */ +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ diff --git a/cpu/kw41z/include/vendor/MKW21Z4_features.h b/cpu/kw41z/include/vendor/MKW21Z4_features.h new file mode 100644 index 0000000000000..f9e93c01dc69f --- /dev/null +++ b/cpu/kw41z/include/vendor/MKW21Z4_features.h @@ -0,0 +1,1781 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2015-09-23 +** Build: b170228 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MKW21Z4_FEATURES_H_ +#define _MKW21Z4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (1) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (1) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (2) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (3) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (3) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (1) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (3) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (1) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (1) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (2) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) + +/* DCDC module features */ + +/* @brief Has VDD1P5 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) +/* @brief Has VDD1P45 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLASH module features */ + +#if defined(CPU_MKW21Z256VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKW21Z512VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKW21Z256VHT4) */ + +/* GENFSK module features */ + +/* No feature definitions */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) + +/* LLWU module features */ + +/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) +/* @brief Has pins 8-15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) +/* @brief Maximum number of internal modules connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) +/* @brief Number of digital filters. */ +#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) +/* @brief Has MF register. */ +#define FSL_FEATURE_LLWU_HAS_MF (0) +/* @brief Has PF register. */ +#define FSL_FEATURE_LLWU_HAS_PF (0) +/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ +#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +/* @brief Has no internal module wakeup flag register. */ +#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) +/* @brief Has external pin 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) +/* @brief Has external pin 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) +/* @brief Has external pin 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) +/* @brief Has external pin 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) +/* @brief Has external pin 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) +/* @brief Has external pin 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) +/* @brief Has external pin 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) +/* @brief Has external pin 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) +/* @brief Has external pin 8 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) +/* @brief Has external pin 9 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) +/* @brief Has external pin 10 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) +/* @brief Has external pin 11 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) +/* @brief Has external pin 12 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) +/* @brief Has external pin 13 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) +/* @brief Has external pin 14 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) +/* @brief Has external pin 15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) +/* @brief Has external pin 16 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) +/* @brief Has external pin 17 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) +/* @brief Has external pin 18 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) +/* @brief Has external pin 19 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) +/* @brief Has external pin 20 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) +/* @brief Has external pin 21 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) +/* @brief Has external pin 22 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) +/* @brief Has external pin 23 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) +/* @brief Has external pin 24 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) +/* @brief Has external pin 25 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) +/* @brief Has external pin 26 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) +/* @brief Has external pin 27 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) +/* @brief Has external pin 28 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) +/* @brief Has external pin 29 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) +/* @brief Has external pin 30 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) +/* @brief Has external pin 31 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) +/* @brief Has internal module 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) +/* @brief Has internal module 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) +/* @brief Has internal module 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) +/* @brief Has internal module 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) +/* @brief Has internal module 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) +/* @brief Has internal module 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) +/* @brief Has internal module 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) +/* @brief Has internal module 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) +/* @brief Has Version ID Register (LLWU_VERID). */ +#define FSL_FEATURE_LLWU_HAS_VERID (0) +/* @brief Has Parameter Register (LLWU_PARAM). */ +#define FSL_FEATURE_LLWU_HAS_PARAM (0) +/* @brief Width of registers of the LLWU. */ +#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) +/* @brief Has DMA Enable register (LLWU_DE). */ +#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* LPUART module features */ + +/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ +#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* LTC module features */ + +/* @brief LTC module supports DES algorithm. */ +#define FSL_FEATURE_LTC_HAS_DES (0) +/* @brief LTC module supports PKHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_PKHA (0) +/* @brief LTC module supports SHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_SHA (0) +/* @brief LTC module supports AES GCM mode. */ +#define FSL_FEATURE_LTC_HAS_GCM (0) +/* @brief LTC module supports DPAMS registers. */ +#define FSL_FEATURE_LTC_HAS_DPAMS (0) +/* @brief LTC module supports AES with 24 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES192 (0) +/* @brief LTC module supports AES with 32 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES256 (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (0) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (0) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (0) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (0) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (0) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (1) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RADIO module features */ + +/* @brief Zigbee availability. */ +#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) +/* @brief Bluetooth availability. */ +#define FSL_FEATURE_RADIO_HAS_BLE (0) +/* @brief ANT availability */ +#define FSL_FEATURE_RADIO_HAS_ANT (1) +/* @brief Generic FSK module availability */ +#define FSL_FEATURE_RADIO_HAS_GENFSK (1) +/* @brief Major version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) +/* @brief Minor version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MINOR (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (0) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RSIM module features */ + +/* No feature definitions */ + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (1) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (4) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) + +/* TRNG module features */ + +/* No feature definitions */ + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* XCVR_ANALOG module features */ + +/* No feature definitions */ + +/* XCVR_PHY module features */ + +/* No feature definitions */ + +/* ZLL module features */ + +/* No feature definitions */ + +#endif /* _MKW21Z4_FEATURES_H_ */ + diff --git a/cpu/kw41z/include/vendor/MKW31Z4.h b/cpu/kw41z/include/vendor/MKW31Z4.h index 689fe7e83d1a2..6b1f4e982a814 100644 --- a/cpu/kw41z/include/vendor/MKW31Z4.h +++ b/cpu/kw41z/include/vendor/MKW31Z4.h @@ -1,23 +1,23 @@ /* ** ################################################################### ** Processors: MKW31Z256VHT4 +** MKW31Z512CAT4 ** MKW31Z512VHT4 ** ** Compilers: Keil ARM C/C++ Compiler ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** ** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 ** Version: rev. 1.0, 2015-09-23 -** Build: b160720 +** Build: b170213 ** ** Abstract: ** CMSIS Peripheral Access Layer for MKW31Z4 ** -** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -28,7 +28,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -43,8 +43,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2015-09-23) @@ -85,6 +85,9 @@ #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ @@ -148,13 +151,114 @@ typedef enum IRQn { #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_MKW31Z4.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0Reserved4 = 4|0x100U, /**< Reserved4 */ + kDmaRequestMux0Reserved5 = 5|0x100U, /**< Reserved5 */ + kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */ + kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ + kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ + kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ + kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ + kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ + kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ + kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ + kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ + kDmaRequestMux0LTC0InputFIFO = 20|0x100U, /**< LTC0 Input FIFO. */ + kDmaRequestMux0LTC0OutputFIFO = 21|0x100U, /**< LTC0 Output FIFO. */ + kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ + kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ + kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ + kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ + kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ + kDmaRequestMux0Reserved28 = 28|0x100U, /**< Reserved28 */ + kDmaRequestMux0Reserved29 = 29|0x100U, /**< Reserved29 */ + kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ + kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ + kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ + kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ + kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ + kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ + kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ + kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ + kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ + kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ + kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0Reserved52 = 52|0x100U, /**< Reserved52 */ + kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ + kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ + kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ + kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ + kDmaRequestMux0TSI0 = 57|0x100U, /**< TSI0. */ + kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ + kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -434,6 +538,8 @@ typedef struct { #define ADC_BASE_ADDRS { ADC0_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } /*! * @} @@ -972,6 +1078,8 @@ typedef struct { #define CMP_BASE_ADDRS { CMP0_BASE } /** Array initializer of CMP peripheral base pointers */ #define CMP_BASE_PTRS { CMP0 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn } /*! * @} @@ -1111,6 +1219,8 @@ typedef struct { #define CMT_BASE_ADDRS { CMT_BASE } /** Array initializer of CMT peripheral base pointers */ #define CMT_BASE_PTRS { CMT } +/** Interrupt vectors for the CMT peripheral type */ +#define CMT_IRQS { CMT_IRQn } /*! * @} @@ -1238,6 +1348,8 @@ typedef struct { #define DAC_BASE_ADDRS { DAC0_BASE } /** Array initializer of DAC peripheral base pointers */ #define DAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC0_IRQn } /*! * @} @@ -2016,6 +2128,8 @@ typedef struct { #define DMA_BASE_ADDRS { DMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } } /*! * @} @@ -2464,6 +2578,8 @@ typedef struct { #define FTFA_BASE_ADDRS { FTFA_BASE } /** Array initializer of FTFA peripheral base pointers */ #define FTFA_BASE_PTRS { FTFA } +/** Interrupt vectors for the FTFA peripheral type */ +#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } /*! * @} @@ -3254,6 +3370,8 @@ typedef struct { #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } /** Array initializer of I2C peripheral base pointers */ #define I2C_BASE_PTRS { I2C0, I2C1 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } /*! * @} @@ -3489,6 +3607,8 @@ typedef struct { #define LLWU_BASE_ADDRS { LLWU_BASE } /** Array initializer of LLWU peripheral base pointers */ #define LLWU_BASE_PTRS { LLWU } +/** Interrupt vectors for the LLWU peripheral type */ +#define LLWU_IRQS { LLWU_IRQn } /*! * @} @@ -3580,6 +3700,8 @@ typedef struct { #define LPTMR_BASE_ADDRS { LPTMR0_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } /*! * @} @@ -3890,6 +4012,9 @@ typedef struct { #define LPUART_BASE_ADDRS { LPUART0_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn } /*! * @} @@ -4159,6 +4284,8 @@ typedef struct { #define LTC_BASE_ADDRS { LTC0_BASE } /** Array initializer of LTC peripheral base pointers */ #define LTC_BASE_PTRS { LTC0 } +/** Interrupt vectors for the LTC peripheral type */ +#define LTC_IRQS { LTC0_IRQn } /*! * @} @@ -4340,6 +4467,8 @@ typedef struct { #define MCG_BASE_ADDRS { MCG_BASE } /** Array initializer of MCG peripheral base pointers */ #define MCG_BASE_PTRS { MCG } +/** Interrupt vectors for the MCG peripheral type */ +#define MCG_IRQS { MCG_IRQn } /*! * @} @@ -5090,6 +5219,8 @@ typedef struct { #define PIT_BASE_ADDRS { PIT_BASE } /** Array initializer of PIT peripheral base pointers */ #define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn } } /*! * @} @@ -5181,6 +5312,8 @@ typedef struct { #define PMC_BASE_ADDRS { PMC_BASE } /** Array initializer of PMC peripheral base pointers */ #define PMC_BASE_PTRS { PMC } +/** Interrupt vectors for the PMC peripheral type */ +#define PMC_IRQS { LVD_LVW_DCDC_IRQn } /*! * @} @@ -5287,6 +5420,8 @@ typedef struct { #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORTA, PORTB, PORTC } +/** Interrupt vectors for the PORT peripheral type */ +#define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn } /*! * @} @@ -6111,6 +6246,9 @@ typedef struct { #define RTC_BASE_ADDRS { RTC_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } /*! * @} @@ -6844,6 +6982,8 @@ typedef struct { #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } /** Array initializer of SPI peripheral base pointers */ #define SPI_BASE_PTRS { SPI0, SPI1 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } /*! * @} @@ -7085,6 +7225,8 @@ typedef struct { #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } /** Array initializer of TPM peripheral base pointers */ #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } +/** Interrupt vectors for the TPM peripheral type */ +#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } /*! * @} @@ -7594,6 +7736,8 @@ typedef struct { #define TRNG_BASE_ADDRS { TRNG0_BASE } /** Array initializer of TRNG peripheral base pointers */ #define TRNG_BASE_PTRS { TRNG0 } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG0_IRQn } /*! * @} @@ -7709,6 +7853,8 @@ typedef struct { #define TSI_BASE_ADDRS { TSI0_BASE } /** Array initializer of TSI peripheral base pointers */ #define TSI_BASE_PTRS { TSI0 } +/** Interrupt vectors for the TSI peripheral type */ +#define TSI_IRQS { TSI0_IRQn } /*! * @} @@ -12108,6 +12254,43 @@ typedef struct { */ /* end of group Peripheral_access_layer */ +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ diff --git a/cpu/kw41z/include/vendor/MKW31Z4_features.h b/cpu/kw41z/include/vendor/MKW31Z4_features.h new file mode 100644 index 0000000000000..56b14a01a5b49 --- /dev/null +++ b/cpu/kw41z/include/vendor/MKW31Z4_features.h @@ -0,0 +1,2016 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2015-09-23 +** Build: b170228 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MKW31Z4_FEATURES_H_ +#define _MKW31Z4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (1) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (1) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (2) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (3) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (3) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (1) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (3) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (1) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (1) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* BTLE_RF module features */ + +/* No feature definitions */ + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (2) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) + +/* DCDC module features */ + +/* @brief Has VDD1P5 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) +/* @brief Has VDD1P45 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLASH module features */ + +#if defined(CPU_MKW31Z256VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKW31Z512CAT4) || defined(CPU_MKW31Z512VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKW31Z256VHT4) */ + +/* GENFSK module features */ + +/* No feature definitions */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) + +/* LLWU module features */ + +#if defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MKW31Z512CAT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#endif /* defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) */ + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* LPUART module features */ + +/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ +#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* LTC module features */ + +/* @brief LTC module supports DES algorithm. */ +#define FSL_FEATURE_LTC_HAS_DES (0) +/* @brief LTC module supports PKHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_PKHA (0) +/* @brief LTC module supports SHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_SHA (0) +/* @brief LTC module supports AES GCM mode. */ +#define FSL_FEATURE_LTC_HAS_GCM (0) +/* @brief LTC module supports DPAMS registers. */ +#define FSL_FEATURE_LTC_HAS_DPAMS (0) +/* @brief LTC module supports AES with 24 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES192 (0) +/* @brief LTC module supports AES with 32 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES256 (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (0) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (0) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (0) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (0) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (0) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (1) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RADIO module features */ + +/* @brief Zigbee availability. */ +#define FSL_FEATURE_RADIO_HAS_ZIGBEE (0) +/* @brief Bluetooth availability. */ +#define FSL_FEATURE_RADIO_HAS_BLE (1) +/* @brief ANT availability */ +#define FSL_FEATURE_RADIO_HAS_ANT (1) +/* @brief Generic FSK module availability */ +#define FSL_FEATURE_RADIO_HAS_GENFSK (1) +/* @brief Major version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) +/* @brief Minor version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MINOR (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (0) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RSIM module features */ + +/* No feature definitions */ + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (1) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (4) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) + +/* TRNG module features */ + +/* No feature definitions */ + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* XCVR_ANALOG module features */ + +/* No feature definitions */ + +/* XCVR_PHY module features */ + +/* No feature definitions */ + +#endif /* _MKW31Z4_FEATURES_H_ */ + diff --git a/cpu/kw41z/include/vendor/MKW41Z4.h b/cpu/kw41z/include/vendor/MKW41Z4.h index f434595bfa54e..08c1ee3aec107 100644 --- a/cpu/kw41z/include/vendor/MKW41Z4.h +++ b/cpu/kw41z/include/vendor/MKW41Z4.h @@ -1,23 +1,23 @@ /* ** ################################################################### ** Processors: MKW41Z256VHT4 +** MKW41Z512CAT4 ** MKW41Z512VHT4 ** ** Compilers: Keil ARM C/C++ Compiler ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** ** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 ** Version: rev. 1.0, 2015-09-23 -** Build: b160720 +** Build: b170213 ** ** Abstract: ** CMSIS Peripheral Access Layer for MKW41Z4 ** -** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -28,7 +28,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -43,8 +43,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2015-09-23) @@ -85,6 +85,9 @@ #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ @@ -154,6 +157,108 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ + kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ + kDmaRequestMux0Reserved4 = 4|0x100U, /**< Reserved4 */ + kDmaRequestMux0Reserved5 = 5|0x100U, /**< Reserved5 */ + kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */ + kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */ + kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ + kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ + kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ + kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ + kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ + kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ + kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ + kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ + kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ + kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ + kDmaRequestMux0LTC0InputFIFO = 20|0x100U, /**< LTC0 Input FIFO. */ + kDmaRequestMux0LTC0OutputFIFO = 21|0x100U, /**< LTC0 Output FIFO. */ + kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ + kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ + kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ + kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ + kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ + kDmaRequestMux0Reserved28 = 28|0x100U, /**< Reserved28 */ + kDmaRequestMux0Reserved29 = 29|0x100U, /**< Reserved29 */ + kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ + kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ + kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ + kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ + kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ + kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ + kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ + kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ + kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ + kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ + kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ + kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0Reserved52 = 52|0x100U, /**< Reserved52 */ + kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ + kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ + kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ + kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ + kDmaRequestMux0TSI0 = 57|0x100U, /**< TSI0. */ + kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ + kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -433,6 +538,8 @@ typedef struct { #define ADC_BASE_ADDRS { ADC0_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } /*! * @} @@ -971,6 +1078,8 @@ typedef struct { #define CMP_BASE_ADDRS { CMP0_BASE } /** Array initializer of CMP peripheral base pointers */ #define CMP_BASE_PTRS { CMP0 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn } /*! * @} @@ -1110,6 +1219,8 @@ typedef struct { #define CMT_BASE_ADDRS { CMT_BASE } /** Array initializer of CMT peripheral base pointers */ #define CMT_BASE_PTRS { CMT } +/** Interrupt vectors for the CMT peripheral type */ +#define CMT_IRQS { CMT_IRQn } /*! * @} @@ -1237,6 +1348,8 @@ typedef struct { #define DAC_BASE_ADDRS { DAC0_BASE } /** Array initializer of DAC peripheral base pointers */ #define DAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC0_IRQn } /*! * @} @@ -2015,6 +2128,8 @@ typedef struct { #define DMA_BASE_ADDRS { DMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } } /*! * @} @@ -2463,6 +2578,8 @@ typedef struct { #define FTFA_BASE_ADDRS { FTFA_BASE } /** Array initializer of FTFA peripheral base pointers */ #define FTFA_BASE_PTRS { FTFA } +/** Interrupt vectors for the FTFA peripheral type */ +#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } /*! * @} @@ -3253,6 +3370,8 @@ typedef struct { #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } /** Array initializer of I2C peripheral base pointers */ #define I2C_BASE_PTRS { I2C0, I2C1 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } /*! * @} @@ -3488,6 +3607,8 @@ typedef struct { #define LLWU_BASE_ADDRS { LLWU_BASE } /** Array initializer of LLWU peripheral base pointers */ #define LLWU_BASE_PTRS { LLWU } +/** Interrupt vectors for the LLWU peripheral type */ +#define LLWU_IRQS { LLWU_IRQn } /*! * @} @@ -3579,6 +3700,8 @@ typedef struct { #define LPTMR_BASE_ADDRS { LPTMR0_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } /*! * @} @@ -3889,6 +4012,9 @@ typedef struct { #define LPUART_BASE_ADDRS { LPUART0_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn } /*! * @} @@ -4158,6 +4284,8 @@ typedef struct { #define LTC_BASE_ADDRS { LTC0_BASE } /** Array initializer of LTC peripheral base pointers */ #define LTC_BASE_PTRS { LTC0 } +/** Interrupt vectors for the LTC peripheral type */ +#define LTC_IRQS { LTC0_IRQn } /*! * @} @@ -4339,6 +4467,8 @@ typedef struct { #define MCG_BASE_ADDRS { MCG_BASE } /** Array initializer of MCG peripheral base pointers */ #define MCG_BASE_PTRS { MCG } +/** Interrupt vectors for the MCG peripheral type */ +#define MCG_IRQS { MCG_IRQn } /*! * @} @@ -5089,6 +5219,8 @@ typedef struct { #define PIT_BASE_ADDRS { PIT_BASE } /** Array initializer of PIT peripheral base pointers */ #define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn } } /*! * @} @@ -5180,6 +5312,8 @@ typedef struct { #define PMC_BASE_ADDRS { PMC_BASE } /** Array initializer of PMC peripheral base pointers */ #define PMC_BASE_PTRS { PMC } +/** Interrupt vectors for the PMC peripheral type */ +#define PMC_IRQS { LVD_LVW_DCDC_IRQn } /*! * @} @@ -5286,6 +5420,8 @@ typedef struct { #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORTA, PORTB, PORTC } +/** Interrupt vectors for the PORT peripheral type */ +#define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn } /*! * @} @@ -6110,6 +6246,9 @@ typedef struct { #define RTC_BASE_ADDRS { RTC_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } /*! * @} @@ -6843,6 +6982,8 @@ typedef struct { #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } /** Array initializer of SPI peripheral base pointers */ #define SPI_BASE_PTRS { SPI0, SPI1 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } /*! * @} @@ -7084,6 +7225,8 @@ typedef struct { #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } /** Array initializer of TPM peripheral base pointers */ #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } +/** Interrupt vectors for the TPM peripheral type */ +#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } /*! * @} @@ -7593,6 +7736,8 @@ typedef struct { #define TRNG_BASE_ADDRS { TRNG0_BASE } /** Array initializer of TRNG peripheral base pointers */ #define TRNG_BASE_PTRS { TRNG0 } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG0_IRQn } /*! * @} @@ -7708,6 +7853,8 @@ typedef struct { #define TSI_BASE_ADDRS { TSI0_BASE } /** Array initializer of TSI peripheral base pointers */ #define TSI_BASE_PTRS { TSI0 } +/** Interrupt vectors for the TSI peripheral type */ +#define TSI_IRQS { TSI0_IRQn } /*! * @} @@ -12810,6 +12957,43 @@ typedef struct { */ /* end of group Peripheral_access_layer */ +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ diff --git a/cpu/kw41z/include/vendor/MKW41Z4_features.h b/cpu/kw41z/include/vendor/MKW41Z4_features.h new file mode 100644 index 0000000000000..7e7fee364b5c7 --- /dev/null +++ b/cpu/kw41z/include/vendor/MKW41Z4_features.h @@ -0,0 +1,2020 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2015-09-23 +** Build: b170228 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MKW41Z4_FEATURES_H_ +#define _MKW41Z4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (1) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (1) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (2) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (3) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (3) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (1) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (3) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (1) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (1) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* BTLE_RF module features */ + +/* No feature definitions */ + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (2) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) + +/* DCDC module features */ + +/* @brief Has VDD1P5 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) +/* @brief Has VDD1P45 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLASH module features */ + +#if defined(CPU_MKW41Z256VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKW41Z512CAT4) || defined(CPU_MKW41Z512VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKW41Z256VHT4) */ + +/* GENFSK module features */ + +/* No feature definitions */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) + +/* LLWU module features */ + +#if defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MKW41Z512CAT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#endif /* defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) */ + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* LPUART module features */ + +/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ +#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* LTC module features */ + +/* @brief LTC module supports DES algorithm. */ +#define FSL_FEATURE_LTC_HAS_DES (0) +/* @brief LTC module supports PKHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_PKHA (0) +/* @brief LTC module supports SHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_SHA (0) +/* @brief LTC module supports AES GCM mode. */ +#define FSL_FEATURE_LTC_HAS_GCM (0) +/* @brief LTC module supports DPAMS registers. */ +#define FSL_FEATURE_LTC_HAS_DPAMS (0) +/* @brief LTC module supports AES with 24 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES192 (0) +/* @brief LTC module supports AES with 32 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES256 (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (0) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (0) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (0) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (0) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (0) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (1) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RADIO module features */ + +/* @brief Zigbee availability. */ +#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) +/* @brief Bluetooth availability. */ +#define FSL_FEATURE_RADIO_HAS_BLE (1) +/* @brief ANT availability */ +#define FSL_FEATURE_RADIO_HAS_ANT (1) +/* @brief Generic FSK module availability */ +#define FSL_FEATURE_RADIO_HAS_GENFSK (1) +/* @brief Major version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) +/* @brief Minor version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MINOR (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (0) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RSIM module features */ + +/* No feature definitions */ + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (1) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (4) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) + +/* TRNG module features */ + +/* No feature definitions */ + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* XCVR_ANALOG module features */ + +/* No feature definitions */ + +/* XCVR_PHY module features */ + +/* No feature definitions */ + +/* ZLL module features */ + +/* No feature definitions */ + +#endif /* _MKW41Z4_FEATURES_H_ */ + diff --git a/cpu/kw41z/vendor/Common/EmbeddedTypes.h b/cpu/kw41z/vendor/Common/EmbeddedTypes.h new file mode 100644 index 0000000000000..822661649c025 --- /dev/null +++ b/cpu/kw41z/vendor/Common/EmbeddedTypes.h @@ -0,0 +1,181 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* +* \file +* +* This file holds type definitions that maps the standard c-types into types +* with guaranteed sizes. The types are target/platform specific and must be edited +* for each new target/platform. +* The header file also provides definitions for TRUE, FALSE and NULL. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _EMBEDDEDTYPES_H_ +#define _EMBEDDEDTYPES_H_ + + +/************************************************************************************ +* +* INCLUDES +* +************************************************************************************/ + +#include + + +/************************************************************************************ +* +* TYPE DEFINITIONS +* +************************************************************************************/ + +/* boolean types */ +typedef uint8_t bool_t; + +typedef uint8_t index_t; + +/* TRUE/FALSE definition*/ +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/* null pointer definition*/ +#ifndef NULL +#define NULL (( void * )( 0x0UL )) +#endif + +#if defined(__GNUC__) +#define PACKED_STRUCT struct __attribute__ ((__packed__)) +#define PACKED_UNION union __attribute__ ((__packed__)) +#elif defined(__IAR_SYSTEMS_ICC__) +#define PACKED_STRUCT __packed struct +#define PACKED_UNION __packed union +#else +#define PACKED_STRUCT struct +#define PACKED_UNION union +#endif + +typedef unsigned char uintn8_t; +typedef unsigned long uintn32_t; + +typedef unsigned char uchar_t; + +#if !defined(MIN) +#define MIN(a,b) (((a) < (b))?(a):(b)) +#endif + +#if !defined(MAX) +#define MAX(a,b) (((a) > (b))?(a):(b)) +#endif + +/* Compute the number of elements of an array */ +#define NumberOfElements(x) (sizeof(x)/sizeof((x)[0])) + +/* Compute the size of a string initialized with quotation marks */ +#define SizeOfString(string) (sizeof(string) - 1) + +#define GetRelAddr(strct, member) ((uint32_t)&(((strct*)(void *)0)->member)) +#define GetSizeOfMember(strct, member) sizeof(((strct*)(void *)0)->member) + +/* Type definitions for link configuration of instantiable layers */ +#define gInvalidInstanceId_c (instanceId_t)(-1) +typedef uint32_t instanceId_t; + +/* Shift definitions */ +#define SHIFT0 (0) +#define SHIFT1 (1) +#define SHIFT2 (2) +#define SHIFT3 (3) +#define SHIFT4 (4) +#define SHIFT5 (5) +#define SHIFT6 (6) +#define SHIFT7 (7) +#define SHIFT8 (8) +#define SHIFT9 (9) +#define SHIFT10 (10) +#define SHIFT11 (11) +#define SHIFT12 (12) +#define SHIFT13 (13) +#define SHIFT14 (14) +#define SHIFT15 (15) +#define SHIFT16 (16) +#define SHIFT17 (17) +#define SHIFT18 (18) +#define SHIFT19 (19) +#define SHIFT20 (20) +#define SHIFT21 (21) +#define SHIFT22 (22) +#define SHIFT23 (23) +#define SHIFT24 (24) +#define SHIFT25 (25) +#define SHIFT26 (26) +#define SHIFT27 (27) +#define SHIFT28 (28) +#define SHIFT29 (29) +#define SHIFT30 (30) +#define SHIFT31 (31) + +#define SHIFT32 (32) +#define SHIFT33 (33) +#define SHIFT34 (34) +#define SHIFT35 (35) +#define SHIFT36 (36) +#define SHIFT37 (37) +#define SHIFT38 (38) +#define SHIFT39 (39) +#define SHIFT40 (40) +#define SHIFT41 (41) +#define SHIFT42 (42) +#define SHIFT43 (43) +#define SHIFT44 (44) +#define SHIFT45 (45) +#define SHIFT46 (46) +#define SHIFT47 (47) +#define SHIFT48 (48) +#define SHIFT49 (49) +#define SHIFT50 (50) +#define SHIFT51 (51) +#define SHIFT52 (52) +#define SHIFT53 (53) +#define SHIFT54 (54) +#define SHIFT55 (55) +#define SHIFT56 (56) +#define SHIFT57 (57) +#define SHIFT58 (58) +#define SHIFT59 (59) +#define SHIFT60 (60) +#define SHIFT61 (61) +#define SHIFT62 (62) +#define SHIFT63 (63) + + +#endif /* _EMBEDDEDTYPES_H_ */ diff --git a/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction.h b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction.h new file mode 100644 index 0000000000000..8f974571164b9 --- /dev/null +++ b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction.h @@ -0,0 +1,608 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#ifndef _FSL_OS_ABSTRACTION_H_ +#define _FSL_OS_ABSTRACTION_H_ + +#include "EmbeddedTypes.h" +#include "fsl_os_abstraction_config.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ +/*! @brief Type for the Task Priority*/ + typedef uint16_t osaTaskPriority_t; +/*! @brief Type for the timer definition*/ + typedef enum { + osaTimer_Once = 0, /*!< one-shot timer*/ + osaTimer_Periodic = 1 /*!< repeating timer*/ + } osaTimer_t; + /*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */ + typedef void* osaTaskId_t; +/*! @brief Type for the parameter to be passed to the task at its creation */ + typedef void* osaTaskParam_t; + /*! @brief Type for task pointer. Task prototype declaration */ + typedef void (*osaTaskPtr_t) (osaTaskParam_t task_param); +/*! @brief Type for the semaphore handler, returned by the OSA_SemaphoreCreate function. */ + typedef void* osaSemaphoreId_t; +/*! @brief Type for the mutex handler, returned by the OSA_MutexCreate function. */ + typedef void* osaMutexId_t; +/*! @brief Type for the event handler, returned by the OSA_EventCreate function. */ + typedef void* osaEventId_t; +/*! @brief Type for an event flags group, bit 32 is reserved. */ + typedef uint32_t osaEventFlags_t; +/*! @brief Message definition. */ + typedef void* osaMsg_t; +/*! @brief Type for the message queue handler, returned by the OSA_MsgQCreate function. */ + typedef void* osaMsgQId_t; + /*! @brief Type for the Timer handler, returned by the OSA_TimerCreate function. */ + typedef void *osaTimerId_t; +/*! @brief Type for the Timer callback function pointer. */ + typedef void (*osaTimerFctPtr_t) (void const *argument); +/*! @brief Thread Definition structure contains startup information of a thread.*/ +typedef struct osaThreadDef_tag { + osaTaskPtr_t pthread; /*!< start address of thread function*/ + uint32_t tpriority; /*!< initial thread priority*/ + uint32_t instances; /*!< maximum number of instances of that thread function*/ + uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ + uint32_t *tstack; + void *tlink; + uint8_t *tname; + bool_t useFloat; +} osaThreadDef_t; +/*! @brief Thread Link Definition structure .*/ +typedef struct osaThreadLink_tag{ + uint8_t link[12]; + osaTaskId_t osThreadId; + osaThreadDef_t *osThreadDefHandle; + uint32_t *osThreadStackHandle; +}osaThreadLink_t, *osaThreadLinkHandle_t; + +/*! @Timer Definition structure contains timer parameters.*/ +typedef struct osaTimerDef_tag { + osaTimerFctPtr_t pfCallback; /* < start address of a timer function */ + void *argument; +} osaTimerDef_t; +/*! @brief Defines the return status of OSA's functions */ +typedef enum osaStatus_tag +{ + osaStatus_Success = 0U, /*!< Success */ + osaStatus_Error = 1U, /*!< Failed */ + osaStatus_Timeout = 2U, /*!< Timeout occurs while waiting */ + osaStatus_Idle = 3U /*!< Used for bare metal only, the wait object is not ready + and timeout still not occur */ +}osaStatus_t; + + +/*! ********************************************************************************* +************************************************************************************* +* Public macros +************************************************************************************* +********************************************************************************** */ +#if defined (FSL_RTOS_MQX) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_FREE_RTOS) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_UCOSII) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_UCOSIII) + #define USE_RTOS 1 +#else + #define USE_RTOS 0 +#endif + +#define OSA_PRIORITY_IDLE (6) +#define OSA_PRIORITY_LOW (5) +#define OSA_PRIORITY_BELOW_NORMAL (4) +#define OSA_PRIORITY_NORMAL (3) +#define OSA_PRIORITY_ABOVE_NORMAL (2) +#define OSA_PRIORITY_HIGH (1) +#define OSA_PRIORITY_REAL_TIME (0) +#define OSA_TASK_PRIORITY_MAX (0) +#define OSA_TASK_PRIORITY_MIN (15) +#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define osaWaitForever_c ((uint32_t)(-1)) +#define osaEventFlagsAll_c ((osaEventFlags_t)(0x00FFFFFF)) +#define osThreadStackArray(name) osThread_##name##_stack +#define osThreadStackDef(name, stacksize, instances) \ + uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize)*(instances)]; + +/* ==== Thread Management ==== */ + +/* Create a Thread Definition with function, priority, and stack requirements. + * \param name name of the thread function. + * \param priority initial priority of the thread function. + * \param instances number of possible thread instances. + * \param stackSz stack size (in bytes) requirements for the thread function. + * \param useFloat + */ +#if defined(FSL_RTOS_MQX) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadLink_t osThreadLink_##name[instances] = {0}; \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + osThreadLink_##name, \ + (uint8_t*) #name,\ + (useFloat)} +#elif defined (FSL_RTOS_UCOSII) + #if gTaskMultipleInstancesManagement_c +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadLink_t osThreadLink_##name[instances] = {0}; \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + osThreadLink_##name, \ + (uint8_t*) #name,\ + (useFloat)} +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + NULL, \ + (uint8_t*) #name,\ + (useFloat)} +#endif +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + NULL, \ + NULL, \ + (uint8_t*) #name,\ + (useFloat)} +#endif +/* Access a Thread defintion. + * \param name name of the thread definition object. + */ +#define OSA_TASK(name) \ +&os_thread_def_##name + +#define OSA_TASK_PROTO(name) \ +extern osaThreadDef_t os_thread_def_##name +/* ==== Timer Management ==== + * Define a Timer object. + * \param name name of the timer object. + * \param function name of the timer call back function. + */ + +#define OSA_TIMER_DEF(name, function) \ +osaTimerDef_t os_timer_def_##name = \ +{ (function), NULL } + +/* Access a Timer definition. + * \param name name of the timer object. + */ +#define OSA_TIMER(name) \ +&os_timer_def_##name + + +/***************************************************************************** +****************************************************************************** +* Public memory declarations +****************************************************************************** +*****************************************************************************/ +extern const uint8_t gUseRtos_c; + + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! + * @name Task management + * @{ + */ + +/*! + * @brief Creates a task. + * + * This function is used to create task based on the resources defined + * by the macro OSA_TASK_DEFINE. + * + * @param thread_def pointer to the osaThreadDef_t structure which defines the task. + * @param task_param Pointer to be passed to the task when it is created. + * + * @retval taskId The task is successfully created. + * @retval NULL The task can not be created.. + * + * Example: + @code + osaTaskId_t taskId; + OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);; + taskId = OSA__TaskCreate(OSA__TASK(Job1), (osaTaskParam_t)NULL); + @endcode + */ +osaTaskId_t OSA_TaskCreate(osaThreadDef_t *thread_def, osaTaskParam_t task_param); + +/*! + * @brief Gets the handler of active task. + * + * @return Handler to current active task. + */ +osaTaskId_t OSA_TaskGetId(void); + +/*! + * @brief Puts the active task to the end of scheduler's queue. + * + * When a task calls this function, it gives up the CPU and puts itself to the + * end of a task ready list. + * + * @retval osaStatus_Success The function is called successfully. + * @retval osaStatus_Error Error occurs with this function. + */ +osaStatus_t OSA_TaskYield(void); + +/*! + * @brief Gets the priority of a task. + * + * @param taskId The handler of the task whose priority is received. + * + * @return Task's priority. + */ +osaTaskPriority_t OSA_TaskGetPriority(osaTaskId_t taskId); + +/*! + * @brief Sets the priority of a task. + * + * @param taskId The handler of the task whose priority is set. + * @param taskPriority The priority to set. + * + * @retval osaStatus_Success Task's priority is set successfully. + * @retval osaStatus_Error Task's priority can not be set. + */ +osaStatus_t OSA_TaskSetPriority(osaTaskId_t taskId, osaTaskPriority_t taskPriority); +/*! + * @brief Destroys a previously created task. + * + * @param taskId The handler of the task to destroy. Returned by the OSA_TaskCreate function. + * + * @retval osaStatus_Success The task was successfully destroyed. + * @retval osaStatus_Error Task destruction failed or invalid parameter. + */ +osaStatus_t OSA_TaskDestroy(osaTaskId_t taskId); + +/*! + * @brief Creates a semaphore with a given value. + * + * This function creates a semaphore and sets the value to the parameter + * initValue. + * + * @param initValue Initial value the semaphore will be set to. + * + * @retval handler to the new semaphore if the semaphore is created successfully. + * @retval NULL if the semaphore can not be created. + * + * + */ +osaSemaphoreId_t OSA_SemaphoreCreate(uint32_t initValue); + +/*! + * @brief Destroys a previously created semaphore. + * + * @param semId Pointer to the semaphore to destroy. + * + * @retval osaStatus_Success The semaphore is successfully destroyed. + * @retval osaStatus_Error The semaphore can not be destroyed. + */ +osaStatus_t OSA_SemaphoreDestroy(osaSemaphoreId_t semId); + +/*! + * @brief Pending a semaphore with timeout. + * + * This function checks the semaphore's counting value. If it is positive, + * decreases it and returns osaStatus_Success. Otherwise, a timeout is used + * to wait. + * + * @param semId Pointer to the semaphore. + * @param millisec The maximum number of milliseconds to wait if semaphore is not + * positive. Pass osaWaitForever_c to wait indefinitely, pass 0 + * will return osaStatus_Timeout immediately. + * + * @retval osaStatus_Success The semaphore is received. + * @retval osaStatus_Timeout The semaphore is not received within the specified 'timeout'. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_SemaphoreWait(osaSemaphoreId_t semId, uint32_t millisec); + +/*! + * @brief Signals for someone waiting on the semaphore to wake up. + * + * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases + * the semaphore's counting value. + * + * @param semId Pointer to the semaphore to signal. + * + * @retval osaStatus_Success The semaphore is successfully signaled. + * @retval osaStatus_Error The object can not be signaled or invalid parameter. + * + */ +osaStatus_t OSA_SemaphorePost(osaSemaphoreId_t semId); + +/*! + * @brief Create an unlocked mutex. + * + * This function creates a non-recursive mutex and sets it to unlocked status. + * + * @param none. + * + * @retval handler to the new mutex if the mutex is created successfully. + * @retval NULL if the mutex can not be created. + */ +osaMutexId_t OSA_MutexCreate(void); + +/*! + * @brief Waits for a mutex and locks it. + * + * This function checks the mutex's status. If it is unlocked, locks it and returns the + * osaStatus_Success. Otherwise, waits for a timeout in milliseconds to lock. + * + * @param mutexId Pointer to the Mutex. + * @param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return osaStatus_Timeout + * immediately. + * + * @retval osaStatus_Success The mutex is locked successfully. + * @retval osaStatus_Timeout Timeout occurred. + * @retval osaStatus_Error Incorrect parameter was passed. + * + * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked. + */ +osaStatus_t OSA_MutexLock(osaMutexId_t mutexId, uint32_t millisec); + +/*! + * @brief Unlocks a previously locked mutex. + * + * @param mutexId Pointer to the Mutex. + * + * @retval osaStatus_Success The mutex is successfully unlocked. + * @retval osaStatus_Error The mutex can not be unlocked or invalid parameter. + */ +osaStatus_t OSA_MutexUnlock(osaMutexId_t mutexId); + +/*! + * @brief Destroys a previously created mutex. + * + * @param mutexId Pointer to the Mutex. + * + * @retval osaStatus_Success The mutex is successfully destroyed. + * @retval osaStatus_Error The mutex can not be destroyed. + * + */ +osaStatus_t OSA_MutexDestroy(osaMutexId_t mutexId); + +/*! + * @brief Initializes an event object with all flags cleared. + * + * This function creates an event object and set its clear mode. If autoClear + * is TRUE, when a task gets the event flags, these flags will be + * cleared automatically. Otherwise these flags must + * be cleared manually. + * + * @param autoClear TRUE The event is auto-clear. + * FALSE The event manual-clear + * @retval handler to the new event if the event is created successfully. + * @retval NULL if the event can not be created. + */ +osaEventId_t OSA_EventCreate(bool_t autoClear); + +/*! + * @brief Sets one or more event flags. + * + * Sets specified flags of an event object. + * + * @param eventId Pointer to the event. + * @param flagsToSet Flags to be set. + * + * @retval osaStatus_Success The flags were successfully set. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_EventSet(osaEventId_t eventId, osaEventFlags_t flagsToSet); + +/*! + * @brief Clears one or more flags. + * + * Clears specified flags of an event object. + * + * @param eventId Pointer to the event. + * @param flagsToClear Flags to be clear. + * + * @retval osaStatus_Success The flags were successfully cleared. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_EventClear(osaEventId_t eventId, osaEventFlags_t flagsToClear); + +/*! + * @brief Waits for specified event flags to be set. + * + * This function waits for a combination of flags to be set in an event object. + * Applications can wait for any/all bits to be set. Also this function could + * obtain the flags who wakeup the waiting task. + * + * @param eventId Pointer to the event. + * @param flagsToWait Flags that to wait. + * @param waitAll Wait all flags or any flag to be set. + * @param millisec The maximum number of milliseconds to wait for the event. + * If the wait condition is not met, pass osaWaitForever_c will + * wait indefinitely, pass 0 will return osaStatus_Timeout + * immediately. + * @param setFlags Flags that wakeup the waiting task are obtained by this parameter. + * + * @retval osaStatus_Success The wait condition met and function returns successfully. + * @retval osaStatus_Timeout Has not met wait condition within timeout. + * @retval osaStatus_Error An incorrect parameter was passed. + + * + * @note Please pay attention to the flags bit width, FreeRTOS uses the most + * significant 8 bis as control bits, so do not wait these bits while using + * FreeRTOS. + * + */ +osaStatus_t OSA_EventWait(osaEventId_t eventId, osaEventFlags_t flagsToWait, bool_t waitAll, uint32_t millisec, osaEventFlags_t *pSetFlags); + +/*! + * @brief Destroys a previously created event object. + * + * @param eventId Pointer to the event. + * + * @retval osaStatus_Success The event is successfully destroyed. + * @retval osaStatus_Error Event destruction failed. + */ +osaStatus_t OSA_EventDestroy(osaEventId_t eventId); + +/*! + * @brief Initializes a message queue. + * + * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*. + * + * @param msgNo :number of messages the message queue should accommodate. + * This parameter should not exceed osNumberOfMessages defined in OSAbstractionConfig.h. + * +* @return: Handler to access the queue for put and get operations. If message queue + * creation failed, return NULL. + */ +osaMsgQId_t OSA_MsgQCreate(uint32_t msgNo); + +/*! + * @brief Puts a message at the end of the queue. + * + * This function puts a message to the end of the message queue. If the queue + * is full, this function returns the osaStatus_Error; + * + * @param msgQId pointer to queue returned by the OSA_MsgQCreate function. + * @param pMessage Pointer to the message to be put into the queue. + * + * @retval osaStatus_Success Message successfully put into the queue. + * @retval osaStatus_Error The queue was full or an invalid parameter was passed. + */ +osaStatus_t OSA_MsgQPut(osaMsgQId_t msgQId, osaMsg_t pMessage); + +/*! + * @brief Reads and remove a message at the head of the queue. + * + * This function gets a message from the head of the message queue. If the + * queue is empty, timeout is used to wait. + * + * @param msgQId Queue handler returned by the OSA_MsgQCreate function. + * @param pMessage Pointer to a memory to save the message. + * @param millisec The number of milliseconds to wait for a message. If the + * queue is empty, pass osaWaitForever_c will wait indefinitely, + * pass 0 will return osaStatus_Timeout immediately. + * + * @retval osaStatus_Success Message successfully obtained from the queue. + * @retval osaStatus_Timeout The queue remains empty after timeout. + * @retval osaStatus_Error Invalid parameter. + */ +osaStatus_t OSA_MsgQGet(osaMsgQId_t msgQId, osaMsg_t pMessage, uint32_t millisec); + +/*! + * @brief Destroys a previously created queue. + * + * @param msgQId queue handler returned by the OSA_MsgQCreate function. + * + * @retval osaStatus_Success The queue was successfully destroyed. + * @retval osaStatus_Error Message queue destruction failed. +*/ +osaStatus_t OSA_MsgQDestroy(osaMsgQId_t msgQId); + +/*! + * @brief Enable all interrupts. +*/ +void OSA_InterruptEnable(void); + +/*! + * @brief Disable all interrupts. +*/ +void OSA_InterruptDisable(void); + +/*! + * @brief Enable all interrupts using PRIMASK. +*/ +void OSA_EnableIRQGlobal(void); + +/*! + * @brief Disable all interrupts using PRIMASK. +*/ +void OSA_DisableIRQGlobal(void); + +/*! + * @brief Delays execution for a number of milliseconds. + * + * @param millisec The time in milliseconds to wait. + */ +void OSA_TimeDelay(uint32_t millisec); + +/*! + * @brief This function gets current time in milliseconds. + * + * @retval current time in milliseconds + */ +uint32_t OSA_TimeGetMsec(void); + +/*! + * @brief Installs the interrupt handler. + * + * @param IRQNumber IRQ number of the interrupt. + * @param handler The interrupt handler to install. + */ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h new file mode 100644 index 0000000000000..43d2927c67f37 --- /dev/null +++ b/cpu/kw41z/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h @@ -0,0 +1,63 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_ +#define _FSL_OS_ABSTRACTION_CONFIG_H_ + +#ifndef osNumberOfSemaphores +#define osNumberOfSemaphores 5 +#endif +#ifndef osNumberOfMutexes +#define osNumberOfMutexes 5 +#endif +#ifndef osNumberOfMessageQs +#define osNumberOfMessageQs 0 +#endif +#ifndef osNumberOfMessages +#define osNumberOfMessages 10 +#endif +#ifndef osNumberOfEvents +#define osNumberOfEvents 5 +#endif + +#ifndef gMainThreadStackSize_c +#define gMainThreadStackSize_c 1024 +#endif +#ifndef gMainThreadPriority_c +#define gMainThreadPriority_c 7 +#endif + +#ifndef gTaskMultipleInstancesManagement_c +#define gTaskMultipleInstancesManagement_c 0 +#endif +#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */ diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile b/cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile new file mode 100644 index 0000000000000..ab64856aad2a3 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/Makefile @@ -0,0 +1,3 @@ +MODULE = mcux_xcvr + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c new file mode 100644 index 0000000000000..7a5c118ce0c46 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c @@ -0,0 +1,212 @@ +/*! +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" +#include "xcvr_test_fsk.h" + +/*! ********************************************************************************* +************************************************************************************* +* Private type definitions +************************************************************************************* +********************************************************************************** */ +enum { + gDftNormal_c = 0, + gDftTxNoMod_Carrier_c = 1, + gDftTxPattern_c = 2, + gDftTxRandom_c = 3, +}; + +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +void XcvrFskModTx(void); +void XcvrFskNoModTx(void); +void XcvrFskIdle(void); +void XcvrFskTxRand(void); +void XcvrFskLoadPattern(uint32_t u32Pattern); +void XcvrFskSetTxPower(uint8_t u8TxPow); +void XcvrFskSetTxChannel(uint8_t u8TxChan); +void XcvrFskRestoreTXControl(void); +uint8_t XcvrFskGetInstantRssi(void); + +/*! ********************************************************************************* +* XcvrFskModTx +***********************************************************************************/ +void XcvrFskModTx(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxPattern_c) | + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK; + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskNoModTx +***********************************************************************************/ +void XcvrFskNoModTx(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxNoMod_Carrier_c); + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskIdle +***********************************************************************************/ +void XcvrFskIdle(void) +{ + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | + XCVR_TX_DIG_CTRL_LFSR_EN_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; + XCVR_MISC->DTEST_CTRL &= ~XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskTxRand +***********************************************************************************/ +void XcvrFskTxRand(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | + XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxRandom_c) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(0) | /* length 9 */ + XCVR_TX_DIG_CTRL_LFSR_EN_MASK; + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskLoadPattern +***********************************************************************************/ +void XcvrFskLoadPattern(uint32_t u32Pattern) +{ + XCVR_TX_DIG->DFT_PATTERN = u32Pattern; +} + +/*! ********************************************************************************* +* XcvrFskGetInstantRssi +***********************************************************************************/ +uint8_t XcvrFskGetInstantRssi(void) +{ + uint8_t u8Rssi; + uint32_t t1,t2,t3; + t1 = XCVR_RX_DIG->RX_DIG_CTRL; + t2 = XCVR_RX_DIG->RSSI_CTRL_0; + t3 = XCVR_PHY->CFG1; + XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | /* 1=OSR8, 2=OSR16, 4=OSR32 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0) | /* Source Rate 0 is default */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(22) | /* Dec filt gain for SRC rate == 0 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1) ; + + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(0x5); + + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(0x3); + + uint32_t temp = XCVR_PHY->CFG1; + temp &= ~XCVR_PHY_CFG1_CTS_THRESH_MASK; + temp |= XCVR_PHY_CFG1_CTS_THRESH(0xFF); + XCVR_PHY->CFG1 = temp; + + XCVR_ForceRxWu(); + for(uint32_t i = 0; i < 10000; i++) + { + __asm("nop"); + } + u8Rssi = (uint8_t)((XCVR_RX_DIG->RSSI_CTRL_1 & + XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) >> + XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT); + XCVR_ForceRxWd(); + + XCVR_RX_DIG->RX_DIG_CTRL = t1; + XCVR_RX_DIG->RSSI_CTRL_0 = t2; + XCVR_PHY->CFG1 = t3; + return u8Rssi; +} + +/*! ********************************************************************************* +* XcvrFskSetTxPower +***********************************************************************************/ +void XcvrFskSetTxPower(uint8_t u8TxPow) +{ + return; +} + +/*! ********************************************************************************* +* XcvrFskSetTxChannel +***********************************************************************************/ +void XcvrFskSetTxChannel(uint8_t u8TxChan) +{ + return; +} + +/*! ********************************************************************************* +* XcvrFskRestoreTXControl +* After calling this function user should switch to +* previous protocol and set the protocol channel to default +***********************************************************************************/ +void XcvrFskRestoreTXControl(void) +{ + return; +} + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h new file mode 100644 index 0000000000000..a3be92c53c2e5 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h @@ -0,0 +1,157 @@ +/*! +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef __XCVR_TEST_FSK_H__ +#define __XCVR_TEST_FSK_H__ + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* +* \brief This function returns instant RSSI value and returns it as unsigned byte. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Initialization of the xcvr is necessary prior to calling this function +* +***********************************************************************************/ +extern uint8_t XcvrFskGetInstantRssi(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous modulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Initialization of the xcvr and calling XcvrFskLoadPattern are necessary +* prior to calling this function +* +***********************************************************************************/ +extern void XcvrFskModTx(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous unmodulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskNoModTx(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into idle. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskIdle(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous modulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details The modulation used is a pseudo-random pattern generated using a LFSR. +* +***********************************************************************************/ +extern void XcvrFskTxRand(void); + +/*! ********************************************************************************* +* \brief This function loads a 32 bit value into the pattern register used by XcvrFskModTx. +* +* \param[in] u32Pattern The pattern to be loaded. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskLoadPattern(uint32_t u32Pattern); + +/*! ********************************************************************************* +* \brief This function gives tx power control to xcvr and sets the power to u8TxPow. +* +* \param[in] u8TxPow Values should be between 0x00 and 0x0F. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskSetTxPower(uint8_t u8TxPow); + +/*! ********************************************************************************* +* \brief This function gives tx channel control to xcvr and sets the channel to u8TxChan. +* +* \param[in] u8TxChan Values should be between 0 and 39. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskSetTxChannel(uint8_t u8TxChan); + +/*! ********************************************************************************* +* \brief This function gives tx channel control and power to the upper layer. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Call this function only if XcvrFskSetTxChannel or XcvrFskSetTxPower were called +* previously. +* +***********************************************************************************/ +extern void XcvrFskRestoreTXControl(void); + +#endif + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.c new file mode 100644 index 0000000000000..31812fa9f773b --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "cpu.h" +#include "fsl_xcvr.h" +#include "dbg_ram_capture.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if RADIO_IS_GEN_3P0 +#define PKT_RAM_SIZE_16B_WORDS (1152) /* Number of 16bit entries in each Packet RAM bank */ +#else +#define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM bank */ +#endif /* RADIO_IS_GEN_3P0 */ +#define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0)) +#define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0)) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void dbg_ram_init(void) +{ + XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns on clocking to DMA/DBG blocks */ + XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to just XCVR */ + + /* Some external code must perform the RX warmup request. */ +} + + +dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer) +{ + dbgRamStatus_t status = DBG_RAM_SUCCESS; + uint32_t temp; + volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1; + uint8_t * output_ptr; + uint16_t i; + + /* Some external code must perform the RX warmup request after the dbg_ram_init() call */ + + if (result_buffer == NULL) + { + status = DBG_RAM_FAIL_NULL_POINTER; + } + else + { + if (buffer_sz_bytes > (544*2*2)) + { + status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT; + } + else + { + temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; + switch (dbg_page) + { + case DBG_PAGE_RXDIGIQ: + case DBG_PAGE_RAWADCIQ: + case DBG_PAGE_DCESTIQ: + XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); + + while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) + { + /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ + } + /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ + output_ptr = result_buffer; +#if !RADIO_IS_GEN_2P1 + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); + pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]); +#else + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); + pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */ +#endif /* !RADIO_IS_GEN_2P1 */ + /* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */ + for (i = 0; i < buffer_sz_bytes / 4; i++) + { + *output_ptr++ = *pkt_ram_ptr0++; + *output_ptr++ = *pkt_ram_ptr0++; + *output_ptr++ = *pkt_ram_ptr1++; + *output_ptr++ = *pkt_ram_ptr1++; + } + + break; + case DBG_PAGE_RXINPH: + case DBG_PAGE_DEMOD_HARD: + case DBG_PAGE_DEMOD_SOFT: + case DBG_PAGE_DEMOD_DATA: + case DBG_PAGE_DEMOD_CFO_PH: + XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); + while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) + { + /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ + } + /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ + output_ptr = result_buffer; +#if !RADIO_IS_GEN_2P1 + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); +#else + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); +#endif /* !RADIO_IS_GEN_2P1 */ + /* This is for non I/Q */ + for (i = 0; i < buffer_sz_bytes; i++) + { + *output_ptr = *pkt_ram_ptr0; + pkt_ram_ptr0++; + output_ptr++; + } + break; + case DBG_PAGE_IDLE: + default: + status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */ + break; + } + } + } + + XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */ + + /* Process the samples and copy to output pointer */ + + XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */ + XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */ + + return status; +} + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.h new file mode 100644 index 0000000000000..4fc56ba4b4fb0 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/dbg_ram_capture.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _DBG_RAM_CAPTURE_H_ +/* clang-format off */ +#define _DBG_RAM_CAPTURE_H_ +/* clang-format on */ + +#include + +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Page definitions */ +#define DBG_PAGE_IDLE (0x00) +#define DBG_PAGE_RXDIGIQ (0x01) +#define DBG_PAGE_RAWADCIQ (0x04) +#define DBG_PAGE_DCESTIQ (0x07) +#define DBG_PAGE_RXINPH (0x0A) +#define DBG_PAGE_DEMOD_HARD (0x0B) +#define DBG_PAGE_DEMOD_SOFT (0x0C) +#define DBG_PAGE_DEMOD_DATA (0x0D) +#define DBG_PAGE_DEMOD_CFO_PH (0x0E) + +typedef enum _dbgRamStatus +{ + DBG_RAM_SUCCESS = 0, + DBG_RAM_FAIL_SAMPLE_NUM_LIMIT = 1, + DBG_RAM_FAIL_PAGE_ERROR = 2, + DBG_RAM_FAIL_NULL_POINTER = 3, + DBG_RAM_INVALID_TRIG_SETTING = 4, + DBG_RAM_FAIL_NOT_ENOUGH_SAMPLES = 5, + DBG_RAM_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling */ +} dbgRamStatus_t; + +#if RADIO_IS_GEN_3P0 +typedef enum _dbgRamStartTriggerType +{ + NO_START_TRIG = 0, + START_ON_FSK_PREAMBLE_FOUND = 1, + START_ON_FSK_AA_MATCH = 2, + START_ON_ZBDEMOD_PREAMBLE_FOUND = 3, + START_ON_ZBDEMOD_SFD_MATCH = 4, + START_ON_AGC_DCOC_GAIN_CHG = 5, + START_ON_TSM_RX_DIG_EN = 6, + START_ON_TSM_SPARE2_EN = 7, + INVALID_START_TRIG = 8 +} dbgRamStartTriggerType; + +typedef enum _dbgRamStopTriggerType +{ + NO_STOP_TRIG = 0, + STOP_ON_FSK_PREAMBLE_FOUND = 1, + STOP_ON_FSK_AA_MATCH = 2, + STOP_ON_ZBDEMOD_PREAMBLE_FOUND = 3, + STOP_ON_ZBDEMOD_SFD_MATCH = 4, + STOP_ON_AGC_DCOC_GAIN_CHG = 5, + STOP_ON_TSM_RX_DIG_EN = 6, + STOP_ON_TSM_SPARE3_EN = 7, + STOP_ON_TSM_PLL_UNLOCK = 8, + STOP_ON_BLE_CRC_ERROR_INC = 9, + STOP_ON_CRC_FAIL_ZGBE_GENFSK = 10, + STOP_ON_GENFSK_HEADER_FAIL = 11, + INVALID_STOP_TRIG = 12 +} dbgRamStopTriggerType; +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief This function prepares for sample capture to packet RAM. + * + * \return None. + * + * \details + * This routine assumes that some other functions in the calling routine both set + * the channel and force RX warmup before calling ::dbg_ram_capture(). + ***********************************************************************************/ +void dbg_ram_init(void); + +/*! ********************************************************************************* + * \brief This function performs any state restoration at the completion of PKT RAM capture. + * + * \details + * Any clocks enabled to the packet RAM capture circuitry are disabled. + ***********************************************************************************/ +void dbg_ram_release(void); + +#if RADIO_IS_GEN_3P0 +/*! ********************************************************************************* + * \brief This function initiates the capture of transceiver data to the transceiver packet RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled). + * \param[in] dbg_stop_trigger - The trigger to stop acquisition (must be "no trigger" if a start trigger is enabled). + * + * \return Status of the request. + * + * \details + * This function starts the process of capturing data to the packet RAM. Depending upon the start and stop trigger + * settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to + * perform a blocking wait for completion or allow polling for completion of the capture. + * After any capture has completed, a separate routine must be called to postprocess the capture and copy all + * data out of the packet RAM into a normal RAM buffer. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_start_capture(uint8_t dbg_page, dbgRamStartTriggerType start_trig, dbgRamStopTriggerType stop_trig); + +/*! ********************************************************************************* + * \brief This function performs a blocking wait for completion of the capture of transceiver data to the transceiver packet RAM. + * + * \return Status of the request, DBG_RAM_SUCCESS if capture is complete. + * + * \details + * This function performs a wait loop for capture completion and may take an indeterminate amount of time for + * some capture trigger types. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_wait_for_complete(void); /* Blocking wait for capture completion, no matter what trigger type */ + +/*! ********************************************************************************* + * \brief This function polls the state of the capture of transceiver data to the transceiver packet RAM. + * + * \return Status of the request, DBG_RAM_SUCCESS if capture is complete, DBG_RAM_CAPTURE_NOT_COMPLETE if not complete. + * + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_poll_capture_status(void); /* Non-blocking completion check, just reads the current status of the capure */ + +/*! ********************************************************************************* + * \brief This function processes the captured data into a usable order and copies from packet RAM to normal RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) + * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. + * + * \return None. + * + * \details + * Data is copied from packet RAM in bytes to ensure no access problems. Data is unpacked from packet RAM + * (either sequentially captured or simultaneously captured) into a linear RAM buffer in system RAM. + * If a start trigger is enabled then the first buffer_sz_bytes that are captured are copied out. + * If a stop trigger is enabled then the last buffer_sz_bytes that are captured are copied out. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_postproc_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); /* postprocess a capture to unpack data */ + +#else +/*! ********************************************************************************* + * \brief This function captures transceiver data to the transceiver packet RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) + * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. + * + * \return None. + * + * \details + * The capture to packet RAM always captures a full PKT_RAM worth of samples. The samples will be + * copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have + * been copied. Data will be copied + * NOTE: This routine has a slight hazard of getting stuck waiting for debug RAM to fill up when RX has + * not been enabled or RX ends before the RAM fills up (such as when capturing packet data ). It is + * intended to be used with manually triggered RX where RX data will continue as long as needed. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); +#endif /* RADIO_IS_GEN_3P0 */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _DBG_RAM_CAPTURE_H_ */ + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c new file mode 100644 index 0000000000000..c0f86fc9b67d9 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c @@ -0,0 +1,27 @@ +#include "irq.h" + +#include "fsl_os_abstraction.h" + +static unsigned int irq_mask; + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ + irq_restore(irq_mask); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ + irq_mask = irq_disable(); +} diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c new file mode 100644 index 0000000000000..1103133c4a5a7 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -0,0 +1,2121 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "EmbeddedTypes.h" +#include "cpu.h" +#include "fsl_xcvr.h" +#include "fsl_xcvr_trim.h" +#include "ifr_radio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define channelMapTableSize (128U) +#define gPllDenom_c 0x02000000U /* Denominator is a constant value */ +#define ABS(x) ((x) > 0 ? (x) : -(x)) + +#ifndef TRUE +#define TRUE (true) +#endif + +#ifndef FALSE +#define FALSE (false) +#endif +#define RF_OSCILLATOR_STAYS_ON (false) /* Control whether RF_OSC can be left on all the time. */ +#define RF_OSCILLATOR_READY ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U) + +#ifndef EXTERNAL_CLOCK_GEN +#define EXTERNAL_CLOCK_GEN 0 +#endif + +#define ANT_A 1 +#define ANT_B 0 + +#ifndef XCVR_COEX_RF_ACTIVE_PIN +#define XCVR_COEX_RF_ACTIVE_PIN ANT_B +#endif /* XCVR_COEX_RF_ACTIVE_PIN */ + +typedef struct xcvr_pllChannel_tag +{ + unsigned int integer; + unsigned int numerator; +} xcvr_pllChannel_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address); +void rf_osc_startup(void); +void rf_osc_shutdown(void); +extern double trunc (double); +extern double round (double); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static panic_fptr s_PanicFunctionPtr = NULL; +const xcvr_pllChannel_t mapTable [channelMapTableSize] = +{ + {0x00000025, 0x07C00000}, /* 0 */ + {0x00000025, 0x07C80000}, /* 1 */ + {0x00000025, 0x07D00000}, /* 2 */ + {0x00000025, 0x07D80000}, /* 3 */ + {0x00000025, 0x07E00000}, /* 4 */ + {0x00000025, 0x07E80000}, /* 5 */ + {0x00000025, 0x07F00000}, /* 6 */ + {0x00000025, 0x07F80000}, /* 7 */ + {0x00000025, 0x00000000}, /* 8 */ + {0x00000025, 0x00080000}, /* 9 */ + {0x00000025, 0x00100000}, /* 10 */ + {0x00000025, 0x00180000}, /* 11 */ + {0x00000025, 0x00200000}, /* 12 */ + {0x00000025, 0x00280000}, /* 13 */ + {0x00000025, 0x00300000}, /* 14 */ + {0x00000025, 0x00380000}, /* 15 */ + {0x00000025, 0x00400000}, /* 16 */ + {0x00000025, 0x00480000}, /* 17 */ + {0x00000025, 0x00500000}, /* 18 */ + {0x00000025, 0x00580000}, /* 19 */ + {0x00000025, 0x00600000}, /* 20 */ + {0x00000025, 0x00680000}, /* 21 */ + {0x00000025, 0x00700000}, /* 22 */ + {0x00000025, 0x00780000}, /* 23 */ + {0x00000025, 0x00800000}, /* 24 */ + {0x00000025, 0x00880000}, /* 25 */ + {0x00000025, 0x00900000}, /* 26 */ + {0x00000025, 0x00980000}, /* 27 */ + {0x00000025, 0x00A00000}, /* 28 */ + {0x00000025, 0x00A80000}, /* 29 */ + {0x00000025, 0x00B00000}, /* 30 */ + {0x00000025, 0x00B80000}, /* 31 */ + {0x00000025, 0x00C00000}, /* 32 */ + {0x00000025, 0x00C80000}, /* 33 */ + {0x00000025, 0x00D00000}, /* 34 */ + {0x00000025, 0x00D80000}, /* 35 */ + {0x00000025, 0x00E00000}, /* 36 */ + {0x00000025, 0x00E80000}, /* 37 */ + {0x00000025, 0x00F00000}, /* 38 */ + {0x00000025, 0x00F80000}, /* 39 */ + {0x00000025, 0x01000000}, /* 40 */ + {0x00000026, 0x07080000}, /* 41 */ + {0x00000026, 0x07100000}, /* 42 */ + {0x00000026, 0x07180000}, /* 43 */ + {0x00000026, 0x07200000}, /* 44 */ + {0x00000026, 0x07280000}, /* 45 */ + {0x00000026, 0x07300000}, /* 46 */ + {0x00000026, 0x07380000}, /* 47 */ + {0x00000026, 0x07400000}, /* 48 */ + {0x00000026, 0x07480000}, /* 49 */ + {0x00000026, 0x07500000}, /* 50 */ + {0x00000026, 0x07580000}, /* 51 */ + {0x00000026, 0x07600000}, /* 52 */ + {0x00000026, 0x07680000}, /* 53 */ + {0x00000026, 0x07700000}, /* 54 */ + {0x00000026, 0x07780000}, /* 55 */ + {0x00000026, 0x07800000}, /* 56 */ + {0x00000026, 0x07880000}, /* 57 */ + {0x00000026, 0x07900000}, /* 58 */ + {0x00000026, 0x07980000}, /* 59 */ + {0x00000026, 0x07A00000}, /* 60 */ + {0x00000026, 0x07A80000}, /* 61 */ + {0x00000026, 0x07B00000}, /* 62 */ + {0x00000026, 0x07B80000}, /* 63 */ + {0x00000026, 0x07C00000}, /* 64 */ + {0x00000026, 0x07C80000}, /* 65 */ + {0x00000026, 0x07D00000}, /* 66 */ + {0x00000026, 0x07D80000}, /* 67 */ + {0x00000026, 0x07E00000}, /* 68 */ + {0x00000026, 0x07E80000}, /* 69 */ + {0x00000026, 0x07F00000}, /* 70 */ + {0x00000026, 0x07F80000}, /* 71 */ + {0x00000026, 0x00000000}, /* 72 */ + {0x00000026, 0x00080000}, /* 73 */ + {0x00000026, 0x00100000}, /* 74 */ + {0x00000026, 0x00180000}, /* 75 */ + {0x00000026, 0x00200000}, /* 76 */ + {0x00000026, 0x00280000}, /* 77 */ + {0x00000026, 0x00300000}, /* 78 */ + {0x00000026, 0x00380000}, /* 79 */ + {0x00000026, 0x00400000}, /* 80 */ + {0x00000026, 0x00480000}, /* 81 */ + {0x00000026, 0x00500000}, /* 82 */ + {0x00000026, 0x00580000}, /* 83 */ + {0x00000026, 0x00600000}, /* 84 */ + {0x00000026, 0x00680000}, /* 85 */ + {0x00000026, 0x00700000}, /* 86 */ + {0x00000026, 0x00780000}, /* 87 */ + {0x00000026, 0x00800000}, /* 88 */ + {0x00000026, 0x00880000}, /* 89 */ + {0x00000026, 0x00900000}, /* 90 */ + {0x00000026, 0x00980000}, /* 91 */ + {0x00000026, 0x00A00000}, /* 92 */ + {0x00000026, 0x00A80000}, /* 93 */ + {0x00000026, 0x00B00000}, /* 94 */ + {0x00000026, 0x00B80000}, /* 95 */ + {0x00000026, 0x00C00000}, /* 96 */ + {0x00000026, 0x00C80000}, /* 97 */ + {0x00000026, 0x00D00000}, /* 98 */ + {0x00000026, 0x00D80000}, /* 99 */ + {0x00000026, 0x00E00000}, /* 100 */ + {0x00000026, 0x00E80000}, /* 101 */ + {0x00000026, 0x00F00000}, /* 102 */ + {0x00000026, 0x00F80000}, /* 103 */ + {0x00000026, 0x01000000}, /* 104 */ + {0x00000027, 0x07080000}, /* 105 */ + {0x00000027, 0x07100000}, /* 106 */ + {0x00000027, 0x07180000}, /* 107 */ + {0x00000027, 0x07200000}, /* 108 */ + {0x00000027, 0x07280000}, /* 109 */ + {0x00000027, 0x07300000}, /* 110 */ + {0x00000027, 0x07380000}, /* 111 */ + {0x00000027, 0x07400000}, /* 112 */ + {0x00000027, 0x07480000}, /* 113 */ + {0x00000027, 0x07500000}, /* 114 */ + {0x00000027, 0x07580000}, /* 115 */ + {0x00000027, 0x07600000}, /* 116 */ + {0x00000027, 0x07680000}, /* 117 */ + {0x00000027, 0x07700000}, /* 118 */ + {0x00000027, 0x07780000}, /* 119 */ + {0x00000027, 0x07800000}, /* 120 */ + {0x00000027, 0x07880000}, /* 121 */ + {0x00000027, 0x07900000}, /* 122 */ + {0x00000027, 0x07980000}, /* 123 */ + {0x00000027, 0x07A00000}, /* 124 */ + {0x00000027, 0x07A80000}, /* 125 */ + {0x00000027, 0x07B00000}, /* 126 */ + {0x00000027, 0x07B80000} /* 127 */ +}; + +/* Registers for timing of TX & RX */ +#if RADIO_IS_GEN_3P0 +uint16_t tx_rx_on_delay = TX_RX_ON_DELinit; +uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init; +#else +#if RF_OSC_26MHZ == 1 +uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ; +#else +uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL; +#endif /* RF_OSC_26MHZ == 1 */ +uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL; +#endif /* RADIO_IS_GEN_3P0 */ + +/* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */ +#if RADIO_IS_GEN_3P0 +const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] = +{ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config, + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config, + &xcvr_MSK_2mbps_config, +}; +#endif /* RADIO_IS_GEN_3P0 */ + +const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ + &xcvr_ANT_1mbps_config, +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config, + &xcvr_MSK_1mbps_config, +}; + +const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, /* Invalid option */ +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */ + &xcvr_ANT_1mbps_config, /* Invalid option */ +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config, + &xcvr_MSK_500kbps_config, +}; +const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, /* Invalid option */ +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ + &xcvr_ANT_1mbps_config, /* Invalid option */ +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config, + &xcvr_MSK_250kbps_config, +}; + +static xcvr_currConfig_t current_xcvr_config; + +void rf_osc_startup(void) +{ + if (!RF_OSCILLATOR_READY) + { + RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; + } + while (!RF_OSCILLATOR_READY) + { + /* Wait for RF_OSC_READY to be asserted before continuing */ + } +} + +void rf_osc_shutdown(void) +{ + if (!RF_OSCILLATOR_STAYS_ON) + { + RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ +xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) +{ + const xcvr_mode_datarate_config_t * mode_datarate_config; + const xcvr_datarate_config_t * datarate_config ; + const xcvr_mode_config_t * radio_mode_cfg; + const xcvr_common_config_t * radio_common_config; + + xcvrStatus_t status; + + IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = + { + {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/ + {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/ + }; + const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T); + +#ifndef SIMULATION + +#if (EXTERNAL_CLOCK_GEN) + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */ +#endif /* EXTERNAL_CLOCK_GEN */ + +#if RADIO_IS_GEN_2P0 + RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */ + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ +#endif /* RADIO_IS_GEN_2P0 */ + + /* Check that this is the proper radio version */ + { + uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT); + + if ( +#if RADIO_IS_GEN_3P0 + (radio_id != 0x5) /* KW3 Gen3 */ +#elif RADIO_IS_GEN_2P1 + (radio_id != 0x5) /* KW35 Gen2.1 */ +#else + (radio_id != 0x3) && /* KW41/31/21 v1 */ + (radio_id != 0xB) /* KW41/31/21 v1.1 */ +#endif /* RADIO_IS_GEN_3P0 */ + ) + { + XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init); + } + } + +#if RADIO_IS_GEN_3P0 + /* Assert Radio Run Request and wait for ack from SPM. */ + RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK; + while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0) + { + } + RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; + rf_osc_startup(); /* Start RF_OSC to allow radio registers access */ +#else + SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; + + /* Load IFR trim values */ + handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES); +#endif /* RADIO_IS_GEN_3P0 */ + +#endif /* ifndef SIMULATION */ + + /* Perform the desired XCVR initialization and configuration */ + status = XCVR_GetDefaultConfig(radio_mode, data_rate, + (const xcvr_common_config_t **)&radio_common_config, + (const xcvr_mode_config_t **)&radio_mode_cfg, + (const xcvr_mode_datarate_config_t **)&mode_datarate_config, + (const xcvr_datarate_config_t **)&datarate_config); + + if (status == gXcvrSuccess_c) + { + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, + (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT); + current_xcvr_config.radio_mode = radio_mode; + current_xcvr_config.data_rate = data_rate; + } + + return status; +} + +void XCVR_Deinit(void) +{ +#if RADIO_IS_GEN_3P0 + rf_osc_shutdown(); + RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */ + RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */ +#else + +#endif /* RADIO_IS_GEN_3P0 */ +} + +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, + const xcvr_datarate_config_t ** datarate_config) +{ + xcvrStatus_t status = gXcvrSuccess_c; + /* Common configuration pointer */ + *com_config = (const xcvr_common_config_t *)&xcvr_common_config; + + /* Mode dependent configuration pointer */ + switch (radio_mode) + { +#if !RADIO_IS_GEN_2P1 + case ZIGBEE_MODE: + *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */ + break; + case ANT_MODE: + *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */ + break; +#endif /* !RADIO_IS_GEN_2P1 */ + case BLE_MODE: + *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */ + break; + case GFSK_BT_0p5_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */ + break; + case GFSK_BT_0p5_h_0p32: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */ + break; + case GFSK_BT_0p5_h_0p7: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */ + break; + case GFSK_BT_0p5_h_1p0: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */ + break; + case GFSK_BT_0p3_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */ + break; + case GFSK_BT_0p7_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */ + break; + case MSK: + *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */ + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + + /* Data rate dependent and modeXdatarate dependent configuration pointers */ + if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ + { + switch (data_rate) + { +#if RADIO_IS_GEN_3P0 + case DR_2MBPS: + if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE)) + { + status = gXcvrInvalidParameters_c; + } + else + { + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode]; + } + break; +#endif /* RADIO_IS_GEN_3P0 */ + case DR_1MBPS: + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode]; + break; + case DR_500KBPS: + if (radio_mode == ZIGBEE_MODE) + { + /* See fsl_xcvr_zgbe_config.c for settings */ +#if !RADIO_IS_GEN_2P1 + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */ +#endif /* !RADIO_IS_GEN_2P1 */ + } + else + { + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */ + } + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode]; + break; + case DR_250KBPS: + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode]; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + return status; +} + +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, + XCVR_INIT_MODE_CHG_T first_init) +{ + xcvrStatus_t config_status = gXcvrSuccess_c; + uint32_t temp; + + /* Turn on the module clocks before doing anything */ +#if RADIO_IS_GEN_3P0 + RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */ +#else + SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits; +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_ANA configs */ + /*******************************************************************************/ + + /* Configure PLL Loop Filter */ + if (first_init) + { + XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask; + XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init; + } + + /* Configure VCO KVM */ + XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask; + XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init; + + /* Configure analog filter bandwidth */ + XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask; + XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init; + XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask; + XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init; + +#if RADIO_IS_GEN_2P0 + if (first_init) + { + temp = XCVR_ANA->TX_DAC_PA; + temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK; + temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4); + XCVR_ANA->TX_DAC_PA = temp; + + temp = XCVR_ANA->BB_LDO_2; + temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0); + XCVR_ANA->BB_LDO_2 = temp; + + temp = XCVR_ANA->RX_LNA; + temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK; + temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1); + XCVR_ANA->RX_LNA = temp; + + temp = XCVR_ANA->BB_LDO_1; + temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1); + XCVR_ANA->BB_LDO_1 = temp; + } +#endif /* RADIO_IS_GEN_2P0 */ + + /*******************************************************************************/ + /* XCVR_MISC configs */ + /*******************************************************************************/ + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK); + temp |= mode_config->xcvr_ctrl.init; + +#if RF_OSC_26MHZ == 1 + { + temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1); + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_MISC->XCVR_CTRL = temp; + +#if RADIO_IS_GEN_2P1 + XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK; +#endif /* RADIO_IS_GEN_2P1 */ + + /*******************************************************************************/ + /* XCVR_PHY configs */ + /*******************************************************************************/ +#if RADIO_IS_GEN_3P0 + XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0; + XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1; + XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg; + XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate; + XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl; +#else + XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init; + XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init; + XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init; + XCVR_PHY->CFG1 = mode_config->phy_cfg1_init; + XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init; + XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */ +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_PLL_DIG configs */ + /*******************************************************************************/ + if (first_init) + { + XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump; + XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl; + XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map; + XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect; + XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl; +#if !RADIO_IS_GEN_2P1 + XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl; +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res; + XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl; + XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1; + XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match; + XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl; + } + + /*******************************************************************************/ + /* XCVR_RX_DIG configs */ + /*******************************************************************************/ + + /* Configure RF Aux PLL for proper operation based on external clock frequency */ + if (first_init) + { + temp = XCVR_ANA->RX_AUXPLL; + temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK; +#if RF_OSC_26MHZ == 1 + { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4); + } +#else + { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7); + } +#endif /* RF_OSC_26MHZ == 1 */ + XCVR_ANA->RX_AUXPLL = temp; + } + + /* Configure RX_DIG_CTRL */ +#if RF_OSC_26MHZ == 1 + { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_26mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */ + } +#else + { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + 0; /* Always disable the sample rate converter for 32MHz */ + } +#endif /* RF_OSC_26MHZ == 1 */ + + temp |= com_config->rx_dig_ctrl_init; /* Common portion of RX_DIG_CTRL init */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + /* DCOC_CAL_IIR */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz; + } +#else + { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* DC_RESID_CTRL */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz; + } +#else + { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* DCOC_CTRL_0 & _1 */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz; +#endif /* RADIO_IS_GEN_3P0 */ + + } +#else + { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz; +#endif /* RADIO_IS_GEN_3P0 */ + } +#endif /* RF_OSC_26MHZ == 1 */ + if (first_init) + { + /* DCOC_CAL_GAIN */ + XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init; + + /* DCOC_CAL_RCP */ + XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init; + XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0; + XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4; + XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8; + + /* LNA_GAIN_LIN_VAL */ + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init; + + /* BBA_RES_TUNE_LIN_VAL */ + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init; + + /* BBA_STEP */ + XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init; + + /* DCOC_TZA_STEP */ + XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init; + XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init; + XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init; + XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init; + XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init; + XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init; + XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init; + XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init; + XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init; + XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init; + +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + /* DCOC_CAL_FAIL and DCOC_CAL_PASS */ + XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init; + XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init; +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + } + + /* AGC_CTRL_0 .. _3 */ + XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init; + +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz; + } +#else + { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + if (first_init) + { + XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init; + + /* AGC_GAIN_TBL_** */ + XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init; + XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init; + XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init; + XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init; + XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init; + XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init; + XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init; + + /* RSSI_CTRL_0 */ + XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init; + +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init; +#endif /* RADIO_IS_GEN_3P0 */ + + /* CCA_ED_LQI_0 and _1 */ + XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init; + XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init; + } + + /* Channel filter coefficients */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11; + } +#else + { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11; + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0; + XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1; + + /*******************************************************************************/ + /* XCVR_TSM configs */ + /*******************************************************************************/ + XCVR_TSM->CTRL = com_config->tsm_ctrl; + +#if RADIO_IS_GEN_2P0 + if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE)) + { + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK; + } +#endif /* RADIO_IS_GEN_2P0 */ + + if (first_init) + { +#if !RADIO_IS_GEN_2P1 + XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */ +#endif /* !RADIO_IS_GEN_2P1 */ + + XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init; + /* TSM registers and timings - dependent upon clock frequency */ +#if RF_OSC_26MHZ == 1 + { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz; + } +#else + { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* TSM timings independent of clock frequency */ + XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init; + XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init; + XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init; + XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init; + XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init; + XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init; + XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init; + XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init; + XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init; + XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init; + XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init; + XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init; + XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init; + XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init; + XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init; + XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init; + XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init; + XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init; + XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init; + XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; + XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init; + XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init; + XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init; + XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init; + XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init; + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init; + XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init; + XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init; + XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init; + XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init; + XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init; + +#if RF_OSC_26MHZ == 1 + { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ); + } +#else + { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD); + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init; + XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init; + +#if RADIO_IS_GEN_3P0 + XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init; + XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init; + + /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */ +#if (PA_RAMP_TIME == 4) + XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */ + XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */ + XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */ + XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */ + XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */ + XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */ + XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */ + XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */ + XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */ + XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */ + XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */ + XCVR_TSM->TIMING20 += B1(2); /* (sy_pd_en) */ + XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */ + XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */ + XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ + XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */ + XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */ + XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */ + XCVR_TSM->TIMING58 += B1(2) /* (tx_hpm_dac_en) */ + temp = XCVR_TSM->TIMING14; + temp &= 0xFFFF0000; + temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */ + XCVR_TSM->TIMING14 = temp; +#endif /* (PA_RAMP_TIME == 4) */ +#endif /* RADIO_IS_GEN_3P0 */ + } + +#if RADIO_IS_GEN_3P0 + if (mode_config->radio_mode == ZIGBEE_MODE) + { + temp = XCVR_TSM->TIMING35; + temp &= ~(B0(0xFF)); + if (DATA_PADDING_EN == 1) + { + temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */ + } + else + { + temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */ + } + XCVR_TSM->TIMING35 = temp; + } +#else + + if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS))) + { + /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */ + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */ + } + else + { + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */ + } +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_TX_DIG configs */ + /*******************************************************************************/ +#if RF_OSC_26MHZ == 1 + { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz; + } +#else + { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + if (first_init) + { + XCVR_TX_DIG->CTRL = com_config->tx_ctrl; + XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding; + XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern; + +#if !RADIO_IS_GEN_2P1 + XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1; + XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2; +#endif /* !RADIO_IS_GEN_2P1 */ + } + + XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl; + +#ifndef SIMULATION +#if (TRIM_BBA_DCOC_DAC_AT_INIT) + if (first_init) + { + uint32_t end_of_rx_wu = 0; + XCVR_ForceRxWu(); + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + +// if (!rx_bba_dcoc_dac_trim_shortIQ()) + if (!rx_bba_dcoc_dac_trim_DCest()) + { + config_status = gXcvrTrimFailure_c; + } + + XCVR_ForceRxWd(); + DCOC_DAC_INIT_Cal(1); + } +#endif /* TRIM_BBA_DCOC_DAC_AT_INIT */ +#endif /* ifndef SIMULATION */ + return config_status; +} + +void XCVR_Reset(void) +{ +#if RADIO_IS_GEN_3P0 +#else + RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */ + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */ + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */ +#endif /* RADIO_IS_GEN_3P0 */ +} + +xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */ +{ + xcvrStatus_t status; + const xcvr_mode_datarate_config_t * mode_datarate_config; + const xcvr_datarate_config_t * datarate_config ; + const xcvr_mode_config_t * radio_mode_cfg; + const xcvr_common_config_t * radio_common_config; + + status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config ); + + if (status == gXcvrSuccess_c) + { + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, + (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE); + current_xcvr_config.radio_mode = new_radio_mode; + current_xcvr_config.data_rate = new_data_rate; + } + + return status; +} + +void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable ) +{ + if (IIRnbEnable) + { + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; + } + else + { + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; + } +} + +xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) +{ + double integer_used_in_Hz, + integer_used_in_LSB, + numerator_fraction, + numerator_in_Hz, + numerator_in_LSB, + numerator_unrounded, + real_int_and_fraction, + real_fraction, + requested_freq_in_LSB, + sdm_lsb; + uint32_t temp; + static uint32_t integer_truncated, + integer_to_use; + static int32_t numerator_rounded; + + /* Configure for Coarse Tune */ + uint32_t coarse_tune_target = freq / 1000000; + + temp = XCVR_PLL_DIG->CTUNE_CTRL; + temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK; + temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target); + XCVR_PLL_DIG->CTUNE_CTRL = temp; + + /* Calculate the Low Port values */ + sdm_lsb = refOsc / 131072.0; + + real_int_and_fraction = freq / (refOsc * 2.0); + + integer_truncated = (uint32_t) trunc(real_int_and_fraction); + + real_fraction = real_int_and_fraction - integer_truncated; + + if (real_fraction > 0.5) + { + integer_to_use = integer_truncated + 1; + } + else + { + integer_to_use = integer_truncated; + } + + numerator_fraction = real_int_and_fraction - integer_to_use; + + integer_used_in_Hz = integer_to_use * refOsc * 2; + integer_used_in_LSB = integer_used_in_Hz / sdm_lsb; + + numerator_in_Hz = numerator_fraction * refOsc * 2; + numerator_in_LSB = numerator_in_Hz / sdm_lsb; + + requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB; + + numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256; + + numerator_rounded = (int32_t)round(numerator_unrounded); + + /* Write the Low Port Integer and Numerator */ + temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; + temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; + temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK); + XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; + + XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded; + + return gXcvrSuccess_c; +} + +void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */ +{ + s_PanicFunctionPtr = fptr; +} + +void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address) +{ + if ( s_PanicFunctionPtr != NULL) + { + s_PanicFunctionPtr(panic_id, panic_address, 0, 0); + } + else + { + uint8_t dummy; + + while(1) + { + dummy = dummy; + } + } +} + +healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */ +{ + return (healthStatus_t)NO_ERRORS; +} + +void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control) +{ + +} + +/* Helper function to map radio mode to LL usage */ +link_layer_t map_mode_to_ll(radio_mode_t mode) +{ + link_layer_t llret; + switch (mode) + { + case BLE_MODE: + llret = BLE_LL; + break; + case ZIGBEE_MODE: + llret = ZIGBEE_LL; + break; + case ANT_MODE: + llret = ANT_LL; + break; + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + case MSK: + llret = GENFSK_LL; + break; + default: + llret = UNASSIGNED_LL; + break; + } + return llret; +} + +#if RADIO_IS_GEN_3P0 +void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address) +{ + XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address; +} + +uint32_t XCVR_GetBSM_NTW_Address(void) +{ + return XCVR_PHY->NTW_ADR_BSM; +} +#endif /* RADIO_IS_GEN_3P0 */ + +/* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */ +xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping) +{ + link_layer_t int0 = map_mode_to_ll(irq0_mapping); + link_layer_t int1 = map_mode_to_ll(irq1_mapping); + xcvrStatus_t statusret; + /* Make sure the two LL's requested aren't the same */ + if (int0 == int1) + { + statusret = gXcvrInvalidParameters_c; + } + else + { + uint32_t temp; + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK); + temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1)); + XCVR_MISC->XCVR_CTRL = temp; + statusret = gXcvrSuccess_c; + } + return statusret; +} + +/* Get current state of IRQ mapping for either radio INT0 or INT1 */ +link_layer_t XCVR_GetIRQMapping(uint8_t int_num) +{ + if (int_num == 0) + { + return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT); + } + else + { + return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT); + } +} + +/* Get current state of radio mode and data rate */ +xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config) +{ + xcvrStatus_t status = gXcvrInvalidParameters_c; + if (curr_config != NULL) + { + curr_config->radio_mode = current_xcvr_config.radio_mode; + curr_config->data_rate = current_xcvr_config.data_rate; + status = gXcvrSuccess_c; + } + return status; +} + +/* Customer level trim functions */ +xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim) +{ + xcvrStatus_t status = gXcvrInvalidParameters_c; + + if ((xtalTrim & 0x80) == 0) + { + uint32_t temp; + temp = RSIM->ANA_TRIM; + temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK; + RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim); + status = gXcvrSuccess_c; + } + return status; +} + +uint8_t XCVR_GetXtalTrim(void) +{ + uint8_t temp_xtal; + temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT); + return temp_xtal; +} + +/* RSSI adjustment */ +xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj) +{ + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj); + return gXcvrSuccess_c; +} + +int8_t XCVR_GetRssiAdjustment(void) +{ + int8_t adj; + adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT; + return adj; +} + +/* Radio debug functions */ +xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) +{ + uint32_t temp; + + if (channel == 0xFF) + { + /* Clear all of the overrides and restore to LL channel control */ + temp = XCVR_PLL_DIG->CHAN_MAP; + temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ +#if RADIO_IS_GEN_3P0 + | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK +#endif /* RADIO_IS_GEN_3P0 */ + ); + + XCVR_PLL_DIG->CHAN_MAP = temp; + + /* Stop using the manual frequency setting */ + XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; + + return gXcvrSuccess_c; + } + + if (channel >= 128) + { + return gXcvrInvalidParameters_c; + } + + if (useMappedChannel) + { + temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */ + + switch (temp) + { +#if !RADIO_IS_GEN_2P1 + case 0x3: /* ANT protocol */ + ANT->CHANNEL_NUM = channel; + break; +#endif /* !RADIO_IS_GEN_2P1 */ + case 0x8: /* GENFSK protocol */ + case 0x9: /* MSK protocol */ + GENFSK->CHANNEL_NUM = channel; + break; + default: /* All other protocols */ + temp = XCVR_PLL_DIG->CHAN_MAP; + temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK +#if RADIO_IS_GEN_3P0 + | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK +#endif /* RADIO_IS_GEN_3P0 */ + ); + temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + ); + XCVR_PLL_DIG->CHAN_MAP = temp; + break; + } + } + else + { + XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + ); + + XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c); + XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator); + + temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; + temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; + temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer); + XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; + + /* Stop using the LL channel map and use the manual frequency setting */ + XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; + } + + return gXcvrSuccess_c; +} + +uint32_t XCVR_GetFreq ( void ) +{ + uint32_t pll_int; + uint32_t pll_num_unsigned; + int32_t pll_num; + uint32_t pll_denom; + float freq_float; + + if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */ + { + pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >> + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT; + + pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2; + pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3; + } + else + { + /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */ + pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >> + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT; + + pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1; + pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2; + } + + uint32_t freq = 0; + +#if RF_OSC_26MHZ == 1 + uint32_t ref_clk = 26U; +#else + uint32_t ref_clk = 32U; +#endif /* RF_OSC_26MHZ == 1 */ + + /* Check if sign bit is asserted */ + if (pll_num_unsigned & 0x04000000U) + { + /* Sign extend the numerator */ + pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; + + /* Calculate the frequency in MHz */ + freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); + } + else + { + /* Calculate the frequency in MHz */ + pll_num = pll_num_unsigned; + freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); + } + + freq = (uint32_t)freq_float; + + return freq; +} + +void XCVR_ForceRxWu(void) +{ + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK; +} + +void XCVR_ForceRxWd(void) +{ + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK; +} + +void XCVR_ForceTxWu(void) +{ + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +void XCVR_ForceTxWd(void) +{ + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol) +{ + uint32_t temp; + if ((protocol != 6) && (protocol != 7)) + { + return gXcvrInvalidParameters_c; /* Failure */ + } + + if ((rf_channel_freq < 2360) || (rf_channel_freq >2487)) + { + return gXcvrInvalidParameters_c; /* failure */ + } + + /* Set the DFT Mode */ + temp = XCVR_TX_DIG->CTRL; + temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK; + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1); + XCVR_TX_DIG->CTRL = temp; + + /* Choose Protocol 6 or 7 if using the Channel Number register */ + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK; + temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol); + XCVR_MISC->XCVR_CTRL = temp; + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(rf_channel_freq-2360,1); + + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + + return gXcvrSuccess_c; /* Success */ +} + +xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern) +{ + uint32_t temp; + uint8_t dft_mode = 0; + uint8_t dft_clk_sel = 0; + xcvrStatus_t status = gXcvrSuccess_c; + + XCVR_ChangeMode(radio_mode, data_rate); + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(channel_num, 1); + + switch (radio_mode) + { + case ZIGBEE_MODE: + dft_mode = 6; /* OQPSK configuration */ + break; + case ANT_MODE: + case BLE_MODE: + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + dft_mode = 2; /* GFSK configuration */ + break; + case MSK: + dft_mode = 4; /* MSK configuration */ + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + + if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ + { + switch (data_rate) + { + case DR_1MBPS: + dft_clk_sel = 4; + break; + case DR_500KBPS: + dft_clk_sel = 3; + break; + case DR_250KBPS: + dft_clk_sel = 2; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + temp = XCVR_TX_DIG->CTRL; + temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK); + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(1) | + XCVR_TX_DIG_CTRL_LFSR_EN(0); + XCVR_TX_DIG->CTRL = temp; + + XCVR_TX_DIG->DFT_PATTERN = tx_pattern; + + if (status == gXcvrSuccess_c) + { + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + } + + return status; +} + +xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length) +{ + uint32_t temp; + uint8_t dft_mode = 0; + uint8_t dft_clk_sel = 0; + xcvrStatus_t status = gXcvrSuccess_c; + uint8_t bitrate_setting = 0xFF; + + if (lfsr_length > 5) + { + return gXcvrInvalidParameters_c; + } + + XCVR_ChangeMode(radio_mode, data_rate); + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(channel_num, 1); + + switch (radio_mode) + { + case ZIGBEE_MODE: + dft_mode = 7; /* OQPSK configuration */ + break; + case ANT_MODE: + case BLE_MODE: + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + dft_mode = 3; /* GFSK configuration */ + bitrate_setting = data_rate; + break; + case MSK: + dft_mode = 5; /* MSK configuration */ + break; + + default: + status = gXcvrInvalidParameters_c; + break; + } + + if (status == gXcvrSuccess_c) + { + switch (data_rate) + { + case DR_1MBPS: + dft_clk_sel = 4; + break; + case DR_500KBPS: + dft_clk_sel = 3; + break; + case DR_250KBPS: + dft_clk_sel = 2; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + if (bitrate_setting < 4) + { + GENFSK->BITRATE = bitrate_setting; + } + + temp = XCVR_TX_DIG->CTRL; + temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | + XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | + XCVR_TX_DIG_CTRL_LFSR_EN_MASK); + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(0) | + XCVR_TX_DIG_CTRL_LFSR_EN(1); + XCVR_TX_DIG->CTRL = temp; + + if (status == gXcvrSuccess_c) + { + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + } + + return status; +} + +void XCVR_DftTxOff(void) +{ + XCVR_ForceTxWd(); + XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */ + /* Clear the RF Channel over-ride */ + XCVR_OverrideChannel(0xFF,1); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */ + XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */ + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */ + XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */ +} + +xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power) +{ + if (pa_power > 0x3F) + { + return gXcvrInvalidParameters_c; /* Failure */ + } + + if (pa_power != 1) + { + pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */ + } + + XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */ + XCVR_TSM->PA_POWER = pa_power; + + return gXcvrSuccess_c; /* Success */ +} + +xcvrStatus_t XCVR_CoexistenceInit(void) +{ +#if gMWS_UseCoexistence_d + uint32_t temp = 0x00U; + uint32_t end_of_tx_wu = 0x00U; + uint32_t end_of_rx_wu = 0x00U; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + uint32_t tsm_timing47 = 0x00U; +#else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */ + uint32_t tsm_timing48 = 0x00U; +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + uint32_t tsm_timing50 = 0x00U; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en) + uint32_t tsm_timing48 = 0x00U; + // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en) + uint32_t tsm_timing47 = 0x00U; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + uint16_t tsm_timing43_rx = 0x00; + uint16_t tsm_timing43_tx = 0x00; + + /* Select GPIO mode for FAD pins */ + temp = XCVR_MISC->FAD_CTRL; + temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK); + XCVR_MISC->FAD_CTRL = temp; + + /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ + end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + +/***************** + * TX SEQUENCE * + *****************/ + + if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_tx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Save the TX RF_ACTIVE start time. */ + tsm_timing43_tx = end_of_tx_wu - temp; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#else + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + +/***************** + * RX SEQUENCE * + *****************/ + + if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_rx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Save the RX RF_ACTIVE start time. */ + tsm_timing43_rx = end_of_rx_wu - temp; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); +#else + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ + tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); + +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; +#else + temp = XCVR_TSM->TIMING48; + temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing48; + XCVR_TSM->TIMING48 = temp; +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + temp = XCVR_TSM->TIMING50; + temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing50; + XCVR_TSM->TIMING50 = temp; + +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + GPIOC->PDDR |= 0x18; + PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#else + GPIOC->PDDR |= 0x0A; + PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + + /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + + /* RF_ACTIVE */ + temp = XCVR_TSM->TIMING48; + temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing48; + XCVR_TSM->TIMING48 = temp; + + /* RF_PRIORITY */ + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; + + /* Overwrite pins settings */ + GPIOC->PDDR |= 0x12; + PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d; + + if (tsm_timing43_tx > end_of_tx_wu - 1) + { + tsm_timing43_tx = end_of_tx_wu - 1; + } + + tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d; + + if (tsm_timing43_rx > end_of_rx_wu - 1) + { + tsm_timing43_rx = end_of_rx_wu - 1; + } + + XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) | + (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | + (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) | + (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)); + + BTLE_RF->MISC_CTRL = 0x02; + + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK; + + /* Save the updated registers values. */ + XCVR_CoexistenceSaveRestoreTimings(1); +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + +xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority) +{ +#if gMWS_UseCoexistence_d + uint32_t temp = 0x00U; + uint32_t end_of_tx_wu = 0x00U; + uint32_t end_of_rx_wu = 0x00U; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + uint32_t tsm_timing50 = 0x00U; +#endif +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + uint32_t tsm_timing47 = 0x00U; +#endif + + /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ + end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + +/***************** + * RX * + *****************/ + + if (XCVR_COEX_HIGH_PRIO == rxPriority) + { + if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_rx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */ + tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */ + tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + else + { + /* Low priority RX */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + +/***************** + * TX * + *****************/ + if (XCVR_COEX_HIGH_PRIO == txPriority) + { + if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_tx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + else + { +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ + tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + temp = XCVR_TSM->TIMING50; + temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing50; + XCVR_TSM->TIMING50 = temp; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + /* Save the updated registers values. */ + XCVR_CoexistenceSaveRestoreTimings(1); +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + +xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) +{ +#if gMWS_UseCoexistence_d + static uint32_t tsm_ovrd0_saved = 0x00; + static uint32_t tsm_ovrd1_saved = 0x00; + static uint32_t tsm_ovrd2_saved = 0x00; + static uint32_t tsm_ovrd3_saved = 0x00; + static uint32_t tsm_timing47_saved = 0x00; + static uint32_t tsm_timing48_saved = 0x00; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + static uint32_t tsm_timing49_saved = 0x00; + static uint32_t tsm_timing50_saved = 0x00; +#endif + + if (saveTimings == 0) + { + /* Restore registers values. */ + XCVR_TSM->OVRD0 = tsm_ovrd0_saved; + XCVR_TSM->OVRD1 = tsm_ovrd1_saved; + XCVR_TSM->OVRD2 = tsm_ovrd2_saved; + XCVR_TSM->OVRD3 = tsm_ovrd3_saved; + + XCVR_TSM->TIMING47 = tsm_timing47_saved; + XCVR_TSM->TIMING48 = tsm_timing48_saved; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + XCVR_TSM->TIMING49 = tsm_timing49_saved; + XCVR_TSM->TIMING50 = tsm_timing50_saved; +#endif + } + else + { + /* Save registers values. */ + tsm_ovrd0_saved = XCVR_TSM->OVRD0; + tsm_ovrd1_saved = XCVR_TSM->OVRD1; + tsm_ovrd2_saved = XCVR_TSM->OVRD2; + tsm_ovrd3_saved = XCVR_TSM->OVRD3; + tsm_timing47_saved = XCVR_TSM->TIMING47; + tsm_timing48_saved = XCVR_TSM->TIMING48; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing49_saved = XCVR_TSM->TIMING49; + tsm_timing50_saved = XCVR_TSM->TIMING50; +#endif + } +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h new file mode 100644 index 0000000000000..0233af3245441 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr.h @@ -0,0 +1,1236 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_XCVR_H_ +/* clang-format off */ +#define _FSL_XCVR_H_ +/* clang-format on */ + +#include "cpu.h" +#include "fsl_xcvr_trim.h" + +#if gMWS_UseCoexistence_d +#include "MWS.h" +#endif /* gMWS_UseCoexistence_d */ +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* KW4xZ/KW3xZ/KW2xZ Radio type */ +#define RADIO_IS_GEN_2P0 (1) + +/* Default RF OSC definition. Allows for compile time clock frequency definition */ +#ifdef CLOCK_MAIN + +#else +#if RF_OSC_26MHZ == 1 +#define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */ +#else +#define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */ +#endif /* RF_OSC_26MHZ == 1 */ +#endif /* CLOCK_MAIN */ + +#define TBD_ZERO (0) +#define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0)) + +#define B0(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU) +#define B1(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U) +#define B2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U) +#define B3(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U) + +#define USE_DEFAULT_PRE_REF (0) +#define TRIM_BBA_DCOC_DAC_AT_INIT (1) +#define PRESLOW_ENA (1) + +/* GEN3 TSM defines */ +#if RADIO_IS_GEN_3P0 + +/* TSM timings initializations for Gen3 radio */ +/* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */ +/* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */ +/* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */ +#if RF_OSC_26MHZ == 1 +#define TSM_TIMING00init (0x6d006f00U) /* (bb_ldo_hf_en) */ +#define TSM_TIMING01init (0x6d006f00U) /* (bb_ldo_adcdac_en) */ +#define TSM_TIMING02init (0x6d00ffffU) /* (bb_ldo_bba_en) */ +#define TSM_TIMING03init (0x6d006f00U) /* (bb_ldo_pd_en) */ +#define TSM_TIMING04init (0x6d006f00U) /* (bb_ldo_fdbk_en) */ +#define TSM_TIMING05init (0x6d006f00U) /* (bb_ldo_vcolo_en) */ +#define TSM_TIMING06init (0x6d006f00U) /* (bb_ldo_vtref_en) */ +#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ +#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ +#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ +#define TSM_TIMING10init (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */ +#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ +#define TSM_TIMING12init (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ +#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ +#define TSM_TIMING14init (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */ +#define TSM_TIMING15init (0x6d036f03U) /* (sy_vco_en) */ +#define TSM_TIMING16init (0x6d20ffffU) /* (sy_lo_rx_buf_en) */ +#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ +#define TSM_TIMING18init (0x6d056f05U) /* (sy_divn_en) */ +#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ +#define TSM_TIMING20init (0x6d036f03U) /* (sy_pd_en) */ +#define TSM_TIMING21init (0x6d046f04U) /* (sy_lo_divn_en) */ +#define TSM_TIMING22init (0x6d04ffffU) /* (sy_lo_rx_en) */ +#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ +#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ +#define TSM_TIMING25init (0x6d21ffffU) /* (rx_lna_mixer_en) */ +#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ +#define TSM_TIMING27init (0x6d24ffffU) /* (rx_adc_i_q_en) */ +#define TSM_TIMING28init (0x2524ffffU) /* (rx_adc_reset_en) */ +#define TSM_TIMING29init (0x6d22ffffU) /* (rx_bba_i_q_en) */ +#define TSM_TIMING30init (0x6d24ffffU) /* (rx_bba_pdet_en) */ +#define TSM_TIMING31init (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */ +#define TSM_TIMING32init (0x6d21ffffU) /* (rx_tza_i_q_en) */ +#define TSM_TIMING33init (0x6d24ffffU) /* (rx_tza_pdet_en) */ +#define TSM_TIMING34init (0x6d076f07U) /* (pll_dig_en) */ +#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ +#define TSM_TIMING36init (0x6d6affffU) /* (rx_dig_en) */ +#define TSM_TIMING37init (0x6b6affffU) /* (rx_init) */ +#define TSM_TIMING38init (0x6d0e6f42U) /* (sigma_delta_en) */ +#define TSM_TIMING39init (0x6d6affffU) /* (rx_phy_en) */ +#define TSM_TIMING40init (0x6d2affffU) /* (dcoc_en) */ +#define TSM_TIMING41init (0x2b2affffU) /* (dcoc_init) */ +#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ +#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ +#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ +#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ +#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ +#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ +#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ +#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ +#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ +#define TSM_TIMING51init (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */ +#define TSM_TIMING52init (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */ +#define TSM_TIMING53init (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */ +#define TSM_TIMING54init (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ +#define TSM_TIMING55init (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */ +#define TSM_TIMING56init (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */ +#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ +#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ +#define END_OF_SEQinit (0x6d6c6f67U) /* */ +#define TX_RX_ON_DELinit (0x00008a86U) /* */ +#define TX_RX_SYNTH_init (0x00002318U) /* */ +#else +#define TSM_TIMING00init (0x69006f00U) /* (bb_ldo_hf_en) */ +#define TSM_TIMING01init (0x69006f00U) /* (bb_ldo_adcdac_en) */ +#define TSM_TIMING02init (0x6900ffffU) /* (bb_ldo_bba_en) */ +#define TSM_TIMING03init (0x69006f00U) /* (bb_ldo_pd_en) */ +#define TSM_TIMING04init (0x69006f00U) /* (bb_ldo_fdbk_en) */ +#define TSM_TIMING05init (0x69006f00U) /* (bb_ldo_vcolo_en) */ +#define TSM_TIMING06init (0x69006f00U) /* (bb_ldo_vtref_en) */ +#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ +#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ +#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ +#define TSM_TIMING10init (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */ +#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ +#define TSM_TIMING12init (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ +#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ +#define TSM_TIMING14init (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */ +#define TSM_TIMING15init (0x69036f03U) /* (sy_vco_en) */ +#define TSM_TIMING16init (0x691cffffU) /* (sy_lo_rx_buf_en) */ +#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ +#define TSM_TIMING18init (0x69056f05U) /* (sy_divn_en) */ +#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ +#define TSM_TIMING20init (0x69036f03U) /* (sy_pd_en) */ +#define TSM_TIMING21init (0x69046f04U) /* (sy_lo_divn_en) */ +#define TSM_TIMING22init (0x6904ffffU) /* (sy_lo_rx_en) */ +#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ +#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ +#define TSM_TIMING25init (0x691dffffU) /* (rx_lna_mixer_en) */ +#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ +#define TSM_TIMING27init (0x6920ffffU) /* (rx_adc_i_q_en) */ +#define TSM_TIMING28init (0x2120ffffU) /* (rx_adc_reset_en) */ +#define TSM_TIMING29init (0x691effffU) /* (rx_bba_i_q_en) */ +#define TSM_TIMING30init (0x6920ffffU) /* (rx_bba_pdet_en) */ +#define TSM_TIMING31init (0x691fffffU) /* (rx_bba_tza_dcoc_en) */ +#define TSM_TIMING32init (0x691dffffU) /* (rx_tza_i_q_en) */ +#define TSM_TIMING33init (0x6920ffffU) /* (rx_tza_pdet_en) */ +#define TSM_TIMING34init (0x69076f07U) /* (pll_dig_en) */ +#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ +#define TSM_TIMING36init (0x6966ffffU) /* (rx_dig_en) */ +#define TSM_TIMING37init (0x6766ffffU) /* (rx_init) */ +#define TSM_TIMING38init (0x690e6f42U) /* (sigma_delta_en) */ +#define TSM_TIMING39init (0x6966ffffU) /* (rx_phy_en) */ +#define TSM_TIMING40init (0x6926ffffU) /* (dcoc_en) */ +#define TSM_TIMING41init (0x2726ffffU) /* (dcoc_init) */ +#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ +#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ +#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ +#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ +#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ +#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ +#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ +#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ +#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ +#define TSM_TIMING51init (0x6903ffffU) /* (rxtx_auxpll_bias_en) */ +#define TSM_TIMING52init (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */ +#define TSM_TIMING53init (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */ +#define TSM_TIMING54init (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ +#define TSM_TIMING55init (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */ +#define TSM_TIMING56init (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */ +#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ +#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ +#define END_OF_SEQinit (0x69686f67U) /* */ +#define TX_RX_ON_DELinit (0x00008a86U) /* */ +#define TX_RX_SYNTH_init (0x00002318U) /* */ +#endif /* RF_OSC_26MHZ == 1 */ + +#define AUX_PLL_DELAY (0) +/* TSM bitfield shift and value definitions */ +#define TX_DIG_EN_ASSERT (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */ +#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ +/* EDIT THIS LINE TO CONTROL PA_RAMP! */ +#define PA_RAMP_TIME (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */ +#define PA_RAMP_SEL_0US (0) +#define PA_RAMP_SEL_1US (1) +#define PA_RAMP_SEL_2US (2) +#define PA_RAMP_SEL_4US (3) +#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4)) +#error "Invalid value for PA_RAMP_TIME macro" +#endif /* Error check of PA RAMP TIME */ + +#define ADD_FOR_26MHZ (4) +#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ +/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ +#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) + #if (PA_RAMP_TIME == 0) + #define PA_RAMP_SEL PA_RAMP_SEL_0US + #define DATA_PADDING_EN (0) + #else + #define DATA_PADDING_EN (1) + #if (PA_RAMP_TIME == 1) + #define PA_RAMP_SEL PA_RAMP_SEL_1US + #else + #define PA_RAMP_SEL PA_RAMP_SEL_2US + #endif /* (PA_RAMP_TIME == 1) */ + #endif /* (PA_RAMP_TIME == 0) */ +#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) */ + #if (PA_RAMP_TIME == 4) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) + #define PA_RAMP_SEL PA_RAMP_SEL_4US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME == 4) */ + #error "Invalid value for PA_RAMP_TIME macro" + #endif /* (PA_RAMP_TIME == 4) */ +#endif/* (PA_RAMP_TIME == 4) */ + +#define END_OF_RX_WU (104 + AUX_PLL_DELAY) + +#if RF_OSC_26MHZ == 1 +#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ +#else +#define END_OF_RX_WD (END_OF_RX_WU + 1) +#endif /* RF_OSC_26MHZ == 1 */ + +#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) +#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) + +/* PA Bias Table - Gen3 version */ +#define PA_RAMP_0 0x1 +#define PA_RAMP_1 0x2 +#define PA_RAMP_2 0x4 +#define PA_RAMP_3 0x6 +#define PA_RAMP_4 0x8 +#define PA_RAMP_5 0xc +#define PA_RAMP_6 0x10 +#define PA_RAMP_7 0x14 +#define PA_RAMP_8 0x18 +#define PA_RAMP_9 0x1c +#define PA_RAMP_10 0x22 +#define PA_RAMP_11 0x28 +#define PA_RAMP_12 0x2c +#define PA_RAMP_13 0x30 +#define PA_RAMP_14 0x36 +#define PA_RAMP_15 0x3c + +#else /* Gen2 TSM definitions */ +/* GEN2 TSM defines */ +#define AUX_PLL_DELAY (0) +/* TSM bitfield shift and value definitions */ +#define TX_DIG_EN_ASSERT (95) +#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ +/* EDIT THIS LINE TO CONTROL PA_RAMP! */ +#define PA_RAMP_TIME (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */ +#define PA_RAMP_SEL_0US (0) +#define PA_RAMP_SEL_2US (1) +#define PA_RAMP_SEL_4US (2) +#define PA_RAMP_SEL_8US (3) + +#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4) || (PA_RAMP_TIME == 8)) +#error "Invalid value for PA_RAMP_TIME macro" +#endif /* Error check of PA RAMP TIME */ +#define ADD_FOR_26MHZ (4) +#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ +/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ +#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) + #define TX_SYNTH_DELAY_ADJ (0) + #define PD_CYCLE_SLIP_TX_HI_ADJ (0) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */ + #if (PA_RAMP_TIME == 0) + #define PA_RAMP_SEL PA_RAMP_SEL_0US + #define DATA_PADDING_EN (0) + #define TX_DIG_EN_TX_HI_ADJ (-2) + #else + #define DATA_PADDING_EN (1) + #define TX_DIG_EN_TX_HI_ADJ (0) + #define PA_RAMP_SEL PA_RAMP_SEL_2US + #endif /* (PA_RAMP_TIME == 0) */ +#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ + #if (PA_RAMP_TIME == 4) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) + #define TX_SYNTH_DELAY_ADJ (2) + #define PD_CYCLE_SLIP_TX_HI_ADJ (2) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define TX_DIG_EN_TX_HI_ADJ (0) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */ + #define PA_RAMP_SEL PA_RAMP_SEL_4US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME==4) */ + #if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 6) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 12) + #define TX_SYNTH_DELAY_ADJ (6) + #define PD_CYCLE_SLIP_TX_HI_ADJ (6) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define TX_DIG_EN_TX_HI_ADJ (4) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */ + #define PA_RAMP_SEL PA_RAMP_SEL_8US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME == 8) */ + #error "Invalid value for PA_RAMP_TIME macro" + #endif /* (PA_RAMP_TIME == 8) */ + #endif/* (PA_RAMP_TIME == 4) */ +#endif /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ + +#define TX_DIG_EN_ASSERT_MSK500 (END_OF_TX_WU - 3) + +#define END_OF_RX_WU (104 + AUX_PLL_DELAY) +#if RF_OSC_26MHZ == 1 +#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ +#else +#define END_OF_RX_WD (END_OF_RX_WU + 1) +#endif /* RF_OSC_26MHZ == 1 */ +#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) +#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) + +/* PA Bias Table */ +#define PA_RAMP_0 0x1 +#define PA_RAMP_1 0x2 +#define PA_RAMP_2 0x4 +#define PA_RAMP_3 0x8 +#define PA_RAMP_4 0xe +#define PA_RAMP_5 0x16 +#define PA_RAMP_6 0x22 +#define PA_RAMP_7 0x2e + +/* BLE LL timing definitions */ +#define TX_ON_DELAY (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */ +#define RX_ON_DELAY (29 + END_OF_RX_WU) +#define RX_ON_DELAY_26MHZ (29 + END_OF_RX_WU_26MHZ) +#define TX_RX_ON_DELAY_VAL (TX_ON_DELAY << 8 | RX_ON_DELAY) +#define TX_RX_ON_DELAY_VAL_26MHZ (TX_ON_DELAY << 8 | RX_ON_DELAY_26MHZ) +#define TX_SYNTH_DELAY (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */ +#define RX_SYNTH_DELAY (0x18) +#define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 | RX_SYNTH_DELAY) + +/* PHY reference waveform assembly */ +#define RW0PS(loc, val) (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */ +#define RW1PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */ +#define RW2PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */ +#endif /* RADIO_IS_GEN_3P0 */ + +/*! @brief Error codes for the XCVR driver. */ +typedef enum _xcvrStatus +{ + gXcvrSuccess_c = 0, + gXcvrInvalidParameters_c, + gXcvrUnsupportedOperation_c, + gXcvrTrimFailure_c +} xcvrStatus_t; + +/*! @brief Health status returned from PHY upon status check function return. */ +typedef enum _healthStatus +{ + NO_ERRORS = 0, + PLL_CTUNE_FAIL = 1, + PLL_CYCLE_SLIP_FAIL = 2, + PLL_FREQ_TARG_FAIL = 4, + PLL_TSM_ABORT_FAIL = 8, +} healthStatus_t; + +/*! @brief Health status returned from PHY upon status check function return. */ +typedef enum _ext_clock_config +{ + EXT_CLK_32_MHZ = 0, + EXT_CLK_26_MHZ = 1, +} ext_clock_config_t; + +/*! @brief Radio operating mode setting types. */ +typedef enum _radio_mode +{ + BLE_MODE = 0, + ZIGBEE_MODE = 1, + ANT_MODE = 2, + + /* BT=0.5, h=** */ + GFSK_BT_0p5_h_0p5 = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */ + GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/ + GFSK_BT_0p5_h_0p7 = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */ + GFSK_BT_0p5_h_1p0 = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */ + + /* BT=** h=0.5 */ + GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */ + GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */ + + MSK = 9, + NUM_RADIO_MODES = 10, +} radio_mode_t; + +/*! @brief Link layer types. */ +typedef enum _link_layer +{ + BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */ + ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */ + ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */ + GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */ + UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */ +} link_layer_t; + +/*! @brief Data rate selections. */ +typedef enum _data_rate +{ + DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */ + DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */ + DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */ +#if RADIO_IS_GEN_3P0 + DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */ +#endif /* RADIO_IS_GEN_3P0 */ + DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */ +} data_rate_t; + +/*! @brief Control settings for Fast Antenna Diversity */ +typedef enum _FAD_LPPS_CTRL +{ + NONE = 0, + FAD_ENABLED = 1, + LPPS_ENABLED = 2 +} FAD_LPPS_CTRL_T; + +/*! @brief XCVR XCVR Panic codes for indicating panic reason. */ +typedef enum _XCVR_PANIC_ID +{ + WRONG_RADIO_ID_DETECTED = 1, + CALIBRATION_INVALID = 2, +} XCVR_PANIC_ID_T; + +/*! @brief Initialization or mode change selection for config routine. */ +typedef enum _XCVR_INIT_MODE_CHG +{ + XCVR_MODE_CHANGE = 0, + XCVR_FIRST_INIT = 1, +} XCVR_INIT_MODE_CHG_T; + +typedef enum _XCVR_COEX_PRIORITY +{ + XCVR_COEX_LOW_PRIO = 0, + XCVR_COEX_HIGH_PRIO = 1 +} XCVR_COEX_PRIORITY_T; + +/*! @brief Current configuration of the radio. */ +typedef struct xcvr_currConfig_tag +{ + radio_mode_t radio_mode; + data_rate_t data_rate; +} xcvr_currConfig_t; + +/*! + * @brief XCVR RX_DIG channel filter coefficient storage + * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage. + */ +typedef struct _xcvr_rx_chf_coeffs +{ + uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */ +} xcvr_rx_chf_coeffs_t; + +/*! + * @brief XCVR masked init type for 32 bit registers + * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position. + */ +typedef struct _xcvr_masked_init_32 +{ + uint32_t mask; + uint32_t init; +} xcvr_masked_init_32_t; + +/*! + * @brief XCVR common configure structure + */ +typedef struct _xcvr_common_config +{ + /* XCVR_ANA configs */ + xcvr_masked_init_32_t ana_sy_ctrl1; + + /* XCVR_PLL_DIG configs */ + uint32_t pll_hpm_bump; + uint32_t pll_mod_ctrl; + uint32_t pll_chan_map; + uint32_t pll_lock_detect; + uint32_t pll_hpm_ctrl; +#if !RADIO_IS_GEN_2P1 + uint32_t pll_hpmcal_ctrl; +#endif /* !RADIO_IS_GEN_2P1 */ + uint32_t pll_hpm_sdm_res; + uint32_t pll_lpm_ctrl; + uint32_t pll_lpm_sdm_ctrl1; + uint32_t pll_delay_match; + uint32_t pll_ctune_ctrl; + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init; + uint32_t dcoc_cal_gain_init; + uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */ + uint32_t dcoc_cal_rcp_init; + uint32_t lna_gain_val_3_0; + uint32_t lna_gain_val_7_4; + uint32_t lna_gain_val_8; + uint32_t bba_res_tune_val_7_0; + uint32_t bba_res_tune_val_10_8; + uint32_t lna_gain_lin_val_2_0_init; + uint32_t lna_gain_lin_val_5_3_init; + uint32_t lna_gain_lin_val_8_6_init; + uint32_t lna_gain_lin_val_9_init; + uint32_t bba_res_tune_lin_val_3_0_init; + uint32_t bba_res_tune_lin_val_7_4_init; + uint32_t bba_res_tune_lin_val_10_8_init; + uint32_t dcoc_bba_step_init; + uint32_t dcoc_tza_step_00_init; + uint32_t dcoc_tza_step_01_init; + uint32_t dcoc_tza_step_02_init; + uint32_t dcoc_tza_step_03_init; + uint32_t dcoc_tza_step_04_init; + uint32_t dcoc_tza_step_05_init; + uint32_t dcoc_tza_step_06_init; + uint32_t dcoc_tza_step_07_init; + uint32_t dcoc_tza_step_08_init; + uint32_t dcoc_tza_step_09_init; + uint32_t dcoc_tza_step_10_init; +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + uint32_t dcoc_cal_fail_th_init; + uint32_t dcoc_cal_pass_th_init; +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ + uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ + uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ + uint32_t agc_ctrl_3_init; + /* Other agc config inits moved to modeXdatarate config table */ + uint32_t agc_gain_tbl_03_00_init; + uint32_t agc_gain_tbl_07_04_init; + uint32_t agc_gain_tbl_11_08_init; + uint32_t agc_gain_tbl_15_12_init; + uint32_t agc_gain_tbl_19_16_init; + uint32_t agc_gain_tbl_23_20_init; + uint32_t agc_gain_tbl_26_24_init; + uint32_t rssi_ctrl_0_init; +#if RADIO_IS_GEN_3P0 + uint32_t rssi_ctrl_1_init; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t cca_ed_lqi_ctrl_0_init; + uint32_t cca_ed_lqi_ctrl_1_init; + + /* XCVR_TSM configs */ + uint32_t tsm_ctrl; + uint32_t tsm_ovrd2_init; + uint32_t end_of_seq_init_26mhz; + uint32_t end_of_seq_init_32mhz; +#if !RADIO_IS_GEN_2P1 + uint32_t lpps_ctrl_init; +#endif /* !RADIO_IS_GEN_2P1 */ + uint32_t tsm_fast_ctrl2_init_26mhz; + uint32_t tsm_fast_ctrl2_init_32mhz; + uint32_t recycle_count_init_26mhz; + uint32_t recycle_count_init_32mhz; + uint32_t pa_ramp_tbl_0_init; + uint32_t pa_ramp_tbl_1_init; +#if RADIO_IS_GEN_3P0 + uint32_t pa_ramp_tbl_2_init; + uint32_t pa_ramp_tbl_3_init; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t tsm_timing_00_init; + uint32_t tsm_timing_01_init; + uint32_t tsm_timing_02_init; + uint32_t tsm_timing_03_init; + uint32_t tsm_timing_04_init; + uint32_t tsm_timing_05_init; + uint32_t tsm_timing_06_init; + uint32_t tsm_timing_07_init; + uint32_t tsm_timing_08_init; + uint32_t tsm_timing_09_init; + uint32_t tsm_timing_10_init; + uint32_t tsm_timing_11_init; + uint32_t tsm_timing_12_init; + uint32_t tsm_timing_13_init; + uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ + uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ + uint32_t tsm_timing_15_init; + uint32_t tsm_timing_16_init_26mhz; + uint32_t tsm_timing_16_init_32mhz; + uint32_t tsm_timing_17_init; + uint32_t tsm_timing_18_init; + uint32_t tsm_timing_19_init; + uint32_t tsm_timing_20_init; + uint32_t tsm_timing_21_init; + uint32_t tsm_timing_22_init; + uint32_t tsm_timing_23_init; + uint32_t tsm_timing_24_init; + uint32_t tsm_timing_25_init_26mhz; + uint32_t tsm_timing_25_init_32mhz; + uint32_t tsm_timing_26_init; + uint32_t tsm_timing_27_init_26mhz; + uint32_t tsm_timing_27_init_32mhz; + uint32_t tsm_timing_28_init_26mhz; + uint32_t tsm_timing_28_init_32mhz; + uint32_t tsm_timing_29_init_26mhz; + uint32_t tsm_timing_29_init_32mhz; + uint32_t tsm_timing_30_init_26mhz; + uint32_t tsm_timing_30_init_32mhz; + uint32_t tsm_timing_31_init_26mhz; + uint32_t tsm_timing_31_init_32mhz; + uint32_t tsm_timing_32_init_26mhz; + uint32_t tsm_timing_32_init_32mhz; + uint32_t tsm_timing_33_init_26mhz; + uint32_t tsm_timing_33_init_32mhz; + uint32_t tsm_timing_34_init; + uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/ + uint32_t tsm_timing_36_init_26mhz; + uint32_t tsm_timing_36_init_32mhz; + uint32_t tsm_timing_37_init_26mhz; + uint32_t tsm_timing_37_init_32mhz; + uint32_t tsm_timing_38_init; + uint32_t tsm_timing_39_init_26mhz; + uint32_t tsm_timing_39_init_32mhz; + uint32_t tsm_timing_40_init_26mhz; + uint32_t tsm_timing_40_init_32mhz; + uint32_t tsm_timing_41_init_26mhz; + uint32_t tsm_timing_41_init_32mhz; + uint32_t tsm_timing_51_init; + uint32_t tsm_timing_52_init_26mhz; + uint32_t tsm_timing_52_init_32mhz; + uint32_t tsm_timing_53_init; + uint32_t tsm_timing_54_init_26mhz; + uint32_t tsm_timing_54_init_32mhz; + uint32_t tsm_timing_55_init_26mhz; + uint32_t tsm_timing_55_init_32mhz; + uint32_t tsm_timing_56_init_26mhz; + uint32_t tsm_timing_56_init_32mhz; + uint32_t tsm_timing_57_init; + uint32_t tsm_timing_58_init; + + /* XCVR_TX_DIG configs */ + uint32_t tx_ctrl; + uint32_t tx_data_padding; + uint32_t tx_dft_pattern; +#if !RADIO_IS_GEN_2P1 + uint32_t rf_dft_bist_1; + uint32_t rf_dft_bist_2; +#endif /* !RADIO_IS_GEN_2P1 */ +} xcvr_common_config_t; + +/*! @brief XCVR mode specific configure structure (varies by radio mode) */ +typedef struct _xcvr_mode_config +{ + radio_mode_t radio_mode; + uint32_t scgc5_clock_ena_bits; + + /* XCVR_MISC configs */ + xcvr_masked_init_32_t xcvr_ctrl; + + /* XCVR_PHY configs */ +#if RADIO_IS_GEN_3P0 + uint32_t phy_fsk_pd_cfg0; + uint32_t phy_fsk_pd_cfg1; + uint32_t phy_fsk_cfg; + uint32_t phy_fsk_misc; + uint32_t phy_fad_ctrl; +#else + uint32_t phy_pre_ref0_init; + uint32_t phy_pre_ref1_init; + uint32_t phy_pre_ref2_init; + uint32_t phy_cfg1_init; + uint32_t phy_el_cfg_init; /* Should leave EL_WIN_SIZE and EL_INTERVAL to the data_rate specific configuration */ +#endif /* RADIO_IS_GEN_3P0 */ + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ + + /* XCVR_TSM configs */ +#if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) + uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */ +#endif /* (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) */ + + /* XCVR_TX_DIG configs */ + uint32_t tx_gfsk_ctrl; + uint32_t tx_gfsk_coeff1_26mhz; + uint32_t tx_gfsk_coeff2_26mhz; + uint32_t tx_gfsk_coeff1_32mhz; + uint32_t tx_gfsk_coeff2_32mhz; +} xcvr_mode_config_t; + +/*! + * @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate) + * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay + * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. + */ +typedef struct _xcvr_mode_datarate_config +{ + radio_mode_t radio_mode; + data_rate_t data_rate; + + /* XCVR_ANA configs */ + xcvr_masked_init_32_t ana_sy_ctrl2; + xcvr_masked_init_32_t ana_rx_bba; + xcvr_masked_init_32_t ana_rx_tza; + + /* XCVR_PHY configs */ +#if RADIO_IS_GEN_3P0 + uint32_t phy_fsk_misc_mode_datarate; +#else + uint32_t phy_cfg2_init; +#endif /* RADIO_IS_GEN_3P0 */ + + uint32_t agc_ctrl_2_init_26mhz; + uint32_t agc_ctrl_2_init_32mhz; + xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */ + xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */ + uint32_t rx_rccal_ctrl_0; + uint32_t rx_rccal_ctrl_1; + + /* XCVR_TX_DIG configs */ + uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */ + uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */ +} xcvr_mode_datarate_config_t; + +/*! + * @brief XCVR datarate specific configure structure (varies by data rate) + * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay + * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. + */ +typedef struct _xcvr_datarate_config +{ + data_rate_t data_rate; + + /* XCVR_PHY configs */ + uint32_t phy_el_cfg_init; /* Note: EL_ENABLE is set in xcvr_mode_config_t settings */ + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t agc_ctrl_1_init_26mhz; + uint32_t agc_ctrl_1_init_32mhz; + uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ + uint32_t dcoc_ctrl_2_init_26mhz; + uint32_t dcoc_ctrl_2_init_32mhz; + uint32_t dcoc_cal_iir_init_26mhz; + uint32_t dcoc_cal_iir_init_32mhz; + uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ + uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ +} xcvr_datarate_config_t; + +/*! + * @brief LPUART callback function type + * + * The panic callback function is defined by system if system need to be informed of XCVR fatal errors. + * refer to #XCVR_RegisterPanicCb + */ +typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2); + +/* Make available const structures from config files */ +extern const xcvr_common_config_t xcvr_common_config; +extern const xcvr_mode_config_t zgbe_mode_config; +extern const xcvr_mode_config_t ble_mode_config; +extern const xcvr_mode_config_t ant_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config; +extern const xcvr_mode_config_t msk_mode_config; + +#if RADIO_IS_GEN_3P0 +extern const xcvr_datarate_config_t xcvr_2mbps_config; +#endif /* RADIO_IS_GEN_3P0 */ +extern const xcvr_datarate_config_t xcvr_1mbps_config; +extern const xcvr_datarate_config_t xcvr_500kbps_config; +extern const xcvr_datarate_config_t xcvr_250kbps_config; +extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */ + +#if RADIO_IS_GEN_3P0 +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config; +#endif /* RADIO_IS_GEN_3P0 */ +extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name XCVR functional Operation + * @{ + */ + +/*! + * @brief Initializes an XCVR instance. + * + * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to + * start up the XCVR in most situations. + * + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions. + */ +xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate); + +/*! + * @brief Deinitializes an XCVR instance. + * + * This function gate the XCVR module clock and set all register value to reset value. + * + */ +void XCVR_Deinit(void); + +/*! + * @brief Initializes XCVR configure structure. + * + * This function updates pointers to the XCVR configure structures with default values. + * The configurations are divided into a common structure, a set of radio mode specific + * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at + * each datarate), and a set of data rate specific structures. + * The pointers provided by this routine point to const structures which can be + * copied to variable structures if changes to settings are required. + * + * @param radio_mode [in] The radio mode for which the configuration structures are requested. + * @param data_rate [in] The data rate for which the configuration structures are requested. + * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure. + * @param mode_config [in,out] Pointer to a pointer to the mode specific configuration settings structure. + * @param mode_datarate_config [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure. + * @param datarate_config [in,out] Pointer to a pointer to the data rate specific configuration settings structure. + * @return 0 success, others failure + * @see XCVR_Configure + */ +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, + const xcvr_datarate_config_t ** datarate_config); + +/*! + * @brief Initializes an XCVR instance. + * + * This function initializes the XCVR module with user-defined settings. + * + * @param com_config Pointer to the common configuration settings structure. + * @param mode_config Pointer to the mode specific configuration settings structure. + * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure. + * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure. + * @param tempDegC temperature of the die in degrees C. + * @param ext_clk indicates the external clock setting, 32MHz or 26MHz. + * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0) + * @return 0 succeed, others failed + */ +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, + XCVR_INIT_MODE_CHG_T first_init); + +/*! + * @brief Set XCVR register to reset value. + * + * This function set XCVR register to the reset value. + * + */ +void XCVR_Reset(void); + +/*! + * @brief Change the operating mode of the radio. + * + * This function changes the XCVR to a new radio operating mode. + * + * @param new_radio_mode The radio mode for which the XCVR should be configured. + * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @return status of the mode change. + */ + xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate); + +/*! + * @brief Enable Narrowband RSSI measurement. + * + * This function enables the narrowband RSSI measurement + * + * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled. + */ +void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable); + +/*! + * @brief Set an arbitrary frequency for RX and TX for the radio. + * + * This function sets the radio frequency used for RX and RX.. + * + * @param freq target frequency setting in Hz. + * @param refOsc reference oscillator setting in Hz. + * @return status of the frequency change. + * @details + */ + xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc); + +/*! + * @brief Register a callback from upper layers. + * + * This function registers a callback from the upper layers for the radio to call in case of fatal errors. + * + * @param fptr The function pointer to a panic callback. + */ +void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */ + +/*! + * @brief Read the health status of the XCVR to detect errors. + * + * This function enables the upper layers to request the current radio health. + * + * @return The health status of the radio.. + */ +healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */ + +/*! + * @brief Control FAD and LPPS features. + * + * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search. + * + * @param fptr control the FAD and LPPS settings. + * + */ + void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control); + +/*! + * @brief Change the mapping of the radio IRQs. + * + * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. + * + * @param irq0_mapping the LL which should be mapped to the INT0 line. + * @param irq1_mapping the LL which should be mapped to the INT1 line. + * @return status of the mapping request. + * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line. + * @warning + * The same LL must NOT be mapped to both INT lines. + */ + xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping); + +#if RADIO_IS_GEN_3P0 +/*! + * @brief Sets the network address used by the PHY during BLE Bit Streaming Mode. + * + * This function programs the register in the PHY which contains the network address used during BSM. + * + * @param bsm_ntw_address the address to be used during BSM. + * @ note This routine does NOT enable BSM. + */ +void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address); + +/*! + * @brief Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode. + * + * This function reads the register in the PHY which contains the network address used during BSM. + * + * @return bsm_ntw_address the address to be used during BSM. + * @ note This routine does NOT enable BSM. + */ +uint32_t XCVR_GetBSM_NTW_Address(void); +#endif /* RADIO_IS_GEN_3P0 */ + +/*! + * @brief Get the mapping of the one of the radio IRQs. + * + * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. + * + * @param int_num the number, 0 or 1, of the INT line to fetched. + * @return the mapping setting of the specified line. + * @note Any value passed into this routine other than 0 will be treated as a 1. + */ + link_layer_t XCVR_GetIRQMapping(uint8_t int_num); + +/*! + * @brief Get the current configuration of the XCVR. + * + * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc + * + * @param curr_config pointer to a structure to be updated with the current mode and data rate. + * @return the status of the request, success or invalid parameter (null pointer). + * @note This API will return meaningless results if called before the radio is initialized... + */ +xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config); + +/******************************************************************************* + * Customer level trim functions + ******************************************************************************/ +/*! + * @brief Controls setting the XTAL trim value.. + * + * This function enables the upper layers set a crystal trim compensation facor + * + * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error. + * @return The health status of the radio.. + */ +xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim); + +/*! + * @brief Controls getting the XTAL trim value.. + * + * This function enables the upper layers to read the current XTAL compensation factors. + * The returned value is in the range 0..127 (7 bits). + * + * @return The XTAL trim compensation factors.. + */ +uint8_t XCVR_GetXtalTrim(void); + +/*! + * @brief Controls setting the RSSI adjustment.. + * + * This function enables the upper layers to set an RSSI adjustment value. + * + * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step. + * @return The health status of the radio.. + */ +xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj); + +/*! + * @brief Controls getting the RSSI adjustment.. + * + * This function enables the upper layers to read the current XCVR RSSI adjustment value. + * The returned value is a signed 8-bit value, in 1/4 dBm step. + * + * @return The RSSI adjustment value.. + */ +int8_t XCVR_GetRssiAdjustment(void); + +/*! + * @brief Controls setting the PLL to a particular channel. + * + * This function enables setting the radio channel for TX and RX. + * + * @param channel the channel number to set + * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list.. + * @return The status of the channel over-ride. + */ +xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel); + +/*! + * @brief Reads the current frequency for RX and TX for the radio. + * + * This function reads the radio frequency used for RX and RX.. + * + * @return Current radio frequency setting. + */ +uint32_t XCVR_GetFreq(void); + +/*! + * @brief Force receiver warmup. + * + * This function forces the initiation of a receiver warmup sequence. + * + */ +void XCVR_ForceRxWu(void); + +/*! + * @brief Force receiver warmdown. + * + * This function forces the initiation of a receiver warmdown sequence. + * + */ + void XCVR_ForceRxWd(void); + +/*! + * @brief Force transmitter warmup. + * + * This function forces the initiation of a transmit warmup sequence. + * + */ +void XCVR_ForceTxWu(void); + +/*! + * @brief Force transmitter warmdown. + * + * This function forces the initiation of a transmit warmdown sequence. + * + */ +void XCVR_ForceTxWd(void); + +/*! + * @brief Starts transmit with a TX pattern register data sequence. + * + * This function starts transmitting using the DFT pattern register mode. + * + * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @param tx_pattern - the data pattern to transmit on. + * @return The status of the pattern reg transmit. + * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode + * and data rate. + */ +xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern); + +/*! + * @brief Starts transmit with a TX LFSR register data sequence. + * + * This function starts transmitting using the DFT LFSR register mode. + * + * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @param lfsr_length - the length of the LFSR sequence to use. + * @return The status of the LFSR reg transmit. + * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode + * and data rate. + */ +xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length); + +/*! + * @brief Controls clearing all TX DFT settings. + * + * This function reverts all TX DFT settings from the test modes to normal operating mode. + * + */ +void XCVR_DftTxOff(void); + +/*! + * @brief Controls setting the PA power level. + * + * This function enables setting the PA power level to a specific setting, overriding any link layer settings. + * + * @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive. + * @return The status of the PA power over-ride. + */ +xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); + +/*! + * @brief Starts CW TX. + * + * This function starts transmitting CW (no modulation). + * + * @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive. + * @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK). + * @return The status of the CW transmit. + */ +xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol); + +xcvrStatus_t XCVR_CoexistenceInit(void); +xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority); +xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_XCVR_H_ */ + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c new file mode 100644 index 0000000000000..319a104a0e8bc --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t ant_mode_config = +{ + .radio_mode = ANT_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK +#if !RADIO_IS_GEN_2P1 + | SIM_SCGC5_ANT_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = RW0PS(0, 0x1B) | + RW0PS(1, 0x1CU) | + RW0PS(2, 0x1CU) | + RW0PS(3, 0x1CU) | + RW0PS(4, 0x1DU) | + RW0PS(5, 0x1DU) | + RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/ + .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift */ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1EU) | + RW1PS(11, 0x1DU) | + RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */ + RW2PS(13, 0x1CU) | + RW2PS(14, 0x1CU) | + RW2PS(15, 0x1CU), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xF8) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = +{ + .radio_mode = ANT_MODE, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, + + /* ANT 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c new file mode 100644 index 0000000000000..054b0ccfeaa06 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t ble_mode_config = +{ + .radio_mode = BLE_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = RW0PS(0, 0x19) | + RW0PS(1, 0x19U) | + RW0PS(2, 0x1AU) | + RW0PS(3, 0x1BU) | + RW0PS(4, 0x1CU) | + RW0PS(5, 0x1CU) | + RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ + .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1DU) | + RW1PS(11, 0x1CU) | + RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ + RW2PS(13, 0x1BU) | + RW2PS(14, 0x1AU) | + RW2PS(15, 0x19U), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(220) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */ +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = +{ + .radio_mode = BLE_MODE, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* BLE 26MHz Channel Filter */ + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, + + /* BLE 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c new file mode 100644 index 0000000000000..4277d3a1f74ff --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_common_config_t xcvr_common_config = +{ + /* XCVR_ANA configs */ + .ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK, + .ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */ + +#define hpm_vcm_tx 0 +#define hpm_vcm_cal 1 +#define hpm_fdb_res_tx 0 +#define hpm_fdb_res_cal 1 +#define modulation_word_manual 0 +#define mod_disable 0 +#define hpm_mod_manual 0 +#define hpm_mod_disable 0 +#define hpm_sdm_out_manual 0 +#define hpm_sdm_out_disable 0 +#define channel_num 0 +#define boc 0 +#define bmr 1 +#define zoc 0 +#define ctune_ldf_lev 8 +#define ftf_rx_thrsh 33 +#define ftw_rx 0 +#define ftf_tx_thrsh 6 +#define ftw_tx 0 +#define freq_count_go 0 +#define freq_count_time 0 +#define hpm_sdm_in_manual 0 +#define hpm_sdm_out_invert 0 +#define hpm_sdm_in_disable 0 +#define hpm_lfsr_size 4 +#define hpm_dth_scl 0 +#define hpm_dth_en 1 +#define hpm_integer_scale 0 +#define hpm_integer_invert 0 +#define hpm_cal_invert 1 +#define hpm_mod_in_invert 1 +#define hpm_cal_not_bumped 0 +#define hpm_cal_count_scale 0 +#define hp_cal_disable 0 +#define hpm_cal_factor_manual 0 +#define hpm_cal_array_size 1 +#define hpm_cal_time 0 +#define hpm_sdm_denom 256 +#define hpm_count_adjust 0 +#define pll_ld_manual 0 +#define pll_ld_disable 0 +#define lpm_sdm_inv 0 +#define lpm_disable 0 +#define lpm_dth_scl 8 +#define lpm_d_ctrl 1 +#define lpm_d_ovrd 1 +#define lpm_scale 8 +#define lpm_sdm_use_neg 0 +#define hpm_array_bias 0 +#define lpm_intg 38 +#define sdm_map_disable 0 +#define lpm_sdm_delay 4 +#define hpm_sdm_delay 0 +#define hpm_integer_delay 0 +#define ctune_target_manual 0 +#define ctune_target_disable 0 +#define ctune_adjust 0 +#define ctune_manual 0 +#define ctune_disable 0 + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) | + XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) | + XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) | + XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) | + XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | + XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) | + XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) | + XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) | + XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) | + XCVR_PLL_DIG_CHAN_MAP_BOC(boc) | + XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num) +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc) +#endif /* !RADIO_IS_GEN_2P1 */ + , + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) | + XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) | + XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) | + XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) | + XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) | + XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) | + XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) | + XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) | + XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) | + XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) | + XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert), +/*-------------------------------------------------------------------------------------------------*/ +#if !RADIO_IS_GEN_2P1 + .pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time), +#endif /* !RADIO_IS_GEN_2P1 */ +/*-------------------------------------------------------------------------------------------------*/ + .pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) | + XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom), +/*-------------------------------------------------------------------------------------------------*/ + .pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) | + XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) | + XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) | + XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) | + XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) | + XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual), +/*-------------------------------------------------------------------------------------------------*/ + .pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable), +/*-------------------------------------------------------------------------------------------------*/ + .pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) | + XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) | + XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay), +/*-------------------------------------------------------------------------------------------------*/ + .pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual), +/*-------------------------------------------------------------------------------------------------*/ + + /* XCVR_RX_DIG configs */ + /* NOTE: Clock specific settings are embedded in the mode dependent configs */ + .rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1), + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7), + + .agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2), + + /* DCOC configs */ + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ +#if (RADIO_IS_GEN_2P1) + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | +#endif /* (RADIO_IS_GEN_2P1) */ + XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | + XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ +#if (RADIO_IS_GEN_2P1) + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | +#endif /* (RADIO_IS_GEN_2P1) */ + XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | + XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), + + .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26), + + .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(4) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26), + + .dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) , + + .dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) | + XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711), + + .lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U), + + .lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU), + .lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) | + XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U), + + .bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF), + .bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2), + + .lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1), + + .lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7), + + .lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50), + + .lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91), + + .bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22), + + .bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */ + + .bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288), + + .dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) | + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279), + + .dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) | + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404), + .dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) | + XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439), + .dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) | + XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691), + .dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) | + XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192), + .dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) | + XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835), + .dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) | + XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601), + .dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) | + XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427), + .dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) | + XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310), + .dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) | + XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209), + .dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) | + XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145), + .dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) | + XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99), +#if (RADIO_IS_GEN_2P1) + .dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) | + XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10), + .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) | + XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2), +#endif /* (RADIO_IS_GEN_2P1) */ + /* AGC Configs */ + .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2), + + .agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2), + + .agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4), + + .agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5), + + .agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7), + + .agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7), + + .agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10), + + .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) | +#else + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) , + + .cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0), + + .cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2), + + /* XCVR_TSM configs */ + .tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) | + XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) | + XCVR_TSM_CTRL_TSM_IRQ0_EN(0) | + XCVR_TSM_CTRL_TSM_IRQ1_EN(0) | + XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) | + XCVR_TSM_CTRL_TX_ABORT_DIS(0) | + XCVR_TSM_CTRL_RX_ABORT_DIS(0) | + XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) | + XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) | + XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) | + XCVR_TSM_CTRL_BKPT(0xFF) , + + .tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK, + .end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), + .end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), + +#if !RADIO_IS_GEN_2P1 + .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0), +#endif /* !RADIO_IS_GEN_2P1 */ + + .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8), + .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8), + + .pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) | + XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3), + .pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) | + XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7), + + .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ), + .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66), + + .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */ + .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */ + .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */ + .tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */ + .tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */ + .tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */ + .tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */ + .tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */ + .tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */ + .tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */ + + .tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */ + .tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */ + .tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */ + .tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */ + .tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */ + .tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), + .tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */ + .tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */ + .tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */ + .tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */ + .tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */ + + .tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */ + .tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */ + .tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_en */ + .tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en */ + .tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */ + .tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */ + .tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */ + .tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */ + .tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */ + .tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */ + .tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + + .tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */ + .tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */ + .tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */ + .tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */ + .tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */ + .tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */ + .tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */ + .tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */ + .tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */ + .tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */ + .tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + + .tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */ + .tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */ + .tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */ + .tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */ + .tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */ + .tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */ + .tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */ + .tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */ + .tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en */ + .tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */ + +/* XCVR_TX_DIG configs */ +#define radio_dft_mode 0 +#define lfsr_length 4 +#define lfsr_en 0 +#define dft_clk_sel 4 +#define tx_dft_en 0 +#define soc_test_sel 0 +#define tx_capture_pol 0 +#define freq_word_adj 0 +#define lrm 0 +#define data_padding_pat_1 0x55 +#define data_padding_pat_0 0xAA +#define gfsk_multiply_table_manual 0 +#define gfsk_mi 1 +#define gfsk_mld 0 +#define gfsk_fld 0 +#define gfsk_mod_index_scaling 0 +#define tx_image_filter_ovrd_en 0 +#define tx_image_filter_0_ovrd 0 +#define tx_image_filter_1_ovrd 0 +#define tx_image_filter_2_ovrd 0 +#define gfsk_filter_coeff_manual2 0xC0630401 +#define gfsk_filter_coeff_manual1 0xBB29960D +#define fsk_modulation_scale_0 0x1800 +#define fsk_modulation_scale_1 0x0800 +#define dft_mod_patternval 0 +#define ctune_bist_go 0 +#define ctune_bist_thrshld 0 +#define pa_am_mod_freq 0 +#define pa_am_mod_entries 0 +#define pa_am_mod_en 0 +#define syn_bist_go 0 +#define syn_bist_all_channels 0 +#define freq_count_threshold 0 +#define hpm_inl_bist_go 0 +#define hpm_dnl_bist_go 0 +#define dft_max_ram_size 0 + + .tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | + XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) | + XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) | + XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) | + XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj), +/*-------------------------------------------------------------------------------------------------*/ + .tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) | + XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) | + XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0), +/*-------------------------------------------------------------------------------------------------*/ + .tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval), +#if !RADIO_IS_GEN_2P1 +/*-------------------------------------------------------------------------------------------------*/ + .rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en), +/*-------------------------------------------------------------------------------------------------*/ + .rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) | + XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) | + XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size), +#endif /* !RADIO_IS_GEN_2P1 */ +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c new file mode 100644 index 0000000000000..8bb5e3637c8ed --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c @@ -0,0 +1,353 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x7BCDEB39, + .phy_pre_ref1_init = 0xCEF7DEF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xda) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */ + (164U) << 7 | /* coeff 6/9 */ + (125U) << 16 | /* coef 3/12 */ + (169U) << 23, /* coeff 7/8 */ + .tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */ + (90U) << 8 | /* coeff 1/14 */ + (141U) << 16 | /* coeff 4/11 */ + (155U) << 24, /* coeff 5/10 */ + .tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */ + (216U) << 7 | /* coeff 6/9 */ + (105U) << 16 | /* coef 3/12 */ + (233U) << 23, /* coeff 7/8 */ + .tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */ + (44U) << 8 | /* coeff 1/14 */ + (145U) << 16 | /* coeff 4/11 */ + (184U) << 24, /* coeff 5/10 */ +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1), + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c new file mode 100644 index 0000000000000..55366cf7498dd --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c @@ -0,0 +1,341 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0xBBDE739B, + .phy_pre_ref1_init = 0xDEFBDEF7, + .phy_pre_ref2_init = 0x0000E739, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xF0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0025, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0043, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x006B, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF6, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0044, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0064, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0077, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c new file mode 100644 index 0000000000000..d57d0696eb108 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c @@ -0,0 +1,356 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + .phy_pre_ref0_init = RW0PS(0, 0x19) | + RW0PS(1, 0x19U) | + RW0PS(2, 0x1AU) | + RW0PS(3, 0x1BU) | + RW0PS(4, 0x1CU) | + RW0PS(5, 0x1CU) | + RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ + .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1DU) | + RW1PS(11, 0x1CU) | + RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ + RW2PS(13, 0x1BU) | + RW2PS(14, 0x1AU) | + RW2PS(15, 0x19U), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(205) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* BLE 26MHz Channel Filter */ + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, + + /* BLE 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079, + + /* 32MHz */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c new file mode 100644 index 0000000000000..cc680b61014ea --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c @@ -0,0 +1,341 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x37ACE2F7, + .phy_pre_ref1_init = 0xADF3BDEF, + .phy_pre_ref2_init = 0x0000BE33, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xCD) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x000C, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003D, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008F, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFDF, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE3, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c new file mode 100644 index 0000000000000..49c6dc75c23d4 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c @@ -0,0 +1,340 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0xF38B5273, + .phy_pre_ref1_init = 0x8CEF9CE6, + .phy_pre_ref2_init = 0x00009D2D, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xb0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(3) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEB, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE9, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0008, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003A, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0090, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE1, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0034, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0021, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x0013, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFC9, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x005E, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFE1, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0034, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFB7, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x003B, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x004F, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFF5B, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0xFFB5, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x018B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x000C, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0011, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE0, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x000F, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0019, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x000C, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFCD, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFD7, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0017, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0075, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00BB, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c new file mode 100644 index 0000000000000..46f6c85086a9a --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c @@ -0,0 +1,353 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x79CDEB39, + .phy_pre_ref1_init = 0xCE77DEF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xb0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */ + (276U) << 7 | /* Coeff 6/9 */ + (62U) << 16 | /* Coef 3/12 */ + (326U) << 23, /* Coeff 7/8 */ + .tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */ + (10U) << 8 | /* Coeff 1/14 */ + (121U) << 16 | /* Coeff 4/11 */ + (198U) << 24, /* Coeff 5/10 */ + .tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */ + (330U) << 7 | /* Coeff 6/9 */ + (7U) << 16 | /* Coef 3/12 */ + (510U) << 23, /* Coeff 7/8 */ + .tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */ + (0U) << 8 | /* Coeff 1/14 */ + (37U) << 16 | /* Coeff 4/11 */ + (138U) << 24, /* Coeff 5/10 */ +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c new file mode 100644 index 0000000000000..dcfc9574758fe --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c @@ -0,0 +1,212 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* ========================= DATA RATE ONLY settings ===============*/ +/*! + * @brief XCVR 1Mbps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_1mbps_config = +{ + .data_rate = DR_1MBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0xF) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x20) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(10) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(21), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(12) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(26), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(3) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(33) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(6), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(7), +}; + +/*! + * @brief XCVR 500K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_500kbps_config = +{ + .data_rate = DR_500KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x10), + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(36), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), +}; + +/*! + * @brief XCVR 250K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_250kbps_config = +{ + .data_rate = DR_250KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x4) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x8) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(4) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(34), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(20) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(42), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(13) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c new file mode 100644 index 0000000000000..44eb38c1f2494 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c @@ -0,0 +1,343 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t msk_mode_config = +{ + .radio_mode = MSK, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x79CDEB38, + .phy_pre_ref1_init = 0xCE77DFF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(208U) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + /* MSK 1MBPS channel filter @ 26MHz RF OSC */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, + + /* MSK 1MBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + /* MSK 500KBPS channel filter @ 26MHz RF OSC */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092, + + /* MSK 500KBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, + + /* MSK 250KBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c new file mode 100644 index 0000000000000..32faa8bf8e5a1 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -0,0 +1,1008 @@ +/* +* Copyright 2016-2017 NXP +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "cpu.h" +#include "fsl_xcvr.h" +#include "fsl_xcvr_trim.h" +#include "dbg_ram_capture.h" +#include + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a,b) \ +({ __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a < _b ? _a : _b; }) +#endif + +#if !defined(MAX) +#define MAX(a,b) \ +({ __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a > _b ? _a : _b; }) +#endif +/* @} */ + +/******************************************************************************* +* Prototypes +******************************************************************************/ +void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val); +float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ); + +/******************************************************************************* +* Variables +******************************************************************************/ +const int8_t TsettleCal = 10; +static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; +static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = +{ + 0, /* Baseline entry is first and not used in this table */ + -16, + +16, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4 +}; + +/******************************************************************************* + * Macros + ******************************************************************************/ +#define ISIGN(x) !((uint16_t)x & 0x8000) +#define ABS(x) ((x) > 0 ? (x) : -(x)) + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! ********************************************************************************* + * \brief This function performs a trim of the BBA DCOC DAC on the DUT + * + * \return status - 1 if passed, 0 if failed. + * + * \ingroup PublicAPIs + * + * \details + * Requires the RX to be warmed up before this function is called. + * + ***********************************************************************************/ +uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) +{ + uint8_t i; + float temp_mi = 0; + float temp_mq = 0; + float temp_pi = 0; + float temp_pq = 0; + float temp_step = 0; + uint8_t bbf_dacinit_i, bbf_dacinit_q; + + uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only. */ + uint32_t bbf_dcoc_step; + uint32_t bbf_dcoc_step_rcp; + TZAdcocstep_t tza_dcoc_step[11]; + uint8_t status = 0; + + /* Save register values. */ + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + + XcvrCalDelay(1000); + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore. */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore. */ + + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode. */ + XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(0); /* Turn OFF AGC */ + + XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) ; /* Set LNA Manual Gain */ + XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) ; /* Set BBA Manual Gain */ + + XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(0); /* Enable HW DC Calibration -- Disable for SW-DCOC */ + XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode. */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); + /* Set DCOC Tracking State. */ + XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(0); /* Disables DCOC Tracking when set to 0 */ + /* Apply Manual Gain. */ + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x02) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x00) ; + XcvrCalDelay(TsettleCal); + + dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Capture DC null setting. */ + + bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); + bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8; + + DC_Measure_short(I_CHANNEL, NOMINAL2); + DC_Measure_short(Q_CHANNEL, NOMINAL2); + + /* SWEEP Q CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(Q_CHANNEL, BBF_NEG); + + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(Q_CHANNEL, BBF_POS); + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */ + XcvrCalDelay(TsettleCal); + + /* SWEEP I CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(I_CHANNEL, BBF_NEG); + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(I_CHANNEL, BBF_POS); + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DACs to initial. */ + XcvrCalDelay(TsettleCal); + + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + + temp_step = (temp_mi+temp_pi + temp_mq+temp_pq) / 4; + + bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + { + bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + + /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */ + for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */ + { + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */ + switch(i){ + case TZA_STEP_N0: + temp_step = (bbf_dcoc_step >> 3U) / 3.6F; + break; + case TZA_STEP_N1: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); + break; + case TZA_STEP_N2: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); + break; + case TZA_STEP_N3: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); + break; + case TZA_STEP_N4: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); + break; + case TZA_STEP_N5: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); + break; + case TZA_STEP_N6: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16); + break; + case TZA_STEP_N7: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); + break; + case TZA_STEP_N8: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); + break; + case TZA_STEP_N9: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); + break; + case TZA_STEP_N10: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); + break; + default: + break; + } + + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + } + + /* Make the trims active. */ + XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp) ; + + status = 1; /* Success */ + } + else + { + status = 0; /* Failure */ + } + + /* Restore Registers. */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings. */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting. */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */ + + return status; +} + +/*! ********************************************************************************* + * \brief This function performs one point of the DC GAIN calibration process on the DUT + * + * \param[in] chan - whether the I or Q channel is being tested. + * \param[in] stage - whether the BBF or TZA gain stage is being tested. + * \param[in] dcoc_init_val - the value being set in the ***DCOC_INIT_* register by the parent. + * \param[in] ext_measmt - the external measurement (in milliVolts) captured by the parent after the ***DCOC_INIT_* register was setup. + * + * \ingroup PublicAPIs + * + * \details + * Relies on a static array to store each point of data for later processing in ::DC_GainCalc(). + * + ***********************************************************************************/ +void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) +{ + int16_t dc_meas_i = 0; + int16_t dc_meas_q = 0; + int16_t sum_dc_meas_i = 0; + int16_t sum_dc_meas_q = 0; + + { + int8_t i; + const int8_t iterations = 1; + sum_dc_meas_i = 0; + sum_dc_meas_q = 0; + + for (i = 0; i < iterations; i++) + { + rx_dc_sample_average(&dc_meas_i, &dc_meas_q); + sum_dc_meas_i = sum_dc_meas_i + dc_meas_i; + sum_dc_meas_q = sum_dc_meas_q + dc_meas_q; + } + sum_dc_meas_i = sum_dc_meas_i / iterations; + sum_dc_meas_q = sum_dc_meas_q / iterations; + } + + measurement_tbl2[chan][dcoc_init_val].step_value = sweep_step_values2[dcoc_init_val]; + + if (chan == I_CHANNEL) + { + measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_i; + } + else + { + measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q; + } +} + +/*! ********************************************************************************* + * \brief This function calculates one point of DC DAC step based on digital samples of I or Q. + * + * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement. + * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. + * + * \return result of the calculation, the measurement DCOC DAC step value for this measurement point. + * + ***********************************************************************************/ +float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ) +{ + static int16_t norm_dc_code; + static float dc_step; + + /* Normalize internal measurement */ + norm_dc_code = meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement; + dc_step = (float)(norm_dc_code) / (float)(meas_ptr->step_value); + dc_step = (dc_step < 0)? -dc_step: dc_step; + + return dc_step; +} + +/*! ********************************************************************************* + * \brief Temporary delay function + * + * \param[in] none. + * + * \return none. + * + * \details + * + ***********************************************************************************/ +void XcvrCalDelay(uint32_t time) +{ + while(time * 32 > 0) /* Time delay is roughly in uSec. */ + { + time--; + } +} + +/*! ********************************************************************************* + * \brief This function calculates the average (DC value) based on a smaller set of digital samples of I and Q. + * + * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. + * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. + * + ***********************************************************************************/ +void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) +{ + static uint32_t samples[128]; /* 544*2*2 (entire packet ram1/2 size) */ + uint16_t i; + uint32_t rx_sample; + uint16_t * sample_ptr; + uint32_t temp, end_of_rx_wu; + uint32_t num_iq_samples; + float avg_i = 0; + float avg_q = 0; + + num_iq_samples = 128; + + /* Clear the entire allocated sample buffer */ + for (i = 0; i < num_iq_samples; i++) + { + samples[i]=0; + } + + /* Assume this has been called *AFTER* RxWu has completed. */ + /* XCVR_ForceRxWu(); */ + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + dbg_ram_init(); + /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ +#if RADIO_IS_GEN_3P0 + dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); + dbg_ram_wait_for_complete(); + dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); + dbg_ram_release(); +#else + (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); +#endif /* RADIO_IS_GEN_3P0 */ + + /* Sign extend the IQ samples in place in the sample buffer. */ + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i++) + { + rx_sample = *sample_ptr; + rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + *sample_ptr = rx_sample; + sample_ptr++; + } + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i += 2) + { + static int16_t i_value; + static int16_t q_value; + + /* Average I & Q channels separately. */ + i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits. */ + q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits. */ + avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ + avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ + } + XcvrCalDelay(10); + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * \brief This function calculates the average (DC value) based on a larger set of digital samples of I and Q. + * + * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. + * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. + * + ***********************************************************************************/ +void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) +{ + static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */ + uint16_t i; + uint32_t rx_sample; + uint16_t * sample_ptr; + uint32_t temp, end_of_rx_wu; + uint32_t num_iq_samples; + float avg_i = 0; + float avg_q = 0; + + num_iq_samples = 512; + + /* Clear the entire allocated sample buffer. */ + for (i = 0; i < num_iq_samples; i++) + { + samples[i]=0; + } + + /* Assume this has been called *AFTER* RxWu has completed. */ + /* XCVR_ForceRxWu(); */ + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + dbg_ram_init(); + /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ +#if RADIO_IS_GEN_3P0 + dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); + dbg_ram_wait_for_complete(); + dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ,num_iq_samples * 2 * 2, &samples[0]); + dbg_ram_release(); +#else + (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); +#endif /* RADIO_IS_GEN_3P0 */ + + /* Sign extend the IQ samples in place in the sample buffer. */ + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i++) + { + rx_sample = *sample_ptr; + rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + *sample_ptr = rx_sample; + sample_ptr++; + } + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i += 2) + { + static int16_t i_value; + static int16_t q_value; + + /* Average I & Q channels separately. */ + i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits */ + q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits */ + avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ + avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ + } + + XcvrCalDelay(10); + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * rx_dc_est_average : Get DC EST values and return the Average + ***********************************************************************************/ +void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber) +{ + float avg_i = 0; + float avg_q = 0; + uint16_t i = 0; + static uint32_t dc_temp, temp; + uint32_t end_of_rx_wu = 0; + static int16_t dc_meas_i; + static int16_t dc_meas_q; + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + /* Read DCOC DC EST register. */ + for (i = 0; i < SampleNumber; i++) + { + dc_temp = XCVR_RX_DIG->DCOC_DC_EST; + dc_meas_i = dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK; + temp = dc_meas_i; + temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_i = temp; + avg_i += (float) dc_meas_i; + + dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; + temp = dc_meas_q; + temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_q = temp; + avg_q += (float) dc_meas_q; + } + + avg_i /= (float) SampleNumber; + avg_q /= (float) SampleNumber; + + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * \brief This function performs a trim of the BBA DCOC DAC on the DUT + * + * \return status - 1 if passed, 0 if failed. + * + * \ingroup PublicAPIs + * + * \details + * Requires the RX to be warmed up before this function is called. + * + ***********************************************************************************/ +uint8_t rx_bba_dcoc_dac_trim_DCest(void) +{ + uint8_t i; + float temp_mi = 0; + float temp_mq = 0; + float temp_pi = 0; + float temp_pq = 0; + float temp_step = 0; + + uint32_t bbf_dcoc_step; + uint32_t bbf_dcoc_step_rcp; + TZAdcocstep_t tza_dcoc_step[11]; + uint8_t status = 0; + + uint8_t bbf_dacinit_i, bbf_dacinit_q; + uint8_t tza_dacinit_i, tza_dacinit_q; + int16_t dc_meas_i; + int16_t dc_meas_q; + uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only */ + uint32_t temp; + + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + + /* Save register */ + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + temp = XCVR_RX_DIG->RX_DIG_CTRL; + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); + + XcvrCalDelay(TsettleCal); + + /* Set default DCOC DAC INIT Value */ + dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ + bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); + bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8; + tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16; + tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; + + XcvrCalDelay(TsettleCal * 4); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; + measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; + measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][NOMINAL2].internal_measurement = dc_meas_q; + + /* SWEEP I/Q CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 2); + + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16; + measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16; + measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][BBF_NEG].internal_measurement = dc_meas_q; + + + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16; + measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16; + measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][BBF_POS].internal_measurement = dc_meas_q; + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ + + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + + temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; + bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + { + bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + + /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ + for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) + { + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ + switch(i){ + case TZA_STEP_N0: + temp_step = (bbf_dcoc_step>>3U) / 3.6F; + break; + case TZA_STEP_N1: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16); + break; + case TZA_STEP_N2: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16); + break; + case TZA_STEP_N3: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16); + break; + case TZA_STEP_N4: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16); + break; + case TZA_STEP_N5: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16); + break; + case TZA_STEP_N6: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16); + break; + case TZA_STEP_N7: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16); + break; + case TZA_STEP_N8: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16); + break; + case TZA_STEP_N9: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16); + break; + case TZA_STEP_N10: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16); + break; + default: + break; + } + + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + } + + /* Make the trims active */ + XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp); + + status = 1; /* Success */ + } + else + { + status = 0; /* Failure */ + } + + /* Restore Registers */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ + + return status; +} + +/*! ********************************************************************************* + * DCOC_DAC_INIT_Cal : slope sign seek depending on measure's sign + ***********************************************************************************/ +void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) +{ + int16_t dc_meas_i = 2000, dc_meas_i_p = 2000; + int16_t dc_meas_q = 2000, dc_meas_q_p = 2000; + uint8_t curr_tza_dac_i, curr_tza_dac_q; + uint8_t curr_bba_dac_i, curr_bba_dac_q; + uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0; + uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0; + uint8_t i = 0; + uint8_t bba_gain = 11; + bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; + + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + uint32_t xcvr_ctrl_stack = 0; + + uint32_t temp; + + /* Save registers */ + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* WarmUp */ + if (standalone_operation) + { + temp = XCVR_MISC->XCVR_CTRL; + xcvr_ctrl_stack = temp; + temp &= ~(XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK); + temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(0); + XCVR_MISC->XCVR_CTRL = temp; + XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */ + XCVR_ForceRxWu(); + XcvrCalDelay(2000); + } + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + temp = XCVR_RX_DIG->RX_DIG_CTRL; + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + + XcvrCalDelay(TsettleCal); + + /* Set default DCOC DAC INIT Value */ + /* LNA and BBA DAC Sweep */ + curr_bba_dac_i = 0x20; + curr_bba_dac_q = 0x20; + curr_tza_dac_i = 0x80; + curr_tza_dac_q = 0x80; + + /* Perform a first DC measurement to ensure that measurement is not clipping */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + do + { + bba_gain--; + /* Set DAC user gain */ + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900)); + + for (i = 0; i < 0x0F; i++) + { + /* I channel : */ + if (!TZA_I_OK) + { + if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0)) + { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) + { + curr_tza_dac_i = p_tza_dac_i; + } + + TZA_I_OK = 1; + } + else + { + p_tza_dac_i = curr_tza_dac_i; + + if (ISIGN(dc_meas_i)) /* If positif */ + { + curr_tza_dac_i--; + } + else + { + curr_tza_dac_i++; + } + } + } + else /* Sweep BBA I */ + { + if (!BBA_I_OK) + { + if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20)) + { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) + { + curr_bba_dac_i = p_bba_dac_i; + } + + BBA_I_OK = 1; + } + else + { + p_bba_dac_i = curr_bba_dac_i; + if (ISIGN(dc_meas_i)) /* If positif */ + { + curr_bba_dac_i--; + } + else + { + curr_bba_dac_i++; + } + } + } + } + + /* Q channel : */ + if (!TZA_Q_OK) + { + if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0)) + { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) + { + curr_tza_dac_q = p_tza_dac_q; + } + TZA_Q_OK = 1; + } + else + { + p_tza_dac_q = curr_tza_dac_q; + if (ISIGN(dc_meas_q)) /* If positif */ + { + curr_tza_dac_q--; + } + else + { + curr_tza_dac_q++; + } + } + } + else /* Sweep BBA Q */ + { + if (!BBA_Q_OK) + { + if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20)) + { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) + { + curr_bba_dac_q = p_bba_dac_q; + } + BBA_Q_OK = 1; + } + else + { + p_bba_dac_q = curr_bba_dac_q; + if (ISIGN(dc_meas_q)) /* If positif */ + { + curr_bba_dac_q--; + } + else + { + curr_bba_dac_q++; + } + } + } + } + + /* DC OK break : */ + if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK) + { + break; + } + + dc_meas_i_p = dc_meas_i; /* Store as previous value */ + dc_meas_q_p = dc_meas_q; /* Store as previous value */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + } + + /* Apply optimized DCOC DAC INIT : */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + /* WarmDown */ + if (standalone_operation) + { + XCVR_ForceRxWd(); /* Don't leave the receiver running. */ + XcvrCalDelay(200); + XCVR_OverrideChannel(0xFF,1); /* Release channel overrides */ + XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack; + } + + /* Restore register */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ +} + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h new file mode 100644 index 0000000000000..eb68fb973ce13 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -0,0 +1,129 @@ +/* +* Copyright 2016-2017 NXP +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _FSL_XCVR_TRIM_H_ +/* Clang-format off. */ +#define _FSL_XCVR_TRIM_H_ +/* Clang-format on. */ + +#include +/*! +* @addtogroup xcvr +* @{ +*/ + +/*! @file*/ + +/************************************************************************************ +************************************************************************************* +* Public constant definitions +************************************************************************************* +************************************************************************************/ + +/************************************************************************************ +************************************************************************************* +* Public type definitions +************************************************************************************* +************************************************************************************/ + +/* \brief The enumerations used to define the I & Q channel selections. */ +typedef enum +{ + I_CHANNEL = 0, + Q_CHANNEL = 1, + NUM_I_Q_CHAN = 2 +} IQ_t; + +typedef enum /* Enumeration of ADC_GAIN_CAL 2 */ +{ + NOMINAL2 = 0, + BBF_NEG = 1, + BBF_POS = 2, + TZA_STEP_N0 = 3, + TZA_STEP_N1 = 4, + TZA_STEP_N2 = 5, + TZA_STEP_N3 = 6, + TZA_STEP_N4 = 7, + TZA_STEP_N5 = 8, + TZA_STEP_N6 = 9, + TZA_STEP_N7 = 10, + TZA_STEP_N8 = 11, + TZA_STEP_N9 = 12, + TZA_STEP_N10 = 13, + TZA_STEP_P0 = 14, + TZA_STEP_P1 = 15, + TZA_STEP_P2 = 16, + TZA_STEP_P3 = 17, + TZA_STEP_P4 = 18, + TZA_STEP_P5 = 19, + TZA_STEP_P6 = 20, + TZA_STEP_P7 = 21, + TZA_STEP_P8 = 22, + TZA_STEP_P9 = 23, + TZA_STEP_P10 = 24, + + NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */ +} DAC_SWEEP_STEP2_t; + +/* \brief Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */ +typedef struct +{ + uint16_t dcoc_step; + uint16_t dcoc_step_rcp; +// uint16_t dcoc_step_q; +// uint16_t dcoc_step_rcp_q; +} TZAdcocstep_t; + +typedef struct +{ + int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */ + int16_t internal_measurement; /* The value (average code) measured from DMA samples. */ +// uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */ +} GAIN_CALC_TBL_ENTRY2_T; + +/******************************************************************************* +* Definitions +******************************************************************************/ +void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg); +void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg); +uint8_t rx_bba_dcoc_dac_trim_shortIQ(void); +void XcvrCalDelay(uint32_t time); +void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber); +uint8_t rx_bba_dcoc_dac_trim_DCest(void); +void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_XCVR_TRIM_H_ */ + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c new file mode 100644 index 0000000000000..47d6f5f0573c7 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t zgbe_mode_config = +{ + .radio_mode = ZIGBEE_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x0, /* Not used in Zigbee */ + .phy_pre_ref1_init = 0x0, /* Not used in Zigbee */ + .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */ + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xC0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_PLL_DIG configs */ + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ +#else + .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) , + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config = +{ + .radio_mode = ZIGBEE_MODE, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2, + + /* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +/* CUSTOM datarate dependent config structure for ONLY 802.15.4 */ +/*! + * @brief XCVR 500K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config = +{ + .data_rate = DR_500KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | + XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | + XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0), +}; + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c new file mode 100644 index 0000000000000..2732fd19dadb0 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.c @@ -0,0 +1,530 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "cpu.h" +#include "fsl_xcvr.h" +#include "ifr_radio.h" +#include "fsl_os_abstraction.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define IFR_RAM (0) + +#if RADIO_IS_GEN_3P0 +#define RDINDX (0x41U) +#define K3_BASE_INDEX (0x11U) /* Based for read index */ +#else +#define RDRSRC (0x03U) +#define KW4x_512_BASE (0x20000U) +#define KW4x_256_BASE (0x10000U) +#endif /* RADIO_IS_GEN_3P0 */ + +#if RADIO_IS_GEN_2P1 +#define FTFA (FTFE) +#endif /* RADIO_IS_GEN_2P1 */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +uint32_t read_another_ifr_word(void); +uint32_t read_first_ifr_word(uint32_t read_addr); + +#if RADIO_IS_GEN_3P0 +uint64_t read_index_ifr(uint32_t read_addr); +#else +/*! ********************************************************************************* + * @brief Reads a location in block 1 IFR for use by the radio. + * + * This function handles reading IFR data from flash memory for trim loading. + * + * @param read_addr the address in the IFR to be read. + * + * @details This function wraps both the Gen2 read_resource command and the Gen2.1 and Gen3 read_index +***********************************************************************************/ +#if RADIO_IS_GEN_2P1 +uint64_t read_resource_ifr(uint32_t read_addr); +#else +uint32_t read_resource_ifr(uint32_t read_addr); +#endif /* RADIO_IS_GEN_2P1 */ +#endif /* RADIO_IS_GEN_3P0 */ + +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t ifr_read_addr; + +#if RADIO_IS_GEN_3P0 +static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ +static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + /* Trim table is empty for Gen3 by default */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#else +#if RADIO_IS_GEN_2P0 +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + 0x4005912CU, /* RSIM_ANA_TRIM address */ + 0x784B0000U, /* RSIM_ANA_TRIM default value */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#else +static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ +static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + 0x4005912CU, /* RSIM_ANA_TRIM address */ + 0x784B0000U, /* RSIM_ANA_TRIM default value */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#endif /* RADIO_IS_GEN_2P0 */ +#endif /* RADIO_IS_GEN_3P0 */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! ********************************************************************************* + * \brief Read command for reading the first 32bit word from IFR, encapsulates different + * flash IFR read mechanisms for multiple generations of SOC + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * +***********************************************************************************/ +uint32_t read_first_ifr_word(uint32_t read_addr) +{ + ifr_read_addr = read_addr; + return read_another_ifr_word(); +} + +/*! ********************************************************************************* + * \brief Read command for reading additional 32bit words from IFR. Encapsulates multiple IFR read mechanisms. + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * + * \remarks PRE-CONDITIONS: + * The function read_first_ifr_word() must have been called so that the ifr_read_addr variable is setup prior to use. + * +***********************************************************************************/ +uint32_t read_another_ifr_word(void) +{ + uint32_t packed_data; + +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + /* Using some static storage and alternating reads to read_index_ifr to replace read_resource_ifr */ + if (num_words_avail == 0) + { +#if RADIO_IS_GEN_3P0 + packed_data_long = read_index_ifr(ifr_read_addr); +#else /* Use 64 bit return version of read_resource */ + packed_data_long = read_resource_ifr(ifr_read_addr); +#endif /* RADIO_IS_GEN_3P0 */ + + num_words_avail = 2; + ifr_read_addr++; /* Read index addresses increment by 1 */ + } + + packed_data = (uint32_t)(packed_data_long & 0xFFFFFFFF); + packed_data_long = packed_data_long >> 32; + num_words_avail--; +#else + packed_data = read_resource_ifr(ifr_read_addr); + ifr_read_addr += 4; /* Read resource addresses increment by 4 */ +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + + return packed_data; +} + +#if RADIO_IS_GEN_3P0 +/*! ********************************************************************************* + * \brief Read command for reading from IFR using RDINDEX command + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * +***********************************************************************************/ +uint64_t read_index_ifr(uint32_t read_addr) +{ + uint8_t rdindex = read_addr; + uint64_t read_data; + uint8_t i; + + while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */ + + if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) + { + FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */ + } + + FTFE->FCCOB[0] = RDINDX; + FTFE->FCCOB[1] = rdindex; + + OSA_InterrupDisable(); + FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; + while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Pack read data back into 64 bit type */ + read_data = FTFE->FCCOB[11]; /* MSB goes in first, will be shifted left sequentially */ + for (i = 10; i > 3; i--) + { + read_data = read_data << 8; + read_data |= FTFE->FCCOB[i]; + } + + return read_data; +} +#else + +/*! ********************************************************************************* + * \brief Read command for reading from IFR + * + * \param read_addr flash address + * + * \return packed data containing radio trims only + * +***********************************************************************************/ +#if RADIO_IS_GEN_2P0 +uint32_t read_resource_ifr(uint32_t read_addr) +{ + + uint32_t packed_data; + uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; + uint32_t read_data31_24, read_data23_16, read_data15_8, read_data7_0; + + flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); + flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); + flash_addr7_0 = (uint8_t)(read_addr & 0xFF); + + while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ + + if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK) == FTFA_FSTAT_ACCERR_MASK ) + { + FTFA->FSTAT = (1<FCCOB0 = RDRSRC; + FTFA->FCCOB1 = flash_addr23_16; + FTFA->FCCOB2 = flash_addr15_8; + FTFA->FCCOB3 = flash_addr7_0; + FTFA->FCCOB8 = 0x00; + + OSA_InterruptDisable(); + FTFA->FSTAT = FTFA_FSTAT_CCIF_MASK; + while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Start reading */ + read_data31_24 = FTFA->FCCOB4; /* FTFA->FCCOB[4] */ + read_data23_16 = FTFA->FCCOB5; /* FTFA->FCCOB[5] */ + read_data15_8 = FTFA->FCCOB6; /* FTFA->FCCOB[6] */ + read_data7_0 = FTFA->FCCOB7; /* FTFA->FCCOB[7] */ + + packed_data = (read_data31_24 << 24) | (read_data23_16 << 16) | (read_data15_8 << 8) | (read_data7_0 << 0); + + return packed_data; +} +#else +uint64_t read_resource_ifr(uint32_t read_addr) +{ + + uint64_t packed_data; + uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; + uint8_t read_data[8]; + uint64_t temp_64; + uint8_t i; + + flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); + flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); + flash_addr7_0 = (uint8_t)(read_addr & 0xFF); + while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + + if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) + { + FTFE->FSTAT = (1<FCCOB0 = RDRSRC; + FTFE->FCCOB1 = flash_addr23_16; + FTFE->FCCOB2 = flash_addr15_8; + FTFE->FCCOB3 = flash_addr7_0; + FTFE->FCCOB4 = 0x00; + + OSA_InterruptDisable(); + FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; + while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Start reading */ + read_data[7] = FTFE->FCCOB4; + read_data[6] = FTFE->FCCOB5; + read_data[5] = FTFE->FCCOB6; + read_data[4] = FTFE->FCCOB7; + read_data[3] = FTFE->FCCOB8; + read_data[2] = FTFE->FCCOB9; + read_data[1] = FTFE->FCCOBA; + read_data[0] = FTFE->FCCOBB; + + packed_data = 0; + for (i = 0; i < 8; i++) + { + temp_64 = read_data[i]; + packed_data |= temp_64 << (i * 8); + } + + return packed_data; +} + +#endif /* RADIO_IS_GEN_2P0 */ +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief Store a SW trim value in the table passed in from calling function. + * + * \param sw_trim_tbl pointer to the software trim table to hold SW trim values + * \param num_entries the number of entries in the SW trim table + * \param addr the software trim ID + * \param data the value of the software trim + * +***********************************************************************************/ +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data) +{ + uint16_t i; + + if (sw_trim_tbl != NULL) + { + for (i = 0; i < num_entries; i++) + { + if (addr == sw_trim_tbl[i].trim_id) + { + sw_trim_tbl[i].trim_value = data; + sw_trim_tbl[i].valid = 1; + break; /* Don't need to scan the array any further... */ + } + } + } +} + +/*! ********************************************************************************* + * \brief Process block 1 IFR data. + * + * \param sw_trim_tbl pointer to the software trim table to hold SW trim values + * \param num_entries the number of entries in the SW trim table + * + * \remarks + * Uses a IFR v2 formatted default array if the IFR is blank or corrupted. + * Stores SW trim values to an array passed into this function. + * +***********************************************************************************/ +void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries) +{ + uint32_t dest_addr; + uint32_t read_addr; + uint32_t dest_data; + uint32_t packed_data; + uint32_t *ifr_ptr; + +#if RADIO_IS_GEN_3P0 + num_words_avail = 0; /* Prep for handling 64 bit words from flash */ +#endif /* RADIO_IS_GEN_3P0 */ + +#if RADIO_IS_GEN_3P0 + read_addr = K3_BASE_INDEX; +#else +#ifdef CPU_MODEL_MKW41Z256VHT4 + read_addr = KW4x_256_BASE; +#else + read_addr = KW4x_512_BASE; +#endif /* CPU_MODEL_MKW41Z256VHT4 */ +#endif /* RADIO_IS_GEN_3P0 */ + + /* Read first entry in IFR table */ + packed_data = read_first_ifr_word(read_addr); + if ((packed_data&~IFR_VERSION_MASK) == IFR_VERSION_HDR) + { + /* Valid header was found, process real IFR data */ + XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); + store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array*/ + packed_data = read_another_ifr_word(); + + while (packed_data !=IFR_EOF_SYMBOL) + { + if (IS_A_SW_ID(packed_data)) /* SW Trim case (non_reg writes) */ + { + dest_addr = packed_data; + packed_data = read_another_ifr_word(); + dest_data = packed_data; + /* Place SW trim in array for driver SW to use */ + store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); + } + else + { + if (IS_VALID_REG_ADDR(packed_data)) /* Valid register write address */ + { + dest_addr = packed_data; + packed_data = read_another_ifr_word(); + dest_data = packed_data; + *(uint32_t *)(dest_addr) = dest_data; + } + else + { /* Invalid address case */ + + } + } + + packed_data=read_another_ifr_word(); + } + } + else + { + /* Valid header is not present, use blind IFR trim table */ + ifr_ptr = (void *)BLOCK_1_IFR; + packed_data = *ifr_ptr; + XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); + store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array */ + ifr_ptr++; + packed_data= *ifr_ptr; + + while (packed_data != IFR_EOF_SYMBOL) + { + if (IS_A_SW_ID(packed_data)) + { + /* SW Trim case (non_reg writes) */ + dest_addr = packed_data; + ifr_ptr++; + packed_data = *(ifr_ptr); + dest_data = packed_data; + /* Place SW trim in array for driver SW to use */ + store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); + } + else + { + dest_addr = packed_data; + ifr_ptr++; + packed_data = *ifr_ptr; + dest_data = packed_data; + + /* Valid register write address */ + if (IS_VALID_REG_ADDR(dest_addr)) + { + *(uint32_t *)(dest_addr) = dest_data; + } + else + { + /* Invalid address case */ + } + } + + ifr_ptr++; + packed_data= *ifr_ptr; + } + } +} + +#if RADIO_IS_GEN_3P0 + +#else +uint32_t handle_ifr_die_id(void) +{ + uint32_t id_x, id_y; + uint32_t id; + + id = read_resource_ifr(0x90); + id_x = id & 0x00FF0000; + id_y = id & 0x000000FF; + + return (id_x | id_y); +} + +uint32_t handle_ifr_die_kw_type(void) +{ + uint32_t zb, ble; + + zb = read_resource_ifr(0x80) & 0x8000; + ble= read_resource_ifr(0x88) & 0x100000; + + return (zb | ble); +} + +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief Dumps block 1 IFR data to an array. + * + * \param dump_tbl pointer to the table to hold the dumped IFR values + * \param num_entries the number of entries to dump + * + * \remarks + * Starts at the first address in IFR and dumps sequential entries. + * +***********************************************************************************/ +void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries) +{ +#if RADIO_IS_GEN_3P0 + uint32_t ifr_address = 0x20000; +#else + uint32_t ifr_address = 0x20000; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t * dump_ptr = dump_tbl; + uint8_t i; + + *dump_ptr = read_first_ifr_word(ifr_address); + dump_ptr++; + + for (i = 0; i < num_entries - 1; i++) + { + *dump_ptr = read_another_ifr_word(); + dump_ptr++; + } +} + diff --git a/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h new file mode 100644 index 0000000000000..96973de715035 --- /dev/null +++ b/cpu/kw41z/vendor/XCVR/MKW41Z4/ifr_radio.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __IFR_RADIO_H__ +/* clang-format off */ +#define __IFR_RADIO_H__ +/* clang-format on */ + +#include +/* clang-format off */ +#define _FSL_XCVR_H_ +/* clang-format on */ + +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define IFR_EOF_SYMBOL (0xFEED0E0FU) /* < Denotes the "End of File" for IFR data */ +#define IFR_VERSION_HDR (0xABCD0000U) /* < Constant value for upper 16 bits of IFR data header */ +#define IFR_VERSION_MASK (0x0000FFFFU) /* < Mask for version number (lower 16 bits) of IFR data header */ +#define IFR_SW_ID_MIN (0x00000000U) /* < Lower limit of SW trim IDs */ +#define IFR_SW_ID_MAX (0x0000FFFFU) /* < Lower limit of SW trim IDs */ + +#define IS_A_SW_ID(x) ((IFR_SW_ID_MIN < (x)) && (IFR_SW_ID_MAX >= (x))) + +/* K3 valid registers support */ +#if (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) +#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x41000000U) /* Valid addresses are 0x410xxxxx */ +#endif /* (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) */ +/* KW41 and KW35/36 valid registers support */ +#if (defined(CPU_MODEL_MKW41Z256VHT4) || defined(CPU_MODEL_MKW41Z512VHT4) || \ + defined(CPU_MODEL_MKW31Z256VHT4) || defined(CPU_MODEL_MKW31Z512VHT4) || \ + defined(CPU_MODEL_MKW21Z256VHT4) || defined(CPU_MODEL_MKW21Z512VHT4) || \ + defined(CPU_MODEL_MKW35A512VFP4) || defined(CPU_MODEL_MKW36A512VFP4) ) + +#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x40050000U) /* Valid addresses are 0x4005xxxx */ +#endif + +#define MAKE_MASK(size) ((1 << (size)) - 1) +#define MAKE_MASKSHFT(size, bitpos) (MAKE_MASK(size) << (bitpos)) + +#define IFR_TZA_CAP_TUNE_MASK (0x0000000FU) +#define IFR_TZA_CAP_TUNE_SHIFT (0) +#define IFR_BBF_CAP_TUNE_MASK (0x000F0000U) +#define IFR_BBF_CAP_TUNE_SHIFT (16) +#define IFR_RES_TUNE2_MASK (0x00F00000U) +#define IFR_RES_TUNE2_SHIFT (20) + +/* \var typedef uint8_t IFR_ERROR_T */ +/* \brief The IFR error reporting type. */ +/* See #IFR_ERROR_T_enum for the enumeration definitions. */ +typedef uint8_t IFR_ERROR_T; + +/* \brief The enumerations used to describe IFR errors. */ +enum IFR_ERROR_T_enum +{ + IFR_SUCCESS = 0, + INVALID_POINTER = 1, /* < NULL pointer error */ + INVALID_DEST_SIZE_SHIFT = 2, /* < the bits won't fit as specified in the destination */ +}; + +/* \var typedef uint16_t SW_TRIM_ID_T */ +/* \brief The SW trim ID type. */ +/* See #SW_TRIM_ID_T_enum for the enumeration definitions. */ +typedef uint16_t SW_TRIM_ID_T; + +/* \brief The enumerations used to define SW trim IDs. */ +enum SW_TRIM_ID_T_enum +{ + Q_RELATIVE_GAIN_BY_PART = 0, /* < Q vs I relative gain trim ID */ + ADC_GAIN = 1, /* < ADC gain trim ID */ + ZB_FILT_TRIM = 2, /* < Baseband Bandwidth filter trim ID for BLE */ + BLE_FILT_TRIM = 3, /* < Baseband Bandwidth filter trim ID for BLE */ + TRIM_STATUS = 4, /* < Status result of the trim process (error indications) */ + TRIM_VERSION = 0xABCD, /* < Version number of the IFR trim algorithm/format. */ +}; + +/* \var typedef uint32_t IFR_TRIM_STATUS_T */ +/* \brief The definition of failure bits stored in IFR trim status word. */ +/* See #IFR_TRIM_STATUS_T_enum for the enumeration definitions. */ +typedef uint32_t IFR_TRIM_STATUS_T; + +/* \brief The enumerations used to describe trim algorithm failures in the status entry in IFR. */ +/* This enum represents multiple values which can be OR'd together in a single status word. */ +enum IFR_TRIM_STATUS_T_enum +{ + TRIM_ALGORITHM_SUCCESS = 0, + BGAP_VOLTAGE_TRIM_FAILED = 1, /* < algorithm failure in BGAP voltagetrim */ + IQMC_GAIN_ADJ_FAILED = 2, /* < algorithm failure in IQMC gain trim */ + IQMC_PHASE_ADJ_FAILED = 4, /* < algorithm failure in IQMC phase trim */ + IQMC_DC_GAIN_ADJ_FAILED = 8, /* < */ + ADC_GAIN_TRIM_FAILED = 10, /* <*/ + ZB_FILT_TRIM_FAILED = 20, /* < */ + BLE_FILT_TRIM_FAILED = 40, /* < */ +}; + +/* \var typedef struct IFR_SW_TRIM_TBL_ENTRY_T */ +/* \brief Structure defining an entry in a table used to contain values to be passed back from IFR */ +/* handling routine to XCVR driver software. */ +typedef struct +{ + SW_TRIM_ID_T trim_id; /* < The assigned ID */ + uint32_t trim_value; /* < The value fetched from IFR.*/ + uint8_t valid; /* < validity of the trim_value field after IFR processing is complete (TRUE/FALSE).*/ +} IFR_SW_TRIM_TBL_ENTRY_T; + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief Reads a location in block 1 IFR for use by the radio. + * + * This function handles reading IFR data from flash memory for trim loading. + * + * @param read_addr the address in the IFR to be read. + */ +uint32_t read_resource_ifr(uint32_t read_addr); + +/*! + * @brief Reads a location in a simulated data array to support IFR handler testing. + * + * This function handles reading data from a const table for testing the trim loading functions. + * + * @param read_addr the address in the IFR to be read. + */ +uint32_t read_resource(uint16_t resource_id); + +/*! + * @brief Main IFR handler function called by XCVR driver software to process trim table. + * + * This function handles reading data from IFR and either loading to registers or storing to a SW trim values table. + * + * @param sw_trim_tbl pointer to the table used to store software trim values. + * @param num_entries the number of entries that can be stored in the SW trim table. + */ +void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries); + +/*! + * @brief Handler function to read die_id from IFR locations.. + * + * This function handles reading die ID value for debug and testing usage. + * + * @return the value of the die ID field. + */ +uint32_t handle_ifr_die_id(void); + +/*! + * @brief Handler function to read KW chip version from IFR locations.. + * + * This function handles reading KW chip version for debug and testing usage. + * + * @return the value of the KW version field. + */ +uint32_t handle_ifr_die_kw_type(void); + +/*! + * @brief Debug function to dump the IFR contents to a RAM array. + * + * This function handles reading data from IFR and storing to a RAM array for debug. + * + * @param dump_tbl pointer to the table used to store IFR entry values. + * @param num_entries the number of entries that can be stored in the dump table. + */ +void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries); + +#endif /*__IFR_RADIO_H__ */ + diff --git a/drivers/Makefile.dep b/drivers/Makefile.dep index 4813af1e70c93..a49a99b632e63 100644 --- a/drivers/Makefile.dep +++ b/drivers/Makefile.dep @@ -129,6 +129,18 @@ ifneq (,$(filter kw2xrf,$(USEMODULE))) endif endif +ifneq (,$(filter kw41zrf,$(USEMODULE))) + USEMODULE += luid + USEMODULE += netif + USEMODULE += ieee802154 + USEMODULE += netdev_ieee802154 + ifneq (,$(filter gnrc_netdev_default,$(USEMODULE))) + # XXX: this can be modeled as a dependency for gnrc_netdev_default as soon + # as all drivers are ported to netdev + USEMODULE += gnrc_netdev + endif +endif + ifneq (,$(filter hd44780,$(USEMODULE))) FEATURES_REQUIRED += periph_gpio USEMODULE += xtimer diff --git a/drivers/Makefile.include b/drivers/Makefile.include index 5ad17a4c32560..77067ecb1f9f8 100644 --- a/drivers/Makefile.include +++ b/drivers/Makefile.include @@ -13,6 +13,9 @@ endif ifneq (,$(filter kw2xrf,$(USEMODULE))) USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw2xrf/include endif +ifneq (,$(filter kw41zrf,$(USEMODULE))) + USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw41zrf/include +endif ifneq (,$(filter io1_xplained,$(USEMODULE))) USEMODULE_INCLUDES += $(RIOTBASE)/drivers/io1_xplained/include endif diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h new file mode 100644 index 0000000000000..1ad58280e92f4 --- /dev/null +++ b/drivers/include/kw41zrf.h @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup drivers_kw41zrf KW41Z radio-driver + * @ingroup drivers_netdev + * @brief Device driver for the NXP KW41Z, KW21Z in-cpu transceiver + * @{ + * + * @file + * @brief Interface definition for the kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW41ZRF_H +#define KW41ZRF_H + +#include + +#include "board.h" +#include "periph/spi.h" +#include "periph/gpio.h" +#include "net/netdev.h" +#include "net/netdev/ieee802154.h" +#include "net/gnrc/nettype.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Maximum packet length + */ +#define KW41ZRF_MAX_PKT_LENGTH (IEEE802154_FRAME_LEN_MAX) + +/** + * @brief Default PAN ID used after initialization + */ +#define KW41ZRF_DEFAULT_PANID (IEEE802154_DEFAULT_PANID) + +/** + * @brief Default channel used after initialization + * + * @{ + */ +#ifndef KW41ZRF_DEFAULT_CHANNEL +#define KW41ZRF_DEFAULT_CHANNEL (IEEE802154_DEFAULT_CHANNEL) +#endif +/** @} */ + +/** + * @brief Allowed range of channels + * + * @{ + */ +#define KW41ZRF_MIN_CHANNEL (11U) +#define KW41ZRF_MAX_CHANNEL (26U) +/** @} */ + +/** + * @brief Default TX_POWER in dbm used after initialization + */ +#define KW41ZRF_DEFAULT_TX_POWER (IEEE802154_DEFAULT_TXPOWER) + +/** + * @brief Maximum output power of the kw41z device in dBm + */ +#define KW41ZRF_OUTPUT_POWER_MAX (2) + +/** + * @brief Minimum output power of the kw41z device in dBm + */ +#define KW41ZRF_OUTPUT_POWER_MIN (-19) + +/** + * @brief Internal device option flags + * + * `0x00ff` is reserved for general IEEE 802.15.4 flags + * (see @ref netdev_ieee802154_t) + * + * @{ + */ +#define KW41ZRF_OPT_SRC_ADDR_LONG (NETDEV_IEEE802154_SRC_MODE_LONG) /**< legacy define */ +#define KW41ZRF_OPT_RAWDUMP (NETDEV_IEEE802154_RAW) /**< legacy define */ +#define KW41ZRF_OPT_ACK_REQ (NETDEV_IEEE802154_ACK_REQ) /**< legacy define */ + +#define KW41ZRF_OPT_AUTOCCA (0x0100) /**< CCA before TX active */ +#define KW41ZRF_OPT_PROMISCUOUS (0x0200) /**< promiscuous mode active */ +#define KW41ZRF_OPT_PRELOADING (0x0400) /**< preloading enabled */ +#define KW41ZRF_OPT_TELL_TX_START (0x0800) /**< notify MAC layer on TX start */ +#define KW41ZRF_OPT_TELL_TX_END (0x1000) /**< notify MAC layer on TX finished */ +#define KW41ZRF_OPT_TELL_RX_START (0x2000) /**< notify MAC layer on RX start */ +#define KW41ZRF_OPT_TELL_RX_END (0x4000) /**< notify MAC layer on RX finished */ +#define KW41ZRF_OPT_AUTOACK (0x8000) /**< enable automatic sending of + * ACKs for incoming packet */ +/** @} */ + +/** + * @brief Device descriptor for KW41ZRF radio devices + * + * @extends netdev_ieee802154_t + */ +typedef struct { + netdev_ieee802154_t netdev; /**< netdev parent struct */ + /** + * @brief device specific fields + * @{ + */ + uint32_t tx_warmup_time; /**< TX warmup time, in event timer ticks */ + uint32_t rx_warmup_time; /**< RX warmup time, in event timer ticks */ + int16_t tx_power; /**< The current tx-power setting of the device */ + uint8_t state; /**< current state of the radio */ + uint8_t idle_state; /**< state to return to after sending */ + /** @} */ +} kw41zrf_t; + +/** + * @brief Setup an KW41ZRF based device state + * + * @param[out] dev device descriptor + * @param[in] params parameters for device initialization + */ +void kw41zrf_setup(kw41zrf_t *dev); + +/** + * @brief Initialize the given KW41ZRF device + * + * @param[out] dev device descriptor + * @param[in] cb irq callback + * + * @return 0 on success + * @return <0 on error + */ +int kw41zrf_init(kw41zrf_t *dev, gpio_cb_t cb); + +/** + * @brief Configure radio with default values + * + * @param[in] dev device to reset + */ +void kw41zrf_reset_phy(kw41zrf_t *dev); + +#ifdef __cplusplus +} +#endif + +#endif /* KW41ZRF_H */ +/** @} */ diff --git a/drivers/kw41zrf/Makefile b/drivers/kw41zrf/Makefile new file mode 100644 index 0000000000000..48422e909a47d --- /dev/null +++ b/drivers/kw41zrf/Makefile @@ -0,0 +1 @@ +include $(RIOTBASE)/Makefile.base diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h new file mode 100644 index 0000000000000..dff93632a9d30 --- /dev/null +++ b/drivers/kw41zrf/include/kw41zrf_getset.h @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2017 SKF AB + * Copyright (C) 2016 Phytec Messtechnik GmbH + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief get/set interfaces for kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW41ZRF_GETSET_H +#define KW41ZRF_GETSET_H + +#include "kw41zrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Transceiver sequence identifiers */ +enum kw41zrf_xcvseq { + XCVSEQ_IDLE = 0b000, + XCVSEQ_RECEIVE = 0b001, + XCVSEQ_TRANSMIT = 0b010, + XCVSEQ_CCA = 0b011, + XCVSEQ_TX_RX = 0b100, + XCVSEQ_CONTINUOUS_CCA = 0b101, + /* Other values are reserved */ +}; + +/** + * @brief Set tx power of given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] txpower transmit power in dBm + */ +void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower); + +/** + * @brief Get tx power value of given device + * + * @param[in] dev kw41zrf device descriptor + * + * @return current tx power value + */ +uint16_t kw41zrf_get_txpower(kw41zrf_t *dev); + +/** + * @brief Set channel of given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] val channel + */ +int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t val); + +/** + * @brief Get channel of given device + * + * @param[in] dev kw41zrf device descriptor + * + * @return current channel + */ +uint8_t kw41zrf_get_channel(kw41zrf_t *dev); + +/** + * @brief Abort current sequence of device + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_abort_sequence(kw41zrf_t *dev); + +/** + * @brief Set idle sequence state of device + * + * @param[in] dev kw41zrf device descriptor + */ +// void kw41zrf_set_idle_sequence(kw41zrf_t *dev); + +/** + * @brief Set sequence state of device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] seq sequence + */ +void kw41zrf_set_sequence(kw41zrf_t *dev, uint8_t seq); + +/** + * @brief Set PAN ID of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] pan PAN ID value + */ +void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan); + +/** + * @brief Set short address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] addr short address + */ +void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr); + +/** + * @brief Set long address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] addr long address + */ +void kw41zrf_set_addr_long(kw41zrf_t *dev, uint64_t addr); + +/** + * @brief Get short address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current short address + */ +uint16_t kw41zrf_get_addr_short(kw41zrf_t *dev); + +/** + * @brief Get long address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current long address + */ +uint64_t kw41zrf_get_addr_long(kw41zrf_t *dev); + +/** + * @brief Get CCA threshhold of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current CCA threshhold + */ +int8_t kw41zrf_get_cca_threshold(kw41zrf_t *dev); + +/** + * @brief Set CCA threshold of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] value CCA threshold + */ +void kw41zrf_set_cca_threshold(kw41zrf_t *dev, int8_t value); + +/** + * @brief Set CCA mode of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] mode CCA mode + */ +void kw41zrf_set_cca_mode(kw41zrf_t *dev, uint8_t mode); + +/** + * @brief Get CCA mode of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current CCA mode + */ +uint8_t kw41zrf_get_cca_mode(kw41zrf_t *dev); + +/** + * @brief Get state of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current state + */ +netopt_state_t kw41zrf_get_status(kw41zrf_t *dev); + +/** + * @brief Enable continous CCA + * + * @param[in] dev kw41zrf device descriptor + * + * @return CCA value + */ +int kw41zrf_cca(kw41zrf_t *dev); + +/** + * @brief Set receive watermark + * + * @param[in] dev kw41zrf device descriptor + * @param[in] value watermark + */ +void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value); + +/** + * @brief Set netopt a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] option Netopt option type + * @param[in] state state + */ +void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* KW41ZRF_GETSET_H */ +/** @} */ diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h new file mode 100644 index 0000000000000..49657236ae7f7 --- /dev/null +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2017 SKF AB + * Copyright (C) 2016 Phytec Messtechnik GmbH + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief Internal function interfaces for kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW2XRF_INTERN_H +#define KW2XRF_INTERN_H + +#include +#include "kw41zrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief KW41Z transceiver power modes + */ +typedef enum { + KW41ZRF_POWER_IDLE = 0, /**< All parts powered */ + KW41ZRF_POWER_DSM, /**< Deep sleep mode */ +} kw41zrf_powermode_t; + +/** + * @brief Timebase settings + */ +typedef enum kw41zrf_timer_timebase { + KW41ZRF_TIMEBASE_500000HZ = 0b010, + KW41ZRF_TIMEBASE_250000HZ = 0b011, + KW41ZRF_TIMEBASE_125000HZ = 0b100, + KW41ZRF_TIMEBASE_62500HZ = 0b101, + KW41ZRF_TIMEBASE_31250HZ = 0b110, + KW41ZRF_TIMEBASE_15625HZ = 0b111, +} kw41zrf_timer_timebase_t; + +/** + * @brief Mask all transceiver interrupts + * + * @param[in] dev kw41zrf device descriptor + */ +static inline void kw41zrf_mask_irqs(void) +{ + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TRCV_MSK_SHIFT); +} + +/** + * @brief Allow transceiver interrupts + * + * @param[in] dev kw41zrf device descriptor + */ +static inline void kw41zrf_unmask_irqs(void) +{ + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TRCV_MSK_SHIFT); +} + +/** + * @brief Set the callback function for the radio ISR + * + * This callback will be called from ISR context when a radio_1 interrupt occurs + * + * @param[in] cb Pointer to callback function + * @param[in] arg Argument that will be passed to the callback + */ +void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg); + +/** + * @brief Disable all interrupts on transceiver + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_disable_interrupts(kw41zrf_t *dev); + +/** + * @brief Set power mode for device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] pm power mode value + */ +void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm); + +/** + * @brief + * + * @param[in] dev + * + * @return + */ +int kw41zrf_can_switch_to_idle(kw41zrf_t *dev); + +/** + * @brief Initialize the Event Timer Block (up counter) + * + * The Event Timer Block provides: + * - Abort an RX and CCA sequence at pre-determined time + * - Latches "timestamp" value during packet reception + * - Initiates timer-triggered sequences + * + * @param[in] dev kw41zrf device descriptor + * @param[in] tb timer base value + */ +void kw41zrf_timer_init(kw41zrf_t *dev, kw41zrf_timer_timebase_t tb); + +/** + * @brief Enable start sequence time + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_timer2_seq_start_on(kw41zrf_t *dev); + +/** + * @brief Disable start sequence timer + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_timer2_seq_start_off(kw41zrf_t *dev); + +/** + * @brief Enable abort sequence timer + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_timer3_seq_abort_on(kw41zrf_t *dev); + +/** + * @brief Disable abort sequence timer + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_timer3_seq_abort_off(kw41zrf_t *dev); + +/** + * @brief Use T2CMP or T2PRIMECMP to Trigger Transceiver Operations + * + * @param[in] dev kw41zrf device descriptor + * @param[in] timeout timeout value + */ +void kw41zrf_trigger_tx_ops_enable(kw41zrf_t *dev, uint32_t timeout); + +/** + * @brief Disable Trigger for Transceiver Operations + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_trigger_tx_ops_disable(kw41zrf_t *dev); + +/** + * @brief Use T3CMP to Abort an RX operation + * + * @param[in] dev kw41zrf device descriptor + * @param[in] timeout timeout value + */ +void kw41zrf_abort_rx_ops_enable(kw41zrf_t *dev, uint32_t timeout); + +/** + * @brief Disable Trigger to Abort an RX operation + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_abort_rx_ops_disable(kw41zrf_t *dev); + +/** + * @brief Returns Timestamp of the actual received packet + * + * @param[in] dev kw41zrf device descriptor + * + * @return timestamp value + */ +uint32_t kw41zrf_get_timestamp(kw41zrf_t *dev); + +#ifdef __cplusplus +} +#endif + +#endif /* KW2XRF_INTERN_H */ +/** @} */ diff --git a/drivers/kw41zrf/include/kw41zrf_netdev.h b/drivers/kw41zrf/include/kw41zrf_netdev.h new file mode 100644 index 0000000000000..59af06d740d10 --- /dev/null +++ b/drivers/kw41zrf/include/kw41zrf_netdev.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief Netdev interface for kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW41ZRF_NETDEV_H +#define KW41ZRF_NETDEV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reference to the netdev device driver struct + */ +extern const netdev_driver_t kw41zrf_driver; + +#ifdef __cplusplus +} +#endif + +#endif /* KW41ZRF_NETDEV_H */ +/** @} */ diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c new file mode 100644 index 0000000000000..c05cce2db4ca4 --- /dev/null +++ b/drivers/kw41zrf/kw41zrf.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * @file + * @brief Basic functionality of kw41zrf driver + * + * @author Joakim Nohlgård + * @} + */ +#include +#include + +#include "log.h" +#include "mutex.h" +#include "msg.h" +#include "net/gnrc.h" +#include "net/ieee802154.h" +#include "luid.h" + +#include "kw41zrf.h" +#include "kw41zrf_netdev.h" +#include "kw41zrf_getset.h" +#include "kw41zrf_intern.h" +#include "fsl_xcvr.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +enum { + KW41Z_CCA_ED, + KW41Z_CCA_MODE1, + KW41Z_CCA_MODE2, + KW41Z_CCA_MODE3 +}; + +enum { + KW41Z_STATE_IDLE, + KW41Z_STATE_RX, + KW41Z_STATE_TX, + KW41Z_STATE_CCA, + KW41Z_STATE_TXRX, + KW41Z_STATE_CCCA +}; + +static void kw41zrf_set_address(kw41zrf_t *dev) +{ + DEBUG("[kw41zrf] Set MAC address\n"); + eui64_t addr_long; + /* get an 8-byte unique ID to use as hardware address */ + luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN); + /* make sure we mark the address as non-multicast and not globally unique */ + addr_long.uint8[0] &= ~(0x01); + addr_long.uint8[0] |= (0x02); + /* set short and long address */ + kw41zrf_set_addr_long(dev, ntohll(addr_long.uint64.u64)); + kw41zrf_set_addr_short(dev, ntohs(addr_long.uint16[0].u16)); +} + +void kw41zrf_setup(kw41zrf_t *dev) +{ + netdev_t *netdev = (netdev_t *)dev; + + netdev->driver = &kw41zrf_driver; + /* initialize device descriptor */ + dev->idle_state = XCVSEQ_RECEIVE; + dev->state = 0; +// kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + DEBUG("[kw41zrf] setup finished\n"); +} + +int kw41zrf_init(kw41zrf_t *dev, gpio_cb_t cb) +{ + if (dev == NULL) { + return -ENODEV; + } + + xcvrStatus_t xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS); + if (xcvrStatus != gXcvrSuccess_c) { + return -EIO; + } + + /* Software reset of most settings */ + kw41zrf_reset_phy(dev); + + /* Compute warmup times (scaled to 16us) */ + dev->rx_warmup_time = + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + dev->tx_warmup_time = + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + + /* divide by 16 and round up */ + dev->rx_warmup_time = (dev->rx_warmup_time + 15) / 16; + dev->tx_warmup_time = (dev->tx_warmup_time + 15) / 16; + + /* Configre Radio IRQ */ + kw41zrf_set_irq_callback(cb, dev); + NVIC_ClearPendingIRQ(Radio_1_IRQn); + NVIC_EnableIRQ(Radio_1_IRQn); + + kw41zrf_abort_sequence(dev); + kw41zrf_unmask_irqs(); + + DEBUG("[kw41zrf] init finished\n"); + + return 0; +} + +void kw41zrf_reset_phy(kw41zrf_t *dev) +{ + /* reset options and sequence number */ + dev->netdev.seq = 0; + dev->netdev.flags = 0; + + /* set default protocol */ +#ifdef MODULE_GNRC_SIXLOWPAN + dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN; +#elif MODULE_GNRC + dev->netdev.proto = GNRC_NETTYPE_UNDEF; +#endif + + /* Reset PHY_CTRL to the default value of mask all interrupts and all other + * settings disabled */ + ZLL->PHY_CTRL = + ZLL_PHY_CTRL_CCATYPE(1) | + ZLL_PHY_CTRL_TSM_MSK_MASK | + ZLL_PHY_CTRL_WAKE_MSK_MASK | + ZLL_PHY_CTRL_CRC_MSK_MASK | + ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK | + ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK | + ZLL_PHY_CTRL_RX_WMRK_MSK_MASK | + ZLL_PHY_CTRL_CCAMSK_MASK | + ZLL_PHY_CTRL_RXMSK_MASK | + ZLL_PHY_CTRL_TXMSK_MASK | + ZLL_PHY_CTRL_SEQMSK_MASK; + + /* Clear and disable all interrupts */ + kw41zrf_disable_interrupts(dev); + + /* Clear source address cache */ + ZLL->SAM_TABLE |= ZLL_SAM_TABLE_INVALIDATE_ALL_MASK; + + /* Accept FrameVersion 0 and 1 packets, reject all others */ + ZLL->RX_FRAME_FILTER = ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(3) | + ZLL_RX_FRAME_FILTER_ACK_FT_MASK | + ZLL_RX_FRAME_FILTER_DATA_FT_MASK; + + /* Set prescaler to obtain 1 symbol (16us) timebase */ + kw41zrf_timer_init(dev, KW41ZRF_TIMEBASE_62500HZ); + + /* Set CCA threshold to -75 dBm */ + ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) | + ZLL_CCA_LQI_CTRL_CCA1_THRESH(0xB5); + + /* Adjust ACK delay to fulfill the 802.15.4 turnaround requirements */ + ZLL->ACKDELAY = (ZLL->ACKDELAY & ~ZLL_ACKDELAY_ACKDELAY_MASK) | ZLL_ACKDELAY_ACKDELAY(-8); + + /* Adjust LQI compensation */ + /* Hardware reset default is 102 */ + ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK) | + ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(96); + + dev->tx_power = KW41ZRF_DEFAULT_TX_POWER; + kw41zrf_set_tx_power(dev, dev->tx_power); + + kw41zrf_set_channel(dev, KW41ZRF_DEFAULT_CHANNEL); + + kw41zrf_set_pan(dev, KW41ZRF_DEFAULT_PANID); + kw41zrf_set_address(dev); + + kw41zrf_set_cca_mode(dev, 1); + + kw41zrf_set_rx_watermark(dev, 1); + + kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOCCA, true); + + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + kw41zrf_set_sequence(dev, dev->idle_state); + + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, true); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_SEQMSK_SHIFT); + + DEBUG("[kw41zrf] reset PHY and (re)set to channel %d and pan %d.\n", + KW41ZRF_DEFAULT_CHANNEL, KW41ZRF_DEFAULT_PANID); +} diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c new file mode 100644 index 0000000000000..a10d91239d36a --- /dev/null +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -0,0 +1,355 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * @file + * @brief get/set functionality of kw41zrf driver + * + * @author Joakim Nohlgård + * @} + */ + +#include +#include "log.h" +#include "cpu.h" +#include "byteorder.h" +#include "kw41zrf.h" +#include "kw41zrf_intern.h" +#include "kw41zrf_getset.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +#define KW41ZRF_NUM_CHANNEL (KW41ZRF_MAX_CHANNEL - KW41ZRF_MIN_CHANNEL + 1) + +/* Lookup table for PA_PWR register */ +static const uint8_t pa_pwr_lt[22] = { + 2, 2, 2, 2, 2, 2, /* -19:-14 dBm */ + 4, 4, 4, /* -13:-11 dBm */ + 6, 6, 6, /* -10:-8 dBm */ + 8, 8, /* -7:-6 dBm */ + 10, 10, /* -5:-4 dBm */ + 12, /* -3 dBm */ + 14, 14, /* -2:-1 dBm */ + 18, 18, /* 0:1 dBm */ + 24 /* 2 dBm */ +}; + +void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower_dbm) +{ + if (txpower_dbm < KW41ZRF_OUTPUT_POWER_MIN) { + ZLL->PA_PWR = 0; + } + else if (txpower_dbm > KW41ZRF_OUTPUT_POWER_MAX) { + ZLL->PA_PWR = 30; + } + else { + ZLL->PA_PWR = pa_pwr_lt[txpower_dbm - KW41ZRF_OUTPUT_POWER_MIN]; + } + + LOG_DEBUG("[kw41zrf] set txpower to: %d\n", txpower_dbm); + dev->tx_power = txpower_dbm; +} + +uint16_t kw41zrf_get_txpower(kw41zrf_t *dev) +{ + return dev->tx_power; +} + +uint8_t kw41zrf_get_channel(kw41zrf_t *dev) +{ + return (ZLL->CHANNEL_NUM0 & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK); +} + +int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t channel) +{ + if (channel < KW41ZRF_MIN_CHANNEL || channel > KW41ZRF_MAX_CHANNEL) { + LOG_ERROR("[kw41zrf] Invalid channel %u\n", channel); + return -EINVAL; + } + + ZLL->CHANNEL_NUM0 = channel; + dev->netdev.chan = channel; + + LOG_DEBUG("[kw41zrf] set channel to %u\n", channel); + return 0; +} + +inline void kw41zrf_abort_sequence(kw41zrf_t *dev) +{ + /* Writing IDLE to XCVSEQ aborts any ongoing sequence */ + ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_XCVSEQ_MASK) | ZLL_PHY_CTRL_XCVSEQ(XCVSEQ_IDLE); + /* Clear interrupt flags */ + ZLL->IRQSTS = ZLL->IRQSTS; +} + +void kw41zrf_set_sequence(kw41zrf_t *dev, uint8_t seq) +{ + kw41zrf_abort_sequence(dev); + + switch (seq) { + case XCVSEQ_IDLE: + case XCVSEQ_RECEIVE: + /* TODO why is RX == IDLE??? */ + dev->state = NETOPT_STATE_IDLE; + break; + + case XCVSEQ_CONTINUOUS_CCA: + case XCVSEQ_CCA: + dev->state = NETOPT_STATE_RX; + break; + + case XCVSEQ_TRANSMIT: + case XCVSEQ_TX_RX: + dev->state = NETOPT_STATE_TX; + break; + + default: + DEBUG("[kw41zrf] undefined state assigned to phy\n"); + dev->state = NETOPT_STATE_IDLE; + } + + DEBUG("[kw41zrf] set sequence to %u\n", (unsigned int)seq); + ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_XCVSEQ_MASK) | ZLL_PHY_CTRL_XCVSEQ(seq); + /* clear all IRQ flags */ + ZLL->IRQSTS = ZLL->IRQSTS; +} + +void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan) +{ + dev->netdev.pan = pan; + + ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACPANID0_MASK) | + ZLL_MACSHORTADDRS0_MACPANID0(pan); + + LOG_DEBUG("[kw41zrf] set pan to: 0x%x\n", pan); + dev->netdev.pan = pan; +} + +void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr) +{ +#ifdef MODULE_SIXLOWPAN + /* https://tools.ietf.org/html/rfc4944#section-12 requires the first bit to + * 0 for unicast addresses */ + addr &= 0x7fff; +#endif + /* Network byte order */ + /* TODO use byteorder.h */ + dev->netdev.short_addr[0] = (addr & 0xff); + dev->netdev.short_addr[1] = (addr >> 8); + ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) | + ZLL_MACSHORTADDRS0_MACSHORTADDRS0(addr); +} + +void kw41zrf_set_addr_long(kw41zrf_t *dev, uint64_t addr) +{ + (void) dev; + for (unsigned i = 0; i < IEEE802154_LONG_ADDRESS_LEN; i++) { + dev->netdev.long_addr[i] = (uint8_t)(addr >> (i * 8)); + } + /* Network byte order */ + addr = byteorder_swapll(addr); + ZLL->MACLONGADDRS0_LSB = (uint32_t)addr; + ZLL->MACLONGADDRS0_MSB = (addr >> 32); +} + +uint16_t kw41zrf_get_addr_short(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->MACSHORTADDRS0 & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) >> + ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT; +} + +uint64_t kw41zrf_get_addr_long(kw41zrf_t *dev) +{ + (void) dev; + uint64_t addr = ((uint64_t)ZLL->MACLONGADDRS0_MSB << 32) | ZLL->MACLONGADDRS0_LSB; + /* Network byte order */ + addr = byteorder_swapll(addr); + + return addr; +} + +int8_t kw41zrf_get_cca_threshold(kw41zrf_t *dev) +{ + (void) dev; + uint8_t tmp = (ZLL->CCA_LQI_CTRL & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK); + return (int8_t)tmp; +} + +void kw41zrf_set_cca_threshold(kw41zrf_t *dev, int8_t value) +{ + (void) dev; + ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) | + ZLL_CCA_LQI_CTRL_CCA1_THRESH(value); +} + +void kw41zrf_set_cca_mode(kw41zrf_t *dev, uint8_t mode) +{ + (void) dev; + ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_CCATYPE_MASK) | + ZLL_PHY_CTRL_CCATYPE(mode); +} + +uint8_t kw41zrf_get_cca_mode(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCATYPE_MASK) >> ZLL_PHY_CTRL_CCATYPE_SHIFT; +} + +void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) +{ + DEBUG("[kw41zrf] set option 0x%04x to %x\n", option, state); + + /* set option field */ + if (state) { + dev->netdev.flags |= option; + + /* trigger option specific actions */ + switch (option) { + case KW41ZRF_OPT_AUTOCCA: + LOG_DEBUG("[kw41zrf] enable: AUTOCCA\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT); + break; + + case KW41ZRF_OPT_PROMISCUOUS: + LOG_DEBUG("[kw41zrf] enable: PROMISCUOUS\n"); + /* enable promiscuous mode */ + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT); + /* auto ACK is always disabled in promiscuous mode by the hardware */ + break; + + case KW41ZRF_OPT_AUTOACK: + LOG_DEBUG("[kw41zrf] enable: AUTOACK\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT); + break; + + case KW41ZRF_OPT_ACK_REQ: + LOG_DEBUG("[kw41zrf] enable: ACK_REQ\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_START: + LOG_DEBUG("[kw41zrf] enable: TELL_RX_START\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_END: + LOG_DEBUG("[kw41zrf] enable: TELL_RX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_END: + LOG_DEBUG("[kw41zrf] enable: TELL_TX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_START: + LOG_DEBUG("[kw41zrf] enable: TELL_TX_START (ignored)\n"); + default: + /* do nothing */ + break; + } + } + else { + dev->netdev.flags &= ~(option); + /* trigger option specific actions */ + switch (option) { + case KW41ZRF_OPT_AUTOCCA: + LOG_DEBUG("[kw41zrf] disable: AUTOCCA\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT); + break; + + case KW41ZRF_OPT_PROMISCUOUS: + LOG_DEBUG("[kw41zrf] disable: PROMISCUOUS\n"); + /* disable promiscuous mode */ + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT); + break; + + case KW41ZRF_OPT_AUTOACK: + LOG_DEBUG("[kw41zrf] disable: AUTOACK\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT); + break; + + case KW41ZRF_OPT_ACK_REQ: + LOG_DEBUG("[kw41zrf] disable: ACK_REQ\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_START: + LOG_DEBUG("[kw41zrf] disable: TELL_RX_START\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_END: + LOG_DEBUG("[kw41zrf] disable: TELL_RX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_END: + LOG_DEBUG("[kw41zrf] disable: TELL_TX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_START: + LOG_DEBUG("[kw41zrf] disable: TELL_TX_START (ignored)\n"); + default: + /* do nothing */ + break; + } + } +} + +netopt_state_t kw41zrf_get_status(kw41zrf_t *dev) +{ + uint32_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; + + switch (seq) { + case XCVSEQ_IDLE: + return NETOPT_STATE_IDLE; + + case XCVSEQ_RECEIVE: + return NETOPT_STATE_RX; + + case XCVSEQ_TRANSMIT: + return NETOPT_STATE_TX; + + case XCVSEQ_CCA: + return NETOPT_STATE_RX; + + case XCVSEQ_TX_RX: + return NETOPT_STATE_TX; + + case XCVSEQ_CONTINUOUS_CCA: + return NETOPT_STATE_RX; + + default: + LOG_ERROR("[kw41zrf] XCVSEQ = %u is reserved!", (unsigned int) seq); + break; + } + return NETOPT_STATE_IDLE; +} + +int kw41zrf_cca(kw41zrf_t *dev) +{ + /* TODO: add Standalone CCA here */ + kw41zrf_set_sequence(dev, XCVSEQ_CCA); + /* using CCA mode 1, this takes exactly RX warmup time + 128 µs, which is + * short enough to just spin */ + while (((ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT) == XCVSEQ_CCA) {} + DEBUG("[kw41zrf] kw41zrf_cca done\n"); + if (ZLL->IRQSTS & ZLL_IRQSTS_CCA_MASK) { + DEBUG("[kw41zrf] Channel busy\n"); + return 1; + } + DEBUG("[kw41zrf] Channel free\n"); + return 0; +} + +void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value) +{ + ZLL->RX_WTR_MARK = ZLL_RX_WTR_MARK_RX_WTR_MARK(value); +} diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c new file mode 100644 index 0000000000000..49410cf7c6acb --- /dev/null +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * @file + * @brief Internal function of kw41zrf driver + * + * @author Joakim Nohlgård + * @} + */ + +#include "irq.h" +#include "panic.h" +#include "kw41zrf.h" +#include "kw41zrf_getset.h" +#include "kw41zrf_intern.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +struct { + void (*cb)(void *arg); /**< Callback function called from radio ISR */ + void *arg; /**< Argument to callback */ +} isr_config; + +void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg) +{ + unsigned int mask = irq_disable(); + isr_config.cb = cb; + isr_config.arg = arg; + irq_restore(mask); +} + +void kw41zrf_disable_interrupts(kw41zrf_t *dev) +{ + DEBUG("[kw41zrf] disable interrupts\n"); + /* Clear and disable all interrupts */ + ZLL->PHY_CTRL |= + ZLL_PHY_CTRL_TSM_MSK_MASK | + ZLL_PHY_CTRL_WAKE_MSK_MASK | + ZLL_PHY_CTRL_CRC_MSK_MASK | + ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK | + ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK | + ZLL_PHY_CTRL_RX_WMRK_MSK_MASK | + ZLL_PHY_CTRL_CCAMSK_MASK | + ZLL_PHY_CTRL_RXMSK_MASK | + ZLL_PHY_CTRL_TXMSK_MASK | + ZLL_PHY_CTRL_SEQMSK_MASK; + + /* Mask all timer interrupts and clear all interrupt flags */ + ZLL->IRQSTS = + ZLL_IRQSTS_TMR1MSK_MASK | + ZLL_IRQSTS_TMR2MSK_MASK | + ZLL_IRQSTS_TMR3MSK_MASK | + ZLL_IRQSTS_TMR4MSK_MASK | + ZLL_IRQSTS_TMR1IRQ_MASK | + ZLL_IRQSTS_TMR2IRQ_MASK | + ZLL_IRQSTS_TMR3IRQ_MASK | + ZLL_IRQSTS_TMR4IRQ_MASK | + ZLL_IRQSTS_WAKE_IRQ_MASK | + ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | + ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | + ZLL_IRQSTS_RXWTRMRKIRQ_MASK | + ZLL_IRQSTS_CCAIRQ_MASK | + ZLL_IRQSTS_RXIRQ_MASK | + ZLL_IRQSTS_TXIRQ_MASK | + ZLL_IRQSTS_SEQIRQ_MASK; +} + +void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) +{ + DEBUG("[kw41zrf] set power mode to %u\n", pm); + /* TODO handle event timer */ + switch (pm) { + case KW41ZRF_POWER_IDLE: + bit_clear32(&ZLL->DSM_CTRL, ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT); + break; + case KW41ZRF_POWER_DSM: + bit_set32(&ZLL->DSM_CTRL, ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT); + break; + default: + DEBUG("[kw41zrf] Unknown power mode %u\n", pm); + return; + } +} + +int kw41zrf_can_switch_to_idle(kw41zrf_t *dev) +{ + uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; + uint8_t actual = (ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT; + + DEBUG("[kw41zrf] XCVSEQ_ACTUAL=0x%x, XCVSEQ=0x%x, SEQ_STATE=0x%" PRIx32 "\n", actual, seq, + (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) >> ZLL_SEQ_STATE_SEQ_STATE_SHIFT); + + switch (seq) + { + case XCVSEQ_TRANSMIT: + case XCVSEQ_TX_RX: + return 0; + + default: + break; + } + switch (actual) + { + case XCVSEQ_TRANSMIT: + case XCVSEQ_TX_RX: + return 0; + + default: + break; + } + + return 1; +} + +/** Load the timer value (Setting Current Time) */ +static inline void kw41zrf_timer_load(kw41zrf_t *dev, uint32_t value) +{ + (void) dev; + ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR(value) | ZLL_EVENT_TMR_EVENT_TMR_LD_MASK; +} + +static inline uint32_t kw41zrf_timer_get(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->EVENT_TMR & ZLL_EVENT_TMR_EVENT_TMR_MASK) >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT; +} + +/** Set a timeout value for the given compare register of the Event Timer */ +static inline void kw41zrf_timer_set(kw41zrf_t *dev, volatile uint32_t *cmp_reg, uint32_t timeout) +{ + uint32_t now = kw41zrf_timer_get(dev); + + DEBUG("[kw41zrf] timer now: %" PRIx32 ", set %" PRIx32 "\n", now, now + timeout); + *cmp_reg = now + timeout; +} + +void kw41zrf_timer_init(kw41zrf_t *dev, kw41zrf_timer_timebase_t tb) +{ + ZLL->TMR_PRESCALE = (ZLL->TMR_PRESCALE & ~ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK) | + ZLL_TMR_PRESCALE_TMR_PRESCALE(tb); + kw41zrf_timer_load(dev, 0); +} + +void kw41zrf_timer2_seq_start_on(kw41zrf_t *dev) +{ + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); +} + +void kw41zrf_timer2_seq_start_off(kw41zrf_t *dev) +{ + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); +} + +void kw41zrf_timer3_seq_abort_on(kw41zrf_t *dev) +{ + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TC3TMOUT_SHIFT); +} + +void kw41zrf_timer3_seq_abort_off(kw41zrf_t *dev) +{ + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TC3TMOUT_SHIFT); +} + +void kw41zrf_trigger_tx_ops_enable(kw41zrf_t *dev, uint32_t timeout) +{ + kw41zrf_timer_set(dev, &ZLL->T2CMP, timeout); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT); +} + +void kw41zrf_trigger_tx_ops_disable(kw41zrf_t *dev) +{ + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT); + DEBUG("[kw41zrf] trigger_tx_ops_disable, now: %" PRIx32 "\n", kw41zrf_timer_get(dev)); +} + +void kw41zrf_abort_rx_ops_enable(kw41zrf_t *dev, uint32_t timeout) +{ + kw41zrf_timer_set(dev, &ZLL->T3CMP, timeout); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT); +} + +void kw41zrf_abort_rx_ops_disable(kw41zrf_t *dev) +{ + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT); + DEBUG("[kw41zrf] abort_rx_ops_disable, now: %" PRIx32 "\n", kw41zrf_timer_get(dev)); +} + +uint32_t kw41zrf_get_timestamp(kw41zrf_t *dev) +{ + return ZLL->TIMESTAMP; +} + +void isr_radio_int1(void) +{ + DEBUG("[kw41zrf] INT1\n"); + if (isr_config.cb != NULL) { + isr_config.cb(isr_config.arg); + } + cortexm_isr_end(); +} diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c new file mode 100644 index 0000000000000..60d8d56cd161f --- /dev/null +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -0,0 +1,812 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief Netdev interface for kw41zrf drivers + * + * @author Joakim Nohlgård + */ + +#include +#include +#include + +#include "log.h" +#include "od.h" +#include "net/eui64.h" +#include "net/ieee802154.h" +#include "net/netdev.h" +#include "net/netdev/ieee802154.h" + +#include "kw41zrf.h" +#include "kw41zrf_netdev.h" +#include "kw41zrf_intern.h" +#include "kw41zrf_getset.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +#define _MAX_MHR_OVERHEAD (25) + +/* Timing */ +#define KW41ZRF_CCA_TIME 8 +#define KW41ZRF_SHR_PHY_TIME 12 +#define KW41ZRF_PER_BYTE_TIME 2 +#define KW41ZRF_ACK_WAIT_TIME 54 + +static void kw41zrf_irq_handler(void *arg) +{ + netdev_t *dev = (netdev_t *) arg; + + kw41zrf_mask_irqs(); + + if (dev->event_callback) { + dev->event_callback(dev, NETDEV_EVENT_ISR); + } +} + +static int kw41zrf_netdev_init(netdev_t *netdev) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + + /* initialise SPI and GPIOs */ + if (kw41zrf_init(dev, &kw41zrf_irq_handler)) { + LOG_ERROR("[kw41zrf] unable to initialize device\n"); + return -1; + } + +#ifdef MODULE_NETSTATS_L2 + memset(&netdev->stats, 0, sizeof(netstats_t)); +#endif + + /* reset device to default values and put it into RX state */ + kw41zrf_reset_phy(dev); + + /* Use TC3 for RX timeouts */ + kw41zrf_timer3_seq_abort_on(dev); + + return 0; +} + +static inline size_t kw41zrf_tx_load(const void *buf, size_t len, size_t offset) +{ + /* Array bounds are checked in the kw41zrf_netdev_send loop */ + /* offset + 1 is used because buf[0] contains the frame length byte */ + memcpy(((uint8_t *)&ZLL->PKT_BUFFER_TX[0]) + offset + 1, buf, len); + return offset + len; +} + +static void kw41zrf_tx_exec(kw41zrf_t *dev) +{ + uint16_t len_fcf = ZLL->PKT_BUFFER_TX[0]; + DEBUG("[kw41zrf] len_fcf=0x%04x\n", len_fcf); + /* Check FCF field in the TX buffer to see if the ACK_REQ flag was set in + * the packet that is queued for transmission */ + uint8_t fcf = (len_fcf >> 8) & 0xff; + if ((dev->netdev.flags & KW41ZRF_OPT_ACK_REQ) && + (fcf & IEEE802154_FCF_ACK_REQ)) { + uint8_t payload_len = len_fcf & 0xff; + uint32_t tx_timeout = dev->tx_warmup_time + KW41ZRF_SHR_PHY_TIME + + payload_len * KW41ZRF_PER_BYTE_TIME + KW41ZRF_ACK_WAIT_TIME; + DEBUG("[kw41zrf] Start TR\n"); + kw41zrf_set_sequence(dev, XCVSEQ_TX_RX); + /* Set timeout for RX ACK */ + kw41zrf_abort_rx_ops_enable(dev, tx_timeout); + } + else { + DEBUG("[kw41zrf] Start T\n"); + kw41zrf_set_sequence(dev, XCVSEQ_TRANSMIT); + } +} + +static int kw41zrf_netdev_send(netdev_t *netdev, const struct iovec *vector, unsigned count) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + const struct iovec *ptr = vector; + size_t len = 0; + + /* make sure ongoing T or TR sequence are finished */ + if (kw41zrf_can_switch_to_idle(dev) == 0) { + /* TX in progress */ + return -ENOBUFS; + } + + /* load packet data into buffer */ + for (unsigned i = 0; i < count; i++, ptr++) { + /* current packet data + FCS too long */ + if ((len + ptr->iov_len + IEEE802154_FCS_LEN) > KW41ZRF_MAX_PKT_LENGTH) { + LOG_ERROR("[kw41zrf] packet too large (%u byte) to fit\n", + (unsigned)len + IEEE802154_FCS_LEN); + return -EOVERFLOW; + } + len = kw41zrf_tx_load(ptr->iov_base, ptr->iov_len, len); + } + + /* Abort what is going on */ + kw41zrf_set_sequence(dev, XCVSEQ_IDLE); + + DEBUG("[kw41zrf] TX %u bytes\n", len); + + /* + * First octet in the TX buffer contains the frame length. + * Nbytes = FRAME_LEN - 2 -> FRAME_LEN = Nbytes + 2 + * MKW41Z ref. man. 44.6.2.6.3.1.3 Sequence T (Transmit), p. 2147 + */ + *((volatile uint8_t *)&ZLL->PKT_BUFFER_TX[0]) = len + IEEE802154_FCS_LEN; +#if defined(MODULE_OD) && ENABLE_DEBUG + DEBUG("[kw41zrf] send:\n"); + od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_TX, len, OD_WIDTH_DEFAULT); +#endif + +#ifdef MODULE_NETSTATS_L2 + netdev->stats.tx_bytes += len; +#endif + + /* send data out directly if pre-loading is disabled */ + if (!(dev->netdev.flags & KW41ZRF_OPT_PRELOADING)) { + kw41zrf_tx_exec(dev); + } + + return (int)len; +} + +static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *info) +{ + /* get size of the received packet */ + uint8_t pkt_len = (ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT; + /* skip FCS */ + pkt_len -= IEEE802154_FCS_LEN; + DEBUG("[kw41zrf] RX %u bytes\n", pkt_len); + + /* just return length when buf == NULL */ + if (buf == NULL) { + return pkt_len; + } + +// DEBUG("[kw41zrf] buf len: %3u\n", (unsigned int)pkt_len); +#if defined(MODULE_OD) && ENABLE_DEBUG + DEBUG("[kw41zrf] recv:\n"); + od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_RX, pkt_len, OD_WIDTH_DEFAULT); +#endif + +#ifdef MODULE_NETSTATS_L2 + netdev->stats.rx_count++; + netdev->stats.rx_bytes += pkt_len; +#else + (void)netdev; +#endif + + if (pkt_len > len) { + /* not enough space in buf */ + return -ENOBUFS; + } + memcpy(buf, (const void *)&ZLL->PKT_BUFFER_RX[0], pkt_len); + + if (info != NULL) { + netdev_ieee802154_rx_info_t *radio_info = info; + uint8_t hw_lqi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >> + ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT; + if (hw_lqi >= 220) { + radio_info->lqi = 255; + } else { + radio_info->lqi = (51 * hw_lqi) / 44; + } + radio_info->rssi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_RSSI_MASK) >> ZLL_LQI_AND_RSSI_RSSI_SHIFT; + } + + return pkt_len; +} + +static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) +{ + switch (state) { + case NETOPT_STATE_OFF: + case NETOPT_STATE_SLEEP: + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); + break; + case NETOPT_STATE_IDLE: + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + kw41zrf_set_sequence(dev, dev->idle_state); + break; + case NETOPT_STATE_TX: + if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { + kw41zrf_tx_exec(dev); + } + break; + case NETOPT_STATE_RESET: + kw41zrf_reset_phy(dev); + break; + default: + return -ENOTSUP; + } + return sizeof(netopt_state_t); +} + +int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + + if (dev == NULL) { + return -ENODEV; + } + + switch (opt) { + case NETOPT_MAX_PACKET_SIZE: + if (len < sizeof(int16_t)) { + return -EOVERFLOW; + } + + *((uint16_t *)value) = KW41ZRF_MAX_PKT_LENGTH - _MAX_MHR_OVERHEAD; + return sizeof(uint16_t); + + case NETOPT_STATE: + if (len < sizeof(netopt_state_t)) { + return -EOVERFLOW; + } + *((netopt_state_t *)value) = dev->state; + return sizeof(netopt_state_t); + + case NETOPT_PRELOADING: + if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { + *((netopt_enable_t *)value) = NETOPT_ENABLE; + } + else { + *((netopt_enable_t *)value) = NETOPT_DISABLE; + } + return sizeof(netopt_enable_t); + + case NETOPT_PROMISCUOUSMODE: + if (dev->netdev.flags & KW41ZRF_OPT_PROMISCUOUS) { + *((netopt_enable_t *)value) = NETOPT_ENABLE; + } + else { + *((netopt_enable_t *)value) = NETOPT_DISABLE; + } + return sizeof(netopt_enable_t); + + case NETOPT_RX_START_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START); + return sizeof(netopt_enable_t); + + case NETOPT_RX_END_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END); + return sizeof(netopt_enable_t); + + case NETOPT_TX_START_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START); + return sizeof(netopt_enable_t); + + case NETOPT_TX_END_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END); + return sizeof(netopt_enable_t); + + case NETOPT_AUTOCCA: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_AUTOCCA); + return sizeof(netopt_enable_t); + + case NETOPT_TX_POWER: + if (len < sizeof(int16_t)) { + return -EOVERFLOW; + } + *((uint16_t *)value) = kw41zrf_get_txpower(dev); + return sizeof(uint16_t); + + case NETOPT_IS_CHANNEL_CLR: + if (kw41zrf_cca(dev)) { + *((netopt_enable_t *)value) = NETOPT_ENABLE; + } + else { + *((netopt_enable_t *)value) = NETOPT_DISABLE; + } + return sizeof(netopt_enable_t); + + case NETOPT_CCA_THRESHOLD: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + else { + *(int8_t *)value = kw41zrf_get_cca_threshold(dev); + } + return sizeof(int8_t); + + case NETOPT_CCA_MODE: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + else { + *(uint8_t *)value = kw41zrf_get_cca_mode(dev); + switch (*((int8_t *)value)) { + case NETDEV_IEEE802154_CCA_MODE_1: + case NETDEV_IEEE802154_CCA_MODE_2: + case NETDEV_IEEE802154_CCA_MODE_3: + return sizeof(uint8_t); + default: + break; + } + return -EOVERFLOW; + } + break; + + case NETOPT_CHANNEL_PAGE: + default: + break; + } + + return netdev_ieee802154_get((netdev_ieee802154_t *)netdev, opt, value, len); +} + +static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, void *value, size_t len) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + int res = -ENOTSUP; + + if (dev == NULL) { + return -ENODEV; + } + + switch (opt) { + case NETOPT_ADDRESS: + if (len > sizeof(uint16_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_addr_short(dev, *((uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ + } + break; + + case NETOPT_ADDRESS_LONG: + if (len > sizeof(uint64_t)) { + return -EOVERFLOW; + } + else { + kw41zrf_set_addr_long(dev, *((uint64_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ + } + break; + + case NETOPT_NID: + if (len > sizeof(uint16_t)) { + return -EOVERFLOW; + } + + else { + kw41zrf_set_pan(dev, *((uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::pan */ + } + break; + + case NETOPT_CHANNEL: + if (len != sizeof(uint16_t)) { + res = -EINVAL; + } + else { + uint8_t chan = ((uint8_t *)value)[0]; + if (kw41zrf_set_channel(dev, chan)) { + res = -EINVAL; + break; + } + /* don't set res to set netdev_ieee802154_t::chan */ + } + break; + + case NETOPT_CHANNEL_PAGE: + res = -EINVAL; + break; + + case NETOPT_TX_POWER: + if (len < sizeof(uint16_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_tx_power(dev, *(int16_t *)value); + res = sizeof(uint16_t); + } + break; + + case NETOPT_STATE: + if (len > sizeof(netopt_state_t)) { + res = -EOVERFLOW; + } + else { + res = kw41zrf_netdev_set_state(dev, *((netopt_state_t *)value)); + } + break; + + case NETOPT_AUTOACK: + /* Set up HW generated automatic ACK after Receive */ + kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, + ((bool *)value)[0]); + break; + + case NETOPT_ACK_REQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, + ((bool *)value)[0]); + break; + + case NETOPT_PRELOADING: + kw41zrf_set_option(dev, KW41ZRF_OPT_PRELOADING, + ((bool *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_PROMISCUOUSMODE: + kw41zrf_set_option(dev, KW41ZRF_OPT_PROMISCUOUS, + ((bool *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_RX_START_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START, + ((bool *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_RX_END_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, + ((bool *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_TX_START_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_START, + ((bool *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_TX_END_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, + ((bool *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_AUTOCCA: + kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOCCA, + ((bool *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_CCA_THRESHOLD: + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_cca_threshold(dev, *((int8_t*)value)); + res = sizeof(uint8_t); + } + break; + + case NETOPT_CCA_MODE: + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + switch (*((int8_t*)value)) { + case NETDEV_IEEE802154_CCA_MODE_1: + case NETDEV_IEEE802154_CCA_MODE_2: + case NETDEV_IEEE802154_CCA_MODE_3: + kw41zrf_set_cca_mode(dev, *((int8_t*)value)); + res = sizeof(uint8_t); + break; + case NETDEV_IEEE802154_CCA_MODE_4: + case NETDEV_IEEE802154_CCA_MODE_5: + case NETDEV_IEEE802154_CCA_MODE_6: + default: + break; + } + } + break; + + case NETOPT_RF_TESTMODE: +#ifdef KW41ZRF_TESTMODE + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_test_mode(dev, *((uint8_t *)value)); + res = sizeof(uint8_t); + } +#endif + break; + + default: + break; + } + + if (res == -ENOTSUP) { + res = netdev_ieee802154_set((netdev_ieee802154_t *)netdev, opt, + value, len); + } + + return res; +} + +/* Common CCA check handler code for sequences T and TR */ +static uint32_t _isr_event_seq_t_ccairq(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_CCAIRQ_MASK) { + /* CCA before TX has completed */ + handled_irqs |= ZLL_IRQSTS_CCAIRQ_MASK; + if (irqsts & ZLL_IRQSTS_CCA_MASK) { + /* Channel was determined busy */ + DEBUG("[kw41zrf] CCA ch busy (RSSI: %d)\n", + (int8_t)((ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> + ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)); + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY); + } + } + else { + /* Channel is idle */ + DEBUG("[kw41zrf] CCA ch idle (RSSI: %d)\n", + (int8_t)((ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> + ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)); + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START) { + /* TX will start after CCA check succeeded */ + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_STARTED); + } + } + } + return handled_irqs; +} + +static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + + if (irqsts & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) { + DEBUG("[kw41zrf] RXWTRMRKIRQ (R)\n"); + handled_irqs |= ZLL_IRQSTS_RXWTRMRKIRQ_MASK; + if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_STARTED); + } + } + + if (irqsts & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) { + DEBUG("[kw41zrf] FILTERFAILIRQ: %04"PRIx32"\n", ZLL->FILTERFAIL_CODE); + handled_irqs |= ZLL_IRQSTS_FILTERFAIL_IRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) { + DEBUG("[kw41zrf] finished RX\n"); + handled_irqs |= ZLL_IRQSTS_RXIRQ_MASK; + DEBUG("[kw41zrf] RX len: %3u\n", + (unsigned int)((ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> + ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)); + if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_AUTOACK_MASK) { + DEBUG("[kw41zrf] perform TXACK\n"); + } + } + + if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + DEBUG("[kw41zrf] finished TXACK\n"); + handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + uint32_t seq_ctrl_sts = ZLL->SEQ_CTRL_STS; + DEBUG("[kw41zrf] SEQIRQ (R)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { + DEBUG("[kw41zrf] RX timeout (R)\n"); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) { + DEBUG("[kw41zrf] PLL unlock (R)\n"); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) { + DEBUG("[kw41zrf] SW abort (R)\n"); + } + else { + /* No error reported */ + DEBUG("[kw41zrf] success (R)\n"); + if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_COMPLETE); + } + } + kw41zrf_set_sequence(dev, dev->idle_state); + } + + return handled_irqs; +} + +static uint32_t _isr_event_seq_t(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + DEBUG("[kw41zrf] finished TX (T)\n"); + handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; + } + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + /* Finished T sequence */ + DEBUG("[kw41zrf] SEQIRQ (T)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE); + } + /* Go back to being idle */ + kw41zrf_set_sequence(dev, dev->idle_state); + } + + return handled_irqs; +} + +/* Standalone CCA */ +static uint32_t _isr_event_seq_cca(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + /* Finished CCA sequence */ + DEBUG("[kw41zrf] SEQIRQ (C)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (irqsts & ZLL_IRQSTS_CCA_MASK) { + DEBUG("[kw41zrf] CCA ch busy\n"); + } + else { + DEBUG("[kw41zrf] CCA ch idle\n"); + } + kw41zrf_set_sequence(dev, dev->idle_state); + } + + return handled_irqs; +} + +static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + DEBUG("[kw41zrf] finished TX (TR)\n"); + handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; + if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_RXACKRQD_MASK) { + DEBUG("[kw41zrf] wait for RX ACK\n"); + } + } + + if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) { + DEBUG("[kw41zrf] got RX ACK\n"); + handled_irqs |= ZLL_IRQSTS_RXIRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) { + DEBUG("[kw41zrf] FILTERFAILIRQ (TR): %04"PRIx32"\n", ZLL->FILTERFAIL_CODE); + handled_irqs |= ZLL_IRQSTS_FILTERFAIL_IRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + uint32_t seq_ctrl_sts = ZLL->SEQ_CTRL_STS; + DEBUG("[kw41zrf] SEQIRQ (TR)\n"); + + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { + DEBUG("[kw41zrf] RXACK timeout (TR)\n"); + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_NOACK); + /* Clear TMR3 IRQ flag */ + handled_irqs |= ZLL_IRQSTS_TMR3IRQ_MASK; + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) { + DEBUG("[kw41zrf] PLL unlock (TR)\n"); + /* TODO: there is no other error event for TX failures */ + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) { + DEBUG("[kw41zrf] SW abort (TR)\n"); + /* TODO: there is no other error event for TX failures */ + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY); + } + else { + /* No error reported */ + DEBUG("[kw41zrf] TX success (TR)\n"); + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE); + } + } + kw41zrf_abort_rx_ops_disable(dev); + kw41zrf_set_sequence(dev, dev->idle_state); + } + + return handled_irqs; +} + +static uint32_t _isr_event_seq_ccca(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + DEBUG("[kw41zrf] SEQIRQ (CCCA)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (irqsts & ZLL_IRQSTS_CCA_MASK) { + DEBUG("[kw41zrf] CCCA ch busy\n"); + } + else { + DEBUG("[kw41zrf] CCCA ch idle\n"); + } + kw41zrf_abort_rx_ops_disable(dev); + kw41zrf_set_sequence(dev, dev->idle_state); + } + + return handled_irqs; +} + +static void kw41zrf_netdev_isr(netdev_t *netdev) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + uint32_t irqsts = ZLL->IRQSTS; + uint32_t handled_irqs = 0; + DEBUG("[kw41zrf] CTRL %08" PRIx32 ", IRQSTS %08" PRIx32 ", FILTERFAIL %08" PRIx32 "\n", + ZLL->PHY_CTRL, irqsts, ZLL->FILTERFAIL_CODE); + + uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; + + switch (seq) { + case XCVSEQ_RECEIVE: + handled_irqs |= _isr_event_seq_r(dev, irqsts); + break; + + case XCVSEQ_TRANSMIT: + /* First check CCA flags */ + handled_irqs |= _isr_event_seq_t_ccairq(dev, irqsts); + /* Then TX flags */ + handled_irqs |= _isr_event_seq_t(dev, irqsts); + break; + + case XCVSEQ_CCA: + handled_irqs |= _isr_event_seq_cca(dev, irqsts); + break; + + case XCVSEQ_TX_RX: + /* First check CCA flags */ + handled_irqs |= _isr_event_seq_t_ccairq(dev, irqsts); + /* Then TX/RX flags */ + handled_irqs |= _isr_event_seq_tr(dev, irqsts); + break; + + case XCVSEQ_CONTINUOUS_CCA: + handled_irqs |= _isr_event_seq_ccca(dev, irqsts); + break; + + case XCVSEQ_IDLE: + DEBUG("[kw41zrf] IRQ while IDLE\n"); + break; + + default: + DEBUG("[kw41zrf] undefined seq state in isr\n"); + break; + } + + /* Clear all IRQ flags now */ + ZLL->IRQSTS = irqsts; + + irqsts &= ~handled_irqs; + + if (irqsts & 0x000f017f) { + DEBUG("[kw41zrf] Unhandled IRQs: 0x%08"PRIx32"\n", + (irqsts & 0x000f017f)); + } + + kw41zrf_unmask_irqs(); +} + +const netdev_driver_t kw41zrf_driver = { + .init = kw41zrf_netdev_init, + .send = kw41zrf_netdev_send, + .recv = kw41zrf_netdev_recv, + .get = kw41zrf_netdev_get, + .set = kw41zrf_netdev_set, + .isr = kw41zrf_netdev_isr, +}; + +/** @} */ diff --git a/sys/auto_init/auto_init.c b/sys/auto_init/auto_init.c index 30fc3be9de854..facce344d5a36 100644 --- a/sys/auto_init/auto_init.c +++ b/sys/auto_init/auto_init.c @@ -208,6 +208,11 @@ void auto_init(void) auto_init_kw2xrf(); #endif +#ifdef MODULE_KW41ZRF + extern void auto_init_kw41zrf(void); + auto_init_kw41zrf(); +#endif + #ifdef MODULE_NETDEV_TAP extern void auto_init_netdev_tap(void); auto_init_netdev_tap(); diff --git a/sys/auto_init/netif/auto_init_kw41zrf.c b/sys/auto_init/netif/auto_init_kw41zrf.c new file mode 100644 index 0000000000000..b90c526c5f10b --- /dev/null +++ b/sys/auto_init/netif/auto_init_kw41zrf.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + * + */ + +/* + * @ingroup auto_init_gnrc_netif + * @{ + * + * @file + * @brief Auto initialization for kw41zrf network interfaces + * + * @author Joakim Nohlgård + */ + +#ifdef MODULE_KW41ZRF + +#include "log.h" +#include "board.h" +#include "net/gnrc/netdev.h" +#include "net/gnrc/netdev/ieee802154.h" +#include "net/gnrc.h" + +#include "kw41zrf.h" + +/** + * @brief Define stack parameters for the MAC layer thread + * @{ + */ +#define KW41ZRF_MAC_STACKSIZE (THREAD_STACKSIZE_DEFAULT) +#ifndef KW41ZRF_MAC_PRIO +#define KW41ZRF_MAC_PRIO (GNRC_NETDEV_MAC_PRIO) +#endif + +/* There is only one memory mapped transceiver in the supported SoCs, the driver + * does not try to take into account multiple instances of the hardware module */ +#define KW41ZRF_NUMOF 1 + +static kw41zrf_t kw41zrf_devs[KW41ZRF_NUMOF]; +static gnrc_netdev_t gnrc_adpt[KW41ZRF_NUMOF]; +static char _kw41zrf_stacks[KW41ZRF_NUMOF][KW41ZRF_MAC_STACKSIZE]; + +void auto_init_kw41zrf(void) +{ + for (unsigned i = 0; i < KW41ZRF_NUMOF; i++) { + LOG_DEBUG("[auto_init_netif] initializing kw41zrf #%u\n", i); + kw41zrf_setup(&kw41zrf_devs[i]); + if (gnrc_netdev_ieee802154_init(&gnrc_adpt[i], (netdev_ieee802154_t *)&kw41zrf_devs[i]) < 0) { + LOG_ERROR("[auto_init_netif] error initializing kw41zrf #%u\n", i); + } + else { + gnrc_netdev_init(_kw41zrf_stacks[i], KW41ZRF_MAC_STACKSIZE, + KW41ZRF_MAC_PRIO, "kw41zrf", &gnrc_adpt[i]); + } + } +} +#else +typedef int dont_be_pedantic; +#endif /* MODULE_KW41ZRF */ + +/** @} */