diff --git a/clang/include/clang/Basic/OpenMPKinds.h b/clang/include/clang/Basic/OpenMPKinds.h
index 16bb967f89d53e..1acdafa8572211 100644
--- a/clang/include/clang/Basic/OpenMPKinds.h
+++ b/clang/include/clang/Basic/OpenMPKinds.h
@@ -15,6 +15,7 @@
 #define LLVM_CLANG_BASIC_OPENMPKINDS_H
 
 #include "clang/Basic/LangOptions.h"
+#include "llvm/ADT/Sequence.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Frontend/OpenMP/OMPConstants.h"
 
@@ -389,5 +390,9 @@ bool isOpenMPInformationalDirective(OpenMPDirectiveKind DKind);
 bool isOpenMPCapturingDirective(OpenMPDirectiveKind DKind);
 }
 
+template <>
+struct llvm::enum_iteration_traits<clang::OpenMPDefaultmapClauseKind> {
+  static constexpr bool is_iterable = true;
+};
 #endif
 
diff --git a/clang/lib/AST/ByteCode/Compiler.cpp b/clang/lib/AST/ByteCode/Compiler.cpp
index 115b0aa7dd29c9..46f9c98d59befc 100644
--- a/clang/lib/AST/ByteCode/Compiler.cpp
+++ b/clang/lib/AST/ByteCode/Compiler.cpp
@@ -3320,6 +3320,10 @@ bool Compiler<Emitter>::VisitCXXStdInitializerListExpr(
 
   if (!this->visit(SubExpr))
     return false;
+  if (!this->emitConstUint8(0, E))
+    return false;
+  if (!this->emitArrayElemPtrPopUint8(E))
+    return false;
   if (!this->emitInitFieldPtr(R->getField(0u)->Offset, E))
     return false;
 
@@ -3334,6 +3338,8 @@ bool Compiler<Emitter>::VisitCXXStdInitializerListExpr(
 
   if (!this->emitGetFieldPtr(R->getField(0u)->Offset, E))
     return false;
+  if (!this->emitExpandPtr(E))
+    return false;
   if (!this->emitConst(static_cast<APSInt>(ArrayType->getSize()), PT_Uint64, E))
     return false;
   if (!this->emitArrayElemPtrPop(PT_Uint64, E))
diff --git a/clang/lib/AST/ByteCode/Interp.h b/clang/lib/AST/ByteCode/Interp.h
index 7a0011b9606976..e345b9ead967ce 100644
--- a/clang/lib/AST/ByteCode/Interp.h
+++ b/clang/lib/AST/ByteCode/Interp.h
@@ -1993,7 +1993,9 @@ bool OffsetHelper(InterpState &S, CodePtr OpPC, const T &Offset,
 template <PrimType Name, class T = typename PrimConv<Name>::T>
 bool AddOffset(InterpState &S, CodePtr OpPC) {
   const T &Offset = S.Stk.pop<T>();
-  const Pointer &Ptr = S.Stk.pop<Pointer>();
+  Pointer Ptr = S.Stk.pop<Pointer>();
+  if (Ptr.isBlockPointer())
+    Ptr = Ptr.expand();
   return OffsetHelper<T, ArithOp::Add>(S, OpPC, Offset, Ptr);
 }
 
diff --git a/clang/lib/AST/ByteCode/Pointer.h b/clang/lib/AST/ByteCode/Pointer.h
index d05d8e9bc1f388..acbef437752388 100644
--- a/clang/lib/AST/ByteCode/Pointer.h
+++ b/clang/lib/AST/ByteCode/Pointer.h
@@ -241,9 +241,8 @@ class Pointer {
     if (asBlockPointer().Base != Offset)
       return *this;
 
-    // If at base, point to an array of base types.
     if (isRoot())
-      return Pointer(Pointee, RootPtrMark, 0);
+      return Pointer(Pointee, asBlockPointer().Base, asBlockPointer().Base);
 
     // Step into the containing array, if inside one.
     unsigned Next = asBlockPointer().Base - getInlineDesc()->Offset;
@@ -711,8 +710,10 @@ class Pointer {
 
   /// Returns the embedded descriptor preceding a field.
   InlineDescriptor *getInlineDesc() const {
+    assert(isBlockPointer());
     assert(asBlockPointer().Base != sizeof(GlobalInlineDescriptor));
     assert(asBlockPointer().Base <= asBlockPointer().Pointee->getSize());
+    assert(asBlockPointer().Base >= sizeof(InlineDescriptor));
     return getDescriptor(asBlockPointer().Base);
   }
 
diff --git a/clang/lib/AST/OpenMPClause.cpp b/clang/lib/AST/OpenMPClause.cpp
index 7e73c076239410..eb15aa84406901 100644
--- a/clang/lib/AST/OpenMPClause.cpp
+++ b/clang/lib/AST/OpenMPClause.cpp
@@ -1125,16 +1125,12 @@ unsigned OMPClauseMappableExprCommon::getComponentsTotalNumber(
 
 unsigned OMPClauseMappableExprCommon::getUniqueDeclarationsTotalNumber(
     ArrayRef<const ValueDecl *> Declarations) {
-  unsigned TotalNum = 0u;
-  llvm::SmallPtrSet<const ValueDecl *, 8> Cache;
+  llvm::SmallPtrSet<const ValueDecl *, 8> UniqueDecls;
   for (const ValueDecl *D : Declarations) {
     const ValueDecl *VD = D ? cast<ValueDecl>(D->getCanonicalDecl()) : nullptr;
-    if (Cache.count(VD))
-      continue;
-    ++TotalNum;
-    Cache.insert(VD);
+    UniqueDecls.insert(VD);
   }
-  return TotalNum;
+  return UniqueDecls.size();
 }
 
 OMPMapClause *OMPMapClause::Create(
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index 9df5ab3c4872a4..9081c037b274e5 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -42,6 +42,7 @@
 #include "llvm/ADT/PointerEmbeddedInt.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Sequence.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Frontend/OpenMP/OMPAssume.h"
@@ -3707,6 +3708,17 @@ getMapClauseKindFromModifier(OpenMPDefaultmapClauseModifier M,
 }
 
 namespace {
+struct VariableImplicitInfo {
+  static const unsigned MapKindNum = OMPC_MAP_unknown;
+  static const unsigned DefaultmapKindNum = OMPC_DEFAULTMAP_unknown + 1;
+
+  llvm::SetVector<Expr *> Privates;
+  llvm::SetVector<Expr *> Firstprivates;
+  llvm::SetVector<Expr *> Mappings[DefaultmapKindNum][MapKindNum];
+  llvm::SmallVector<OpenMPMapModifierKind, NumberOfOMPMapClauseModifiers>
+      MapModifiers[DefaultmapKindNum];
+};
+
 class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
   DSAStackTy *Stack;
   Sema &SemaRef;
@@ -3714,12 +3726,8 @@ class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
   bool ErrorFound = false;
   bool TryCaptureCXXThisMembers = false;
   CapturedStmt *CS = nullptr;
-  const static unsigned DefaultmapKindNum = OMPC_DEFAULTMAP_unknown + 1;
-  llvm::SmallVector<Expr *, 4> ImplicitFirstprivate;
-  llvm::SmallVector<Expr *, 4> ImplicitPrivate;
-  llvm::SmallVector<Expr *, 4> ImplicitMap[DefaultmapKindNum][OMPC_MAP_delete];
-  llvm::SmallVector<OpenMPMapModifierKind, NumberOfOMPMapClauseModifiers>
-      ImplicitMapModifier[DefaultmapKindNum];
+
+  VariableImplicitInfo ImpInfo;
   SemaOpenMP::VarsWithInheritedDSAType VarsWithInheritedDSA;
   llvm::SmallDenseSet<const ValueDecl *, 4> ImplicitDeclarations;
 
@@ -3871,9 +3879,9 @@ class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
         bool IsModifierPresent = Stack->getDefaultmapModifier(ClauseKind) ==
                                  OMPC_DEFAULTMAP_MODIFIER_present;
         if (IsModifierPresent) {
-          if (!llvm::is_contained(ImplicitMapModifier[ClauseKind],
+          if (!llvm::is_contained(ImpInfo.MapModifiers[ClauseKind],
                                   OMPC_MAP_MODIFIER_present)) {
-            ImplicitMapModifier[ClauseKind].push_back(
+            ImpInfo.MapModifiers[ClauseKind].push_back(
                 OMPC_MAP_MODIFIER_present);
           }
         }
@@ -3913,13 +3921,13 @@ class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
           IsFirstprivate =
               IsFirstprivate || (Stack->mustBeFirstprivate(ClauseKind) && !Res);
           if (IsFirstprivate) {
-            ImplicitFirstprivate.emplace_back(E);
+            ImpInfo.Firstprivates.insert(E);
           } else {
             OpenMPDefaultmapClauseModifier M =
                 Stack->getDefaultmapModifier(ClauseKind);
             OpenMPMapClauseKind Kind = getMapClauseKindFromModifier(
                 M, ClauseKind == OMPC_DEFAULTMAP_aggregate || Res);
-            ImplicitMap[ClauseKind][Kind].emplace_back(E);
+            ImpInfo.Mappings[ClauseKind][Kind].insert(E);
           }
           return;
         }
@@ -3956,9 +3964,9 @@ class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
             !DVar.RefExpr)) &&
           !Stack->isLoopControlVariable(VD).first) {
         if (Stack->getDefaultDSA() == DSA_private)
-          ImplicitPrivate.push_back(E);
+          ImpInfo.Privates.insert(E);
         else
-          ImplicitFirstprivate.push_back(E);
+          ImpInfo.Firstprivates.insert(E);
         return;
       }
 
@@ -4015,7 +4023,7 @@ class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
             getVariableCategoryFromDecl(SemaRef.getLangOpts(), FD);
         OpenMPMapClauseKind Kind = getMapClauseKindFromModifier(
             Modifier, /*IsAggregateOrDeclareTarget=*/true);
-        ImplicitMap[ClauseKind][Kind].emplace_back(E);
+        ImpInfo.Mappings[ClauseKind][Kind].insert(E);
         return;
       }
 
@@ -4050,7 +4058,7 @@ class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
         // expression.
         // TODO: try to make it firstprivate.
         if (DVar.CKind != OMPC_unknown)
-          ImplicitFirstprivate.push_back(E);
+          ImpInfo.Firstprivates.insert(E);
       }
       return;
     }
@@ -4172,18 +4180,7 @@ class DSAAttrChecker final : public StmtVisitor<DSAAttrChecker, void> {
     }
   }
   bool isErrorFound() const { return ErrorFound; }
-  ArrayRef<Expr *> getImplicitFirstprivate() const {
-    return ImplicitFirstprivate;
-  }
-  ArrayRef<Expr *> getImplicitPrivate() const { return ImplicitPrivate; }
-  ArrayRef<Expr *> getImplicitMap(OpenMPDefaultmapClauseKind DK,
-                                  OpenMPMapClauseKind MK) const {
-    return ImplicitMap[DK][MK];
-  }
-  ArrayRef<OpenMPMapModifierKind>
-  getImplicitMapModifier(OpenMPDefaultmapClauseKind Kind) const {
-    return ImplicitMapModifier[Kind];
-  }
+  const VariableImplicitInfo &getImplicitInfo() const { return ImpInfo; }
   const SemaOpenMP::VarsWithInheritedDSAType &getVarsWithInheritedDSA() const {
     return VarsWithInheritedDSA;
   }
@@ -6509,69 +6506,56 @@ StmtResult SemaOpenMP::ActOnOpenMPExecutableDirective(
       return StmtError();
     // Generate list of implicitly defined firstprivate variables.
     VarsWithInheritedDSA = DSAChecker.getVarsWithInheritedDSA();
+    VariableImplicitInfo ImpInfo = DSAChecker.getImplicitInfo();
 
-    SmallVector<Expr *, 4> ImplicitFirstprivates(
-        DSAChecker.getImplicitFirstprivate());
-    SmallVector<Expr *, 4> ImplicitPrivates(DSAChecker.getImplicitPrivate());
-    const unsigned DefaultmapKindNum = OMPC_DEFAULTMAP_unknown + 1;
-    SmallVector<Expr *, 4> ImplicitMaps[DefaultmapKindNum][OMPC_MAP_delete];
-    SmallVector<OpenMPMapModifierKind, NumberOfOMPMapClauseModifiers>
-        ImplicitMapModifiers[DefaultmapKindNum];
     SmallVector<SourceLocation, NumberOfOMPMapClauseModifiers>
-        ImplicitMapModifiersLoc[DefaultmapKindNum];
+        ImplicitMapModifiersLoc[VariableImplicitInfo::DefaultmapKindNum];
     // Get the original location of present modifier from Defaultmap clause.
-    SourceLocation PresentModifierLocs[DefaultmapKindNum];
+    SourceLocation PresentModifierLocs[VariableImplicitInfo::DefaultmapKindNum];
     for (OMPClause *C : Clauses) {
       if (auto *DMC = dyn_cast<OMPDefaultmapClause>(C))
         if (DMC->getDefaultmapModifier() == OMPC_DEFAULTMAP_MODIFIER_present)
           PresentModifierLocs[DMC->getDefaultmapKind()] =
               DMC->getDefaultmapModifierLoc();
     }
-    for (unsigned VC = 0; VC < DefaultmapKindNum; ++VC) {
-      auto K = static_cast<OpenMPDefaultmapClauseKind>(VC);
-      for (unsigned I = 0; I < OMPC_MAP_delete; ++I) {
-        ArrayRef<Expr *> ImplicitMap =
-            DSAChecker.getImplicitMap(K, static_cast<OpenMPMapClauseKind>(I));
-        ImplicitMaps[VC][I].append(ImplicitMap.begin(), ImplicitMap.end());
-      }
-      ArrayRef<OpenMPMapModifierKind> ImplicitModifier =
-          DSAChecker.getImplicitMapModifier(K);
-      ImplicitMapModifiers[VC].append(ImplicitModifier.begin(),
-                                      ImplicitModifier.end());
-      std::fill_n(std::back_inserter(ImplicitMapModifiersLoc[VC]),
-                  ImplicitModifier.size(), PresentModifierLocs[VC]);
+
+    for (OpenMPDefaultmapClauseKind K :
+         llvm::enum_seq_inclusive<OpenMPDefaultmapClauseKind>(
+             OpenMPDefaultmapClauseKind(), OMPC_DEFAULTMAP_unknown)) {
+      std::fill_n(std::back_inserter(ImplicitMapModifiersLoc[K]),
+                  ImpInfo.MapModifiers[K].size(), PresentModifierLocs[K]);
     }
     // Mark taskgroup task_reduction descriptors as implicitly firstprivate.
     for (OMPClause *C : Clauses) {
       if (auto *IRC = dyn_cast<OMPInReductionClause>(C)) {
         for (Expr *E : IRC->taskgroup_descriptors())
           if (E)
-            ImplicitFirstprivates.emplace_back(E);
+            ImpInfo.Firstprivates.insert(E);
       }
       // OpenMP 5.0, 2.10.1 task Construct
       // [detach clause]... The event-handle will be considered as if it was
       // specified on a firstprivate clause.
       if (auto *DC = dyn_cast<OMPDetachClause>(C))
-        ImplicitFirstprivates.push_back(DC->getEventHandler());
+        ImpInfo.Firstprivates.insert(DC->getEventHandler());
     }
-    if (!ImplicitFirstprivates.empty()) {
+    if (!ImpInfo.Firstprivates.empty()) {
       if (OMPClause *Implicit = ActOnOpenMPFirstprivateClause(
-              ImplicitFirstprivates, SourceLocation(), SourceLocation(),
-              SourceLocation())) {
+              ImpInfo.Firstprivates.getArrayRef(), SourceLocation(),
+              SourceLocation(), SourceLocation())) {
         ClausesWithImplicit.push_back(Implicit);
         ErrorFound = cast<OMPFirstprivateClause>(Implicit)->varlist_size() !=
-                     ImplicitFirstprivates.size();
+                     ImpInfo.Firstprivates.size();
       } else {
         ErrorFound = true;
       }
     }
-    if (!ImplicitPrivates.empty()) {
-      if (OMPClause *Implicit =
-              ActOnOpenMPPrivateClause(ImplicitPrivates, SourceLocation(),
-                                       SourceLocation(), SourceLocation())) {
+    if (!ImpInfo.Privates.empty()) {
+      if (OMPClause *Implicit = ActOnOpenMPPrivateClause(
+              ImpInfo.Privates.getArrayRef(), SourceLocation(),
+              SourceLocation(), SourceLocation())) {
         ClausesWithImplicit.push_back(Implicit);
         ErrorFound = cast<OMPPrivateClause>(Implicit)->varlist_size() !=
-                     ImplicitPrivates.size();
+                     ImpInfo.Privates.size();
       } else {
         ErrorFound = true;
       }
@@ -6601,9 +6585,10 @@ StmtResult SemaOpenMP::ActOnOpenMPExecutableDirective(
           ClausesWithImplicit.emplace_back(Implicit);
       }
     }
-    for (unsigned I = 0, E = DefaultmapKindNum; I < E; ++I) {
+    for (unsigned I = 0; I < VariableImplicitInfo::DefaultmapKindNum; ++I) {
       int ClauseKindCnt = -1;
-      for (ArrayRef<Expr *> ImplicitMap : ImplicitMaps[I]) {
+      for (unsigned J = 0; J < VariableImplicitInfo::MapKindNum; ++J) {
+        ArrayRef<Expr *> ImplicitMap = ImpInfo.Mappings[I][J].getArrayRef();
         ++ClauseKindCnt;
         if (ImplicitMap.empty())
           continue;
@@ -6611,7 +6596,7 @@ StmtResult SemaOpenMP::ActOnOpenMPExecutableDirective(
         DeclarationNameInfo MapperId;
         auto K = static_cast<OpenMPMapClauseKind>(ClauseKindCnt);
         if (OMPClause *Implicit = ActOnOpenMPMapClause(
-                nullptr, ImplicitMapModifiers[I], ImplicitMapModifiersLoc[I],
+                nullptr, ImpInfo.MapModifiers[I], ImplicitMapModifiersLoc[I],
                 MapperIdScopeSpec, MapperId, K, /*IsMapTypeImplicit=*/true,
                 SourceLocation(), SourceLocation(), ImplicitMap,
                 OMPVarListLocTy())) {
diff --git a/clang/test/AST/ByteCode/initializer_list.cpp b/clang/test/AST/ByteCode/initializer_list.cpp
new file mode 100644
index 00000000000000..4e3b8dc9120167
--- /dev/null
+++ b/clang/test/AST/ByteCode/initializer_list.cpp
@@ -0,0 +1,55 @@
+// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -fms-extensions -std=c++20 -verify=expected,both %s
+// RUN: %clang_cc1 -std=c++20 -fms-extensions -verify=ref,both %s
+
+// both-no-diagnostics
+
+namespace std {
+  typedef decltype(sizeof(int)) size_t;
+  template <class _E>
+  class initializer_list
+  {
+    const _E* __begin_;
+    size_t    __size_;
+
+    initializer_list(const _E* __b, size_t __s)
+      : __begin_(__b),
+        __size_(__s)
+    {}
+
+  public:
+    typedef _E        value_type;
+    typedef const _E& reference;
+    typedef const _E& const_reference;
+    typedef size_t    size_type;
+
+    typedef const _E* iterator;
+    typedef const _E* const_iterator;
+
+    constexpr initializer_list() : __begin_(nullptr), __size_(0) {}
+
+    constexpr size_t    size()  const {return __size_;}
+    constexpr const _E* begin() const {return __begin_;}
+    constexpr const _E* end()   const {return __begin_ + __size_;}
+  };
+}
+
+class Thing {
+public:
+  int m = 12;
+  constexpr Thing(int m) : m(m) {}
+  constexpr bool operator==(const Thing& that) const {
+    return this->m == that.m;
+  }
+};
+
+constexpr bool is_contained(std::initializer_list<Thing> Set, const Thing &Element) {
+   return (*Set.begin() == Element);
+}
+
+constexpr int foo() {
+  const Thing a{12};
+  const Thing b{14};
+  return is_contained({a}, b);
+}
+
+static_assert(foo() == 0);
diff --git a/libc/hdr/types/CMakeLists.txt b/libc/hdr/types/CMakeLists.txt
index 3f4d70140082cf..8789e0c7870263 100644
--- a/libc/hdr/types/CMakeLists.txt
+++ b/libc/hdr/types/CMakeLists.txt
@@ -181,3 +181,12 @@ add_proxy_header_library(
     libc.include.signal
 )
 
+add_proxy_header_library(
+  stack_t
+  HDRS
+    stack_t.h
+  FULL_BUILD_DEPENDS
+    libc.include.llvm-libc-types.stack_t
+    libc.include.signal
+)
+
diff --git a/libc/hdr/types/stack_t.h b/libc/hdr/types/stack_t.h
new file mode 100644
index 00000000000000..8c7c37a5d814ee
--- /dev/null
+++ b/libc/hdr/types/stack_t.h
@@ -0,0 +1,23 @@
+//===-- Definition of stack_t.h -------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https:llvm.or/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_HDR_STACK_T_H
+#define LLVM_LIBC_HDR_STACK_T_H
+
+#ifdef LIBC_FULL_BUILD
+
+#include "include/llvm-libc-types/stack_t.h"
+
+#else // overlay mode
+
+#include <signal.h>
+
+#endif // LLVM_LIBC_FULL_BUILD
+
+#endif // LLVM_LIBC_HDR_TYPES_STACK_T_H
diff --git a/libc/src/signal/linux/CMakeLists.txt b/libc/src/signal/linux/CMakeLists.txt
index 103175bb139bab..e314242dc376fb 100644
--- a/libc/src/signal/linux/CMakeLists.txt
+++ b/libc/src/signal/linux/CMakeLists.txt
@@ -77,6 +77,7 @@ add_entrypoint_object(
     libc.include.sys_syscall
     libc.src.__support.OSUtil.osutil
     libc.src.errno.errno
+    libc.hdr.types.stack_t
 )
 
 add_entrypoint_object(
diff --git a/libc/src/signal/linux/sigaltstack.cpp b/libc/src/signal/linux/sigaltstack.cpp
index 2e142a473fea71..c19394cd179122 100644
--- a/libc/src/signal/linux/sigaltstack.cpp
+++ b/libc/src/signal/linux/sigaltstack.cpp
@@ -7,13 +7,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "src/signal/sigaltstack.h"
+#include "hdr/types/stack_t.h"
 #include "src/__support/macros/config.h"
 #include "src/errno/libc_errno.h"
 #include "src/signal/linux/signal_utils.h"
 
 #include "src/__support/common.h"
 
-#include <signal.h>
 #include <sys/syscall.h>
 
 namespace LIBC_NAMESPACE_DECL {
diff --git a/libc/src/signal/sigaltstack.h b/libc/src/signal/sigaltstack.h
index fc6ec356e5ef86..7a82c0ee997118 100644
--- a/libc/src/signal/sigaltstack.h
+++ b/libc/src/signal/sigaltstack.h
@@ -9,8 +9,8 @@
 #ifndef LLVM_LIBC_SRC_SIGNAL_SIGALTSTACK_H
 #define LLVM_LIBC_SRC_SIGNAL_SIGALTSTACK_H
 
+#include "hdr/types/stack_t.h"
 #include "src/__support/macros/config.h"
-#include <signal.h>
 
 namespace LIBC_NAMESPACE_DECL {
 
diff --git a/llvm/include/llvm/AsmParser/LLParser.h b/llvm/include/llvm/AsmParser/LLParser.h
index 06855561f0c0bf..0246d41bb24a0b 100644
--- a/llvm/include/llvm/AsmParser/LLParser.h
+++ b/llvm/include/llvm/AsmParser/LLParser.h
@@ -394,7 +394,7 @@ namespace llvm {
     bool parseGVFlags(GlobalValueSummary::GVFlags &GVFlags);
     bool parseGVarFlags(GlobalVarSummary::GVarFlags &GVarFlags);
     bool parseOptionalFFlags(FunctionSummary::FFlags &FFlags);
-    bool parseOptionalCalls(std::vector<FunctionSummary::EdgeTy> &Calls);
+    bool parseOptionalCalls(SmallVectorImpl<FunctionSummary::EdgeTy> &Calls);
     bool parseHotness(CalleeInfo::HotnessType &Hotness);
     bool parseOptionalTypeIdInfo(FunctionSummary::TypeIdInfo &TypeIdInfo);
     bool parseTypeTests(std::vector<GlobalValue::GUID> &TypeTests);
diff --git a/llvm/include/llvm/IR/ModuleSummaryIndex.h b/llvm/include/llvm/IR/ModuleSummaryIndex.h
index 701c67f1b0af2b..af3734cc2c54b5 100644
--- a/llvm/include/llvm/IR/ModuleSummaryIndex.h
+++ b/llvm/include/llvm/IR/ModuleSummaryIndex.h
@@ -851,7 +851,7 @@ class FunctionSummary : public GlobalValueSummary {
   /// Create an empty FunctionSummary (with specified call edges).
   /// Used to represent external nodes and the dummy root node.
   static FunctionSummary
-  makeDummyFunctionSummary(std::vector<FunctionSummary::EdgeTy> Edges) {
+  makeDummyFunctionSummary(SmallVectorImpl<FunctionSummary::EdgeTy> &&Edges) {
     return FunctionSummary(
         FunctionSummary::GVFlags(
             GlobalValue::LinkageTypes::AvailableExternallyLinkage,
@@ -880,7 +880,9 @@ class FunctionSummary : public GlobalValueSummary {
   FFlags FunFlags;
 
   /// List of <CalleeValueInfo, CalleeInfo> call edge pairs from this function.
-  std::vector<EdgeTy> CallGraphEdgeList;
+  /// We use SmallVector<ValueInfo, 0> instead of std::vector<ValueInfo> for its
+  /// smaller memory footprint.
+  SmallVector<EdgeTy, 0> CallGraphEdgeList;
 
   std::unique_ptr<TypeIdInfo> TIdInfo;
 
@@ -910,7 +912,7 @@ class FunctionSummary : public GlobalValueSummary {
 public:
   FunctionSummary(GVFlags Flags, unsigned NumInsts, FFlags FunFlags,
                   SmallVectorImpl<ValueInfo> &&Refs,
-                  std::vector<EdgeTy> CGEdges,
+                  SmallVectorImpl<EdgeTy> &&CGEdges,
                   std::vector<GlobalValue::GUID> TypeTests,
                   std::vector<VFuncId> TypeTestAssumeVCalls,
                   std::vector<VFuncId> TypeCheckedLoadVCalls,
@@ -957,7 +959,7 @@ class FunctionSummary : public GlobalValueSummary {
   /// Return the list of <CalleeValueInfo, CalleeInfo> pairs.
   ArrayRef<EdgeTy> calls() const { return CallGraphEdgeList; }
 
-  std::vector<EdgeTy> &mutableCalls() { return CallGraphEdgeList; }
+  SmallVector<EdgeTy, 0> &mutableCalls() { return CallGraphEdgeList; }
 
   void addCall(EdgeTy E) { CallGraphEdgeList.push_back(E); }
 
@@ -1535,7 +1537,7 @@ class ModuleSummaryIndex {
       discoverNodes(ValueInfo(HaveGVs, &S), FunctionHasParent);
     }
 
-    std::vector<FunctionSummary::EdgeTy> Edges;
+    SmallVector<FunctionSummary::EdgeTy, 0> Edges;
     // create edges to all roots in the Index
     for (auto &P : FunctionHasParent) {
       if (P.second)
@@ -1544,9 +1546,11 @@ class ModuleSummaryIndex {
     }
     if (Edges.empty()) {
       // Failed to find root - return an empty node
-      return FunctionSummary::makeDummyFunctionSummary({});
+      return FunctionSummary::makeDummyFunctionSummary(
+          SmallVector<FunctionSummary::EdgeTy, 0>());
     }
-    auto CallGraphRoot = FunctionSummary::makeDummyFunctionSummary(Edges);
+    auto CallGraphRoot =
+        FunctionSummary::makeDummyFunctionSummary(std::move(Edges));
     return CallGraphRoot;
   }
 
@@ -1894,10 +1898,11 @@ template <> struct GraphTraits<ValueInfo> {
     return P.first;
   }
   using ChildIteratorType =
-      mapped_iterator<std::vector<FunctionSummary::EdgeTy>::iterator,
+      mapped_iterator<SmallVector<FunctionSummary::EdgeTy, 0>::iterator,
                       decltype(&valueInfoFromEdge)>;
 
-  using ChildEdgeIteratorType = std::vector<FunctionSummary::EdgeTy>::iterator;
+  using ChildEdgeIteratorType =
+      SmallVector<FunctionSummary::EdgeTy, 0>::iterator;
 
   static NodeRef getEntryNode(ValueInfo V) { return V; }
 
diff --git a/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h b/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h
index 8bfdd69a0bafaa..902d1305c818ac 100644
--- a/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h
+++ b/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h
@@ -230,7 +230,7 @@ template <> struct CustomMappingTraits<GlobalValueSummaryMapTy> {
               FSum.CanAutoHide,
               static_cast<GlobalValueSummary::ImportKind>(FSum.ImportType)),
           /*NumInsts=*/0, FunctionSummary::FFlags{}, std::move(Refs),
-          ArrayRef<FunctionSummary::EdgeTy>{}, std::move(FSum.TypeTests),
+          SmallVector<FunctionSummary::EdgeTy, 0>{}, std::move(FSum.TypeTests),
           std::move(FSum.TypeTestAssumeVCalls),
           std::move(FSum.TypeCheckedLoadVCalls),
           std::move(FSum.TypeTestAssumeConstVCalls),
diff --git a/llvm/include/llvm/TableGen/Error.h b/llvm/include/llvm/TableGen/Error.h
index 04618995e0fe6d..a51ed48dba0e86 100644
--- a/llvm/include/llvm/TableGen/Error.h
+++ b/llvm/include/llvm/TableGen/Error.h
@@ -14,12 +14,16 @@
 #ifndef LLVM_TABLEGEN_ERROR_H
 #define LLVM_TABLEGEN_ERROR_H
 
+#include "llvm/ADT/STLFunctionalExtras.h"
 #include "llvm/Support/SourceMgr.h"
-#include "llvm/TableGen/Record.h"
 
 namespace llvm {
+class Record;
+class RecordVal;
+class Init;
 
 void PrintNote(const Twine &Msg);
+void PrintNote(function_ref<void(raw_ostream &OS)> PrintMsg);
 void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg);
 
 [[noreturn]] void PrintFatalNote(const Twine &Msg);
@@ -32,6 +36,7 @@ void PrintWarning(ArrayRef<SMLoc> WarningLoc, const Twine &Msg);
 void PrintWarning(const char *Loc, const Twine &Msg);
 
 void PrintError(const Twine &Msg);
+void PrintError(function_ref<void(raw_ostream &OS)> PrintMsg);
 void PrintError(ArrayRef<SMLoc> ErrorLoc, const Twine &Msg);
 void PrintError(const char *Loc, const Twine &Msg);
 void PrintError(const Record *Rec, const Twine &Msg);
@@ -41,6 +46,7 @@ void PrintError(const RecordVal *RecVal, const Twine &Msg);
 [[noreturn]] void PrintFatalError(ArrayRef<SMLoc> ErrorLoc, const Twine &Msg);
 [[noreturn]] void PrintFatalError(const Record *Rec, const Twine &Msg);
 [[noreturn]] void PrintFatalError(const RecordVal *RecVal, const Twine &Msg);
+[[noreturn]] void PrintFatalError(function_ref<void(raw_ostream &OS)> PrintMsg);
 
 void CheckAssert(SMLoc Loc, Init *Condition, Init *Message);
 void dumpMessage(SMLoc Loc, Init *Message);
diff --git a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
index 95ef97a23a686e..2d4961dade9db1 100644
--- a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
+++ b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
@@ -309,7 +309,7 @@ static void computeFunctionSummary(
   // Map from callee ValueId to profile count. Used to accumulate profile
   // counts for all static calls to a given callee.
   MapVector<ValueInfo, CalleeInfo, DenseMap<ValueInfo, unsigned>,
-            std::vector<std::pair<ValueInfo, CalleeInfo>>>
+            SmallVector<FunctionSummary::EdgeTy, 0>>
       CallGraphEdges;
   SetVector<ValueInfo, SmallVector<ValueInfo, 0>> RefEdges, LoadRefEdges,
       StoreRefEdges;
@@ -964,7 +964,7 @@ ModuleSummaryIndex llvm::buildModuleSummaryIndex(
                         /* HasUnknownCall */ true,
                         /* MustBeUnreachable */ false},
                     SmallVector<ValueInfo, 0>{},
-                    ArrayRef<FunctionSummary::EdgeTy>{},
+                    SmallVector<FunctionSummary::EdgeTy, 0>{},
                     ArrayRef<GlobalValue::GUID>{},
                     ArrayRef<FunctionSummary::VFuncId>{},
                     ArrayRef<FunctionSummary::VFuncId>{},
diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
index 9bdbc0f45f0fdc..b5639c9b9382ae 100644
--- a/llvm/lib/AsmParser/LLParser.cpp
+++ b/llvm/lib/AsmParser/LLParser.cpp
@@ -9637,7 +9637,7 @@ bool LLParser::parseFunctionSummary(std::string Name, GlobalValue::GUID GUID,
       /*Live=*/false, /*IsLocal=*/false, /*CanAutoHide=*/false,
       GlobalValueSummary::Definition);
   unsigned InstCount;
-  std::vector<FunctionSummary::EdgeTy> Calls;
+  SmallVector<FunctionSummary::EdgeTy, 0> Calls;
   FunctionSummary::TypeIdInfo TypeIdInfo;
   std::vector<FunctionSummary::ParamAccess> ParamAccesses;
   SmallVector<ValueInfo, 0> Refs;
@@ -9926,7 +9926,8 @@ bool LLParser::parseOptionalFFlags(FunctionSummary::FFlags &FFlags) {
 /// Call ::= '(' 'callee' ':' GVReference
 ///            [( ',' 'hotness' ':' Hotness | ',' 'relbf' ':' UInt32 )]?
 ///            [ ',' 'tail' ]? ')'
-bool LLParser::parseOptionalCalls(std::vector<FunctionSummary::EdgeTy> &Calls) {
+bool LLParser::parseOptionalCalls(
+    SmallVectorImpl<FunctionSummary::EdgeTy> &Calls) {
   assert(Lex.getKind() == lltok::kw_calls);
   Lex.Lex();
 
diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 7c90d907ffcd8a..fddd01464716f4 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -986,10 +986,9 @@ class ModuleSummaryIndexBitcodeReader : public BitcodeReaderBase {
       uint64_t Offset,
       DenseMap<unsigned, GlobalValue::LinkageTypes> &ValueIdToLinkageMap);
   SmallVector<ValueInfo, 0> makeRefList(ArrayRef<uint64_t> Record);
-  std::vector<FunctionSummary::EdgeTy> makeCallList(ArrayRef<uint64_t> Record,
-                                                    bool IsOldProfileFormat,
-                                                    bool HasProfile,
-                                                    bool HasRelBF);
+  SmallVector<FunctionSummary::EdgeTy, 0>
+  makeCallList(ArrayRef<uint64_t> Record, bool IsOldProfileFormat,
+               bool HasProfile, bool HasRelBF);
   Error parseEntireSummary(unsigned ID);
   Error parseModuleStringTable();
   void parseTypeIdCompatibleVtableSummaryRecord(ArrayRef<uint64_t> Record);
@@ -7377,11 +7376,11 @@ ModuleSummaryIndexBitcodeReader::makeRefList(ArrayRef<uint64_t> Record) {
   return Ret;
 }
 
-std::vector<FunctionSummary::EdgeTy>
+SmallVector<FunctionSummary::EdgeTy, 0>
 ModuleSummaryIndexBitcodeReader::makeCallList(ArrayRef<uint64_t> Record,
                                               bool IsOldProfileFormat,
                                               bool HasProfile, bool HasRelBF) {
-  std::vector<FunctionSummary::EdgeTy> Ret;
+  SmallVector<FunctionSummary::EdgeTy, 0> Ret;
   // In the case of new profile formats, there are two Record entries per
   // Edge. Otherwise, conservatively reserve up to Record.size.
   if (!IsOldProfileFormat && (HasProfile || HasRelBF))
@@ -7669,7 +7668,7 @@ Error ModuleSummaryIndexBitcodeReader::parseEntireSummary(unsigned ID) {
           ArrayRef<uint64_t>(Record).slice(RefListStartIndex, NumRefs));
       bool HasProfile = (BitCode == bitc::FS_PERMODULE_PROFILE);
       bool HasRelBF = (BitCode == bitc::FS_PERMODULE_RELBF);
-      std::vector<FunctionSummary::EdgeTy> Calls = makeCallList(
+      SmallVector<FunctionSummary::EdgeTy, 0> Calls = makeCallList(
           ArrayRef<uint64_t>(Record).slice(CallGraphEdgeStartIndex),
           IsOldProfileFormat, HasProfile, HasRelBF);
       setSpecialRefs(Refs, NumRORefs, NumWORefs);
@@ -7823,7 +7822,7 @@ Error ModuleSummaryIndexBitcodeReader::parseEntireSummary(unsigned ID) {
       SmallVector<ValueInfo, 0> Refs = makeRefList(
           ArrayRef<uint64_t>(Record).slice(RefListStartIndex, NumRefs));
       bool HasProfile = (BitCode == bitc::FS_COMBINED_PROFILE);
-      std::vector<FunctionSummary::EdgeTy> Edges = makeCallList(
+      SmallVector<FunctionSummary::EdgeTy, 0> Edges = makeCallList(
           ArrayRef<uint64_t>(Record).slice(CallGraphEdgeStartIndex),
           IsOldProfileFormat, HasProfile, false);
       ValueInfo VI = std::get<0>(getValueInfoFromValueId(ValueID));
diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
index 37221b8cd8bfed..0ac1b36c75d51d 100644
--- a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+++ b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
@@ -551,9 +551,8 @@ class MetadataLoader::MetadataLoaderImpl {
     DenseSet<DILocalScope *> Visited;
     while (S && !isa<DISubprogram>(S)) {
       S = dyn_cast_or_null<DILocalScope>(S->getScope());
-      if (Visited.contains(S))
+      if (!Visited.insert(S).second)
         break;
-      Visited.insert(S);
     }
     ParentSubprogram[InitialScope] = llvm::dyn_cast_or_null<DISubprogram>(S);
 
diff --git a/llvm/lib/IR/ModuleSummaryIndex.cpp b/llvm/lib/IR/ModuleSummaryIndex.cpp
index a788e63d95a117..12a558b3bc1b12 100644
--- a/llvm/lib/IR/ModuleSummaryIndex.cpp
+++ b/llvm/lib/IR/ModuleSummaryIndex.cpp
@@ -37,7 +37,8 @@ static cl::opt<bool> ImportConstantsWithRefs(
 constexpr uint32_t FunctionSummary::ParamAccess::RangeWidth;
 
 FunctionSummary FunctionSummary::ExternalNode =
-    FunctionSummary::makeDummyFunctionSummary({});
+    FunctionSummary::makeDummyFunctionSummary(
+        SmallVector<FunctionSummary::EdgeTy, 0>());
 
 GlobalValue::VisibilityTypes ValueInfo::getELFVisibility() const {
   bool HasProtected = false;
diff --git a/llvm/lib/TableGen/Error.cpp b/llvm/lib/TableGen/Error.cpp
index 4b99ff89da3b93..e21f369833be63 100644
--- a/llvm/lib/TableGen/Error.cpp
+++ b/llvm/lib/TableGen/Error.cpp
@@ -40,12 +40,23 @@ static void PrintMessage(ArrayRef<SMLoc> Loc, SourceMgr::DiagKind Kind,
                         "instantiated from multiclass");
 }
 
+// Run file cleanup handlers and then exit fatally (with non-zero exit code).
+[[noreturn]] inline static void fatal_exit() {
+  // The following call runs the file cleanup handlers.
+  sys::RunInterruptHandlers();
+  std::exit(1);
+}
+
 // Functions to print notes.
 
 void PrintNote(const Twine &Msg) {
   WithColor::note() << Msg << "\n";
 }
 
+void PrintNote(function_ref<void(raw_ostream &OS)> PrintMsg) {
+  PrintMsg(WithColor::note());
+}
+
 void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg) {
   PrintMessage(NoteLoc, SourceMgr::DK_Note, Msg);
 }
@@ -54,34 +65,26 @@ void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg) {
 
 void PrintFatalNote(const Twine &Msg) {
   PrintNote(Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
 }
 
 void PrintFatalNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg) {
   PrintNote(NoteLoc, Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
 }
 
 // This method takes a Record and uses the source location
 // stored in it.
 void PrintFatalNote(const Record *Rec, const Twine &Msg) {
   PrintNote(Rec->getLoc(), Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
 }
 
 // This method takes a RecordVal and uses the source location
 // stored in it.
 void PrintFatalNote(const RecordVal *RecVal, const Twine &Msg) {
   PrintNote(RecVal->getLoc(), Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
 }
 
 // Functions to print warnings.
@@ -100,6 +103,10 @@ void PrintWarning(const char *Loc, const Twine &Msg) {
 
 void PrintError(const Twine &Msg) { WithColor::error() << Msg << "\n"; }
 
+void PrintError(function_ref<void(raw_ostream &OS)> PrintMsg) {
+  PrintMsg(WithColor::error());
+}
+
 void PrintError(ArrayRef<SMLoc> ErrorLoc, const Twine &Msg) {
   PrintMessage(ErrorLoc, SourceMgr::DK_Error, Msg);
 }
@@ -124,34 +131,31 @@ void PrintError(const RecordVal *RecVal, const Twine &Msg) {
 
 void PrintFatalError(const Twine &Msg) {
   PrintError(Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
+}
+
+void PrintFatalError(function_ref<void(raw_ostream &OS)> PrintMsg) {
+  PrintError(PrintMsg);
+  fatal_exit();
 }
 
 void PrintFatalError(ArrayRef<SMLoc> ErrorLoc, const Twine &Msg) {
   PrintError(ErrorLoc, Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
 }
 
 // This method takes a Record and uses the source location
 // stored in it.
 void PrintFatalError(const Record *Rec, const Twine &Msg) {
   PrintError(Rec->getLoc(), Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
 }
 
 // This method takes a RecordVal and uses the source location
 // stored in it.
 void PrintFatalError(const RecordVal *RecVal, const Twine &Msg) {
   PrintError(RecVal->getLoc(), Msg);
-  // The following call runs the file cleanup handlers.
-  sys::RunInterruptHandlers();
-  std::exit(1);
+  fatal_exit();
 }
 
 // Check an assertion: Obtain the condition value and be sure it is true.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 18c601a671ac69..f59906ad59f2b7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17087,6 +17087,16 @@ bool AArch64TargetLowering::lowerInterleavedLoad(
   if (!isLegalInterleavedAccessType(VTy, DL, UseScalable))
     return false;
 
+  // Check if the interleave is a zext(shuffle), that can be better optimized
+  // into shift / and masks. For the moment we do this just for uitofp (not
+  // zext) to avoid issues with widening instructions.
+  if (Shuffles.size() == 4 && all_of(Shuffles, [](ShuffleVectorInst *SI) {
+        return SI->hasOneUse() && match(SI->user_back(), m_UIToFP(m_Value())) &&
+               SI->getType()->getScalarSizeInBits() * 4 ==
+                   SI->user_back()->getType()->getScalarSizeInBits();
+      }))
+    return false;
+
   unsigned NumLoads = getNumInterleavedAccesses(VTy, DL, UseScalable);
 
   auto *FVTy = cast<FixedVectorType>(VTy);
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index 8a78ed6f2f8068..e81cddb086f062 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -255,9 +255,8 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
   const RISCVTargetLowering &TLI = *Subtarget.getTargetLowering();
 
-  unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
-  assert(XLen == 32 || XLen == 64);
-  MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
+  unsigned XLen = Subtarget.getXLen();
+  MVT XLenVT = Subtarget.getXLenVT();
 
   // Static chain parameter must not be passed in normal argument registers,
   // so we assign t2 for it as done in GCC's __builtin_call_with_static_chain
diff --git a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
index 58f06ca8b0297b..ef9c264482a640 100644
--- a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
+++ b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
@@ -502,10 +502,8 @@ struct MainSwitch {
   void addToQueue(Value *Val, BasicBlock *BB,
                   std::deque<std::pair<Value *, BasicBlock *>> &Q,
                   SmallSet<Value *, 16> &SeenValues) {
-    if (SeenValues.contains(Val))
-      return;
-    Q.push_back({Val, BB});
-    SeenValues.insert(Val);
+    if (SeenValues.insert(Val).second)
+      Q.push_back({Val, BB});
   }
 
   bool isValidSelectInst(SelectInst *SI) {
diff --git a/llvm/test/CodeGen/AArch64/zext-shuffle.ll b/llvm/test/CodeGen/AArch64/zext-shuffle.ll
index 6d25c874a28933..2965996ddcb026 100644
--- a/llvm/test/CodeGen/AArch64/zext-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/zext-shuffle.ll
@@ -472,59 +472,61 @@ define <8 x double> @uitofp_fadd(<32 x i16> %l) {
 define <8 x double> @uitofp_load_fadd(ptr %p) {
 ; CHECK-LABEL: uitofp_load_fadd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]
-; CHECK-NEXT:    ushll2 v4.4s, v0.8h, #0
-; CHECK-NEXT:    ushll v5.4s, v0.4h, #0
-; CHECK-NEXT:    ushll2 v6.4s, v1.8h, #0
-; CHECK-NEXT:    ushll v7.4s, v1.4h, #0
-; CHECK-NEXT:    ushll2 v16.4s, v2.8h, #0
-; CHECK-NEXT:    ushll v17.4s, v2.4h, #0
-; CHECK-NEXT:    ushll2 v18.4s, v3.8h, #0
-; CHECK-NEXT:    ushll v0.4s, v3.4h, #0
-; CHECK-NEXT:    ushll2 v1.2d, v4.4s, #0
-; CHECK-NEXT:    ushll2 v2.2d, v5.4s, #0
-; CHECK-NEXT:    ushll v3.2d, v4.2s, #0
-; CHECK-NEXT:    ushll v4.2d, v5.2s, #0
-; CHECK-NEXT:    ushll2 v5.2d, v6.4s, #0
-; CHECK-NEXT:    ushll2 v19.2d, v7.4s, #0
-; CHECK-NEXT:    ushll v6.2d, v6.2s, #0
-; CHECK-NEXT:    ushll v7.2d, v7.2s, #0
-; CHECK-NEXT:    ushll2 v20.2d, v16.4s, #0
-; CHECK-NEXT:    ushll2 v21.2d, v17.4s, #0
-; CHECK-NEXT:    ushll v16.2d, v16.2s, #0
-; CHECK-NEXT:    ushll v17.2d, v17.2s, #0
-; CHECK-NEXT:    ushll v22.2d, v0.2s, #0
-; CHECK-NEXT:    ushll2 v23.2d, v18.4s, #0
-; CHECK-NEXT:    ushll2 v0.2d, v0.4s, #0
-; CHECK-NEXT:    ushll v18.2d, v18.2s, #0
-; CHECK-NEXT:    ucvtf v1.2d, v1.2d
-; CHECK-NEXT:    ucvtf v2.2d, v2.2d
-; CHECK-NEXT:    ucvtf v3.2d, v3.2d
-; CHECK-NEXT:    ucvtf v4.2d, v4.2d
-; CHECK-NEXT:    ucvtf v5.2d, v5.2d
+; CHECK-NEXT:    ldp q1, q2, [x0]
+; CHECK-NEXT:    movi v0.2d, #0x0000000000ffff
+; CHECK-NEXT:    ldp q3, q4, [x0, #32]
+; CHECK-NEXT:    ushr v5.2d, v1.2d, #16
+; CHECK-NEXT:    ushr v6.2d, v2.2d, #16
+; CHECK-NEXT:    ushr v20.2d, v1.2d, #32
+; CHECK-NEXT:    ushr v7.2d, v3.2d, #16
+; CHECK-NEXT:    ushr v17.2d, v4.2d, #16
+; CHECK-NEXT:    ushr v22.2d, v2.2d, #32
+; CHECK-NEXT:    ushr v23.2d, v3.2d, #32
+; CHECK-NEXT:    ushr v24.2d, v4.2d, #32
+; CHECK-NEXT:    and v16.16b, v1.16b, v0.16b
+; CHECK-NEXT:    and v18.16b, v2.16b, v0.16b
+; CHECK-NEXT:    and v19.16b, v3.16b, v0.16b
+; CHECK-NEXT:    and v21.16b, v4.16b, v0.16b
+; CHECK-NEXT:    and v5.16b, v5.16b, v0.16b
+; CHECK-NEXT:    and v6.16b, v6.16b, v0.16b
+; CHECK-NEXT:    and v7.16b, v7.16b, v0.16b
+; CHECK-NEXT:    and v17.16b, v17.16b, v0.16b
+; CHECK-NEXT:    and v20.16b, v20.16b, v0.16b
+; CHECK-NEXT:    and v22.16b, v22.16b, v0.16b
+; CHECK-NEXT:    and v23.16b, v23.16b, v0.16b
+; CHECK-NEXT:    and v0.16b, v24.16b, v0.16b
+; CHECK-NEXT:    ushr v1.2d, v1.2d, #48
+; CHECK-NEXT:    ushr v2.2d, v2.2d, #48
+; CHECK-NEXT:    ushr v3.2d, v3.2d, #48
+; CHECK-NEXT:    ushr v4.2d, v4.2d, #48
+; CHECK-NEXT:    ucvtf v16.2d, v16.2d
+; CHECK-NEXT:    ucvtf v18.2d, v18.2d
 ; CHECK-NEXT:    ucvtf v19.2d, v19.2d
+; CHECK-NEXT:    ucvtf v21.2d, v21.2d
+; CHECK-NEXT:    ucvtf v5.2d, v5.2d
 ; CHECK-NEXT:    ucvtf v6.2d, v6.2d
 ; CHECK-NEXT:    ucvtf v7.2d, v7.2d
-; CHECK-NEXT:    ucvtf v20.2d, v20.2d
-; CHECK-NEXT:    ucvtf v21.2d, v21.2d
-; CHECK-NEXT:    ucvtf v16.2d, v16.2d
 ; CHECK-NEXT:    ucvtf v17.2d, v17.2d
+; CHECK-NEXT:    ucvtf v20.2d, v20.2d
 ; CHECK-NEXT:    ucvtf v22.2d, v22.2d
 ; CHECK-NEXT:    ucvtf v23.2d, v23.2d
 ; CHECK-NEXT:    ucvtf v0.2d, v0.2d
-; CHECK-NEXT:    ucvtf v18.2d, v18.2d
-; CHECK-NEXT:    fadd v1.2d, v1.2d, v5.2d
-; CHECK-NEXT:    fadd v4.2d, v4.2d, v7.2d
-; CHECK-NEXT:    fadd v6.2d, v3.2d, v6.2d
-; CHECK-NEXT:    fadd v2.2d, v2.2d, v19.2d
-; CHECK-NEXT:    fadd v3.2d, v17.2d, v22.2d
-; CHECK-NEXT:    fadd v5.2d, v16.2d, v18.2d
-; CHECK-NEXT:    fadd v7.2d, v21.2d, v0.2d
-; CHECK-NEXT:    fadd v16.2d, v20.2d, v23.2d
-; CHECK-NEXT:    fadd v0.2d, v4.2d, v3.2d
-; CHECK-NEXT:    fadd v3.2d, v1.2d, v16.2d
-; CHECK-NEXT:    fadd v1.2d, v2.2d, v7.2d
-; CHECK-NEXT:    fadd v2.2d, v6.2d, v5.2d
+; CHECK-NEXT:    ucvtf v1.2d, v1.2d
+; CHECK-NEXT:    ucvtf v2.2d, v2.2d
+; CHECK-NEXT:    ucvtf v3.2d, v3.2d
+; CHECK-NEXT:    ucvtf v4.2d, v4.2d
+; CHECK-NEXT:    fadd v6.2d, v18.2d, v6.2d
+; CHECK-NEXT:    fadd v5.2d, v16.2d, v5.2d
+; CHECK-NEXT:    fadd v17.2d, v21.2d, v17.2d
+; CHECK-NEXT:    fadd v7.2d, v19.2d, v7.2d
+; CHECK-NEXT:    fadd v1.2d, v20.2d, v1.2d
+; CHECK-NEXT:    fadd v3.2d, v23.2d, v3.2d
+; CHECK-NEXT:    fadd v2.2d, v22.2d, v2.2d
+; CHECK-NEXT:    fadd v4.2d, v0.2d, v4.2d
+; CHECK-NEXT:    fadd v0.2d, v5.2d, v1.2d
+; CHECK-NEXT:    fadd v1.2d, v6.2d, v2.2d
+; CHECK-NEXT:    fadd v2.2d, v7.2d, v3.2d
+; CHECK-NEXT:    fadd v3.2d, v17.2d, v4.2d
 ; CHECK-NEXT:    ret
     %l = load <32 x i16>, ptr %p
     %s1 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
diff --git a/llvm/test/CodeGen/ARM/big-endian-vmov.ll b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
index 7e0947ccfd58e8..327d4334ad83a1 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vmov.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
@@ -144,7 +144,7 @@ define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
 ;
 ; CHECK-BE-LABEL: vmov_i64_b:
 ; CHECK-BE:       @ %bb.0:
-; CHECK-BE-NEXT:    d16, #0xff0000ff00ffff00
+; CHECK-BE-NEXT:    vmov.i64 d16, #0xff0000ff00ffff00
 ; CHECK-BE-NEXT:    vrev64.32 d0, d16
 ; CHECK-BE-NEXT:    bx lr
   ret <1 x i64> <i64 72056498804490495>
@@ -180,7 +180,7 @@ define arm_aapcs_vfpcc <2 x i64> @and_v2i64_b(<2 x i64> %a) {
 ;
 ; CHECK-BE-LABEL: and_v2i64_b:
 ; CHECK-BE:       @ %bb.0:
-; CHECK-BE-NEXT:    q8, #0xff0000ff00ffff00
+; CHECK-BE-NEXT:    vmov.i64 q8, #0xff0000ff00ffff00
 ; CHECK-BE-NEXT:    vrev64.32 q8, q8
 ; CHECK-BE-NEXT:    vand q0, q0, q8
 ; CHECK-BE-NEXT:    bx lr
@@ -219,6 +219,7 @@ define arm_aapcs_vfpcc <8 x i16> @vmvn_v16i8_m1() {
   ret <8 x i16> <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
 }
 
+; FIXME: This is incorrect for BE
 define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
 ; CHECK-LE-LABEL: and_v8i16_m1:
 ; CHECK-LE:       @ %bb.0:
@@ -236,6 +237,22 @@ define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
 }
 
 ; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {
+; CHECK-LE-LABEL: or_v8i16_1:
+; CHECK-LE:       @ %bb.0:
+; CHECK-LE-NEXT:    vorr.i32 q0, #0x10000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: or_v8i16_1:
+; CHECK-BE:       @ %bb.0:
+; CHECK-BE-NEXT:    vrev64.32 q8, q0
+; CHECK-BE-NEXT:    vorr.i32 q8, #0x10000
+; CHECK-BE-NEXT:    vrev64.32 q0, q8
+; CHECK-BE-NEXT:    bx lr
+  %b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
+  ret <8 x i16> %b
+}
+
 define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_m1(<8 x i16> %a) {
 ; CHECK-LE-LABEL: xor_v8i16_m1:
 ; CHECK-LE:       @ %bb.0:
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
index 54bbb0d48643c3..3399d62ff13460 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
@@ -1,61 +1,104 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 
 define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh0(<8 x i16> %a) {
-; CHECK-LABEL: test_vbicq_n_u16_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vbic.i16 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u16_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vbic.i16 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u16_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vbic.i16 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = and <8 x i16> %a, <i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101>
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh8(<8 x i16> %a) {
-; CHECK-LABEL: test_vbicq_n_u16_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vbic.i16 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u16_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vbic.i16 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u16_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vbic.i16 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = and <8 x i16> %a, <i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601>
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh0(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vbic.i32 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vbic.i32 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vbic.i32 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = and <4 x i32> %a, <i32 -101, i32 -101, i32 -101, i32 -101>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh8(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vbic.i32 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vbic.i32 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vbic.i32 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = and <4 x i32> %a, <i32 -25601, i32 -25601, i32 -25601, i32 -25601>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh16(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh16:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vbic.i32 q0, #0x640000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh16:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vbic.i32 q0, #0x640000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh16:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vbic.i32 q1, #0x640000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = and <4 x i32> %a, <i32 -6553601, i32 -6553601, i32 -6553601, i32 -6553601>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh24(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh24:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vbic.i32 q0, #0x64000000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh24:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vbic.i32 q0, #0x64000000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh24:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vbic.i32 q1, #0x64000000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = and <4 x i32> %a, <i32 -1677721601, i32 -1677721601, i32 -1677721601, i32 -1677721601>
   ret <4 x i32> %0
@@ -65,83 +108,142 @@ entry:
 ; so in this case we expect to see the constant being prepared in
 ; another register.
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_illegal(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_illegal:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmvn.i32 q1, #0x54ff
-; CHECK-NEXT:    vand q0, q0, q1
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_illegal:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmvn.i32 q1, #0x54ff
+; CHECK-LE-NEXT:    vand q0, q0, q1
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_illegal:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmvn.i32 q0, #0x54ff
+; CHECK-BE-NEXT:    vand q1, q1, q0
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = and <4 x i32> %a, <i32 -21760, i32 -21760, i32 -21760, i32 -21760>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh0(<8 x i16> %a) {
-; CHECK-LABEL: test_vorrq_n_u16_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vorr.i16 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u16_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vorr.i16 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u16_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vorr.i16 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = or <8 x i16> %a, <i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100>
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh8(<8 x i16> %a) {
-; CHECK-LABEL: test_vorrq_n_u16_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vorr.i16 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u16_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vorr.i16 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u16_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vorr.i16 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = or <8 x i16> %a, <i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600>
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh0(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vorr.i32 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vorr.i32 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vorr.i32 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = or <4 x i32> %a, <i32 100, i32 100, i32 100, i32 100>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh8(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vorr.i32 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vorr.i32 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vorr.i32 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = or <4 x i32> %a, <i32 25600, i32 25600, i32 25600, i32 25600>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh16(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh16:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vorr.i32 q0, #0x640000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh16:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vorr.i32 q0, #0x640000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh16:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vorr.i32 q1, #0x640000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = or <4 x i32> %a, <i32 6553600, i32 6553600, i32 6553600, i32 6553600>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh24(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh24:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vorr.i32 q0, #0x64000000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh24:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vorr.i32 q0, #0x64000000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh24:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vorr.i32 q1, #0x64000000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = or <4 x i32> %a, <i32 1677721600, i32 1677721600, i32 1677721600, i32 1677721600>
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u16_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vbict.i16 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u16_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vbict.i16 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u16_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vbict.i16 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -151,12 +253,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u16_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vbict.i16 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u16_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vbict.i16 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u16_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vbict.i16 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -166,12 +277,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vbict.i32 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vbict.i32 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vbict.i32 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -181,12 +301,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vbict.i32 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vbict.i32 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vbict.i32 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -196,12 +325,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh16:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vbict.i32 q0, #0x640000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh16:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vbict.i32 q0, #0x640000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh16:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vbict.i32 q1, #0x640000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -211,12 +349,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh24:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vbict.i32 q0, #0x64000000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh24:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vbict.i32 q0, #0x64000000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh24:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vbict.i32 q1, #0x64000000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -226,12 +373,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u16_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vorrt.i16 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u16_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vorrt.i16 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u16_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vorrt.i16 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -241,12 +397,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u16_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vorrt.i16 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u16_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vorrt.i16 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u16_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vorrt.i16 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -256,12 +421,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh0:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vorrt.i32 q0, #0x64
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh0:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vorrt.i32 q0, #0x64
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh0:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vorrt.i32 q1, #0x64
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -271,12 +445,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh8:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vorrt.i32 q0, #0x6400
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh8:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vorrt.i32 q0, #0x6400
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh8:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vorrt.i32 q1, #0x6400
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -286,12 +469,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh16:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vorrt.i32 q0, #0x640000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh16:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vorrt.i32 q0, #0x640000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh16:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vorrt.i32 q1, #0x640000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -301,12 +493,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh24:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vorrt.i32 q0, #0x64000000
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh24:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vorrt.i32 q0, #0x64000000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh24:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vorrt.i32 q1, #0x64000000
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -334,12 +535,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> %inactive, i16 zeroext %p) {
-; CHECK-LABEL: test_vmvnq_m_n_u16:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmvnt.i16 q0, #0xaa00
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vmvnq_m_n_u16:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vmvnt.i16 q0, #0xaa00
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vmvnq_m_n_u16:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vmvnt.i16 q1, #0xaa00
+; CHECK-BE-NEXT:    vrev64.16 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -348,12 +558,21 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_u32(<4 x i32> %inactive, i16 zeroext %p) {
-; CHECK-LABEL: test_vmvnq_m_n_u32:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmvnt.i32 q0, #0xaa00
-; CHECK-NEXT:    bx lr
+; CHECK-LE-LABEL: test_vmvnq_m_n_u32:
+; CHECK-LE:       @ %bb.0: @ %entry
+; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vpst
+; CHECK-LE-NEXT:    vmvnt.i32 q0, #0xaa00
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: test_vmvnq_m_n_u32:
+; CHECK-BE:       @ %bb.0: @ %entry
+; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    vmsr p0, r0
+; CHECK-BE-NEXT:    vpst
+; CHECK-BE-NEXT:    vmvnt.i32 q1, #0xaa00
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
index fe63034c7acd37..9cf92663e3b052 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
@@ -1050,7 +1050,6 @@ entry:
   ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
 }
 
-; FIXME: This is incorrect for BE
 define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f0f0f0f0f0f0f0f(<16 x i8> %a) {
 ; CHECKLE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
 ; CHECKLE:       @ %bb.0: @ %entry
@@ -1331,3 +1330,37 @@ entry:
   %s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %s
 }
+
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
+; CHECKLE-LABEL: and_v8i16_m1:
+; CHECKLE:       @ %bb.0:
+; CHECKLE-NEXT:    vbic.i32 q0, #0x10000
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: and_v8i16_m1:
+; CHECKBE:       @ %bb.0:
+; CHECKBE-NEXT:    vrev64.32 q1, q0
+; CHECKBE-NEXT:    vbic.i32 q1, #0x10000
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+  %b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
+  ret <8 x i16> %b
+}
+
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {
+; CHECKLE-LABEL: or_v8i16_1:
+; CHECKLE:       @ %bb.0:
+; CHECKLE-NEXT:    vorr.i32 q0, #0x10000
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: or_v8i16_1:
+; CHECKBE:       @ %bb.0:
+; CHECKBE-NEXT:    vrev64.32 q1, q0
+; CHECKBE-NEXT:    vorr.i32 q1, #0x10000
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+  %b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
+  ret <8 x i16> %b
+}
diff --git a/llvm/test/TableGen/intrinsic-prefix-error.td b/llvm/test/TableGen/intrinsic-prefix-error.td
new file mode 100644
index 00000000000000..3869bde3a4ba76
--- /dev/null
+++ b/llvm/test/TableGen/intrinsic-prefix-error.td
@@ -0,0 +1,14 @@
+// RUN: not llvm-tblgen -gen-intrinsic-enums --intrinsic-prefix=gen3 -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s
+
+include "llvm/IR/Intrinsics.td"
+
+// CHECK: error: tried to generate intrinsics for unknown target gen3
+// CHECK-NEXT: Known targets are: gen1, gen2
+
+let TargetPrefix = "gen1" in {
+  def int_gen1_int0 : Intrinsic<[llvm_i32_ty]>;
+}
+
+let TargetPrefix = "gen2" in {
+  def int_gen2_int0 : Intrinsic<[llvm_i32_ty]>;
+}
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index df3f72ff2ec7f5..9a31d4f6487cb5 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -1603,14 +1603,11 @@ static TreePatternNode &getOperandNum(unsigned OpNo, TreePatternNode &N,
   OpNo -= NumResults;
 
   if (OpNo >= N.getNumChildren()) {
-    std::string S;
-    raw_string_ostream OS(S);
-    OS << "Invalid operand number in type constraint " << (OpNo + NumResults)
-       << " ";
-    N.print(OS);
-    PrintFatalError(S);
+    PrintFatalError([&N, OpNo, NumResults](raw_ostream &OS) {
+      OS << "Invalid operand number in type constraint " << (OpNo + NumResults);
+      N.print(OS);
+    });
   }
-
   return N.getChild(OpNo);
 }
 
diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp
index 9cc1b5ccb8acb9..39b4a3ac375ed6 100644
--- a/llvm/utils/TableGen/DXILEmitter.cpp
+++ b/llvm/utils/TableGen/DXILEmitter.cpp
@@ -402,10 +402,8 @@ static void emitDXILOperationTable(std::vector<DXILOperationDesc> &Ops,
   for (auto &Op : Ops) {
     OpStrings.add(Op.OpName);
 
-    if (ClassSet.contains(Op.OpClass))
-      continue;
-    ClassSet.insert(Op.OpClass);
-    OpClassStrings.add(Op.OpClass.data());
+    if (ClassSet.insert(Op.OpClass).second)
+      OpClassStrings.add(Op.OpClass.data());
   }
 
   // Layout names.
diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp
index f46a8d1e9f081d..e367fad5838aae 100644
--- a/llvm/utils/TableGen/DecoderEmitter.cpp
+++ b/llvm/utils/TableGen/DecoderEmitter.cpp
@@ -1961,12 +1961,11 @@ void parseVarLenInstOperand(const Record &Def,
 }
 
 static void debugDumpRecord(const Record &Rec) {
-  // Dump the record, so we can see what's going on...
-  std::string E;
-  raw_string_ostream S(E);
-  S << "Dumping record for previous error:\n";
-  S << Rec;
-  PrintNote(E);
+  // Dump the record, so we can see what's going on.
+  PrintNote([&Rec](raw_ostream &OS) {
+    OS << "Dumping record for previous error:\n";
+    OS << Rec;
+  });
 }
 
 /// For an operand field named OpName: populate OpInfo.InitValue with the
diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index 0f8f1cce817002..b97b87e2117507 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -1696,9 +1696,8 @@ bool CombineRuleBuilder::emitPatFragMatchPattern(
     DenseSet<const Pattern *> &SeenPats) {
   auto StackTrace = PrettyStackTraceEmit(RuleDef, &PFP);
 
-  if (SeenPats.contains(&PFP))
+  if (!SeenPats.insert(&PFP).second)
     return true;
-  SeenPats.insert(&PFP);
 
   const auto &PF = PFP.getPatFrag();
 
@@ -1919,11 +1918,9 @@ bool CombineRuleBuilder::emitInstructionApplyPattern(
     StringMap<unsigned> &OperandToTempRegID) {
   auto StackTrace = PrettyStackTraceEmit(RuleDef, &P);
 
-  if (SeenPats.contains(&P))
+  if (!SeenPats.insert(&P).second)
     return true;
 
-  SeenPats.insert(&P);
-
   // First, render the uses.
   for (auto &Op : P.named_operands()) {
     if (Op.isDef())
@@ -2188,11 +2185,9 @@ bool CombineRuleBuilder::emitCodeGenInstructionMatchPattern(
     OperandMapperFnRef OperandMapper) {
   auto StackTrace = PrettyStackTraceEmit(RuleDef, &P);
 
-  if (SeenPats.contains(&P))
+  if (!SeenPats.insert(&P).second)
     return true;
 
-  SeenPats.insert(&P);
-
   IM.addPredicate<InstructionOpcodeMatcher>(&P.getInst());
   declareInstExpansion(CE, IM, P.getName());
 
diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp
index bda97c61d3d581..71a6ecd0b4882a 100644
--- a/llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -14,7 +14,6 @@
 #include "Basic/SequenceToOffsetTable.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/CommandLine.h"
@@ -122,7 +121,8 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
   // Find the TargetSet for which to generate enums. There will be an initial
   // set with an empty target prefix which will include target independent
   // intrinsics like dbg.value.
-  const CodeGenIntrinsicTable::TargetSet *Set = nullptr;
+  using TargetSet = CodeGenIntrinsicTable::TargetSet;
+  const TargetSet *Set = nullptr;
   for (const auto &Target : Ints.Targets) {
     if (Target.Name == IntrinsicPrefix) {
       Set = &Target;
@@ -130,13 +130,15 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
     }
   }
   if (!Set) {
-    std::vector<std::string> KnownTargets;
-    for (const auto &Target : Ints.Targets)
-      if (!Target.Name.empty())
-        KnownTargets.push_back(Target.Name.str());
-    PrintFatalError("tried to generate intrinsics for unknown target " +
-                    IntrinsicPrefix +
-                    "\nKnown targets are: " + join(KnownTargets, ", ") + "\n");
+    // The first entry is for target independent intrinsics, so drop it.
+    auto KnowTargets = ArrayRef<TargetSet>(Ints.Targets).drop_front();
+    PrintFatalError([KnowTargets](raw_ostream &OS) {
+      OS << "tried to generate intrinsics for unknown target "
+         << IntrinsicPrefix << "\nKnown targets are: ";
+      interleaveComma(KnowTargets, OS,
+                      [&OS](const TargetSet &Target) { OS << Target.Name; });
+      OS << '\n';
+    });
   }
 
   // Generate a complete header for target specific intrinsics.
diff --git a/mlir/include/mlir/Dialect/Vector/IR/VectorAttributes.td b/mlir/include/mlir/Dialect/Vector/IR/VectorAttributes.td
index 0f08f61d7b2575..bcf53dafbce9bb 100644
--- a/mlir/include/mlir/Dialect/Vector/IR/VectorAttributes.td
+++ b/mlir/include/mlir/Dialect/Vector/IR/VectorAttributes.td
@@ -17,21 +17,21 @@ include "mlir/Dialect/Vector/IR/Vector.td"
 include "mlir/IR/EnumAttr.td"
 
 // The "kind" of combining function for contractions and reductions.
-def COMBINING_KIND_ADD : I32BitEnumAttrCaseBit<"ADD", 0, "add">;
-def COMBINING_KIND_MUL : I32BitEnumAttrCaseBit<"MUL", 1, "mul">;
-def COMBINING_KIND_MINUI : I32BitEnumAttrCaseBit<"MINUI", 2, "minui">;
-def COMBINING_KIND_MINSI : I32BitEnumAttrCaseBit<"MINSI", 3, "minsi">;
-def COMBINING_KIND_MINNUMF : I32BitEnumAttrCaseBit<"MINNUMF", 4, "minnumf">;
-def COMBINING_KIND_MAXUI : I32BitEnumAttrCaseBit<"MAXUI", 5, "maxui">;
-def COMBINING_KIND_MAXSI : I32BitEnumAttrCaseBit<"MAXSI", 6, "maxsi">;
-def COMBINING_KIND_MAXNUMF : I32BitEnumAttrCaseBit<"MAXNUMF", 7, "maxnumf">;
-def COMBINING_KIND_AND : I32BitEnumAttrCaseBit<"AND", 8, "and">;
-def COMBINING_KIND_OR  : I32BitEnumAttrCaseBit<"OR", 9, "or">;
-def COMBINING_KIND_XOR : I32BitEnumAttrCaseBit<"XOR", 10, "xor">;
-def COMBINING_KIND_MINIMUMF : I32BitEnumAttrCaseBit<"MINIMUMF", 11, "minimumf">;
-def COMBINING_KIND_MAXIMUMF : I32BitEnumAttrCaseBit<"MAXIMUMF", 12, "maximumf">;
+def COMBINING_KIND_ADD : I32EnumAttrCase<"ADD", 0, "add">;
+def COMBINING_KIND_MUL : I32EnumAttrCase<"MUL", 1, "mul">;
+def COMBINING_KIND_MINUI : I32EnumAttrCase<"MINUI", 2, "minui">;
+def COMBINING_KIND_MINSI : I32EnumAttrCase<"MINSI", 3, "minsi">;
+def COMBINING_KIND_MINNUMF : I32EnumAttrCase<"MINNUMF", 4, "minnumf">;
+def COMBINING_KIND_MAXUI : I32EnumAttrCase<"MAXUI", 5, "maxui">;
+def COMBINING_KIND_MAXSI : I32EnumAttrCase<"MAXSI", 6, "maxsi">;
+def COMBINING_KIND_MAXNUMF : I32EnumAttrCase<"MAXNUMF", 7, "maxnumf">;
+def COMBINING_KIND_AND : I32EnumAttrCase<"AND", 8, "and">;
+def COMBINING_KIND_OR  : I32EnumAttrCase<"OR", 9, "or">;
+def COMBINING_KIND_XOR : I32EnumAttrCase<"XOR", 10, "xor">;
+def COMBINING_KIND_MINIMUMF : I32EnumAttrCase<"MINIMUMF", 11, "minimumf">;
+def COMBINING_KIND_MAXIMUMF : I32EnumAttrCase<"MAXIMUMF", 12, "maximumf">;
 
-def CombiningKind : I32BitEnumAttr<
+def CombiningKind : I32EnumAttr<
     "CombiningKind",
     "Kind of combining function for contractions and reductions",
     [COMBINING_KIND_ADD, COMBINING_KIND_MUL, COMBINING_KIND_MINUI,