[bsp/bl808] add: drv_gpio

bsp/bl808/m0/drivers/SConscript

@@ -15,8 +15,8 @@ if GetDepend(['RT_USING_SERIAL']):
     else:
         src += ['drv_uart.c']
 
-# if GetDepend('RT_USING_PIN'):
-#     src += ['drv_gpio.c']
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
 
 # if GetDepend('BSP_USING_LCD'):
 #     src += ['drv_lcd.c']

bsp/bl808/m0/drivers/board.c

@@ -76,6 +76,11 @@ void rt_hw_board_init(void)
     rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
 #endif
 
+    /* GPIO driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
     /* UART driver initialization is open by default */
 #ifdef RT_USING_SERIAL
     rt_hw_uart_init();

bsp/bl808/m0/drivers/drv_gpio.c

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/01/5      chushicheng  first version
+ *
+ */
+
+#include "drv_gpio.h"
+#include <stdbool.h>
+#include "bl808_gpio.h"
+#include "bl808_glb.h"
+#include "bl808.h"
+
+#ifdef RT_USING_PIN
+
+#define DBG_TAG              "drv.gpio"
+#define DBG_LVL               DBG_INFO
+#include <rtdbg.h>
+
+static void GPIO0_IRQHandler(void);
+
+struct gpio_int_cfg_private {
+    slist_t list;
+    uint32_t pin;
+    void (*hdr)(uint32_t pin);
+};
+
+static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head);
+
+
+static void bl808_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    GLB_GPIO_Write(pin, value);
+}
+
+static int bl808_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    value = GLB_GPIO_Read(pin);;
+    return value;
+}
+
+static void bl808_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+        GLB_GPIO_Cfg_Type gpio_cfg;
+
+    gpio_cfg.gpioFun = GPIO_FUN_GPIO;
+    gpio_cfg.gpioPin = pin;
+    gpio_cfg.drive = 0;
+    gpio_cfg.smtCtrl = 1;
+    gpio_cfg.outputMode = 0;
+
+    switch (mode) {
+        case GPIO_OUTPUT_MODE:
+            gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+            gpio_cfg.pullType = GPIO_PULL_NONE;
+            break;
+
+        case GPIO_OUTPUT_PP_MODE:
+            gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+            gpio_cfg.pullType = GPIO_PULL_UP;
+            break;
+
+        case GPIO_OUTPUT_PD_MODE:
+            gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
+            gpio_cfg.pullType = GPIO_PULL_DOWN;
+            break;
+
+        case GPIO_INPUT_MODE:
+            gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+            gpio_cfg.pullType = GPIO_PULL_NONE;
+            break;
+
+        case GPIO_INPUT_PP_MODE:
+            gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+            gpio_cfg.pullType = GPIO_PULL_UP;
+            break;
+
+        case GPIO_INPUT_PD_MODE:
+            gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+            gpio_cfg.pullType = GPIO_PULL_DOWN;
+            break;
+        case GPIO_HZ_MODE:
+            GLB_GPIO_Set_HZ(pin);
+        default:
+            CPU_Interrupt_Disable(GPIO_INT0_IRQn);
+            GLB_GPIO_IntMask(pin, MASK);
+
+            GLB_GPIO_INT_Cfg_Type intCfg;
+
+            intCfg.gpioPin = pin;
+            intCfg.intMask = MASK;
+
+            gpio_cfg.gpioMode = GPIO_MODE_INPUT;
+
+            if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_DOWN;
+                intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE;
+            }
+            else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_UP;
+                intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE;
+            }
+            else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_DOWN;
+                intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL;
+            }
+            else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_UP;
+                intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL;
+            }
+            else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_DOWN;
+                intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE;
+            }
+            else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_UP;
+                intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE;
+            }
+            else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_NONE;
+                intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE;
+            }
+            else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_DOWN;
+                intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL;
+            }
+            else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) {
+                gpio_cfg.pullType = GPIO_PULL_UP;
+                intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL;
+            }
+
+            GLB_GPIO_Int_Init(&intCfg);
+            break;
+    }
+
+    GLB_GPIO_Init(&gpio_cfg);
+}
+
+
+static rt_err_t bl808_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                   rt_uint32_t irq_mode, void (*hdr)(void *args), void *args)
+{
+    struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private));
+    int_cfg->hdr = hdr;
+    int_cfg->pin = pin;
+    slist_add_tail(&gpio_int_head, &int_cfg->list);
+    CPU_Interrupt_Disable(GPIO_INT0_IRQn);
+    Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO0_IRQHandler);
+    CPU_Interrupt_Enable(GPIO_INT0_IRQn);
+    return RT_EOK;
+}
+
+
+static rt_err_t bl808_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                   rt_uint32_t enabled)
+{
+    if (enabled) {
+        GLB_GPIO_IntMask(pin, UNMASK);
+    } else {
+        GLB_GPIO_IntMask(pin, MASK);
+    }
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _bl808_pin_ops =
+{
+    bl808_pin_mode,
+    bl808_pin_write,
+    bl808_pin_read,
+    bl808_pin_attach_irq,
+    bl808_pin_irq_enable,
+    NULL,
+};
+
+int rt_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &_bl808_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+/* irq handle */
+void GPIO0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    // GPIO_INT0_IRQHandler();
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_PIN */

bsp/bl808/m0/drivers/drv_gpio.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/01/5      chushicheng  first version
+ *
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <board.h>
+#include <rtdevice.h>
+#include "drv_device.h"
+
+#define GPIO_OUTPUT_MODE                         0
+#define GPIO_OUTPUT_PP_MODE                      1
+#define GPIO_OUTPUT_PD_MODE                      2
+#define GPIO_INPUT_MODE                          3
+#define GPIO_INPUT_PP_MODE                       4
+#define GPIO_INPUT_PD_MODE                       5
+#define GPIO_ASYNC_RISING_TRIGER_INT_MODE        6
+#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE       7
+#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE           8
+#define GPIO_ASYNC_LOW_LEVEL_INT_MODE            9
+#define GPIO_SYNC_RISING_TRIGER_INT_MODE         10
+#define GPIO_SYNC_FALLING_TRIGER_INT_MODE        11
+#define GPIO_SYNC_RISING_FALLING_TRIGER_INT_MODE 12
+#define GPIO_SYNC_HIGH_LEVEL_INT_MODE            13
+#define GPIO_SYNC_LOW_LEVEL_INT_MODE             14
+#define GPIO_HZ_MODE                             15
+
+
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */

bsp/bl808/m0/libraries/SConscript

@@ -91,6 +91,8 @@ src += Split("""
 """)
 
 path += [cwd + r'/platform/hosal/bl808_e907_hal']
+path += [cwd + r'/platform/soc/bl808/bl808_e907_std/common/device',
+		 cwd + r'/platform/soc/bl808/bl808_e907_std/common/list']
 
 libpath = []
 libs = []

bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.c

@@ -85,7 +85,7 @@ static int __hw_init(bl_audio_dev_t *p_dev)
         AUIDO_RAMP_RATE_2_FS,
         AUIDO_ZERO_CROSS_RATE_2_FS,
     };
- 
+
     GLB_Config_AUDIO_PLL(GLB_XTAL_40M, audioPllCfg_451P584M);
     /* ungate audio */
     GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_AUDIO);
@@ -202,7 +202,7 @@ static int __hw_init(bl_audio_dev_t *p_dev)
 static void __audio_lli_init(bl_audio_dev_t *p_dev)
 {
     p_dev->lli_tx_buffer_size = p_dev->lli_tx_buffer_size / 2;
-    
+
     switch (p_dev->playBitWidth) {
         case AUDIO_BIT_WIDTH_16:
             dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS;
@@ -230,7 +230,7 @@ static void __audio_lli_init(bl_audio_dev_t *p_dev)
             //private_bflb_platform_printf("BIT WIDTH Is Invaild\r\n");
             break;
     }
- 
+
     p_dev->lli_tx_list[0].srcDmaAddr = (uint32_t)p_dev->lli_tx_buffer;
     p_dev->lli_tx_list[0].destDmaAddr = AUDIO_TX_FIFO_ADDR;
     p_dev->lli_tx_list[0].nextLLI = (uint32_t)&p_dev->lli_tx_list[1];
@@ -246,7 +246,7 @@ static void __audio_lli_init(bl_audio_dev_t *p_dev)
 
     if (p_dev->rx_enable) {
         p_dev->lli_rx_buffer_size = p_dev->lli_rx_buffer_size / 2;
- 
+
         switch (p_dev->playBitWidth) {
             case AUDIO_BIT_WIDTH_16:
                 dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS;

bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.c

@@ -47,14 +47,14 @@ PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg,
     if(ptEntry==NULL||ptStuff==NULL){
         return PT_ERROR_PARAMETER;
     }
-    
+
     ptTable=&ptStuff->ptTable;
     ptEntries=ptStuff->ptEntries;
-    
+
     if(targetTableID==PT_TABLE_ID_INVALID){
         return PT_ERROR_TABLE_NOT_VALID;
     }
-    
+
     if(targetTableID==PT_TABLE_ID_0){
         writeAddr=BFLB_PT_TABLE0_ADDRESS;
     }else{
@@ -75,17 +75,17 @@ PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg,
             return PT_ERROR_ENTRY_UPDATE_FAIL;
         }
     }
-    
+
     /* Prepare write back to flash */
     /* Update age */
     ptTable->age++;
     ptTable->crc32=BFLB_Soft_CRC32((uint8_t*)ptTable,sizeof(PtTable_Config)-4);
-    
+
     /* Update entries CRC */
     entriesLen=ptTable->entryCnt*sizeof(PtTable_Entry_Config);
     pCrc32=(uint32_t *)((uint32_t)ptEntries+entriesLen);
     *pCrc32=BFLB_Soft_CRC32((uint8_t *)&ptEntries[0],entriesLen);
-    
+
     /* Write back to flash */
     /* Erase flash first */
     ret=bl_flash_erase(writeAddr,sizeof(PtTable_Config)+entriesLen+4);
@@ -108,7 +108,7 @@ PtTable_Error_Type PtTable_Get_Active_Entries(PtTable_Stuff_Config *ptStuff,
                                             PtTable_Entry_Config *ptEntry)
 {
     uint32_t i=0;
-    
+
     if(ptStuff==NULL||ptEntry==NULL){
         return PT_ERROR_PARAMETER;
     }
@@ -130,16 +130,16 @@ PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptSt
 
     if(ptStuff==NULL||ptEntry==NULL){
         return PT_ERROR_PARAMETER;
-    }   
+    }
     for (i=0; i < ptStuff->ptTable.entryCnt; i++) {
         if (strlen((char *)ptStuff->ptEntries[i].name) == len &&
-        memcmp((char *)ptStuff->ptEntries[i].name,(char *)name,len) == 0){ 
+        memcmp((char *)ptStuff->ptEntries[i].name,(char *)name,len) == 0){
         //BL602_MemCpy_Fast(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config));
         /*FIXME :need fast memory copy*/
         memcpy(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config));
         return PT_ERROR_SUCCESS;
-        }   
-    }   
+        }
+    }
     return PT_ERROR_ENTRY_NOT_FOUND;
 }
 

bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.h

@@ -184,8 +184,8 @@ PtTable_ID_Type targetTableID,
                                         PtTable_Stuff_Config *ptStuff,
 PtTable_Entry_Config *ptEntry);
 PtTable_Error_Type PtTable_Create(const SPI_Flash_Cfg_Type *pFlashCfg,PtTable_ID_Type ptID);
-PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff,                                                             
-                                                    uint8_t *name,                                                     
+PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff,
+                                                    uint8_t *name,
                                                     PtTable_Entry_Config *ptEntry);
 
 /*@} end of group PARTITION_Public_Functions */