diff --git a/blake2/src/as_bytes.rs b/blake2/src/as_bytes.rs
index 02cca6bba..76342c92e 100644
--- a/blake2/src/as_bytes.rs
+++ b/blake2/src/as_bytes.rs
@@ -8,6 +8,11 @@
 use core::mem;
 use core::slice;
 
+/// # Safety
+///
+/// T is safe to implement Safe if any bit level manipulation of its memory region
+/// (including possible alignment padding) still yields a valid instance of T
+/// and its use is always sound.
 pub unsafe trait Safe {}
 
 pub trait AsBytes {
diff --git a/blake2/src/macros.rs b/blake2/src/macros.rs
index 4a014716d..127df037c 100644
--- a/blake2/src/macros.rs
+++ b/blake2/src/macros.rs
@@ -109,7 +109,7 @@ macro_rules! blake2_impl {
 
                 #[inline(always)]
                 fn quarter_round(v: &mut [$vec; 4], rd: u32, rb: u32, m: $vec) {
-                    v[0] = v[0].wrapping_add(v[1]).wrapping_add(m.from_le());
+                    v[0] = v[0].wrapping_add(v[1]).wrapping_add($vec::from_le(m));
                     v[3] = (v[3] ^ v[0]).rotate_right_const(rd);
                     v[2] = v[2].wrapping_add(v[3]);
                     v[1] = (v[1] ^ v[2]).rotate_right_const(rb);
diff --git a/blake2/src/simd.rs b/blake2/src/simd.rs
index b6fb15a40..4f1e6b8f1 100644
--- a/blake2/src/simd.rs
+++ b/blake2/src/simd.rs
@@ -15,7 +15,7 @@ pub use self::simdty::{u32x4, u64x4};
 pub trait Vector4<T>: Copy {
     fn gather(src: &[T], i0: usize, i1: usize, i2: usize, i3: usize) -> Self;
 
-    fn from_le(self) -> Self;
+    fn from_le(vec: Self) -> Self;
     fn to_le(self) -> Self;
 
     fn wrapping_add(self, rhs: Self) -> Self;
@@ -50,8 +50,8 @@ macro_rules! impl_vector4 {
 
             #[cfg(target_endian = "little")]
             #[inline(always)]
-            fn from_le(self) -> Self {
-                self
+            fn from_le(vec: Self) -> Self {
+                vec
             }
 
             #[cfg(not(target_endian = "little"))]
diff --git a/sha1/src/compress/soft.rs b/sha1/src/compress/soft.rs
index f4777e7cc..0b9fb2701 100644
--- a/sha1/src/compress/soft.rs
+++ b/sha1/src/compress/soft.rs
@@ -201,6 +201,7 @@ fn sha1_digest_block_u32(state: &mut [u32; 5], block: &[u32; 16]) {
     let mut w1 = [block[4], block[5], block[6], block[7]];
     let mut w2 = [block[8], block[9], block[10], block[11]];
     let mut w3 = [block[12], block[13], block[14], block[15]];
+    #[allow(clippy::needless_late_init)]
     let mut w4;
 
     let mut h0 = [state[0], state[1], state[2], state[3]];
diff --git a/sha1/src/compress/x86.rs b/sha1/src/compress/x86.rs
index d30234249..4dcd56b8a 100644
--- a/sha1/src/compress/x86.rs
+++ b/sha1/src/compress/x86.rs
@@ -52,6 +52,7 @@ unsafe fn digest_blocks(state: &mut [u32; 5], blocks: &[[u8; 64]]) {
         let mut w1 = _mm_shuffle_epi8(_mm_loadu_si128(block_ptr.offset(1)), MASK);
         let mut w2 = _mm_shuffle_epi8(_mm_loadu_si128(block_ptr.offset(2)), MASK);
         let mut w3 = _mm_shuffle_epi8(_mm_loadu_si128(block_ptr.offset(3)), MASK);
+        #[allow(clippy::needless_late_init)]
         let mut w4;
 
         let mut h0 = state_abcd;
diff --git a/whirlpool/src/lib.rs b/whirlpool/src/lib.rs
index 84d8c7012..996c9b797 100644
--- a/whirlpool/src/lib.rs
+++ b/whirlpool/src/lib.rs
@@ -126,6 +126,8 @@ impl WhirlpoolCore {
     }
 }
 
+// derivable impl does not inline
+#[allow(clippy::derivable_impls)]
 impl Default for WhirlpoolCore {
     #[inline]
     fn default() -> Self {