From 993df174ee10ed1124a1cbdc1c463d93dd181e1f Mon Sep 17 00:00:00 2001 From: bbinxie Date: Thu, 24 Jan 2019 10:44:19 +0800 Subject: [PATCH 1/4] [Celestica]: Update port led code for seastone-xp (#2476) --- .../x86_64-cel_seastone-r0/led-code/ledcode0 | 29 ++++++++++--------- .../x86_64-cel_seastone-r0/led-code/ledcode1 | 29 ++++++++++--------- 2 files changed, 32 insertions(+), 26 deletions(-) diff --git a/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode0 b/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode0 index df26e4abd679..829087013a2a 100755 --- a/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode0 +++ b/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode0 @@ -1,13 +1,16 @@ -02 20 28 67 72 12 30 80 D1 74 02 02 00 28 67 72 -12 20 80 D1 74 0D 02 30 28 67 72 02 31 28 67 72 -02 32 28 67 72 02 33 28 67 72 02 34 28 67 72 02 -35 28 67 72 02 36 28 67 72 02 37 28 67 72 02 38 -28 67 72 02 39 28 67 72 02 3A 28 67 72 02 3B 28 -67 72 02 3C 28 67 72 02 3D 28 67 72 02 3E 28 67 -72 02 3F 28 67 72 12 E0 85 05 D2 05 71 70 52 00 -3A 80 67 98 75 B0 77 78 67 9F 75 7E 77 8B 28 67 -A6 75 B6 16 E0 DA 04 74 B0 77 B6 28 67 A6 75 B3 -16 E0 DA 04 74 B0 77 B3 12 A0 F8 15 1A 00 57 12 -A0 F8 15 1A 01 57 28 32 00 32 01 B7 97 77 AF 57 -67 B9 57 67 C7 57 67 C0 57 32 0F 87 32 0F 87 57 -32 0F 87 32 0E 87 57 32 0E 87 32 0E 87 57 00 00 + 02 20 28 67 2A 12 30 D1 74 02 02 00 28 67 2A 12 + 20 D1 74 0C 02 30 28 67 2A 12 40 D1 74 16 12 E0 + 85 05 D2 05 71 28 52 00 3A 80 67 7C 75 30 77 42 + 67 83 75 36 77 53 67 8A 75 3C 77 42 67 91 75 64 + 77 64 67 75 75 A9 28 67 9F 75 B4 16 E0 DA 04 74 + A9 77 B4 67 75 75 BF 28 67 9F 75 C6 16 E0 DA 04 + 74 BF 77 C6 67 75 75 CD 28 67 9F 75 D2 16 E0 DA + 04 74 CD 77 D2 12 A0 F8 15 1A 00 57 12 A0 F8 15 + 1A 01 57 12 A0 F8 15 1A 02 57 12 A0 F8 15 1A 03 + 57 12 A0 F8 15 1A 04 57 12 A0 F8 15 1A 05 57 28 + 32 00 32 01 B7 97 77 A8 57 67 D7 67 DE 67 DE 67 + DE F2 04 57 67 E5 67 DE 67 DE 67 DE F2 04 57 67 + D7 67 DE F2 02 57 67 E5 67 DE F2 02 57 67 D7 F2 + 01 57 67 E5 F2 01 57 32 0F 87 32 0F 87 57 32 0F + 87 32 0E 87 57 32 0E 87 32 0E 87 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode1 b/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode1 index df26e4abd679..829087013a2a 100755 --- a/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode1 +++ b/device/celestica/x86_64-cel_seastone-r0/led-code/ledcode1 @@ -1,13 +1,16 @@ -02 20 28 67 72 12 30 80 D1 74 02 02 00 28 67 72 -12 20 80 D1 74 0D 02 30 28 67 72 02 31 28 67 72 -02 32 28 67 72 02 33 28 67 72 02 34 28 67 72 02 -35 28 67 72 02 36 28 67 72 02 37 28 67 72 02 38 -28 67 72 02 39 28 67 72 02 3A 28 67 72 02 3B 28 -67 72 02 3C 28 67 72 02 3D 28 67 72 02 3E 28 67 -72 02 3F 28 67 72 12 E0 85 05 D2 05 71 70 52 00 -3A 80 67 98 75 B0 77 78 67 9F 75 7E 77 8B 28 67 -A6 75 B6 16 E0 DA 04 74 B0 77 B6 28 67 A6 75 B3 -16 E0 DA 04 74 B0 77 B3 12 A0 F8 15 1A 00 57 12 -A0 F8 15 1A 01 57 28 32 00 32 01 B7 97 77 AF 57 -67 B9 57 67 C7 57 67 C0 57 32 0F 87 32 0F 87 57 -32 0F 87 32 0E 87 57 32 0E 87 32 0E 87 57 00 00 + 02 20 28 67 2A 12 30 D1 74 02 02 00 28 67 2A 12 + 20 D1 74 0C 02 30 28 67 2A 12 40 D1 74 16 12 E0 + 85 05 D2 05 71 28 52 00 3A 80 67 7C 75 30 77 42 + 67 83 75 36 77 53 67 8A 75 3C 77 42 67 91 75 64 + 77 64 67 75 75 A9 28 67 9F 75 B4 16 E0 DA 04 74 + A9 77 B4 67 75 75 BF 28 67 9F 75 C6 16 E0 DA 04 + 74 BF 77 C6 67 75 75 CD 28 67 9F 75 D2 16 E0 DA + 04 74 CD 77 D2 12 A0 F8 15 1A 00 57 12 A0 F8 15 + 1A 01 57 12 A0 F8 15 1A 02 57 12 A0 F8 15 1A 03 + 57 12 A0 F8 15 1A 04 57 12 A0 F8 15 1A 05 57 28 + 32 00 32 01 B7 97 77 A8 57 67 D7 67 DE 67 DE 67 + DE F2 04 57 67 E5 67 DE 67 DE 67 DE F2 04 57 67 + D7 67 DE F2 02 57 67 E5 67 DE F2 02 57 67 D7 F2 + 01 57 67 E5 F2 01 57 32 0F 87 32 0F 87 57 32 0F + 87 32 0E 87 57 32 0E 87 32 0E 87 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 2acfac712cde23c636840a5d13407063026d419e Mon Sep 17 00:00:00 2001 From: Joe LeVeque Date: Wed, 23 Jan 2019 18:47:05 -0800 Subject: [PATCH 2/4] [caclmgrd] Don't crash if we find empty/null rule_props (#2475) * [caclmgrd] Don't crash if we find empty/null rule_props --- files/image_config/caclmgrd/caclmgrd | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/files/image_config/caclmgrd/caclmgrd b/files/image_config/caclmgrd/caclmgrd index a7ec952ca21f..5e8d83074de1 100755 --- a/files/image_config/caclmgrd/caclmgrd +++ b/files/image_config/caclmgrd/caclmgrd @@ -183,7 +183,15 @@ class ControlPlaneAclManager(object): for ((rule_table_name, rule_id), rule_props) in self._rules_db_info.iteritems(): if rule_table_name == table_name: - acl_rules[rule_props["PRIORITY"]] = rule_props + if not rule_props: + log_warning("rule_props for rule_id {} empty or null!".format(rule_id)) + continue + + try: + acl_rules[rule_props["PRIORITY"]] = rule_props + except KeyError: + log_error("rule_props for rule_id {} does not have key 'PRIORITY'!".format(rule_id)) + continue # If we haven't determined the IP version for this ACL table yet, # try to do it now. We determine heuristically based on whether the From 959a2ce26ce4938cc1874aed0f8b734c9bf27ed4 Mon Sep 17 00:00:00 2001 From: Joe LeVeque Date: Thu, 24 Jan 2019 13:13:19 -0800 Subject: [PATCH 3/4] [dockers] Prevent old supervisord messages from gettting re-logged to syslog (#2439) --- dockers/docker-base/etc/rsyslog.d/supervisor.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/dockers/docker-base/etc/rsyslog.d/supervisor.conf b/dockers/docker-base/etc/rsyslog.d/supervisor.conf index e6fece313efc..7c7a64d7afe0 100644 --- a/dockers/docker-base/etc/rsyslog.d/supervisor.conf +++ b/dockers/docker-base/etc/rsyslog.d/supervisor.conf @@ -5,4 +5,5 @@ $InputFileTag supervisord $InputFileStateFile state-supervisor $InputFileSeverity info $InputFileFacility local0 +$InputFilePersistStateInterval 1 $InputRunFileMonitor From 7b33538686f2694a5d159637f71bc39d869d4391 Mon Sep 17 00:00:00 2001 From: zhenggen-xu Date: Wed, 23 Jan 2019 18:47:46 -0800 Subject: [PATCH 4/4] [devices]: Support 32x50G+16x40G profile on Seastone-DX010 (#2474) The sai profile itself can support 32x50G+16x100G/40G while the initial port_config.ini uses 40G speeds for port 17-32. Signed-off-by: Zhenggen Xu --- .../Seastone-DX010-50-40/port_config.ini | 49 ++ .../Seastone-DX010-50-40/sai.profile | 1 + ...h-seastone-dx010-32x50G-16x100G.config.bcm | 499 ++++++++++++++++++ 3 files changed, 549 insertions(+) create mode 100644 device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/port_config.ini create mode 100644 device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/sai.profile create mode 100644 device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/th-seastone-dx010-32x50G-16x100G.config.bcm diff --git a/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/port_config.ini b/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/port_config.ini new file mode 100644 index 000000000000..9a2b38e6da79 --- /dev/null +++ b/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/port_config.ini @@ -0,0 +1,49 @@ +# name lanes alias index speed +Ethernet0 65,66 Eth1/1 0 50000 +Ethernet2 67,68 Eth1/2 0 50000 +Ethernet4 69,70 Eth2/1 1 50000 +Ethernet6 71,72 Eth2/2 1 50000 +Ethernet8 73,74 Eth3/1 2 50000 +Ethernet10 75,76 Eth3/2 2 50000 +Ethernet12 77,78 Eth4/1 3 50000 +Ethernet14 79,80 Eth4/2 3 50000 +Ethernet16 33,34 Eth5/1 4 50000 +Ethernet18 35,36 Eth5/2 4 50000 +Ethernet20 37,38 Eth6/1 5 50000 +Ethernet22 39,40 Eth6/2 5 50000 +Ethernet24 41,42 Eth7/1 6 50000 +Ethernet26 43,44 Eth7/2 6 50000 +Ethernet28 45,46 Eth8/1 7 50000 +Ethernet30 47,48 Eth8/2 7 50000 +Ethernet32 49,50 Eth9/1 8 50000 +Ethernet34 51,52 Eth9/2 8 50000 +Ethernet36 53,54 Eth10/1 9 50000 +Ethernet38 55,56 Eth10/2 9 50000 +Ethernet40 57,58 Eth11/1 10 50000 +Ethernet42 59,60 Eth11/2 10 50000 +Ethernet44 61,62 Eth12/1 11 50000 +Ethernet46 63,64 Eth12/2 11 50000 +Ethernet48 81,82 Eth13/1 12 50000 +Ethernet50 83,84 Eth13/2 12 50000 +Ethernet52 85,86 Eth14/1 13 50000 +Ethernet54 87,88 Eth14/2 13 50000 +Ethernet56 89,90 Eth15/1 14 50000 +Ethernet58 91,92 Eth15/2 14 50000 +Ethernet60 93,94 Eth16/1 15 50000 +Ethernet62 95,96 Eth16/2 15 50000 +Ethernet64 97,98,99,100 Eth17 16 40000 +Ethernet68 101,102,103,104 Eth18 17 40000 +Ethernet72 105,106,107,108 Eth19 18 40000 +Ethernet76 109,110,111,112 Eth20 19 40000 +Ethernet80 1,2,3,4 Eth21 20 40000 +Ethernet84 5,6,7,8 Eth22 21 40000 +Ethernet88 9,10,11,12 Eth23 22 40000 +Ethernet92 13,14,15,16 Eth24 23 40000 +Ethernet96 17,18,19,20 Eth25 24 40000 +Ethernet100 21,22,23,24 Eth26 25 40000 +Ethernet104 25,26,27,28 Eth27 26 40000 +Ethernet108 29,30,31,32 Eth28 27 40000 +Ethernet112 113,114,115,116 Eth29 28 40000 +Ethernet116 117,118,119,120 Eth30 29 40000 +Ethernet120 121,122,123,124 Eth31 30 40000 +Ethernet124 125,126,127,128 Eth32 31 40000 diff --git a/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/sai.profile b/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/sai.profile new file mode 100644 index 000000000000..3ae50f718493 --- /dev/null +++ b/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-seastone-dx010-32x50G-16x100G.config.bcm diff --git a/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/th-seastone-dx010-32x50G-16x100G.config.bcm b/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/th-seastone-dx010-32x50G-16x100G.config.bcm new file mode 100644 index 000000000000..ee9e283efe52 --- /dev/null +++ b/device/celestica/x86_64-cel_seastone-r0/Seastone-DX010-50-40/th-seastone-dx010-32x50G-16x100G.config.bcm @@ -0,0 +1,499 @@ +# Define default OS / SAL +os=unix + +# all XPORTs to XE ports +#pbmp_xport_xe=0x1fffffffe +pbmp_xport_xe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe +pbmp_oversubscribe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe + +# Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or +# L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification. +l2xmsg_mode=1 + +# Memory table size configs, enable ALPM +l2_mem_entries=8192 +l3_mem_entries=8192 +l3_alpm_enable=2 +ipv6_lpm_128b_enable=1 + +#Use MMU lossy configuration +mmu_lossless=0 + +################################################################################### +# SeaStone customized configuration +################################################################################### + +#ext mdio frequency to 495/0x80/2(1.933Mhz) or 415/0x80/2(1.62MHz) +# default is 40 +# Set external MDIO freq to 6.19MHz (495MHz) or 5.19MHz (415MHz) +#* target_freq is core_clock_freq * DIVIDEND / DIVISOR / 2 +# +rate_ext_mdio_divisor=0x80 + +# use internal rom boot +phy_ext_rom_boot=0 + +oversubscribe_mode=1 + +# Map the physical ports to logical ports +dport_map_enable=1 + +dport_map_port_68=1 +dport_map_port_69=2 + +dport_map_port_72=5 +dport_map_port_73=6 + +dport_map_port_76=9 +dport_map_port_77=10 + +dport_map_port_80=13 +dport_map_port_81=14 + +dport_map_port_34=17 +dport_map_port_35=18 + +dport_map_port_38=21 +dport_map_port_39=22 + +dport_map_port_42=25 +dport_map_port_43=26 + +dport_map_port_46=29 +dport_map_port_47=30 + +dport_map_port_50=33 +dport_map_port_51=34 + +dport_map_port_54=37 +dport_map_port_55=38 + +dport_map_port_58=41 +dport_map_port_59=42 + +dport_map_port_62=45 +dport_map_port_63=46 + +dport_map_port_84=49 +dport_map_port_85=50 + +dport_map_port_88=53 +dport_map_port_89=54 + +dport_map_port_92=57 +dport_map_port_93=58 + +dport_map_port_96=61 +dport_map_port_97=62 + +# 100G/40G ports +dport_map_port_102=65 +dport_map_port_106=69 +dport_map_port_110=73 +dport_map_port_114=77 +dport_map_port_1=81 +dport_map_port_5=85 +dport_map_port_9=89 +dport_map_port_13=93 +dport_map_port_17=97 +dport_map_port_21=101 +dport_map_port_25=105 +dport_map_port_29=109 +dport_map_port_118=113 +dport_map_port_122=117 +dport_map_port_126=121 +dport_map_port_130=125 + + +# port/lane mapping, 32x50G + 16x100G +portmap_68=65:50:2 +portmap_69=67:50:2 + +portmap_72=69:50:2 +portmap_73=71:50:2 + +portmap_76=73:50:2 +portmap_77=75:50:2 + +portmap_80=77:50:2 +portmap_81=79:50:2 + +portmap_34=33:50:2 +portmap_35=35:50:2 + +portmap_38=37:50:2 +portmap_39=39:50:2 + +portmap_42=41:50:2 +portmap_43=43:50:2 + +portmap_46=45:50:2 +portmap_47=47:50:2 + +portmap_50=49:50:2 +portmap_51=51:50:2 + +portmap_54=53:50:2 +portmap_55=55:50:2 + +portmap_58=57:50:2 +portmap_59=59:50:2 + +portmap_62=61:50:2 +portmap_63=63:50:2 + +portmap_84=81:50:2 +portmap_85=83:50:2 + +portmap_88=85:50:2 +portmap_89=87:50:2 + +portmap_92=89:50:2 +portmap_93=91:50:2 + +portmap_96=93:50:2 +portmap_97=95:50:2 + +portmap_102=97:100:4 +portmap_106=101:100:4 +portmap_110=105:100:4 +portmap_114=109:100:4 +portmap_1=1:100:4 +portmap_5=5:100:4 +portmap_9=9:100:4 +portmap_13=13:100:4 +portmap_17=17:100:4 +portmap_21=21:100:4 +portmap_25=25:100:4 +portmap_29=29:100:4 +portmap_118=113:100:4 +portmap_122=117:100:4 +portmap_126=121:100:4 +portmap_130=125:100:4 + + +#WC16 +xgxs_tx_lane_map_68=0x3201 +xgxs_rx_lane_map_68=0x2310 +xgxs_tx_lane_map_69=0x3201 +xgxs_rx_lane_map_69=0x2310 + + +#WC17 +xgxs_tx_lane_map_72=0x3201 +xgxs_rx_lane_map_72=0x2301 +xgxs_tx_lane_map_73=0x3201 +xgxs_rx_lane_map_73=0x2301 + +#WC18 +xgxs_tx_lane_map_76=0x0132 +xgxs_rx_lane_map_76=0x0123 +xgxs_tx_lane_map_77=0x0132 +xgxs_rx_lane_map_77=0x0123 + +#WC19 +xgxs_tx_lane_map_80=0x2031 +xgxs_rx_lane_map_80=0x1320 +xgxs_tx_lane_map_81=0x2031 +xgxs_rx_lane_map_81=0x1320 + +#WC8 +xgxs_tx_lane_map_34=0x3021 +xgxs_rx_lane_map_34=0x0213 +xgxs_tx_lane_map_35=0x3021 +xgxs_rx_lane_map_35=0x0213 + +#WC9 +xgxs_tx_lane_map_38=0x3210 +xgxs_rx_lane_map_38=0x1023 +xgxs_tx_lane_map_39=0x3210 +xgxs_rx_lane_map_39=0x1023 + +#WC10 +xgxs_tx_lane_map_42=0x2310 +xgxs_rx_lane_map_42=0x3210 +xgxs_tx_lane_map_43=0x2310 +xgxs_rx_lane_map_43=0x3210 + +#WC11 +xgxs_tx_lane_map_46=0x1032 +xgxs_rx_lane_map_46=0x1302 +xgxs_tx_lane_map_47=0x1032 +xgxs_rx_lane_map_47=0x1302 + +#WC12 +xgxs_tx_lane_map_50=0x3201 +xgxs_rx_lane_map_50=0x0213 +xgxs_tx_lane_map_51=0x3201 +xgxs_rx_lane_map_51=0x0213 + + +#WC13 +xgxs_tx_lane_map_54=0x2301 +xgxs_rx_lane_map_54=0x2310 +xgxs_tx_lane_map_55=0x2301 +xgxs_rx_lane_map_55=0x2310 + +#WC14 +xgxs_tx_lane_map_58=0x3201 +xgxs_rx_lane_map_58=0x0213 +xgxs_tx_lane_map_59=0x3201 +xgxs_rx_lane_map_59=0x0213 + +#WC15 +xgxs_tx_lane_map_62=0x1302 +xgxs_rx_lane_map_62=0x2310 +xgxs_tx_lane_map_63=0x1302 +xgxs_rx_lane_map_63=0x2310 + +#WC20 +xgxs_tx_lane_map_84=0x0213 +xgxs_rx_lane_map_84=0x2301 +xgxs_tx_lane_map_85=0x0213 +xgxs_rx_lane_map_85=0x2301 + +#WC21 +xgxs_tx_lane_map_88=0x0132 +xgxs_rx_lane_map_88=0x3210 +xgxs_tx_lane_map_89=0x0132 +xgxs_rx_lane_map_89=0x3210 + +#WC22 +xgxs_tx_lane_map_92=0x0132 +xgxs_rx_lane_map_92=0x2031 +xgxs_tx_lane_map_93=0x0132 +xgxs_rx_lane_map_93=0x2031 + +#WC23 +xgxs_tx_lane_map_96=0x2031 +xgxs_rx_lane_map_96=0x3201 +xgxs_tx_lane_map_97=0x2031 +xgxs_rx_lane_map_97=0x3201 + + +#WC24 +xgxs_tx_lane_map_102=0x0132 +xgxs_rx_lane_map_102=0x2301 + +#WC25 +xgxs_tx_lane_map_106=0x0132 +xgxs_rx_lane_map_106=0x3201 + +#WC26 +xgxs_tx_lane_map_110=0x0132 +xgxs_rx_lane_map_110=0x2031 + +#WC27 +xgxs_tx_lane_map_114=0x2031 +xgxs_rx_lane_map_114=0x2301 + +#WC0 +xgxs_tx_lane_map_1=0x3210 +xgxs_rx_lane_map_1=0x3120 + +#WC1 +xgxs_tx_lane_map_5=0x0132 +xgxs_rx_lane_map_5=0x1023 + +#WC2 +xgxs_tx_lane_map_9=0x3201 +xgxs_rx_lane_map_9=0x3120 + +#WC3 +xgxs_tx_lane_map_13=0x2031 +xgxs_rx_lane_map_13=0x1032 + +#WC4 +xgxs_tx_lane_map_17=0x2310 +xgxs_rx_lane_map_17=0x3210 + +#WC5 +xgxs_tx_lane_map_21=0x2301 +xgxs_rx_lane_map_21=0x3120 + +#WC6 +xgxs_tx_lane_map_25=0x3201 +xgxs_rx_lane_map_25=0x0213 + +#WC7 +xgxs_tx_lane_map_29=0x1302 +xgxs_rx_lane_map_29=0x1023 + +#WC28 +xgxs_tx_lane_map_118=0x1320 +xgxs_rx_lane_map_118=0x1302 + +#WC29 +xgxs_tx_lane_map_122=0x1032 +xgxs_rx_lane_map_122=0x1023 + +#WC30 +xgxs_tx_lane_map_126=0x3120 +xgxs_rx_lane_map_126=0x3120 + +#WC31 +xgxs_tx_lane_map_130=0x1302 +xgxs_rx_lane_map_130=0x2310 + + +#Polarity flip settings +#WC16 +phy_xaui_tx_polarity_flip_68=0x0000 +phy_xaui_rx_polarity_flip_68=0x0000 +phy_xaui_tx_polarity_flip_69=0x0000 +phy_xaui_rx_polarity_flip_69=0x0000 + +#WC17 +phy_xaui_tx_polarity_flip_72=0x0001 +phy_xaui_rx_polarity_flip_72=0x0002 +phy_xaui_tx_polarity_flip_73=0x0003 +phy_xaui_rx_polarity_flip_73=0x0000 + +#WC18 +phy_xaui_tx_polarity_flip_76=0x0003 +phy_xaui_rx_polarity_flip_76=0x0000 +phy_xaui_tx_polarity_flip_77=0x0003 +phy_xaui_rx_polarity_flip_77=0x0000 + +#WC19 +phy_xaui_tx_polarity_flip_80=0x0003 +phy_xaui_rx_polarity_flip_80=0x0003 +phy_xaui_tx_polarity_flip_81=0x0003 +phy_xaui_rx_polarity_flip_81=0x0003 + +#WC8 +phy_xaui_tx_polarity_flip_34=0x0002 +phy_xaui_rx_polarity_flip_34=0x0000 +phy_xaui_tx_polarity_flip_35=0x0003 +phy_xaui_rx_polarity_flip_35=0x0000 + +#WC9 +phy_xaui_tx_polarity_flip_38=0x0000 +phy_xaui_rx_polarity_flip_38=0x0000 +phy_xaui_tx_polarity_flip_39=0x0002 +phy_xaui_rx_polarity_flip_39=0x0000 + +#WC10 +phy_xaui_tx_polarity_flip_42=0x0001 +phy_xaui_rx_polarity_flip_42=0x0000 +phy_xaui_tx_polarity_flip_43=0x0003 +phy_xaui_rx_polarity_flip_43=0x0000 + +#WC11 +phy_xaui_tx_polarity_flip_46=0x0000 +phy_xaui_rx_polarity_flip_46=0x0000 +phy_xaui_tx_polarity_flip_47=0x0000 +phy_xaui_rx_polarity_flip_47=0x0000 + +#WC12 +phy_xaui_tx_polarity_flip_50=0x0002 +phy_xaui_rx_polarity_flip_50=0x0000 +phy_xaui_tx_polarity_flip_51=0x0000 +phy_xaui_rx_polarity_flip_51=0x0000 + +#WC13 +phy_xaui_tx_polarity_flip_54=0x0002 +phy_xaui_rx_polarity_flip_54=0x0000 +phy_xaui_tx_polarity_flip_55=0x0000 +phy_xaui_rx_polarity_flip_55=0x0000 + +#WC14 +phy_xaui_tx_polarity_flip_58=0x0000 +phy_xaui_rx_polarity_flip_58=0x0000 +phy_xaui_tx_polarity_flip_59=0x0000 +phy_xaui_rx_polarity_flip_59=0x0000 + +#WC15 +phy_xaui_tx_polarity_flip_62=0x0002 +phy_xaui_rx_polarity_flip_62=0x0003 +phy_xaui_tx_polarity_flip_63=0x0002 +phy_xaui_rx_polarity_flip_63=0x0003 + +#WC20 +phy_xaui_tx_polarity_flip_84=0x0003 +phy_xaui_rx_polarity_flip_84=0x0002 +phy_xaui_tx_polarity_flip_85=0x0001 +phy_xaui_rx_polarity_flip_85=0x0003 + +#WC21 +phy_xaui_tx_polarity_flip_88=0x0001 +phy_xaui_rx_polarity_flip_88=0x0001 +phy_xaui_tx_polarity_flip_89=0x0003 +phy_xaui_rx_polarity_flip_89=0x0003 + +#WC22 +phy_xaui_tx_polarity_flip_92=0x0003 +phy_xaui_rx_polarity_flip_92=0x0000 +phy_xaui_tx_polarity_flip_93=0x0003 +phy_xaui_rx_polarity_flip_93=0x0002 + +#WC23 +phy_xaui_tx_polarity_flip_96=0x0001 +phy_xaui_rx_polarity_flip_96=0x0000 +phy_xaui_tx_polarity_flip_97=0x0001 +phy_xaui_rx_polarity_flip_97=0x0000 + +#WC24 +phy_xaui_tx_polarity_flip_102=0x0000 +phy_xaui_rx_polarity_flip_102=0x000F + +#WC25 +phy_xaui_tx_polarity_flip_106=0x000F +phy_xaui_rx_polarity_flip_106=0x0000 + +#WC26 +phy_xaui_tx_polarity_flip_110=0x000F +phy_xaui_rx_polarity_flip_110=0x000F + +#WC27 +phy_xaui_tx_polarity_flip_114=0x000F +phy_xaui_rx_polarity_flip_114=0x0007 + +#WC0 +phy_xaui_tx_polarity_flip_1=0x0003 +phy_xaui_rx_polarity_flip_1=0x000F + +#WC1 +phy_xaui_tx_polarity_flip_5=0x0007 +phy_xaui_rx_polarity_flip_5=0x0000 + +#WC2 +phy_xaui_tx_polarity_flip_9=0x0002 +phy_xaui_rx_polarity_flip_9=0x0008 + +#WC3 +phy_xaui_tx_polarity_flip_13=0x000F +phy_xaui_rx_polarity_flip_13=0x0000 + +#WC4 +phy_xaui_tx_polarity_flip_17=0x0007 +phy_xaui_rx_polarity_flip_17=0x0000 + +#WC5 +phy_xaui_tx_polarity_flip_21=0x0000 +phy_xaui_rx_polarity_flip_21=0x0000 + +#WC6 +phy_xaui_tx_polarity_flip_25=0x0002 +phy_xaui_rx_polarity_flip_25=0x0005 + +#WC7 +phy_xaui_tx_polarity_flip_29=0x0002 +phy_xaui_rx_polarity_flip_29=0x0000 + +#WC28 +phy_xaui_tx_polarity_flip_118=0x000F +phy_xaui_rx_polarity_flip_118=0x000F + +#WC29 +phy_xaui_tx_polarity_flip_122=0x0004 +phy_xaui_rx_polarity_flip_122=0x0000 + +#WC30 +phy_xaui_tx_polarity_flip_126=0x000F +phy_xaui_rx_polarity_flip_126=0x0000 + +#WC31 +phy_xaui_tx_polarity_flip_130=0x0006 +phy_xaui_rx_polarity_flip_130=0x0000 +