This started as an attempt to blink MIO through PL, but that's not possible..
There is a schematic page named Z720_PL
, showing the available, to the PL unit, pins.
These are called IO_*
.
There is a schematic page named Z720_PS
, showing the available, to the PL unit, pins.
These are called PS_DDR_*
and PS_MIO_*
.
They can also be seen under FIXED_IO
and DDR
entries inside the I/O Ports
[tab] (after opening "Elaborate Design").
I think EMIO serves as sharing PL's pins to PS.
(I'm a bit unsure of the following, but):
- Enable EMIO
- Make the [new] GPIO port external.
- Choose PL pins for the [new] GPIO (external) bus. (Through "I/O Ports" (Open "Elaborate Design")).
The following are only accessible from the PS:
- Buttton(
MIO50
) - user LED1/LED2 (
MIO0
/MIO9
) - CAN [pins] (
MIO14
/MIO15
)