diff --git a/cmake/ncnn_add_layer.cmake b/cmake/ncnn_add_layer.cmake index 6ce5feadbf31..0b0fb3233334 100644 --- a/cmake/ncnn_add_layer.cmake +++ b/cmake/ncnn_add_layer.cmake @@ -133,15 +133,15 @@ macro(ncnn_add_layer class) set(layer_registry_vulkan "${layer_registry_vulkan}#if NCNN_STRING\n{\"${class}\", 0},\n#else\n{0},\n#endif\n") endif() - if(NCNN_TARGET_ARCH STREQUAL "x86") + if(NCNN_RUNTIME_CPU AND NCNN_TARGET_ARCH STREQUAL "x86") if(CMAKE_CXX_COMPILER_ID MATCHES "MSVC") - if(NCNN_RUNTIME_CPU AND NCNN_AVX512) + if(NCNN_AVX512) ncnn_add_arch_opt_layer(${class} avx512 "/arch:AVX512 /D__SSSE3__ /D__SSE4_1__ /D__FMA__ /D__F16C__") endif() - if(NCNN_RUNTIME_CPU AND NCNN_FMA) + if(NCNN_FMA) ncnn_add_arch_opt_layer(${class} fma "/arch:AVX /D__SSSE3__ /D__SSE4_1__ /D__FMA__ /D__F16C__") endif() - if(NCNN_RUNTIME_CPU AND NCNN_AVX) + if(NCNN_AVX) ncnn_add_arch_opt_layer(${class} avx "/arch:AVX /D__SSSE3__ /D__SSE4_1__") endif() if(NCNN_AVX512VNNI) @@ -166,13 +166,13 @@ macro(ncnn_add_layer class) ncnn_add_arch_opt_source(${class} f16c "/arch:AVX /D__SSSE3__ /D__SSE4_1__ /D__F16C__") endif() elseif(CMAKE_CXX_COMPILER_ID MATCHES "Clang" AND CMAKE_CXX_SIMULATE_ID MATCHES "MSVC" AND CMAKE_CXX_COMPILER_FRONTEND_VARIANT MATCHES "MSVC") - if(NCNN_RUNTIME_CPU AND NCNN_AVX512) + if(NCNN_AVX512) ncnn_add_arch_opt_layer(${class} avx512 "/arch:AVX512 -mavx512cd -mavx512bw -mavx512dq -mavx512vl -mfma -mf16c /D__SSSE3__ /D__SSE4_1__ /D__FMA__ /D__F16C__") endif() - if(NCNN_RUNTIME_CPU AND NCNN_FMA) + if(NCNN_FMA) ncnn_add_arch_opt_layer(${class} fma "/arch:AVX -mfma -mf16c /D__SSSE3__ /D__SSE4_1__ /D__FMA__ /D__F16C__") endif() - if(NCNN_RUNTIME_CPU AND NCNN_AVX) + if(NCNN_AVX) ncnn_add_arch_opt_layer(${class} avx "/arch:AVX /D__SSSE3__ /D__SSE4_1__") endif() if(NCNN_AVX512VNNI) @@ -197,13 +197,13 @@ macro(ncnn_add_layer class) ncnn_add_arch_opt_source(${class} f16c "/arch:AVX -mf16c /D__SSSE3__ /D__SSE4_1__ /D__F16C__") endif() else() - if(NCNN_RUNTIME_CPU AND NCNN_AVX512) + if(NCNN_AVX512) ncnn_add_arch_opt_layer(${class} avx512 "-mavx512f -mavx512cd -mavx512bw -mavx512dq -mavx512vl -mfma -mf16c") endif() - if(NCNN_RUNTIME_CPU AND NCNN_FMA) + if(NCNN_FMA) ncnn_add_arch_opt_layer(${class} fma "-mavx -mfma -mf16c") endif() - if(NCNN_RUNTIME_CPU AND NCNN_AVX) + if(NCNN_AVX) ncnn_add_arch_opt_layer(${class} avx "-mavx") endif() if(NCNN_AVX512VNNI) @@ -230,7 +230,7 @@ macro(ncnn_add_layer class) endif() endif() - if(NCNN_TARGET_ARCH STREQUAL "arm" AND (CMAKE_SIZEOF_VOID_P EQUAL 4 AND NOT NCNN_TARGET_ILP32)) + if(NCNN_RUNTIME_CPU AND NCNN_TARGET_ARCH STREQUAL "arm" AND (CMAKE_SIZEOF_VOID_P EQUAL 4 AND NOT NCNN_TARGET_ILP32)) if(CMAKE_CXX_COMPILER_ID MATCHES "MSVC" OR (CMAKE_CXX_COMPILER_ID MATCHES "Clang" AND CMAKE_CXX_SIMULATE_ID MATCHES "MSVC" AND CMAKE_CXX_COMPILER_FRONTEND_VARIANT MATCHES "MSVC")) if(NCNN_VFPV4) ncnn_add_arch_opt_source(${class} vfpv4 "/arch:VFPv4 /D__ARM_FP=0x0E") @@ -246,7 +246,7 @@ macro(ncnn_add_layer class) endif() endif() - if(NCNN_TARGET_ARCH STREQUAL "arm" AND (CMAKE_SIZEOF_VOID_P EQUAL 8 OR NCNN_TARGET_ILP32)) + if(NCNN_RUNTIME_CPU AND NCNN_TARGET_ARCH STREQUAL "arm" AND (CMAKE_SIZEOF_VOID_P EQUAL 8 OR NCNN_TARGET_ILP32)) if(CMAKE_CXX_COMPILER_ID MATCHES "MSVC") if(NCNN_VFPV4) ncnn_add_arch_opt_source(${class} vfpv4 " ") @@ -344,8 +344,8 @@ macro(ncnn_add_layer class) endif() endif() - if(NCNN_TARGET_ARCH STREQUAL "mips") - if(NCNN_RUNTIME_CPU AND NCNN_MSA) + if(NCNN_RUNTIME_CPU AND NCNN_TARGET_ARCH STREQUAL "mips") + if(NCNN_MSA) ncnn_add_arch_opt_layer(${class} msa "-mmsa") endif() if(NCNN_MMI) @@ -353,17 +353,17 @@ macro(ncnn_add_layer class) endif() endif() - if(NCNN_TARGET_ARCH STREQUAL "loongarch") - if(NCNN_RUNTIME_CPU AND NCNN_LASX) + if(NCNN_RUNTIME_CPU AND NCNN_TARGET_ARCH STREQUAL "loongarch") + if(NCNN_LASX) ncnn_add_arch_opt_layer(${class} lasx "-mlasx -mlsx") endif() - if(NCNN_RUNTIME_CPU AND NCNN_LSX) + if(NCNN_LSX) ncnn_add_arch_opt_layer(${class} lsx "-mlsx") endif() endif() - if(NCNN_TARGET_ARCH STREQUAL "riscv" AND CMAKE_SIZEOF_VOID_P EQUAL 8) - if(NCNN_RUNTIME_CPU AND NCNN_RVV) + if(NCNN_RUNTIME_CPU AND NCNN_TARGET_ARCH STREQUAL "riscv" AND CMAKE_SIZEOF_VOID_P EQUAL 8) + if(NCNN_RVV) if(NCNN_COMPILER_SUPPORT_RVV_ZFH) ncnn_add_arch_opt_layer(${class} rvv "-march=rv64gcv_zfh") elseif(NCNN_COMPILER_SUPPORT_RVV_ZVFH)