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rasterizer_gpu.cpp
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rasterizer_gpu.cpp
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#include <context.hpp>
#include "rasterizer_gpu.hpp"
#include "context.hpp"
#include "device.hpp"
#include <stdexcept>
#include "math.hpp"
#include "stb_image_write.h"
#include <string.h>
using namespace Granite;
using namespace Vulkan;
namespace RetroWarp
{
struct BBox
{
int min_x, max_x, min_y, max_y;
};
constexpr unsigned MAX_NUM_SHADER_STATE_INDICES = 64;
constexpr unsigned MAX_NUM_RENDER_STATE_INDICES = 1024;
constexpr unsigned VRAM_SIZE = 64 * 1024 * 1024;
struct RasterizerGPU::Impl
{
Device *device;
BufferHandle vram_buffer;
struct Framebuffer
{
uint32_t offset = 0;
uint32_t width = 0;
uint32_t height = 0;
uint32_t stride = 0;
};
Framebuffer color, depth;
bool subgroup = false;
bool ubershader = false;
bool async_compute = false;
struct
{
// First pass, bin at 64x64.
BufferHandle mask_buffer_low_res;
// Bin at 16x16.
BufferHandle mask_buffer[2];
// Groups group of 32 primitives into one 1 bit for faster rejection in raster.
BufferHandle mask_buffer_coarse[2];
} binning;
struct
{
// Final resolved tile offsets.
BufferHandle tile_offset[2];
} tile_count;
struct
{
BufferHandle color[2];
BufferHandle depth[2];
BufferHandle flags[2];
unsigned index = 0;
Semaphore rop_complete[2];
} tile_instance_data;
struct RenderState
{
int16_t scissor_x = 0;
int16_t scissor_y = 0;
int16_t scissor_width = 0;
int16_t scissor_height = 0;
uint8_t constant_color[4] = {};
uint8_t depth_state = uint8_t(DepthWrite::On);
uint8_t blend_state = uint8_t(BlendState::Replace);
uint8_t combiner_state = 0;
uint8_t alpha_threshold = 0;
TextureDescriptor tex;
};
static_assert(sizeof(RenderState) == 64, "Sizeof render state must be 64.");
struct
{
BufferHandle positions;
BufferHandle attributes;
BufferHandle shader_state_index;
BufferHandle render_state_index;
BufferHandle render_state;
BufferHandle positions_gpu;
BufferHandle attributes_gpu;
BufferHandle shader_state_index_gpu;
BufferHandle render_state_index_gpu;
BufferHandle render_state_gpu;
PrimitiveSetupPos *mapped_positions = nullptr;
PrimitiveSetupAttr *mapped_attributes = nullptr;
uint8_t *mapped_shader_state_index = nullptr;
uint16_t *mapped_render_state_index = nullptr;
RenderState *mapped_render_state = nullptr;
unsigned count = 0;
unsigned num_conservative_tile_instances = 0;
bool host_visible = false;
} staging;
struct
{
BufferHandle item_count_per_variant;
BufferHandle work_list_per_variant;
} raster_work;
struct
{
uint32_t shader_states[MAX_NUM_SHADER_STATE_INDICES] = {};
unsigned shader_state_count = 0;
uint32_t current_shader_state = 0;
RenderState last_render_state;
RenderState current_render_state;
unsigned render_state_count = 0;
} state;
void init(Device &device, bool subgroup, bool ubershader, bool async_compute, unsigned tile_size);
void reset_staging();
void begin_staging();
void end_staging();
void init_binning_buffers();
void init_prefix_sum_buffers();
void init_tile_buffers();
void init_raster_work_buffers();
void flush();
void flush_ubershader();
void flush_split();
ImageHandle copy_to_framebuffer();
void queue_primitive(const PrimitiveSetup &setup);
unsigned compute_num_conservative_tiles(const PrimitiveSetup &setup) const;
BBox compute_bbox(const PrimitiveSetup &setup) const;
bool clip_bbox_scissor(BBox &clipped_bbox, const BBox &bbox) const;
void set_fb_info(CommandBuffer &cmd);
void clear_indirect_buffer(CommandBuffer &cmd);
void binning_low_res_prepass(CommandBuffer &cmd);
void binning_full_res(CommandBuffer &cmd, bool ubershader);
void dispatch_combiner_work(CommandBuffer &cmd);
void run_rop(CommandBuffer &cmd);
void run_rop_ubershader(CommandBuffer &cmd);
bool can_support_minimum_subgroup_size(unsigned size) const;
bool supports_subgroup_size_control(uint32_t minimum_size, uint32_t maximum_size) const;
int tile_size = 0;
int tile_size_log2 = 0;
int max_tiles_x = 0;
int max_tiles_y = 0;
int max_tiles_x_low_res = 0;
int max_tiles_y_low_res = 0;
uint32_t compute_shader_state() const;
};
struct FBInfo
{
uvec2 resolution;
uvec2 resolution_tiles;
uint32_t primitive_count;
uint32_t primitive_count_32;
uint32_t primitive_count_1024;
uint32_t color_offset;
uint32_t color_width;
uint32_t color_height;
uint32_t color_stride;
uint32_t depth_offset;
uint32_t depth_width;
uint32_t depth_height;
uint32_t depth_stride;
};
constexpr int MAX_PRIMITIVES = 0x4000;
constexpr int TILE_BINNING_STRIDE = MAX_PRIMITIVES / 32;
constexpr int TILE_BINNING_STRIDE_COARSE = TILE_BINNING_STRIDE / 32;
constexpr int MAX_WIDTH = 2048;
constexpr int MAX_HEIGHT = 2048;
constexpr int TILE_DOWNSAMPLE = 8;
constexpr int TILE_DOWNSAMPLE_LOG2 = 3;
constexpr int MAX_NUM_TILE_INSTANCES = 0xffff;
const int RASTER_ROUNDING = (1 << (SUBPIXELS_LOG2 + 16)) - 1;
struct TileRasterWork
{
uint32_t tile_x, tile_y;
uint32_t tile_instance;
uint32_t primitive;
};
void RasterizerGPU::Impl::reset_staging()
{
staging = {};
state.render_state_count = 0;
state.shader_state_count = 0;
}
uint32_t RasterizerGPU::Impl::compute_shader_state() const
{
// Ignore shader state for ubershaders.
if (ubershader)
return 0;
uint32_t shader_state = 0;
shader_state |= state.current_render_state.combiner_state;
shader_state |= state.current_render_state.alpha_threshold << 8u;
shader_state |= state.current_render_state.tex.texture_fmt << 16u;
return shader_state;
}
BBox RasterizerGPU::Impl::compute_bbox(const PrimitiveSetup &setup) const
{
int lo_x = std::numeric_limits<int>::max();
int hi_x = std::numeric_limits<int>::min();
int lo_y = std::numeric_limits<int>::max();
int hi_y = std::numeric_limits<int>::min();
lo_x = std::min(lo_x, setup.pos.x_a);
lo_x = std::min(lo_x, setup.pos.x_b);
lo_x = std::min(lo_x, setup.pos.x_c);
hi_x = std::max(hi_x, setup.pos.x_a);
hi_x = std::max(hi_x, setup.pos.x_b);
hi_x = std::max(hi_x, setup.pos.x_c);
int end_point_a = setup.pos.x_a + setup.pos.dxdy_a * (setup.pos.y_hi - setup.pos.y_lo);
int end_point_b = setup.pos.x_b + setup.pos.dxdy_b * (setup.pos.y_mid - setup.pos.y_lo);
int end_point_c = setup.pos.x_c + setup.pos.dxdy_c * (setup.pos.y_hi - setup.pos.y_mid);
lo_x = std::min(lo_x, end_point_a);
lo_x = std::min(lo_x, end_point_b);
lo_x = std::min(lo_x, end_point_c);
hi_x = std::max(hi_x, end_point_a);
hi_x = std::max(hi_x, end_point_b);
hi_x = std::max(hi_x, end_point_c);
BBox bbox = {};
bbox.min_x = (lo_x + RASTER_ROUNDING) >> (16 + SUBPIXELS_LOG2);
bbox.max_x = (hi_x - 1) >> (16 + SUBPIXELS_LOG2);
bbox.min_y = (setup.pos.y_lo + (1 << SUBPIXELS_LOG2) - 1) >> SUBPIXELS_LOG2;
bbox.max_y = (setup.pos.y_hi - 1) >> SUBPIXELS_LOG2;
return bbox;
}
bool RasterizerGPU::Impl::clip_bbox_scissor(BBox &clipped_bbox, const BBox &bbox) const
{
int scissor_x = state.current_render_state.scissor_x;
int scissor_y = state.current_render_state.scissor_y;
int scissor_width = state.current_render_state.scissor_width;
int scissor_height = state.current_render_state.scissor_height;
clipped_bbox.min_x = std::max(scissor_x, bbox.min_x);
clipped_bbox.max_x = std::min(scissor_x + scissor_width - 1, bbox.max_x);
clipped_bbox.min_y = std::max(scissor_y, bbox.min_y);
clipped_bbox.max_y = std::min(scissor_y + scissor_height - 1, bbox.max_y);
return clipped_bbox.min_x <= clipped_bbox.max_x && clipped_bbox.min_y <= clipped_bbox.max_y;
}
unsigned RasterizerGPU::Impl::compute_num_conservative_tiles(const PrimitiveSetup &setup) const
{
auto bbox = compute_bbox(setup);
BBox clipped_bbox;
if (!clip_bbox_scissor(clipped_bbox, bbox))
return 0;
int start_tile_x = clipped_bbox.min_x >> tile_size_log2;
int end_tile_x = clipped_bbox.max_x >> tile_size_log2;
int start_tile_y = clipped_bbox.min_y >> tile_size_log2;
int end_tile_y = clipped_bbox.max_y >> tile_size_log2;
return (end_tile_x - start_tile_x + 1) * (end_tile_y - start_tile_y + 1);
}
void RasterizerGPU::Impl::begin_staging()
{
BufferCreateInfo info;
info.domain = BufferDomain::Device;
info.usage = VK_BUFFER_USAGE_STORAGE_BUFFER_BIT | VK_BUFFER_USAGE_TRANSFER_DST_BIT;
info.size = MAX_PRIMITIVES * sizeof(PrimitiveSetupPos);
staging.positions_gpu = device->create_buffer(info);
info.usage = VK_BUFFER_USAGE_STORAGE_BUFFER_BIT | VK_BUFFER_USAGE_TRANSFER_DST_BIT;
info.size = MAX_PRIMITIVES * sizeof(PrimitiveSetupAttr);
staging.attributes_gpu = device->create_buffer(info);
info.usage = VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT | VK_BUFFER_USAGE_STORAGE_BUFFER_BIT | VK_BUFFER_USAGE_TRANSFER_DST_BIT;
info.size = MAX_PRIMITIVES * sizeof(uint8_t);
staging.shader_state_index_gpu = device->create_buffer(info);
info.usage = VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT | VK_BUFFER_USAGE_TRANSFER_DST_BIT;
info.size = MAX_PRIMITIVES * sizeof(uint16_t);
staging.render_state_index_gpu = device->create_buffer(info);
info.size = MAX_NUM_RENDER_STATE_INDICES * sizeof(RenderState);
staging.render_state_gpu = device->create_buffer(info);
staging.mapped_positions = static_cast<PrimitiveSetupPos *>(
device->map_host_buffer(*staging.positions_gpu,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_attributes = static_cast<PrimitiveSetupAttr *>(
device->map_host_buffer(*staging.attributes_gpu,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_shader_state_index = static_cast<uint8_t *>(
device->map_host_buffer(*staging.shader_state_index_gpu,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_render_state = static_cast<RenderState *>(
device->map_host_buffer(*staging.render_state_gpu,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_render_state_index = static_cast<uint16_t *>(
device->map_host_buffer(*staging.render_state_index_gpu,
MEMORY_ACCESS_WRITE_BIT));
if (staging.mapped_positions && staging.mapped_attributes && staging.mapped_shader_state_index &&
staging.mapped_render_state && staging.mapped_render_state_index)
{
staging.positions = staging.positions_gpu;
staging.attributes = staging.attributes_gpu;
staging.shader_state_index = staging.shader_state_index_gpu;
staging.render_state = staging.render_state_gpu;
staging.render_state_index = staging.render_state_index_gpu;
staging.host_visible = true;
}
else
{
info.domain = BufferDomain::Host;
info.usage = VK_BUFFER_USAGE_TRANSFER_SRC_BIT;
info.size = MAX_PRIMITIVES * sizeof(PrimitiveSetupPos);
staging.positions = device->create_buffer(info);
info.size = MAX_PRIMITIVES * sizeof(PrimitiveSetupAttr);
staging.attributes = device->create_buffer(info);
info.size = MAX_PRIMITIVES * sizeof(uint8_t);
staging.shader_state_index = device->create_buffer(info);
info.size = MAX_PRIMITIVES * sizeof(uint16_t);
staging.render_state_index = device->create_buffer(info);
info.size = MAX_NUM_RENDER_STATE_INDICES * sizeof(RenderState);
staging.render_state = device->create_buffer(info);
staging.mapped_positions = static_cast<PrimitiveSetupPos *>(
device->map_host_buffer(*staging.positions,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_attributes = static_cast<PrimitiveSetupAttr *>(
device->map_host_buffer(*staging.attributes,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_shader_state_index = static_cast<uint8_t *>(
device->map_host_buffer(*staging.shader_state_index,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_render_state = static_cast<RenderState *>(
device->map_host_buffer(*staging.render_state,
MEMORY_ACCESS_WRITE_BIT));
staging.mapped_render_state_index = static_cast<uint16_t *>(
device->map_host_buffer(*staging.render_state_index,
MEMORY_ACCESS_WRITE_BIT));
staging.host_visible = false;
}
staging.count = 0;
staging.num_conservative_tile_instances = 0;
}
void RasterizerGPU::Impl::end_staging()
{
if (staging.mapped_positions)
device->unmap_host_buffer(*staging.positions, MEMORY_ACCESS_WRITE_BIT);
if (staging.mapped_attributes)
device->unmap_host_buffer(*staging.attributes, MEMORY_ACCESS_WRITE_BIT);
if (staging.mapped_shader_state_index)
device->unmap_host_buffer(*staging.shader_state_index, MEMORY_ACCESS_WRITE_BIT);
if (staging.mapped_render_state_index)
device->unmap_host_buffer(*staging.render_state_index, MEMORY_ACCESS_WRITE_BIT);
if (staging.mapped_render_state)
device->unmap_host_buffer(*staging.render_state, MEMORY_ACCESS_WRITE_BIT);
staging.mapped_positions = nullptr;
staging.mapped_attributes = nullptr;
staging.mapped_shader_state_index = nullptr;
staging.mapped_render_state_index = nullptr;
staging.mapped_render_state = nullptr;
if (!staging.host_visible && staging.count != 0)
{
auto cmd = device->request_command_buffer(CommandBuffer::Type::AsyncTransfer);
cmd->copy_buffer(*staging.positions_gpu, 0, *staging.positions, 0, staging.count * sizeof(PrimitiveSetupPos));
cmd->copy_buffer(*staging.attributes_gpu, 0, *staging.attributes, 0, staging.count * sizeof(PrimitiveSetupAttr));
cmd->copy_buffer(*staging.shader_state_index_gpu, 0, *staging.shader_state_index, 0, staging.count * sizeof(uint8_t));
cmd->copy_buffer(*staging.render_state_index_gpu, 0, *staging.render_state_index, 0, staging.count * sizeof(uint16_t));
cmd->copy_buffer(*staging.render_state_gpu, 0, *staging.render_state, 0, state.render_state_count * sizeof(RenderState));
Semaphore sem;
device->submit(cmd, nullptr, 1, &sem);
device->add_wait_semaphore(async_compute ? CommandBuffer::Type::AsyncCompute : CommandBuffer::Type::Generic, sem, VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, true);
}
}
void RasterizerGPU::Impl::clear_indirect_buffer(CommandBuffer &cmd)
{
cmd.begin_region("clear-indirect-buffer");
cmd.set_program("assets://shaders/clear_indirect_buffers.comp");
cmd.set_specialization_constant_mask(1);
cmd.set_specialization_constant(0, MAX_NUM_SHADER_STATE_INDICES);
cmd.set_storage_buffer(0, 0, *raster_work.item_count_per_variant);
cmd.dispatch(1, 1, 1);
cmd.end_region();
cmd.set_specialization_constant_mask(0);
}
void RasterizerGPU::Impl::binning_low_res_prepass(CommandBuffer &cmd)
{
uint32_t width = std::max(color.width, depth.width);
uint32_t height = std::max(color.height, depth.height);
cmd.begin_region("binning-low-res-prepass");
cmd.set_storage_buffer(0, 0, *binning.mask_buffer_low_res);
cmd.set_storage_buffer(0, 1, *staging.positions_gpu);
cmd.set_uniform_buffer(0, 2, *staging.render_state_index_gpu);
cmd.set_uniform_buffer(0, 3, *staging.render_state_gpu);
auto &features = device->get_device_features();
uint32_t subgroup_size = features.subgroup_properties.subgroupSize;
#if 0
if (features.subgroup_size_control_features.subgroupSizeControl &&
(features.subgroup_size_control_properties.requiredSubgroupSizeStages & VK_SHADER_STAGE_COMPUTE_BIT) &&
features.subgroup_size_control_properties.minSubgroupSize <= 32 &&
features.subgroup_size_control_properties.maxSubgroupSize >= 32)
{
// Prefer subgroup size of 32 if possible.
subgroup_size = 32;
}
#endif
const VkSubgroupFeatureFlags required = VK_SUBGROUP_FEATURE_BALLOT_BIT | VK_SUBGROUP_FEATURE_BASIC_BIT;
if (subgroup && (features.subgroup_properties.supportedOperations & required) == required &&
(features.subgroup_properties.supportedStages & VK_SHADER_STAGE_COMPUTE_BIT) != 0 &&
can_support_minimum_subgroup_size(32) && subgroup_size <= 64)
{
cmd.set_program("assets://shaders/binning_low_res.comp", {{ "SUBGROUP", 1 }, { "TILE_SIZE", tile_size }});
cmd.set_specialization_constant_mask(1);
cmd.set_specialization_constant(0, subgroup_size);
if (supports_subgroup_size_control(32, subgroup_size))
{
cmd.enable_subgroup_size_control(true);
cmd.set_subgroup_size_log2(true, 5, trailing_zeroes(subgroup_size));
}
cmd.dispatch((staging.count + subgroup_size - 1) / subgroup_size,
(width + TILE_DOWNSAMPLE * tile_size - 1) / (TILE_DOWNSAMPLE * tile_size),
(height + TILE_DOWNSAMPLE * tile_size - 1) / (TILE_DOWNSAMPLE * tile_size));
cmd.enable_subgroup_size_control(false);
}
else
{
// Fallback with shared memory.
cmd.set_program("assets://shaders/binning_low_res.comp", {{ "SUBGROUP", 0 }, { "TILE_SIZE", tile_size }});
cmd.dispatch((staging.count + 31) / 32,
(width + TILE_DOWNSAMPLE * tile_size - 1) / (TILE_DOWNSAMPLE * tile_size),
(height + TILE_DOWNSAMPLE * tile_size - 1) / (TILE_DOWNSAMPLE * tile_size));
}
cmd.end_region();
cmd.set_specialization_constant_mask(0);
}
void RasterizerGPU::Impl::binning_full_res(CommandBuffer &cmd, bool ubershader)
{
uint32_t width = std::max(color.width, depth.width);
uint32_t height = std::max(color.height, depth.height);
cmd.begin_region("binning-full-res");
cmd.set_storage_buffer(0, 0, *binning.mask_buffer[tile_instance_data.index]);
cmd.set_storage_buffer(0, 1, *staging.positions_gpu);
cmd.set_storage_buffer(0, 2, *binning.mask_buffer_low_res);
cmd.set_storage_buffer(0, 3, *binning.mask_buffer_coarse[tile_instance_data.index]);
cmd.set_uniform_buffer(0, 4, *staging.render_state_index_gpu);
cmd.set_uniform_buffer(0, 5, *staging.render_state_gpu);
if (!ubershader)
{
cmd.set_storage_buffer(0, 6, *tile_count.tile_offset[tile_instance_data.index]);
cmd.set_storage_buffer(0, 7, *raster_work.item_count_per_variant);
cmd.set_storage_buffer(0, 8, *raster_work.work_list_per_variant);
cmd.set_storage_buffer(0, 9, *staging.shader_state_index_gpu);
}
auto &features = device->get_device_features();
uint32_t subgroup_size = features.subgroup_properties.subgroupSize;
#if 0
if (features.subgroup_size_control_features.subgroupSizeControl &&
(features.subgroup_size_control_properties.requiredSubgroupSizeStages & VK_SHADER_STAGE_COMPUTE_BIT) &&
features.subgroup_size_control_properties.minSubgroupSize <= 32 &&
features.subgroup_size_control_properties.maxSubgroupSize >= 32)
{
// Prefer subgroup size of 32 if possible.
subgroup_size = 32;
}
#endif
uint32_t num_masks = (staging.count + 31) / 32;
const VkSubgroupFeatureFlags required = VK_SUBGROUP_FEATURE_BALLOT_BIT |
VK_SUBGROUP_FEATURE_BASIC_BIT |
VK_SUBGROUP_FEATURE_VOTE_BIT |
VK_SUBGROUP_FEATURE_ARITHMETIC_BIT;
if (subgroup && (features.subgroup_properties.supportedOperations & required) == required &&
(features.subgroup_properties.supportedStages & VK_SHADER_STAGE_COMPUTE_BIT) != 0 &&
can_support_minimum_subgroup_size(32))
{
cmd.set_program("assets://shaders/binning.comp", {{ "SUBGROUP", 1 }, { "UBERSHADER", ubershader ? 1 : 0 }, { "TILE_SIZE", tile_size }});
cmd.set_specialization_constant_mask(1);
cmd.set_specialization_constant(0, subgroup_size);
if (supports_subgroup_size_control(32, subgroup_size))
{
cmd.enable_subgroup_size_control(true);
cmd.set_subgroup_size_log2(true, 5, trailing_zeroes(subgroup_size));
}
cmd.dispatch((num_masks + subgroup_size - 1) / subgroup_size,
(width + tile_size - 1) / tile_size,
(height + tile_size - 1) / tile_size);
cmd.enable_subgroup_size_control(false);
}
else
{
// Fallback with shared memory.
cmd.set_program("assets://shaders/binning.comp", {{ "SUBGROUP", 0 }, { "UBERSHADER", ubershader ? 1 : 0 }, { "TILE_SIZE", tile_size }});
cmd.dispatch((num_masks + 31) / 32,
(width + tile_size - 1) / tile_size,
(height + tile_size - 1) / tile_size);
}
cmd.end_region();
cmd.set_specialization_constant_mask(0);
}
bool RasterizerGPU::Impl::can_support_minimum_subgroup_size(unsigned size) const
{
return supports_subgroup_size_control(size, device->get_device_features().subgroup_properties.subgroupSize);
}
bool RasterizerGPU::Impl::supports_subgroup_size_control(uint32_t minimum_size, uint32_t maximum_size) const
{
auto &features = device->get_device_features();
if (!features.subgroup_size_control_features.computeFullSubgroups)
return false;
bool use_varying = minimum_size <= features.subgroup_size_control_properties.minSubgroupSize &&
maximum_size >= features.subgroup_size_control_properties.maxSubgroupSize;
if (!use_varying)
{
bool outside_range = minimum_size > features.subgroup_size_control_properties.maxSubgroupSize ||
maximum_size < features.subgroup_size_control_properties.minSubgroupSize;
if (outside_range)
return false;
if ((features.subgroup_size_control_properties.requiredSubgroupSizeStages & VK_SHADER_STAGE_COMPUTE_BIT) == 0)
return false;
}
return true;
}
void RasterizerGPU::Impl::dispatch_combiner_work(CommandBuffer &cmd)
{
cmd.begin_region("dispatch-combiner-work");
cmd.set_storage_buffer(0, 1, *tile_instance_data.color[tile_instance_data.index]);
cmd.set_storage_buffer(0, 2, *tile_instance_data.depth[tile_instance_data.index]);
cmd.set_storage_buffer(0, 3, *tile_instance_data.flags[tile_instance_data.index]);
cmd.set_storage_buffer(0, 4, *staging.positions_gpu);
cmd.set_storage_buffer(0, 5, *staging.attributes_gpu);
cmd.set_uniform_buffer(0, 6, *staging.render_state_index_gpu);
cmd.set_uniform_buffer(0, 7, *staging.render_state_gpu);
cmd.set_storage_buffer(0, 8, *vram_buffer);
auto &features = device->get_device_features();
uint32_t subgroup_size = features.subgroup_properties.subgroupSize;
const VkSubgroupFeatureFlags required = VK_SUBGROUP_FEATURE_BASIC_BIT |
VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
VK_SUBGROUP_FEATURE_BALLOT_BIT;
if (subgroup && features.compute_shader_derivative_features.computeDerivativeGroupQuads)
{
cmd.set_program("assets://shaders/combiner.comp", {
{"DERIVATIVE_GROUP_QUAD", 1},
{"SUBGROUP", 0},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
}
else if (subgroup && features.compute_shader_derivative_features.computeDerivativeGroupLinear)
{
cmd.set_program("assets://shaders/combiner.comp", {
{"DERIVATIVE_GROUP_LINEAR", 1},
{"SUBGROUP", 0},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
}
else if (subgroup && (features.subgroup_properties.supportedOperations & required) == required &&
(features.subgroup_properties.supportedStages & VK_SHADER_STAGE_COMPUTE_BIT) != 0 &&
can_support_minimum_subgroup_size(4))
{
cmd.set_program("assets://shaders/combiner.comp", {
{"SUBGROUP", 1},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
if (supports_subgroup_size_control(4, 64))
{
cmd.set_subgroup_size_log2(true, 2, 6);
cmd.enable_subgroup_size_control(true);
}
}
else
{
cmd.set_program("assets://shaders/combiner.comp", {
{"SUBGROUP", 0},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
}
cmd.set_specialization_constant_mask(1);
for (unsigned variant = 0; variant < state.shader_state_count; variant++)
{
cmd.set_specialization_constant(0, state.shader_states[variant]);
cmd.set_storage_buffer(0, 0, *raster_work.work_list_per_variant,
variant * (MAX_NUM_TILE_INSTANCES + 1) * sizeof(TileRasterWork),
(MAX_NUM_TILE_INSTANCES + 1) * sizeof(TileRasterWork));
cmd.dispatch_indirect(*raster_work.item_count_per_variant, 16 * variant);
}
cmd.end_region();
cmd.enable_subgroup_size_control(false);
cmd.set_specialization_constant_mask(0);
}
void RasterizerGPU::Impl::set_fb_info(CommandBuffer &cmd)
{
uint32_t width = std::max(color.width, depth.width);
uint32_t height = std::max(color.height, depth.height);
auto *fb_info = cmd.allocate_typed_constant_data<FBInfo>(2, 0, 1);
fb_info->resolution.x = width;
fb_info->resolution.y = height;
fb_info->resolution_tiles.x = (width + tile_size - 1) / tile_size;
fb_info->resolution_tiles.y = (height + tile_size - 1) / tile_size;
fb_info->primitive_count = staging.count;
uint32_t num_masks = (staging.count + 31) / 32;
fb_info->primitive_count_32 = num_masks;
fb_info->primitive_count_1024 = (staging.count + 1023) / 1024;
fb_info->color_offset = color.offset >> 1u;
fb_info->color_width = color.width;
fb_info->color_height = color.height;
fb_info->color_stride = color.stride >> 1u;
fb_info->depth_offset = depth.offset >> 1u;
fb_info->depth_width = depth.width;
fb_info->depth_height = depth.height;
fb_info->depth_stride = depth.stride >> 1u;
}
void RasterizerGPU::Impl::run_rop_ubershader(CommandBuffer &cmd)
{
uint32_t width = std::max(color.width, depth.width);
uint32_t height = std::max(color.height, depth.height);
cmd.begin_region("run-rop");
cmd.set_storage_buffer(0, 0, *vram_buffer);
cmd.set_storage_buffer(0, 1, *binning.mask_buffer[tile_instance_data.index]);
cmd.set_storage_buffer(0, 2, *binning.mask_buffer_coarse[tile_instance_data.index]);
cmd.set_storage_buffer(0, 3, *staging.positions_gpu);
cmd.set_storage_buffer(0, 4, *staging.attributes_gpu);
cmd.set_uniform_buffer(0, 5, *staging.shader_state_index_gpu);
cmd.set_uniform_buffer(0, 6, *staging.render_state_index_gpu);
cmd.set_uniform_buffer(0, 7, *staging.render_state_gpu);
auto &features = device->get_device_features();
const VkSubgroupFeatureFlags required = VK_SUBGROUP_FEATURE_BASIC_BIT |
VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
VK_SUBGROUP_FEATURE_BALLOT_BIT;
if (subgroup && features.compute_shader_derivative_features.computeDerivativeGroupQuads)
{
cmd.set_program("assets://shaders/rop_ubershader.comp", {
{"DERIVATIVE_GROUP_QUAD", 1},
{"SUBGROUP", 0},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
}
else if (subgroup && features.compute_shader_derivative_features.computeDerivativeGroupLinear)
{
cmd.set_program("assets://shaders/rop_ubershader.comp", {
{"DERIVATIVE_GROUP_LINEAR", 1},
{"SUBGROUP", 0},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
}
else if (subgroup && (features.subgroup_properties.supportedOperations & required) == required &&
(features.subgroup_properties.supportedStages & VK_SHADER_STAGE_COMPUTE_BIT) != 0 &&
can_support_minimum_subgroup_size(4))
{
cmd.set_program("assets://shaders/rop_ubershader.comp", {
{"SUBGROUP", 1},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
if (supports_subgroup_size_control(4, 128))
{
cmd.set_subgroup_size_log2(true, 2, 7);
cmd.enable_subgroup_size_control(true);
}
}
else
{
cmd.set_program("assets://shaders/rop_ubershader.comp", {
{"SUBGROUP", 0},
{"TILE_SIZE", tile_size},
{"TILE_SIZE_SQUARE", tile_size * tile_size},
});
}
cmd.dispatch((width + tile_size - 1) / tile_size, (height + tile_size - 1) / tile_size, 1);
cmd.end_region();
cmd.enable_subgroup_size_control(false);
}
void RasterizerGPU::Impl::run_rop(CommandBuffer &cmd)
{
uint32_t width = std::max(color.width, depth.width);
uint32_t height = std::max(color.height, depth.height);
cmd.begin_region("run-rop");
cmd.set_program("assets://shaders/rop.comp", {
{"TILE_SIZE", tile_size}
});
cmd.set_storage_buffer(0, 0, *vram_buffer);
cmd.set_storage_buffer(0, 1, *binning.mask_buffer[tile_instance_data.index]);
cmd.set_storage_buffer(0, 2, *binning.mask_buffer_coarse[tile_instance_data.index]);
cmd.set_storage_buffer(0, 3, *tile_instance_data.color[tile_instance_data.index]);
cmd.set_storage_buffer(0, 4, *tile_instance_data.depth[tile_instance_data.index]);
cmd.set_storage_buffer(0, 5, *tile_instance_data.flags[tile_instance_data.index]);
cmd.set_storage_buffer(0, 6, *tile_count.tile_offset[tile_instance_data.index]);
cmd.set_uniform_buffer(0, 7, *staging.render_state_index_gpu);
cmd.set_uniform_buffer(0, 8, *staging.render_state_gpu);
cmd.dispatch((width + tile_size - 1) / tile_size, (height + tile_size - 1) / tile_size, 1);
cmd.end_region();
}
void RasterizerGPU::Impl::flush_ubershader()
{
end_staging();
if (staging.count == 0)
return;
auto queue_type = async_compute ? CommandBuffer::Type::AsyncCompute : CommandBuffer::Type::Generic;
auto cmd = device->request_command_buffer(queue_type);
set_fb_info(*cmd);
auto t0 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
binning_low_res_prepass(*cmd);
cmd->barrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, VK_ACCESS_SHADER_WRITE_BIT,
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, VK_ACCESS_SHADER_READ_BIT);
auto t1 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
device->register_time_interval("GPU", t0, t1, "binning-low-res-prepass");
device->submit(cmd);
auto &rop_sem = tile_instance_data.rop_complete[tile_instance_data.index];
if (rop_sem)
{
device->add_wait_semaphore(queue_type, rop_sem, VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, true);
rop_sem.reset();
}
cmd = device->request_command_buffer(queue_type);
set_fb_info(*cmd);
t1 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
binning_full_res(*cmd, true);
auto t2 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
device->register_time_interval("GPU", t1, t2, "binning-full-res");
Semaphore sem;
device->submit(cmd, nullptr, 1, &sem);
device->add_wait_semaphore(CommandBuffer::Type::Generic, sem, VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, true);
cmd = device->request_command_buffer();
set_fb_info(*cmd);
t2 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
cmd->barrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
VK_ACCESS_SHADER_WRITE_BIT,
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
VK_ACCESS_SHADER_WRITE_BIT | VK_ACCESS_SHADER_READ_BIT);
run_rop_ubershader(*cmd);
auto t3 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
device->register_time_interval("GPU", t2, t3, "rop-ubershader");
sem.reset();
device->submit(cmd, nullptr, 1, &sem);
tile_instance_data.rop_complete[tile_instance_data.index] = sem;
reset_staging();
device->register_time_interval("GPU", t0, t3, "iteration");
tile_instance_data.index ^= 1;
}
void RasterizerGPU::Impl::flush_split()
{
end_staging();
if (staging.count == 0)
return;
auto queue_type = async_compute ? CommandBuffer::Type::AsyncCompute : CommandBuffer::Type::Generic;
auto cmd = device->request_command_buffer(queue_type);
set_fb_info(*cmd);
// This part can overlap with previous flush.
// Clear indirect buffer.
clear_indirect_buffer(*cmd);
auto t0 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
// Binning low-res prepass.
binning_low_res_prepass(*cmd);
cmd->barrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, VK_ACCESS_SHADER_WRITE_BIT,
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, VK_ACCESS_SHADER_READ_BIT);
auto t1 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
device->register_time_interval("GPU", t0, t1, "binning-low-res-prepass");
device->submit(cmd);
// Need to wait until an earlier pass of ROP completes.
auto &rop_sem = tile_instance_data.rop_complete[tile_instance_data.index];
if (rop_sem)
{
device->add_wait_semaphore(queue_type,
rop_sem,
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, true);
rop_sem.reset();
}
cmd = device->request_command_buffer(queue_type);
set_fb_info(*cmd);
t1 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
// Binning at full-resolution.
binning_full_res(*cmd, false);
cmd->barrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, VK_ACCESS_SHADER_WRITE_BIT,
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT,
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_INDIRECT_COMMAND_READ_BIT);
auto t2 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
device->register_time_interval("GPU", t1, t2, "binning-full-res");
dispatch_combiner_work(*cmd);
auto t3 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
device->register_time_interval("GPU", t2, t3, "dispatch-combiner-work");
// Hand off shaded result to ROP.
Semaphore sem;
device->submit(cmd, nullptr, 1, &sem);
device->add_wait_semaphore(CommandBuffer::Type::Generic, sem, VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, true);
cmd = device->request_command_buffer();
set_fb_info(*cmd);
t3 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
cmd->barrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
VK_ACCESS_SHADER_WRITE_BIT,
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT);
// ROP.
run_rop(*cmd);
auto t4 = cmd->write_timestamp(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT);
device->register_time_interval("GPU", t3, t4, "rop");
device->register_time_interval("GPU", t0, t4, "iteration");
sem.reset();
device->submit(cmd, nullptr, 1, &sem);
tile_instance_data.rop_complete[tile_instance_data.index] = sem;
reset_staging();
tile_instance_data.index ^= 1;
}
void RasterizerGPU::Impl::init_binning_buffers()
{
BufferCreateInfo info;
info.domain = BufferDomain::Device;
info.usage = VK_BUFFER_USAGE_STORAGE_BUFFER_BIT |
VK_BUFFER_USAGE_TRANSFER_DST_BIT |
VK_BUFFER_USAGE_TRANSFER_SRC_BIT;
info.size = max_tiles_x * max_tiles_y * TILE_BINNING_STRIDE * sizeof(uint32_t);
for (auto &mask_buffer : binning.mask_buffer)
mask_buffer = device->create_buffer(info);
info.size = max_tiles_x_low_res * max_tiles_y_low_res * TILE_BINNING_STRIDE * sizeof(uint32_t);
binning.mask_buffer_low_res = device->create_buffer(info);
info.size = max_tiles_x * max_tiles_y * TILE_BINNING_STRIDE_COARSE * sizeof(uint32_t);
for (auto &mask_buffer : binning.mask_buffer_coarse)
mask_buffer = device->create_buffer(info);
}
void RasterizerGPU::Impl::init_prefix_sum_buffers()
{
BufferCreateInfo info;
info.domain = BufferDomain::Device;
info.usage = VK_BUFFER_USAGE_STORAGE_BUFFER_BIT |
VK_BUFFER_USAGE_TRANSFER_DST_BIT |
VK_BUFFER_USAGE_TRANSFER_SRC_BIT;
info.size = max_tiles_x * max_tiles_y * TILE_BINNING_STRIDE * sizeof(uint16_t);
for (auto &offset : tile_count.tile_offset)
offset = device->create_buffer(info);
}
void RasterizerGPU::Impl::init_tile_buffers()
{
BufferCreateInfo info;
info.domain = BufferDomain::Device;
info.usage = VK_BUFFER_USAGE_STORAGE_BUFFER_BIT |
VK_BUFFER_USAGE_TRANSFER_DST_BIT |
VK_BUFFER_USAGE_TRANSFER_SRC_BIT;
info.size = MAX_NUM_TILE_INSTANCES * tile_size * tile_size * sizeof(uint32_t);
for (auto &color : tile_instance_data.color)
color = device->create_buffer(info);
info.size = MAX_NUM_TILE_INSTANCES * tile_size * tile_size * sizeof(uint16_t);
for (auto &depth : tile_instance_data.depth)
depth = device->create_buffer(info);
info.size = MAX_NUM_TILE_INSTANCES * tile_size * tile_size * sizeof(uint8_t);
for (auto &flags : tile_instance_data.flags)
flags = device->create_buffer(info);
}
void RasterizerGPU::Impl::init_raster_work_buffers()
{
BufferCreateInfo info;
info.domain = BufferDomain::Device;
info.usage = VK_BUFFER_USAGE_STORAGE_BUFFER_BIT |
VK_BUFFER_USAGE_TRANSFER_DST_BIT |
VK_BUFFER_USAGE_TRANSFER_SRC_BIT;
// Round MAX_NUM_TILE_INSTANCES up to 0x10000.
info.size = (MAX_NUM_TILE_INSTANCES + 1) * sizeof(TileRasterWork) * MAX_NUM_SHADER_STATE_INDICES;
raster_work.work_list_per_variant = device->create_buffer(info);
info.size = MAX_NUM_SHADER_STATE_INDICES * (4 * sizeof(uint32_t));
info.usage |= VK_BUFFER_USAGE_INDIRECT_BUFFER_BIT;
raster_work.item_count_per_variant = device->create_buffer(info);
}
template <typename T>
static std::vector<T> readback_buffer(Device *device, const Buffer &buffer)
{
std::vector<T> result(buffer.get_create_info().size / sizeof(T));