From 2e6846f3a282e65dbd579d5c3a4af47183354ed2 Mon Sep 17 00:00:00 2001
From: Lukas Vik <10241915+LukasVik@users.noreply.github.com>
Date: Mon, 4 Mar 2024 10:55:45 +0100
Subject: [PATCH] Group signal assignments a little more logically

---
 vunit/vhdl/verification_components/src/axi_lite_master.vhd | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/vunit/vhdl/verification_components/src/axi_lite_master.vhd b/vunit/vhdl/verification_components/src/axi_lite_master.vhd
index e33da4061..31cf604c0 100644
--- a/vunit/vhdl/verification_components/src/axi_lite_master.vhd
+++ b/vunit/vhdl/verification_components/src/axi_lite_master.vhd
@@ -132,9 +132,8 @@ begin
         expected_resp := pop_std_ulogic_vector(request_msg) when is_axi_lite_msg(msg_type) else axi_resp_okay;
         push(reply_queue, request_msg);
 
-        araddr <= addr_this_transaction;
-
         arvalid <= '1';
+        araddr <= addr_this_transaction;
         wait until (arvalid and arready) = '1' and rising_edge(aclk);
         arvalid <= '0';
         drive_ar_invalid;