VHDL/Verilog/EDIF/SystemC Simulator build 12.0.118.7745

(c) 1997-2020 Aldec, Inc. All rights reserved.

License Number 0

VSIMSA: Configuration files: `C:\GIT_TEMP\Develop\Vunit\vunit_out\activehdl\library.cfg', `C:\GIT_TEMP\Develop\Vunit\vunit_out\activehdl\vsimsa.cfg'
 Welcome to VSIMSA!
 This message was printed from `startup.do' macro file.

log "C:\GIT_TEMP\Develop\Vunit\vunit_out\test_output\lib.tb_ftdi_interface.TC003_UPDATE_FLASH_PULSE_WIDTH_b8fdec091a2d1e809ec8214116e6d70c3522b40b\activehdl\transcript"
log -assert "C:\GIT_TEMP\Develop\Vunit\vunit_out\test_output\lib.tb_ftdi_interface.TC003_UPDATE_FLASH_PULSE_WIDTH_b8fdec091a2d1e809ec8214116e6d70c3522b40b\activehdl\transcript"
source "C:/GIT_TEMP/Develop/Vunit/vunit_out/test_output/lib.tb_ftdi_interface.TC003_UPDATE_FLASH_PULSE_WIDTH_b8fdec091a2d1e809ec8214116e6d70c3522b40b/activehdl/common.tcl"
VSIM: Warning: SLP acceleration cannot be used when -advdataflow is in effect. SLP acceleration disabled.
ELBREAD: Elaboration process.
ELBREAD: Elaboration time 0.0 [s].
KERNEL: Warning: Some or all source files were compiled for Path Coverage but Path Coverage was not enabled at simulation initialization.
KERNEL: Main thread initiated.
KERNEL: Kernel process initialization phase.
ELAB2: Elaboration final pass...
KERNEL: Warning: Some or all source files were compiled for Expression/Condition Coverage but Expression/Condition Coverage was not enabled at simulation initialization.
KERNEL: PLI/VHPI kernel's engine initialization done.
PLI: Loading library 'C:\Aldec\Active-HDL-12.0-x64\bin\systf.dll'
VHPI: Loading library 'systf.dll'
ELAB2: Create instances ...
KERNEL: Time resolution set to 1ps.
ELAB2: Create instances complete.
ELAB2: Elaboration final pass complete - time: 0.1 [s].
ACDB: Code Coverage session started in hierarchical mode for local units.
KERNEL: Kernel process initialization done.
Allocation: Simulator allocated 26246 kB (elbread=428 elab2=22492 kernel=3326 sdf=0)
ASDB: Error: remove: "C:\GIT_TEMP\Develop\Vunit\vunit_out\activehdl\wave.asdbw\strings.data": The process cannot access the file because it is being used by another process. 
VSIM: Error: Fatal error occurred during simulation.
set failed [vunit_load]
if {$failed} {quit -code 1}
ACDB: Statement and Branch Coverage data has been saved to "C:/GIT_TEMP/Develop/Vunit/vunit_out/test_output/lib.tb_ftdi_interface.TC003_UPDATE_FLASH_PULSE_WIDTH_b8fdec091a2d1e809ec8214116e6d70c3522b40b/coverage.acdb" database.
ACDB: Closing Code Coverage session.
VSIM: Simulation has finished.