See Vitis Development Environment on xilinx.com |
The tutorials under the AI Engine Development help you learn how to target, develop, and deploy advanced algorithms using a Versal AI Engine array in conjunction with PL IP/kernels and software applications running on the embedded processors. To successfully deploy AI Engine applications in hardware, you need to be aware of the Vitis and AI Engine tools and flows.
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The AI Engine Development Feature Tutorials highlight specific features and flows that help develop AI Engine applications.
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The AI Engine Development Design Tutorials showcase the two major phases of AI Engine application development: architecting the application and developing the kernels. Both phases are demonstrated in these tutorials.
To easily find the right documentation corresponding to the development stage you are at, we recommend you use the AI Engine Design Process Hub.
The major documentation for AI Engine includes:
- Versal ACAP AI Engine Architecture Manual AM009
- AI Engine Tools and Flows UG1076
- AI Engine Kernel and Graph Programming Guide UG1079
If you are new with AI Engine, the following training courses can help you understand the architechure and design flow.
- Designing with Versal AI Engine 1: Architecture and Design Flow
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
- Designing with Versal AI Engine 3: Kernel Programming and Optimization
IMPORTANT: Before beginning the tutorial make sure you have read and followed the Vitis Software Platform Release Notes (v2024.1) for setting up software and installing the VCK190 base platform.
Run the following steps to setup environment (do NOT apply to tutorials that do not use the VCK190 base platform):
- Set up your platform by running the
xilinx-versal-common-v2024.1/environment-setup-cortexa72-cortexa53-xilinx-linuxscript as provided in the platform download. This script sets up theSYSROOTandCXXvariables. If the script is not present, you must run thexilinx-versal-common-v2024.1/sdk.sh. - Set up your
ROOTFSto point to thexilinx-versal-common-v2024.1/rootfs.ext4. - Set up your
IMAGEto point toxilinx-versal-common-v2024.1/Image. - Set up your
PLATFORM_REPO_PATHSenvironment variable based upon where you downloaded the platform.
If you are new with the AI Engine Architecture and tools, we recommend that you start with the A to Z Bare-metal Flow, which will guide you through the entire flow from platform creation in AMD Vivado™ to AI Engine application creation, system integration and testing on Hardware using the Vitis IDE.
To get started with AI Engine application development, we recommend that you look at the following tutorials:
- DSP Library Tutorial which will guide you to create an AI Engine using application using the AMD provided DSP library
- AIE DSPLib and Model Composer which will also guide you to create an AI Engine using application using the AMD provided DSP library but using the ModelComposer tool which enables easy designs through a MATLAB Simulink environment.
- Using GMIO with AIE which goes through using the GMIOs for connectivity between the AI Engine and the DDR (through the NoC)
- Implementing an IIR Filter on the AIE will guide you into custom kernel coding using a IIR application
The following tutorials describe some features of the AI Engine, which might be useful for your application:
After you have written your first AI Engine application you might want to verify the correct functionality of your graphs and kernels using x86 simulation and AI Engine simulation. In this regards, the following tutorials will be useful for you:
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Debug Walkthrough Tutorial will guide you to analyze the performance of your AI Engine application and help you with debugging functional issues.
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AIE Performance and Deadlock Analysis which introduces you to performance analysis and optimization methods, and shows you how synchronization works in graph execution.
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Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows: This tutorial demonstrates how to create external traffic generators as Python scripts or C++ applications to exercise the AI Engine kernels in the x86 simulator, AI Engine simulator, and in hardware emulation.
When your AI Engine Application meets your expectation (in terms of functionality and performances), it will be the right time to integrate it with the rest of the Versal System. At this stage, the following tutorials will be useful for you:
- AIE Versal Integration. This tutorial demonstrates creating a system design running on the AI Engine, PS, and Programmable Logic (PL).
- Versal System Design Clocking. In this tutorial, you will learn clocking concepts for the Vitis compiler and how to define clocking for an ADF Graph, as well as PL kernels using clocking automation functionality.
- Versal Emulation Waveform Analysis which demonstrates how you can use the Vivado Design Suite logic simulator (XSIM) waveform GUI, and the Vitis analyzer to debug and analyze your design.
These tutorials target the VCK190 board. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in.
| Tutorial | Platform | OS | IDE Flow | Libraries Used | HLS Kernel | x86 simulator | aie simulator | SW Emu | HW Emu | HW | Event Trace in HW | Profile in HW |
| AI Engine A-to-Z Flow for Linux | Base / Custom | Linux | MM2S / S2MM | Yes | Yes | Yes | Yes | Yes | ||||
| A to Z Bare-metal Flow | Custom | Baremetal | Vivado & Vitis IDE |
MM2S / S2MM | Yes | Yes | Yes | |||||
| Using GMIO with AIE | Base | Linux | Yes | Yes | Yes | Yes | ||||||
| Runtime Parameter Reconfiguration | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| Packet Switching | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| AIE Versal Integration | Base | Linux | CLI / Vitis Unified IDE | MM2S / S2MM | Yes | Yes | Yes | Yes | Yes | |||
| Versal System Design Clocking | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| Using Floating-Point in the AIE | Base | Linux | Yes | |||||||||
| DSP Library Tutorial | Base | Linux | DSPLib | MM2S / S2MM Variant | Yes | |||||||
| Debug Walkthrough Tutorial | Base | Linux | Vitis IDE | Yes | Yes | Yes | Yes | Yes | Yes | Yes | ||
| AIE DSPLib and Model Composer | Base | Linux | Simulink | DSPLib | MM2S / S2MM | Yes | Yes | |||||
| Versal Emulation Waveform Analysis | Base | Linux | Traffic Generators | Yes | ||||||||
| AXIS External Traffic Generator | Base | Linux | DSPLib | MM2S / S2MM | Yes | Yes | ||||||
| AIE Performance and Deadlock Analysis | Base | Linux | Yes | Yes | Yes | Yes | ||||||
| Implementing an IIR Filter on the AIE | Base | Linux | Vitis IDE | Yes | Yes | |||||||
| Post-Link Recompile of an AIE Application | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows | Base | Linux | MM2S / S2MM / PolarClip | Yes | Yes | Yes | Yes | |||||
| Using RTL IP with AI Engines | Custom | Linux | MM2S / S2MM | Yes | Yes | |||||||
| Using Verilog Traffic Generators in AIE Simulation | Base | Linux | Vivado | Yes | Yes | |||||||
| AIE Compiler Features | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | Yes | Yes | Yes | |||
| Two Tone Filter | Base | Linux | Yes | DSPLib | Yes | Yes | ||||||
| Performance Validation in Analysis View | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | Yes | Yes | Yes | |||
| RTL / AI Engine interfacing Examples | Custom | N/A | Vivado & Vitis IDE | Yes |
These tutorials target the VCK190 board. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in.
| Tutorial | Platform | OS | IDE Flow | Libraries Used | HLS Kernel | x86 simulator | aie simulator | SW Emu | HW Emu | HW | Event Trace in HW | Profile in HW |
| Versal Custom Thin Platform Extensible System | Custom | Linux | MM2S / S2MM / VADD | Yes | Yes | |||||||
| LeNet Tutorial | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | Yes | |||||
| Super Sampling Rate FIR Filters | Base | Linux | Yes | |||||||||
| Beamforming Design | Base | Linux | Yes | Yes | Yes | Yes | ||||||
| Polyphase Channelizer | Base | Linux | MM2S / S2MM | Yes | Yes | |||||||
| Prime Factor FFT | Base | Linux | MM2S / S2MM | Yes | Yes | |||||||
| 2D-FFT | Base | Linux | DSPLib | PL Data Generator and Checker | Yes | Yes | Yes | Yes | ||||
| FIR Filter | Base | Linux | DSPLib | PL Data Generator and Checker | Yes | Yes | Yes | Yes | ||||
| N-Body Simulator | Base | Linux | PL Datamover | Yes | Yes | Yes | ||||||
| Digital Down-conversion Chain | Base | Linux | Yes | Yes | ||||||||
| Versal GeMM Implementation | Base | Linux | DSPLib | Datamover | Yes | Yes | Yes | Yes | ||||
| Bilinear Interpolation | Base | Linux | Yes | Yes | ||||||||
| 64K IFFT Using 2D Architecture | Base | Linux | MM2S / S2MM | Yes | Yes | |||||||
| FFT and DFT on AI Engine | Base | Linux | DSPLib | Yes | Yes | |||||||
| Bitonic SIMD Sorting on AI Engine | Base | Linux | Yes | Yes | ||||||||
| Fractional Delay Farrow Filter | Base | Linux | Data Movers | Yes | Yes | Yes | Yes | |||||
| 1M Point float FFT @ 32 Gsps | Custom | Baremetal | Yes | Yes | Yes | Yes | ||||||
| System Partitioning of a Hough Transform | Base | Linux | Yes | Yes | ||||||||
| MUSIC Algorithm on AI Engine | Base | Linux | MM2S / S2MM | Yes | ||||||||
| Softmax Function on AI Engine | Base | Linux | Yes | Yes |
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