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constraints.xdc
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constraints.xdc
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set_property IOSTANDARD LVCMOS33 [get_ports *]
set_property PACKAGE_PIN B7 [get_ports {vga_r[3]}]
set_property PACKAGE_PIN C5 [get_ports {vga_r[2]}]
set_property PACKAGE_PIN C6 [get_ports {vga_r[1]}]
set_property PACKAGE_PIN F5 [get_ports {vga_r[0]}]
set_property PACKAGE_PIN D8 [get_ports {vga_g[3]}]
set_property PACKAGE_PIN A5 [get_ports {vga_g[2]}]
set_property PACKAGE_PIN A6 [get_ports {vga_g[1]}]
set_property PACKAGE_PIN B6 [get_ports {vga_g[0]}]
set_property PACKAGE_PIN E7 [get_ports {vga_b[3]}]
set_property PACKAGE_PIN E5 [get_ports {vga_b[2]}]
set_property PACKAGE_PIN E6 [get_ports {vga_b[1]}]
set_property PACKAGE_PIN C7 [get_ports {vga_b[0]}]
set_property PACKAGE_PIN G2 [get_ports {tube_en[7]}]
set_property PACKAGE_PIN C2 [get_ports {tube_en[6]}]
set_property PACKAGE_PIN C1 [get_ports {tube_en[5]}]
set_property PACKAGE_PIN H1 [get_ports {tube_en[4]}]
set_property PACKAGE_PIN G1 [get_ports {tube_en[3]}]
set_property PACKAGE_PIN F1 [get_ports {tube_en[2]}]
set_property PACKAGE_PIN E1 [get_ports {tube_en[1]}]
set_property PACKAGE_PIN G6 [get_ports {tube_en[0]}]
set_property PACKAGE_PIN D5 [get_ports {tube_l[7]}]
set_property PACKAGE_PIN B2 [get_ports {tube_l[6]}]
set_property PACKAGE_PIN B3 [get_ports {tube_l[5]}]
set_property PACKAGE_PIN A1 [get_ports {tube_l[4]}]
set_property PACKAGE_PIN B1 [get_ports {tube_l[3]}]
set_property PACKAGE_PIN A3 [get_ports {tube_l[2]}]
set_property PACKAGE_PIN A4 [get_ports {tube_l[1]}]
set_property PACKAGE_PIN B4 [get_ports {tube_l[0]}]
set_property PACKAGE_PIN H2 [get_ports {tube_r[7]}]
set_property PACKAGE_PIN D2 [get_ports {tube_r[6]}]
set_property PACKAGE_PIN E2 [get_ports {tube_r[5]}]
set_property PACKAGE_PIN F3 [get_ports {tube_r[4]}]
set_property PACKAGE_PIN F4 [get_ports {tube_r[3]}]
set_property PACKAGE_PIN D3 [get_ports {tube_r[2]}]
set_property PACKAGE_PIN E3 [get_ports {tube_r[1]}]
set_property PACKAGE_PIN D4 [get_ports {tube_r[0]}]
set_property PACKAGE_PIN R15 [get_ports c_btn_r]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN R17 [get_ports d_btn_r]
set_property PACKAGE_PIN V1 [get_ports l_btn_r]
set_property PACKAGE_PIN K2 [get_ports out_1]
set_property PACKAGE_PIN R11 [get_ports r_btn_r]
set_property PACKAGE_PIN P15 [get_ports reset]
set_property PACKAGE_PIN R1 [get_ports swch_1_r]
set_property PACKAGE_PIN N4 [get_ports swch_2_r]
set_property PACKAGE_PIN M4 [get_ports swch_3_r]
set_property PACKAGE_PIN P4 [get_ports swch_6_r]
set_property PACKAGE_PIN P5 [get_ports swch_7_r]
set_property PACKAGE_PIN U4 [get_ports u_btn_r]
set_property PACKAGE_PIN D7 [get_ports vga_hsync]
set_property PACKAGE_PIN C4 [get_ports vga_vsync]
set_max_delay -from [get_pins -hierarchical -filter { NAME =~ "*a_angle_reg*" && NAME !~ "*_i*" && NAME =~ "*/C*" && NAME !~ "*/CE*" && DIRECTION == "IN" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_ix_reg*" && NAME =~ "*/D*" }] 75.000
set_max_delay -from [get_pins -hierarchical -filter { NAME =~ "*a_angle_reg*" && NAME !~ "*_i*" && NAME =~ "*/C*" && NAME !~ "*/CE*" && DIRECTION == "IN" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_iy_reg*" && NAME =~ "*/D*" }] 75.000
set_max_delay -from [get_pins -hierarchical -filter { NAME =~ "*a_angle_reg*" && NAME !~ "*_i*" && NAME =~ "*/C*" && NAME !~ "*/CE*" && DIRECTION == "IN" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_sin_reg*" && NAME =~ "*/D*" }] 75.000
set_max_delay -from [get_pins -hierarchical -filter { NAME =~ "*a_angle_reg*" && NAME !~ "*_i*" && NAME =~ "*/C*" && NAME !~ "*/CE*" && DIRECTION == "IN" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_cos_reg*" && NAME =~ "*/D*" }] 75.000