Releases: YosysHQ/apicula
Releases · YosysHQ/apicula
0.0.1a12
0.0.1a11
0.0.1a10
What's Changed
- Pin modes by @yrabbit in #35
- gowin_pack: fix typo in description by @whitequark in #36
- Fuzz io standards by @yrabbit in #37
- Fix unpacking IOB by @yrabbit in #38
- check everything is (un)packed more or less in a sane way by @pepijndevos in #39
- Preparing for complex I/O modes and correcting minor errors. by @yrabbit in #40
- IOBUF + TBUF fuzzer by @yrabbit in #42
- Use aliases of I/O standards in the packer by @yrabbit in #43
- Create .cst (constraints) file from gowin_pack and gowin_unpack by @yrabbit in #44
- Fix the fuzzing of the DFFs. by @yrabbit in #46
- don't mangle 1000+ fuses by @pepijndevos in #47
- Correct a minor error in the documentation. by @yrabbit in #48
- Fix instructions for manual build of examples: by @yrabbit in #50
- Add long wire constraints. by @yrabbit in #51
New Contributors
- @yrabbit made their first contribution in #35
- @whitequark made their first contribution in #36
- @pepijndevos made their first contribution in #39
Full Changelog: 0.0.1a9...0.0.1a10
GW1NS-2C support
0.0.1a9 generate GW1NS-2 chipdb on CI
Slightly less broken
0.0.1a8 allow different reset polarity in same cls
0.0.1a6
Merge branch 'master' of github.com:pepijndevos/apicula
0.0.0.dev
Bucket