Yosys 0.19

Yosys 0.18 .. Yosys 0.19

• New commands and options

  • Added option "-rom-only" to "memory_libmap" pass
  • Added option "-smtcheck" to "hierarchy" pass
  • Added option "-keepdc" to "memory_libmap" pass
  • Added option "-suffix" to "rename" pass
  • Added "gatemate_foldinv" pass

• Formal Verification

  • Added support for $pos cell in btor backend
  • Added the "smtlib2_module" and "smtlib2_comb_expr" attributes

• GateMate support

  • Added LUT tree mapping

• Verific support

  • Added option "-pp" to "verific -import"

Yosys 0.18

Yosys 0.17 .. Yosys 0.18

• Various

  • Migrated most flows to use memory_libmap based memory inference

• New commands and options

  • Added "memory_libmap" pass
  • Added "memory_bmux2rom" pass - converts muxes to ROMs
  • Added "memory_dff -no-rw-check"
  • Added "opt_ffinv" pass - push inverters through FFs
  • Added "proc_rom" pass - convert switches to ROMs
  • Added "proc -norom" option - will omit the proc_rom pass
  • Added option "-no-rw-check" to synth passes
  • Added "synth_ice40 -spram" option for automatic inference of SB_SPRAM256KA
  • Added options "-nobram" and "-nolutram" to synth_machxo2 pass

• Formal Verification

  • Fixed the signedness of $past's return value to be the same as the
    argument's instead of always unsigned.

• Verilog

  • Fixed an issue where simplifying case statements by removing unreachable
    cases could result in the wrong signedness being used for comparison with
    the remaining cases
  • Fixed size and signedness computation for expressions containing array
    querying functions
  • Fixed size and signedness computation of functions used in ternary
    expressions or case item expressions

• Verific support

  • Proper file location for readmem commands
  • Added "-vlog-libext" option to specify search extension for libraries

Yosys 0.17

Yosys 0.16 .. Yosys 0.17

• New commands and options

  • Added "write_jny" ( JSON netlist metadata format )
  • Added "tribuf -formal"

• SystemVerilog

  • Fixed automatic nosync inference for local variables in always_comb
    procedures not applying to nested blocks and blocks in functions

Yosys 0.16

Yosys 0.15 .. Yosys 0.16

• Various

  • Added BTOR2 witness file co-simulation.
  • Simulation calls external vcd2fst for VCD conversion.
  • Added fst2tb pass - generates testbench for the circuit using
    the given top-level module and simulus signal from FST file.
  • yosys-smtbmc: Option to keep going after failed assertions in BMC mode

• Verific support

  • Import modules in alphabetic (reproducible) order.

Yosys 0.15

Yosys 0.14 .. Yosys 0.15

• Various

  • clk2fflogic: nice names for autogenerated signals
  • simulation include support for all flip-flop types.
  • Added AIGER witness file co-simulation.

• Verilog

  • Fixed evaluation of constant functions with variables or arguments with
    reversed dimensions
  • Fixed elaboration of dynamic range assignments where the vector is
    reversed or is not zero-indexed
  • Added frontend support for time scale delay values (e.g., #1ns)

• SystemVerilog

  • Added support for accessing whole sub-structures in expressions

• New commands and options

  • Added glift command, used to create gate-level information flow tracking
    (GLIFT) models by the "constructive mapping" approach

• Verific support

  • Ability to override default parser mode for verific -f command.

Yosys 0.14

Yosys 0.13 .. Yosys 0.14

• Various

  • Added $bmux and $demux cells and related optimization patterns.

• New commands and options

  • Added "bmuxmap" and "dmuxmap" passes
  • Added "-fst" option to "sim" pass for writing FST files
  • Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
    "-sim-gold" options to "sim" pass for co-simulation

• Anlogic support

  • Added support for BRAMs

Yosys 0.13

Yosys 0.12 .. Yosys 0.13

• Various

  • Use "read" command to parse HDL files from Yosys command-line
  • Added "yosys -r " command line option
  • write_verilog: dump zero width sigspecs correctly

• SystemVerilog

  • Fixed regression preventing the use array querying functions in case
    expressions and case item expressions
  • Fixed static size casts inadvertently limiting the result width of binary
    operations
  • Fixed static size casts ignoring expression signedness
  • Fixed static size casts not extending unbased unsized literals
  • Added automatic nosync inference for local variables in always_comb
    procedures which are always assigned before they are used to avoid errant
    latch inference

• New commands and options

  • Added "clean_zerowidth" pass

• Verific support

  • Add YOSYS to the implicitly defined verilog macros in verific

Yosys 0.12

Yosys 0.11 .. Yosys 0.12

• Various

  • Added iopadmap native support for negative-polarity output enable
  • ABC update

• SystemVerilog

  • Support parameters using struct as a wiretype

• New commands and options

  • Added "-genlib" option to "abc" pass
  • Added "sta" very crude static timing analysis pass

• Verific support

  • Fixed memory block size in import

• New back-ends

  • Added support for GateMate FPGA from Cologne Chip AG

• Intel ALM support

  • Added preliminary Arria V support

Yosys 0.11

Yosys 0.10 .. Yosys 0.11

• Various

  • Added $aldff and $aldffe (flip-flops with async load) cells

• SystemVerilog

  • Fixed an issue which prevented writing directly to a memory word via a
    connection to an output port
  • Fixed an issue which prevented unbased unsized literals (e.g., '1) from
    filling the width of a cell input
  • Fixed an issue where connecting a slice covering the entirety of a signed
    signal to a cell input would cause a failed assertion

• Verific support

  • Importer support for {PRIM,WIDE_OPER}_DFF
  • Importer support for PRIM_BUFIF1
  • Option to use Verific without VHDL support
  • Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  • Added -cfg option for getting/setting Verific runtime flags

Yosys 0.10

Yosys 0.9 .. Yosys 0.10.0

• Various

  • Added automatic gzip decompression for frontends
  • Added $NMUX cell type
  • Added automatic gzip compression (based on filename extension) for backends
  • Improve attribute and parameter encoding in JSON to avoid ambiguities between
    bit vectors and strings containing [01xz]*
  • Improvements in pmgen: subpattern and recursive matches
  • Support explicit FIRRTL properties
  • Improvements in pmgen: slices, choices, define, generate
  • Added "TECHMAP_WIREINIT_" parameter and "TECHMAP_REMOVEINIT_" wire for "techmap" pass
  • Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  • Added new frontend: rpc
  • Added --version and -version as aliases for -V
  • Improve yosys-smtbmc "solver not found" handling
  • Improved support of $readmem[hb] Memory Content File inclusion
  • Added CXXRTL backend
  • Use YosysHQ/abc instead of upstream berkeley-abc/abc
  • Added WASI platform support.
  • Added extmodule support to firrtl backend
  • Added $divfloor and $modfloor cells
  • Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  • Added "TECHMAP_CELLNAME" parameter for "techmap" pass
  • Added firrtl backend support for generic parameters in blackbox components
  • Added $meminit_v2 cells (with support for write mask)
  • Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
    • write priority masks, per write/write port pair
    • transparency and undefined collision behavior masks, per read/write port pair
    • read port reset and initialization
    • wide ports (accessing a naturally aligned power-of-two number of memory cells)

• New commands and options

  • Added "write_xaiger" backend
  • Added "read_xaiger"
  • Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  • Added "synth -abc9" (experimental)
  • Added "script -scriptwire"
  • Added "clkbufmap" pass
  • Added "extractinv" pass and "invertible_pin" attribute
  • Added "proc_clean -quiet"
  • Added "proc_prune" pass
  • Added "stat -tech cmos"
  • Added "opt_share" pass, run as part of "opt -full"
  • Added "-match-init" option to "dff2dffs" pass
  • Added "equiv_opt -multiclock"
  • Added "techmap_autopurge" support to techmap
  • Added "add -mod <modname[s]>"
  • Added "paramap" pass
  • Added "portlist" command
  • Added "check -mapped"
  • Added "check -allow-tbuf"
  • Added "autoname" pass
  • Added "write_verilog -extmem"
  • Added "opt_mem" pass
  • Added "scratchpad" pass
  • Added "fminit" pass
  • Added "opt_lut_ins" pass
  • Added "logger" pass
  • Added "show -nobg"
  • Added "exec" command
  • Added "design -delete"
  • Added "design -push-copy"
  • Added "qbfsat" command
  • Added "select -unset"
  • Added "dfflegalize" pass
  • Removed "opt_expr -clkinv" option, made it the default
  • Added "proc -nomux
  • Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass

• SystemVerilog

  • Added checking of always block types (always_comb, always_latch and always_ff)
  • Added support for wildcard port connections (.*)
  • Added support for enum typedefs
  • Added support for structs and packed unions.
  • Allow constant function calls in for loops and generate if and case
  • Added support for static cast
  • Added support for logic typed parameters
  • Fixed generate scoping issues
  • Added support for real-valued parameters
  • Allow localparams in constant functions
  • Module name scope support
  • Support recursive functions using ternary expressions
  • Extended support for integer types
  • Support for parameters without default values
  • Allow globals in one file to depend on globals in another
  • Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
  • Added support for parsing the 'bind' construct
  • support declaration in procedural for initialization
  • support declaration in generate for initialization
  • Support wand and wor of data types

• Verific support

  • Added "verific -L"
  • Add Verific SVA support for "always" properties
  • Add Verific support for SVA nexttime properties
  • Improve handling of verific primitives in "verific -import -V" mode
  • Import attributes for wires
  • Support VHDL enums
  • Added support for command files

• New back-ends

  • Added initial EFINIX support
  • Added Intel ALM: alternative synthesis for Intel FPGAs
  • Added initial Nexus support
  • Added initial MachXO2 support
  • Added initial QuickLogic PolarPro 3 support

• ECP5 support

  • Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
  • Added "synth_ecp5 -abc9" (experimental)
  • Added "synth_ecp5 -nowidelut"
  • "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)

• iCE40 support

  • Added "synth_ice40 -abc9" (experimental)
  • Added "synth_ice40 -device"
  • Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
  • Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
  • Removed "ice40_unlut"
  • Added "ice40_dsp" for Lattice iCE40 DSP packing
  • "synth_ice40 -dsp" to infer DSP blocks

• Xilinx support

  • Added "synth_xilinx -abc9" (experimental)
  • Added "synth_xilinx -nocarry"
  • Added "synth_xilinx -nowidelut"
  • "synth_xilinx" to now infer wide multiplexers (-widemux to enable)
  • Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
  • Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
  • Added "synth_xilinx -ise" (experimental)
  • Added "synth_xilinx -iopad"
  • "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
  • Added "xilinx_srl" for Xilinx shift register extraction
  • Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
  • Added "xilinx_dsp" for Xilinx DSP packing
  • "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
  • Added latch support to synth_xilinx
  • Added support for flip-flops with synchronous reset to synth_xilinx
  • Added support for flip-flops with reset and enable to synth_xilinx
  • Added "xilinx_dffopt" pass
  • Added "synth_xilinx -dff"

• Intel support

  • Renamed labels in synth_intel (e.g. bram -> map_bram)
  • synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
  • Added "intel_alm -abc9" (experimental)

• CoolRunner2 support

  • Separate and improve buffer cell insertion pass
  • Use extract_counter to optimize counters