Merge pull request #93 from YuzukiHD/dev

avaota add board memtester test
YuzukiHD · May 30, 2024 · f0370b5 · f0370b5
2 parents 7335ddf + f01a996
commit f0370b5
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Showing 3 changed files with 140 additions and 119 deletions.
diff --git a/board/avaota-a1/extlinux_boot/main.c b/board/avaota-a1/extlinux_boot/main.c
@@ -381,7 +381,7 @@ static int update_pmu_ext_info_dtb(image_info_t *image) {
     return 0;
 }
 
-static char to_hex_char(uint8_t value) {
+static inline char to_hex_char(uint8_t value) {
     return (value < 10) ? ('0' + value) : ('A' + value - 10);
 }
 

diff --git a/board/avaota-a1/init_dram/main.c b/board/avaota-a1/init_dram/main.c
@@ -11,12 +11,13 @@
 #include <common.h>
 
 #include <pmu/axp.h>
+#include <sys-clk.h>
 #include <sys-dram.h>
 #include <sys-i2c.h>
 
 extern sunxi_serial_t uart_dbg;
-
 extern sunxi_i2c_t i2c_pmu;
+extern uint32_t dram_para[32];
 
 extern void set_rpio_power_mode(void);
 extern void rtc_set_vccio_det_spare(void);
@@ -27,46 +28,74 @@ extern void rtc_set_vccio_det_spare(void);
 int main(void) {
     sunxi_serial_init(&uart_dbg);
 
-    show_banner();
-
-    sunxi_clk_init();
+    arm32_dcache_enable();
+    arm32_icache_enable();
 
-    sunxi_clk_dump();
+    show_banner();
 
     rtc_set_vccio_det_spare();
 
+    sunxi_clk_init();
+
     set_rpio_power_mode();
 
+    sunxi_clk_dump();
+
     sunxi_i2c_init(&i2c_pmu);
 
+    pmu_axp2202_init(&i2c_pmu);
+
     pmu_axp1530_init(&i2c_pmu);
 
-    pmu_axp2202_init(&i2c_pmu);
+    pmu_axp2202_set_vol(&i2c_pmu, "dcdc1", 1100, 1);
+
+    pmu_axp1530_set_dual_phase(&i2c_pmu);
+    pmu_axp1530_set_vol(&i2c_pmu, "dcdc1", 1100, 1);
+    pmu_axp1530_set_vol(&i2c_pmu, "dcdc2", 1100, 1);
 
+    pmu_axp2202_set_vol(&i2c_pmu, "dcdc2", 920, 1);
     pmu_axp2202_set_vol(&i2c_pmu, "dcdc3", 1160, 1);
+    pmu_axp2202_set_vol(&i2c_pmu, "dcdc4", 3300, 1);
 
-    mdelay(30); /* Delay 300ms for pmu bootup */
+    pmu_axp2202_set_vol(&i2c_pmu, "bldo3", 1800, 1);
+    pmu_axp2202_set_vol(&i2c_pmu, "bldo1", 1800, 1);
 
+    pmu_axp2202_dump(&i2c_pmu);
     pmu_axp1530_dump(&i2c_pmu);
 
-    pmu_axp2202_dump(&i2c_pmu);
+    sunxi_clk_set_cpu_pll(1800);
 
     enable_sram_a3();
 
-    uint64_t dram_size = sunxi_dram_init(NULL);
+    uint64_t dram_size = sunxi_dram_init(&dram_para);
+    arm32_mmu_enable(SDRAM_BASE, dram_size);
+    printk_info("DRAM: DRAM Size = %dMB", dram_size);
 
-    printk_info("DRAM: DRAM Size = %dMB\n", dram_size);
+    /* PLL DDR0 */
+    uint32_t reg32 = read32(CCU_BASE + CCU_PLL_DDR0_CTRL_REG);
+    if (reg32 & (1 << 31)) {
+        uint32_t plln = ((reg32 >> 8) & 0xff) + 1;
 
-    sunxi_clk_dump();
+        uint32_t pllm = (reg32 & 0x01) + 1;
+        uint32_t p1 = ((reg32 >> 1) & 0x1) + 1;
+        uint32_t p0 = (reg32 & 0x01) + 1;
+
+        printk(LOG_LEVEL_MUTE, ", DRAM CLK = %luMHz", (24 * plln) / (p0 * p1));
+    }
 
-    do_memtester(SDRAM_BASE, dram_size * 1024 * 1024);
+    printk(LOG_LEVEL_MUTE, "\n");
+
+    sunxi_clk_dump();
 
-    int i = 0;
+#define DRAM_TEST_SIZE 32 * 1024 * 1024
+#define DRAM_SIZE_BYTE dram_size * 1024 * 1024
 
+    static int i = 0;
     while (1) {
+        do_memtester((uint64_t) SDRAM_BASE, DRAM_SIZE_BYTE, DRAM_TEST_SIZE, i);
+        do_memtester((uint64_t) SDRAM_BASE + (uint64_t) 0x40000000, DRAM_SIZE_BYTE, DRAM_TEST_SIZE, i);
+        do_memtester((uint64_t) SDRAM_BASE + (uint64_t) 0x80000000, DRAM_SIZE_BYTE, DRAM_TEST_SIZE, i);
         i++;
-        printk_info("Count: %d\n", i);
-        mdelay(1000);
     }
 
     abort();