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[board] avaota-a1: set GICR_WAKER bit 2 for BL31 #104

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merged 4 commits into from
Jun 9, 2024

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BigfootACA
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GICR_WAKER is GIC Redistributor Power Management Control Register, the second bit is Processor Sleep (WAKER_CA_BIT in BL31)

BL31 require GICR_WAKER bit 2 to be 1, otherwise it crashes.

ASSERT: drivers/arm/gic/v3/gicv3_helpers.c:28:(gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U

when boot from SD Card, GICR_WAKER is 0x6
when boot from USB Fel, GICR_WAKER is 0x0

simply setting this bit to 1 will make bl31 to work properly

@YuzukiTsuru
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Move gicr_set_waker to jump to bl31, if change it in start.S you will not able back to USB FEL.

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do not use 0x60014, add new define in reg-ncat.h
like

#define GIC_IROUTR(_n)       (SUNXI_GIC600_BASE + 0x6000 + 8 * (_n))
#define GICR_LPI_BASE(n)     (SUNXI_GIC600_BASE + 0x60000 + n*0x20000)
#define GICR_WAKER(m)        (GICR_LPI_BASE(m) + 0x0014)
#define GICR_PWRR(m)         (GICR_LPI_BASE(m) + 0x0024)
#define LEVEL_TRIGERRED      (0)
#define EDGE_TRIGERRED       (1)
#define GIC_IRQ_TYPE_CFG(_n)	(SUNXI_GIC600_BASE + 0xc00 + 4 * (_n))
#define GIC_IRQ_MOD_CFG(_n)	(SUNXI_GIC600_BASE + 0xd00 + 4 * (_n))

using gicr_set_waker in

clean_syterkit_data();
jmp_to_arm64(CONFIG_BL31_LOAD_ADDR);

    clean_syterkit_data();
    gicr_set_waker();
    jmp_to_arm64(CONFIG_BL31_LOAD_ADDR);

GICR_WAKER is GIC Redistributor Power Management Control Register,
the second bit is Processor Sleep (WAKER_CA_BIT in BL31)

BL31 require GICR_WAKER bit 2 to be 1, otherwise it crashes.

ASSERT: drivers/arm/gic/v3/gicv3_helpers.c:28:(gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U

when boot from SD Card, GICR_WAKER is 0x6
when boot from USB Fel, GICR_WAKER is 0x0

simply setting this bit to 1 will make bl31 to work properly
@BigfootACA
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all problems are fixed, thank!

@YuzukiTsuru YuzukiTsuru merged commit 55d3aba into YuzukiHD:main Jun 9, 2024
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2 participants