diff --git a/CMakeLists.txt b/CMakeLists.txt index eea4fb539..ae68a1861 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ # Specify the minimum required version of CMake cmake_minimum_required(VERSION 3.10) @@ -94,10 +94,11 @@ else () endif () # Define the project name and languages used -project(SyterKit VERSION 0.3.0 LANGUAGES C CXX ASM) +project(SyterKit VERSION 0.4.0 LANGUAGES C CXX ASM) # Include other CMake modules include(cmake/add_syterkit_app.cmake) +include(cmake/add_syterkit_driver.cmake) # Get the name of the compiler string(SUBSTRING ${CMAKE_C_COMPILER} 1 -1 COMPILER_NAME) @@ -234,6 +235,7 @@ include_directories( include/drivers/reg include/drivers/usb include/drivers/mtd + include/drivers/intc include/lib/fatfs include/lib/fdt include/lib/elf diff --git a/LICENSE.GPL2.0 b/LICENSE similarity index 100% rename from LICENSE.GPL2.0 rename to LICENSE diff --git a/LICENSE.GPL3.0 b/LICENSE.GPL3.0 deleted file mode 100644 index f288702d2..000000000 --- a/LICENSE.GPL3.0 +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/board/100ask-d1-h/board.c b/board/100ask-d1-h/board.c index 04e010fae..57b661f7d 100644 --- a/board/100ask-d1-h/board.c +++ b/board/100ask-d1-h/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-d1-h/eabi_compat.c b/board/100ask-d1-h/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/100ask-d1-h/eabi_compat.c +++ b/board/100ask-d1-h/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/100ask-d1-h/head.c b/board/100ask-d1-h/head.c index 80c77b37c..8c2a1d7de 100644 --- a/board/100ask-d1-h/head.c +++ b/board/100ask-d1-h/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-d1-h/hello_world/CMakeLists.txt b/board/100ask-d1-h/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/100ask-d1-h/hello_world/CMakeLists.txt +++ b/board/100ask-d1-h/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/100ask-d1-h/hello_world/main.c b/board/100ask-d1-h/hello_world/main.c index 2df8a8ade..25044faf9 100644 --- a/board/100ask-d1-h/hello_world/main.c +++ b/board/100ask-d1-h/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-d1-h/init_dram/CMakeLists.txt b/board/100ask-d1-h/init_dram/CMakeLists.txt index cc4627c58..8d9c9c1c1 100644 --- a/board/100ask-d1-h/init_dram/CMakeLists.txt +++ b/board/100ask-d1-h/init_dram/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(init_dram main.c diff --git a/board/100ask-d1-h/init_dram/main.c b/board/100ask-d1-h/init_dram/main.c index d108e2377..61ecafe2a 100644 --- a/board/100ask-d1-h/init_dram/main.c +++ b/board/100ask-d1-h/init_dram/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-d1-h/load_hifi4/CMakeLists.txt b/board/100ask-d1-h/load_hifi4/CMakeLists.txt index 9ee55cfeb..6daa27e2b 100644 --- a/board/100ask-d1-h/load_hifi4/CMakeLists.txt +++ b/board/100ask-d1-h/load_hifi4/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(load_hifi4 main.c diff --git a/board/100ask-d1-h/load_hifi4/main.c b/board/100ask-d1-h/load_hifi4/main.c index 1dd3068e7..c4468c7a8 100644 --- a/board/100ask-d1-h/load_hifi4/main.c +++ b/board/100ask-d1-h/load_hifi4/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-d1-h/start.S b/board/100ask-d1-h/start.S index e3b30d12a..eb83d30ff 100644 --- a/board/100ask-d1-h/start.S +++ b/board/100ask-d1-h/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-d1-h/syter_boot/CMakeLists.txt b/board/100ask-d1-h/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/100ask-d1-h/syter_boot/CMakeLists.txt +++ b/board/100ask-d1-h/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/100ask-d1-h/syter_boot/main.c b/board/100ask-d1-h/syter_boot/main.c index f6262cfed..14ea87c3c 100644 --- a/board/100ask-d1-h/syter_boot/main.c +++ b/board/100ask-d1-h/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-ros/board.c b/board/100ask-ros/board.c index b359222a3..fa9847870 100644 --- a/board/100ask-ros/board.c +++ b/board/100ask-ros/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-ros/eabi_compat.c b/board/100ask-ros/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/100ask-ros/eabi_compat.c +++ b/board/100ask-ros/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/100ask-ros/extlinux_boot/CMakeLists.txt b/board/100ask-ros/extlinux_boot/CMakeLists.txt index 4127a920e..76896b188 100644 --- a/board/100ask-ros/extlinux_boot/CMakeLists.txt +++ b/board/100ask-ros/extlinux_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(extlinux_boot main.c diff --git a/board/100ask-ros/extlinux_boot/fdt.c b/board/100ask-ros/extlinux_boot/fdt.c index 57f70831c..93eb8ed74 100644 --- a/board/100ask-ros/extlinux_boot/fdt.c +++ b/board/100ask-ros/extlinux_boot/fdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifdef SYTERKIT_CLI_CMD_FDT msh_declare_command(fdt); diff --git a/board/100ask-ros/extlinux_boot/main.c b/board/100ask-ros/extlinux_boot/main.c index e7abc39ab..078161c12 100644 --- a/board/100ask-ros/extlinux_boot/main.c +++ b/board/100ask-ros/extlinux_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-ros/head.c b/board/100ask-ros/head.c index 05d101a78..d4d47332c 100644 --- a/board/100ask-ros/head.c +++ b/board/100ask-ros/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-ros/hello_world/CMakeLists.txt b/board/100ask-ros/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/100ask-ros/hello_world/CMakeLists.txt +++ b/board/100ask-ros/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/100ask-ros/hello_world/main.c b/board/100ask-ros/hello_world/main.c index a3ff9e8f1..f857e9de4 100644 --- a/board/100ask-ros/hello_world/main.c +++ b/board/100ask-ros/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-ros/init_dram/CMakeLists.txt b/board/100ask-ros/init_dram/CMakeLists.txt index cc4627c58..8d9c9c1c1 100644 --- a/board/100ask-ros/init_dram/CMakeLists.txt +++ b/board/100ask-ros/init_dram/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(init_dram main.c diff --git a/board/100ask-ros/init_dram/main.c b/board/100ask-ros/init_dram/main.c index 33370fd4a..45df91af0 100644 --- a/board/100ask-ros/init_dram/main.c +++ b/board/100ask-ros/init_dram/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-ros/smhc_test/CMakeLists.txt b/board/100ask-ros/smhc_test/CMakeLists.txt index 1ea20e493..9be87d6f0 100644 --- a/board/100ask-ros/smhc_test/CMakeLists.txt +++ b/board/100ask-ros/smhc_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(smhc_test main.c diff --git a/board/100ask-ros/smhc_test/main.c b/board/100ask-ros/smhc_test/main.c index 4eda750a5..6151a8ef3 100644 --- a/board/100ask-ros/smhc_test/main.c +++ b/board/100ask-ros/smhc_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-ros/start.S b/board/100ask-ros/start.S index 529e63636..11e4fdfd3 100644 --- a/board/100ask-ros/start.S +++ b/board/100ask-ros/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/100ask-ros/syter_boot/CMakeLists.txt b/board/100ask-ros/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/100ask-ros/syter_boot/CMakeLists.txt +++ b/board/100ask-ros/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/100ask-ros/syter_boot/main.c b/board/100ask-ros/syter_boot/main.c index e1fbbcda2..caa75882d 100644 --- a/board/100ask-ros/syter_boot/main.c +++ b/board/100ask-ros/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113i/board.c b/board/100ask-t113i/board.c index 5b103feee..b3f842793 100644 --- a/board/100ask-t113i/board.c +++ b/board/100ask-t113i/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-t113i/eabi_compat.c b/board/100ask-t113i/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/100ask-t113i/eabi_compat.c +++ b/board/100ask-t113i/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/100ask-t113i/head.c b/board/100ask-t113i/head.c index 05d101a78..d4d47332c 100644 --- a/board/100ask-t113i/head.c +++ b/board/100ask-t113i/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-t113i/hello_world/CMakeLists.txt b/board/100ask-t113i/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/100ask-t113i/hello_world/CMakeLists.txt +++ b/board/100ask-t113i/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/100ask-t113i/hello_world/main.c b/board/100ask-t113i/hello_world/main.c index 726d614a9..70c93f708 100644 --- a/board/100ask-t113i/hello_world/main.c +++ b/board/100ask-t113i/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113i/load_c906/CMakeLists.txt b/board/100ask-t113i/load_c906/CMakeLists.txt index edf4245ae..04835824c 100644 --- a/board/100ask-t113i/load_c906/CMakeLists.txt +++ b/board/100ask-t113i/load_c906/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(load_c906 main.c diff --git a/board/100ask-t113i/load_c906/main.c b/board/100ask-t113i/load_c906/main.c index 1851f19f9..5c494a559 100644 --- a/board/100ask-t113i/load_c906/main.c +++ b/board/100ask-t113i/load_c906/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113i/load_hifi4/CMakeLists.txt b/board/100ask-t113i/load_hifi4/CMakeLists.txt index 9ee55cfeb..6daa27e2b 100644 --- a/board/100ask-t113i/load_hifi4/CMakeLists.txt +++ b/board/100ask-t113i/load_hifi4/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(load_hifi4 main.c diff --git a/board/100ask-t113i/load_hifi4/main.c b/board/100ask-t113i/load_hifi4/main.c index b0f9f94df..9a3320a0e 100644 --- a/board/100ask-t113i/load_hifi4/main.c +++ b/board/100ask-t113i/load_hifi4/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113i/os_test/CMakeLists.txt b/board/100ask-t113i/os_test/CMakeLists.txt index b54c6d0d9..8504c2c0f 100644 --- a/board/100ask-t113i/os_test/CMakeLists.txt +++ b/board/100ask-t113i/os_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(os_test main.c diff --git a/board/100ask-t113i/os_test/main.c b/board/100ask-t113i/os_test/main.c index f7cf0914c..2e006cc9a 100644 --- a/board/100ask-t113i/os_test/main.c +++ b/board/100ask-t113i/os_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113i/start.S b/board/100ask-t113i/start.S index 179f110e9..d227c0c00 100644 --- a/board/100ask-t113i/start.S +++ b/board/100ask-t113i/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/100ask-t113i/sys_info/CMakeLists.txt b/board/100ask-t113i/sys_info/CMakeLists.txt index c559a1abb..26242f673 100644 --- a/board/100ask-t113i/sys_info/CMakeLists.txt +++ b/board/100ask-t113i/sys_info/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(sys_info main.c diff --git a/board/100ask-t113i/sys_info/main.c b/board/100ask-t113i/sys_info/main.c index e85234c2e..4a89ab8ef 100644 --- a/board/100ask-t113i/sys_info/main.c +++ b/board/100ask-t113i/sys_info/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113i/syter_boot/CMakeLists.txt b/board/100ask-t113i/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/100ask-t113i/syter_boot/CMakeLists.txt +++ b/board/100ask-t113i/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/100ask-t113i/syter_boot/main.c b/board/100ask-t113i/syter_boot/main.c index cc151c93a..c38441a4f 100644 --- a/board/100ask-t113i/syter_boot/main.c +++ b/board/100ask-t113i/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113s3/board.c b/board/100ask-t113s3/board.c index eaffca872..ace8bc24f 100644 --- a/board/100ask-t113s3/board.c +++ b/board/100ask-t113s3/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-t113s3/eabi_compat.c b/board/100ask-t113s3/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/100ask-t113s3/eabi_compat.c +++ b/board/100ask-t113s3/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/100ask-t113s3/head.c b/board/100ask-t113s3/head.c index 05d101a78..d4d47332c 100644 --- a/board/100ask-t113s3/head.c +++ b/board/100ask-t113s3/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/100ask-t113s3/hello_world/CMakeLists.txt b/board/100ask-t113s3/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/100ask-t113s3/hello_world/CMakeLists.txt +++ b/board/100ask-t113s3/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/100ask-t113s3/hello_world/main.c b/board/100ask-t113s3/hello_world/main.c index 726d614a9..70c93f708 100644 --- a/board/100ask-t113s3/hello_world/main.c +++ b/board/100ask-t113s3/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113s3/load_hifi4/CMakeLists.txt b/board/100ask-t113s3/load_hifi4/CMakeLists.txt index 9ee55cfeb..6daa27e2b 100644 --- a/board/100ask-t113s3/load_hifi4/CMakeLists.txt +++ b/board/100ask-t113s3/load_hifi4/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(load_hifi4 main.c diff --git a/board/100ask-t113s3/load_hifi4/main.c b/board/100ask-t113s3/load_hifi4/main.c index b0f9f94df..9a3320a0e 100644 --- a/board/100ask-t113s3/load_hifi4/main.c +++ b/board/100ask-t113s3/load_hifi4/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113s3/start.S b/board/100ask-t113s3/start.S index 179f110e9..d227c0c00 100644 --- a/board/100ask-t113s3/start.S +++ b/board/100ask-t113s3/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/100ask-t113s3/syter_boot_rtt/CMakeLists.txt b/board/100ask-t113s3/syter_boot_rtt/CMakeLists.txt index 4429be4ce..97b1af205 100644 --- a/board/100ask-t113s3/syter_boot_rtt/CMakeLists.txt +++ b/board/100ask-t113s3/syter_boot_rtt/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_rtt main.c diff --git a/board/100ask-t113s3/syter_boot_rtt/main.c b/board/100ask-t113s3/syter_boot_rtt/main.c index b3430db2e..82e5fad0d 100644 --- a/board/100ask-t113s3/syter_boot_rtt/main.c +++ b/board/100ask-t113s3/syter_boot_rtt/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/100ask-t113s3/usb_test/CMakeLists.txt b/board/100ask-t113s3/usb_test/CMakeLists.txt index b345462d4..d32d5cc99 100644 --- a/board/100ask-t113s3/usb_test/CMakeLists.txt +++ b/board/100ask-t113s3/usb_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(usb_test main.c diff --git a/board/100ask-t113s3/usb_test/main.c b/board/100ask-t113s3/usb_test/main.c index 8e085fa44..c9f964a46 100644 --- a/board/100ask-t113s3/usb_test/main.c +++ b/board/100ask-t113s3/usb_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/CMakeLists.txt b/board/CMakeLists.txt index a9dea4a68..6b8bf9b78 100644 --- a/board/CMakeLists.txt +++ b/board/CMakeLists.txt @@ -52,4 +52,8 @@ endif() if(CONFIG_BOARD_AVAOTA-CAM) add_subdirectory(avaota-cam) +endif() + +if(CONFIG_BOARD_AVAOTA-NAS) + add_subdirectory(avaota-nas) endif() \ No newline at end of file diff --git a/board/avaota-a1/board.c b/board/avaota-a1/board.c index 60dfa5d67..661fc7a44 100644 --- a/board/avaota-a1/board.c +++ b/board/avaota-a1/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include @@ -140,7 +142,7 @@ sunxi_sdhci_t sdhci2 = { .id = MMC_CONTROLLER_2, .reg_base = SUNXI_SMHC2_BASE, .sdhci_mmc_type = MMC_TYPE_EMMC, - .max_clk = 25000000, + .max_clk = 5200000, .width = SMHC_WIDTH_8BIT, .dma_des_addr = SDRAM_BASE + 0x30080000, .pinctrl = { @@ -168,7 +170,7 @@ sunxi_sdhci_t sdhci2 = { .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, .clk_sel = 0x1, - .parent_clk = 600000000, + .parent_clk = 800000000, }, }; diff --git a/board/avaota-a1/eabi_compat.c b/board/avaota-a1/eabi_compat.c index fe4ce09ab..8f1826f83 100644 --- a/board/avaota-a1/eabi_compat.c +++ b/board/avaota-a1/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/avaota-a1/extlinux_boot/CMakeLists.txt b/board/avaota-a1/extlinux_boot/CMakeLists.txt index 4127a920e..76896b188 100644 --- a/board/avaota-a1/extlinux_boot/CMakeLists.txt +++ b/board/avaota-a1/extlinux_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(extlinux_boot main.c diff --git a/board/avaota-a1/extlinux_boot/fdt.c b/board/avaota-a1/extlinux_boot/fdt.c index 57f70831c..93eb8ed74 100644 --- a/board/avaota-a1/extlinux_boot/fdt.c +++ b/board/avaota-a1/extlinux_boot/fdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifdef SYTERKIT_CLI_CMD_FDT msh_declare_command(fdt); diff --git a/board/avaota-a1/extlinux_boot/main.c b/board/avaota-a1/extlinux_boot/main.c index e17c98a4e..4b8e046bb 100644 --- a/board/avaota-a1/extlinux_boot/main.c +++ b/board/avaota-a1/extlinux_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/extlinux_boot/spi_lcd.c b/board/avaota-a1/extlinux_boot/spi_lcd.c index 9283cfc7b..a98b0e02c 100644 --- a/board/avaota-a1/extlinux_boot/spi_lcd.c +++ b/board/avaota-a1/extlinux_boot/spi_lcd.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/head.c b/board/avaota-a1/head.c index 05d101a78..d4d47332c 100644 --- a/board/avaota-a1/head.c +++ b/board/avaota-a1/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/avaota-a1/hello_world/CMakeLists.txt b/board/avaota-a1/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/avaota-a1/hello_world/CMakeLists.txt +++ b/board/avaota-a1/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/avaota-a1/hello_world/main.c b/board/avaota-a1/hello_world/main.c index a3ff9e8f1..f857e9de4 100644 --- a/board/avaota-a1/hello_world/main.c +++ b/board/avaota-a1/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/init_dram/CMakeLists.txt b/board/avaota-a1/init_dram/CMakeLists.txt index cc4627c58..8d9c9c1c1 100644 --- a/board/avaota-a1/init_dram/CMakeLists.txt +++ b/board/avaota-a1/init_dram/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(init_dram main.c diff --git a/board/avaota-a1/init_dram/main.c b/board/avaota-a1/init_dram/main.c index 0363bc968..9362e5cfb 100644 --- a/board/avaota-a1/init_dram/main.c +++ b/board/avaota-a1/init_dram/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/link_bin.ld b/board/avaota-a1/link_bin.ld index 3fd4af27a..48c17b9ea 100644 --- a/board/avaota-a1/link_bin.ld +++ b/board/avaota-a1/link_bin.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) diff --git a/board/avaota-a1/link_elf.ld b/board/avaota-a1/link_elf.ld index 0a4c4d8a9..19d9baf16 100644 --- a/board/avaota-a1/link_elf.ld +++ b/board/avaota-a1/link_elf.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) diff --git a/board/avaota-a1/load_e906/CMakeLists.txt b/board/avaota-a1/load_e906/CMakeLists.txt index 88a169a26..6a91ae16b 100644 --- a/board/avaota-a1/load_e906/CMakeLists.txt +++ b/board/avaota-a1/load_e906/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(load_e906 main.c diff --git a/board/avaota-a1/load_e906/main.c b/board/avaota-a1/load_e906/main.c index 8d54f2e24..2e0bd07bc 100644 --- a/board/avaota-a1/load_e906/main.c +++ b/board/avaota-a1/load_e906/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/smhc2_test/CMakeLists.txt b/board/avaota-a1/smhc2_test/CMakeLists.txt index c6dccad31..f5b9d517d 100644 --- a/board/avaota-a1/smhc2_test/CMakeLists.txt +++ b/board/avaota-a1/smhc2_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(smhc2_test main.c diff --git a/board/avaota-a1/smhc2_test/main.c b/board/avaota-a1/smhc2_test/main.c index f7ed8ea92..e1cd13c09 100644 --- a/board/avaota-a1/smhc2_test/main.c +++ b/board/avaota-a1/smhc2_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -18,12 +18,13 @@ #include #include #include +#include #include #include #include #include -#define CONFIG_SDMMC_SPEED_TEST_SIZE 10240 +#define CONFIG_SDMMC_SPEED_TEST_SIZE 102400 * 4 extern sunxi_serial_t uart_dbg; @@ -39,12 +40,12 @@ int cmd_speedtest(int argc, const char **argv) { uint32_t start; uint32_t test_time; - // start = time_ms(); - // sdmmc_blk_write(&card0, (uint8_t *) (SDRAM_BASE), 0, CONFIG_SDMMC_SPEED_TEST_SIZE); - // test_time = time_ms() - start; - // printk_info("SDMMC: Write speedtest %uKB in %ums at %uKB/S\n", - // (CONFIG_SDMMC_SPEED_TEST_SIZE * 512) / 1024, test_time, - // (CONFIG_SDMMC_SPEED_TEST_SIZE * 512) / test_time); + start = time_ms(); + sdmmc_blk_write(&card0, (uint8_t *) (SDRAM_BASE), 0, CONFIG_SDMMC_SPEED_TEST_SIZE); + test_time = time_ms() - start; + printk_info("SDMMC: Write speedtest %uKB in %ums at %uKB/S\n", + (CONFIG_SDMMC_SPEED_TEST_SIZE * 512) / 1024, test_time, + (CONFIG_SDMMC_SPEED_TEST_SIZE * 512) / test_time); start = time_ms(); sdmmc_blk_read(&card0, (uint8_t *) (SDRAM_BASE), 0, CONFIG_SDMMC_SPEED_TEST_SIZE); @@ -72,19 +73,54 @@ const msh_command_entry commands[] = { int main(void) { sunxi_serial_init(&uart_dbg); + arm32_dcache_enable(); + arm32_icache_enable(); + show_banner(); + rtc_set_vccio_det_spare(); + sunxi_clk_init(); + set_rpio_power_mode(); + sunxi_clk_dump(); sunxi_i2c_init(&i2c_pmu); + pmu_axp2202_init(&i2c_pmu); + pmu_axp1530_init(&i2c_pmu); + pmu_axp2202_set_vol(&i2c_pmu, "dcdc1", 1100, 1); + + pmu_axp1530_set_dual_phase(&i2c_pmu); + pmu_axp1530_set_vol(&i2c_pmu, "dcdc1", 1100, 1); + pmu_axp1530_set_vol(&i2c_pmu, "dcdc2", 1100, 1); + + pmu_axp2202_set_vol(&i2c_pmu, "dcdc2", 920, 1); + pmu_axp2202_set_vol(&i2c_pmu, "dcdc3", 1160, 1); + pmu_axp2202_set_vol(&i2c_pmu, "dcdc4", 3300, 1); + + pmu_axp2202_set_vol(&i2c_pmu, "bldo3", 1800, 1); + pmu_axp2202_set_vol(&i2c_pmu, "bldo1", 1800, 1); + pmu_axp2202_set_vol(&i2c_pmu, "cldo1", 2100, 1); + + pmu_axp2202_dump(&i2c_pmu); + pmu_axp1530_dump(&i2c_pmu); + + sunxi_clk_set_cpu_pll(1416); + enable_sram_a3(); - printk_info("DRAM: DRAM Size = %dMB\n", sunxi_dram_init(&dram_para)); + /* Initialize the DRAM and enable memory management unit (MMU). */ + uint32_t dram_size = sunxi_dram_init((void *) dram_para); + + printk_debug("DRAM Size = %dM\n", dram_size); + + sunxi_clk_dump(); + + arm32_mmu_enable(SDRAM_BASE, dram_size); sunxi_clk_dump(); diff --git a/board/avaota-a1/smhc_test/CMakeLists.txt b/board/avaota-a1/smhc_test/CMakeLists.txt index 1ea20e493..9be87d6f0 100644 --- a/board/avaota-a1/smhc_test/CMakeLists.txt +++ b/board/avaota-a1/smhc_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(smhc_test main.c diff --git a/board/avaota-a1/smhc_test/main.c b/board/avaota-a1/smhc_test/main.c index 1ade7f504..31692827a 100644 --- a/board/avaota-a1/smhc_test/main.c +++ b/board/avaota-a1/smhc_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/spi_lcd/CMakeLists.txt b/board/avaota-a1/spi_lcd/CMakeLists.txt index 698ec3ef8..2d0c1a915 100644 --- a/board/avaota-a1/spi_lcd/CMakeLists.txt +++ b/board/avaota-a1/spi_lcd/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(spi_lcd main.c diff --git a/board/avaota-a1/spi_lcd/main.c b/board/avaota-a1/spi_lcd/main.c index c7ba93857..822ff33cf 100644 --- a/board/avaota-a1/spi_lcd/main.c +++ b/board/avaota-a1/spi_lcd/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/start.S b/board/avaota-a1/start.S index 32d178589..a61d07925 100644 --- a/board/avaota-a1/start.S +++ b/board/avaota-a1/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/avaota-a1/syter_boot/CMakeLists.txt b/board/avaota-a1/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/avaota-a1/syter_boot/CMakeLists.txt +++ b/board/avaota-a1/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/avaota-a1/syter_boot/main.c b/board/avaota-a1/syter_boot/main.c index 966f39213..f2052f35d 100644 --- a/board/avaota-a1/syter_boot/main.c +++ b/board/avaota-a1/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/syter_boot_bl33/CMakeLists.txt b/board/avaota-a1/syter_boot_bl33/CMakeLists.txt index 4c843473a..9721919d0 100644 --- a/board/avaota-a1/syter_boot_bl33/CMakeLists.txt +++ b/board/avaota-a1/syter_boot_bl33/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_bl33 main.c diff --git a/board/avaota-a1/syter_boot_bl33/main.c b/board/avaota-a1/syter_boot_bl33/main.c index ae217aa53..913f60ca7 100644 --- a/board/avaota-a1/syter_boot_bl33/main.c +++ b/board/avaota-a1/syter_boot_bl33/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-a1/syter_boot_uboot/CMakeLists.txt b/board/avaota-a1/syter_boot_uboot/CMakeLists.txt index 7f4b7afbb..745ef9dfc 100644 --- a/board/avaota-a1/syter_boot_uboot/CMakeLists.txt +++ b/board/avaota-a1/syter_boot_uboot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_uboot main.c diff --git a/board/avaota-a1/syter_boot_uboot/main.c b/board/avaota-a1/syter_boot_uboot/main.c index 1303da6c4..7225651e6 100644 --- a/board/avaota-a1/syter_boot_uboot/main.c +++ b/board/avaota-a1/syter_boot_uboot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/avaota-cam/board.c b/board/avaota-cam/board.c index 3b2e66246..109a07fb9 100644 --- a/board/avaota-cam/board.c +++ b/board/avaota-cam/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/avaota-cam/cdk/avaota_cam.cdkproj b/board/avaota-cam/cdk/avaota_cam.cdkproj index 6f6b65e93..fd43a16bd 100644 --- a/board/avaota-cam/cdk/avaota_cam.cdkproj +++ b/board/avaota-cam/cdk/avaota_cam.cdkproj @@ -374,6 +374,9 @@ + + + @@ -453,16 +456,16 @@ - + - + - + - + @@ -624,12 +627,12 @@ - CONFIG_CHIP_SUN20IW5;TRACE_MODE + CONFIG_CHIP_SUN20IW5;DEBUG_MODE None (-O0) Maximum (-g3) $(ProjectPath);../../../include/;../../../include/arch/riscv/;../../../include/cli/;../../../include/drivers/chips/sun20iw5/;../../../include/drivers/mmc/;../../../include/drivers/pmu/reg/;../../../include/drivers/pmu/;../../../include/drivers/reg/;../../../include/drivers/usb/;../../../include/image/;../../../include/lib/elf/;../../../include/lib/fatfs/;../../../include/lib/fdt/;../../../include/drivers/;../../../include/drivers/chips/;../../../include/drivers/mtd - -nostdlib -nostdinc -march=rv32imafcxthead -mabi=ilp32f -Wno-int-to-pointer-cast -Wno-int-to-pointer-cast -Wno-shift-count-overflow -Wno-builtin-declaration-mismatch -Wno-pointer-to-int-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers -Wno-unused-function -Wno-unused-variable -Wno-unused-but-set-variable + -nostdlib -nostdinc -march=rv32imafcxthead -mabi=ilp32f -Wno-int-to-pointer-cast -Wno-int-to-pointer-cast -Wno-shift-count-overflow -Wno-builtin-declaration-mismatch -Wno-pointer-to-int-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers -Wno-unused-function -Wno-unused-variable -Wno-unused-but-set-variable -Wno-parentheses no no no @@ -744,13 +747,13 @@ - ;;; + 0x20181C8;;; ;;32;;MHZ;;up 1 1 - 100:8;100:8;100:8;100:8; + 100:4;100:8;100:8;100:8; 1 diff --git a/board/avaota-cam/cdk/config.h b/board/avaota-cam/cdk/config.h index 8d3053ca8..a53a0d5c7 100644 --- a/board/avaota-cam/cdk/config.h +++ b/board/avaota-cam/cdk/config.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CONFIG_H_ #define _CONFIG_H_ diff --git a/board/avaota-cam/cdk/link_elf.ld b/board/avaota-cam/cdk/link_elf.ld index 246f8a234..714fd70aa 100644 --- a/board/avaota-cam/cdk/link_elf.ld +++ b/board/avaota-cam/cdk/link_elf.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") OUTPUT_ARCH("riscv") diff --git a/board/avaota-cam/eabi_compat.c b/board/avaota-cam/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/avaota-cam/eabi_compat.c +++ b/board/avaota-cam/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/avaota-cam/head.c b/board/avaota-cam/head.c index 010bdda54..f95e844fc 100644 --- a/board/avaota-cam/head.c +++ b/board/avaota-cam/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/avaota-cam/hello_world/CMakeLists.txt b/board/avaota-cam/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/avaota-cam/hello_world/CMakeLists.txt +++ b/board/avaota-cam/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/avaota-cam/hello_world/main.c b/board/avaota-cam/hello_world/main.c index 9295747a5..9cd2c842c 100644 --- a/board/avaota-cam/hello_world/main.c +++ b/board/avaota-cam/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -95,10 +95,19 @@ int cmd_load(int argc, const char **argv) { return 0; } -msh_declare_command(dump); -msh_define_help(dump, "test", "Usage: dump\n"); -int cmd_dump(int argc, const char **argv) { - uart_printf("%s\n", (void *) (0x2020C00)); +msh_declare_command(reset); +msh_define_help(reset, "reset test", "Usage: reset\n"); +int cmd_reset(int argc, const char **argv) { + setbits_le32(SUNXI_PRCM_BASE + 0x1c, BIT(3)); /* enable WDT clk */ + writel(0x16aa0000, SUNXI_RTC_WDG_BASE + 0x18); /* disable WDT */ + writel(0x16aa0000 | BIT(0), SUNXI_RTC_WDG_BASE + 0x08); /* trigger WDT */ + return 0; +} + +msh_declare_command(bt); +msh_define_help(bt, "backtrace test", "Usage: bt\n"); +int cmd_bt(int argc, const char **argv) { + dump_stack(); return 0; } @@ -106,7 +115,8 @@ const msh_command_entry commands[] = { msh_define_command(load), msh_define_command(read), msh_define_command(write), - msh_define_command(dump), + msh_define_command(bt), + msh_define_command(reset), msh_command_end, }; @@ -117,7 +127,7 @@ int main(void) { sunxi_serial_init(&uart_card); - show_banner(); + //show_banner(); printk_info("Hello World!\n"); @@ -129,10 +139,6 @@ int main(void) { uint32_t dram_size = sunxi_dram_init(&dram_para); - printk_info("DRAM Size = %u\n", dram_size); - - printk_info("peri1x = %u\n", sunxi_clk_get_peri1x_rate()); - sunxi_spi_init(&sunxi_spi0); spi_nor_detect(&sunxi_spi0); diff --git a/board/avaota-cam/start.S b/board/avaota-cam/start.S index ae280dd9d..209bfd3d7 100644 --- a/board/avaota-cam/start.S +++ b/board/avaota-cam/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -48,9 +48,17 @@ _start: csrs mstatus, t0 /* enable MXSTATUS.THEADISAEE bit[22] */ - li t0, MSTATUS_TSR + li t0, MXSTATUS_THEADISAEE csrs mxstatus, t0 + /* enable MHCR IE, DE, WB, WA, RS, BPE, BTE */ + li t0, MHCR_IE | MHCR_DE | MHCR_WB | MHCR_WA | MHCR_RS | MHCR_BPE | MHCR_BTE + csrs mhcr, t0 + + /* enable MHINT D_PLD, IWPE, AMR_1, PREF_N_16 */ + li t0, MHINT_D_PLD | MHINT_IWPE | MHINT_AMR_1 | MHINT_PREF_N_16 + csrs mhint, t0 + /* invaild ICACHE/DCACHE/BTB/BHT */ fence.i diff --git a/board/avaota-nas/CMakeLists.txt b/board/avaota-nas/CMakeLists.txt new file mode 100644 index 000000000..6c25abcf0 --- /dev/null +++ b/board/avaota-nas/CMakeLists.txt @@ -0,0 +1,9 @@ +set(APP_COMMON_SOURCE + ${CMAKE_CURRENT_SOURCE_DIR}/start.S + ${CMAKE_CURRENT_SOURCE_DIR}/board.c + ${CMAKE_CURRENT_SOURCE_DIR}/eabi_compat.c + # ${CMAKE_CURRENT_SOURCE_DIR}/payloads/init_dram_bin.c + ${CMAKE_CURRENT_SOURCE_DIR}/head.c +) + +add_subdirectory(hello_world) diff --git a/src/arch/riscv/riscv64_ae350/cache.c b/board/avaota-nas/README.md similarity index 100% rename from src/arch/riscv/riscv64_ae350/cache.c rename to board/avaota-nas/README.md diff --git a/board/avaota-nas/board.c b/board/avaota-nas/board.c new file mode 100644 index 000000000..18fc19179 --- /dev/null +++ b/board/avaota-nas/board.c @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +sunxi_serial_t uart_dbg = { + .base = SUNXI_UART0_BASE, + .id = 0, + .baud_rate = UART_BAUDRATE_115200, + .dlen = UART_DLEN_8, + .stop = UART_STOP_BIT_0, + .parity = UART_PARITY_NO, + .gpio_pin = { + .gpio_tx = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX3}, + .gpio_rx = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX3}, + }, + .uart_clk = { + .gate_reg_base = SUNXI_CCU_BASE + UART0_BGR_REG, + .gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET(0), + .rst_reg_base = SUNXI_CCU_BASE + UART0_BGR_REG, + .rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET(0), + .parent_clk = SERIAL_DEFAULT_PARENT_CLK, + }, +}; + +sunxi_i2c_t i2c_pmu = { + .base = SUNXI_RTWI_BASE, + .id = SUNXI_R_I2C0, + .speed = SUNXI_I2C_SPEED_400K, + .gpio = { + .gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX2}, + .gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX2}, + }, + .i2c_clk = { + .gate_reg_base = SUNXI_RTWI_BRG_REG, + .gate_reg_offset = TWI_DEFAULT_CLK_GATE_OFFSET(0), + .rst_reg_base = SUNXI_RTWI_BRG_REG, + .rst_reg_offset = TWI_DEFAULT_CLK_RST_OFFSET(0), + .parent_clk = 24000000, + }, +}; + +sunxi_sdhci_t sdhci0 = { + .name = "sdhci0", + .id = MMC_CONTROLLER_0, + .reg_base = SUNXI_SMHC0_BASE, + .sdhci_mmc_type = MMC_TYPE_SD, + .max_clk = 50000000, + .width = SMHC_WIDTH_4BIT, + .dma_des_addr = SDRAM_BASE + 0x30080000, + .pinctrl = { + //.gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2}, + .gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2}, + .gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2}, + .gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2}, + .gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2}, + //.gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2}, + .gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT}, + .cd_level = GPIO_LEVEL_LOW, + }, + .clk_ctrl = { + .gate_reg_base = SUNXI_CCU_BASE + SMHC0_BGR_REG, + .gate_reg_offset = SDHCI_DEFAULT_CLK_GATE_OFFSET(0), + .rst_reg_base = SUNXI_CCU_BASE + SMHC0_BGR_REG, + .rst_reg_offset = SDHCI_DEFAULT_CLK_RST_OFFSET(0), + }, + .sdhci_clk = { + .reg_base = SUNXI_CCU_BASE + SMHC0_CLK_REG, + .reg_factor_n_offset = SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET, + .reg_factor_m_offset = SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET, + .clk_sel = 0x1, + .parent_clk = 300000000, + }, +}; + +void neon_enable(void) { + /* Set the CPACR for access to CP10 and CP11*/ + asm volatile("LDR r0, =0xF00000"); + asm volatile("MCR p15, 0, r0, c1, c0, 2"); + /* Set the FPEXC EN bit to enable the FPU */ + asm volatile("MOV r3, #0x40000000"); + /*@VMSR FPEXC, r3*/ + asm volatile("MCR p10, 7, r3, c8, c0, 0"); +} + +void clean_syterkit_data(void) { + /* Disable MMU, data cache, instruction cache, interrupts */ + arm32_mmu_disable(); + printk_info("disable mmu ok...\n"); + arm32_dcache_disable(); + printk_info("disable dcache ok...\n"); + arm32_icache_disable(); + printk_info("disable icache ok...\n"); + arm32_interrupt_disable(); + printk_info("free interrupt ok...\n"); +} + +void show_chip() { + uint32_t chip_sid[4]; + chip_sid[0] = read32(SUNXI_SID_SRAM_BASE + 0x0); + chip_sid[1] = read32(SUNXI_SID_SRAM_BASE + 0x4); + chip_sid[2] = read32(SUNXI_SID_SRAM_BASE + 0x8); + chip_sid[3] = read32(SUNXI_SID_SRAM_BASE + 0xc); + + printk_info("Chip SID = %08x%08x%08x%08x\n", chip_sid[0], chip_sid[1], chip_sid[2], chip_sid[3]); + + uint32_t chip_markid_sid = chip_sid[0] & 0xffff; + + switch (chip_markid_sid) { + case 0x5f00: + printk_info("Chip type = A733MX-N3X"); + break; + default: + printk_info("Chip type = UNKNOW"); + break; + } + + setbits_le32(SUNXI_SYSCTRL_BASE + 0x24, BIT(15)); + uint32_t version = (read32(SUNXI_SYSCTRL_BASE + 0x24) & 0xFFFF0007) >> 16; + printk(LOG_LEVEL_MUTE, " Chip Version = 0x%04x \n", version); +} \ No newline at end of file diff --git a/board/avaota-nas/eabi_compat.c b/board/avaota-nas/eabi_compat.c new file mode 100644 index 000000000..efa4d10e3 --- /dev/null +++ b/board/avaota-nas/eabi_compat.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +void abort(void) { + while (1) + ; +} + +int raise(int signum) { + return 0; +} + +/* Dummy function to avoid linker complaints */ +void __aeabi_unwind_cpp_pr0(void) { +} \ No newline at end of file diff --git a/board/avaota-nas/head.c b/board/avaota-nas/head.c new file mode 100644 index 000000000..d4d47332c --- /dev/null +++ b/board/avaota-nas/head.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include + +typedef struct boot_file_head { + uint32_t jump_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" */ + uint32_t check_sum; /* generated by PC */ + uint32_t *length; /* generated by LD */ + uint32_t pub_head_size; /* the size of boot_file_head_t */ + uint8_t pub_head_vsn[4]; /* the version of boot_file_head_t */ + uint32_t *ret_addr; /* the return value */ + uint32_t *run_addr; /* run addr */ + uint32_t boot_cpu; /* eGON version */ + uint8_t platform[8]; /* platform information */ +} boot_file_head_t; + +#define BROM_FILE_HEAD_SIZE_OFFSET (((sizeof(boot_file_head_t) + sizeof(int)) / sizeof(int) + 1)) +#define JUMP_INSTRUCTION (BROM_FILE_HEAD_SIZE_OFFSET | 0xEA000000) + +#define BOOT0_MAGIC "eGON.BT0" +#define STAMP_VALUE (0x12345678) +#define BOOT_PUB_HEAD_VERSION "3000" + +extern uint32_t __spl_size[]; +extern uint32_t __code_start_address[]; + +const __attribute__((section(".boot0_head"))) boot_file_head_t boot_head = { + .jump_instruction = JUMP_INSTRUCTION, + .magic = BOOT0_MAGIC, + .check_sum = STAMP_VALUE, + .length = __spl_size, + .pub_head_size = sizeof(boot_file_head_t), + .pub_head_vsn = BOOT_PUB_HEAD_VERSION, + .ret_addr = __code_start_address, + .run_addr = __code_start_address, + .boot_cpu = 0, + .platform = {0, 0, '3', '.', '0', '.', '0', 0}, +}; \ No newline at end of file diff --git a/board/avaota-nas/hello_world/CMakeLists.txt b/board/avaota-nas/hello_world/CMakeLists.txt new file mode 100644 index 000000000..4b10765c7 --- /dev/null +++ b/board/avaota-nas/hello_world/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +add_syterkit_app(helloworld + main.c +) \ No newline at end of file diff --git a/board/avaota-nas/hello_world/main.c b/board/avaota-nas/hello_world/main.c new file mode 100644 index 000000000..3534a22f8 --- /dev/null +++ b/board/avaota-nas/hello_world/main.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include + +#include + +#include + +#include + +#include +#include +#include + +extern sunxi_serial_t uart_dbg; + +extern sunxi_i2c_t i2c_pmu; + +extern sunxi_sdhci_t sdhci0; + +int main(void) { + sunxi_serial_init(&uart_dbg); + + show_banner(); + + sunxi_i2c_init(&i2c_pmu); + + sunxi_clk_init(); + + sunxi_clk_dump(); + + pmu_axp8191_init(&i2c_pmu); + + pmu_axp8191_dump(&i2c_pmu); + + printk_info("Hello World!\n"); + + abort(); + + return 0; +} \ No newline at end of file diff --git a/board/avaota-nas/payloads/init_dram_bin.c b/board/avaota-nas/payloads/init_dram_bin.c new file mode 100644 index 000000000..f476fefdf --- /dev/null +++ b/board/avaota-nas/payloads/init_dram_bin.c @@ -0,0 +1,12349 @@ +const unsigned char __attribute__((section(".init_dram_bin"))) init_dram_bin[197502] = { + 0xFF, 0xFF, 0xFF, 0xEA, 0x00, 0x40, 0x2D, 0xE9, 0x05, 0x00, 0x00, 0xEB, 0x10, 0x0F, 0x11, 0xEE, + 0x01, 0x0A, 0x80, 0xE3, 0x10, 0x0F, 0x01, 0xEE, 0x16, 0x01, 0x00, 0xFA, 0x00, 0x40, 0xBD, 0xE8, + 0x0E, 0xF0, 0xA0, 0xE1, 0x18, 0x00, 0x9F, 0xE5, 0x18, 0x10, 0x9F, 0xE5, 0x00, 0x20, 0xA0, 0xE3, + 0x00, 0x20, 0x80, 0xE5, 0x04, 0x00, 0x80, 0xE2, 0x01, 0x00, 0x50, 0xE1, 0xFB, 0xFF, 0xFF, 0x1A, + 0x0E, 0xF0, 0xA0, 0xE1, 0x80, 0x03, 0x2B, 0x07, 0xA4, 0x03, 0x2B, 0x07, 0x01, 0x00, 0x50, 0xE1, + 0x0E, 0xF0, 0xA0, 0x01, 0x11, 0x40, 0x2D, 0xE9, 0x04, 0x20, 0x52, 0xE2, 0x29, 0x00, 0x00, 0xBA, + 0x03, 0xC0, 0x10, 0xE2, 0x30, 0x00, 0x00, 0x1A, 0x03, 0xC0, 0x11, 0xE2, 0x3A, 0x00, 0x00, 0x1A, + 0x1C, 0x20, 0x52, 0xE2, 0xE0, 0x01, 0x2D, 0xE9, 0x0A, 0x00, 0x00, 0xBA, 0x1F, 0xC0, 0x10, 0xE2, + 0x20, 0x30, 0x6C, 0xE2, 0x02, 0x40, 0xD3, 0x10, 0x02, 0x00, 0x00, 0x2A, 0x24, 0x40, 0x8F, 0xE2, + 0x03, 0x20, 0x52, 0xE0, 0x0C, 0xF0, 0x84, 0xE0, 0xF8, 0x51, 0xB1, 0xE8, 0x20, 0x20, 0x52, 0xE2, + 0xF8, 0x51, 0xA0, 0xE8, 0xFB, 0xFF, 0xFF, 0xAA, 0x1C, 0xC0, 0x12, 0xE2, 0x20, 0xC0, 0x6C, 0xE2, + 0x0C, 0xF0, 0x8F, 0x10, 0x12, 0x00, 0x00, 0xEA, 0x00, 0xF0, 0x20, 0xE3, 0x04, 0x30, 0x91, 0xE4, + 0x04, 0x40, 0x91, 0xE4, 0x04, 0x50, 0x91, 0xE4, 0x04, 0x60, 0x91, 0xE4, 0x04, 0x70, 0x91, 0xE4, + 0x04, 0x80, 0x91, 0xE4, 0x04, 0xE0, 0x91, 0xE4, 0x0C, 0xF0, 0x8F, 0xE0, 0x00, 0xF0, 0x20, 0xE3, + 0x00, 0xF0, 0x20, 0xE3, 0x04, 0x30, 0x80, 0xE4, 0x04, 0x40, 0x80, 0xE4, 0x04, 0x50, 0x80, 0xE4, + 0x04, 0x60, 0x80, 0xE4, 0x04, 0x70, 0x80, 0xE4, 0x04, 0x80, 0x80, 0xE4, 0x04, 0xE0, 0x80, 0xE4, + 0xE4, 0xFF, 0xFF, 0x2A, 0xE0, 0x01, 0xBD, 0xE8, 0x82, 0x2F, 0xB0, 0xE1, 0x01, 0x30, 0xD1, 0x14, + 0x01, 0x40, 0xD1, 0x24, 0x01, 0xC0, 0xD1, 0x24, 0x01, 0x30, 0xC0, 0x14, 0x01, 0x40, 0xC0, 0x24, + 0x01, 0xC0, 0xC0, 0x24, 0x11, 0x40, 0xBD, 0xE8, 0x3E, 0xFF, 0x2F, 0xE1, 0x04, 0xC0, 0x6C, 0xE2, + 0x02, 0x00, 0x5C, 0xE3, 0x01, 0x30, 0xD1, 0xC4, 0x01, 0x40, 0xD1, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x00, 0x00, 0x01, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x97, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x08, 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xC0, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +unsigned long long init_dram_bin_length = 197502; + \ No newline at end of file diff --git a/board/avaota-nas/start.S b/board/avaota-nas/start.S new file mode 100644 index 000000000..c06fb9c14 --- /dev/null +++ b/board/avaota-nas/start.S @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include + +// Macro to save register values onto the stack +.macro save_regs + str lr, [sp, #-4] // Save value of lr register onto the stack + mrs lr, spsr_all // Save value of spsr_all register onto lr register + str lr, [sp, #-8] // Save value of lr register onto the stack + str r1, [sp, #-12] // Save value of r1 register onto the stack + str r0, [sp, #-16] // Save value of r0 register onto the stack + mov r0, sp // Copy value of sp register to r0 register + cps #0x13 // Switch to SVC mode + ldr r1, [r0, #-4] // Load value of r1 register from stack to r1 register + str r1, [sp, #-4]! // Save value of r1 register onto the stack and update stack pointer + ldr r1, [r0, #-8] // Load value of r1 register from stack to r1 register + str r1, [sp, #-(4 * 16)] // Save value of r1 register onto the stack + ldr r1, [r0, #-12] // Load value of r1 register from stack to r1 register + ldr r0, [r0, #-16] // Load value of r0 register from stack to r0 register + stmdb sp, {r0 - r14}^ // Save values of registers r0-r14 onto the stack + sub sp, sp, #(4 * 16) // Update stack pointer + ldr r4, [sp] // Load value of r4 register from stack to r4 register + and r0, r4, #0x1f // Copy the lower 5 bits of r4 register to r0 register + cmp r0, #0x10 // Compare value of r0 register with 0x10 + beq 10f // If equal, jump to label 10 + cmp r0, #0x13 // Compare value of r0 register with 0x13 + beq 11f // If equal, jump to label 11 + b . // Jump to current location +11: add r1, sp, #(4 * 17) // Add (4 * 17) to sp register and copy result to r1 register + str r1, [sp, #(4 * 14)] // Save value of r1 register onto the stack + str lr, [sp, #(4 * 15)] // Save value of lr register onto the stack +10: add r1, sp, #(4 * 17) // Add (4 * 17) to sp register and copy result to r1 register + str r1, [sp, #-4]! // Save value of r1 register onto the stack and update stack pointer + mov r0, sp // Copy value of sp register to r0 register +.endm + +// Macro to restore register values from the stack +.macro restore_regs + mov r12, sp // Copy value of sp register to r12 register + ldr sp, [r12], #4 // Load value from memory pointed by r12 register to sp register and update r12 register + ldr r1, [r12], #4 // Load value from memory pointed by r12 register to r1 register and update r12 register + msr spsr_cxsf, r1 // Write value of r1 register to spsr_cxsf register + and r0, r1, #0x1f // Copy the lower 5 bits of r1 register to r0 register + cmp r0, #0x10 // Compare value of r0 register with 0x10 + beq 20f // If equal, jump to label 20 + cmp r0, #0x13 // Compare value of r0 register with 0x13 + beq 21f // If equal, jump to label 21 + b . // Jump to current location +20: ldr lr, [r12, #(4 * 15)] // Load value from memory pointed by r12 register to lr register + ldmia r12, {r0 - r14}^ // Load values of registers r0-r14 from memory pointed by r12 register and update r12 register + movs pc, lr // Set value of PC register to value of lr register +21: ldm r12, {r0 - r15}^ // Load values of registers r0-r15 from memory pointed by r12 register + mov r0, r0 // Copy value of r0 register to r0 register +.endm + +.arm +.globl _start +.text + +_start: + b reset + + .align 5 +_vector: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + +reset: + /* Enter svc mode cleanly and mask interrupts */ + mrs r0, cpsr + bic r0, r0, #ARMV7_MODE_MASK + orr r0, r0, #ARMV7_SVC_MODE + orr r0, r0, #(ARMV7_IRQ_MASK | ARMV7_FIQ_MASK) + bic r0, r0, #(1<<9) @set little-endian + msr cpsr_c, r0 + + /* Set vector base address register */ + ldr r0, =_vector + mcr p15, 0, r0, c12, c0, 0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1 << 13) + mcr p15, 0, r0, c1, c0, 0 + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB + bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache + mcr p15, 0, r0, c1, c0, 0 + + /* Set stack pointer */ + /* Initialize UND stacks */ + mrs r0, cpsr + bic r0, r0, #ARMV7_MODE_MASK + orr r1, r0, #ARMV7_UND_MODE + msr cpsr_cxsf, r1 + ldr sp, _stack_und_end + + /* Initialize ABT stacks */ + mrs r0, cpsr + bic r0, r0, #ARMV7_MODE_MASK + orr r1, r0, #ARMV7_ABT_MODE + msr cpsr_cxsf, r1 + ldr sp, _stack_abt_end + + /* Initialize IRQ stacks */ + mrs r0, cpsr + bic r0, r0, #ARMV7_MODE_MASK + orr r1, r0, #ARMV7_IRQ_MODE + msr cpsr_cxsf, r1 + ldr sp, _stack_irq_end + + /* Initialize FIQ stacks */ + mrs r0, cpsr + bic r0, r0, #ARMV7_MODE_MASK + orr r1, r0, #ARMV7_FIQ_MODE + msr cpsr_cxsf, r1 + ldr sp, _stack_fiq_end + + /* Initialize SVC stacks */ + mrs r0, cpsr + bic r0, r0, #ARMV7_MODE_MASK + orr r1, r0, #ARMV7_SVC_MODE + msr cpsr_cxsf, r1 + ldr sp, _stack_srv_end + + bl clear_bss + + bl neon_enable + + /* + * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, + * except if in HYP mode already + */ + mrs r0, cpsr + and r1, r0, #ARMV7_MODE_MASK @ mask mode bits + teq r1, #0x1a @ test for HYP mode + bicne r0, r0, #ARMV7_MODE_MASK @ clear all mode bits + orrne r0, r0, #ARMV7_SVC_MODE @ set SVC mode + orr r0, r0, #0xc0 @ disable FIQ and IRQ + msr cpsr,r0 + + bl set_timer_count + + bl main + +clear_bss: + ldr r0, =_sbss + ldr r1, =_ebss + mov r2, #0 + +clbss_1: + stmia r0!, {r2} + cmp r0, r1 + blt clbss_1 + + mov pc, lr + + /* + * Exception handlers + */ + .align 5 +undefined_instruction: + sub lr, lr, #4 + save_regs + bl arm32_do_undefined_instruction + restore_regs + + .align 5 +software_interrupt: + sub lr, lr, #4 + save_regs + bl arm32_do_software_interrupt + restore_regs + + .align 5 +prefetch_abort: + sub lr, lr, #4 + save_regs + bl arm32_do_prefetch_abort + restore_regs + + .align 5 +data_abort: + sub lr, lr, #8 + save_regs + bl arm32_do_data_abort + restore_regs + + .align 5 +not_used: + b . + + .align 5 +irq: + sub lr, lr, #4 + save_regs + bl arm32_do_irq + restore_regs + + .align 5 +fiq: + sub lr, lr, #4 + save_regs + bl arm32_do_fiq + restore_regs + + /* + * The location of section + */ + .align 4 +_stack_und_end: + .long __stack_und_end +_stack_abt_end: + .long __stack_abt_end +_stack_irq_end: + .long __stack_irq_end +_stack_fiq_end: + .long __stack_fiq_end +_stack_srv_end: + .long __stack_srv_end \ No newline at end of file diff --git a/board/dongshanpi-aict/board.c b/board/dongshanpi-aict/board.c index b1686e0d4..d29932342 100644 --- a/board/dongshanpi-aict/board.c +++ b/board/dongshanpi-aict/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/dongshanpi-aict/eabi_compat.c b/board/dongshanpi-aict/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/dongshanpi-aict/eabi_compat.c +++ b/board/dongshanpi-aict/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/dongshanpi-aict/head.c b/board/dongshanpi-aict/head.c index 05d101a78..d4d47332c 100644 --- a/board/dongshanpi-aict/head.c +++ b/board/dongshanpi-aict/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/dongshanpi-aict/hello_world/CMakeLists.txt b/board/dongshanpi-aict/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/dongshanpi-aict/hello_world/CMakeLists.txt +++ b/board/dongshanpi-aict/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/dongshanpi-aict/hello_world/main.c b/board/dongshanpi-aict/hello_world/main.c index 726d614a9..70c93f708 100644 --- a/board/dongshanpi-aict/hello_world/main.c +++ b/board/dongshanpi-aict/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/dongshanpi-aict/start.S b/board/dongshanpi-aict/start.S index 179f110e9..d227c0c00 100644 --- a/board/dongshanpi-aict/start.S +++ b/board/dongshanpi-aict/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/dongshanpi-aict/syter_boot/CMakeLists.txt b/board/dongshanpi-aict/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/dongshanpi-aict/syter_boot/CMakeLists.txt +++ b/board/dongshanpi-aict/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/dongshanpi-aict/syter_boot/main.c b/board/dongshanpi-aict/syter_boot/main.c index 65de84954..1a452fc52 100644 --- a/board/dongshanpi-aict/syter_boot/main.c +++ b/board/dongshanpi-aict/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/dongshanpi-aict/syter_boot_spi/CMakeLists.txt b/board/dongshanpi-aict/syter_boot_spi/CMakeLists.txt index 7ea44abdc..b6fbda74d 100644 --- a/board/dongshanpi-aict/syter_boot_spi/CMakeLists.txt +++ b/board/dongshanpi-aict/syter_boot_spi/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_spi main.c diff --git a/board/dongshanpi-aict/syter_boot_spi/main.c b/board/dongshanpi-aict/syter_boot_spi/main.c index 0ab434430..2c6c8e56a 100644 --- a/board/dongshanpi-aict/syter_boot_spi/main.c +++ b/board/dongshanpi-aict/syter_boot_spi/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-3h/board.c b/board/longanpi-3h/board.c index a3d714429..2bf0c408b 100644 --- a/board/longanpi-3h/board.c +++ b/board/longanpi-3h/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/longanpi-3h/cli_test/CMakeLists.txt b/board/longanpi-3h/cli_test/CMakeLists.txt index e2505e8ec..137e7a122 100644 --- a/board/longanpi-3h/cli_test/CMakeLists.txt +++ b/board/longanpi-3h/cli_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(cli_test main.c diff --git a/board/longanpi-3h/cli_test/main.c b/board/longanpi-3h/cli_test/main.c index 7ee88e1a6..a8b2c9019 100644 --- a/board/longanpi-3h/cli_test/main.c +++ b/board/longanpi-3h/cli_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-3h/eabi_compat.c b/board/longanpi-3h/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/longanpi-3h/eabi_compat.c +++ b/board/longanpi-3h/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/longanpi-3h/head.c b/board/longanpi-3h/head.c index 05d101a78..d4d47332c 100644 --- a/board/longanpi-3h/head.c +++ b/board/longanpi-3h/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/longanpi-3h/hello_world/CMakeLists.txt b/board/longanpi-3h/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/longanpi-3h/hello_world/CMakeLists.txt +++ b/board/longanpi-3h/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/longanpi-3h/hello_world/main.c b/board/longanpi-3h/hello_world/main.c index a3ff9e8f1..f857e9de4 100644 --- a/board/longanpi-3h/hello_world/main.c +++ b/board/longanpi-3h/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-3h/init_dram/CMakeLists.txt b/board/longanpi-3h/init_dram/CMakeLists.txt index cc4627c58..8d9c9c1c1 100644 --- a/board/longanpi-3h/init_dram/CMakeLists.txt +++ b/board/longanpi-3h/init_dram/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(init_dram main.c diff --git a/board/longanpi-3h/init_dram/main.c b/board/longanpi-3h/init_dram/main.c index 5cb1e7800..90b632f3f 100644 --- a/board/longanpi-3h/init_dram/main.c +++ b/board/longanpi-3h/init_dram/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-3h/load_bl31/CMakeLists.txt b/board/longanpi-3h/load_bl31/CMakeLists.txt index 021faa788..aba654650 100644 --- a/board/longanpi-3h/load_bl31/CMakeLists.txt +++ b/board/longanpi-3h/load_bl31/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(load_bl31 main.c diff --git a/board/longanpi-3h/load_bl31/main.c b/board/longanpi-3h/load_bl31/main.c index 98375bf40..1a2cf9f43 100644 --- a/board/longanpi-3h/load_bl31/main.c +++ b/board/longanpi-3h/load_bl31/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-3h/smhc_test/CMakeLists.txt b/board/longanpi-3h/smhc_test/CMakeLists.txt index 1ea20e493..9be87d6f0 100644 --- a/board/longanpi-3h/smhc_test/CMakeLists.txt +++ b/board/longanpi-3h/smhc_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(smhc_test main.c diff --git a/board/longanpi-3h/smhc_test/main.c b/board/longanpi-3h/smhc_test/main.c index ddf3ed1ef..dde8b43d7 100644 --- a/board/longanpi-3h/smhc_test/main.c +++ b/board/longanpi-3h/smhc_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-3h/start.S b/board/longanpi-3h/start.S index 529e63636..11e4fdfd3 100644 --- a/board/longanpi-3h/start.S +++ b/board/longanpi-3h/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/longanpi-3h/syter_boot/CMakeLists.txt b/board/longanpi-3h/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/longanpi-3h/syter_boot/CMakeLists.txt +++ b/board/longanpi-3h/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/longanpi-3h/syter_boot/main.c b/board/longanpi-3h/syter_boot/main.c index 1e5d982d6..2a474055b 100644 --- a/board/longanpi-3h/syter_boot/main.c +++ b/board/longanpi-3h/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-3h/tinymaix/CMakeLists.txt b/board/longanpi-3h/tinymaix/CMakeLists.txt index df0218494..acfa70846 100644 --- a/board/longanpi-3h/tinymaix/CMakeLists.txt +++ b/board/longanpi-3h/tinymaix/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(tinymaix main.c diff --git a/board/longanpi-3h/tinymaix/main.c b/board/longanpi-3h/tinymaix/main.c index 783d508f5..02a530af0 100644 --- a/board/longanpi-3h/tinymaix/main.c +++ b/board/longanpi-3h/tinymaix/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-4b/board.c b/board/longanpi-4b/board.c index 8694f16eb..7b00a1d11 100644 --- a/board/longanpi-4b/board.c +++ b/board/longanpi-4b/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/longanpi-4b/eabi_compat.c b/board/longanpi-4b/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/longanpi-4b/eabi_compat.c +++ b/board/longanpi-4b/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/longanpi-4b/extlinux_boot/CMakeLists.txt b/board/longanpi-4b/extlinux_boot/CMakeLists.txt index 4127a920e..76896b188 100644 --- a/board/longanpi-4b/extlinux_boot/CMakeLists.txt +++ b/board/longanpi-4b/extlinux_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(extlinux_boot main.c diff --git a/board/longanpi-4b/extlinux_boot/fdt.c b/board/longanpi-4b/extlinux_boot/fdt.c index 57f70831c..93eb8ed74 100644 --- a/board/longanpi-4b/extlinux_boot/fdt.c +++ b/board/longanpi-4b/extlinux_boot/fdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifdef SYTERKIT_CLI_CMD_FDT msh_declare_command(fdt); diff --git a/board/longanpi-4b/extlinux_boot/main.c b/board/longanpi-4b/extlinux_boot/main.c index c06f920a9..ca5cc6a80 100644 --- a/board/longanpi-4b/extlinux_boot/main.c +++ b/board/longanpi-4b/extlinux_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-4b/head.c b/board/longanpi-4b/head.c index 05d101a78..d4d47332c 100644 --- a/board/longanpi-4b/head.c +++ b/board/longanpi-4b/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/longanpi-4b/hello_world/CMakeLists.txt b/board/longanpi-4b/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/longanpi-4b/hello_world/CMakeLists.txt +++ b/board/longanpi-4b/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/longanpi-4b/hello_world/main.c b/board/longanpi-4b/hello_world/main.c index a3ff9e8f1..f857e9de4 100644 --- a/board/longanpi-4b/hello_world/main.c +++ b/board/longanpi-4b/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/longanpi-4b/start.S b/board/longanpi-4b/start.S index 699af2177..4ff92a712 100644 --- a/board/longanpi-4b/start.S +++ b/board/longanpi-4b/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/lt527x/board.c b/board/lt527x/board.c index 6451c2bec..1661bfa19 100644 --- a/board/lt527x/board.c +++ b/board/lt527x/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/lt527x/eabi_compat.c b/board/lt527x/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/lt527x/eabi_compat.c +++ b/board/lt527x/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/lt527x/head.c b/board/lt527x/head.c index 05d101a78..d4d47332c 100644 --- a/board/lt527x/head.c +++ b/board/lt527x/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/lt527x/hello_world/CMakeLists.txt b/board/lt527x/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/lt527x/hello_world/CMakeLists.txt +++ b/board/lt527x/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/lt527x/hello_world/main.c b/board/lt527x/hello_world/main.c index a3ff9e8f1..f857e9de4 100644 --- a/board/lt527x/hello_world/main.c +++ b/board/lt527x/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/lt527x/link_bin.ld b/board/lt527x/link_bin.ld index 3fd4af27a..48c17b9ea 100644 --- a/board/lt527x/link_bin.ld +++ b/board/lt527x/link_bin.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) diff --git a/board/lt527x/link_elf.ld b/board/lt527x/link_elf.ld index 0a4c4d8a9..19d9baf16 100644 --- a/board/lt527x/link_elf.ld +++ b/board/lt527x/link_elf.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) diff --git a/board/lt527x/start.S b/board/lt527x/start.S index 003b786c7..96cc92352 100644 --- a/board/lt527x/start.S +++ b/board/lt527x/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/project-yosemite/board.c b/board/project-yosemite/board.c index 58f0096f0..9f21a4f9e 100644 --- a/board/project-yosemite/board.c +++ b/board/project-yosemite/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/project-yosemite/eabi_compat.c b/board/project-yosemite/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/project-yosemite/eabi_compat.c +++ b/board/project-yosemite/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/project-yosemite/head.c b/board/project-yosemite/head.c index 05d101a78..d4d47332c 100644 --- a/board/project-yosemite/head.c +++ b/board/project-yosemite/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/project-yosemite/hello_world/CMakeLists.txt b/board/project-yosemite/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/project-yosemite/hello_world/CMakeLists.txt +++ b/board/project-yosemite/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/project-yosemite/hello_world/main.c b/board/project-yosemite/hello_world/main.c index 726d614a9..70c93f708 100644 --- a/board/project-yosemite/hello_world/main.c +++ b/board/project-yosemite/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/project-yosemite/start.S b/board/project-yosemite/start.S index 179f110e9..d227c0c00 100644 --- a/board/project-yosemite/start.S +++ b/board/project-yosemite/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/project-yosemite/syter_boot/CMakeLists.txt b/board/project-yosemite/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/project-yosemite/syter_boot/CMakeLists.txt +++ b/board/project-yosemite/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/project-yosemite/syter_boot/main.c b/board/project-yosemite/syter_boot/main.c index 65de84954..1a452fc52 100644 --- a/board/project-yosemite/syter_boot/main.c +++ b/board/project-yosemite/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/project-yosemite/syter_boot_spi/CMakeLists.txt b/board/project-yosemite/syter_boot_spi/CMakeLists.txt index 7ea44abdc..b6fbda74d 100644 --- a/board/project-yosemite/syter_boot_spi/CMakeLists.txt +++ b/board/project-yosemite/syter_boot_spi/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_spi main.c diff --git a/board/project-yosemite/syter_boot_spi/main.c b/board/project-yosemite/syter_boot_spi/main.c index 963c548c5..a25680b2c 100644 --- a/board/project-yosemite/syter_boot_spi/main.c +++ b/board/project-yosemite/syter_boot_spi/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/board.c b/board/tinyvision/board.c index 51120d4db..f9b8a338f 100644 --- a/board/tinyvision/board.c +++ b/board/tinyvision/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/tinyvision/cli_test/CMakeLists.txt b/board/tinyvision/cli_test/CMakeLists.txt index e2505e8ec..137e7a122 100644 --- a/board/tinyvision/cli_test/CMakeLists.txt +++ b/board/tinyvision/cli_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(cli_test main.c diff --git a/board/tinyvision/cli_test/main.c b/board/tinyvision/cli_test/main.c index 7ee88e1a6..a8b2c9019 100644 --- a/board/tinyvision/cli_test/main.c +++ b/board/tinyvision/cli_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/eabi_compat.c b/board/tinyvision/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/tinyvision/eabi_compat.c +++ b/board/tinyvision/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/tinyvision/fdt_cli/CMakeLists.txt b/board/tinyvision/fdt_cli/CMakeLists.txt index 20c9a6496..67b3c98f0 100644 --- a/board/tinyvision/fdt_cli/CMakeLists.txt +++ b/board/tinyvision/fdt_cli/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(fdt_cli main.c diff --git a/board/tinyvision/fdt_cli/main.c b/board/tinyvision/fdt_cli/main.c index 4f02a0787..033422361 100644 --- a/board/tinyvision/fdt_cli/main.c +++ b/board/tinyvision/fdt_cli/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/fdt_parser/CMakeLists.txt b/board/tinyvision/fdt_parser/CMakeLists.txt index 8014f0ea5..5e7747579 100644 --- a/board/tinyvision/fdt_parser/CMakeLists.txt +++ b/board/tinyvision/fdt_parser/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(fdtparser main.c diff --git a/board/tinyvision/fdt_parser/main.c b/board/tinyvision/fdt_parser/main.c index ad8951186..640842429 100644 --- a/board/tinyvision/fdt_parser/main.c +++ b/board/tinyvision/fdt_parser/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/head.c b/board/tinyvision/head.c index 05d101a78..d4d47332c 100644 --- a/board/tinyvision/head.c +++ b/board/tinyvision/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/tinyvision/hello_world/CMakeLists.txt b/board/tinyvision/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/tinyvision/hello_world/CMakeLists.txt +++ b/board/tinyvision/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/tinyvision/hello_world/main.c b/board/tinyvision/hello_world/main.c index 726d614a9..70c93f708 100644 --- a/board/tinyvision/hello_world/main.c +++ b/board/tinyvision/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/i2c_oled/CMakeLists.txt b/board/tinyvision/i2c_oled/CMakeLists.txt index c0ae01a50..de9c26317 100644 --- a/board/tinyvision/i2c_oled/CMakeLists.txt +++ b/board/tinyvision/i2c_oled/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(i2c_oled main.c diff --git a/board/tinyvision/i2c_oled/main.c b/board/tinyvision/i2c_oled/main.c index bd5d0efed..33ba7973a 100644 --- a/board/tinyvision/i2c_oled/main.c +++ b/board/tinyvision/i2c_oled/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/i2c_test/CMakeLists.txt b/board/tinyvision/i2c_test/CMakeLists.txt index 03fa16278..445e030c5 100644 --- a/board/tinyvision/i2c_test/CMakeLists.txt +++ b/board/tinyvision/i2c_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(i2c_test main.c diff --git a/board/tinyvision/i2c_test/main.c b/board/tinyvision/i2c_test/main.c index 6074bd574..16ccfde06 100644 --- a/board/tinyvision/i2c_test/main.c +++ b/board/tinyvision/i2c_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/init_dram/CMakeLists.txt b/board/tinyvision/init_dram/CMakeLists.txt index c02c6d1ea..d86180558 100644 --- a/board/tinyvision/init_dram/CMakeLists.txt +++ b/board/tinyvision/init_dram/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(initdram main.c diff --git a/board/tinyvision/init_dram/main.c b/board/tinyvision/init_dram/main.c index aa251a434..6dec36da7 100644 --- a/board/tinyvision/init_dram/main.c +++ b/board/tinyvision/init_dram/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/load_e907/CMakeLists.txt b/board/tinyvision/load_e907/CMakeLists.txt index 457b306a7..974c606f1 100644 --- a/board/tinyvision/load_e907/CMakeLists.txt +++ b/board/tinyvision/load_e907/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(loade907 main.c diff --git a/board/tinyvision/load_e907/main.c b/board/tinyvision/load_e907/main.c index b3df2e9ae..f1b900cb3 100644 --- a/board/tinyvision/load_e907/main.c +++ b/board/tinyvision/load_e907/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/read_chip_efuse/CMakeLists.txt b/board/tinyvision/read_chip_efuse/CMakeLists.txt index b515d278c..d2c6d6576 100644 --- a/board/tinyvision/read_chip_efuse/CMakeLists.txt +++ b/board/tinyvision/read_chip_efuse/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(read_chipsid main.c diff --git a/board/tinyvision/read_chip_efuse/main.c b/board/tinyvision/read_chip_efuse/main.c index f38e5b8db..bf4dc9432 100644 --- a/board/tinyvision/read_chip_efuse/main.c +++ b/board/tinyvision/read_chip_efuse/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/read_chipsid/CMakeLists.txt b/board/tinyvision/read_chipsid/CMakeLists.txt index 7f1611a34..a5d890b7a 100644 --- a/board/tinyvision/read_chipsid/CMakeLists.txt +++ b/board/tinyvision/read_chipsid/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(read_chip_efuse main.c diff --git a/board/tinyvision/read_chipsid/main.c b/board/tinyvision/read_chipsid/main.c index accc24446..7f8ad2a7c 100644 --- a/board/tinyvision/read_chipsid/main.c +++ b/board/tinyvision/read_chipsid/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/ruapu_test/CMakeLists.txt b/board/tinyvision/ruapu_test/CMakeLists.txt index 8bae387a8..1c79325bb 100644 --- a/board/tinyvision/ruapu_test/CMakeLists.txt +++ b/board/tinyvision/ruapu_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(ruapu_test main.c diff --git a/board/tinyvision/ruapu_test/main.c b/board/tinyvision/ruapu_test/main.c index 1288975e2..212a889b7 100644 --- a/board/tinyvision/ruapu_test/main.c +++ b/board/tinyvision/ruapu_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/spi_lcd/CMakeLists.txt b/board/tinyvision/spi_lcd/CMakeLists.txt index d82093cf9..06f7edcc3 100644 --- a/board/tinyvision/spi_lcd/CMakeLists.txt +++ b/board/tinyvision/spi_lcd/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(spi_lcd main.c diff --git a/board/tinyvision/spi_lcd/lcd.h b/board/tinyvision/spi_lcd/lcd.h index 335301454..e692776ba 100644 --- a/board/tinyvision/spi_lcd/lcd.h +++ b/board/tinyvision/spi_lcd/lcd.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LCD_H__ #define __LCD_H__ diff --git a/board/tinyvision/spi_lcd/lcd_init.h b/board/tinyvision/spi_lcd/lcd_init.h index 2896f6da6..a2c3e3802 100644 --- a/board/tinyvision/spi_lcd/lcd_init.h +++ b/board/tinyvision/spi_lcd/lcd_init.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LCD_INIT_H__ #define __LCD_INIT_H__ diff --git a/board/tinyvision/spi_lcd/main.c b/board/tinyvision/spi_lcd/main.c index dc83b712c..ca9f9eefb 100644 --- a/board/tinyvision/spi_lcd/main.c +++ b/board/tinyvision/spi_lcd/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/start.S b/board/tinyvision/start.S index 179f110e9..d227c0c00 100644 --- a/board/tinyvision/start.S +++ b/board/tinyvision/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/tinyvision/syter_amp/CMakeLists.txt b/board/tinyvision/syter_amp/CMakeLists.txt index 317a09870..482c902ec 100644 --- a/board/tinyvision/syter_amp/CMakeLists.txt +++ b/board/tinyvision/syter_amp/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_amp main.c diff --git a/board/tinyvision/syter_amp/main.c b/board/tinyvision/syter_amp/main.c index 02f669ada..2107ac1f6 100644 --- a/board/tinyvision/syter_amp/main.c +++ b/board/tinyvision/syter_amp/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/syter_boot/CMakeLists.txt b/board/tinyvision/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/tinyvision/syter_boot/CMakeLists.txt +++ b/board/tinyvision/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/tinyvision/syter_boot/main.c b/board/tinyvision/syter_boot/main.c index 65de84954..1a452fc52 100644 --- a/board/tinyvision/syter_boot/main.c +++ b/board/tinyvision/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/syter_boot_sdnand/CMakeLists.txt b/board/tinyvision/syter_boot_sdnand/CMakeLists.txt index 6d58c49e6..6be2071b2 100644 --- a/board/tinyvision/syter_boot_sdnand/CMakeLists.txt +++ b/board/tinyvision/syter_boot_sdnand/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_sdnand main.c diff --git a/board/tinyvision/syter_boot_sdnand/main.c b/board/tinyvision/syter_boot_sdnand/main.c index ab5c2742d..7c081c4bc 100644 --- a/board/tinyvision/syter_boot_sdnand/main.c +++ b/board/tinyvision/syter_boot_sdnand/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/syter_boot_spi/CMakeLists.txt b/board/tinyvision/syter_boot_spi/CMakeLists.txt index 7ea44abdc..b6fbda74d 100644 --- a/board/tinyvision/syter_boot_spi/CMakeLists.txt +++ b/board/tinyvision/syter_boot_spi/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_spi main.c diff --git a/board/tinyvision/syter_boot_spi/main.c b/board/tinyvision/syter_boot_spi/main.c index 1b88961d9..69fd5c38b 100644 --- a/board/tinyvision/syter_boot_spi/main.c +++ b/board/tinyvision/syter_boot_spi/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/syter_bootargs/CMakeLists.txt b/board/tinyvision/syter_bootargs/CMakeLists.txt index ea16d4227..fc7770931 100644 --- a/board/tinyvision/syter_bootargs/CMakeLists.txt +++ b/board/tinyvision/syter_bootargs/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_bootargs main.c diff --git a/board/tinyvision/syter_bootargs/main.c b/board/tinyvision/syter_bootargs/main.c index ad5135a1a..30b5b03ba 100644 --- a/board/tinyvision/syter_bootargs/main.c +++ b/board/tinyvision/syter_bootargs/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/tinyvision/usb_test/CMakeLists.txt b/board/tinyvision/usb_test/CMakeLists.txt index b345462d4..d32d5cc99 100644 --- a/board/tinyvision/usb_test/CMakeLists.txt +++ b/board/tinyvision/usb_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(usb_test main.c diff --git a/board/tinyvision/usb_test/main.c b/board/tinyvision/usb_test/main.c index ddf03c2ab..d87099ec7 100644 --- a/board/tinyvision/usb_test/main.c +++ b/board/tinyvision/usb_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/yuzukihomekit/board.c b/board/yuzukihomekit/board.c index eb35d702d..8b2cea3cb 100644 --- a/board/yuzukihomekit/board.c +++ b/board/yuzukihomekit/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/yuzukihomekit/eabi_compat.c b/board/yuzukihomekit/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/yuzukihomekit/eabi_compat.c +++ b/board/yuzukihomekit/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/yuzukihomekit/head.c b/board/yuzukihomekit/head.c index 05d101a78..d4d47332c 100644 --- a/board/yuzukihomekit/head.c +++ b/board/yuzukihomekit/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/yuzukihomekit/load_c906/CMakeLists.txt b/board/yuzukihomekit/load_c906/CMakeLists.txt index edf4245ae..04835824c 100644 --- a/board/yuzukihomekit/load_c906/CMakeLists.txt +++ b/board/yuzukihomekit/load_c906/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(load_c906 main.c diff --git a/board/yuzukihomekit/load_c906/main.c b/board/yuzukihomekit/load_c906/main.c index dbfa227cc..7bca78a2d 100644 --- a/board/yuzukihomekit/load_c906/main.c +++ b/board/yuzukihomekit/load_c906/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/yuzukihomekit/start.S b/board/yuzukihomekit/start.S index 179f110e9..d227c0c00 100644 --- a/board/yuzukihomekit/start.S +++ b/board/yuzukihomekit/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/yuzukihomekit/syter_boot/CMakeLists.txt b/board/yuzukihomekit/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/yuzukihomekit/syter_boot/CMakeLists.txt +++ b/board/yuzukihomekit/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/yuzukihomekit/syter_boot/main.c b/board/yuzukihomekit/syter_boot/main.c index 2d5ea9f48..39a6930da 100644 --- a/board/yuzukihomekit/syter_boot/main.c +++ b/board/yuzukihomekit/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/yuzukihomekit/usb_test/CMakeLists.txt b/board/yuzukihomekit/usb_test/CMakeLists.txt index b345462d4..d32d5cc99 100644 --- a/board/yuzukihomekit/usb_test/CMakeLists.txt +++ b/board/yuzukihomekit/usb_test/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(usb_test main.c diff --git a/board/yuzukihomekit/usb_test/main.c b/board/yuzukihomekit/usb_test/main.c index 8e085fa44..c9f964a46 100644 --- a/board/yuzukihomekit/usb_test/main.c +++ b/board/yuzukihomekit/usb_test/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/yuzukilizard/board.c b/board/yuzukilizard/board.c index 98d746b77..accbaaf5a 100644 --- a/board/yuzukilizard/board.c +++ b/board/yuzukilizard/board.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/yuzukilizard/eabi_compat.c b/board/yuzukilizard/eabi_compat.c index 93303d893..efa4d10e3 100644 --- a/board/yuzukilizard/eabi_compat.c +++ b/board/yuzukilizard/eabi_compat.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ void abort(void) { while (1) diff --git a/board/yuzukilizard/head.c b/board/yuzukilizard/head.c index 05d101a78..d4d47332c 100644 --- a/board/yuzukilizard/head.c +++ b/board/yuzukilizard/head.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/board/yuzukilizard/hello_world/CMakeLists.txt b/board/yuzukilizard/hello_world/CMakeLists.txt index b5ce1ea59..4b10765c7 100644 --- a/board/yuzukilizard/hello_world/CMakeLists.txt +++ b/board/yuzukilizard/hello_world/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(helloworld main.c diff --git a/board/yuzukilizard/hello_world/main.c b/board/yuzukilizard/hello_world/main.c index 726d614a9..70c93f708 100644 --- a/board/yuzukilizard/hello_world/main.c +++ b/board/yuzukilizard/hello_world/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/yuzukilizard/start.S b/board/yuzukilizard/start.S index 179f110e9..d227c0c00 100644 --- a/board/yuzukilizard/start.S +++ b/board/yuzukilizard/start.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/board/yuzukilizard/syter_boot/CMakeLists.txt b/board/yuzukilizard/syter_boot/CMakeLists.txt index 5bfbb5f4f..19db5564a 100644 --- a/board/yuzukilizard/syter_boot/CMakeLists.txt +++ b/board/yuzukilizard/syter_boot/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot main.c diff --git a/board/yuzukilizard/syter_boot/main.c b/board/yuzukilizard/syter_boot/main.c index 65de84954..1a452fc52 100644 --- a/board/yuzukilizard/syter_boot/main.c +++ b/board/yuzukilizard/syter_boot/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/board/yuzukilizard/syter_boot_spi/CMakeLists.txt b/board/yuzukilizard/syter_boot_spi/CMakeLists.txt index 7ea44abdc..b6fbda74d 100644 --- a/board/yuzukilizard/syter_boot_spi/CMakeLists.txt +++ b/board/yuzukilizard/syter_boot_spi/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_syterkit_app(syter_boot_spi main.c diff --git a/board/yuzukilizard/syter_boot_spi/main.c b/board/yuzukilizard/syter_boot_spi/main.c index 529c60ed5..e3efbb3c8 100644 --- a/board/yuzukilizard/syter_boot_spi/main.c +++ b/board/yuzukilizard/syter_boot_spi/main.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/cmake/add_syterkit_app.cmake b/cmake/add_syterkit_app.cmake index 1411d5749..e6df996a0 100644 --- a/cmake/add_syterkit_app.cmake +++ b/cmake/add_syterkit_app.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ # List of common libraries used by the application set(APP_COMMON_LIBRARY diff --git a/cmake/add_syterkit_driver.cmake b/cmake/add_syterkit_driver.cmake new file mode 100644 index 000000000..c122bef0f --- /dev/null +++ b/cmake/add_syterkit_driver.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +macro(add_syterkit_driver target_name) + include(${target_name}/CMakeModule.cmake) +endmacro() diff --git a/cmake/board/100ask-d1-h.cmake b/cmake/board/100ask-d1-h.cmake index 502e5a645..cb4e04d14 100644 --- a/cmake/board/100ask-d1-h.cmake +++ b/cmake/board/100ask-d1-h.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_RISCV64 True) set(CONFIG_ARCH_RISCV64_CORE_C906 True) diff --git a/cmake/board/100ask-ros.cmake b/cmake/board/100ask-ros.cmake index 6e3881aae..69c154db3 100644 --- a/cmake/board/100ask-ros.cmake +++ b/cmake/board/100ask-ros.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_ARCH_ARM32_ARM64 True) diff --git a/cmake/board/100ask-t113i.cmake b/cmake/board/100ask-t113i.cmake index 881de0ae0..0c465b6e2 100644 --- a/cmake/board/100ask-t113i.cmake +++ b/cmake/board/100ask-t113i.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW20 True) diff --git a/cmake/board/100ask-t113s3.cmake b/cmake/board/100ask-t113s3.cmake index 52f9ceb0a..2bf064cca 100644 --- a/cmake/board/100ask-t113s3.cmake +++ b/cmake/board/100ask-t113s3.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW20 True) diff --git a/cmake/board/avaota-a1.cmake b/cmake/board/avaota-a1.cmake index aed12ec80..2dd4aaecd 100644 --- a/cmake/board/avaota-a1.cmake +++ b/cmake/board/avaota-a1.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_ARCH_ARM32_ARM64 True) diff --git a/cmake/board/avaota-cam.cmake b/cmake/board/avaota-cam.cmake index a5b969133..c78342983 100644 --- a/cmake/board/avaota-cam.cmake +++ b/cmake/board/avaota-cam.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_RISCV32 True) set(CONFIG_ARCH_RISCV32_CORE_E907 True) diff --git a/cmake/board/avaota-nas.cmake b/cmake/board/avaota-nas.cmake new file mode 100644 index 000000000..727d30b50 --- /dev/null +++ b/cmake/board/avaota-nas.cmake @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0+ + +set(CONFIG_ARCH_ARM32 True) +set(CONFIG_ARCH_ARM32_ARM64 True) +set(CONFIG_CHIP_SUN60IW2 True) +set(CONFIG_CHIP_WITHPMU True) +set(CONFIG_CHIP_DCACHE True) +set(CONFIG_CHIP_MMC_V2 True) +set(CONFIG_CHIP_GPIO_V3 True) +set(CONFIG_BOARD_AVAOTA-NAS True) + +add_definitions(-DCONFIG_CHIP_SUN60IW2) +add_definitions(-DCONFIG_CHIP_DCACHE) +add_definitions(-DCONFIG_CHIP_MMC_V2) +add_definitions(-DCONFIG_CHIP_GPIO_V3) +add_definitions(-DCONFIG_FATFS_CACHE_SIZE=0xFFFFFFF) +add_definitions(-DCONFIG_FATFS_CACHE_ADDR=0x60000000) + +set(CONFIG_USE_DRAM_PAYLOAD True) +set(CONFIG_USE_PREBUILT_DRAM_PAYLOAD True) +set(CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH "${CMAKE_SOURCE_DIR}/payloads/sun60iw2_libdram") +set(CONFIG_USE_DRAM_PAYLOAD_BIN_PATH "${CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH}/output/ddr.bin") +set(CONFIG_USE_DRAM_PAYLOAD_FILE_PATH "${CMAKE_SOURCE_DIR}/board/avaota-nas/payloads/init_dram_bin.c") +set(CONFIG_USE_DRAM_PAYLOAD_SECTION "init_dram_bin") + +# Set the cross-compile toolchain +set(CROSS_COMPILE "arm-none-eabi-") +set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain") + +# Set the C and C++ compilers +set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc") +set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}g++") + +set(CMAKE_COMMON_FLAGS "-nostdlib -nostdinc -Os -march=armv8.4-a -mthumb-interwork -fno-common -ffunction-sections -fno-builtin -fno-stack-protector -ffreestanding -mthumb -mfpu=neon -mfloat-abi=softfp -pipe") + +# Disable specific warning flags for C and C++ compilers +set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers") +set(CMAKE_CXX_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast") + +set(ARCH_BIN_START_ADDRESS "0x00047000") +set(ARCH_BIN_SRAM_LENGTH "256K") + +set(ARCH_FEL_START_ADDRESS "0x00048c00") +set(ARCH_FEL_SRAM_LENGTH "240K") + +if(NOT CONFIG_USE_PREBUILT_DRAM_PAYLOAD) + # Create an external project and build it + ExternalProject_Add( + init_dram + PREFIX init_dram + SOURCE_DIR "${CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH}" + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND make -C ${CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH} + BUILD_IN_SOURCE 1 + ) + + # Create inital init dram bin file for build + add_custom_command( + TARGET init_dram + POST_BUILD COMMAND ${CMAKE_BIN2ARRAY} ${CONFIG_USE_DRAM_PAYLOAD_BIN_PATH} ${CONFIG_USE_DRAM_PAYLOAD_FILE_PATH} ${CONFIG_USE_DRAM_PAYLOAD_SECTION} + COMMENT "Generate DRAM LIB Payload ${CONFIG_USE_DRAM_PAYLOAD_BIN_PATH} for ${CONFIG_USE_DRAM_PAYLOAD_FILE_PATH}" + ) +endif() diff --git a/cmake/board/dongshanpi-aict.cmake b/cmake/board/dongshanpi-aict.cmake index 8de49a581..b4851be96 100644 --- a/cmake/board/dongshanpi-aict.cmake +++ b/cmake/board/dongshanpi-aict.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW21 True) diff --git a/cmake/board/longanpi-3h.cmake b/cmake/board/longanpi-3h.cmake index 32d763a9d..ea69b6a70 100644 --- a/cmake/board/longanpi-3h.cmake +++ b/cmake/board/longanpi-3h.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_ARCH_ARM32_ARM64 True) diff --git a/cmake/board/longanpi-4b.cmake b/cmake/board/longanpi-4b.cmake index a9aa2c1e8..a57905bd7 100644 --- a/cmake/board/longanpi-4b.cmake +++ b/cmake/board/longanpi-4b.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_ARCH_ARM32_ARM64 True) diff --git a/cmake/board/lt527x.cmake b/cmake/board/lt527x.cmake index 9a9210a58..3e3aaa231 100644 --- a/cmake/board/lt527x.cmake +++ b/cmake/board/lt527x.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_ARCH_ARM32_ARM64 True) diff --git a/cmake/board/project-yosemite.cmake b/cmake/board/project-yosemite.cmake index a08dd10b0..c3c8ee3ec 100644 --- a/cmake/board/project-yosemite.cmake +++ b/cmake/board/project-yosemite.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW21 True) diff --git a/cmake/board/tinyvision.cmake b/cmake/board/tinyvision.cmake index 7314fab60..fd7b9fd39 100644 --- a/cmake/board/tinyvision.cmake +++ b/cmake/board/tinyvision.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW21 True) diff --git a/cmake/board/yuzukihomekit.cmake b/cmake/board/yuzukihomekit.cmake index f454eac9e..df42b5ae0 100644 --- a/cmake/board/yuzukihomekit.cmake +++ b/cmake/board/yuzukihomekit.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW20 True) diff --git a/cmake/board/yuzukilizard.cmake b/cmake/board/yuzukilizard.cmake index bd3c7a2b0..120789804 100644 --- a/cmake/board/yuzukilizard.cmake +++ b/cmake/board/yuzukilizard.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW21 True) diff --git a/cmake/lib/generic_sun8iw21.cmake b/cmake/lib/generic_sun8iw21.cmake index 6c8c65d10..51928678d 100644 --- a/cmake/lib/generic_sun8iw21.cmake +++ b/cmake/lib/generic_sun8iw21.cmake @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ set(CONFIG_ARCH_ARM32 True) set(CONFIG_CHIP_SUN8IW21 True) diff --git a/config.h.in b/config.h.in index e95bc3a2a..2ea8dc398 100644 --- a/config.h.in +++ b/config.h.in @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CONFIG_H_ #define _CONFIG_H_ diff --git a/include/arch/arm32/barrier.h b/include/arch/arm32/barrier.h index 5f5b88fdf..b71e68f35 100644 --- a/include/arch/arm32/barrier.h +++ b/include/arch/arm32/barrier.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARM32_BARRIER_H__ #define __ARM32_BARRIER_H__ diff --git a/include/arch/arm32/io.h b/include/arch/arm32/io.h index 0402662e2..a855400aa 100644 --- a/include/arch/arm32/io.h +++ b/include/arch/arm32/io.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __IO_H__ #define __IO_H__ diff --git a/include/arch/arm32/jmp.h b/include/arch/arm32/jmp.h index e9d2518a6..ff3eddbe1 100644 --- a/include/arch/arm32/jmp.h +++ b/include/arch/arm32/jmp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef _JMP_H_ #define _JMP_H_ diff --git a/include/arch/arm32/linkage.h b/include/arch/arm32/linkage.h index fae34a8ba..9a01c25d2 100644 --- a/include/arch/arm32/linkage.h +++ b/include/arch/arm32/linkage.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARM32_LINKAGE_H__ #define __ARM32_LINKAGE_H__ diff --git a/include/arch/arm32/mmu.h b/include/arch/arm32/mmu.h index 0bea741eb..d582eb844 100644 --- a/include/arch/arm32/mmu.h +++ b/include/arch/arm32/mmu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MMU_H__ #define __MMU_H__ diff --git a/include/arch/arm32/stdlib.h b/include/arch/arm32/stdlib.h index e69de29bb..bf65e67c4 100644 --- a/include/arch/arm32/stdlib.h +++ b/include/arch/arm32/stdlib.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __STDLIB_H__ +#define __STDLIB_H__ + +/** + * @brief Convert a program counter (PC) to Thumb mode address. + * + * This macro modifies the program counter (PC) to ensure it points to a valid Thumb + * mode address by setting the least significant bit (LSB) to 1. Thumb instructions + * in ARM architecture require that the LSB of the PC is set to 1 to indicate Thumb mode. + * + * @param pc The program counter to be converted to Thumb mode address. + */ +#define MAKE_THUMB_ADDR(pc) \ + do { \ + (pc) = (void *) ((uint32_t) (pc) | 0x1); /**< Set the least significant bit of PC to 1 */ \ + } while (0) + +/** + * @brief Perform a backtrace to find the call stack. + * + * This function attempts to walk the call stack by analyzing the program counter (PC), + * stack pointer (SP), and link register (LR) to determine the sequence of function calls + * leading to the current execution point. + * + * The backtrace process works by using the stack and link register to trace the call hierarchy, + * logging each level of the backtrace, and attempting recovery from any errors. + * If the backtrace from the stack fails, it will attempt to trace using the link register (LR). + * + * @param PC The current program counter (PC), typically pointing to the instruction where the backtrace starts. + * @param SP The current stack pointer (SP), pointing to the top of the stack. + * @param LR The link register (LR), used to store return addresses for function calls. + * + * @return The number of backtrace levels successfully traversed. + * Returns 0 if no valid backtrace could be performed. + */ +int backtrace(char *PC, long *SP, char *LR); + +/** + * @brief Dumps the current stack state and performs a backtrace. + * + * This function captures the current program counter (PC), stack pointer (SP), + * link register (LR), and current processor status register (CPSR). It uses inline assembly + * to obtain these values, then performs a backtrace to provide insight into the function call stack. + * + * The function also checks if the processor is in THUMB mode based on the CPSR state and adjusts + * the program counter (PC) accordingly. If the program counter or stack pointer is invalid, + * the function will return early with a status of 0. + * + * @return The result of the backtrace function, representing the number of successfully + * traced backtrace levels, or 0 if the stack pointer (SP) or program counter (PC) is invalid. + */ +int dump_stack(void); + +#endif // __STDLIB_H__ \ No newline at end of file diff --git a/include/arch/arm32/timer.h b/include/arch/arm32/timer.h index 81ac51d46..9fa1f2625 100644 --- a/include/arch/arm32/timer.h +++ b/include/arch/arm32/timer.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_TIMER_H__ #define __SYS_TIMER_H__ diff --git a/include/arch/riscv/barrier.h b/include/arch/riscv/barrier.h index 83cf293a3..860f7debe 100644 --- a/include/arch/riscv/barrier.h +++ b/include/arch/riscv/barrier.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __RISCV_BARRIER_H__ #define __RISCV_BARRIER_H__ diff --git a/include/arch/riscv/csr.h b/include/arch/riscv/csr.h index a4df4323c..e7553f4d9 100644 --- a/include/arch/riscv/csr.h +++ b/include/arch/riscv/csr.h @@ -5,6 +5,7 @@ extern "C" { #endif +/** Machine Status Bit Definitions */ #define MSTATUS_UIE (1 << 0) #define MSTATUS_SIE (1 << 1) #define MSTATUS_MIE (1 << 3) @@ -20,12 +21,37 @@ extern "C" { #define MSTATUS_MXR (1 << 19) #define MSTATUS_TVM (1 << 20) #define MSTATUS_TW (1 << 21) -#define MSTATUS_TSR (1 << 22) #define MSTATUS32_SD (1 << 31) #define MSTATUS_UXL (3ULL << 32) #define MSTATUS_SXL (3ULL << 34) #define MSTATUS64_SD (1ULL << 63) +/** Machine Extra Status Bit Definitions */ +#define MXSTATUS_THEADISAEE (1 << 22) + +/** Machine Hardware Config Bit Definitions */ +#define MHCR_IE (1 << 0) +#define MHCR_DE (1 << 1) +#define MHCR_WB (1 << 2) +#define MHCR_WA (1 << 3) +#define MHCR_RS (1 << 4) +#define MHCR_BPE (1 << 5) +#define MHCR_BTE (1 << 12) + +/** Machine HINT Bit Definitions */ +#define MHINT_D_PLD (1 << 2) +#define MHINT_AMR_0 (0b00 << 3) +#define MHINT_AMR_1 (0b01 << 3) +#define MHINT_AMR_2 (0b10 << 3) +#define MHINT_AMR_3 (0b11 << 3) +#define MHINT_IWPE (1 << 10) +#define MHINT_PREF_N_2 (0b00 << 13) +#define MHINT_PREF_N_4 (0b01 << 13) +#define MHINT_PREF_N_8 (0b10 << 13) +#define MHINT_PREF_N_16 (0b11 << 13) +#define MHINT_AEE (1 << 20) +#define MHINT_PCFIFO_FREEZE (1 << 24) + /** Machine Interrupt Pending (mip) Bit Definitions */ #define MIP_USIP (1 << 0) /**< User Software Interrupt Pending */ #define MIP_SSIP (1 << 1) /**< Supervisor Software Interrupt Pending */ diff --git a/include/arch/riscv/io.h b/include/arch/riscv/io.h index b7df3080a..0ad7bc24c 100644 --- a/include/arch/riscv/io.h +++ b/include/arch/riscv/io.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __IO_H__ #define __IO_H__ diff --git a/include/arch/riscv/limits.h b/include/arch/riscv/limits.h index 66dd0b621..5aaef6a95 100644 --- a/include/arch/riscv/limits.h +++ b/include/arch/riscv/limits.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __RISCV_LIMITS_H__ #define __RISCV_LIMITS_H__ diff --git a/include/arch/riscv/linkage.h b/include/arch/riscv/linkage.h index b078d55d0..1365b0875 100644 --- a/include/arch/riscv/linkage.h +++ b/include/arch/riscv/linkage.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __RISCV_LINKAGE_H__ #define __RISCV_LINKAGE_H__ diff --git a/include/arch/riscv/mmu.h b/include/arch/riscv/mmu.h index dd0aefbfd..12f184834 100644 --- a/include/arch/riscv/mmu.h +++ b/include/arch/riscv/mmu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MMU_H__ #define __MMU_H__ diff --git a/include/arch/riscv/stdarg.h b/include/arch/riscv/stdarg.h index 428ffda42..644af19c6 100644 --- a/include/arch/riscv/stdarg.h +++ b/include/arch/riscv/stdarg.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __STDARG_H__ #define __STDARG_H__ diff --git a/include/arch/riscv/stdbool.h b/include/arch/riscv/stdbool.h index 5e77cda28..5b9fac0ba 100644 --- a/include/arch/riscv/stdbool.h +++ b/include/arch/riscv/stdbool.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __STDBOOL_H__ #define __STDBOOL_H__ diff --git a/include/arch/riscv/stddef.h b/include/arch/riscv/stddef.h index a61515ac5..cbef7283b 100644 --- a/include/arch/riscv/stddef.h +++ b/include/arch/riscv/stddef.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __STDDEF_H__ #define __STDDEF_H__ diff --git a/include/arch/riscv/stdint.h b/include/arch/riscv/stdint.h index 9d14e267f..4d8309ea8 100644 --- a/include/arch/riscv/stdint.h +++ b/include/arch/riscv/stdint.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /** * @file riscv64_stdint.h diff --git a/include/arch/riscv/stdlib.h b/include/arch/riscv/stdlib.h index e69de29bb..815dee90e 100644 --- a/include/arch/riscv/stdlib.h +++ b/include/arch/riscv/stdlib.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __STDLIB_H__ +#define __STDLIB_H__ + +/** + * @brief Perform a backtrace to find the call stack. + * + * This function attempts to walk the call stack by analyzing the program counter (PC), + * stack pointer (SP), and link register (LR) to determine the sequence of function calls + * leading to the current execution point. + * + * The backtrace process works by using the stack and link register to trace the call hierarchy, + * logging each level of the backtrace, and attempting recovery from any errors. + * If the backtrace from the stack fails, it will attempt to trace using the link register (LR). + * + * @param PC The current program counter (PC), typically pointing to the instruction where the backtrace starts. + * @param SP The current stack pointer (SP), pointing to the top of the stack. + * @param LR The link register (LR), used to store return addresses for function calls. + * + * @return The number of backtrace levels successfully traversed. + * Returns 0 if no valid backtrace could be performed. + */ +int backtrace(char *PC, long *SP, char *LR); + +/** + * @brief Dumps the current stack state and performs a backtrace. + * + * This function captures the current program counter (PC), stack pointer (SP), + * link register (LR), and current processor status register (CPSR). It uses inline assembly + * to obtain these values, then performs a backtrace to provide insight into the function call stack. + * + * The function also checks if the processor is in THUMB mode based on the CPSR state and adjusts + * the program counter (PC) accordingly. If the program counter or stack pointer is invalid, + * the function will return early with a status of 0. + * + * @return The result of the backtrace function, representing the number of successfully + * traced backtrace levels, or 0 if the stack pointer (SP) or program counter (PC) is invalid. + */ +int dump_stack(void); + +#endif // __STDLIB_H__ \ No newline at end of file diff --git a/include/arch/riscv/timer.h b/include/arch/riscv/timer.h index 884afbfba..44983743d 100644 --- a/include/arch/riscv/timer.h +++ b/include/arch/riscv/timer.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_TIMER_H__ #define __SYS_TIMER_H__ diff --git a/include/arch/riscv/types.h b/include/arch/riscv/types.h index 8bbc57960..3fbbf5873 100644 --- a/include/arch/riscv/types.h +++ b/include/arch/riscv/types.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __RISCV_TYPES_H__ #define __RISCV_TYPES_H__ diff --git a/include/cli/cli.h b/include/cli/cli.h index 639264081..54fa0338a 100644 --- a/include/cli/cli.h +++ b/include/cli/cli.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CLI_H__ #define __CLI_H__ diff --git a/include/cli/cli_config.h b/include/cli/cli_config.h index 758a934a5..786e40b94 100644 --- a/include/cli/cli_config.h +++ b/include/cli/cli_config.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CLI_CONFIG_H__ #define __CLI_CONFIG_H__ diff --git a/include/cli/cli_history.h b/include/cli/cli_history.h index 1ad48cf24..33f2e581c 100644 --- a/include/cli/cli_history.h +++ b/include/cli/cli_history.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CLI_HISTORY_H__ #define __CLI_HISTORY_H__ diff --git a/include/cli/cli_shell.h b/include/cli/cli_shell.h index adc6acef9..159960af6 100644 --- a/include/cli/cli_shell.h +++ b/include/cli/cli_shell.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CLI_SHELL_H__ #define __CLI_SHELL_H__ diff --git a/include/cli/cli_termesc.h b/include/cli/cli_termesc.h index ae67ac685..775e6ed28 100644 --- a/include/cli/cli_termesc.h +++ b/include/cli/cli_termesc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CLI_TERMESC_H__ #define __CLI_TERMESC_H__ diff --git a/include/common.h b/include/common.h index 59f48b37c..c2a08e23f 100644 --- a/include/common.h +++ b/include/common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __COMMON_H__ #define __COMMON_H__ diff --git a/include/ctype.h b/include/ctype.h index f63a5e962..2b97e5c24 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CTYPE_H__ #define __CTYPE_H__ diff --git a/include/drivers/chips/sun20iw1/reg-ccu.h b/include/drivers/chips/sun20iw1/reg-ccu.h index 8c688bc2c..d5b92b9e7 100644 --- a/include/drivers/chips/sun20iw1/reg-ccu.h +++ b/include/drivers/chips/sun20iw1/reg-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN20IW1_REG_CCU_H__ #define __SUN20IW1_REG_CCU_H__ diff --git a/include/drivers/chips/sun20iw1/reg-rproc.h b/include/drivers/chips/sun20iw1/reg-rproc.h index c24132567..ad28bcc76 100644 --- a/include/drivers/chips/sun20iw1/reg-rproc.h +++ b/include/drivers/chips/sun20iw1/reg-rproc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_RPROC_H__ #define __REG_RPROC_H__ diff --git a/include/drivers/chips/sun20iw5/reg-ccu.h b/include/drivers/chips/sun20iw5/reg-ccu.h index 94bdbd2b7..569cedc74 100644 --- a/include/drivers/chips/sun20iw5/reg-ccu.h +++ b/include/drivers/chips/sun20iw5/reg-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN20IW5_REG_CCU_H__ #define __SUN20IW5_REG_CCU_H__ diff --git a/include/drivers/chips/sun20iw5/reg-rproc.h b/include/drivers/chips/sun20iw5/reg-rproc.h index 622e9c11a..93a42164d 100644 --- a/include/drivers/chips/sun20iw5/reg-rproc.h +++ b/include/drivers/chips/sun20iw5/reg-rproc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_RPROC_H__ #define __REG_RPROC_H__ diff --git a/include/drivers/chips/sun50iw10/reg-ccu.h b/include/drivers/chips/sun50iw10/reg-ccu.h index 2ccc56430..e909bd344 100644 --- a/include/drivers/chips/sun50iw10/reg-ccu.h +++ b/include/drivers/chips/sun50iw10/reg-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN50IW10_REG_CCU_H__ #define __SUN50IW10_REG_CCU_H__ diff --git a/include/drivers/chips/sun50iw9/reg-ccu.h b/include/drivers/chips/sun50iw9/reg-ccu.h index ff4a6d35e..0ae404128 100644 --- a/include/drivers/chips/sun50iw9/reg-ccu.h +++ b/include/drivers/chips/sun50iw9/reg-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN50IW9_REG_CCU_H__ #define __SUN50IW9_REG_CCU_H__ diff --git a/include/drivers/chips/sun55iw3/reg-ccu.h b/include/drivers/chips/sun55iw3/reg-ccu.h index b7c0e81af..319a774f7 100644 --- a/include/drivers/chips/sun55iw3/reg-ccu.h +++ b/include/drivers/chips/sun55iw3/reg-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN55IW3_REG_CCU_H__ #define __SUN55IW3_REG_CCU_H__ diff --git a/include/drivers/chips/sun55iw3/reg-rproc.h b/include/drivers/chips/sun55iw3/reg-rproc.h index dc76ec72d..e3ba82678 100644 --- a/include/drivers/chips/sun55iw3/reg-rproc.h +++ b/include/drivers/chips/sun55iw3/reg-rproc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_RPROC_H__ #define __REG_RPROC_H__ diff --git a/include/drivers/chips/sun60iw2/reg-ccu.h b/include/drivers/chips/sun60iw2/reg-ccu.h new file mode 100644 index 000000000..a1c313f23 --- /dev/null +++ b/include/drivers/chips/sun60iw2/reg-ccu.h @@ -0,0 +1,5180 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SUN60IW2_REG_CCU_H__ +#define __SUN60IW2_REG_CCU_H__ + +#include + +#define PLL_REF_CTRL_REG 0x00000000//PLL_REF Control Register +#define PLL_REF_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_REF_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_REF_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_REF_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_REF_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_REF_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_REF_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_REF_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_REF_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_REF_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_REF_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_REF_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_REF_CTRL_REG_LOCK_OFFSET 28 +#define PLL_REF_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_REF_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_REF_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_REF_CTRL_REG_PLL_REG_EN_OFFSET 24 +#define PLL_REF_CTRL_REG_PLL_REG_EN_CLEAR_MASK (0x01000000) +#define PLL_REF_CTRL_REG_PLL_REG_EN_DISABLE 0b0 +#define PLL_REF_CTRL_REG_PLL_REG_EN_ENABLE 0b1 +#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 16 +#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x007f0000) +#define PLL_REF_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_REF_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_REF_LOCK_CTRL_REG 0x00000004//PLL_REF Lock Control Register +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_OFFSET 4 +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_PENDING 0b1 +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_OFFSET 0 +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_REF_BIAS_REG 0x00000010//PLL_REF Bias Register +#define PLL_REF_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_REF_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_DDR_CTRL_REG 0x00000020//PLL_DDR Control Register +#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_DDR_CTRL_REG_LOCK_OFFSET 28 +#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20 +#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000) +#define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_DDR_LOCK_CTRL_REG 0x00000024//PLL_DDR Lock Control Register +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_OFFSET 4 +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_PENDING 0b1 +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_OFFSET 0 +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_DDR_PAT0_CTRL_REG 0x00000028//PLL_DDR Pattern0 Control Register +#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_DDR_PAT1_CTRL_REG 0x0000002c//PLL_DDR Pattern1 Control Register +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_DDR_BIAS_REG 0x00000030//PLL_DDR Bias Register +#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_PERI0_CTRL_REG 0x000000a0//PLL_PERI0 Control Register +#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28 +#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000) +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000) +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET 25 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK (0x02000000) +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE 0b0 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE 0b1 +#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000) +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000) +#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET 2 +#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK (0x0000001c) +#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_PERI0_LOCK_CTRL_REG 0x000000a4//PLL_PERI0 Lock Control Register +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_OFFSET 4 +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_PENDING 0b1 +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_OFFSET 0 +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_PERI0_PAT0_CTRL_REG 0x000000a8//PLL_PERI0 Pattern0 Control Register +#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_PERI0_PAT1_CTRL_REG 0x000000ac//PLL_PERI0 Pattern1 Control Register +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_PERI0_BIAS_REG 0x00000b0//PLL_)PERI0 Bias Register +#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_PERI1_CTRL_REG 0x000000c0//PLL_PERI1 Control Register +#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28 +#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000) +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000) +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET 25 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK (0x02000000) +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE 0b0 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE 0b1 +#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000) +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000) +#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET 2 +#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK (0x0000001c) +#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_PERI1_LOCK_CTRL_REG 0x000000c4//PLL_PERI1 Lock Control Register +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_OFFSET 4 +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_PENDING 0b1 +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_OFFSET 0 +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_PERI1_PAT0_CTRL_REG 0x000000c8//PLL_PERI1 Pattern0 Control Register +#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_PERI1_PAT1_CTRL_REG 0x000000cc//PLL_PERI1 Pattern1 Control Register +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_PERI1_BIAS_REG 0x000000d0//PLL_PERI1 Bias Register +#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_GPU0_CTRL_REG 0x000000e0//PLL_GPU0 Control Register +#define PLL_GPU0_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_GPU0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_GPU0_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_GPU0_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_GPU0_CTRL_REG_LOCK_OFFSET 28 +#define PLL_GPU0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_GPU0_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_GPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20 +#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000) +#define PLL_GPU0_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_GPU0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_GPU0_LOCK_CTRL_REG 0x000000e4//PLL_GPU0 Lock Control Register +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_OFFSET 4 +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_PENDING 0b1 +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_OFFSET 0 +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_GPU0_PAT0_CTRL_REG 0x000000e8//PLL_GPU0 Pattern0 Control Register +#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_GPU0_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_GPU0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_GPU0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_GPU0_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_GPU0_PAT1_CTRL_REG 0x000000ec//PLL_GPU0 Pattern1 Control Register +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_GPU0_BIAS_REG 0x000000f0//PLL_GPU0 Bias Register +#define PLL_GPU0_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_GPU0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_VIDEO0_CTRL_REG 0x00000120//PLL_VIDEO0 Control Register +#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28 +#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000) +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000) +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1 +#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000) +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16 +#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000) +#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_VIDEO0_LOCK_CTRL_REG 0x00000124//PLL_VIDEO0 Lock Control Register +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_OFFSET 4 +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_PENDING 0b1 +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_OFFSET 0 +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_VIDEO0_PAT0_CTRL_REG \ + 0x00000128//PLL_VIDEO0 Pattern0 Control Register +#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_VIDEO0_PAT1_CTRL_REG \ + 0x0000012c//PLL_VIDEO0 Pattern1 Control Register +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_VIDEO0_BIAS_REG 0x00000130//PLL_VIDEO0 Bias Register +#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_VIDEO1_CTRL_REG 0x00000140//PLL_VIDEO1 Control Register +#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28 +#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000) +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000) +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1 +#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000) +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16 +#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000) +#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_VIDEO1_LOCK_CTRL_REG 0x00000144//PLL_VIDEO1 Lock Control Register +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_OFFSET 4 +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_PENDING 0b1 +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_OFFSET 0 +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_VIDEO1_PAT0_CTRL_REG \ + 0x00000148//PLL_VIDEO1 Pattern0 Control Register +#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_VIDEO1_PAT1_CTRL_REG \ + 0x0000014c//PLL_VIDEO1 Pattern1 Control Register +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_VIDEO1_BIAS_REG 0x00000150//PLL_VIDEO1 Bias Register +#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_VIDEO2_CTRL_REG 0x00000160//PLL_VIDEO2 Control Register +#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET 28 +#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000) +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000) +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1 +#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000) +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16 +#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000) +#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_VIDEO2_LOCK_CTRL_REG 0x00000164//PLL_VIDEO2 Lock Control Register +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_OFFSET 4 +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_PENDING 0b1 +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_OFFSET 0 +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_VIDEO2_PAT0_CTRL_REG \ + 0x00000168//PLL_VIDEO2 Pattern0 Control Register +#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_VIDEO2_PAT1_CTRL_REG \ + 0x0000016c//PLL_VIDEO2 Pattern1 Control Register +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_VIDEO2_BIAS_REG 0x00000170//PLL_VIDEO2 Bias Register +#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_VE0_CTRL_REG 0x00000220//PLL_VE0 Control Register +#define PLL_VE0_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_VE0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_VE0_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_VE0_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_VE0_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_VE0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_VE0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_VE0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_VE0_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_VE0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_VE0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_VE0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_VE0_CTRL_REG_LOCK_OFFSET 28 +#define PLL_VE0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_VE0_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_VE0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20 +#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000) +#define PLL_VE0_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_VE0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_VE0_LOCK_CTRL_REG 0x00000224//PLL_VE0 Lock Control Register +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_OFFSET 4 +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_PENDING 0b1 +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_OFFSET 0 +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_VE0_PAT0_CTRL_REG 0x00000228//PLL_VE0 Pattern0 Control Register +#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_VE0_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_VE0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_VE0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_VE0_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_VE0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_VE0_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_VE0_PAT1_CTRL_REG 0x0000022c//PLL_VE0 Pattern1 Control Register +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_VE0_BIAS_REG 0x00000230//PLL_VE0 Bias Register +#define PLL_VE0_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_VE0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_VE1_CTRL_REG 0x00000240//PLL_VE1 Control Register +#define PLL_VE1_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_VE1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_VE1_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_VE1_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_VE1_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_VE1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_VE1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_VE1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_VE1_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_VE1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_VE1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_VE1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_VE1_CTRL_REG_LOCK_OFFSET 28 +#define PLL_VE1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_VE1_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_VE1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20 +#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000) +#define PLL_VE1_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_VE1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_VE1_LOCK_CTRL_REG 0x00000244//PLL_VE1 Lock Control Register +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_OFFSET 4 +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_PENDING 0b1 +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_OFFSET 0 +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_VE1_PAT0_CTRL_REG 0x00000248//PLL_VE1 Pattern0 Control Register +#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_VE1_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_VE1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_VE1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_VE1_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_VE1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_VE1_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_VE1_PAT1_CTRL_REG 0x0000024c//PLL_VE1 Pattern1 Control Register +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_VE1_BIAS_REG 0x00000250//PLL_VE1 Bias Register +#define PLL_VE1_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_VE1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_AUDIO0_CTRL_REG 0x00000260//PLL_AUDIO0 Control Register +#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28 +#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 16 +#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x007f0000) +#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_AUDIO0_LOCK_CTRL_REG 0x00000264//PLL_AUDIO0 Lock Control Register +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_OFFSET 4 +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_PENDING 0b1 +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_OFFSET 0 +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_AUDIO0_PAT0_CTRL_REG \ + 0x00000268//PLL_AUDIO0 Pattern0 Control Register +#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_AUDIO0_PAT1_CTRL_REG \ + 0x0000026c//PLL_AUDIO0 Pattern1 Control Register +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_AUDIO0_BIAS_REG 0x00000270//PLL_AUDIO0 Bias Register +#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_AUDIO1_CTRL_REG 0x00000280//PLL_AUDIO1 Control Register +#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET 28 +#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET 20 +#define PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK (0x00700000) +#define PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET 16 +#define PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK (0x00070000) +#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_AUDIO1_LOCK_CTRL_REG 0x00000284//PLL_AUDIO1 Lock Control Register +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_OFFSET 4 +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_PENDING 0b1 +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_OFFSET 0 +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_AUDIO1_PAT0_CTRL_REG \ + 0x00000288//PLL_AUDIO1 Pattern0 Control Register +#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_AUDIO1_PAT1_CTRL_REG \ + 0x0000028c//PLL_AUDIO1 Pattern1 Control Register +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_AUDIO1_BIAS_REG 0x00000290//PLL_AUDIO1 Bias Register +#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_NPU_CTRL_REG 0x000002a0//PLL_NPU Control Register +#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_NPU_CTRL_REG_LOCK_OFFSET 28 +#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 +#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000) +#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0 +#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1 +#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20 +#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000) +#define PLL_NPU_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_NPU_LOCK_CTRL_REG 0x000002a4//PLL_NPU Lock Control Register +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_OFFSET 4 +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_PENDING 0b1 +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_OFFSET 0 +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_NPU_PAT0_CTRL_REG 0x000002a8//PLL_NPU Pattern0 Control Register +#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_NPU_PAT1_CTRL_REG 0x000002ac//PLL_NPU Pattern1 Control Register +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_NPU_BIAS_REG 0x000002b0//PLL_NPU Bias Register +#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define PLL_DE_CTRL_REG 0x000002e0//PLL_DE Control Register +#define PLL_DE_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_DE_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000) +#define PLL_DE_CTRL_REG_PLL_EN_DISABLE 0b0 +#define PLL_DE_CTRL_REG_PLL_EN_ENABLE 0b1 +#define PLL_DE_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_DE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000) +#define PLL_DE_CTRL_REG_PLL_LDO_EN_DISABLE 0b0 +#define PLL_DE_CTRL_REG_PLL_LDO_EN_ENABLE 0b1 +#define PLL_DE_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_DE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000) +#define PLL_DE_CTRL_REG_LOCK_ENABLE_DISABLE 0b0 +#define PLL_DE_CTRL_REG_LOCK_ENABLE_ENABLE 0b1 +#define PLL_DE_CTRL_REG_LOCK_OFFSET 28 +#define PLL_DE_CTRL_REG_LOCK_CLEAR_MASK (0x10000000) +#define PLL_DE_CTRL_REG_LOCK_UNLOCKED 0b0 +#define PLL_DE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE \ + 0b1 +#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27 +#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000) +#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0 +#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1 +#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26 +#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000) +#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0 +#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1 +#define PLL_DE_CTRL_REG_PLL_FREF_SEL_OFFSET 24 +#define PLL_DE_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000) +#define PLL_DE_CTRL_REG_PLL_FREF_SEL_HOSC 0b0 +#define PLL_DE_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1 +#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20 +#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000) +#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16 +#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000) +#define PLL_DE_CTRL_REG_PLL_N_OFFSET 8 +#define PLL_DE_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00) +#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6 +#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0) +#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00 +#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01 +#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10 +#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5 +#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020) +#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0 +#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1 +#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_OFFSET 1 +#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002) + +#define PLL_DE_LOCK_CTRL_REG 0x000002e4//PLL_DE Lock Control Register +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_OFFSET 4 +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_CLEAR_MASK (0x00000010) +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_NO_EFFECT 0b0 +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_PENDING 0b1 +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_OFFSET 0 +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_CLEAR_MASK (0x00000001) +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_DISABLE 0b0 +#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_ENABLE 0b1 + +#define PLL_DE_PAT0_CTRL_REG 0x000002e8//PLL_DE Pattern0 Control Register +#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31 +#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000) +#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29 +#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000) +#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00 +#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01 +#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10 +#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11 +#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20 +#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000) +#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19 +#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000) +#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0 +#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1 +#define PLL_DE_PAT0_CTRL_REG_FREQ_OFFSET 17 +#define PLL_DE_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000) +#define PLL_DE_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00 +#define PLL_DE_PAT0_CTRL_REG_FREQ_32KHZ 0b01 +#define PLL_DE_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10 +#define PLL_DE_PAT0_CTRL_REG_FREQ_33KHZ 0b11 +#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0 +#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff) + +#define PLL_DE_PAT1_CTRL_REG 0x000002ec//PLL_DE Pattern1 Control Register +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000) +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000) +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110 +#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111 +#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27 +#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000) +#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0 +#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1 +#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26 +#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000) +#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0 +#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1 +#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25 +#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000) +#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0 +#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1 +#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24 +#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000) +#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20 +#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000) +#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0 +#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff) + +#define PLL_DE_BIAS_REG 0x000002f0//PLL_DE Bias Register +#define PLL_DE_BIAS_REG_PLL_CP_OFFSET 16 +#define PLL_DE_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000) + +#define AHB_CLK_REG 0x00000500//AHB Clock Register +#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000) +#define AHB_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b00 +#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K 0b01 +#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10 +#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11 +#define AHB_CLK_REG_FACTOR_M_OFFSET 0 +#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define APB0_CLK_REG 0x00000510//APB0 Clock Register +#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000) +#define APB0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b00 +#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K 0b01 +#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10 +#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11 +#define APB0_CLK_REG_FACTOR_M_OFFSET 0 +#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define APB1_CLK_REG 0x00000518//APB1 Clock Register +#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000) +#define APB1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b00 +#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K 0b01 +#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10 +#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11 +#define APB1_CLK_REG_FACTOR_M_OFFSET 0 +#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define APB_UART_CLK_REG 0x00000538//APB_UART Clock Register +#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K 0b001 +#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010 +#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b011 +#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS 0b100 +#define APB_UART_CLK_REG_FACTOR_M_OFFSET 0 +#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define TRACE_CLK_REG 0x00000540//TRACE Clock Register +#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31 +#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK (0x80000000) +#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF 0b0 +#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON 0b1 +#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TRACE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K 0b001 +#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010 +#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011 +#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100 +#define TRACE_CLK_REG_FACTOR_M_OFFSET 0 +#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define GIC_CLK_REG 0x00000560//GIC Clock Register +#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31 +#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK (0x80000000) +#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF 0b0 +#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON 0b1 +#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define GIC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K 0b001 +#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010 +#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011 +#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100 +#define GIC_CLK_REG_FACTOR_M_OFFSET 0 +#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define CPU_PERI_CLK_REG 0x00000568//CPU_PERI Clock Register +#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_OFFSET 31 +#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLEAR_MASK (0x80000000) +#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_OFF 0b0 +#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_ON 0b1 +#define CPU_PERI_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define CPU_PERI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLK32K 0b001 +#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010 +#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011 +#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100 +#define CPU_PERI_CLK_REG_FACTOR_M_OFFSET 0 +#define CPU_PERI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define ITS0_BGR_REG 0x00000574//ITS0 Bus Gating Reset Register +#define ITS0_BGR_REG_ITS_PCIE0_RST_OFFSET 16 +#define ITS0_BGR_REG_ITS_PCIE0_RST_CLEAR_MASK (0x00010000) +#define ITS0_BGR_REG_ITS_PCIE0_RST_ASSERT 0b0 +#define ITS0_BGR_REG_ITS_PCIE0_RST_DE_ASSERT 0b1 +#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_OFFSET 1 +#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_CLEAR_MASK (0x00000002) +#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_MASK 0b0 +#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_PASS 0b1 + +#define NSI_CLK_REG 0x00000580//NSI Clock Register +#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET 31 +#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK (0x80000000) +#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF 0b0 +#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON 0b1 +#define NSI_CLK_REG_NSI_RST_OFFSET 30 +#define NSI_CLK_REG_NSI_RST_CLEAR_MASK (0x40000000) +#define NSI_CLK_REG_NSI_RST_ASSERT 0b0 +#define NSI_CLK_REG_NSI_RST_DE_ASSERT 0b1 +#define NSI_CLK_REG_NSI_DFS_EN_OFFSET 28 +#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK (0x10000000) +#define NSI_CLK_REG_NSI_DFS_EN_DISABLE 0b0 +#define NSI_CLK_REG_NSI_DFS_EN_ENABLE 0b1 +#define NSI_CLK_REG_NSI_UPD_OFFSET 27 +#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK (0x08000000) +#define NSI_CLK_REG_NSI_UPD_INVALID 0b0 +#define NSI_CLK_REG_NSI_UPD_VALID 0b1 +#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET 24 +#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK (0x07000000) +#define NSI_CLK_REG_NSI_CLK_SEL_SYS_CLK24M 0b000 +#define NSI_CLK_REG_NSI_CLK_SEL_DDRPLL 0b001 +#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_800M 0b010 +#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M 0b011 +#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M 0b100 +#define NSI_CLK_REG_NSI_CLK_SEL_DEPLL3X 0b101 +#define NSI_CLK_REG_NSI_DIV1_OFFSET 0 +#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK (0x0000001f) + +#define NSI_BGR_REG 0x00000584//NSI Bus Gating Reset Register +#define NSI_BGR_REG_NSI_CFG_RST_OFFSET 16 +#define NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK (0x00010000) +#define NSI_BGR_REG_NSI_CFG_RST_ASSERT 0b0 +#define NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT 0b1 +#define NSI_BGR_REG_NSI_CFG_GATING_OFFSET 0 +#define NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK (0x00000001) +#define NSI_BGR_REG_NSI_CFG_GATING_MASK 0b0 +#define NSI_BGR_REG_NSI_CFG_GATING_PASS 0b1 + +#define MBUS_CLK_REG 0x00000588//MBUS Clock Register +#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31 +#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK (0x80000000) +#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF 0b0 +#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON 0b1 +#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28 +#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK (0x10000000) +#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE 0b0 +#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE 0b1 +#define MBUS_CLK_REG_MBUS_UPD_OFFSET 27 +#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK (0x08000000) +#define MBUS_CLK_REG_MBUS_UPD_INVALID 0b0 +#define MBUS_CLK_REG_MBUS_UPD_VALID 0b1 +#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24 +#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK (0x07000000) +#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_CLK24M 0b000 +#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M 0b001 +#define MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL 0b010 +#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M 0b011 +#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M 0b100 +#define MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL 0b101 +#define MBUS_CLK_REG_MBUS_DIV1_OFFSET 0 +#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK (0x0000001f) + +#define IOMMU0_BGR_REG 0x0000058c//IOMMU0 Bus Gating Reset Register +#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_OFFSET 16 +#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_CLEAR_MASK (0x00010000) +#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_ASSERT 0b0 +#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_DE_ASSERT 0b1 +#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_OFFSET 2 +#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_CLEAR_MASK (0x00000004) +#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_MASK 0b0 +#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_PASS 0b1 +#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_OFFSET 1 +#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_CLEAR_MASK (0x00000002) +#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_MASK 0b0 +#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_PASS 0b1 +#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_OFFSET 0 +#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_CLEAR_MASK (0x00000001) +#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_MASK 0b0 +#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_PASS 0b1 + +#define MSI_LITE0_BGR_REG 0x00000594//MSI_LITE0 Bus Gating Reset Register +#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_OFFSET 17 +#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_CLEAR_MASK (0x00020000) +#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_ASSERT 0b0 +#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_DE_ASSERT 0b1 +#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_OFFSET 16 +#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_CLEAR_MASK (0x00010000) +#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_ASSERT 0b0 +#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_DE_ASSERT 0b1 +#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_OFFSET 0 +#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_CLEAR_MASK (0x00000001) +#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_MASK 0b0 +#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_PASS 0b1 + +#define MSI_LITE1_BGR_REG 0x0000059c//MSI_LITE1 Bus Gating Reset Register +#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_OFFSET 17 +#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_CLEAR_MASK (0x00020000) +#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_ASSERT 0b0 +#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_DE_ASSERT 0b1 +#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_OFFSET 16 +#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_CLEAR_MASK (0x00010000) +#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_ASSERT 0b0 +#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_DE_ASSERT 0b1 +#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_OFFSET 0 +#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_CLEAR_MASK (0x00000001) +#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_MASK 0b0 +#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_PASS 0b1 + +#define MSI_LITE2_BGR_REG 0x000005a4//MSI_LITE2 Bus Gating Reset Register +#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_OFFSET 17 +#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_CLEAR_MASK (0x00020000) +#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_ASSERT 0b0 +#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_DE_ASSERT 0b1 +#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_OFFSET 16 +#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_CLEAR_MASK (0x00010000) +#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_ASSERT 0b0 +#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_DE_ASSERT 0b1 +#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_OFFSET 0 +#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_CLEAR_MASK (0x00000001) +#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_MASK 0b0 +#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_PASS 0b1 + +#define IOMMU1_BGR_REG 0x000005b4//IOMMU1 Bus Gating Reset Register +#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_OFFSET 16 +#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_CLEAR_MASK (0x00010000) +#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_ASSERT 0b0 +#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_DE_ASSERT 0b1 +#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_OFFSET 2 +#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_CLEAR_MASK (0x00000004) +#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_MASK 0b0 +#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_PASS 0b1 +#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_OFFSET 1 +#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_CLEAR_MASK (0x00000002) +#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_MASK 0b0 +#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_PASS 0b1 +#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_OFFSET 0 +#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_CLEAR_MASK (0x00000001) +#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_MASK 0b0 +#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_PASS 0b1 + +#define AHB_MAT_CLK_GATING_REG 0x000005c0//AHB Master Clock Gating Register +#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_OFFSET 31 +#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_CLEAR_MASK (0x80000000) +#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0 +#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1 +#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_OFFSET 29 +#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_CLEAR_MASK (0x20000000) +#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0 +#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1 +#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28 +#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK (0x10000000) +#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_OFFSET 24 +#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_CLEAR_MASK (0x01000000) +#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_OFFSET 16 +#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_OFFSET 9 +#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_CLEAR_MASK \ + (0x00000200) +#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_OFFSET 8 +#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000100) +#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_OFFSET 7 +#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000080) +#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_OFFSET 6 +#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000040) +#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_OFFSET 5 +#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000020) +#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_OFFSET 4 +#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000010) +#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_OFFSET 3 +#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000008) +#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2 +#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000004) +#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_OFFSET 1 +#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000002) +#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_ENABLE 0b1 +#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_OFFSET 0 +#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000001) +#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_DISABLE 0b0 +#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_ENABLE 0b1 + +#define MBUS_MAT_CLK_GATING_REG 0x000005e0//MBUS Master Clock Gating Register +#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_OFFSET 31 +#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_CLEAR_MASK (0x80000000) +#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_OFFSET 30 +#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_CLEAR_MASK (0x40000000) +#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_OFFSET 29 +#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x20000000) +#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_OFFSET 28 +#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_CLEAR_MASK (0x10000000) +#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 24 +#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK (0x01000000) +#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 18 +#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00040000) +#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_OFFSET 16 +#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_OFFSET 14 +#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00004000) +#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_OFFSET 12 +#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00001000) +#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_OFFSET 11 +#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000800) +#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_OFFSET 1 +#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000002) +#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_ENABLE 0b1 +#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_OFFSET 0 +#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000001) +#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_DISABLE 0b0 +#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_ENABLE 0b1 + +#define MBUS_GATE_EN_REG 0x000005e4//MBUS Gate Enable Register +#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_OFFSET 18 +#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_CLEAR_MASK (0x00040000) +#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET 12 +#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK (0x00001000) +#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET 11 +#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK (0x00000800) +#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET 9 +#define MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK (0x00000200) +#define MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET 8 +#define MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK (0x00000100) +#define MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_NAND_MCLK_EN_OFFSET 5 +#define MBUS_GATE_EN_REG_NAND_MCLK_EN_CLEAR_MASK (0x00000020) +#define MBUS_GATE_EN_REG_NAND_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_NAND_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET 3 +#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK (0x00000008) +#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET 2 +#define MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK (0x00000004) +#define MBUS_GATE_EN_REG_CE_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG 0b1 +#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_OFFSET 1 +#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_CLEAR_MASK (0x00000002) +#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_PASS 0b1 +#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET 0 +#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK (0x00000001) +#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK 0b0 +#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS 0b1 + +#define DMA0_BGR_REG 0x00000704//DMA0 Bus Gating Reset Register +#define DMA0_BGR_REG_DMA0_RST_OFFSET 16 +#define DMA0_BGR_REG_DMA0_RST_CLEAR_MASK (0x00010000) +#define DMA0_BGR_REG_DMA0_RST_ASSERT 0b0 +#define DMA0_BGR_REG_DMA0_RST_DE_ASSERT 0b1 +#define DMA0_BGR_REG_DMA0_GATING_OFFSET 0 +#define DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK (0x00000001) +#define DMA0_BGR_REG_DMA0_GATING_MASK 0b0 +#define DMA0_BGR_REG_DMA0_GATING_PASS 0b1 + +#define DMA1_BGR_REG 0x0000070c//DMA1 Bus Gating Reset Register +#define DMA1_BGR_REG_DMA1_RST_OFFSET 16 +#define DMA1_BGR_REG_DMA1_RST_CLEAR_MASK (0x00010000) +#define DMA1_BGR_REG_DMA1_RST_ASSERT 0b0 +#define DMA1_BGR_REG_DMA1_RST_DE_ASSERT 0b1 +#define DMA1_BGR_REG_DMA1_GATING_OFFSET 0 +#define DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK (0x00000001) +#define DMA1_BGR_REG_DMA1_GATING_MASK 0b0 +#define DMA1_BGR_REG_DMA1_GATING_PASS 0b1 + +#define SPINLOCK_BGR_REG 0x00000724//SPINLOCK Bus Gating Reset Register +#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16 +#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK (0x00010000) +#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT 0b0 +#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT 0b1 +#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0 +#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK (0x00000001) +#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK 0b0 +#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS 0b1 + +#define MSGBOX0_BGR_REG 0x00000744//MSGBOX0 Bus Gating Reset Register +#define MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET 16 +#define MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK (0x00010000) +#define MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT 0b0 +#define MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT 0b1 +#define MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET 0 +#define MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK (0x00000001) +#define MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK 0b0 +#define MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS 0b1 + +#define PWM0_BGR_REG 0x00000784//PWM0 Bus Gating Reset Register +#define PWM0_BGR_REG_PWM0_RST_OFFSET 16 +#define PWM0_BGR_REG_PWM0_RST_CLEAR_MASK (0x00010000) +#define PWM0_BGR_REG_PWM0_RST_ASSERT 0b0 +#define PWM0_BGR_REG_PWM0_RST_DE_ASSERT 0b1 +#define PWM0_BGR_REG_PWM0_GATING_OFFSET 0 +#define PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK (0x00000001) +#define PWM0_BGR_REG_PWM0_GATING_MASK 0b0 +#define PWM0_BGR_REG_PWM0_GATING_PASS 0b1 + +#define PWM1_BGR_REG 0x0000078c//PWM1 Bus Gating Reset Register +#define PWM1_BGR_REG_PWM1_RST_OFFSET 16 +#define PWM1_BGR_REG_PWM1_RST_CLEAR_MASK (0x00010000) +#define PWM1_BGR_REG_PWM1_RST_ASSERT 0b0 +#define PWM1_BGR_REG_PWM1_RST_DE_ASSERT 0b1 +#define PWM1_BGR_REG_PWM1_GATING_OFFSET 0 +#define PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK (0x00000001) +#define PWM1_BGR_REG_PWM1_GATING_MASK 0b0 +#define PWM1_BGR_REG_PWM1_GATING_PASS 0b1 + +#define DBGSYS_BGR_REG 0x000007a4//DBGSYS Bus Gating Reset Register +#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16 +#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK (0x00010000) +#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT 0b0 +#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT 0b1 +#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0 +#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK (0x00000001) +#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK 0b0 +#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS 0b1 + +#define SYSDAP_BGR_REG 0x000007ac//SYSDAP Bus Gating Reset Register +#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16 +#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK (0x00010000) +#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT 0b0 +#define SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG 0b1 +#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0 +#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK (0x00000001) +#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK 0b0 +#define SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG 0b1 + +#define TIMER0_CLK0_CLK_REG 0x00000800//TIMER0_CLK0 Clock Register +#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_OFFSET 31 +#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK0_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK0_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK0_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK0_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK0_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK0_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK0_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK0_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK0_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK0_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK1_CLK_REG 0x00000804//TIMER0_CLK1 Clock Register +#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_OFFSET 31 +#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK1_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK1_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK1_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK1_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK1_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK1_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK1_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK1_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK1_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK1_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK2_CLK_REG 0x00000808//TIMER0_CLK2 Clock Register +#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_OFFSET 31 +#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK2_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK2_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK2_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK2_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK2_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK2_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK2_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK2_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK2_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK2_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK3_CLK_REG 0x0000080c//TIMER0_CLK3 Clock Register +#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_OFFSET 31 +#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK3_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK3_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK3_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK3_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK3_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK3_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK3_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK3_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK3_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK3_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK4_CLK_REG 0x00000810//TIMER0_CLK4 Clock Register +#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_OFFSET 31 +#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK4_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK4_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK4_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK4_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK4_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK4_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK4_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK4_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK4_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK4_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK5_CLK_REG 0x00000814//TIMER0_CLK5 Clock Register +#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_OFFSET 31 +#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK5_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK5_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK5_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK5_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK5_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK5_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK5_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK5_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK5_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK5_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK6_CLK_REG 0x00000818//TIMER0_CLK6 Clock Register +#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_OFFSET 31 +#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK6_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK6_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK6_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK6_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK6_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK6_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK6_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK6_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK6_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK6_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK7_CLK_REG 0x0000081c//TIMER0_CLK7 Clock Register +#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_OFFSET 31 +#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK7_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK7_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK7_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK7_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK7_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK7_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK7_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK7_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK7_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK7_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK8_CLK_REG 0x00000820//TIMER0_CLK8 Clock Register +#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_OFFSET 31 +#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK8_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK8_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK8_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK8_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK8_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK8_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK8_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK8_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK8_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK8_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_CLK9_CLK_REG 0x00000824//TIMER0_CLK9 Clock Register +#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_OFFSET 31 +#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_CLEAR_MASK (0x80000000) +#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_DISABLE 0b0 +#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_ENABLE 0b1 +#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001 +#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK32K 0b010 +#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_HOSC 0b100 +#define TIMER0_CLK9_CLK_REG_FACTOR_P_OFFSET 0 +#define TIMER0_CLK9_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007) +#define TIMER0_CLK9_CLK_REG_FACTOR_P__1 0b000 +#define TIMER0_CLK9_CLK_REG_FACTOR_P__2 0b001 +#define TIMER0_CLK9_CLK_REG_FACTOR_P__4 0b010 +#define TIMER0_CLK9_CLK_REG_FACTOR_P__8 0b011 +#define TIMER0_CLK9_CLK_REG_FACTOR_P__16 0b100 +#define TIMER0_CLK9_CLK_REG_FACTOR_P__32 0b101 +#define TIMER0_CLK9_CLK_REG_FACTOR_P__64 0b110 +#define TIMER0_CLK9_CLK_REG_FACTOR_P__128 0b111 + +#define TIMER0_BGR_REG 0x00000850//TIMER0 Bus Gating Reset Register +#define TIMER0_BGR_REG_TIMER0_RST_OFFSET 16 +#define TIMER0_BGR_REG_TIMER0_RST_CLEAR_MASK (0x00010000) +#define TIMER0_BGR_REG_TIMER0_RST_ASSERT 0b0 +#define TIMER0_BGR_REG_TIMER0_RST_DE_ASSERT 0b1 +#define TIMER0_BGR_REG_TIMER0_GATING_OFFSET 0 +#define TIMER0_BGR_REG_TIMER0_GATING_CLEAR_MASK (0x00000001) +#define TIMER0_BGR_REG_TIMER0_GATING_MASK 0b0 +#define TIMER0_BGR_REG_TIMER0_GATING_PASS 0b1 + +#define AVS_CLK_REG 0x00000880//AVS Clock Register +#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET 31 +#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK (0x80000000) +#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF 0b0 +#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON 0b1 +#define AVS_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define AVS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define AVS_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define AVS_CLK_REG_CLK_SRC_SEL_HOSC 0b001 + +#define DE0_CLK_REG 0x00000a00//DE0 Clock Register +#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31 +#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK (0x80000000) +#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON 0b1 +#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b000 +#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL4X 0b001 +#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010 +#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011 +#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b100 +#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101 +#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b110 +#define DE0_CLK_REG_FACTOR_M_OFFSET 0 +#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define DE0_BGR_REG 0x00000a04//DE0 Bus Gating Reset Register +#define DE0_BGR_REG_DE0_RST_OFFSET 16 +#define DE0_BGR_REG_DE0_RST_CLEAR_MASK (0x00010000) +#define DE0_BGR_REG_DE0_RST_ASSERT 0b0 +#define DE0_BGR_REG_DE0_RST_DE_ASSERT 0b1 +#define DE0_BGR_REG_DE0_GATING_OFFSET 0 +#define DE0_BGR_REG_DE0_GATING_CLEAR_MASK (0x00000001) +#define DE0_BGR_REG_DE0_GATING_MASK 0b0 +#define DE0_BGR_REG_DE0_GATING_PASS 0b1 + +#define DI_CLK_REG 0x00000a20//DI Clock Register +#define DI_CLK_REG_DI_CLK_GATING_OFFSET 31 +#define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK (0x80000000) +#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF 0b0 +#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON 0b1 +#define DI_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define DI_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b000 +#define DI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001 +#define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010 +#define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011 +#define DI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b100 +#define DI_CLK_REG_FACTOR_M_OFFSET 0 +#define DI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define DI_BGR_REG 0x00000a24//DI Bus Gating Reset Register +#define DI_BGR_REG_DI_RST_OFFSET 16 +#define DI_BGR_REG_DI_RST_CLEAR_MASK (0x00010000) +#define DI_BGR_REG_DI_RST_ASSERT 0b0 +#define DI_BGR_REG_DI_RST_DE_ASSERT 0b1 +#define DI_BGR_REG_DI_GATING_OFFSET 0 +#define DI_BGR_REG_DI_GATING_CLEAR_MASK (0x00000001) +#define DI_BGR_REG_DI_GATING_MASK 0b0 +#define DI_BGR_REG_DI_GATING_PASS 0b1 + +#define G2D_CLK_REG 0x00000a40//G2D Clock Register +#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31 +#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK (0x80000000) +#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0b0 +#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0b1 +#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000 +#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b010 +#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b011 +#define G2D_CLK_REG_FACTOR_M_OFFSET 0 +#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define G2D_BGR_REG 0x00000a44//G2D Bus Gating Reset Register +#define G2D_BGR_REG_G2D_RST_OFFSET 16 +#define G2D_BGR_REG_G2D_RST_CLEAR_MASK (0x00010000) +#define G2D_BGR_REG_G2D_RST_ASSERT 0b0 +#define G2D_BGR_REG_G2D_RST_DE_ASSERT 0b1 +#define G2D_BGR_REG_G2D_GATING_OFFSET 0 +#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK (0x00000001) +#define G2D_BGR_REG_G2D_GATING_MASK 0b0 +#define G2D_BGR_REG_G2D_GATING_PASS 0b1 + +#define EINK_CLK_REG 0x00000a60//EINK Clock Register +#define EINK_CLK_REG_EINK_CLK_GATING_OFFSET 31 +#define EINK_CLK_REG_EINK_CLK_GATING_CLEAR_MASK (0x80000000) +#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_OFF 0b0 +#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_ON 0b1 +#define EINK_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define EINK_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000 +#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define EINK_CLK_REG_FACTOR_M_OFFSET 0 +#define EINK_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define EINK_PANEL_CLK_REG 0x00000a64//EINK PANEL Clock Register +#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET 31 +#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK (0x80000000) +#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF 0b0 +#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON 0b1 +#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b001 +#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b010 +#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b011 +#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b100 +#define EINK_PANEL_CLK_REG_FACTOR_M_OFFSET 0 +#define EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define EINK_BGR_REG 0x00000a6c//EINK Bus Gating Reset Register +#define EINK_BGR_REG_EINK_RST_OFFSET 16 +#define EINK_BGR_REG_EINK_RST_CLEAR_MASK (0x00010000) +#define EINK_BGR_REG_EINK_RST_ASSERT 0b0 +#define EINK_BGR_REG_EINK_RST_DE_ASSERT 0b1 +#define EINK_BGR_REG_EINK_GATING_OFFSET 0 +#define EINK_BGR_REG_EINK_GATING_CLEAR_MASK (0x00000001) +#define EINK_BGR_REG_EINK_GATING_MASK 0b0 +#define EINK_BGR_REG_EINK_GATING_PASS 0b1 + +#define DE_SYS_BGR_REG 0x00000a74//DE_SYS Bus Gating Reset Register +#define DE_SYS_BGR_REG_DE_SYS_RST_OFFSET 16 +#define DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK (0x00010000) +#define DE_SYS_BGR_REG_DE_SYS_RST_ASSERT 0b0 +#define DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT 0b1 + +#define VE_ENC0_CLK_REG 0x00000a80//VE_ENC0 Clock Register +#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_OFFSET 31 +#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLEAR_MASK (0x80000000) +#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_ON 0b1 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE0PLL 0b000 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE1PLL 0b001 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b010 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b101 +#define VE_ENC0_CLK_REG_CLK_SRC_SEL_NPUPLL 0b110 +#define VE_ENC0_CLK_REG_FACTOR_M_OFFSET 0 +#define VE_ENC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define VE_DEC_CLK_REG 0x00000a88//VE_DEC Clock Register +#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_OFFSET 31 +#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLEAR_MASK (0x80000000) +#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_OFF 0b0 +#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_ON 0b1 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE1PLL 0b000 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE0PLL 0b001 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b010 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b101 +#define VE_DEC_CLK_REG_CLK_SRC_SEL_NPUPLL 0b110 +#define VE_DEC_CLK_REG_FACTOR_M_OFFSET 0 +#define VE_DEC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define VE_BGR_REG 0x00000a8c//VE Bus Gating Reset Register +#define VE_BGR_REG_VE_DEC_RST_OFFSET 18 +#define VE_BGR_REG_VE_DEC_RST_CLEAR_MASK (0x00040000) +#define VE_BGR_REG_VE_DEC_RST_ASSERT 0b0 +#define VE_BGR_REG_VE_DEC_RST_DE_ASSERT 0b1 +#define VE_BGR_REG_VE_ENC0_RST_OFFSET 16 +#define VE_BGR_REG_VE_ENC0_RST_CLEAR_MASK (0x00010000) +#define VE_BGR_REG_VE_ENC0_RST_ASSERT 0b0 +#define VE_BGR_REG_VE_ENC0_RST_DE_ASSERT 0b1 +#define VE_BGR_REG_VE_DEC_GATING_OFFSET 2 +#define VE_BGR_REG_VE_DEC_GATING_CLEAR_MASK (0x00000004) +#define VE_BGR_REG_VE_DEC_GATING_MASK 0b0 +#define VE_BGR_REG_VE_DEC_GATING_PASS 0b1 +#define VE_BGR_REG_VE_ENC0_GATING_OFFSET 0 +#define VE_BGR_REG_VE_ENC0_GATING_CLEAR_MASK (0x00000001) +#define VE_BGR_REG_VE_ENC0_GATING_MASK 0b0 +#define VE_BGR_REG_VE_ENC0_GATING_PASS 0b1 + +#define CE_CLK_REG 0x00000ac0//CE Clock Register +#define CE_CLK_REG_CE_CLK_GATING_OFFSET 31 +#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK (0x80000000) +#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF 0b0 +#define CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG 0b1 +#define CE_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define CE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define CE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010 +#define CE_CLK_REG_FACTOR_M_OFFSET 0 +#define CE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define CE_BGR_REG 0x00000ac4//CE Bus Gating Reset Register +#define CE_BGR_REG_CE_SYS_RST_OFFSET 17 +#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK (0x00020000) +#define CE_BGR_REG_CE_SYS_RST_ASSERT 0b0 +#define CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG 0b1 +#define CE_BGR_REG_CE_RST_OFFSET 16 +#define CE_BGR_REG_CE_RST_CLEAR_MASK (0x00010000) +#define CE_BGR_REG_CE_RST_ASSERT 0b0 +#define CE_BGR_REG_CE_RST_SECURE_DEBUG 0b1 +#define CE_BGR_REG_CE_SYS_GATING_OFFSET 1 +#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK (0x00000002) +#define CE_BGR_REG_CE_SYS_GATING_MASK 0b0 +#define CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG 0b1 +#define CE_BGR_REG_CE_GATING_OFFSET 0 +#define CE_BGR_REG_CE_GATING_CLEAR_MASK (0x00000001) +#define CE_BGR_REG_CE_GATING_MASK 0b0 +#define CE_BGR_REG_CE_GATING_SECURE_DEBUG 0b1 + +#define NPU_CLK_REG 0x00000b00//NPU) Clock Register +#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31 +#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK (0x80000000) +#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF 0b0 +#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON 0b1 +#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL 0b000 +#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001 +#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010 +#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011 +#define NPU_CLK_REG_CLK_SRC_SEL_VE0PLL 0b100 +#define NPU_CLK_REG_CLK_SRC_SEL_VE1PLL 0b101 +#define NPU_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b110 +#define NPU_CLK_REG_FACTOR_M_OFFSET 0 +#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define NPU_BGR_REG 0x00000b04//NPU) Bus Gating Reset Register +#define NPU_BGR_REG_NPU_SRAM_RST_OFFSET 19 +#define NPU_BGR_REG_NPU_SRAM_RST_CLEAR_MASK (0x00080000) +#define NPU_BGR_REG_NPU_SRAM_RST_ASSERT 0b0 +#define NPU_BGR_REG_NPU_SRAM_RST_DE_ASSERT 0b1 +#define NPU_BGR_REG_NPU_AHB_RST_OFFSET 18 +#define NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK (0x00040000) +#define NPU_BGR_REG_NPU_AHB_RST_ASSERT 0b0 +#define NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT 0b1 +#define NPU_BGR_REG_NPU_AXI_RST_OFFSET 17 +#define NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK (0x00020000) +#define NPU_BGR_REG_NPU_AXI_RST_ASSERT 0b0 +#define NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT 0b1 +#define NPU_BGR_REG_NPU_CORE_RST_OFFSET 16 +#define NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK (0x00010000) +#define NPU_BGR_REG_NPU_CORE_RST_ASSERT 0b0 +#define NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT 0b1 +#define NPU_BGR_REG_NPU_GATING_OFFSET 0 +#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK (0x00000001) +#define NPU_BGR_REG_NPU_GATING_MASK 0b0 +#define NPU_BGR_REG_NPU_GATING_PASS 0b1 + +#define DRAM0_CLK_REG 0x00000c00//DRAM0 Clock Register +#define DRAM0_CLK_REG_DRAM0_CLK_GATING_OFFSET 31 +#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLEAR_MASK (0x80000000) +#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_ON 0b1 +#define DRAM0_CLK_REG_DRAM0_UPD_OFFSET 27 +#define DRAM0_CLK_REG_DRAM0_UPD_CLEAR_MASK (0x08000000) +#define DRAM0_CLK_REG_DRAM0_UPD_INVALID 0b0 +#define DRAM0_CLK_REG_DRAM0_UPD_VALID 0b1 +#define DRAM0_CLK_REG_DRAM0_CLK_SEL_OFFSET 24 +#define DRAM0_CLK_REG_DRAM0_CLK_SEL_CLEAR_MASK (0x07000000) +#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DDRPLL 0b000 +#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_800M 0b001 +#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_600M 0b010 +#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DEPLL3X 0b011 +#define DRAM0_CLK_REG_DRAM0_CLK_SEL_NPUPLL 0b100 +#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_OFFSET 16 +#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_CLEAR_MASK (0x00010000) +#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_FROM_PHY 0b0 +#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_DRAM0_CLK_8 0b1 +#define DRAM0_CLK_REG_DRAM0_DIV1_OFFSET 0 +#define DRAM0_CLK_REG_DRAM0_DIV1_CLEAR_MASK (0x0000001f) + +#define DRAM0_BGR_REG 0x00000c0c//DRAM0 Bus Gating Reset Register +#define DRAM0_BGR_REG_DRAM0_RST_OFFSET 16 +#define DRAM0_BGR_REG_DRAM0_RST_CLEAR_MASK (0x00010000) +#define DRAM0_BGR_REG_DRAM0_RST_ASSERT 0b0 +#define DRAM0_BGR_REG_DRAM0_RST_DE_ASSERT 0b1 +#define DRAM0_BGR_REG_DRAM0_GATING_OFFSET 0 +#define DRAM0_BGR_REG_DRAM0_GATING_CLEAR_MASK (0x00000001) +#define DRAM0_BGR_REG_DRAM0_GATING_MASK 0b0 +#define DRAM0_BGR_REG_DRAM0_GATING_PASS 0b1 + +#define NAND0_CLK0_CLK_REG 0x00000c80//NAND0 CLK0 Clock Register +#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET 31 +#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK (0x80000000) +#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON 0b1 +#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010 +#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011 +#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100 +#define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET 0 +#define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define NAND0_CLK1_CLK_REG 0x00000c84//NAND0 CLK1 Clock Register +#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31 +#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK (0x80000000) +#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON 0b1 +#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010 +#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011 +#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100 +#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0 +#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define NAND0_BGR_REG 0x00000c8c//NAND0 Bus Gating Reset Register +#define NAND0_BGR_REG_NAND0_RST_OFFSET 16 +#define NAND0_BGR_REG_NAND0_RST_CLEAR_MASK (0x00010000) +#define NAND0_BGR_REG_NAND0_RST_ASSERT 0b0 +#define NAND0_BGR_REG_NAND0_RST_DE_ASSERT 0b1 +#define NAND0_BGR_REG_NAND0_GATING_OFFSET 0 +#define NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK (0x00000001) +#define NAND0_BGR_REG_NAND0_GATING_MASK 0b0 +#define NAND0_BGR_REG_NAND0_GATING_PASS 0b1 + +#define SMHC0_CLK_REG 0x00000d00//SMHC0 Clock Register +#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31 +#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK (0x80000000) +#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0b1 +#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010 +#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011 +#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100 +#define SMHC0_CLK_REG_FACTOR_N_OFFSET 8 +#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SMHC0_CLK_REG_FACTOR_M_OFFSET 0 +#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SMHC0_BGR_REG 0x00000d0c//SMHC0 Bus Gating Reset Register +#define SMHC0_BGR_REG_SMHC0_RST_OFFSET 16 +#define SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK (0x00010000) +#define SMHC0_BGR_REG_SMHC0_RST_ASSERT 0b0 +#define SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT 0b1 +#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET 0 +#define SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK (0x00000001) +#define SMHC0_BGR_REG_SMHC0_GATING_MASK 0b0 +#define SMHC0_BGR_REG_SMHC0_GATING_PASS 0b1 + +#define SMHC1_CLK_REG 0x00000d10//SMHC1 Clock Register +#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31 +#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK (0x80000000) +#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0b1 +#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010 +#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011 +#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100 +#define SMHC1_CLK_REG_FACTOR_N_OFFSET 8 +#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SMHC1_CLK_REG_FACTOR_M_OFFSET 0 +#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SMHC1_BGR_REG 0x00000d1c//SMHC1 Bus Gating Reset Register +#define SMHC1_BGR_REG_SMHC1_RST_OFFSET 16 +#define SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK (0x00010000) +#define SMHC1_BGR_REG_SMHC1_RST_ASSERT 0b0 +#define SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT 0b1 +#define SMHC1_BGR_REG_SMHC1_GATING_OFFSET 0 +#define SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK (0x00000001) +#define SMHC1_BGR_REG_SMHC1_GATING_MASK 0b0 +#define SMHC1_BGR_REG_SMHC1_GATING_PASS 0b1 + +#define SMHC2_CLK_REG 0x00000d20//SMHC2 Clock Register +#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31 +#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK (0x80000000) +#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0b1 +#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001 +#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010 +#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011 +#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100 +#define SMHC2_CLK_REG_FACTOR_N_OFFSET 8 +#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SMHC2_CLK_REG_FACTOR_M_OFFSET 0 +#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SMHC2_BGR_REG 0x00000d2c//SMHC2 Bus Gating Reset Register +#define SMHC2_BGR_REG_SMHC2_RST_OFFSET 16 +#define SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK (0x00010000) +#define SMHC2_BGR_REG_SMHC2_RST_ASSERT 0b0 +#define SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT 0b1 +#define SMHC2_BGR_REG_SMHC2_GATING_OFFSET 0 +#define SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK (0x00000001) +#define SMHC2_BGR_REG_SMHC2_GATING_MASK 0b0 +#define SMHC2_BGR_REG_SMHC2_GATING_PASS 0b1 + +#define SMHC3_CLK_REG 0x00000d30//SMHC3 Clock Register +#define SMHC3_CLK_REG_SMHC3_CLK_GATING_OFFSET 31 +#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLEAR_MASK (0x80000000) +#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_ON 0b1 +#define SMHC3_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SMHC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SMHC3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001 +#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010 +#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011 +#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100 +#define SMHC3_CLK_REG_FACTOR_N_OFFSET 8 +#define SMHC3_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SMHC3_CLK_REG_FACTOR_M_OFFSET 0 +#define SMHC3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SMHC3_BGR_REG 0x00000d3c//SMHC3 Bus Gating Reset Register +#define SMHC3_BGR_REG_SMHC3_RST_OFFSET 16 +#define SMHC3_BGR_REG_SMHC3_RST_CLEAR_MASK (0x00010000) +#define SMHC3_BGR_REG_SMHC3_RST_ASSERT 0b0 +#define SMHC3_BGR_REG_SMHC3_RST_DE_ASSERT 0b1 +#define SMHC3_BGR_REG_SMHC3_GATING_OFFSET 0 +#define SMHC3_BGR_REG_SMHC3_GATING_CLEAR_MASK (0x00000001) +#define SMHC3_BGR_REG_SMHC3_GATING_MASK 0b0 +#define SMHC3_BGR_REG_SMHC3_GATING_PASS 0b1 + +#define UFS_AXI_CLK_REG 0x00000d80//UFS_AXI Clock Register +#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_OFFSET 31 +#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLEAR_MASK (0x80000000) +#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_OFF 0b0 +#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_ON 0b1 +#define UFS_AXI_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define UFS_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000 +#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001 +#define UFS_AXI_CLK_REG_FACTOR_M_OFFSET 0 +#define UFS_AXI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define UFS_CFG_CLK_REG 0x00000d84//UFS_CFG Clock Register +#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_OFFSET 31 +#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLEAR_MASK (0x80000000) +#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_OFF 0b0 +#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_ON 0b1 +#define UFS_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define UFS_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define UFS_CFG_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000 +#define UFS_CFG_CLK_REG_CLK_SRC_SEL_HOSC 0b001 +#define UFS_CFG_CLK_REG_FACTOR_M_OFFSET 0 +#define UFS_CFG_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define UFS_BGR_REG 0x00000d8c//UFS Bus Gating Reset Register +#define UFS_BGR_REG_UFS_CORE_RST_OFFSET 19 +#define UFS_BGR_REG_UFS_CORE_RST_CLEAR_MASK (0x00080000) +#define UFS_BGR_REG_UFS_CORE_RST_ASSERT 0b0 +#define UFS_BGR_REG_UFS_CORE_RST_DE_ASSERT 0b1 +#define UFS_BGR_REG_UFS_PHY_RST_OFFSET 18 +#define UFS_BGR_REG_UFS_PHY_RST_CLEAR_MASK (0x00040000) +#define UFS_BGR_REG_UFS_PHY_RST_ASSERT 0b0 +#define UFS_BGR_REG_UFS_PHY_RST_DE_ASSERT 0b1 +#define UFS_BGR_REG_UFS_AXI_RST_OFFSET 17 +#define UFS_BGR_REG_UFS_AXI_RST_CLEAR_MASK (0x00020000) +#define UFS_BGR_REG_UFS_AXI_RST_ASSERT 0b0 +#define UFS_BGR_REG_UFS_AXI_RST_DE_ASSERT 0b1 +#define UFS_BGR_REG_UFS_RST_OFFSET 16 +#define UFS_BGR_REG_UFS_RST_CLEAR_MASK (0x00010000) +#define UFS_BGR_REG_UFS_RST_ASSERT 0b0 +#define UFS_BGR_REG_UFS_RST_DE_ASSERT 0b1 +#define UFS_BGR_REG_UFS_GATING_OFFSET 0 +#define UFS_BGR_REG_UFS_GATING_CLEAR_MASK (0x00000001) +#define UFS_BGR_REG_UFS_GATING_MASK 0b0 +#define UFS_BGR_REG_UFS_GATING_PASS 0b1 + +#define UFS_REF_CLK_EN_REG 0x00000d90//UFS Reference Clock Enable Register +#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_OFFSET 0 +#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_CLEAR_MASK (0x00000001) + +#define UART0_BGR_REG 0x00000e00//UART0 Bus Gating Reset Register +#define UART0_BGR_REG_UART0_RST_OFFSET 16 +#define UART0_BGR_REG_UART0_RST_CLEAR_MASK (0x00010000) +#define UART0_BGR_REG_UART0_RST_ASSERT 0b0 +#define UART0_BGR_REG_UART0_RST_DE_ASSERT 0b1 +#define UART0_BGR_REG_UART0_GATING_OFFSET 0 +#define UART0_BGR_REG_UART0_GATING_CLEAR_MASK (0x00000001) +#define UART0_BGR_REG_UART0_GATING_MASK 0b0 +#define UART0_BGR_REG_UART0_GATING_PASS 0b1 + +#define UART1_BGR_REG 0x00000e04//UART1 Bus Gating Reset Register +#define UART1_BGR_REG_UART1_RST_OFFSET 16 +#define UART1_BGR_REG_UART1_RST_CLEAR_MASK (0x00010000) +#define UART1_BGR_REG_UART1_RST_ASSERT 0b0 +#define UART1_BGR_REG_UART1_RST_DE_ASSERT 0b1 +#define UART1_BGR_REG_UART1_GATING_OFFSET 0 +#define UART1_BGR_REG_UART1_GATING_CLEAR_MASK (0x00000001) +#define UART1_BGR_REG_UART1_GATING_MASK 0b0 +#define UART1_BGR_REG_UART1_GATING_PASS 0b1 + +#define UART2_BGR_REG 0x00000e08//UART2 Bus Gating Reset Register +#define UART2_BGR_REG_UART2_RST_OFFSET 16 +#define UART2_BGR_REG_UART2_RST_CLEAR_MASK (0x00010000) +#define UART2_BGR_REG_UART2_RST_ASSERT 0b0 +#define UART2_BGR_REG_UART2_RST_DE_ASSERT 0b1 +#define UART2_BGR_REG_UART2_GATING_OFFSET 0 +#define UART2_BGR_REG_UART2_GATING_CLEAR_MASK (0x00000001) +#define UART2_BGR_REG_UART2_GATING_MASK 0b0 +#define UART2_BGR_REG_UART2_GATING_PASS 0b1 + +#define UART3_BGR_REG 0x00000e0c//UART3 Bus Gating Reset Register +#define UART3_BGR_REG_UART3_RST_OFFSET 16 +#define UART3_BGR_REG_UART3_RST_CLEAR_MASK (0x00010000) +#define UART3_BGR_REG_UART3_RST_ASSERT 0b0 +#define UART3_BGR_REG_UART3_RST_DE_ASSERT 0b1 +#define UART3_BGR_REG_UART3_GATING_OFFSET 0 +#define UART3_BGR_REG_UART3_GATING_CLEAR_MASK (0x00000001) +#define UART3_BGR_REG_UART3_GATING_MASK 0b0 +#define UART3_BGR_REG_UART3_GATING_PASS 0b1 + +#define UART4_BGR_REG 0x00000e10//UART4 Bus Gating Reset Register +#define UART4_BGR_REG_UART4_RST_OFFSET 16 +#define UART4_BGR_REG_UART4_RST_CLEAR_MASK (0x00010000) +#define UART4_BGR_REG_UART4_RST_ASSERT 0b0 +#define UART4_BGR_REG_UART4_RST_DE_ASSERT 0b1 +#define UART4_BGR_REG_UART4_GATING_OFFSET 0 +#define UART4_BGR_REG_UART4_GATING_CLEAR_MASK (0x00000001) +#define UART4_BGR_REG_UART4_GATING_MASK 0b0 +#define UART4_BGR_REG_UART4_GATING_PASS 0b1 + +#define UART5_BGR_REG 0x00000e14//UART5 Bus Gating Reset Register +#define UART5_BGR_REG_UART5_RST_OFFSET 16 +#define UART5_BGR_REG_UART5_RST_CLEAR_MASK (0x00010000) +#define UART5_BGR_REG_UART5_RST_ASSERT 0b0 +#define UART5_BGR_REG_UART5_RST_DE_ASSERT 0b1 +#define UART5_BGR_REG_UART5_GATING_OFFSET 0 +#define UART5_BGR_REG_UART5_GATING_CLEAR_MASK (0x00000001) +#define UART5_BGR_REG_UART5_GATING_MASK 0b0 +#define UART5_BGR_REG_UART5_GATING_PASS 0b1 + +#define UART6_BGR_REG 0x00000e18//UART6 Bus Gating Reset Register +#define UART6_BGR_REG_UART6_RST_OFFSET 16 +#define UART6_BGR_REG_UART6_RST_CLEAR_MASK (0x00010000) +#define UART6_BGR_REG_UART6_RST_ASSERT 0b0 +#define UART6_BGR_REG_UART6_RST_DE_ASSERT 0b1 +#define UART6_BGR_REG_UART6_GATING_OFFSET 0 +#define UART6_BGR_REG_UART6_GATING_CLEAR_MASK (0x00000001) +#define UART6_BGR_REG_UART6_GATING_MASK 0b0 +#define UART6_BGR_REG_UART6_GATING_PASS 0b1 + +#define TWI0_BGR_REG 0x00000e80//TWI0 Bus Gating Reset Register +#define TWI0_BGR_REG_TWI0_RST_OFFSET 16 +#define TWI0_BGR_REG_TWI0_RST_CLEAR_MASK (0x00010000) +#define TWI0_BGR_REG_TWI0_RST_ASSERT 0b0 +#define TWI0_BGR_REG_TWI0_RST_DE_ASSERT 0b1 +#define TWI0_BGR_REG_TWI0_GATING_OFFSET 0 +#define TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK (0x00000001) +#define TWI0_BGR_REG_TWI0_GATING_MASK 0b0 +#define TWI0_BGR_REG_TWI0_GATING_PASS 0b1 + +#define TWI1_BGR_REG 0x00000e84//TWI1 Bus Gating Reset Register +#define TWI1_BGR_REG_TWI1_RST_OFFSET 16 +#define TWI1_BGR_REG_TWI1_RST_CLEAR_MASK (0x00010000) +#define TWI1_BGR_REG_TWI1_RST_ASSERT 0b0 +#define TWI1_BGR_REG_TWI1_RST_DE_ASSERT 0b1 +#define TWI1_BGR_REG_TWI1_GATING_OFFSET 0 +#define TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK (0x00000001) +#define TWI1_BGR_REG_TWI1_GATING_MASK 0b0 +#define TWI1_BGR_REG_TWI1_GATING_PASS 0b1 + +#define TWI2_BGR_REG 0x00000e88//TWI2 Bus Gating Reset Register +#define TWI2_BGR_REG_TWI2_RST_OFFSET 16 +#define TWI2_BGR_REG_TWI2_RST_CLEAR_MASK (0x00010000) +#define TWI2_BGR_REG_TWI2_RST_ASSERT 0b0 +#define TWI2_BGR_REG_TWI2_RST_DE_ASSERT 0b1 +#define TWI2_BGR_REG_TWI2_GATING_OFFSET 0 +#define TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK (0x00000001) +#define TWI2_BGR_REG_TWI2_GATING_MASK 0b0 +#define TWI2_BGR_REG_TWI2_GATING_PASS 0b1 + +#define TWI3_BGR_REG 0x00000e8c//TWI3 Bus Gating Reset Register +#define TWI3_BGR_REG_TWI3_RST_OFFSET 16 +#define TWI3_BGR_REG_TWI3_RST_CLEAR_MASK (0x00010000) +#define TWI3_BGR_REG_TWI3_RST_ASSERT 0b0 +#define TWI3_BGR_REG_TWI3_RST_DE_ASSERT 0b1 +#define TWI3_BGR_REG_TWI3_GATING_OFFSET 0 +#define TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK (0x00000001) +#define TWI3_BGR_REG_TWI3_GATING_MASK 0b0 +#define TWI3_BGR_REG_TWI3_GATING_PASS 0b1 + +#define TWI4_BGR_REG 0x00000e90//TWI4 Bus Gating Reset Register +#define TWI4_BGR_REG_TWI4_RST_OFFSET 16 +#define TWI4_BGR_REG_TWI4_RST_CLEAR_MASK (0x00010000) +#define TWI4_BGR_REG_TWI4_RST_ASSERT 0b0 +#define TWI4_BGR_REG_TWI4_RST_DE_ASSERT 0b1 +#define TWI4_BGR_REG_TWI4_GATING_OFFSET 0 +#define TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK (0x00000001) +#define TWI4_BGR_REG_TWI4_GATING_MASK 0b0 +#define TWI4_BGR_REG_TWI4_GATING_PASS 0b1 + +#define TWI5_BGR_REG 0x00000e94//TWI5 Bus Gating Reset Register +#define TWI5_BGR_REG_TWI5_RST_OFFSET 16 +#define TWI5_BGR_REG_TWI5_RST_CLEAR_MASK (0x00010000) +#define TWI5_BGR_REG_TWI5_RST_ASSERT 0b0 +#define TWI5_BGR_REG_TWI5_RST_DE_ASSERT 0b1 +#define TWI5_BGR_REG_TWI5_GATING_OFFSET 0 +#define TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK (0x00000001) +#define TWI5_BGR_REG_TWI5_GATING_MASK 0b0 +#define TWI5_BGR_REG_TWI5_GATING_PASS 0b1 + +#define TWI6_BGR_REG 0x00000e98//TWI6 Bus Gating Reset Register +#define TWI6_BGR_REG_TWI6_RST_OFFSET 16 +#define TWI6_BGR_REG_TWI6_RST_CLEAR_MASK (0x00010000) +#define TWI6_BGR_REG_TWI6_RST_ASSERT 0b0 +#define TWI6_BGR_REG_TWI6_RST_DE_ASSERT 0b1 +#define TWI6_BGR_REG_TWI6_GATING_OFFSET 0 +#define TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK (0x00000001) +#define TWI6_BGR_REG_TWI6_GATING_MASK 0b0 +#define TWI6_BGR_REG_TWI6_GATING_PASS 0b1 + +#define TWI7_BGR_REG 0x00000e9c//TWI7 Bus Gating Reset Register +#define TWI7_BGR_REG_TWI7_RST_OFFSET 16 +#define TWI7_BGR_REG_TWI7_RST_CLEAR_MASK (0x00010000) +#define TWI7_BGR_REG_TWI7_RST_ASSERT 0b0 +#define TWI7_BGR_REG_TWI7_RST_DE_ASSERT 0b1 +#define TWI7_BGR_REG_TWI7_GATING_OFFSET 0 +#define TWI7_BGR_REG_TWI7_GATING_CLEAR_MASK (0x00000001) +#define TWI7_BGR_REG_TWI7_GATING_MASK 0b0 +#define TWI7_BGR_REG_TWI7_GATING_PASS 0b1 + +#define TWI8_BGR_REG 0x00000ea0//TWI8 Bus Gating Reset Register +#define TWI8_BGR_REG_TWI8_RST_OFFSET 16 +#define TWI8_BGR_REG_TWI8_RST_CLEAR_MASK (0x00010000) +#define TWI8_BGR_REG_TWI8_RST_ASSERT 0b0 +#define TWI8_BGR_REG_TWI8_RST_DE_ASSERT 0b1 +#define TWI8_BGR_REG_TWI8_GATING_OFFSET 0 +#define TWI8_BGR_REG_TWI8_GATING_CLEAR_MASK (0x00000001) +#define TWI8_BGR_REG_TWI8_GATING_MASK 0b0 +#define TWI8_BGR_REG_TWI8_GATING_PASS 0b1 + +#define TWI9_BGR_REG 0x00000ea4//TWI9 Bus Gating Reset Register +#define TWI9_BGR_REG_TWI9_RST_OFFSET 16 +#define TWI9_BGR_REG_TWI9_RST_CLEAR_MASK (0x00010000) +#define TWI9_BGR_REG_TWI9_RST_ASSERT 0b0 +#define TWI9_BGR_REG_TWI9_RST_DE_ASSERT 0b1 +#define TWI9_BGR_REG_TWI9_GATING_OFFSET 0 +#define TWI9_BGR_REG_TWI9_GATING_CLEAR_MASK (0x00000001) +#define TWI9_BGR_REG_TWI9_GATING_MASK 0b0 +#define TWI9_BGR_REG_TWI9_GATING_PASS 0b1 + +#define TWI10_BGR_REG 0x00000ea8//TWI10 Bus Gating Reset Register +#define TWI10_BGR_REG_TWI10_RST_OFFSET 16 +#define TWI10_BGR_REG_TWI10_RST_CLEAR_MASK (0x00010000) +#define TWI10_BGR_REG_TWI10_RST_ASSERT 0b0 +#define TWI10_BGR_REG_TWI10_RST_DE_ASSERT 0b1 +#define TWI10_BGR_REG_TWI10_GATING_OFFSET 0 +#define TWI10_BGR_REG_TWI10_GATING_CLEAR_MASK (0x00000001) +#define TWI10_BGR_REG_TWI10_GATING_MASK 0b0 +#define TWI10_BGR_REG_TWI10_GATING_PASS 0b1 + +#define TWI11_BGR_REG 0x00000eac//TWI11 Bus Gating Reset Register +#define TWI11_BGR_REG_TWI11_RST_OFFSET 16 +#define TWI11_BGR_REG_TWI11_RST_CLEAR_MASK (0x00010000) +#define TWI11_BGR_REG_TWI11_RST_ASSERT 0b0 +#define TWI11_BGR_REG_TWI11_RST_DE_ASSERT 0b1 +#define TWI11_BGR_REG_TWI11_GATING_OFFSET 0 +#define TWI11_BGR_REG_TWI11_GATING_CLEAR_MASK (0x00000001) +#define TWI11_BGR_REG_TWI11_GATING_MASK 0b0 +#define TWI11_BGR_REG_TWI11_GATING_PASS 0b1 + +#define TWI12_BGR_REG 0x00000eb0//TWI12 Bus Gating Reset Register +#define TWI12_BGR_REG_TWI12_RST_OFFSET 16 +#define TWI12_BGR_REG_TWI12_RST_CLEAR_MASK (0x00010000) +#define TWI12_BGR_REG_TWI12_RST_ASSERT 0b0 +#define TWI12_BGR_REG_TWI12_RST_DE_ASSERT 0b1 +#define TWI12_BGR_REG_TWI12_GATING_OFFSET 0 +#define TWI12_BGR_REG_TWI12_GATING_CLEAR_MASK (0x00000001) +#define TWI12_BGR_REG_TWI12_GATING_MASK 0b0 +#define TWI12_BGR_REG_TWI12_GATING_PASS 0b1 + +#define SPI0_CLK_REG 0x00000f00//SPI0 Clock Register +#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31 +#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010 +#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011 +#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100 +#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101 +#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110 +#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC 0b111 +#define SPI0_CLK_REG_FACTOR_N_OFFSET 8 +#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SPI0_CLK_REG_FACTOR_M_OFFSET 0 +#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPI0_BGR_REG 0x00000f04//SPI0 Bus Gating Reset Register +#define SPI0_BGR_REG_SPI0_RST_OFFSET 16 +#define SPI0_BGR_REG_SPI0_RST_CLEAR_MASK (0x00010000) +#define SPI0_BGR_REG_SPI0_RST_ASSERT 0b0 +#define SPI0_BGR_REG_SPI0_RST_DE_ASSERT 0b1 +#define SPI0_BGR_REG_SPI0_GATING_OFFSET 0 +#define SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK (0x00000001) +#define SPI0_BGR_REG_SPI0_GATING_MASK 0b0 +#define SPI0_BGR_REG_SPI0_GATING_PASS 0b1 + +#define SPI1_CLK_REG 0x00000f08//SPI1 Clock Register +#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31 +#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010 +#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011 +#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100 +#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101 +#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110 +#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC 0b111 +#define SPI1_CLK_REG_FACTOR_N_OFFSET 8 +#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SPI1_CLK_REG_FACTOR_M_OFFSET 0 +#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPI1_BGR_REG 0x00000f0c//SPI1 Bus Gating Reset Register +#define SPI1_BGR_REG_SPI1_RST_OFFSET 16 +#define SPI1_BGR_REG_SPI1_RST_CLEAR_MASK (0x00010000) +#define SPI1_BGR_REG_SPI1_RST_ASSERT 0b0 +#define SPI1_BGR_REG_SPI1_RST_DE_ASSERT 0b1 +#define SPI1_BGR_REG_SPI1_GATING_OFFSET 0 +#define SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK (0x00000001) +#define SPI1_BGR_REG_SPI1_GATING_MASK 0b0 +#define SPI1_BGR_REG_SPI1_GATING_PASS 0b1 + +#define SPI2_CLK_REG 0x00000f10//SPI2 Clock Register +#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31 +#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010 +#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011 +#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100 +#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101 +#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110 +#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC 0b111 +#define SPI2_CLK_REG_FACTOR_N_OFFSET 8 +#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SPI2_CLK_REG_FACTOR_M_OFFSET 0 +#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPI2_BGR_REG 0x00000f14//SPI2 Bus Gating Reset Register +#define SPI2_BGR_REG_SPI2_RST_OFFSET 16 +#define SPI2_BGR_REG_SPI2_RST_CLEAR_MASK (0x00010000) +#define SPI2_BGR_REG_SPI2_RST_ASSERT 0b0 +#define SPI2_BGR_REG_SPI2_RST_DE_ASSERT 0b1 +#define SPI2_BGR_REG_SPI2_GATING_OFFSET 0 +#define SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK (0x00000001) +#define SPI2_BGR_REG_SPI2_GATING_MASK 0b0 +#define SPI2_BGR_REG_SPI2_GATING_PASS 0b1 + +#define SPIF_CLK_REG 0x00000f18//SPIF Clock Register +#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31 +#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPIF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001 +#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010 +#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011 +#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100 +#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_160M 0b101 +#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_160M 0b110 +#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC 0b111 +#define SPIF_CLK_REG_FACTOR_N_OFFSET 8 +#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SPIF_CLK_REG_FACTOR_M_OFFSET 0 +#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPIF_BGR_REG 0x00000f1c//SPIF Bus Gating Reset Register +#define SPIF_BGR_REG_SPIF_RST_OFFSET 16 +#define SPIF_BGR_REG_SPIF_RST_CLEAR_MASK (0x00010000) +#define SPIF_BGR_REG_SPIF_RST_ASSERT 0b0 +#define SPIF_BGR_REG_SPIF_RST_DE_ASSERT 0b1 +#define SPIF_BGR_REG_SPIF_GATING_OFFSET 0 +#define SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK (0x00000001) +#define SPIF_BGR_REG_SPIF_GATING_MASK 0b0 +#define SPIF_BGR_REG_SPIF_GATING_PASS 0b1 + +#define SPI3_CLK_REG 0x00000f20//SPI3 Clock Register +#define SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET 31 +#define SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPI3_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPI3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010 +#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011 +#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100 +#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101 +#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110 +#define SPI3_CLK_REG_CLK_SRC_SEL_HOSC 0b111 +#define SPI3_CLK_REG_FACTOR_N_OFFSET 8 +#define SPI3_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SPI3_CLK_REG_FACTOR_M_OFFSET 0 +#define SPI3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPI3_BGR_REG 0x00000f24//SPI3 Bus Gating Reset Register +#define SPI3_BGR_REG_SPI3_RST_OFFSET 16 +#define SPI3_BGR_REG_SPI3_RST_CLEAR_MASK (0x00010000) +#define SPI3_BGR_REG_SPI3_RST_ASSERT 0b0 +#define SPI3_BGR_REG_SPI3_RST_DE_ASSERT 0b1 +#define SPI3_BGR_REG_SPI3_GATING_OFFSET 0 +#define SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK (0x00000001) +#define SPI3_BGR_REG_SPI3_GATING_MASK 0b0 +#define SPI3_BGR_REG_SPI3_GATING_PASS 0b1 + +#define SPI4_CLK_REG 0x00000f28//SPI4 Clock Register +#define SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET 31 +#define SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPI4_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPI4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010 +#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011 +#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100 +#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101 +#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110 +#define SPI4_CLK_REG_CLK_SRC_SEL_HOSC 0b111 +#define SPI4_CLK_REG_FACTOR_N_OFFSET 8 +#define SPI4_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define SPI4_CLK_REG_FACTOR_M_OFFSET 0 +#define SPI4_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPI4_BGR_REG 0x00000f2c//SPI4 Bus Gating Reset Register +#define SPI4_BGR_REG_SPI4_RST_OFFSET 16 +#define SPI4_BGR_REG_SPI4_RST_CLEAR_MASK (0x00010000) +#define SPI4_BGR_REG_SPI4_RST_ASSERT 0b0 +#define SPI4_BGR_REG_SPI4_RST_DE_ASSERT 0b1 +#define SPI4_BGR_REG_SPI4_GATING_OFFSET 0 +#define SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK (0x00000001) +#define SPI4_BGR_REG_SPI4_GATING_MASK 0b0 +#define SPI4_BGR_REG_SPI4_GATING_PASS 0b1 + +#define GPADC0_24M_CLK_REG 0x00000fc0//GPADC0_24M Clock Register +#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_OFFSET 31 +#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLEAR_MASK (0x80000000) +#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_OFF 0b0 +#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_ON 0b1 +#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_HOSC 0b001 +#define GPADC0_24M_CLK_REG_FACTOR_M_OFFSET 0 +#define GPADC0_24M_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define GPADC0_BGR_REG 0x00000fc4//GPADC0 Bus Gating Reset Register +#define GPADC0_BGR_REG_GPADC0_RST_OFFSET 16 +#define GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK (0x00010000) +#define GPADC0_BGR_REG_GPADC0_RST_ASSERT 0b0 +#define GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT 0b1 +#define GPADC0_BGR_REG_GPADC0_GATING_OFFSET 0 +#define GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK (0x00000001) +#define GPADC0_BGR_REG_GPADC0_GATING_MASK 0b0 +#define GPADC0_BGR_REG_GPADC0_GATING_PASS 0b1 + +#define THS0_BGR_REG 0x00000fe4//THS0 Bus Gating Reset Register +#define THS0_BGR_REG_THS0_RST_OFFSET 16 +#define THS0_BGR_REG_THS0_RST_CLEAR_MASK (0x00010000) +#define THS0_BGR_REG_THS0_RST_ASSERT 0b0 +#define THS0_BGR_REG_THS0_RST_DE_ASSERT 0b1 +#define THS0_BGR_REG_THS0_GATING_OFFSET 0 +#define THS0_BGR_REG_THS0_GATING_CLEAR_MASK (0x00000001) +#define THS0_BGR_REG_THS0_GATING_MASK 0b0 +#define THS0_BGR_REG_THS0_GATING_PASS 0b1 + +#define IRRX_CLK_REG 0x00001000//IRRX Clock Register +#define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET 31 +#define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK (0x80000000) +#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF 0b0 +#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON 0b1 +#define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K 0b000 +#define IRRX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b001 +#define IRRX_CLK_REG_CLK_SRC_SEL_HOSC 0b010 +#define IRRX_CLK_REG_FACTOR_M_OFFSET 0 +#define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define IRRX_BGR_REG 0x00001004//IRRX Bus Gating Reset Register +#define IRRX_BGR_REG_IRRX_RST_OFFSET 16 +#define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK (0x00010000) +#define IRRX_BGR_REG_IRRX_RST_ASSERT 0b0 +#define IRRX_BGR_REG_IRRX_RST_DE_ASSERT 0b1 +#define IRRX_BGR_REG_IRRX_GATING_OFFSET 0 +#define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK (0x00000001) +#define IRRX_BGR_REG_IRRX_GATING_MASK 0b0 +#define IRRX_BGR_REG_IRRX_GATING_PASS 0b1 + +#define IRTX_CLK_REG 0x00001008//IRTX Clock Register +#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31 +#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK (0x80000000) +#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF 0b0 +#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON 0b1 +#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define IRTX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001 +#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC 0b010 +#define IRTX_CLK_REG_FACTOR_M_OFFSET 0 +#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define IRTX_BGR_REG 0x0000100c//IRTX Bus Gating Reset Register +#define IRTX_BGR_REG_IRTX_RST_OFFSET 16 +#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK (0x00010000) +#define IRTX_BGR_REG_IRTX_RST_ASSERT 0b0 +#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT 0b1 +#define IRTX_BGR_REG_IRTX_GATING_OFFSET 0 +#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK (0x00000001) +#define IRTX_BGR_REG_IRTX_GATING_MASK 0b0 +#define IRTX_BGR_REG_IRTX_GATING_PASS 0b1 + +#define LRADC_BGR_REG 0x00001024//LRADC Bus Gating Reset Register +#define LRADC_BGR_REG_LRADC_RST_OFFSET 16 +#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK (0x00010000) +#define LRADC_BGR_REG_LRADC_RST_ASSERT 0b0 +#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT 0b1 +#define LRADC_BGR_REG_LRADC_GATING_OFFSET 0 +#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK (0x00000001) +#define LRADC_BGR_REG_LRADC_GATING_MASK 0b0 +#define LRADC_BGR_REG_LRADC_GATING_PASS 0b1 + +#define SGPIO_CLK_REG 0x00001060//SGPIO Clock Register +#define SGPIO_CLK_REG_SGPIO_CLK_GATING_OFFSET 31 +#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLEAR_MASK (0x80000000) +#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_ON 0b1 +#define SGPIO_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SGPIO_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SGPIO_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SGPIO_CLK_REG_CLK_SRC_SEL_CLK32K 0b001 +#define SGPIO_CLK_REG_FACTOR_M_OFFSET 0 +#define SGPIO_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SGPIO_BGR_REG 0x00001064//SGPIO Bus Gating Reset Register +#define SGPIO_BGR_REG_SGPIO_RST_OFFSET 16 +#define SGPIO_BGR_REG_SGPIO_RST_CLEAR_MASK (0x00010000) +#define SGPIO_BGR_REG_SGPIO_RST_ASSERT 0b0 +#define SGPIO_BGR_REG_SGPIO_RST_DE_ASSERT 0b1 +#define SGPIO_BGR_REG_SGPIO_GATING_OFFSET 0 +#define SGPIO_BGR_REG_SGPIO_GATING_CLEAR_MASK (0x00000001) +#define SGPIO_BGR_REG_SGPIO_GATING_MASK 0b0 +#define SGPIO_BGR_REG_SGPIO_GATING_PASS 0b1 + +#define LPC_CLK_REG 0x00001080//LPC Clock Register +#define LPC_CLK_REG_LPC_CLK_GATING_OFFSET 31 +#define LPC_CLK_REG_LPC_CLK_GATING_CLEAR_MASK (0x80000000) +#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_OFF 0b0 +#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_ON 0b1 +#define LPC_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define LPC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b000 +#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b001 +#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b010 +#define LPC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011 +#define LPC_CLK_REG_FACTOR_M_OFFSET 0 +#define LPC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define LPC_BGR_REG 0x00001084//LPC Bus Gating Reset Register +#define LPC_BGR_REG_LPC_RST_OFFSET 16 +#define LPC_BGR_REG_LPC_RST_CLEAR_MASK (0x00010000) +#define LPC_BGR_REG_LPC_RST_ASSERT 0b0 +#define LPC_BGR_REG_LPC_RST_DE_ASSERT 0b1 +#define LPC_BGR_REG_LPC_GATING_OFFSET 0 +#define LPC_BGR_REG_LPC_GATING_CLEAR_MASK (0x00000001) +#define LPC_BGR_REG_LPC_GATING_MASK 0b0 +#define LPC_BGR_REG_LPC_GATING_PASS 0b1 + +#define I2SPCM0_CLK_REG 0x00001200//I2SPCM0 Clock Register +#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_OFFSET 31 +#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLEAR_MASK (0x80000000) +#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_ON 0b1 +#define I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define I2SPCM0_CLK_REG_FACTOR_M_OFFSET 0 +#define I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define I2SPCM0_BGR_REG 0x0000120c//I2SPCM0 Bus Gating Reset Register +#define I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET 16 +#define I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK (0x00010000) +#define I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT 0b0 +#define I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT 0b1 +#define I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET 0 +#define I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK (0x00000001) +#define I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK 0b0 +#define I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS 0b1 + +#define I2SPCM1_CLK_REG 0x00001210//I2SPCM1 Clock Register +#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_OFFSET 31 +#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLEAR_MASK (0x80000000) +#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_ON 0b1 +#define I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define I2SPCM1_CLK_REG_FACTOR_M_OFFSET 0 +#define I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define I2SPCM1_BGR_REG 0x0000121c//I2SPCM1 Bus Gating Reset Register +#define I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET 16 +#define I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK (0x00010000) +#define I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT 0b0 +#define I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT 0b1 +#define I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET 0 +#define I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK (0x00000001) +#define I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK 0b0 +#define I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS 0b1 + +#define I2SPCM2_CLK_REG 0x00001220//I2SPCM2 Clock Register +#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_OFFSET 31 +#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLEAR_MASK (0x80000000) +#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_OFF 0b0 +#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_ON 0b1 +#define I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define I2SPCM2_CLK_REG_FACTOR_M_OFFSET 0 +#define I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define I2SPCM2_ASRC_CLK_REG 0x00001224//I2SPCM2_ASRC Clock Register +#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_OFFSET 31 +#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLEAR_MASK (0x80000000) +#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_OFF 0b0 +#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_ON 0b1 +#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011 +#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100 +#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_OFFSET 0 +#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define I2SPCM2_BGR_REG 0x0000122c//I2SPCM2 Bus Gating Reset Register +#define I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET 16 +#define I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK (0x00010000) +#define I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT 0b0 +#define I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT 0b1 +#define I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET 0 +#define I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK (0x00000001) +#define I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK 0b0 +#define I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS 0b1 +#define I2SPCM2_BGR_REG_I2SPCM2_GATING____CCU_AUTO_GEN_I2S2_PROT 0x2 + +#define I2SPCM3_CLK_REG 0x00001230//I2SPCM3 Clock Register +#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_OFFSET 31 +#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLEAR_MASK (0x80000000) +#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_OFF 0b0 +#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_ON 0b1 +#define I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define I2SPCM3_CLK_REG_FACTOR_M_OFFSET 0 +#define I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define I2SPCM3_BGR_REG 0x0000123c//I2SPCM3 Bus Gating Reset Register +#define I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET 16 +#define I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK (0x00010000) +#define I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT 0b0 +#define I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT 0b1 +#define I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET 0 +#define I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK (0x00000001) +#define I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK 0b0 +#define I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS 0b1 +#define I2SPCM3_BGR_REG_I2SPCM3_GATING____CCU_AUTO_GEN_I2S3_PROT 0x3 + +#define I2SPCM4_CLK_REG 0x00001240//I2SPCM4 Clock Register +#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_OFFSET 31 +#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLEAR_MASK (0x80000000) +#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_OFF 0b0 +#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_ON 0b1 +#define I2SPCM4_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define I2SPCM4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define I2SPCM4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011 +#define I2SPCM4_CLK_REG_FACTOR_M_OFFSET 0 +#define I2SPCM4_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define I2SPCM4_BGR_REG 0x0000124c//I2SPCM4 Bus Gating Reset Register +#define I2SPCM4_BGR_REG_I2SPCM4_RST_OFFSET 16 +#define I2SPCM4_BGR_REG_I2SPCM4_RST_CLEAR_MASK (0x00010000) +#define I2SPCM4_BGR_REG_I2SPCM4_RST_ASSERT 0b0 +#define I2SPCM4_BGR_REG_I2SPCM4_RST_DE_ASSERT 0b1 +#define I2SPCM4_BGR_REG_I2SPCM4_GATING_OFFSET 0 +#define I2SPCM4_BGR_REG_I2SPCM4_GATING_CLEAR_MASK (0x00000001) +#define I2SPCM4_BGR_REG_I2SPCM4_GATING_MASK 0b0 +#define I2SPCM4_BGR_REG_I2SPCM4_GATING_PASS 0b1 +#define I2SPCM4_BGR_REG_I2SPCM4_GATING____CCU_AUTO_GEN_I2S4_PROT 0x4 + +#define SPDIF_TX_CLK_REG 0x00001280//SPDIF TX Clock Register +#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_OFFSET 31 +#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define SPDIF_TX_CLK_REG_FACTOR_M_OFFSET 0 +#define SPDIF_TX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPDIF_RX_CLK_REG 0x00001284//SPDIF RX Clock Register +#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_OFFSET 31 +#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLEAR_MASK (0x80000000) +#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_ON 0b1 +#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b000 +#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010 +#define SPDIF_RX_CLK_REG_FACTOR_M_OFFSET 0 +#define SPDIF_RX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SPDIF_BGR_REG 0x0000128c//SPDIF Bus Gating Reset Register +#define SPDIF_BGR_REG_SPDIF_RST_OFFSET 16 +#define SPDIF_BGR_REG_SPDIF_RST_CLEAR_MASK (0x00010000) +#define SPDIF_BGR_REG_SPDIF_RST_ASSERT 0b0 +#define SPDIF_BGR_REG_SPDIF_RST_DE_ASSERT 0b1 +#define SPDIF_BGR_REG_SPDIF_GATING_OFFSET 0 +#define SPDIF_BGR_REG_SPDIF_GATING_CLEAR_MASK (0x00000001) +#define SPDIF_BGR_REG_SPDIF_GATING_MASK 0b0 +#define SPDIF_BGR_REG_SPDIF_GATING_PASS 0b1 + +#define DMIC_CLK_REG 0x000012c0//DMIC Clock Register +#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET 31 +#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK (0x80000000) +#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF 0b0 +#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON 0b1 +#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000 +#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001 +#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010 +#define DMIC_CLK_REG_FACTOR_M_OFFSET 0 +#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define DMIC_BGR_REG 0x000012cc//DMIC Bus Gating Reset Register +#define DMIC_BGR_REG_DMIC_RST_OFFSET 16 +#define DMIC_BGR_REG_DMIC_RST_CLEAR_MASK (0x00010000) +#define DMIC_BGR_REG_DMIC_RST_ASSERT 0b0 +#define DMIC_BGR_REG_DMIC_RST_DE_ASSERT 0b1 +#define DMIC_BGR_REG_DMIC_GATING_OFFSET 0 +#define DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK (0x00000001) +#define DMIC_BGR_REG_DMIC_GATING_MASK 0b0 +#define DMIC_BGR_REG_DMIC_GATING_PASS 0b1 + +#define USB0_CLK_REG 0x00001300//USB0 Clock Register +#define USB0_CLK_REG_USB0_CLKEN_OFFSET 31 +#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK (0x80000000) +#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0b0 +#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0b1 +#define USB0_CLK_REG_USB0_PHY_RSTN_OFFSET 30 +#define USB0_CLK_REG_USB0_PHY_RSTN_CLEAR_MASK (0x40000000) +#define USB0_CLK_REG_USB0_PHY_RSTN_ASSERT 0b0 +#define USB0_CLK_REG_USB0_PHY_RSTN_DE_ASSERT 0b1 +#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24 +#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK (0x03000000) +#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b000 +#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M 0b001 +#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K 0b010 +#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC 0b011 + +#define USB0_BGR_REG 0x00001304//USB0 Bus Gating Reset Register +#define USB0_BGR_REG_USB0_DEVICE_RST_OFFSET 24 +#define USB0_BGR_REG_USB0_DEVICE_RST_CLEAR_MASK (0x01000000) +#define USB0_BGR_REG_USB0_DEVICE_RST_ASSERT 0b0 +#define USB0_BGR_REG_USB0_DEVICE_RST_DE_ASSERT 0b1 +#define USB0_BGR_REG_USB0_EHCI_RST_OFFSET 20 +#define USB0_BGR_REG_USB0_EHCI_RST_CLEAR_MASK (0x00100000) +#define USB0_BGR_REG_USB0_EHCI_RST_ASSERT 0b0 +#define USB0_BGR_REG_USB0_EHCI_RST_DE_ASSERT 0b1 +#define USB0_BGR_REG_USB0_OHCI_RST_OFFSET 16 +#define USB0_BGR_REG_USB0_OHCI_RST_CLEAR_MASK (0x00010000) +#define USB0_BGR_REG_USB0_OHCI_RST_ASSERT 0b0 +#define USB0_BGR_REG_USB0_OHCI_RST_DE_ASSERT 0b1 +#define USB0_BGR_REG_USB0_DEVICE_GATING_OFFSET 8 +#define USB0_BGR_REG_USB0_DEVICE_GATING_CLEAR_MASK (0x00000100) +#define USB0_BGR_REG_USB0_DEVICE_GATING_MASK 0b0 +#define USB0_BGR_REG_USB0_DEVICE_GATING_PASS 0b1 +#define USB0_BGR_REG_USB0_EHCI_GATING_OFFSET 4 +#define USB0_BGR_REG_USB0_EHCI_GATING_CLEAR_MASK (0x00000010) +#define USB0_BGR_REG_USB0_EHCI_GATING_MASK 0b0 +#define USB0_BGR_REG_USB0_EHCI_GATING_PASS 0b1 +#define USB0_BGR_REG_USB0_OHCI_GATING_OFFSET 0 +#define USB0_BGR_REG_USB0_OHCI_GATING_CLEAR_MASK (0x00000001) +#define USB0_BGR_REG_USB0_OHCI_GATING_MASK 0b0 +#define USB0_BGR_REG_USB0_OHCI_GATING_PASS 0b1 + +#define USB1_CLK_REG 0x00001308//USB1 Clock Register +#define USB1_CLK_REG_USB1_CLKEN_OFFSET 31 +#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK (0x80000000) +#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0b0 +#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0b1 +#define USB1_CLK_REG_USB1_PHY_RSTN_OFFSET 30 +#define USB1_CLK_REG_USB1_PHY_RSTN_CLEAR_MASK (0x40000000) +#define USB1_CLK_REG_USB1_PHY_RSTN_ASSERT 0b0 +#define USB1_CLK_REG_USB1_PHY_RSTN_DE_ASSERT 0b1 +#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24 +#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK (0x03000000) +#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b000 +#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M 0b001 +#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K 0b010 +#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC 0b011 + +#define USB1_BGR_REG 0x0000130c//USB1 Bus Gating Reset Register +#define USB1_BGR_REG_USB1_EHCI_RST_OFFSET 20 +#define USB1_BGR_REG_USB1_EHCI_RST_CLEAR_MASK (0x00100000) +#define USB1_BGR_REG_USB1_EHCI_RST_ASSERT 0b0 +#define USB1_BGR_REG_USB1_EHCI_RST_DE_ASSERT 0b1 +#define USB1_BGR_REG_USB1_OHCI_RST_OFFSET 16 +#define USB1_BGR_REG_USB1_OHCI_RST_CLEAR_MASK (0x00010000) +#define USB1_BGR_REG_USB1_OHCI_RST_ASSERT 0b0 +#define USB1_BGR_REG_USB1_OHCI_RST_DE_ASSERT 0b1 +#define USB1_BGR_REG_USB1_EHCI_GATING_OFFSET 4 +#define USB1_BGR_REG_USB1_EHCI_GATING_CLEAR_MASK (0x00000010) +#define USB1_BGR_REG_USB1_EHCI_GATING_MASK 0b0 +#define USB1_BGR_REG_USB1_EHCI_GATING_PASS 0b1 +#define USB1_BGR_REG_USB1_OHCI_GATING_OFFSET 0 +#define USB1_BGR_REG_USB1_OHCI_GATING_CLEAR_MASK (0x00000001) +#define USB1_BGR_REG_USB1_OHCI_GATING_MASK 0b0 +#define USB1_BGR_REG_USB1_OHCI_GATING_PASS 0b1 + +#define USB0_USB1_REF_CLK_REG 0x00001340//USB0_USB1_REF Clock Register +#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_OFFSET 31 +#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLEAR_MASK (0x80000000) +#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_OFF 0b0 +#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_ON 0b1 +#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_HOSC 0b001 + +#define USB2_U2_REF_CLK_REG 0x00001348//USB2_U2_REF Clock Register +#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_OFFSET 31 +#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLEAR_MASK (0x80000000) +#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_OFF 0b0 +#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_ON 0b1 +#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_HOSC 0b001 + +#define USB2_SUSPEND_CLK_REG 0x00001350//USB2_SUSPEND Clock Register +#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31 +#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK (0x80000000) +#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0b0 +#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0b1 +#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x01000000) +#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K 0b0 +#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b1 +#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET 0 +#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define USB2_MF_CLK_REG 0x00001354//USB2_MF Clock Register +#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET 31 +#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK (0x80000000) +#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF 0b0 +#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON 0b1 +#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC 0b010 +#define USB2_MF_CLK_REG_FACTOR_M_OFFSET 0 +#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define USB2_BGR_REG 0x0000135c//USB2 Bus Gating Reset Register +#define USB2_BGR_REG_USB2_RST_OFFSET 16 +#define USB2_BGR_REG_USB2_RST_CLEAR_MASK (0x00010000) +#define USB2_BGR_REG_USB2_RST_ASSERT 0b0 +#define USB2_BGR_REG_USB2_RST_DE_ASSERT 0b1 + +#define USB2_U3_UTMI_CLK_REG 0x00001360//USB2_U3_UTMI Clock Register +#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_OFFSET 31 +#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLEAR_MASK (0x80000000) +#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_OFF 0b0 +#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_ON 0b1 +#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001 +#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_HOSC 0b010 +#define USB2_U3_UTMI_CLK_REG_FACTOR_M_OFFSET 0 +#define USB2_U3_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define USB2_U2_PIPE_CLK_REG 0x00001364//USB2_U2_PIPE Clock Register +#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_OFFSET 31 +#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLEAR_MASK (0x80000000) +#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_OFF 0b0 +#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_ON 0b1 +#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001 +#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_HOSC 0b010 +#define USB2_U2_PIPE_CLK_REG_FACTOR_M_OFFSET 0 +#define USB2_U2_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define PCIE0_AUX_CLK_REG 0x00001380//PCIE0_AUX Clock Register +#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET 31 +#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK (0x80000000) +#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF 0b0 +#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON 0b1 +#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x01000000) +#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b0 +#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLK32K 0b1 +#define PCIE0_AUX_CLK_REG_FACTOR_M_OFFSET 0 +#define PCIE0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define PCIE0_AXI_SLV_CLK_REG 0x00001384//PCIE0_AXI_SLV Clock Register +#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_OFFSET 31 +#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLEAR_MASK (0x80000000) +#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_OFF 0b0 +#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_ON 0b1 +#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b000 +#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001 +#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010 +#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_OFFSET 0 +#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define PCIE0_BGR_REG 0x0000138c//PCIE0 Bus Gating Reset Register +#define PCIE0_BGR_REG_PCIE0_RST_OFFSET 17 +#define PCIE0_BGR_REG_PCIE0_RST_CLEAR_MASK (0x00020000) +#define PCIE0_BGR_REG_PCIE0_RST_ASSERT 0b0 +#define PCIE0_BGR_REG_PCIE0_RST_DE_ASSERT 0b1 +#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_OFFSET 16 +#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_CLEAR_MASK (0x00010000) +#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_ASSERT 0b0 +#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_DE_ASSERT 0b1 + +#define SERDES_PHY_CFG_CLK_REG 0x000013c0//SERDES_PHY_CFG Clock Register +#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET 31 +#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK (0x80000000) +#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF 0b0 +#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON 0b1 +#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b001 +#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET 0 +#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define SERDES_BGR_REG 0x000013c4//SERDES Bus Gating Reset Register +#define SERDES_BGR_REG_SERDES_RST_OFFSET 16 +#define SERDES_BGR_REG_SERDES_RST_CLEAR_MASK (0x00010000) +#define SERDES_BGR_REG_SERDES_RST_ASSERT 0b0 +#define SERDES_BGR_REG_SERDES_RST_DE_ASSERT 0b1 + +#define GMAC_PTP_CLK_REG 0x00001400//GMAC_PTP Clock Register +#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_OFFSET 31 +#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLEAR_MASK (0x80000000) +#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_OFF 0b0 +#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_ON 0b1 +#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001 +#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b010 +#define GMAC_PTP_CLK_REG_FACTOR_M_OFFSET 0 +#define GMAC_PTP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define GMAC0_PHY_CLK_REG 0x00001410//GMAC0_PHY Clock Register +#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31 +#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK (0x80000000) +#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF 0b0 +#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON 0b1 +#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0 +#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define GMAC0_BGR_REG 0x0000141c//GMAC0 Bus Gating Reset Register +#define GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET 17 +#define GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK (0x00020000) +#define GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT 0b0 +#define GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT 0b1 +#define GMAC0_BGR_REG_GMAC0_RST_OFFSET 16 +#define GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK (0x00010000) +#define GMAC0_BGR_REG_GMAC0_RST_ASSERT 0b0 +#define GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT 0b1 +#define GMAC0_BGR_REG_GMAC0_GATING_OFFSET 0 +#define GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK (0x00000001) +#define GMAC0_BGR_REG_GMAC0_GATING_MASK 0b0 +#define GMAC0_BGR_REG_GMAC0_GATING_PASS 0b1 + +#define GMAC1_PHY_CLK_REG 0x00001420//GMAC1_PHY Clock Register +#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET 31 +#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK (0x80000000) +#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF 0b0 +#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON 0b1 +#define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET 0 +#define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define GMAC1_BGR_REG 0x0000142c//GMAC1 Bus Gating Reset Register +#define GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET 17 +#define GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK (0x00020000) +#define GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT 0b0 +#define GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT 0b1 +#define GMAC1_BGR_REG_GMAC1_RST_OFFSET 16 +#define GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK (0x00010000) +#define GMAC1_BGR_REG_GMAC1_RST_ASSERT 0b0 +#define GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT 0b1 +#define GMAC1_BGR_REG_GMAC1_GATING_OFFSET 0 +#define GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK (0x00000001) +#define GMAC1_BGR_REG_GMAC1_GATING_MASK 0b0 +#define GMAC1_BGR_REG_GMAC1_GATING_PASS 0b1 + +#define VO0_TCONLCD0_CLK_REG 0x00001500//VO0_TCONLCD0 Clock Register +#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31 +#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK (0x80000000) +#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0b1 +#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001 +#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010 +#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011 +#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0 +#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define VO0_TCONLCD0_BGR_REG 0x00001504//VO0_TCONLCD0 Bus Gating Reset Register +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16 +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK (0x00010000) +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT 0b0 +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT 0b1 +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0 +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK (0x00000001) +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK 0b0 +#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS 0b1 + +#define VO0_TCONLCD1_CLK_REG 0x00001508//VO0_TCONLCD1 Clock Register +#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET 31 +#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK (0x80000000) +#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON 0b1 +#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001 +#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010 +#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011 +#define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET 0 +#define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define VO0_TCONLCD1_BGR_REG 0x0000150c//VO0_TCONLCD1 Bus Gating Reset Register +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_OFFSET 16 +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK (0x00010000) +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_ASSERT 0b0 +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT 0b1 +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_OFFSET 0 +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK (0x00000001) +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_MASK 0b0 +#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_PASS 0b1 + +#define VO0_TCONLCD2_CLK_REG 0x00001510//VO0_TCONLCD2 Clock Register +#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_OFFSET 31 +#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLEAR_MASK (0x80000000) +#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_OFF 0b0 +#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_ON 0b1 +#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001 +#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010 +#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011 +#define VO0_TCONLCD2_CLK_REG_FACTOR_M_OFFSET 0 +#define VO0_TCONLCD2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define VO0_TCONLCD2_BGR_REG 0x00001514//VO0_TCONLCD2 Bus Gating Reset Register +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_OFFSET 16 +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_CLEAR_MASK (0x00010000) +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_ASSERT 0b0 +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_DE_ASSERT 0b1 +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_OFFSET 0 +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_CLEAR_MASK (0x00000001) +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_MASK 0b0 +#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_PASS 0b1 + +#define LVDS0_BGR_REG 0x00001544//LVDS0 Bus Gating Reset Register +#define LVDS0_BGR_REG_LVDS0_RST_OFFSET 16 +#define LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK (0x00010000) +#define LVDS0_BGR_REG_LVDS0_RST_ASSERT 0b0 +#define LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT 0b1 + +#define LVDS1_BGR_REG 0x0000154c//LVDS1 Bus Gating Reset Register +#define LVDS1_BGR_REG_LVDS1_RST_OFFSET 16 +#define LVDS1_BGR_REG_LVDS1_RST_CLEAR_MASK (0x00010000) +#define LVDS1_BGR_REG_LVDS1_RST_ASSERT 0b0 +#define LVDS1_BGR_REG_LVDS1_RST_DE_ASSERT 0b1 + +#define DSI0_CLK_REG 0x00001580//DSI0 Clock Register +#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31 +#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK (0x80000000) +#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON 0b1 +#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define DSI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001 +#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010 +#define DSI0_CLK_REG_FACTOR_M_OFFSET 0 +#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define DSI0_BGR_REG 0x00001584//DSI0 Bus Gating Reset Register +#define DSI0_BGR_REG_DSI0_RST_OFFSET 16 +#define DSI0_BGR_REG_DSI0_RST_CLEAR_MASK (0x00010000) +#define DSI0_BGR_REG_DSI0_RST_ASSERT 0b0 +#define DSI0_BGR_REG_DSI0_RST_DE_ASSERT 0b1 +#define DSI0_BGR_REG_DSI0_GATING_OFFSET 0 +#define DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK (0x00000001) +#define DSI0_BGR_REG_DSI0_GATING_MASK 0b0 +#define DSI0_BGR_REG_DSI0_GATING_PASS 0b1 + +#define DSI1_CLK_REG 0x00001588//DSI1 Clock Register +#define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET 31 +#define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK (0x80000000) +#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON 0b1 +#define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define DSI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001 +#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010 +#define DSI1_CLK_REG_FACTOR_M_OFFSET 0 +#define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define DSI1_BGR_REG 0x0000158c//DSI1 Bus Gating Reset Register +#define DSI1_BGR_REG_DSI1_RST_OFFSET 16 +#define DSI1_BGR_REG_DSI1_RST_CLEAR_MASK (0x00010000) +#define DSI1_BGR_REG_DSI1_RST_ASSERT 0b0 +#define DSI1_BGR_REG_DSI1_RST_DE_ASSERT 0b1 +#define DSI1_BGR_REG_DSI1_GATING_OFFSET 0 +#define DSI1_BGR_REG_DSI1_GATING_CLEAR_MASK (0x00000001) +#define DSI1_BGR_REG_DSI1_GATING_MASK 0b0 +#define DSI1_BGR_REG_DSI1_GATING_PASS 0b1 + +#define COMBPHY0_CLK_REG 0x000015c0//COMBPHY0 Clock Register +#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET 31 +#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK (0x80000000) +#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON 0b1 +#define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001 +#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010 +#define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011 +#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100 +#define COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0 +#define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define COMBPHY1_CLK_REG 0x000015c4//COMBPHY1 Clock Register +#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET 31 +#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK (0x80000000) +#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON 0b1 +#define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001 +#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010 +#define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011 +#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100 +#define COMBPHY1_CLK_REG_FACTOR_M_OFFSET 0 +#define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define TCONTV0_BGR_REG 0x00001604//TCONTV0 Bus Gating Reset Register +#define TCONTV0_BGR_REG_TCONTV0_RST_OFFSET 16 +#define TCONTV0_BGR_REG_TCONTV0_RST_CLEAR_MASK (0x00010000) +#define TCONTV0_BGR_REG_TCONTV0_RST_ASSERT 0b0 +#define TCONTV0_BGR_REG_TCONTV0_RST_DE_ASSERT 0b1 +#define TCONTV0_BGR_REG_TCONTV0_GATING_OFFSET 0 +#define TCONTV0_BGR_REG_TCONTV0_GATING_CLEAR_MASK (0x00000001) +#define TCONTV0_BGR_REG_TCONTV0_GATING_MASK 0b0 +#define TCONTV0_BGR_REG_TCONTV0_GATING_PASS 0b1 + +#define TCONTV1_BGR_REG 0x0000160c//TCONTV1 Bus Gating Reset Register +#define TCONTV1_BGR_REG_TCONTV1_RST_OFFSET 16 +#define TCONTV1_BGR_REG_TCONTV1_RST_CLEAR_MASK (0x00010000) +#define TCONTV1_BGR_REG_TCONTV1_RST_ASSERT 0b0 +#define TCONTV1_BGR_REG_TCONTV1_RST_DE_ASSERT 0b1 +#define TCONTV1_BGR_REG_TCONTV1_GATING_OFFSET 0 +#define TCONTV1_BGR_REG_TCONTV1_GATING_CLEAR_MASK (0x00000001) +#define TCONTV1_BGR_REG_TCONTV1_GATING_MASK 0b0 +#define TCONTV1_BGR_REG_TCONTV1_GATING_PASS 0b1 + +#define EDP_TV_CLK_REG 0x00001640//EDP_TV Clock Register +#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_OFFSET 31 +#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLEAR_MASK (0x80000000) +#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_OFF 0b0 +#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_ON 0b1 +#define EDP_TV_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define EDP_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001 +#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010 +#define EDP_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011 +#define EDP_TV_CLK_REG_FACTOR_N_OFFSET 8 +#define EDP_TV_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define EDP_TV_CLK_REG_FACTOR_M_OFFSET 0 +#define EDP_TV_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define EDP_BGR_REG 0x0000164c//EDP Bus Gating Reset Register +#define EDP_BGR_REG_EDP_RST_OFFSET 16 +#define EDP_BGR_REG_EDP_RST_CLEAR_MASK (0x00010000) +#define EDP_BGR_REG_EDP_RST_ASSERT 0b0 +#define EDP_BGR_REG_EDP_RST_DE_ASSERT 0b1 +#define EDP_BGR_REG_EDP_GATING_OFFSET 0 +#define EDP_BGR_REG_EDP_GATING_CLEAR_MASK (0x00000001) +#define EDP_BGR_REG_EDP_GATING_MASK 0b0 +#define EDP_BGR_REG_EDP_GATING_PASS 0b1 + +#define HDMI_CEC_CLK_REG 0x00001680//HDMI CEC Clock Register +#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET 31 +#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK (0x80000000) +#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF 0b0 +#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON 0b1 +#define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET 30 +#define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK (0x40000000) +#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF 0b0 +#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON 0b1 +#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K 0b000 +#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K_PERI0PLL2X_36621_32_768KHZ \ + 0b001 + +#define HDMI_TV_CLK_REG 0x00001684//HDMI_TV Clock Register +#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_OFFSET 31 +#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLEAR_MASK (0x80000000) +#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_OFF 0b0 +#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_ON 0b1 +#define HDMI_TV_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define HDMI_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000 +#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001 +#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010 +#define HDMI_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011 +#define HDMI_TV_CLK_REG_FACTOR_N_OFFSET 8 +#define HDMI_TV_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define HDMI_TV_CLK_REG_FACTOR_M_OFFSET 0 +#define HDMI_TV_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define HDMI_BGR_REG 0x0000168c//HDMI Bus Gating Reset Register +#define HDMI_BGR_REG_HDMI_HDCP_RST_OFFSET 18 +#define HDMI_BGR_REG_HDMI_HDCP_RST_CLEAR_MASK (0x00040000) +#define HDMI_BGR_REG_HDMI_HDCP_RST_ASSERT 0b0 +#define HDMI_BGR_REG_HDMI_HDCP_RST_DE_ASSERT 0b1 +#define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET 17 +#define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK (0x00020000) +#define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT 0b0 +#define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT 0b1 +#define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET 16 +#define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK (0x00010000) +#define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT 0b0 +#define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT 0b1 +#define HDMI_BGR_REG_HDMI_GATING_OFFSET 0 +#define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK (0x00000001) +#define HDMI_BGR_REG_HDMI_GATING_MASK 0b0 +#define HDMI_BGR_REG_HDMI_GATING_PASS 0b1 + +#define HDMI_SFR_CLK_REG 0x00001690//HDMI SFR Clock Register +#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_OFFSET 31 +#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLEAR_MASK (0x80000000) +#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_OFF 0b0 +#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_ON 0b1 +#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_HOSC 0b001 + +#define HDCP_ESM_CLK_REG 0x00001694//HDCP ESM Clock Register +#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_OFFSET 31 +#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLEAR_MASK (0x80000000) +#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_OFF 0b0 +#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_ON 0b1 + +#define DPSS_TOP0_BGR_REG 0x000016c4//DPSS_TOP0 Bus Gating Reset Register +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET 16 +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK (0x00010000) +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT 0b0 +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT 0b1 +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET 0 +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK (0x00000001) +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK 0b0 +#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS 0b1 + +#define DPSS_TOP1_BGR_REG 0x000016cc//DPSS_TOP1 Bus Gating Reset Register +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET 16 +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK (0x00010000) +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT 0b0 +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT 0b1 +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET 0 +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK (0x00000001) +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK 0b0 +#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS 0b1 + +#define VIDEO_OUT0_BGR_REG 0x000016e4//VIDEO_OUT0 Bus Gating Reset Register +#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET 16 +#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK (0x00010000) +#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT 0b0 +#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT 0b1 + +#define VIDEO_OUT1_BGR_REG 0x000016ec//VIDEO_OUT1 Bus Gating Reset Register +#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_OFFSET 16 +#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_CLEAR_MASK (0x00010000) +#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_ASSERT 0b0 +#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_DE_ASSERT 0b1 + +#define LEDC_CLK_REG 0x00001700//LEDC Clock Register +#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31 +#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK (0x80000000) +#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0b0 +#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0b1 +#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b001 +#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC 0b010 +#define LEDC_CLK_REG_FACTOR_M_OFFSET 0 +#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define LEDC_BGR_REG 0x00001704//LEDC Bus Gating Reset Register +#define LEDC_BGR_REG_LEDC_RST_OFFSET 16 +#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK (0x00010000) +#define LEDC_BGR_REG_LEDC_RST_ASSERT 0b0 +#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT 0b1 +#define LEDC_BGR_REG_LEDC_GATING_OFFSET 0 +#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK (0x00000001) +#define LEDC_BGR_REG_LEDC_GATING_MASK 0b0 +#define LEDC_BGR_REG_LEDC_GATING_PASS 0b1 + +#define DSC_BGR_REG 0x00001744//DSC Bus Gating Reset Register +#define DSC_BGR_REG_DSC_RST_OFFSET 16 +#define DSC_BGR_REG_DSC_RST_CLEAR_MASK (0x00010000) +#define DSC_BGR_REG_DSC_RST_ASSERT 0b0 +#define DSC_BGR_REG_DSC_RST_DE_ASSERT 0b1 +#define DSC_BGR_REG_DSC_GATING_OFFSET 0 +#define DSC_BGR_REG_DSC_GATING_CLEAR_MASK (0x00000001) +#define DSC_BGR_REG_DSC_GATING_MASK 0b0 +#define DSC_BGR_REG_DSC_GATING_PASS 0b1 + +#define CSI_MASTER0_CLK_REG 0x00001800//CSI Master0 Clock Register +#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31 +#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK (0x80000000) +#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0b0 +#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0b1 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b011 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b101 +#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110 +#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8 +#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0 +#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define CSI_MASTER1_CLK_REG 0x00001804//CSI Master1 Clock Register +#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31 +#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK (0x80000000) +#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0b0 +#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0b1 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b011 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b101 +#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110 +#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8 +#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0 +#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define CSI_MASTER2_CLK_REG 0x00001808//CSI Master2 Clock Register +#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31 +#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK (0x80000000) +#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0b0 +#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0b1 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b011 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b101 +#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110 +#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8 +#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00) +#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0 +#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define CSI_CLK_REG 0x00001840//CSI Clock Register +#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31 +#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK (0x80000000) +#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0b0 +#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0b1 +#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b000 +#define CSI_CLK_REG_CLK_SRC_SEL_DEPLL4X 0b001 +#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010 +#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011 +#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b100 +#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101 +#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b110 +#define CSI_CLK_REG_FACTOR_M_OFFSET 0 +#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define CSI_BGR_REG 0x00001844//CSI Bus Gating Reset Register +#define CSI_BGR_REG_CSI_RST_OFFSET 16 +#define CSI_BGR_REG_CSI_RST_CLEAR_MASK (0x00010000) +#define CSI_BGR_REG_CSI_RST_ASSERT 0b0 +#define CSI_BGR_REG_CSI_RST_DE_ASSERT 0b1 +#define CSI_BGR_REG_CSI_GATING_OFFSET 0 +#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK (0x00000001) +#define CSI_BGR_REG_CSI_GATING_MASK 0b0 +#define CSI_BGR_REG_CSI_GATING_PASS 0b1 + +#define ISP_CLK_REG 0x00001860//ISP Clock Register +#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31 +#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK (0x80000000) +#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0b0 +#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0b1 +#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b000 +#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001 +#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010 +#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011 +#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b100 +#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b101 +#define ISP_CLK_REG_FACTOR_M_OFFSET 0 +#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define VIDEO_IN_BGR_REG 0x00001884//VIDEO_IN Bus Gating Reset Register +#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_OFFSET 16 +#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_CLEAR_MASK (0x00010000) +#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_ASSERT 0b0 +#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_DE_ASSERT 0b1 + +#define DDRPLL_GATE_EN_REG 0x00001904//DDRPLL Gate Enable Register +#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET 16 +#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE 0b0 +#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE 0b1 +#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET 0 +#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO 0b0 +#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO 0b1 + +#define PERI0PLL_GATE_EN_REG 0x00001908//PERI0PLL Gate Enable Register +#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_OFFSET 31 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_CLEAR_MASK (0x80000000) +#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27 +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK (0x08000000) +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26 +#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK (0x04000000) +#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25 +#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000) +#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK (0x01000000) +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000) +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22 +#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000) +#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000) +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK (0x00100000) +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19 +#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000) +#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000) +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000) +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16 +#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11 +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK (0x00000800) +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10 +#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000400) +#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9 +#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200) +#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000100) +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080) +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6 +#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040) +#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020) +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK (0x00000010) +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3 +#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008) +#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004) +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002) +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0 +#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0b0 +#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0b1 + +#define PERI1PLL_GATE_EN_REG 0x0000190c//PERI1PLL Gate Enable Register +#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_OFFSET 31 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_CLEAR_MASK (0x80000000) +#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27 +#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK (0x08000000) +#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK (0x04000000) +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000) +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET 24 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK (0x01000000) +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000) +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET 22 +#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000) +#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000) +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK (0x00100000) +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19 +#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000) +#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000) +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000) +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16 +#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11 +#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000800) +#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000400) +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200) +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET 8 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000100) +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080) +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET 6 +#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040) +#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020) +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK (0x00000010) +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3 +#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008) +#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004) +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002) +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO 0b1 +#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0 +#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO 0b0 +#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO 0b1 + +#define VIDEOPLL_GATE_EN_REG 0x00001910//VIDEOPLL Gate Enable Register +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET 22 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00400000) +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET 21 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00200000) +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET 20 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00100000) +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET 18 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00040000) +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET 17 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00020000) +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET 6 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000040) +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET 5 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000020) +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET 4 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000010) +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET 2 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000004) +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET 1 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000002) +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO 0b1 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO 0b0 +#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1 + +#define GPUPLL_GATE_EN_REG 0x00001914//GPUPLL Gate Enable Register +#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_OFFSET 16 +#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_DISABLE 0b0 +#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_ENABLE 0b1 +#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_OFFSET 0 +#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_AUTO 0b0 +#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_NO_AUTO 0b1 + +#define VEPLL_GATE_EN_REG 0x00001918//VEPLL Gate Enable Register +#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_OFFSET 17 +#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_CLEAR_MASK (0x00020000) +#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_DISABLE 0b0 +#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_ENABLE 0b1 +#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_OFFSET 16 +#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_DISABLE 0b0 +#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_ENABLE 0b1 +#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_OFFSET 1 +#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000002) +#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_AUTO 0b0 +#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_NO_AUTO 0b1 +#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_OFFSET 0 +#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_AUTO 0b0 +#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_NO_AUTO 0b1 + +#define AUDIOPLL_GATE_EN_REG 0x0000191c//AUDIOPLL Gate Enable Register +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_OFFSET 18 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_CLEAR_MASK (0x00040000) +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_DISABLE 0b0 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_ENABLE 0b1 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_OFFSET 17 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_CLEAR_MASK (0x00020000) +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_DISABLE 0b0 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_ENABLE 0b1 +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_OFFSET 16 +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_DISABLE 0b0 +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_ENABLE 0b1 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_OFFSET 2 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_CLEAR_MASK (0x00000004) +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_AUTO 0b0 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_NO_AUTO 0b1 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_OFFSET 1 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_CLEAR_MASK (0x00000002) +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_AUTO 0b0 +#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_NO_AUTO 0b1 +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_OFFSET 0 +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_AUTO 0b0 +#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1 + +#define NPUPLL_GATE_EN_REG 0x00001920//NPUPLL Gate Enable Register +#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_OFFSET 16 +#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_DISABLE 0b0 +#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_ENABLE 0b1 +#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_OFFSET 0 +#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_AUTO 0b0 +#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_NO_AUTO 0b1 + +#define DEPLL_GATE_EN_REG 0x00001928//DEPLL Gate Enable Register +#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_OFFSET 17 +#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_CLEAR_MASK (0x00020000) +#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_DISABLE 0b0 +#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_ENABLE 0b1 +#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_OFFSET 16 +#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000) +#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_DISABLE 0b0 +#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_ENABLE 0b1 +#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_OFFSET 1 +#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000002) +#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_AUTO 0b0 +#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_NO_AUTO 0b1 +#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_OFFSET 0 +#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001) +#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_AUTO 0b0 +#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_NO_AUTO 0b1 + +#define DDRPLL_GATE_STAT_REG 0x00001984//DDRPLL Gate Status Register +#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET 16 +#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK (0x00010000) +#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE 0b0 +#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE 0b1 + +#define PERI0PLL_GATE_STAT_REG 0x00001988//PERI0PLL Gate Status Register +#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 27 +#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK (0x08000000) +#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 26 +#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK (0x04000000) +#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 25 +#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK (0x02000000) +#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 24 +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK (0x01000000) +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 23 +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK (0x00800000) +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 22 +#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK (0x00400000) +#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 21 +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000) +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 20 +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK (0x00100000) +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 19 +#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK (0x00080000) +#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 18 +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000) +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 17 +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK (0x00020000) +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE 0b1 +#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 16 +#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK (0x00010000) +#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE 0b0 +#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE 0b1 + +#define PERI1PLL_GATE_STAT_REG 0x0000198c//PERI1PLL Gate Status Register +#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 27 +#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK (0x08000000) +#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 26 +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK (0x04000000) +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 25 +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK (0x02000000) +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET 24 +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK (0x01000000) +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 23 +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK (0x00800000) +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET 22 +#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK (0x00400000) +#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 21 +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000) +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 20 +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK (0x00100000) +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 19 +#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK (0x00080000) +#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 18 +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000) +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 17 +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK (0x00020000) +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE 0b1 +#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 16 +#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK (0x00010000) +#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE 0b0 +#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE 0b1 + +#define VIDEOPLL_GATE_STAT_REG 0x00001990//VIDEOPLL Gate Status Register +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET 22 +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK (0x00400000) +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE 0b0 +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE 0b1 +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET 21 +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK (0x00200000) +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE 0b0 +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE 0b1 +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET 20 +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK (0x00100000) +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE 0b0 +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE 0b1 +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET 18 +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK (0x00040000) +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE 0b0 +#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE 0b1 +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET 17 +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK (0x00020000) +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE 0b0 +#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE 0b1 +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET 16 +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK (0x00010000) +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE 0b0 +#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE 0b1 + +#define GPUPLL_GATE_STAT_REG 0x00001994//GPUPLL Gate Status Register +#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_OFFSET 16 +#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_CLEAR_MASK (0x00010000) +#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_DISABLE 0b0 +#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_ENABLE 0b1 + +#define VEPLL_GATE_STAT_REG 0x00001998//VEPLL Gate Status Register +#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_OFFSET 17 +#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_CLEAR_MASK (0x00020000) +#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_DISABLE 0b0 +#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_ENABLE 0b1 +#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_OFFSET 16 +#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_CLEAR_MASK (0x00010000) +#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_DISABLE 0b0 +#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_ENABLE 0b1 + +#define AUDIOPLL_GATE_STAT_REG 0x0000199c//AUDIOPLL Gate Status Register +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_OFFSET 18 +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_CLEAR_MASK (0x00040000) +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_DISABLE 0b0 +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_ENABLE 0b1 +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_OFFSET 17 +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_CLEAR_MASK (0x00020000) +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_DISABLE 0b0 +#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_ENABLE 0b1 +#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_OFFSET 16 +#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_CLEAR_MASK (0x00010000) +#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_DISABLE 0b0 +#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_ENABLE 0b1 + +#define NPUPLL_GATE_STAT_REG 0x000019a0//NPUPLL Gate Status Register +#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_OFFSET 16 +#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_CLEAR_MASK (0x00010000) +#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_DISABLE 0b0 +#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_ENABLE 0b1 + +#define DEPLL_GATE_STAT_REG 0x000019a8//DEPLL Gate Status Register +#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_OFFSET 17 +#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_CLEAR_MASK (0x00020000) +#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_DISABLE 0b0 +#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_ENABLE 0b1 +#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_OFFSET 16 +#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_CLEAR_MASK (0x00010000) +#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_DISABLE 0b0 +#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_ENABLE 0b1 + +#define CLK24M_GATE_EN_REG 0x00001a00//CLK24M Gate Enable Register +#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3 +#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK (0x00000008) +#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE 0b0 +#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE 0b1 + +#define CM_VI_CFG_REG 0x00001b00//CM VI Enable Configuration Register +#define CM_VI_CFG_REG_CM_VI_STATUS_OFFSET 16 +#define CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK (0x00030000) +#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF 0b01 +#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON 0b10 +#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET 0 +#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE 0b0 +#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE 0b1 + +#define CM_DESYS_CFG_REG 0x00001b04//CM DESYS Enable Configuration Register +#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_OFFSET 16 +#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_CLEAR_MASK (0x00030000) +#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_OFF 0b01 +#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_ON 0b10 +#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_OFFSET 0 +#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_DISABLE 0b0 +#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_ENABLE 0b1 + +#define CM_VE_DEC_CFG_REG 0x00001b10//CM VE_DEC Enable Configuration Register +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_OFFSET 16 +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_CLEAR_MASK (0x00030000) +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_OFF 0b01 +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_ON 0b10 +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_OFFSET 0 +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_DISABLE 0b0 +#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_ENABLE 0b1 + +#define CM_VE_ENC_CFG_REG 0x00001b14//CM VE_ENC Enable Configuration Register +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_OFFSET 16 +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_CLEAR_MASK (0x00030000) +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_OFF 0b01 +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_ON 0b10 +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_OFFSET 0 +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_DISABLE 0b0 +#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_ENABLE 0b1 + +#define CM_NPU_CFG_REG 0x00001b1c//CM NPU Enable Configuration Register +#define CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET 16 +#define CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK (0x00030000) +#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF 0b01 +#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON 0b10 +#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET 0 +#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE 0b0 +#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE 0b1 + +#define CM_GPU0_CFG_REG 0x00001b24//CM GPU0 Enable Configuration Register +#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_OFFSET 16 +#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_CLEAR_MASK (0x00030000) +#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_OFF 0b01 +#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_ON 0b10 +#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_OFFSET 0 +#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_DISABLE 0b0 +#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_ENABLE 0b1 + +#define CM_PCIE0_CFG_REG 0x00001b28//CM PCIE0 Enable Configuration Register +#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_OFFSET 16 +#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_CLEAR_MASK (0x00030000) +#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_OFF 0b01 +#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_ON 0b10 +#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_OFFSET 0 +#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_DISABLE 0b0 +#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_ENABLE 0b1 + +#define CM_USB2_CFG_REG 0x00001b30//CM USB2 Enable Configuration Register +#define CM_USB2_CFG_REG_CM_USB2_STATUS_OFFSET 16 +#define CM_USB2_CFG_REG_CM_USB2_STATUS_CLEAR_MASK (0x00030000) +#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_OFF 0b01 +#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_ON 0b10 +#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_OFFSET 0 +#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_DISABLE 0b0 +#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_ENABLE 0b1 + +#define CM_VO_CFG_REG 0x00001b34//CM VO Enable Configuration Register +#define CM_VO_CFG_REG_CM_VO_STATUS_OFFSET 16 +#define CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK (0x00030000) +#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF 0b01 +#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON 0b10 +#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET 0 +#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE 0b0 +#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE 0b1 + +#define CM_VO1_CFG_REG 0x00001b38//CM VO1 Enable Configuration Register +#define CM_VO1_CFG_REG_CM_VO1_STATUS_OFFSET 16 +#define CM_VO1_CFG_REG_CM_VO1_STATUS_CLEAR_MASK (0x00030000) +#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_OFF 0b01 +#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_ON 0b10 +#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_OFFSET 0 +#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_CLEAR_MASK (0x00000001) +#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_DISABLE 0b0 +#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_ENABLE 0b1 + +#define APB2JTAG_CLK_REG 0x00001c00//APB2JTAG Clock Register +#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_OFFSET 31 +#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLEAR_MASK (0x80000000) +#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_OFF 0b0 +#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_ON 0b1 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_OFFSET 24 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000) +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK32K 0b001 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b101 +#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110 +#define APB2JTAG_CLK_REG_FACTOR_M_OFFSET 0 +#define APB2JTAG_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f) + +#define APB2JTAG_BGR_REG 0x00001c04//APB2JTAG Bus Gating Reset Register +#define APB2JTAG_BGR_REG_APB2JTAG_RST_OFFSET 16 +#define APB2JTAG_BGR_REG_APB2JTAG_RST_CLEAR_MASK (0x00010000) +#define APB2JTAG_BGR_REG_APB2JTAG_RST_ASSERT 0b0 +#define APB2JTAG_BGR_REG_APB2JTAG_RST_DE_ASSERT 0b1 + +#define CCU_SEC_SWITCH_REG 0x00001f00//CCU Security Switch Register +#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2 +#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK (0x00000004) +#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0b0 +#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0b1 +#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1 +#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK (0x00000002) +#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0b0 +#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0b1 +#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0 +#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK (0x00000001) +#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0b0 +#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0b1 + +#define SYSDAP_REQ_CTRL_REG 0x00001f10//SYSDAP REQ Control Register +#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0 +#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK (0x00000001) + +#define PLL_CFG0_REG 0x00001f20//PLL Configuration0 Register +#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0 +#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK (0xffffffff) + +#define PLL_CFG1_REG 0x00001f24//PLL Configuration1 Register +#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0 +#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK (0xffffffff) + +#define PLL_CFG2_REG 0x00001f28//PLL Configuration2 Register +#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0 +#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK (0xffffffff) + +#define PLL_LOCK_DBG_CTRL_REG 0x00001f2c//PLL Lock Debug Control Register +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK (0x80000000) +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0b0 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0b1 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK (0x07f00000) +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_REFPLL 0b0000000 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL 0b0000001 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL 0b0000010 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL 0b0000011 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_GPU0PLL 0b0000100 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL 0b0000101 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL 0b0000110 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL 0b0000111 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE0PLL 0b0001001 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE1PLL 0b0001010 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL 0b0001011 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL 0b0001100 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DEPLL 0b0001101 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL 0b0100000 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL 0b1000000 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL 0b1000001 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU2PLL 0b1000010 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU3PLL 0b1000011 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL0 0b1100000 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL1 0b1100001 +#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_HDMIPLL 0b1110000 + +#define CCU_FAN_GATE_REG 0x00001f30//CCU FANOUT CLOCK GATE Register +#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3 +#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK (0x00000008) +#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0b1 +#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2 +#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK (0x00000004) +#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0b1 +#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1 +#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK (0x00000002) +#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0b1 +#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0 +#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK (0x00000001) +#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0b1 + +#define CLK27M_FAN_REG 0x00001f34//CLK27M FANOUT Register +#define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31 +#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK (0x80000000) +#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0b0 +#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0b1 +#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24 +#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK (0x03000000) +#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X 0b000 +#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X 0b001 +#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X 0b010 +#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8 +#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK (0x00001f00) +#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0 +#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK (0x0000001f) + +#define CLK_FAN_REG 0x00001f38//CLK FANOUT Register +#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31 +#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK (0x80000000) +#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0b0 +#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0b1 +#define CLK_FAN_REG_PCLK_DIV1_OFFSET 5 +#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK (0x000003e0) +#define CLK_FAN_REG_PCLK_DIV_OFFSET 0 +#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK (0x0000001f) + +#define CCU_FAN_REG 0x00001f3c//CCU FANOUT Register +#define CCU_FAN_REG_CLK_FANOUT3_EN_OFFSET 24 +#define CCU_FAN_REG_CLK_FANOUT3_EN_CLEAR_MASK (0x01000000) +#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_ON 0b1 +#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23 +#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK (0x00800000) +#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON 0b1 +#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22 +#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK (0x00400000) +#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON 0b1 +#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21 +#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK (0x00200000) +#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF 0b0 +#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON 0b1 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_OFFSET 9 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLEAR_MASK (0x00000e00) +#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK16M_FROM_PERI0_160M_10 0b010 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK24M_FROM_SYS_CLK24M 0b011 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK25M_FROM_PERI0_150M_6 0b100 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK27M 0b101 +#define CCU_FAN_REG_CLK_FANOUT3_SEL_PCLK 0b110 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK (0x000001c0) +#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10 0b010 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_SYS_CLK24M 0b011 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6 0b100 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M 0b101 +#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK 0b110 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK (0x00000038) +#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10 0b010 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_SYS_CLK24M 0b011 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6 0b100 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M 0b101 +#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK 0b110 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK (0x00000007) +#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10 0b010 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_SYS_CLK24M 0b011 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6 0b100 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M 0b101 +#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK 0b110 + +#define BUS_CLK_DBG_REG 0x00001f50//Bus Clock Debug Register +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET 0 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK (0x00000007) +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK 0b000 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK 0b001 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK 0b010 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK 0b011 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK 0b100 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK 0b101 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR0_CLK 0b110 +#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_HDR0_CLK 0b111 + +#define CCU_VERSION_REG 0x00001ff0//CCU Version Register +#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16 +#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK (0xffff0000) +#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0 +#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK (0x0000ffff) + +/* cpu pll */ +#define PLL_CPU_CTRL_REG_PLL_EN_OFFSET 31 +#define PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET 30 +#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET 29 +#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27 + +#define APB2_CLK_RATE_N_1 (0x0 << 8) +#define APB2_CLK_RATE_N_2 (0x1 << 8) +#define APB2_CLK_RATE_N_4 (0x2 << 8) +#define APB2_CLK_RATE_N_8 (0x3 << 8) +#define APB2_CLK_RATE_N_MASK (3 << 8) +#define APB2_CLK_RATE_M(m) (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET) +#define APB2_CLK_RATE_M_MASK (3 << APB1_CLK_REG_FACTOR_M_OFFSET) + +#define SUNXI_MEMC_CLK_RST (SUNXI_MEMC_COMMON_BASE + 0x10) +#define MEMC_REG_PLLREF_CLK_EN (1U << 13) +#define MEMC_REG_HDR_CLK1_EN (1U << 10) +#define MEMC_REG_HDR_CLK0_EN (1U << 9) +#define MEMC_REG_HCLK1_EN (1U << 8) +#define CCU_MMC_CTRL_M(x) (x) +#define CCU_MMC_CTRL_N(x) ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET) +#define CCU_MMC_CTRL_OSCM24 (SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PLL6X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PLL_PERIPH2X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI0_400M_freq (400000000) +#define CCU_MMC_CTRL_PERI0_300M_freq (300000000) +#define CCU_MMC_CTRL_PERI0_800M_freq (800000000) +#define CCU_MMC_CTRL_PERI0_600M_freq (600000000) +#define CCU_MMC_CTRL_PERI0_400M (0x1 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI0_300M (0x2 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI0_800M (0x1 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI0_600M (0x2 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI1_400M (0x3 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI1_300M (0x4 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI1_800M (0x3 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_PERI1_600M (0x4 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CCU_MMC_CTRL_ENABLE (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET) +/* if doesn't have these delays */ +#define CCU_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) +#define CCU_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) + +/* Module gate/reset shift*/ +#define RESET_SHIFT (16) +#define GATING_SHIFT (0) + +/*CE*/ +#define CE_CLK_SRC_MASK (0x7) +#define CE_CLK_SRC_SEL_BIT (CE_CLK_REG_CLK_SRC_SEL_OFFSET) +#define CE_CLK_SRC (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M) + +#define CE_CLK_DIV_RATION_N_BIT (8) +#define CE_CLK_DIV_RATION_N_MASK (0x3) +#define CE_CLK_DIV_RATION_N (0) + +#define CE_CLK_DIV_RATION_M_BIT (CE_CLK_REG_FACTOR_M_OFFSET) +//@TODO +#define CE_CLK_DIV_RATION_M_MASK (CE_CLK_REG_FACTOR_M_CLEAR_MASK) +#define CE_CLK_DIV_RATION_M (0) + +#define CE_SCLK_ONOFF_BIT (CE_CLK_REG_CE_CLK_GATING_OFFSET) +//@TODO +#define CE_SCLK_ON (CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF) + +//@TODO +#define CE_GATING_PASS (CE_BGR_REG_CE_GATING_MASK) +#define CE_GATING_BIT (CE_BGR_REG_CE_GATING_OFFSET) + +#define CE_RST_BIT (CE_BGR_REG_CE_RST_OFFSET) +//@TODO +#define CE_DEASSERT (CE_BGR_REG_CE_SYS_RST_ASSERT) +#define CE_SYS_RST_BIT (CE_BGR_REG_CE_SYS_RST_OFFSET) +#define CE_SYS_GATING_BIT (CE_BGR_REG_CE_SYS_GATING_OFFSET) + +#define CE_MBUS_GATING_MASK (1) +#define CE_MBUS_GATING_BIT (MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET) +#define CE_MBUS_GATING (1) + +#define USBEHCI0_RST_BIT 20 +#define USBEHCI0_GATIING_BIT 4 +#define USBPHY0_RST_BIT 30 +#define USBPHY0_SCLK_GATING_BIT 31 + +#define USBEHCI1_RST_BIT 20 +#define USBEHCI1_GATIING_BIT 4 +#define USBPHY1_RST_BIT 30 +#define USBPHY1_SCLK_GATING_BIT 31 + +#define CCU_PLL_CPU_L_CTRL_REG (SUNXI_CPU_PLL_CFG_BASE + 0x1000) +#define CCU_PLL_CPU_L_CLK_REG (SUNXI_CPU_PLL_CFG_BASE + 0x101c) +#define CCU_PLL_CPU_B_CTRL_REG (SUNXI_CPU_PLL_CFG_BASE + 0x2000) +#define CCU_PLL_CPU_B_CLK_REG (SUNXI_CPU_PLL_CFG_BASE + 0x201c) +#define CCU_PLL_CPU_DSU_CTRL_REG (SUNXI_CPU_PLL_CFG_BASE + 0x3000) +#define CCU_PLL_DSU_CLK_REG (SUNXI_CPU_PLL_CFG_BASE + 0x301c) + +/* storage */ +#define CCU_MBUS_MST_CLK_GATING_REG (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG) +#define CCU_MBUS_GATE_ENABLE_REG (SUNXI_CCU_BASE + MBUS_GATE_EN_REG) + +#define CCU_SDMMC0_CLK_REG (SUNXI_CCU_BASE + SMHC0_CLK_REG) +#define CCU_SDMMC1_CLK_REG (SUNXI_CCU_BASE + SMHC1_CLK_REG) +#define CCU_SDMMC2_CLK_REG (SUNXI_CCU_BASE + SMHC2_CLK_REG) +#define CCU_SMHC0_BGR_REG (SUNXI_CCU_BASE + SMHC0_BGR_REG) +/* nsi */ +#define CCU_NSI_CLK_GREG (SUNXI_CCU_BASE + NSI_CLK_REG) +#define CCU_NSI_BGR_REG (SUNXI_CCU_BASE + NSI_BGR_REG) +#define CCU_PLL_PERI0_CTRL_REG (SUNXI_CCU_BASE + PLL_PERI0_CTRL_REG) +#define CCU_PLL_PERI1_CTRL_REG (SUNXI_CCU_BASE + PLL_PERI1_CTRL_REG) + +/*normal interface*/ +#define CCU_UART_BGR_REG (SUNXI_CCU_BASE + UART0_BGR_REG) + +/*DMA*/ +#define DMA_GATING_BASE CCU_DMA_BGR_REG +#define DMA_GATING_PASS (1) +#define DMA_GATING_BIT (0) + +/*gpadc gate and reset reg*/ +#define CCU_GPADC_BGR_REG (SUNXI_CCU_BASE + GPADC0_BGR_REG) +#define CCU_GPADC_24M_REG (SUNXI_CCU_BASE + GPADC0_24M_CLK_REG) + +/*lpadc gate and reset reg*/ +#define CCU_LRADC_BGR_REG (SUNXI_CCU_BASE + LRADC_BGR_REG) + +/* RTC */ +#define RTC_LOSC_CTRL_REG (SUNXI_RTC_BASE) +#define XO_CONTROL0_REG 0x0160 +#define RTC_XO_CONTROL0_REG (SUNXI_RTC_BASE + XO_CONTROL0_REG) + +#define LOSC_CONTROL_KEY_FIFLD 0x16aa0000 +#define LOSC_AUTO_SWT_32K_SEL_EN_MASK (0x00004000) +#define LOSC_AUTO_SWT_32K_SEL_EN (1U << 14) +#define LOSC_AUTO_SWT_32K_SEL_DISABLE (0U << 14) +#define EXT_LOSC_GSM_HIGH (0x0000000C) +#define LOSC_SRC_SEL_MASK (0x00000001) +#define LOSC_SRC_SEL_32K (1U << 0) +#define LOSC_SRC_SEL_16M (0U << 0) + + +#endif// __SUN60IW2_REG_CCU_H__ diff --git a/include/drivers/chips/sun60iw2/reg-ncat.h b/include/drivers/chips/sun60iw2/reg-ncat.h new file mode 100644 index 000000000..cc0cc897e --- /dev/null +++ b/include/drivers/chips/sun60iw2/reg-ncat.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SUN60IW2_REG_NCAT_H__ +#define __SUN60IW2_REG_NCAT_H__ + +#define SUNXI_FIXS_BROM_BASE 0x00000000 +#define SUNXI_HS_BROM_BASE 0x00011000 +#define SUNXI_NS_BROM_BASE 0x00017000 +#define SUNXI_DSP0_IRAM_BASE 0x00020000 +#define SUNXI_DSP0_DRAM0_BASE 0x00030000 +#define SUNXI_DSP0_DRAM1_BASE 0x00038000 +#define SUNXI_SRAM_A2_BASE 0x00044000 +#define SUNXI_DSP0_IRAM_LOCAL_SRAM__BASE 0x00400000 +#define SUNXI_DSP0_DRAM0_LOCAL_SRAM__BASE 0x00420000 +#define SUNXI_DSP0_DRAM1_LOCAL_SRAM__BASE 0x00440000 +#define SUNXI_GPU0_BASE 0x01800000 +#define SUNXI_VE_DEC_BASE 0x01C0E000 +#define SUNXI_VE_ENC0_BASE 0x01C10000 +#define SUNXI_VE_ENC1_BASE 0x01C11000 +#define SUNXI_GPIO_OS0__BASE 0x02000000 +#define SUNXI_GPIO_OS1__BASE 0x02001000 +#define SUNXI_CCMU_OS0__BASE 0x02002000 +#define SUNXI_CCMU_OS1__BASE 0x02004000 +#define SUNXI_LEDC_BASE 0x02008000 +#define SUNXI_GPADC_BASE 0x02009000 +#define SUNXI_THS_BASE 0x0200A000 +#define SUNXI_LRADC0_BASE 0x0200B000 +#define SUNXI_GPADC1_BASE 0x0200C000 +#define SUNXI_NSI_BASE 0x02020000 +#define SUNXI_AUDIO_SYS_BASE 0x02031000 +#define SUNXI_I2S1_BASE 0x02031000 +#define SUNXI_I2S2_BASE 0x02032000 +#define SUNXI_I2S3_BASE 0x02033000 +#define SUNXI_I2S4_BASE 0x02034000 +#define SUNXI_I2S5_BASE 0x02035000 +#define SUNXI_SPDIF0_BASE 0x02036000 +#define SUNXI_WDT0_BASE 0x02050000 +#define SUNXI_WDT1_BASE 0x02051000 +#define SUNXI_PWM0_BASE 0x02052000 +#define SUNXI_PWM1_BASE 0x02053000 +#define SUNXI_SPC_BASE 0x02054000 +#define SUNXI_NPD_BASE 0x02070000 +#define SUNXI_NSI_CPU0_BASE 0x02071000 +#define SUNXI_NSI_SBR_BASE 0x02072000 +#define SUNXI_NPU_TZMA_BASE 0x02073000 +#define SUNXI_AIPU_DBG_BASE 0x02074000 +#define SUNXI_IRTX_BASE 0x02075000 +#define SUNXI_IRRX_BASE 0x02076000 +#define SUNXI_UART0_BASE 0x02500000 +#define SUNXI_UART1_BASE 0x02501000 +#define SUNXI_UART2_BASE 0x02502000 +#define SUNXI_UART3_BASE 0x02503000 +#define SUNXI_UART4_BASE 0x02504000 +#define SUNXI_UART5_BASE 0x02505000 +#define SUNXI_UART6_BASE 0x02506000 +#define SUNXI_UART7_BASE 0x02507000 +#define SUNXI_UART8_BASE 0x02508000 +#define SUNXI_TWI0_BASE 0x02700000 +#define SUNXI_TWI1_BASE 0x02701000 +#define SUNXI_TWI2_BASE 0x02702000 +#define SUNXI_TWI3_BASE 0x02703000 +#define SUNXI_TWI4_BASE 0x02704000 +#define SUNXI_TWI5_BASE 0x02705000 +#define SUNXI_TWI6_BASE 0x02706000 +#define SUNXI_TWI7_BASE 0x02707000 +#define SUNXI_TWI8_BASE 0x02708000 +#define SUNXI_LBC_BASE 0x02600000 +#define SUNXI_SYSCTRL_BASE 0x03000000 +#define SUNXI_DMAC_OS0__BASE 0x03002000 +#define SUNXI_DMAC_OS1__BASE 0x03003000 +#define SUNXI_CPUX_MSGBOX_BASE 0x03004000 +#define SUNXI_SPINLOCK_BASE 0x03005000 +#define SUNXI_SID_BASE 0x03006000 +#define SUNXI_TIMER0_BASE 0x03009000 +#define SUNXI_TIMER1_BASE 0x0300A000 +#define SUNXI_DCU_BASE 0x03010000 +#define SUNXI_CE_SYS_BASE 0x03040000 +#define SUNXI_CE_NS_BASE 0x03040000 +#define SUNXI_CE_S_BASE 0x03040800 +#define SUNXI_CE_KEY_SRAM_BASE 0x03041400 +#define SUNXI_SECURE_DEBUG_CFG_BASE 0x03042000 +#define SUNXI_KEYSRAM_DEBUG_BASE 0x03042400 +#define SUNXI_AIPU_BASE 0x03050000 +#define SUNXI_CPU_GIC600_BASE 0x03400000 +#define SUNXI_NPU_BASE 0x03600000 +#define SUNXI_CCI_BASE 0x03700000 +#define SUNXI_MSI_LITE0_BASE 0x03800000 +#define SUNXI_MSI_LITE1_BASE 0x03801000 +#define SUNXI_SMMU_BASE 0x03900000 +#define SUNXI_CPU0_MSGBOX_OS0__BASE 0x03C42000 +#define SUNXI_CPU0_MSGBOX_OS1__BASE 0x03C43000 +#define SUNXI_CPU1_MSGBOX_OS0__BASE 0x03C44000 +#define SUNXI_CPU1_MSGBOX_OS1__BASE 0x03C45000 +#define SUNXI_DMAC1_OS0__BASE 0x03C46000 +#define SUNXI_DMAC1_OS1__BASE 0x03C47000 +#define SUNXI_NAND_BASE 0x04011000 +#define SUNXI_SMHC0_BASE 0x04020000 +#define SUNXI_SMHC1_BASE 0x04021000 +#define SUNXI_SMHC2_BASE 0x04022000 +#define SUNXI_SMHC3_BASE 0x04023000 +#define SUNXI_SPI0_BASE 0x04025000 +#define SUNXI_SPI1_BASE 0x04026000 +#define SUNXI_SPI2_BASE 0x04027000 +#define SUNXI_USB0_BASE 0x04100000 +#define SUNXI_USB1_BASE 0x04200000 +#define SUNXI_USB2_BASE 0x04300000 +#define SUNXI_GMAC0_BASE 0x04500000 +#define SUNXI_GMAC1_BASE 0x04510000 +#define SUNXI_UFS_BASE 0x04520000 +#define SUNXI_SPI_FLASH_BASE 0x047F0000 +#define SUNXI_PCIE0_BASE 0x06000000 +#define SUNXI_PCIE1_BASE 0x06500000 +#define SUNXI_USB3_1_BASE 0x06A00000 +#define SUNXI_SERDES_SYS_BASE 0x06C00000 +#define SUNXI_COMBPHY0_BASE 0x06C80000 +#define SUNXI_COMBPHY1_BASE 0x06CA0000 +#define SUNXI_MEMC0_BASE 0x0A000000 +#define SUNXI_DE0_BASE 0x05000000 +#define SUNXI_DI_BASE 0x05400000 +#define SUNXI_G2D_BASE 0x05440000 +#define SUNXI_DE1_BASE 0x0D000000 +#define SUNXI_DISPLAY0_TOP_BASE 0x05500000 +#define SUNXI_TCON_LCD0_BASE 0x05501000 +#define SUNXI_TCON_LCD1_BASE 0x05502000 +#define SUNXI_TCON_LCD2_BASE 0x05503000 +#define SUNXI_TCON_LCD3_BASE 0x05504000 +#define SUNXI_DSI0_BASE 0x05506000 +#define SUNXI_DSI1_BASE 0x05508000 +#define SUNXI_DISPLAY1_TOP_BASE 0x05510000 +#define SUNXI_HDMI_BASE 0x05520000 +#define SUNXI_EDP0_BASE 0x05720000 +#define SUNXI_TCON_TV0_BASE 0x05730000 +#define SUNXI_TCON_TV1_BASE 0x05731000 +#define SUNXI_TCON_TV2_BASE 0x05732000 +#define SUNXI_CSI_BASE 0x05800000 +#define SUNXI_ISP_BASE 0x05900000 +#define SUNXI_R_SPC_BASE 0x07002000 +#define SUNXI_R_TZMA_BASE 0x07003000 +#define SUNXI_R_PRCM_BASE 0x07010000 +#define SUNXI_R_WDG_BASE 0x07021000 +#define SUNXI_R_TWD_BASE 0x07022000 +#define SUNXI_R_PWM_BASE 0x07023000 +#define SUNXI_R_INTC_BASE 0x07024000 +#define SUNXI_R_GPIO_OS0__BASE 0x07025000 +#define SUNXI_R_GPIO_OS1__BASE 0x07026000 +#define SUNXI_CPUS_BIST_BASE 0x07031000 +#define SUNXI_R_IRRX_BASE 0x07040000 +#define SUNXI_CPUIDLE_BASE 0x07050000 +#define SUNXI_PCK600_QCHANNEL_BASE 0x07060000 +#define SUNXI_R_UART0_BASE 0x07080000 +#define SUNXI_R_UART1_BASE 0x07081000 +#define SUNXI_R_UART2_BASE 0x07082000 +#define SUNXI_R_TWI0_BASE 0x07083000 +#define SUNXI_R_TWI1_BASE 0x07084000 +#define SUNXI_R_TWI2_BASE 0x07085000 +#define SUNXI_RTC_BASE 0x07090000 +#define SUNXI_R_TIMER_BASE 0x07091000 +#define SUNXI_R_SPI_BASE 0x07092000 +#define SUNXI_R_MBOX_BASE 0x07094000 +#define SUNXI_RISCV_CFG_BASE 0x07130000 +#define SUNXI_RISCV_WDG_BASE 0x07132000 +#define SUNXI_RISCV_LCNT_BASE 0x07134000 +#define SUNXI_RISCV_MBOX_BASE 0x07136000 +#define SUNXI_RISCV_TIMER_BASE 0x07138000 +#define SUNXI_MCU_PRCM_BASE 0x07140000 +#define SUNXI_MCU_TZMA0_BASE 0x07141000 +#define SUNXI_MCU_TZMA1_BASE 0x07142000 +#define SUNXI_MCU_I2S_BASE 0x07143000 +#define SUNXI_MCU_DMIC_BASE 0x07144000 +#define SUNXI_MCU_DMA_OS0__BASE 0x07150000 +#define SUNXI_MCU_DMA_OS1__BASE 0x07151000 +#define SUNXI_MCU_SPINLOCK_BASE 0x07152000 +#define SUNXI_MSI_LITE2_BASE 0x07153000 +#define SUNXI_MCU_SRAM0_BASE 0x07200000 +#define SUNXI_MCU_SRAM1_BASE 0x07280000 +#define SUNXI_DSP_CFG_BASE 0x07300000 +#define SUNXI_DSP_WDG_BASE 0x07301000 +#define SUNXI_DSP_INTC_BASE 0x07302000 +#define SUNXI_DSP_TZMA_BASE 0x07303000 +#define SUNXI_DSP_MSGBOX_BASE 0x07320000 +#define SUNXI_DSP_TIMER_BASE 0x07323000 +#define SUNXI_NPU_MEM_BASE 0x01700000 +#define SUNXI_CPU_SUBSYS_CTRL_BASE 0x08000000 +#define SUNXI_TIMESTAMP_STA_BASE 0x08010000 +#define SUNXI_TIMESTAMP_CTRL_BASE 0x08020000 +#define SUNXI_APB_ROM1_BASE 0x08801000 +#define SUNXI_CTI_BASE 0x08803000 +#define SUNXI_CS_TS_CTRL_BASE 0x08805000 +#define SUNXI_CS_TS_READ_BASE 0x08807000 +#define SUNXI_TPIU_BASE 0x08809000 +#define SUNXI_ETB_BASE 0x0880B000 +#define SUNXI_APB_ROM2_BASE 0x08841000 +#define SUNXI_ATB_FUNNEL_BASE 0x08843000 +#define SUNXI_CLUSTER_CFG_BASE 0x08860000 +#define SUNXI_CPU_PLL_CFG_BASE 0x08870000 +#define SUNXI_CLUSTER_DBUG_BASE 0x09800000 +#define SUNXI_SPI_FLASH_XIP_BASE 0x0E000000 +#define SUNXI_LBC_DIRECT_BASE 0x10000000 +#define SUNXI_PCIE_SLV0_BASE 0x20000000 +#define SUNXI_PCIE_SLV1_BASE 0x28000000 +#define SUNXI_RISCV 0XE0000000 +#define SUNXI_RISCV_CLINT_BASE 0xE0000000 +#define SUNXI_RISCV_CLIC_BASE 0xE0800000 +#define SUNXI_RISCV_SYSMAP_BASE 0xEFFFF000 + +#define SUNXI_TIMER_BASE (SUNXI_TIMER0_BASE) +#define SUNXI_GIC600_BASE (SUNXI_CPU_GIC600_BASE) +#define SUNXI_DMAC_BASE (SUNXI_DMAC_OS0__BASE) +#define SUNXI_MMC0_BASE (SUNXI_SMHC0_BASE) +#define SUNXI_MMC1_BASE (SUNXI_SMHC1_BASE) +#define SUNXI_MMC2_BASE (SUNXI_SMHC2_BASE) +#define SUNXI_USBOTG_BASE (SUNXI_USB0_BASE) +#define SUNXI_PIO_BASE (SUNXI_GPIO_OS0__BASE) +#define SUNXI_R_PIO_BASE (SUNXI_R_GPIO_OS0__BASE) +#define SUNXI_CCU_BASE (SUNXI_CCMU_OS0__BASE) +#define SUNXI_DMA_BASE (SUNXI_DMAC_BASE) +#define SUNXI_CE_BASE (SUNXI_CE_NS_BASE) +#define SUNXI_SS_BASE (SUNXI_CE_BASE) +#define SUNXI_CPUXCFG_BASE (SUNXI_CPU_SUBSYS_CTRL_BASE) +#define SUNXI_SYSCRL_BASE (SUNXI_SYSCTRL_BASE) +#define SUNXI_RPRCM_BASE (SUNXI_R_PRCM_BASE) +#define SUNXI_RPWM_BASE (SUNXI_R_PWM_BASE) +#define SUNXI_RPIO_BASE (SUNXI_R_GPIO_OS0__BASE) +#define SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200) + +#define SUNXI_RTWI_BASE (SUNXI_R_TWI0_BASE) +#define SUNXI_RTWI_BRG_REG (SUNXI_RPRCM_BASE + 0x019c) +#define SUNXI_RTWI0_RST_BIT (16) +#define SUNXI_RTWI0_GATING_BIT (0) +#define SUNXI_RST_BIT (16) +#define SUNXI_GATING_BIT (0) +#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100) + +#define SUNXI_CPUS_CFG_BASE (0x07000400U) +#define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE) + +/* use for usb correct */ +#define VDD_SYS_PWROFF_GATING_REG (SUNXI_RPRCM_BASE + 0x250) +#define RES_CAL_CTRL_REG (SUNXI_RPRCM_BASE + 0X310) +#define VDD_ADDA_OFF_GATING (9) +#define CAL_ANA_EN (1) +#define CAL_EN (0) + +#define RVBARADDR0_L (SUNXI_CPUXCFG_BASE + 0x40) +#define RVBARADDR0_H (SUNXI_CPUXCFG_BASE + 0x44) + +#define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0) +#define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4) + +#define GPIO_BIAS_MAX_LEN (32) +#define GPIO_BIAS_MAIN_NAME "gpio_bias" +#define GPIO_POW_MODE_REG (0x0340) +#define GPIO_POW_MODE_VAL_REG (0x0348) +#define GPIO_3_3V_MODE 0 +#define GPIO_1_8V_MODE 1 + +#endif// __SUN60IW2_REG_NCAT_H__ diff --git a/include/drivers/chips/sun60iw2/reg-rproc.h b/include/drivers/chips/sun60iw2/reg-rproc.h new file mode 100644 index 000000000..e3ba82678 --- /dev/null +++ b/include/drivers/chips/sun60iw2/reg-rproc.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __REG_RPROC_H__ +#define __REG_RPROC_H__ + + + +#endif// __REG_RPROC_H__ \ No newline at end of file diff --git a/include/drivers/chips/sun8iw20/reg-ccu.h b/include/drivers/chips/sun8iw20/reg-ccu.h index 15a93a57d..77b81d621 100644 --- a/include/drivers/chips/sun8iw20/reg-ccu.h +++ b/include/drivers/chips/sun8iw20/reg-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN8IW20_REG_CCU_H__ #define __SUN8IW20_REG_CCU_H__ diff --git a/include/drivers/chips/sun8iw20/reg-rproc.h b/include/drivers/chips/sun8iw20/reg-rproc.h index 2604bf436..684addaa5 100644 --- a/include/drivers/chips/sun8iw20/reg-rproc.h +++ b/include/drivers/chips/sun8iw20/reg-rproc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_RPROC_H__ #define __REG_RPROC_H__ diff --git a/include/drivers/chips/sun8iw21/reg-ccu.h b/include/drivers/chips/sun8iw21/reg-ccu.h index 0107aa955..8b35cac20 100644 --- a/include/drivers/chips/sun8iw21/reg-ccu.h +++ b/include/drivers/chips/sun8iw21/reg-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN8IW21_REG_CCU_H__ #define __SUN8IW21_REG_CCU_H__ diff --git a/include/drivers/chips/sun8iw21/reg-rproc.h b/include/drivers/chips/sun8iw21/reg-rproc.h index 8eb190669..de647054b 100644 --- a/include/drivers/chips/sun8iw21/reg-rproc.h +++ b/include/drivers/chips/sun8iw21/reg-rproc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SUN8IW21_REG_RPROC_H__ #define __SUN8IW21_REG_RPROC_H__ diff --git a/include/drivers/intc/sys-gic.h b/include/drivers/intc/sys-gic.h new file mode 100644 index 000000000..90a934351 --- /dev/null +++ b/include/drivers/intc/sys-gic.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SYS_GIC_H_ +#define _SYS_GIC_H_ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif// __cplusplus + +/** + * @brief Handles the IRQ with ARM registers + * + * @param regs Pointer to the ARM registers + */ +void do_irq(struct arm_regs_t *regs); + +/** + * @brief Initializes the interrupt mechanism + * + * @return 0 on success, or an error code + */ +int arch_interrupt_init(void); + +/** + * @brief Exits the interrupt mechanism + * + * @return 0 on success, or an error code + */ +int arch_interrupt_exit(void); + +/** + * @brief Initializes the Sunxi GIC CPU interface + * + * @param cpu CPU identifier + * @return 0 on success, or an error code + */ +int sunxi_gic_cpu_interface_init(int cpu); + +/** + * @brief Exits the Sunxi GIC CPU interface + * + * @return 0 on success, or an error code + */ +int sunxi_gic_cpu_interface_exit(void); + +#ifdef __cplusplus +} +#endif// __cplusplus + +#endif// _SYS_GIC_H_ \ No newline at end of file diff --git a/include/drivers/sys-gic.h b/include/drivers/intc/sys-intc.h similarity index 63% rename from include/drivers/sys-gic.h rename to include/drivers/intc/sys-intc.h index 91a182059..703d6f766 100644 --- a/include/drivers/sys-gic.h +++ b/include/drivers/intc/sys-intc.h @@ -1,7 +1,7 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SYS_GIC_H_ -#define _SYS_GIC_H_ +#ifndef _SYS_INTC_H_ +#define _SYS_INTC_H_ #include #include @@ -13,10 +13,6 @@ #include #include -#include - -#include "reg-gic.h" - #ifdef __cplusplus extern "C" { #endif// __cplusplus @@ -48,42 +44,6 @@ typedef void(interrupt_handler_t)(void *); */ void irq_install_handler(int irq, interrupt_handler_t handle_irq, void *data); -/** - * @brief Handles the IRQ with ARM registers - * - * @param regs Pointer to the ARM registers - */ -void do_irq(struct arm_regs_t *regs); - -/** - * @brief Initializes the interrupt mechanism - * - * @return 0 on success, or an error code - */ -int arch_interrupt_init(void); - -/** - * @brief Exits the interrupt mechanism - * - * @return 0 on success, or an error code - */ -int arch_interrupt_exit(void); - -/** - * @brief Initializes the Sunxi GIC CPU interface - * - * @param cpu CPU identifier - * @return 0 on success, or an error code - */ -int sunxi_gic_cpu_interface_init(int cpu); - -/** - * @brief Exits the Sunxi GIC CPU interface - * - * @return 0 on success, or an error code - */ -int sunxi_gic_cpu_interface_exit(void); - /** * @brief Frees the resources associated with the specified IRQ handler * @@ -111,4 +71,4 @@ int irq_disable(int irq_no); } #endif// __cplusplus -#endif// _SYS_GIC_H_ \ No newline at end of file +#endif// _SYS_INTC_H_ \ No newline at end of file diff --git a/include/drivers/mmc/sys-sdhci.h b/include/drivers/mmc/sys-sdhci.h index 5b10c8d0b..66d4ce5fc 100644 --- a/include/drivers/mmc/sys-sdhci.h +++ b/include/drivers/mmc/sys-sdhci.h @@ -201,6 +201,28 @@ int sunxi_sdhci_xfer(sunxi_sdhci_t *sdhci, mmc_cmd_t *cmd, mmc_data_t *data); */ void sunxi_sdhci_dump_reg(sunxi_sdhci_t *sdhci); +/* Internal Use */ +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +extern int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz); + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +extern uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci); + #ifdef __cplusplus } #endif// __cplusplus diff --git a/include/drivers/mtd/sys-spi-nand.h b/include/drivers/mtd/sys-spi-nand.h index 0f0a657bb..5c34cc6b3 100644 --- a/include/drivers/mtd/sys-spi-nand.h +++ b/include/drivers/mtd/sys-spi-nand.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_SPI_NAND_H__ #define __SYS_SPI_NAND_H__ diff --git a/include/drivers/mtd/sys-spi-nor.h b/include/drivers/mtd/sys-spi-nor.h index 21d5ebffe..d705e3818 100644 --- a/include/drivers/mtd/sys-spi-nor.h +++ b/include/drivers/mtd/sys-spi-nor.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_SPI_NOR_H__ #define __SYS_SPI_NOR_H__ diff --git a/include/drivers/pmu/reg-axp.h b/include/drivers/pmu/reg-axp.h index 0fbf9b57c..b82c1b585 100644 --- a/include/drivers/pmu/reg-axp.h +++ b/include/drivers/pmu/reg-axp.h @@ -15,6 +15,7 @@ extern "C" { #include "reg/reg-axp1530.h" #include "reg/reg-axp2202.h" #include "reg/reg-axp2101.h" +#include "reg/reg-axp8191.h" #ifdef __cplusplus } diff --git a/include/drivers/pmu/reg/reg-axp8191.h b/include/drivers/pmu/reg/reg-axp8191.h new file mode 100644 index 000000000..e97b1982d --- /dev/null +++ b/include/drivers/pmu/reg/reg-axp8191.h @@ -0,0 +1,179 @@ +#ifndef __REG_AXP8191_H__ +#define __REG_AXP8191_H__ + +/* AXP8191 AXP318W */ +#define AXP8191_RUNTIME_ADDR (0x36) + +/* define AXP8191 REGISTER */ +#define AXP8191_IC_TYPE (0x03) +#define AXP8191_CHIP_ID (0x0E) +#define AXP8191_CHIP_VER (0x0F) +#define AXP8191_DCDC_POWER_ON_OFF_CTL1 (0x10) +#define AXP8191_DCDC_POWER_ON_OFF_CTL2 (0x11) + +#define AXP8191_DC1OUT_VOL (0x12) +#define AXP8191_DC2OUT_VOL (0x13) +#define AXP8191_DC3OUT_VOL (0x14) +#define AXP8191_DC4OUT_VOL (0x15) +#define AXP8191_DC5OUT_VOL (0x16) +#define AXP8191_DC6OUT_VOL (0x17) +#define AXP8191_DC7OUT_VOL (0x18) +#define AXP8191_DC8OUT_VOL (0x19) +#define AXP8191_DC9OUT_VOL (0x1A) + +#define AXP8191_DCDC_MODE_CTL1 (0x1B) +#define AXP8191_DCDC_MODE_CTL2 (0x1C) +#define AXP8191_DCDC_MODE_CTL3 (0x1D) +#define AXP8191_DCDC_MODE_CTL4 (0x1E) + +#define AXP8191_DC8SET_STATUS (0x1F) + +#define AXP8191_LDO_POWER_ON_OFF_CTL1 (0x20) +#define AXP8191_LDO_POWER_ON_OFF_CTL2 (0x21) +#define AXP8191_LDO_POWER_ON_OFF_CTL3 (0x22) +#define AXP8191_LDO_POWER_ON_OFF_CTL4 (0x23) + +#define AXP8191_ALDO1OUT_VOL (0x24) +#define AXP8191_ALDO2OUT_VOL (0x25) +#define AXP8191_ALDO3OUT_VOL (0x26) +#define AXP8191_ALDO4OUT_VOL (0x27) +#define AXP8191_ALDO5OUT_VOL (0x28) +#define AXP8191_ALDO6OUT_VOL (0x29) + +#define AXP8191_BLDO1OUT_VOL (0x2A) +#define AXP8191_BLDO2OUT_VOL (0x2B) +#define AXP8191_BLDO3OUT_VOL (0x2C) +#define AXP8191_BLDO4OUT_VOL (0x2D) +#define AXP8191_BLDO5OUT_VOL (0x2E) + +#define AXP8191_CLDO1OUT_VOL (0x2F) +#define AXP8191_CLDO2OUT_VOL (0x30) +#define AXP8191_CLDO3OUT_VOL (0x31) +#define AXP8191_CLDO4OUT_VOL (0x32) +#define AXP8191_CLDO5OUT_VOL (0x33) + +#define AXP8191_DLDO1OUT_VOL (0x34) +#define AXP8191_DLDO2OUT_VOL (0x35) +#define AXP8191_DLDO3OUT_VOL (0x36) +#define AXP8191_DLDO4OUT_VOL (0x37) +#define AXP8191_DLDO5OUT_VOL (0x38) +#define AXP8191_DLDO6OUT_VOL (0x39) + +#define AXP8191_ELDO1OUT_VOL (0x3A) +#define AXP8191_ELDO2OUT_VOL (0x3B) +#define AXP8191_ELDO3OUT_VOL (0x3C) +#define AXP8191_ELDO4OUT_VOL (0x3D) +#define AXP8191_ELDO5OUT_VOL (0x3E) +#define AXP8191_ELDO6OUT_VOL (0x3F) + +#define AXP8191_IRQ_ENABLE1 (0x40) +#define AXP8191_IRQ_ENABLE2 (0x41) +#define AXP8191_IRQ_ENABLE3 (0x42) +#define AXP8191_IRQ_ENABLE4 (0x43) + +#define AXP8191_IRQ_STATUS1 (0x48) +#define AXP8191_IRQ_STATUS2 (0x49) +#define AXP8191_IRQ_STATUS3 (0x4A) +#define AXP8191_IRQ_STATUS4 (0x4B) + +#define AXP8191_POWER_ON_OFF_SOURCE_INDIVATION (0x50) +#define AXP8191_POWER_OFF_SOURCE_INDIVATION (0x51) +#define AXP8191_POWER_ON_OFF_SOURCE_EN1 (0x52) +#define AXP8191_POWER_ON_OFF_SOURCE_EN2 (0x53) +#define AXP8191_OVP_DISCHARGE_TEMPERATURE_CFG (0x54) +#define AXP8191_POWER_DISABLE_POWER_DOWN_SEQUENCE (0x55) +#define AXP8191_WAKEUP_CTRL_VOFF_SET (0x56) +#define AXP8191_POWERON_LEVEL_POWEROF_SET (0x57) +#define AXP8191_AUTO_SLEEP_CFG1 (0x58) +#define AXP8191_AUTO_SLEEP_CFG2 (0x59) +#define AXP8191_AUTO_SLEEP_CFG3 (0x5A) +#define AXP8191_AUTO_SLEEP_CFG4 (0x5B) +#define AXP8191_AUTO_SLEEP_CFG5 (0x5C) +#define AXP8191_AUTO_SLEEP_CFG6 (0x5D) +#define AXP8191_TS_CTRL (0x60) +#define AXP8191_TS_HYSL2H (0x61) +#define AXP8191_TS_HYSH2L (0x62) +#define AXP8191_VLTF_WORK (0x63) +#define AXP8191_VHTF_WORK (0x64) +#define AXP8191_TS_ADC_EN_DATA_H (0x65) +#define AXP8191_TS_ADC_DATA_L (0x66) +#define AXP8191_TDIE_ADC_EN_DATA_H (0x67) +#define AXP8191_TDIE_ADC_DATA_L (0x68) +#define AXP8191_GPADC_EN_DATA_H (0x69) +#define AXP8191_GPADC_DATA_L (0x6A) +#define AXP8191_PS_ADC_EN_DATA_H (0x6B) +#define AXP8191_PS_ADC_DATA_L (0x6C) + +#define AXP8191_CHANNEL_DEBUG_ADC_SEL (0x6D) + +#define AXP8191_ADC_CTL (0x6E) +#define AXP8191_ADC_CTL (0x6E) +#define AXP8191_GPIO_FUNC_CTL (0x70) +#define AXP8191_GPIO_INPUT_CTL (0x71) +#define AXP8191_GPIO_OUPUT_CTL (0x72) +#define AXP8191_PWM_CTL1 (0x73) +#define AXP8191_PWM_CTL2 (0x74) +#define AXP8191_PWM_CTL3 (0x75) +#define AXP8191_BACKUP_BAT_CHARGE_CTL (0x76) +#define AXP8191_WATCHDOG_CFG (0x77) +#define AXP8191_WRITE_LOCK_F1 (0xF0) +#define AXP8191_EFUSE_CTL (0xF1) +#define AXP8191_VREF (0xF2) +#define AXP8191_SCL_SDA_CFG (0xF3) +#define AXP8191_REG_ADD_EXT (0xFF) + +#define AXP8191_COMMOM_CFG1 (0x100) +#define AXP8191_COMMOM_CFG2 (0x101) +#define AXP8191_COMMOM_CFG3 (0x102) +#define AXP8191_COMMOM_CFG4 (0x103) + +#define AXP8191_DCDC1VOL_DEFAULT_SET (0x104) +#define AXP8191_DCDC2VOL_DEFAULT_SET (0x105) +#define AXP8191_DCDC3VOL_DEFAULT_SET (0x106) +#define AXP8191_DCDC4VOL_DEFAULT_SET (0x107) +#define AXP8191_DCDC5VOL_DEFAULT_SET (0x108) +#define AXP8191_DCDC6VOL_DEFAULT_SET (0x109) +#define AXP8191_DCDC7VOL_DEFAULT_SET (0x10A) +#define AXP8191_DCDC8VOL_DEFAULT_SET (0x10B) +#define AXP8191_DCDC9VOL_DEFAULT_SET (0x10C) + +#define AXP8191_ALDO1_ALDO2_VOL_DEFAULT_SET (0x10D) +#define AXP8191_ALDO3_ALDO4_VOL_DEFAULT_SET (0x10E) +#define AXP8191_ALDO5_ALDO6_VOL_DEFAULT_SET (0x10F) + +#define AXP8191_BLDO1_BLDO2_VOL_DEFAULT_SET (0x110) +#define AXP8191_BLDO3_BLDO4_VOL_DEFAULT_SET (0x111) +#define AXP8191_BLDO5_CLDO1_VOL_DEFAULT_SET (0x112) +#define AXP8191_CLDO2_CLDO3_VOL_DEFAULT_SET (0x113) +#define AXP8191_CLDO4_CLDO5_VOL_DEFAULT_SET (0x114) + +#define AXP8191_DLDO1_CLDO2_VOL_DEFAULT_SET (0x115) +#define AXP8191_DLDO3_CLDO4_VOL_DEFAULT_SET (0x116) +#define AXP8191_DLDO5_CLDO6_VOL_DEFAULT_SET (0x117) + +#define AXP8191_ELDO1_ELDO2_VOL_DEFAULT_SET (0x118) +#define AXP8191_ELDO3_ELDO4_VOL_DEFAULT_SET (0x119) +#define AXP8191_ELDO5_ELDO6_VOL_DEFAULT_SET (0x11A) + +#define AXP8191_DC8_OUTPUT_SET (0x12A) +#define AXP8191_RTC_DCXO_CTL_VOFF (0x12C) +#define AXP8191_DCDC_OC (0x12D) +#define AXP8191_FANOUT_SEQ_TRIM (0x12E) +#define AXP8191_VREF_VRPN_TUNING (0x12F) +#define AXP8191_VREF_VOLTAGE_TUNING (0x130) +#define AXP8191_BIAS_TUNING (0x131) +#define AXP8191_FREQUENCY_TUNING (0x132) +#define AXP8191_ADC_TUNING (0x133) +#define AXP8191_DCDC_TRIM1 (0x135) +#define AXP8191_DCDC_TRIM2 (0x136) + +#define AXP8191_PAGE_SELECT (0x137) +#define AXP8191_TEST_MODE_CTL1 (0x180) +#define AXP8191_TEST_MODE_CTL2 (0x181) +#define AXP8191_TEST_MODE_CTL3 (0x188) +#define AXP8191_DCDC_DEBUG1 (0x18A) +#define AXP8191_DCDC_DEBUG2 (0x18B) +#define AXP8191_DCDC_DEBUG3 (0x18C) +#define AXP8191_DCDC_DEBUG4 (0x18D) + +#endif// __REG_AXP8191_H__ \ No newline at end of file diff --git a/include/drivers/reg/reg-ccu.h b/include/drivers/reg/reg-ccu.h index d939040d3..f119757aa 100644 --- a/include/drivers/reg/reg-ccu.h +++ b/include/drivers/reg/reg-ccu.h @@ -6,19 +6,21 @@ extern "C" { #endif// __cplusplus #if defined(CONFIG_CHIP_SUN8IW21) -#include + #include #elif defined(CONFIG_CHIP_SUN8IW20) -#include + #include #elif defined(CONFIG_CHIP_SUN20IW1) -#include + #include #elif defined(CONFIG_CHIP_SUN50IW9) -#include + #include #elif defined(CONFIG_CHIP_SUN55IW3) -#include + #include #elif defined(CONFIG_CHIP_SUN50IW10) -#include + #include #elif defined(CONFIG_CHIP_SUN20IW5) -#include + #include +#elif defined(CONFIG_CHIP_SUN60IW2) + #include #else #error "Unsupported chip" #endif diff --git a/include/drivers/reg/reg-dma.h b/include/drivers/reg/reg-dma.h index af5d52671..af05f4f93 100644 --- a/include/drivers/reg/reg-dma.h +++ b/include/drivers/reg/reg-dma.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_DMA_H__ #define __REG_DMA_H__ diff --git a/include/drivers/reg/reg-gic.h b/include/drivers/reg/reg-gic.h index 6fb51339e..5d1ee79fd 100644 --- a/include/drivers/reg/reg-gic.h +++ b/include/drivers/reg/reg-gic.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_GIC_H__ #define __REG_GIC_H__ diff --git a/include/drivers/reg/reg-ncat.h b/include/drivers/reg/reg-ncat.h index c3def6896..b67c98046 100644 --- a/include/drivers/reg/reg-ncat.h +++ b/include/drivers/reg/reg-ncat.h @@ -21,6 +21,8 @@ extern "C" { #include #elif defined(CONFIG_CHIP_SUN20IW5) #include +#elif defined(CONFIG_CHIP_SUN60IW2) + #include #else #error "Unsupported chip" #endif diff --git a/include/drivers/reg/reg-smhc.h b/include/drivers/reg/reg-smhc.h index 7efdd5917..03778592a 100644 --- a/include/drivers/reg/reg-smhc.h +++ b/include/drivers/reg/reg-smhc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_SMHC_H__ #define __REG_SMHC_H__ diff --git a/include/drivers/reg/reg-spi.h b/include/drivers/reg/reg-spi.h index d297cfa2a..1a5829a0b 100644 --- a/include/drivers/reg/reg-spi.h +++ b/include/drivers/reg/reg-spi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __REG_SPI_H__ #define __REG_SPI_H__ diff --git a/include/drivers/sdhci/sys-sdcard.h b/include/drivers/sdhci/sys-sdcard.h index eae26abcd..ede713a31 100644 --- a/include/drivers/sdhci/sys-sdcard.h +++ b/include/drivers/sdhci/sys-sdcard.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SDHCI_SDCARD_H__ #define __SDHCI_SDCARD_H__ diff --git a/include/drivers/sdhci/sys-sdhci.h b/include/drivers/sdhci/sys-sdhci.h index 128b7b4b6..11d52bf1d 100644 --- a/include/drivers/sdhci/sys-sdhci.h +++ b/include/drivers/sdhci/sys-sdhci.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SDHCI_SDHCI_H__ #define __SDHCI_SDHCI_H__ diff --git a/include/drivers/sys-dma.h b/include/drivers/sys-dma.h index 68543bf2c..fe5b69af1 100644 --- a/include/drivers/sys-dma.h +++ b/include/drivers/sys-dma.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef _SUNXI_DMA_H #define _SUNXI_DMA_H diff --git a/include/drivers/sys-gpio.h b/include/drivers/sys-gpio.h index 5c4a1ba84..cd4f83173 100644 --- a/include/drivers/sys-gpio.h +++ b/include/drivers/sys-gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_GPIO_H__ #define __SYS_GPIO_H__ diff --git a/include/drivers/sys-i2c.h b/include/drivers/sys-i2c.h index 6e32b5706..2246bf2cd 100644 --- a/include/drivers/sys-i2c.h +++ b/include/drivers/sys-i2c.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_I2C_H__ #define __SYS_I2C_H__ diff --git a/include/drivers/sys-rproc.h b/include/drivers/sys-rproc.h index db8d72efe..667c9fc3b 100644 --- a/include/drivers/sys-rproc.h +++ b/include/drivers/sys-rproc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_RPROC_H__ #define __SYS_RPROC_H__ diff --git a/include/drivers/sys-rtc.h b/include/drivers/sys-rtc.h index f01cd8429..6f04f8f28 100644 --- a/include/drivers/sys-rtc.h +++ b/include/drivers/sys-rtc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_RTC_H__ #define __SYS_RTC_H__ diff --git a/include/drivers/sys-sdcard.h b/include/drivers/sys-sdcard.h index 67c252a66..06e8f745c 100644 --- a/include/drivers/sys-sdcard.h +++ b/include/drivers/sys-sdcard.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SDCARD_H__ #define __SDCARD_H__ diff --git a/include/drivers/sys-sdhci.h b/include/drivers/sys-sdhci.h index 5814807cb..5940ab72c 100644 --- a/include/drivers/sys-sdhci.h +++ b/include/drivers/sys-sdhci.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SDHCI_H__ #define __SDHCI_H__ diff --git a/include/drivers/sys-sid.h b/include/drivers/sys-sid.h index 7825c8bad..97298d2d3 100644 --- a/include/drivers/sys-sid.h +++ b/include/drivers/sys-sid.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef _SYS_SID_H_ #define _SYS_SID_H_ diff --git a/include/drivers/sys-spi.h b/include/drivers/sys-spi.h index 7db5febe4..63e59a27c 100644 --- a/include/drivers/sys-spi.h +++ b/include/drivers/sys-spi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_SPI_H__ #define __SYS_SPI_H__ @@ -161,6 +161,7 @@ int sunxi_spi_update_clk(sunxi_spi_t *spi, uint32_t clk); */ int sunxi_spi_transfer(sunxi_spi_t *spi, spi_io_mode_t mode, void *txbuf, uint32_t txlen, void *rxbuf, uint32_t rxlen); + #ifdef __cplusplus } #endif// __cplusplus diff --git a/include/drivers/sys-wdt.h b/include/drivers/sys-wdt.h index 77a058f52..eb4030224 100644 --- a/include/drivers/sys-wdt.h +++ b/include/drivers/sys-wdt.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SYS_WDT_H__ #define __SYS_WDT_H__ diff --git a/include/image/image_loader.h b/include/image/image_loader.h index ae4f6dca9..c6accd98e 100644 --- a/include/image/image_loader.h +++ b/include/image/image_loader.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __IMAGE_LOADER_H__ #define __IMAGE_LOADER_H__ diff --git a/include/lib/elf/elf_loader.h b/include/lib/elf/elf_loader.h index dd2da400c..9529b6018 100644 --- a/include/lib/elf/elf_loader.h +++ b/include/lib/elf/elf_loader.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ELF_LOADER_H__ #define __ELF_LOADER_H__ diff --git a/include/log.h b/include/log.h index af997baa9..19aa5170b 100644 --- a/include/log.h +++ b/include/log.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __DEBUG_H__ #define __DEBUG_H__ @@ -24,6 +24,7 @@ extern "C" { #define LOG_LEVEL_INFO 3 #define LOG_LEVEL_DEBUG 4 #define LOG_LEVEL_TRACE 5 +#define LOG_LEVEL_BACKTRACE 6 #ifndef LOG_LEVEL_DEFAULT diff --git a/include/os.h b/include/os.h index f4a7b9b7f..c1e92dab2 100644 --- a/include/os.h +++ b/include/os.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __OS_H__ #define __OS_H__ diff --git a/include/smalloc.h b/include/smalloc.h index d90d2bce2..e4455b181 100644 --- a/include/smalloc.h +++ b/include/smalloc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SMALLOC_H__ #define __SMALLOC_H__ diff --git a/include/sstdlib.h b/include/sstdlib.h index 64168e88c..d170a9761 100644 --- a/include/sstdlib.h +++ b/include/sstdlib.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __STDLIB_H__ #define __STDLIB_H__ diff --git a/include/string.h b/include/string.h index dcde63e3c..c4f592372 100644 --- a/include/string.h +++ b/include/string.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __STRING_H__ #define __STRING_H__ diff --git a/include/uart.h b/include/uart.h index 30cf2f4c0..4378dd1a8 100644 --- a/include/uart.h +++ b/include/uart.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CLI_UART_H__ #define __CLI_UART_H__ diff --git a/lib/elf/elf32.c b/lib/elf/elf32.c index 54c2ac905..93df67d6b 100644 --- a/lib/elf/elf32.c +++ b/lib/elf/elf32.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/lib/elf/elf64.c b/lib/elf/elf64.c index 784b60a8a..326f3d494 100644 --- a/lib/elf/elf64.c +++ b/lib/elf/elf64.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/link/arm32/link.ld b/link/arm32/link.ld index f2633bf4e..6818584b4 100644 --- a/link/arm32/link.ld +++ b/link/arm32/link.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) diff --git a/link/riscv32/link.ld b/link/riscv32/link.ld index 733ee6d0c..6f8a89a6f 100644 --- a/link/riscv32/link.ld +++ b/link/riscv32/link.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") OUTPUT_ARCH("riscv") diff --git a/link/riscv64/link.ld b/link/riscv64/link.ld index 02a056d4f..734e9d295 100644 --- a/link/riscv64/link.ld +++ b/link/riscv64/link.ld @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") OUTPUT_ARCH("riscv") diff --git a/payloads b/payloads index c1c422fd9..f73a18f5f 160000 --- a/payloads +++ b/payloads @@ -1 +1 @@ -Subproject commit c1c422fd9b0a7a7a50ae21f77b3635c82bd6daa8 +Subproject commit f73a18f5f6f8c2c4672e9532b60a623dd061778a diff --git a/src/arch/arm32/CMakeLists.txt b/src/arch/arm32/CMakeLists.txt index d0bf784a4..ca74924c9 100644 --- a/src/arch/arm32/CMakeLists.txt +++ b/src/arch/arm32/CMakeLists.txt @@ -1,4 +1,5 @@ add_library(arch-obj OBJECT + backtrace.c exception.c memcmp.S memcpy.S diff --git a/src/arch/arm32/backtrace.c b/src/arch/arm32/backtrace.c new file mode 100644 index 000000000..5b030c560 --- /dev/null +++ b/src/arch/arm32/backtrace.c @@ -0,0 +1,1248 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/** + * @brief Maximum limit for backtrace scanning. + * + * This constant defines the maximum limit for scanning the backtrace. + * The backtrace function will scan instructions and stack frames + * up to this size. If the limit is exceeded, the backtrace operation will fail. + */ +#define BT_SCAN_MAX_LIMIT 0xFFFFFF + +/** + * @brief Maximum number of backtrace levels. + * + * This constant defines the maximum depth of the backtrace. It limits + * how many stack frames the backtrace function can unwind before stopping. + */ +#define BT_LEVEL_LIMIT 64 + +/** + * @brief Converts a program counter (PC) value to an address. + * + * This macro takes a program counter (PC) value and converts it to + * a valid address by clearing the least significant bit. This operation + * is commonly used to align PC addresses properly for instruction fetch. + * + * @param pc The program counter value to convert. + * @return The corresponding address, aligned to a 2-byte boundary. + */ +#define PC2ADDR(pc) ((char *) (((uint32_t) (pc)) & 0xfffffffe)) + +/** + * @brief Determines the length of an instruction in bytes based on its encoding. + * + * This macro computes the length of an instruction in bytes, given a 32-bit + * instruction encoding. The length is determined based on specific bit patterns + * in the instruction word. + * + * @param x The instruction encoding (32-bit). + * @return The length of the instruction in bytes (either 2, 4, 6, or 8). + */ +#define insn_length(x) (((x) &0x03) < 0x03 ? 2 : ((x) &0x1f) < 0x1f ? 4 \ + : ((x) &0x3f) < 0x3f ? 6 \ + : 8) + +/** + * @brief Extracts a specific bit field from a value. + * + * This macro extracts a bit field from a value `x` based on the specified + * high and low bit positions. The bits are masked and shifted to the + * right, leaving the desired bit field. + * + * @param x The value from which to extract the bit field. + * @param high The index of the highest bit (inclusive). + * @param low The index of the lowest bit (inclusive). + * @return The extracted bit field. + */ +#define BITS(x, high, low) ((x) & (((1 << ((high) - (low) + 1)) - 1) << (low))) + +/** + * @brief ARM state macro definition + * + * This macro represents the ARM state in ARM architecture. + */ +#define ARM_STATE 0 + +/** + * @brief THUMB state macro definition + * + * This macro represents the THUMB state in ARM architecture. + */ +#define THUMB_STATE 1 + +/** + * @brief Macro to check if the program counter (PC) is in THUMB mode + * + * This macro checks whether the given program counter address (PC) points to the THUMB mode. + * According to ARM architecture, if the least significant bit (LSB) of the program counter (PC) is 1, + * the instruction set is in THUMB mode. + * + * @param pc The program counter (typically the address of an instruction) + * @return Returns a non-zero value if the address is in THUMB mode, otherwise returns 0. + */ +#define IS_THUMB_ADDR(pc) ((uint32_t) (pc) &0x1) + +/** + * @brief Pointer to the start of the image in memory. + * + * This variable marks the start address of the memory region that + * contains the program image. It is used to check if a program counter + * (PC) value falls within the valid range of executable memory. + */ +extern uint8_t __spl_start[]; + +/** + * @brief Pointer to the end of the stack service region. + * + * This variable marks the end address of the memory region used for the + * stack service. It is used to check if a program counter (PC) value falls + * within the valid memory region, preventing access to out-of-bounds memory. + */ +extern uint8_t __stack_srv_end[]; + +/** + * @brief Checks whether a given program counter (PC) address is within a valid range. + * + * This function checks if the provided PC (program counter) value lies within + * the memory region between `__spl_start` and `__stack_srv_end`. It ensures that + * the PC value points to a valid memory address in the executable region of the program. + * + * @param pc The program counter value to check. + * @return 1 if the PC is within the valid address range, 0 otherwise. + */ +static int inline backtrace_check_address(void *pc) { + if (((uint32_t) pc > (uint32_t) __spl_start) && ((uint32_t) pc < (uint32_t) __stack_srv_end)) { + return 1; /**< Valid address in the range. */ + } + return 0; /**< Invalid address outside the range. */ +} + +/** + * @brief Checks if a given Thumb instruction is a 32-bit Thumb instruction. + * + * This function examines the top 5 bits of the input instruction to determine + * whether it corresponds to a specific set of Thumb instructions (0x1D, 0x1E, or 0x1F). + * These values indicate a 32-bit Thumb instruction. + * + * @param ic A 16-bit uint32_teger representing the Thumb instruction to be checked. + * + * @return Returns 1 if the instruction is a 32-bit Thumb instruction (i.e., its top 5 bits match + * 0x1D, 0x1E, or 0x1F), otherwise returns 0. + */ +static int thumb_thumb32bit_code(uint16_t ic) { + uint16_t op = (ic >> 11) & 0xFFFF; + if (op == 0x1D || op == 0x1E || op == 0x1F) + return 1; + return 0; +} + +/** + * @brief Finds the offset for the Link Register (LR) based on the processor state. + * + * This function computes the offset for the Link Register (LR) based on the current processor + * state (ARM or THUMB) and the instruction sequence at the return address. It checks for + * specific branch instructions such as `bx` and `blx` and adjusts the LR offset accordingly. + * + * The function will also handle both 16-bit and 32-bit instructions based on the processor mode + * and update the state of the processor. + * + * @param LR A pointer to the Link Register value (the return address). + * @param state A pointer to a boolean representing the processor state. It can be either + * ARM_STATE or THUMB_STATE. + * + * @return The offset to be applied to the LR, typically 2 or 4 bytes, depending on the + * type of instruction found. + */ +static int find_lr_offset(char *LR, bool *state) { + char *LR_fixed;///< Pointer to the adjusted Link Register address + int offset; ///< Offset to be returned (2 or 4 bytes) + + // Check the processor state and determine the default offset + if (*state == ARM_STATE) { + offset = 4;///< ARM state typically uses 4-byte instructions + } else if (*state == THUMB_STATE) { + offset = 2;///< THUMB state typically uses 2-byte instructions + } + + // Adjust LR address based on the processor's current mode + LR_fixed = PC2ADDR(LR);///< Convert LR address to a fixed address for processing + + // Check if the address is valid and within text (code) segment + if (backtrace_check_address(LR_fixed)) { + uint16_t ins16 = *(uint16_t *) (LR_fixed - 2);///< 16-bit instruction at LR - 2 + uint32_t ins32 = *(uint32_t *) (LR_fixed - 4);///< 32-bit instruction at LR - 4 + + // Check for "bx " instruction (16-bit) + if ((ins16 & 0xFF80) == 0x4700) { + *state = !(*state);///< Toggle state between ARM and THUMB + offset = 2; ///< "bx" instruction uses 2-byte offset + printk_trace("BT: \tbx off=2\n"); + } + // Check for "blx " instruction (16-bit) + else if ((ins16 & 0xFF80) == 0x4780) { + *state = !(*state);///< Toggle state + offset = 2; ///< "blx" instruction uses 2-byte offset + printk_trace("BT: \tblx off=2\n"); + } + // Check for "bx " instruction (32-bit) + else if ((ins32 & 0x0FFFFFF0) == 0x012FFF10) { + *state = !(*state);///< Toggle state + offset = 4; ///< "bx" instruction uses 4-byte offset + printk_trace("BT: \tbx off=4\n"); + } + // Check for "blx immediate" instruction (32-bit) + else if ((ins32 & 0xFE000000) == 0xFA000000) { + *state = !(*state);///< Toggle state + offset = 4; ///< "blx immediate" instruction uses 4-byte offset + printk_trace("BT: \tblx #imm off=4\n"); + } + // Check for another form of "blx immediate" (32-bit) + else if ((ins32 & 0xF800D000) == 0xF000C000) { + *state = !(*state);///< Toggle state + offset = 4; ///< "blx immediate" instruction uses 4-byte offset + printk_trace("BT: \tblx #imm off=4\n"); + } + // If state is THUMB and not a specific instruction, determine offset using helper function + else if (*state == THUMB_STATE) { + ins16 = *(uint16_t *) (LR_fixed - 4); ///< Fetch instruction at LR - 4 + offset = thumb_thumb32bit_code(ins16) == 1 ? 4 : 2;///< Determine offset based on instruction type + } + } + + // Log the final backtrace information with the calculated offset + printk(LOG_LEVEL_BACKTRACE, "backtrace: 0x%08x\n", LR_fixed - offset); + + // Return the calculated offset (2 or 4) + return offset; +} + +/** + * @brief Retrieves the next Thumb instruction from the given addresses. + * + * This function fetches the next instruction in the Thumb instruction set from two 16-bit + * instruction addresses. It checks whether the instruction is a 32-bit Thumb-2 instruction + * (Thumb-32), and if so, combines the two 16-bit values to form a 32-bit instruction. It + * also updates the offset and returns the appropriate instruction. + * + * The function uses the `lsb` (least significant bit) flag to determine which part of the + * instruction to select when the instruction is not Thumb-32. + * + * @param error A pointer to an integer that will be set to `-1` in case of an error. + * @param offset A pointer to the offset, which will be updated if a Thumb-32 instruction is found. + * @param ins16_h_addr Address of the high part of the instruction (16 bits). + * @param ins16_l_addr Address of the low part of the instruction (16 bits). + * @param lsb Flag indicating whether to fetch the least significant bit of the instruction. + * @param thumb32bit A pointer to an integer that will be set to `1` if a Thumb-32 instruction is detected, otherwise `0`. + * + * @return Returns the 32-bit instruction if Thumb-32 is detected, otherwise returns the appropriate 16-bit instruction. + */ +static int thumb_get_next_inst(int *error, int *offset, char *ins16_h_addr, char *ins16_l_addr, int lsb, int *thumb32bit) { + uint32_t ins32 = 0; ///< 32-bit instruction to be returned + uint16_t ins16_l = 0;///< Lower 16 bits of the instruction + uint16_t ins16_h = 0;///< Higher 16 bits of the instruction + + // Check if the low address is valid (points to valid code segment) + if (backtrace_check_address(ins16_l_addr) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", ins16_l_addr); + *error = -1;///< Set error flag to indicate invalid address + return -1; ///< Return -1 to indicate error + } + ins16_l = *(uint16_t *) (ins16_l_addr);///< Fetch lower 16 bits of the instruction + + // Check if the high address is valid (points to valid code segment) + if (backtrace_check_address(ins16_h_addr) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", ins16_h_addr); + *error = -1;///< Set error flag to indicate invalid address + return -1; ///< Return -1 to indicate error + } + ins16_h = *(uint16_t *) (ins16_h_addr);///< Fetch higher 16 bits of the instruction + + // Check if the low part of the instruction indicates a Thumb-32 instruction + if (thumb_thumb32bit_code(ins16_l)) { + /* Thumb-2 (Thumb-32) instruction: combine low and high parts */ + ins32 = (ins16_l << 16) | ins16_h;///< Combine low and high parts to form a 32-bit instruction + *offset += 2; ///< Update offset (since it's a 32-bit instruction) + *thumb32bit = 1; ///< Set thumb32bit flag to 1 indicating Thumb-32 instruction + } else { + *thumb32bit = 0;///< Set thumb32bit flag to 0, indicating it's not Thumb-32 + if (lsb) { + ins32 = ins16_l;///< Use the low part of the instruction (16-bit) + } else { + ins32 = ins16_h;///< Use the high part of the instruction (16-bit) + } + } + + // Return the constructed 32-bit instruction (or a 16-bit instruction if not Thumb-32) + return ins32; +} + +/** + * @brief Calculates the frame size for a `push` or `store-multiple` instruction that includes the link register (lr). + * + * This function processes a Thumb instruction to determine the frame size (number of registers pushed) + * based on the presence of the link register (`lr`). It checks both Thumb-2 (32-bit) and Thumb-1 (16-bit) + * instructions and computes the frame size accordingly. + * + * @param inst The instruction to analyze (32-bit Thumb instruction). + * @param offset Pointer to an integer that will be set to `1` if a push or store-multiple instruction is found, + * otherwise `0`. + * @param thumb32bit A flag indicating whether the instruction is a 32-bit Thumb instruction (`1` if Thumb-32, + * `0` if Thumb-16). + * + * @return The number of registers pushed (frame size) or `-1` if no matching instruction is found. + */ +static int thumb_get_push_lr_ins_framesize(uint32_t inst, int *offset, int thumb32bit) { + int framesize = -1;///< Default frame size if no matching instruction is found + + // Process Thumb-32 (Thumb-2) instruction + if (thumb32bit) { + // Check if the instruction is "stmdb sp!, {..., lr}" + if ((inst & 0xFFFFF000) == 0xe92d4000) { + // The instruction is "stmdb sp!, {..., lr}" + printk_trace("BT: \tstmdb sp!, {..., lr}\n"); + framesize = __builtin_popcount(inst & 0xFFF);///< Count the number of registers in the mask (lower 12 bits) + framesize++; ///< Add 1 for the lr register being stored + *offset = 1; ///< Set offset to 1 (this is a 32-bit instruction) + } + } else { + // Process Thumb-16 instructions + // Check if the instruction is "push {..., lr, ...}" + if ((inst & 0xFF00) == 0xB500) { + // The instruction is "push {..., lr, ...}" + printk_trace("BT: \tpush {..., lr, ... }\n"); + framesize = __builtin_popcount(inst & 0xFF) + 1;///< Count registers and add 1 for lr + *offset = 1; ///< Set offset to 1 (this is a 16-bit instruction) + } + // Check if the instruction is "push { ... }" + else if ((inst & 0xFF00) == 0xB400) { + // The instruction is "push { ... }" + printk_trace("BT: \tpush { ... }\n"); + framesize = __builtin_popcount(inst & 0xFF);///< Count the registers in the mask (lower 8 bits) + *offset = 0; ///< Set offset to 0 (this is a 16-bit instruction without lr) + } + } + + // Print the instruction and its calculated frame size for debugging + printk_trace("BT: inst:0x%x, framesize = %d\n", inst, framesize); + + return framesize;///< Return the frame size +} + +/** + * @brief Calculate the frame size based on the instruction and determine the stack adjustment. + * + * This function analyzes Thumb instructions to determine the frame size of a function prologue, + * based on push or stack adjustment operations. It handles both 16-bit and 32-bit Thumb instructions. + * + * @param inst The instruction to analyze (32-bit). + * @param thumb32bit Flag indicating whether the instruction is a 32-bit Thumb instruction (1 for Thumb-32, 0 for Thumb-16). + * + * @return The calculated frame size (number of registers pushed or stack adjusted), or -1 if no match is found. + */ +static int thumb_backtrace_stack_push(uint32_t inst, int thumb32bit) { + uint32_t sub; /**< Temporary variable to hold the immediate value for 'sub' instruction. */ + uint32_t shift; /**< Temporary variable to hold the calculated shift value. */ + int framesize = -1; /**< Default frame size, indicating no matching instruction. */ + + if (thumb32bit) { + // Check if the instruction is a store-multiple decrement (stmdb sp!, {...}) + if ((inst & 0xFFFFF000) == 0xe92d4000) { + printk_trace("BT: \tstmdb sp!, { ... }\n"); + framesize = __builtin_popcount(inst & 0xfff); /**< Count the number of registers to be stored. */ + framesize++; /**< Add 1 for the 'lr' register being stored. */ + } + // Check if the instruction is a subtract (sub.w sp, sp, #imm) + else if ((inst & 0xFBFF8F00) == 0xF1AD0D00) { + printk_trace("BT: \tsub.w sp, sp, #imm\n"); + sub = 128 + (inst & 0x7f); /**< Calculate the immediate value to subtract from sp. */ + shift = (inst >> 7) & 0x1; /**< Extract and calculate the shift value for the instruction. */ + shift += ((inst >> 12) & 0x7) << 1; + shift += ((inst >> 26) & 0x1) << 4; + framesize = sub << (30 - shift); /**< Calculate the frame size by applying the shift to the immediate. */ + } + // Check if the instruction is a vector push for 64-bit registers (vpush {...} x64) + else if ((inst & 0xffbf0f00) == 0xed2d0b00) { + printk_trace("BT: \tvpush {...} x64\n"); + framesize = (inst & 0xff); /**< Frame size is determined by the lower byte of the instruction. */ + } + // Check if the instruction is a vector push for 32-bit registers (vpush {...} x32) + else if ((inst & 0xffbf0f00) == 0xed2d0a00) { + printk_trace("BT: \tvpush {...} x32\n"); + framesize = (inst & 0xff); /**< Frame size is determined by the lower byte of the instruction. */ + } + } else { + // Check if the instruction is a push instruction involving the link register (push {..., lr}) + if ((inst & 0xff00) == 0xb500) { + printk_trace("BT: \tpush {..., lr}\n"); + framesize = __builtin_popcount(inst & 0xff); /**< Count the registers being pushed, including lr. */ + framesize++; /**< Add 1 for the 'lr' register. */ + } + // Check if the instruction is a subtract instruction (sub sp, sp, #imm) + else if ((inst & 0xff80) == 0xb080) { + printk_trace("BT: \tsub sp, sp, #imm\n"); + framesize = (inst & 0x7f); /**< Calculate the immediate value to subtract from sp. */ + } + } + + // Print the instruction and its calculated frame size for debugging. + printk_trace("BT: inst:0x%x, framesize = %d\n", inst, framesize); + return framesize; /**< Return the calculated frame size. */ +} + +/** + * @brief Perform a backtrace from the stack and retrieve the next return address and program counter (PC). + * + * This function traverses the stack to reconstruct a backtrace by parsing Thumb instructions and + * calculating the correct stack pointer (SP), program counter (PC), and link register (LR). It + * uses the Thumb instruction set to decode stack frames and returns the updated SP, PC, and LR values. + * + * @param pSP Pointer to the current stack pointer (SP). + * @param pPC Pointer to the current program counter (PC). + * @param pLR Pointer to the current link register (LR). + * + * @return + * - 1: If the backtrace is successfully completed. + * - 0: If the backtrace is successful but no LR was found. + * - -1: If an error occurs (e.g., invalid address, overflow, or failed instruction parsing). + */ +static int thumb_backtrace_from_stack(int **pSP, char **pPC, char **pLR) { + char *parse_addr = NULL; /**< Temporary variable to hold address being parsed. */ + int *SP = *pSP; /**< Current stack pointer (SP) value. */ + char *PC = PC2ADDR(*pPC); /**< Converted program counter (PC) address. */ + char *LR = NULL; /**< Temporary variable to hold the link register (LR). */ + int i, temp, framesize = 0, offset = 1; /**< Temporary variables for iteration, frame size, and offset calculation. */ + uint32_t ins32 = 0; /**< 32-bit instruction fetched during the backtrace. */ + bool state = THUMB_STATE; /**< Current state of the processor (THUMB_STATE). */ + + // Loop to search for the first instruction that indicates the frame size. + for (int i = 2; i < BT_SCAN_MAX_LIMIT; i += 2) { + parse_addr = PC - i; /**< Calculate the address to fetch instructions from. */ + int error = 0; /**< Error flag for instruction parsing. */ + int thumb32bit = 0; /**< Flag to indicate whether the instruction is a 32-bit Thumb instruction. */ + ins32 = thumb_get_next_inst(&error, &i, parse_addr, parse_addr - 2, 0, &thumb32bit); /**< Fetch the next instruction. */ + if (error) { + return -1; /**< Return -1 if an error occurs during instruction fetching. */ + } + framesize = thumb_get_push_lr_ins_framesize(ins32, &offset, thumb32bit); /**< Get the frame size based on the instruction. */ + if (framesize >= 0) { + break; /**< Exit loop if valid frame size is found. */ + } + } + + printk_trace("BT: i = %d, parse_addr = %p, PC = %p, offset = %d, framesize = %d\n", i, parse_addr, PC, offset, framesize); + + // Check if the scan reached the maximum limit without finding a valid frame size. + if (i == BT_SCAN_MAX_LIMIT) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. scope overflow\n"); + return -1; + } + + // Process remaining instructions to calculate the total frame size. + for (i = 2; parse_addr + i <= PC; i += 2) { + int error = 0; /**< Error flag for instruction parsing. */ + int thumb32bit = 0; /**< Flag for 32-bit Thumb instruction. */ + ins32 = thumb_get_next_inst(&error, &i, parse_addr + i + 2, parse_addr + i, 1, &thumb32bit); /**< Fetch next instruction. */ + if (error) { + return -1; /**< Return -1 if an error occurs. */ + } + temp = thumb_backtrace_stack_push(ins32, thumb32bit); /**< Calculate the stack frame size for this instruction. */ + if (temp >= 0) { + framesize += temp; /**< Add the calculated frame size to the total. */ + } + } + + printk_trace("BT: i = %d, framesize = %d, SP = %p, offset = %d\n", i, framesize, SP, offset); + + // If offset is zero, use the provided link register (LR). + if (offset == 0) { + LR = *pLR; + } + + // If no LR found, try to fetch it from the stack. + if (!LR) { + if (backtrace_check_address(SP + framesize - offset) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", SP + framesize - offset); + return -1; /**< Return -1 if the LR address is invalid. */ + } + LR = (char *) *(SP + framesize - offset); /**< Fetch LR from the calculated stack address. */ + } + + // Check if the LR address is valid. + if (backtrace_check_address(LR) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); + return -1; /**< Return -1 if the LR is invalid. */ + } + + *pSP = SP + framesize; /**< Update the stack pointer (SP) based on the calculated frame size. */ + offset = find_lr_offset(LR, &state); /**< Find the offset for the link register (LR). */ + *pPC = LR - offset; /**< Calculate the program counter (PC) based on the LR and offset. */ + + // Adjust for THUMB state if needed. + if (state == THUMB_STATE) { + MAKE_THUMB_ADDR(*pPC); /**< Make the program counter address compatible with THUMB state. */ + } + + printk_trace("BT: *pSP = %p, offset = %d, *pPC = %p, state=%d\n", *pSP, offset, *pPC, state); + + return offset == 0 ? 1 : 0; /**< Return 1 if no offset, else return 0. */ +} + +/** + * @brief Analyzes an ARM instruction to determine the frame size and the offset for the link register (LR). + * + * This function inspects the provided ARM instruction to detect specific types of instructions + * related to pushing the link register (LR) onto the stack. It calculates the size of the stack frame + * and determines the offset of the link register, if applicable. + * + * @param inst The ARM instruction to be analyzed (32-bit uint32_teger). + * @param offset Pointer to an integer where the offset of LR will be stored. + * + * @return The size of the stack frame in terms of the number of registers pushed, or -1 if no relevant instruction is found. + */ +static int arm_get_push_lr_ins_framesize(uint32_t inst, int *offset) { + int framesize = -1; /**< Default return value when no matching instruction is found */ + + // Check if the instruction is 'push {..., lr, ...}' (with optional PC) + if ((inst & 0xFFFF4000) == 0xE92D4000) { + /* push {..., lr, ... } */ + printk_trace("BT: \tpush {..., lr, ... }\n"); + + // Check if the instruction also pushes the 'pc', set offset to 2 if true, else to 1 for just 'lr' + *offset = (inst & 0x8000) == 0x8000 ? 2 : 1; + + // Count how many registers are pushed (count the 1s in the lower 16 bits) + framesize = __builtin_popcount(inst & 0xFFFF); + } + // Check if the instruction is 'str lr [sp, #-4]!' (store lr at sp-4) + else if (inst == 0xE52DE004) { + /* str lr [sp, #-4]! */ + printk_trace("BT: \tstr lr [sp, #-4]!\n"); + *offset = 1; /**< Only one register (lr) involved */ + framesize = 1; /**< Only one register is stored (lr) */ + } + // Check if the instruction is a general 'push' instruction + else if ((inst & 0xFFFF0000) == 0xE92D0000) { + /* push {.....} */ + printk_trace("BT: \tpush {.....}\n"); + *offset = 0; /**< No special handling for link register here */ + framesize = __builtin_popcount(inst & 0xFFFF); /**< Count the number of registers pushed */ + } + + // Debug trace of the instruction and calculated frame size + printk_trace("BT: inst = 0x%x, framesize = %d\n", inst, framesize); + + return framesize; /**< Return the calculated frame size */ +} + +/** + * @brief Analyzes an ARM instruction to determine the frame size for stack operations. + * + * This function inspects the provided ARM instruction to determine the size of the stack frame + * based on common instructions such as `sub sp, sp, #imm`, `push`, `vpush`, and `str xxx, [sp, #-4]!`. + * It returns the size of the stack frame in terms of the number of words (4-byte units) affected by the instruction. + * + * @param inst The ARM instruction to be analyzed (32-bit uint32_teger). + * + * @return The size of the stack frame in terms of the number of 4-byte words, or -1 if no relevant instruction is found. + */ +static int arm_backtrace_stack_push(uint32_t inst) { + uint32_t sub; /**< Temporary variable for the immediate value */ + uint32_t shift; /**< Temporary variable for the shift value */ + int framesize = -1; /**< Default return value when no matching instruction is found */ + + // Check if the instruction is 'sub sp, sp, #imm' (subtract an immediate from sp) + if ((inst & 0x0FFFF000) == 0x024DD000) { + /* sub sp, sp, #imm */ + printk_trace("BT: \tsub sp, sp, #imm\n"); + + sub = inst & 0xFF; /**< Extract the immediate value */ + shift = (inst >> 8) & 0xF; /**< Extract the shift value */ + + // Adjust the immediate value based on the shift + if (shift != 0) { + shift = 32 - 2 * shift; /**< Convert shift into bitwise adjustment */ + sub = sub << shift; /**< Apply the shift to the immediate value */ + } + + framesize = sub / 4; /**< Calculate the frame size in terms of 4-byte words */ + } + // Check if the instruction is a 'push {...}' (push registers onto the stack) + else if ((inst & 0x0FFF0000) == 0x092D0000) { + /* push {...} */ + printk_trace("BT: \tpush {...}\n"); + framesize = __builtin_popcount(inst & 0xFFFF); /**< Count the number of registers pushed */ + } + // Check if the instruction is a 'vpush {...}' (push vector registers onto the stack) + else if ((inst & 0x0FBF0F00) == 0x0D2D0B00) { + /* vpush {...} */ + printk_trace("BT: \tvpush {...}\n"); + framesize = inst & 0xFF; /**< Set frame size to the number of vector registers pushed */ + } + // Check if the instruction is 'str xxx, [sp, #-4]!' (store register at sp-4) + else if ((inst & 0xFFFF0FFF) == 0xE52D0004) { + /* str xxx, [sp, #-4]! */ + printk_trace("BT: \tstr xxx, [sp, #-4]!\n"); + framesize = 1; /**< Only one register is stored (frame size = 1 word) */ + } + + // Debug trace of the instruction and calculated frame size + printk_trace("BT: inst = 0x%x, framesize = %d\n", inst, framesize); + + return framesize; /**< Return the calculated frame size */ +} + +/** + * @brief Performs backtrace from the stack to find the return address and program counter. + * + * This function attempts to deduce the return address (LR) and program counter (PC) by analyzing + * the stack and the instructions around it. It parses the stack to find the correct frame size, + * validates the text addresses, and adjusts the program counter based on the instruction state + * (ARM/Thumb). + * + * @param pSP Pointer to the current stack pointer (SP). + * @param pPC Pointer to the current program counter (PC). + * @param pLR Pointer to the link register (LR). + * + * @return 1 if a valid return address is found, 0 if the backtrace is incomplete, and -1 if an error occurs. + */ +static int arm_bakctrace_from_stack(int **pSP, char **pPC, char **pLR) { + int *SP = *pSP; /**< Current stack pointer */ + char *PC = *pPC; /**< Current program counter */ + char *LR = NULL; /**< Link register (LR) will be determined later */ + char *parse_addr = NULL; /**< Address used for parsing instructions */ + int i, temp, framesize, offset = 0, swi_num = 0; /**< Temporary variables for backtrace calculations */ + uint32_t ins32 = 0; /**< Holds instruction value */ + bool state = ARM_STATE; /**< CPU state (ARM or Thumb) */ + + // Scan for a valid frame in the first few instructions + for (i = 4; i < BT_SCAN_MAX_LIMIT; i += 4) { + parse_addr = PC - i; + if (backtrace_check_address(parse_addr) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", parse_addr); + return -1; /**< Invalid address encountered */ + } + + ins32 = *(long *) parse_addr; /**< Fetch the instruction at the parse address */ + framesize = arm_get_push_lr_ins_framesize(ins32, &offset); /**< Determine the frame size and offset */ + if (framesize >= 0) { + break; /**< Found a valid instruction with frame size */ + } + } + + // Trace information about the found instruction and frame size + printk_trace("BT: i = %d, parse_addr = %p, PC = %p, offset = %d, framesize = %d\n", i, parse_addr, PC, offset, framesize); + + if (i == BT_SCAN_MAX_LIMIT) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. scope overflow\n"); + return -1; /**< Reached the scan limit without finding a valid frame */ + } + + // Scan the stack for additional instructions and calculate frame size + for (i = 4; parse_addr + i < PC; i += 4) { + if (backtrace_check_address(parse_addr + i) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", parse_addr + i); + return -1; /**< Invalid address encountered */ + } + + ins32 = *(uint64_t *) (parse_addr + i); /**< Fetch the instruction at the next address */ + temp = arm_backtrace_stack_push(ins32); /**< Calculate the additional frame size */ + if (temp >= 0) { + framesize += temp; /**< Add the frame size to the total */ + } + + if (ins32 == 0xef000000) { /**< SWI (Software Interrupt) detected */ + swi_num++; /**< Count the number of software interrupts */ + } + } + + // Check if previous instruction is valid and update frame size + if (backtrace_check_address(parse_addr - 4)) { + ins32 = *(uint64_t *) (parse_addr - 4); /**< Get the previous instruction */ + } else { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr - 4); + return -1; /**< Invalid address encountered */ + } + + temp = arm_backtrace_stack_push(ins32); /**< Update frame size based on the previous instruction */ + if (temp >= 0) { + framesize += temp; + offset += temp; + } + + framesize -= swi_num; /**< Adjust the frame size by subtracting the SWI count */ + + // Determine the link register (LR) based on the offset + if (offset == 0) { + LR = *pLR; /**< Use the provided LR if no offset was found */ + } + + if (LR == NULL) { + if (backtrace_check_address(SP + framesize - offset)) { + LR = (char *) *(SP + framesize - offset); /**< Calculate LR from stack if not provided */ + } else { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", SP + framesize - offset); + return -1; /**< Invalid address for LR calculation */ + } + } + + // Check the validity of the LR address + if (backtrace_check_address(LR) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); + return -1; /**< Invalid LR address */ + } + + *pSP = SP + framesize; /**< Update the stack pointer */ + offset = find_lr_offset(LR, &state); /**< Find the offset of the LR based on the state */ + *pPC = LR - offset; /**< Calculate the program counter (PC) based on LR and offset */ + + // Adjust the program counter if in Thumb mode + if (state == THUMB_STATE) { + MAKE_THUMB_ADDR(*pPC); /**< Adjust PC for Thumb instructions */ + } + + // Trace the final stack pointer, program counter, and frame size + printk_trace("BT: *pSP = %p, offset = %d, *pPC = %p, framesize = %d, state = %d\n", *pSP, offset, *pPC, framesize, state); + + return offset == 0 ? 1 : 0; /**< Return 1 if backtrace is successful, else 0 or -1 */ +} + +/** + * @brief Backtrace from stack based on program counter (PC) state. + * + * This function performs a backtrace by checking if the current code is running in ARM or Thumb + * state and calls the appropriate backtrace function accordingly. If the program counter (PC) + * address is invalid, it returns an error. + * + * @param pSP Pointer to the stack pointer. + * @param pPC Pointer to the program counter. + * @param pLR Pointer to the link register. + * + * @return 0 if backtrace was successful, -1 if the PC is invalid or an error occurred. + */ +static int backtrace_from_stack(int **pSP, char **pPC, char **pLR) { + // Check if the provided program counter (PC) address is valid + if (backtrace_check_address(*pPC) == 0) { + return -1;// Invalid address, return error + } + + // Check if the address is in Thumb state (16-bit instruction set) + if (IS_THUMB_ADDR(*pPC)) { + return thumb_backtrace_from_stack(pSP, pPC, pLR);// Perform Thumb-specific backtrace + } else { + return arm_bakctrace_from_stack(pSP, pPC, pLR);// Perform ARM-specific backtrace + } +} + +/** + * @brief Pop a frame from the stack for Thumb instructions. + * + * This function processes a Thumb instruction to determine the frame size + * and updates the stack pointer change flag. It distinguishes between normal + * "pop" and vector "vpop" instructions. + * + * @param inst The Thumb instruction to analyze. + * @param sp_change Pointer to a flag that will be set to 1 if the stack pointer changes. + * @param thumb32bit Flag indicating if the instruction is Thumb-32 bit (true) or not (false). + * + * @return The size of the frame to pop, or -1 if no valid "pop" instruction is found. + */ +static int thumb_backtrace_stack_pop(uint32_t inst, uint8_t *sp_change, int thumb32bit) { + int framesize = -1; /**< Initialize frame size to -1 (invalid) */ + + // Check for non-Thumb-32 bit instruction + if (!thumb32bit) { + // Check for "pop {...}" instruction pattern + if ((inst & 0xff00) == 0xbc00) { + printk_trace("BT: \tpop {...}\n"); /**< Trace log for pop instruction */ + framesize = __builtin_popcount((uint8_t) inst); /**< Count the number of registers popped */ + *sp_change = 1; /**< Set stack pointer change flag */ + } + } else { + // Check for "vpop {...}" instruction pattern + if ((inst & 0xffbf0f00) == 0xecbd0b00) { + printk_trace("BT: \tvpop {...}\n"); /**< Trace log for vpop instruction */ + framesize = inst & 0xFF; /**< Get the frame size from the instruction */ + *sp_change = 1; /**< Set stack pointer change flag */ + } + } + + printk_trace("BT: inst = 0x%x, framesize = %d\n", inst, framesize); /**< Log the instruction and frame size */ + return framesize; /**< Return the calculated frame size (or -1 if invalid) */ +} + +/** + * @brief Process the return instruction for Thumb mode and determine the frame size. + * + * This function checks if the current instruction is a return instruction, such as + * "bx lr", which is used for returning from functions in ARM architecture. + * It specifically handles the case for Thumb mode instructions and sets the + * frame size appropriately. + * + * @param inst The Thumb instruction to analyze. + * @param thumb32bit Flag indicating if the instruction is Thumb-32 bit (true) or not (false). + * + * @return 0 if the return instruction is detected, otherwise the frame size (or -1 if not detected). + */ +static int thumb_backtrace_return_pop(uint32_t inst, int thumb32bit) { + int framesize = -1; /**< Initialize frame size to -1 (invalid) */ + + // Check for non-Thumb-32 bit instruction + if (!thumb32bit) { + /* Check for "bx lr" instruction (branch to link register) */ + printk_trace("BT: \tbx lr\n"); /**< Trace log for bx lr instruction */ + if ((inst & 0xFFFF) == 0x4770) { + return 0; /**< Return 0 for a valid return instruction */ + } + } + + printk_trace("BT: inst = 0x%x, framesize = %d\n", inst, framesize); /**< Log the instruction and frame size */ + return framesize; /**< Return the frame size (or -1 if not a valid return instruction) */ +} + +/** + * @brief Calculate the frame size for a "push" instruction in Thumb mode. + * + * This function checks if the instruction is a "push" instruction or a "sub sp" instruction + * in Thumb-32 bit mode. It determines the frame size based on the instruction and sets + * the jump flag if needed. + * + * @param inst The Thumb instruction to analyze. + * @param jump Pointer to a flag that will be set to 1 if the instruction is a "push". + * @param thumb32bit Flag indicating if the instruction is Thumb-32 bit (true) or not (false). + * + * @return The calculated frame size, or -1 if the instruction does not match "push" or "sub sp". + */ +static int thumb_get_push_ins_framesize(uint32_t inst, uint8_t *jump, int thumb32bit) { + int framesize = -1; /**< Initialize frame size to -1 (invalid) */ + + // Check for Thumb-32 bit instructions + if (thumb32bit) { + // Check for "push {...}" instruction pattern + if ((inst & 0xff00) == 0xb400) { + printk_trace("BT: \tpush {...}\n"); /**< Trace log for push instruction */ + framesize = __builtin_popcount((uint8_t) inst); /**< Count the number of registers pushed */ + *jump = 1; /**< Set jump flag to 1 */ + } + // Check for "sub sp, #immed" instruction pattern + else if ((inst & 0xff80) == 0xb080) { + printk_trace("BT: \tsub sp, #immed\n"); /**< Trace log for sub sp instruction */ + framesize = (inst & 0x7f); /**< Get immediate value to determine the frame size */ + } + } + + printk_trace("BT: inst:0x%x, framesize = %d\n", inst, framesize); /**< Log the instruction and frame size */ + return framesize; /**< Return the calculated frame size (or -1 if invalid) */ +} + +/** + * @brief Perform a backtrace from the Link Register (LR) in Thumb mode. + * + * This function extracts the frame size from the LR and updates the SP and PC + * based on the Thumb instruction set. It scans the instructions, identifies + * the backtrace points, and handles stack frame adjustments. + * + * @param pSP Pointer to the stack pointer. + * @param pPC Pointer to the program counter. + * @param LR The link register address to backtrace from. + * @return 1 if backtrace is successful, 0 if the frame is not valid, -1 on error. + */ +static int thumb_backtrace_from_lr(int **pSP, char **pPC, char *LR) { + int *SP = *pSP; /**< Current stack pointer */ + char *PC = PC2ADDR(*pPC); /**< Program counter address converted to proper format */ + char *parse_addr = NULL; /**< Address used for parsing instructions */ + int i, temp = 0; /**< Loop counter and temporary value for instruction processing */ + uint32_t ins32 = 0, framesize = 0, offset = 0; /**< Instruction, frame size, and LR offset */ + uint8_t sp_change = 0, jump = 0; /**< Flags indicating stack pointer change and jump */ + + bool state = THUMB_STATE; /**< Current CPU state (Thumb or ARM) */ + + // Check if the program counter is a valid text address + if (backtrace_check_address(PC) == 0) { + // Check if the link register is a valid address + if (backtrace_check_address(LR) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); /**< Log invalid LR address */ + return -1; /**< Return error on invalid LR */ + } + // Find the LR offset and adjust the program counter + offset = find_lr_offset(LR, &state); + PC = LR - offset; /**< Adjust program counter based on LR offset */ + *pPC = PC; /**< Update PC pointer */ + return offset == 0 ? 1 : 0; /**< Return success if offset is 0, otherwise return failure */ + } + + // Start scanning instructions to perform backtrace + for (i = 2; i < BT_SCAN_MAX_LIMIT; i += 2) { + parse_addr = PC + i; /**< Set the address to parse the instruction */ + int error = 0; /**< Error flag for instruction fetching */ + int thumb32bit = 0; /**< Flag for Thumb-32 bit mode */ + + // Get the next Thumb instruction + ins32 = thumb_get_next_inst(&error, &i, PC + i + 2, PC + i, 1, &thumb32bit); + if (error) { + return -1; /**< Return error if instruction fetching fails */ + } + + printk_trace("BT: parse_addr = 0x%x, i = %d\n", parse_addr, i); /**< Trace parsed address */ + + // Check if it's a stack pop operation + temp = thumb_backtrace_stack_pop(ins32, &sp_change, thumb32bit); + if (temp >= 0) { + continue; /**< Continue scanning if it's a valid stack pop */ + } + + // Check if it's a return pop operation + temp = thumb_backtrace_return_pop(ins32, thumb32bit); + if (temp >= 0) { + framesize += temp; /**< Add frame size for return pop */ + break; /**< Break after finding the return pop */ + } + } + + // If scan limit is exceeded, return an error + if (i == BT_SCAN_MAX_LIMIT) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. scope overflow\n"); /**< Log failure */ + return -1; + } + + printk_trace("BT: parse_addr = 0x%08x, framesize = %d, sp_change = %d\n", parse_addr, framesize, sp_change); /**< Log framesize and SP change status */ + + // If the stack pointer has changed, scan for push instructions + if (sp_change) { + for (i = 2; i < BT_SCAN_MAX_LIMIT; i += 2) { + parse_addr = PC - i; /**< Adjust the parse address for backwards scanning */ + int error = 0; + int thumb32bit = 0; + + // Get the next Thumb instruction while scanning backwards + ins32 = thumb_get_next_inst(&error, &i, parse_addr, parse_addr - 2, 0, &thumb32bit); + if (error) { + return -1; /**< Return error if instruction fetching fails */ + } + + // Check if it's a push instruction and adjust framesize + temp = thumb_get_push_ins_framesize(ins32, &jump, thumb32bit); + if (temp >= 0) { + framesize += temp; /**< Add to framesize for push instruction */ + } + if (jump > 0) { + break; /**< Break if a jump is encountered */ + } + } + } + + // Check if the LR is still valid + if (backtrace_check_address(LR) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); /**< Log invalid LR */ + return -1; /**< Return error if LR is invalid */ + } + + // Update the stack pointer and program counter + *pSP = SP + framesize; /**< Update stack pointer based on framesize */ + offset = find_lr_offset(LR, &state); /**< Find LR offset */ + *pPC = LR - offset; /**< Update program counter */ + + // Adjust program counter if in Thumb state + if (state == THUMB_STATE) { + MAKE_THUMB_ADDR(*pPC); /**< Adjust PC to Thumb address format */ + } + + printk_trace("BT: *pSP = %p, offset = %d, *pPC = %p, framesize = %d, state=%d\n", *pSP, offset, *pPC, framesize, state); /**< Trace final backtrace information */ + + return offset == 0 ? 1 : 0; /**< Return success or failure based on LR offset */ +} + +/** + * @brief Analyze the ARM instruction to determine the frame size for backtrace. + * + * This function interprets an ARM instruction and determines the frame size based on the + * instruction type. It handles the following instructions: + * - `pop {..., pc}`: Pops the program counter (pc) from the stack. + * - `bx lr`: Branches to the link register (lr), effectively returning from a function. + * - `ldr pc, [sp], #4`: Loads the program counter (pc) from the stack and updates the stack pointer. + * + * @param inst The ARM instruction to analyze. + * + * @return The size of the frame affected by the instruction. + */ +static int arm_backtrace_return_pop(uint32_t inst) { + int framesize = -1; /**< Default frame size is -1 (unknown) */ + + if ((inst & 0x0FFF8000) == 0x08BD8000) { /**< Check for 'pop {..., pc}' instruction */ + printk_trace("BT: \tpop {..., pc}\n"); + framesize = __builtin_popcount(inst & 0xFFFF); /**< Count the number of registers popped */ + } else if ((inst & 0x0FFFFFFF) == 0x012FFF1E) { /**< Check for 'bx lr' instruction */ + printk_trace("BT: \tbx lr\n"); + framesize = 0; /**< No frame size change for 'bx lr' */ + } else if ((inst & 0x0FFFFFFF) == 0x049DF004) { /**< Check for 'ldr pc, [sp], #4' instruction */ + printk_trace("BT: \tldr pc, [sp], #4\n"); + framesize = 1; /**< Frame size is 1 for 'ldr pc, [sp], #4' */ + } + + printk_trace("BT: inst = 0x%x, framesize = %d\n", inst, framesize); /**< Log instruction and frame size */ + return framesize; /**< Return the computed frame size */ +} + +/** + * @brief Analyze the ARM instruction to determine the frame size for stack pop operations. + * + * This function interprets an ARM instruction and determines the frame size based on the + * instruction type. It handles the following instructions: + * - `add sp, sp, #imm`: Adds an immediate value to the stack pointer (sp). + * - `pop {...}`: Pops a set of registers from the stack. + * - `vpop {...}`: Pops a set of vector registers from the stack. + * - `ldr xxx, [sp], #4`: Loads a value from the stack into a register and updates the stack pointer. + * + * @param inst The ARM instruction to analyze. + * + * @return The size of the frame affected by the instruction. + */ +static int arm_backtrace_stack_pop(uint32_t inst) { + uint32_t add; /**< Immediate value to be added to the stack pointer */ + uint32_t shift; /**< Shift value for scaling the immediate */ + int framesize = -1; /**< Default frame size is -1 (unknown) */ + + if ((inst & 0x0FFFF000) == 0x028DD000) { /**< Check for 'add sp, sp, #imm' instruction */ + printk_trace("BT: \tadd sp, sp, #imm\n"); + add = inst & 0xFF; /**< Extract the immediate value */ + shift = (inst >> 8) & 0xF; /**< Extract the shift value */ + if (shift != 0) { /**< Apply shift if non-zero */ + shift = 32 - 2 * shift; + add = add << shift; + } + framesize = add / 4; /**< Frame size is the immediate value divided by 4 (stack units) */ + } else if ((inst & 0x0FFF0000) == 0x08BD0000) { /**< Check for 'pop {...}' instruction */ + printk_trace("BT: \tpop {...}\n"); + framesize = __builtin_popcount(inst & 0xFFFF); /**< Count the number of registers popped */ + } else if ((inst & 0x0FBF0F00) == 0x0CBD0B00) { /**< Check for 'vpop {...}' instruction */ + printk_trace("BT: \tvpop {...}\n"); + framesize = inst & 0xFF; /**< Frame size is determined by the immediate value (vector registers) */ + } else if ((inst & 0x0FFF0FFF) == 0x049D0004) { /**< Check for 'ldr xxx, [sp], #4' instruction */ + printk_trace("BT: \tldr xxx, [sp], #4\n"); + framesize = 1; /**< Frame size is 1 (single word loaded) */ + } + + printk_trace("BT: inst = 0x%x, framesize = %d\n", inst, framesize); /**< Log the instruction and computed frame size */ + return framesize; /**< Return the computed frame size */ +} + +/** + * @brief Perform backtrace from the link register (LR) to determine the stack pointer (SP) and program counter (PC). + * + * This function performs a backtrace from the provided LR (link register) to locate the stack pointer + * and program counter of the current function. It checks the validity of addresses, scans instructions + * to compute the stack frame size, and adjusts the program counter based on the ARM instruction set state + * (ARM or Thumb). + * + * @param pSP A pointer to the stack pointer (SP) to be updated. + * @param pPC A pointer to the program counter (PC) to be updated. + * @param LR The link register value from which the backtrace will begin. + * + * @return 1 if backtrace is successful with no offset, 0 if backtrace is successful with offset, + * or -1 if there is an error during the process. + */ +static int arm_backtrace_from_lr(int **pSP, char **pPC, char *LR) { + int *SP = *pSP; /**< Current stack pointer */ + char *PC = *pPC; /**< Current program counter */ + char *parse_addr = NULL; /**< Temporary address used for parsing instructions */ + int i, temp, framesize = 0, offset; /**< Loop index, temporary storage, and frame size */ + uint32_t ins32; /**< 32-bit instruction */ + bool state = ARM_STATE; /**< ARM state (ARM or Thumb) */ + + if (backtrace_check_address(PC) == 0) { /**< Check if PC is a valid address */ + if (backtrace_check_address(LR) == 0) { /**< Check if LR is a valid address */ + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); + return -1; /**< Invalid LR address */ + } + offset = find_lr_offset(LR, &state); /**< Find the offset of LR */ + PC = LR - offset; /**< Set PC to LR minus offset */ + *pPC = PC; /**< Update the program counter pointer */ + return offset == 0 ? 1 : 0; /**< Return success or failure based on the offset */ + } + + for (i = 0; i < BT_SCAN_MAX_LIMIT; i += 4) { /**< Scan instructions up to a maximum limit */ + parse_addr = PC + i; + if (backtrace_check_address(parse_addr)) { + ins32 = *(uint64_t *) parse_addr; /**< Read instruction at current address */ + } else { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", parse_addr); + return -1; /**< Invalid instruction address */ + } + framesize = arm_backtrace_return_pop(ins32); /**< Analyze instruction for stack frame size */ + if (framesize >= 0) { /**< Frame size found, break loop */ + break; + } + + temp = arm_get_push_lr_ins_framesize(ins32, &offset); /**< Check for push lr instruction */ + if (temp >= 0) { /**< Valid push lr instruction found */ + framesize = 0; /**< No frame size adjustment needed */ + break; + } + } + + if (i == BT_SCAN_MAX_LIMIT) { /**< If the maximum scan limit is reached, fail the backtrace */ + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. scope overflow\n"); + return -1; + } + + for (i = 4; parse_addr - i >= PC; i += 4) { /**< Scan previous instructions to adjust frame size */ + if (backtrace_check_address(parse_addr - i)) { + ins32 = *(uint64_t *) (parse_addr - i); /**< Read previous instruction */ + } else { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr - i); + return -1; /**< Invalid address during scan */ + } + temp = arm_backtrace_stack_pop(ins32); /**< Analyze instruction for stack pop size */ + if (temp >= 0) { /**< Valid stack pop found, update frame size */ + framesize += temp; + } + } + + if (backtrace_check_address(LR) == 0) { /**< Check if LR is a valid address again */ + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); + return -1; /**< Invalid LR address */ + } + *pSP = SP + framesize; /**< Update the stack pointer based on the calculated frame size */ + offset = find_lr_offset(LR, &state); /**< Recalculate LR offset */ + *pPC = LR - offset; /**< Update program counter (PC) based on LR and offset */ + + if (state == THUMB_STATE) { /**< If the state is Thumb, adjust the PC address for Thumb mode */ + MAKE_THUMB_ADDR(*pPC); + } + + printk_trace("BT: *pSP = %p, offset = %d, *pPC = %p, framesize = %d, state = %d\n", *pSP, offset, *pPC, framesize, state); + + return offset == 0 ? 1 : 0; /**< Return 1 for success with no offset, 0 for success with offset */ +} + +/** + * @brief Perform a backtrace from the Link Register (LR). + * + * This function determines whether the current address is in Thumb mode or ARM mode + * and calls the appropriate backtrace function based on the result. + * + * @param pSP Pointer to the stack pointer. + * @param pPC Pointer to the program counter. + * @param LR The link register address to backtrace from. + * @return 1 if backtrace is successful, 0 if the frame is not valid, -1 on error. + */ +static int backtrace_from_lr(int **pSP, char **pPC, char *LR) { + // Check if the current program counter is in Thumb mode + if (IS_THUMB_ADDR(*pPC)) { + return thumb_backtrace_from_lr(pSP, pPC, LR); /**< Call Thumb backtrace function */ + } else { + return arm_backtrace_from_lr(pSP, pPC, LR); /**< Call ARM backtrace function */ + } +} + +/** + * @brief Perform a backtrace to find the call stack. + * + * This function attempts to walk the call stack by analyzing the program counter (PC), + * stack pointer (SP), and link register (LR) to determine the sequence of function calls + * leading to the current execution point. + * + * The backtrace process works by using the stack and link register to trace the call hierarchy, + * logging each level of the backtrace, and attempting recovery from any errors. + * If the backtrace from the stack fails, it will attempt to trace using the link register (LR). + * + * @param PC The current program counter (PC), typically pointing to the instruction where the backtrace starts. + * @param SP The current stack pointer (SP), pointing to the top of the stack. + * @param LR The link register (LR), used to store return addresses for function calls. + * + * @return The number of backtrace levels successfully traversed. + * Returns 0 if no valid backtrace could be performed. + */ +int backtrace(char *PC, long *SP, char *LR) { + int level = 0;///< Backtrace level counter + int ret; ///< Return value for backtrace_from_stack + + /* Backup PC, SP, LR for backtrace_from_lr */ + char *_PC = PC;///< Program counter (PC) + long *_SP = SP;///< Stack pointer (SP) + char *_LR = LR;///< Link register (LR) + + // Log the current program counter (PC) + printk(LOG_LEVEL_BACKTRACE, "backtrace: 0x%08x\n", PC); + + // Traverse the stack and perform backtrace + for (level = 1; level < BT_LEVEL_LIMIT; level++) { + ret = backtrace_from_stack((int **) &SP, &PC, &LR);///< Get the next backtrace level + if (ret != 0) { + break;///< Stop if backtrace fails + } + } + + /* If stack backtrace fails, try to trace using the link register (LR) */ + if (level == 1) { + ret = backtrace_from_lr((int **) &_SP, &_PC, _LR); + if (ret == 0) { + for (; level < BT_LEVEL_LIMIT; level++) { + ret = backtrace_from_stack((int **) &SP, &PC, &LR); + if (ret != 0) { + break; + } + } + } + } + + // Return the backtrace level, ensuring it's at least 0 + return level > 0 ? level : 0; +} + +/** + * @brief Dumps the current stack state and performs a backtrace. + * + * This function captures the current program counter (PC), stack pointer (SP), + * link register (LR), and current processor status register (CPSR). It uses inline assembly + * to obtain these values, then performs a backtrace to provide insight into the function call stack. + * + * The function also checks if the processor is in THUMB mode based on the CPSR state and adjusts + * the program counter (PC) accordingly. If the program counter or stack pointer is invalid, + * the function will return early with a status of 0. + * + * @return The result of the backtrace function, representing the number of successfully + * traced backtrace levels, or 0 if the stack pointer (SP) or program counter (PC) is invalid. + */ +int dump_stack(void) { + char *PC = NULL;///< Program counter (PC) + long *SP = NULL;///< Stack pointer (SP) + char *LR = NULL;///< Link register (LR) + int CPSR = 0; + + // Inline assembly to get the current stack pointer (SP), program counter (PC), link register (LR), + // and current processor status register (CPSR). + asm volatile("mov %0, sp\r\n" + : "=r"(SP)); + asm volatile("mov %0, pc\r\n" + : "=r"(PC)); + asm volatile("mov %0, lr\r\n" + : "=r"(LR)); + asm volatile("mrs %0, CPSR\r\n" + : "=r"(CPSR)); + + /* CPSR Thumb state bit. bit[5] */ + if (CPSR & 0x20) { + MAKE_THUMB_ADDR(PC);///< Adjust PC if in THUMB mode. + } + + // Check if stack pointer or program counter is invalid + if (SP == NULL || PC == NULL) { + return 0;///< Return 0 if SP or PC is invalid + } + + // Perform the backtrace using the collected values for PC, SP, and LR + return backtrace(PC, SP, LR); +} diff --git a/src/arch/arm32/exception.c b/src/arch/arm32/exception.c index a530126b8..204efb81f 100644 --- a/src/arch/arm32/exception.c +++ b/src/arch/arm32/exception.c @@ -1,8 +1,9 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include #include @@ -12,6 +13,20 @@ extern void abort(); +// #define START_UP_DEBUG +#ifdef START_UP_DEBUG +void int_to_hex_string(int value, char* buffer) { + char hex_digits[] = "0123456789ABCDEF"; + int i; + + for (i = 0; i < 8; i++) { + buffer[7 - i] = hex_digits[value & 0xF]; + value >>= 4; + } + buffer[8] = '\0'; +} +#endif + static void show_regs(struct arm_regs_t *regs) { int i = 0; @@ -20,6 +35,14 @@ static void show_regs(struct arm_regs_t *regs) { for (i = 12; i >= 0; i--) printk_error("r%-2d: 0x%08lx\n", i, regs->r[i]); printk_error("\n"); + + char *PC = (char *) regs->pc; + long *SP = (long *) regs->sp; + char *LR = (char *) regs->lr; + if (regs->cpsr & 0x20) { + MAKE_THUMB_ADDR(PC); + } + backtrace(PC, SP, LR); } void __attribute__((weak)) arm32_do_undefined_instruction(struct arm_regs_t *regs) { diff --git a/src/arch/arm32/timer.c b/src/arch/arm32/timer.c index cacb3a607..fd4decbd0 100644 --- a/src/arch/arm32/timer.c +++ b/src/arch/arm32/timer.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/arch/riscv/riscv32_e907/CMakeLists.txt b/src/arch/riscv/riscv32_e907/CMakeLists.txt index b19eb5892..50e63dddd 100644 --- a/src/arch/riscv/riscv32_e907/CMakeLists.txt +++ b/src/arch/riscv/riscv32_e907/CMakeLists.txt @@ -1,6 +1,7 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_library(arch-obj OBJECT + backtrace.c timer.c exception.c memcpy.S diff --git a/src/arch/riscv/riscv32_e907/backtrace.c b/src/arch/riscv/riscv32_e907/backtrace.c new file mode 100644 index 000000000..a2f0e4ee4 --- /dev/null +++ b/src/arch/riscv/riscv32_e907/backtrace.c @@ -0,0 +1,965 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#if LOG_LEVEL_DEFAULT <= LOG_LEVEL_DEBUG +#define LOG_LEVEL_DEFAULT LOG_LEVEL_TRACE +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define CONFIG_ARCH_RISCV32 1 + +/** + * @brief Maximum limit for backtrace scanning. + * + * This constant defines the maximum limit for scanning the backtrace. + * The backtrace function will scan instructions and stack frames + * up to this size. If the limit is exceeded, the backtrace operation will fail. + */ +#define BT_SCAN_MAX_LIMIT 0xFFFFFF + +/** + * @brief Maximum number of backtrace levels. + * + * This constant defines the maximum depth of the backtrace. It limits + * how many stack frames the backtrace function can unwind before stopping. + */ +#define BT_LEVEL_LIMIT 64 + +/** + * @brief Converts a program counter (PC) value to an address. + * + * This macro takes a program counter (PC) value and converts it to + * a valid address by clearing the least significant bit. This operation + * is commonly used to align PC addresses properly for instruction fetch. + * + * @param pc The program counter value to convert. + * @return The corresponding address, aligned to a 2-byte boundary. + */ +#define PC2ADDR(pc) ((char *) (((uint32_t) (pc)) & 0xfffffffe)) + +/** + * @brief Determines the length of an instruction in bytes based on its encoding. + * + * This macro computes the length of an instruction in bytes, given a 32-bit + * instruction encoding. The length is determined based on specific bit patterns + * in the instruction word. + * + * @param x The instruction encoding (32-bit). + * @return The length of the instruction in bytes (either 2, 4, 6, or 8). + */ +#define insn_length(x) (((x) &0x03) < 0x03 ? 2 : ((x) &0x1f) < 0x1f ? 4 \ + : ((x) &0x3f) < 0x3f ? 6 \ + : 8) + +/** + * @brief Extracts a specific bit field from a value. + * + * This macro extracts a bit field from a value `x` based on the specified + * high and low bit positions. The bits are masked and shifted to the + * right, leaving the desired bit field. + * + * @param x The value from which to extract the bit field. + * @param high The index of the highest bit (inclusive). + * @param low The index of the lowest bit (inclusive). + * @return The extracted bit field. + */ +#define BITS(x, high, low) ((x) & (((1 << ((high) - (low) + 1)) - 1) << (low))) + +/** + * @brief Pointer to the start of the image in memory. + * + * This variable marks the start address of the memory region that + * contains the program image. It is used to check if a program counter + * (PC) value falls within the valid range of executable memory. + */ +extern uint8_t __spl_start[]; + +/** + * @brief Pointer to the end of the stack service region. + * + * This variable marks the end address of the memory region used for the + * stack service. It is used to check if a program counter (PC) value falls + * within the valid memory region, preventing access to out-of-bounds memory. + */ +extern uint8_t __stack_srv_end[]; + +/** + * @brief Checks whether a given program counter (PC) address is within a valid range. + * + * This function checks if the provided PC (program counter) value lies within + * the memory region between `__spl_start` and `__stack_srv_end`. It ensures that + * the PC value points to a valid memory address in the executable region of the program. + * + * @param pc The program counter value to check. + * @return 1 if the PC is within the valid address range, 0 otherwise. + */ +static int inline backtrace_check_address(void *pc) { + if (((uint32_t) pc > (uint32_t) __spl_start) && ((uint32_t) pc < (uint32_t) __stack_srv_end)) { + return 1; /**< Valid address in the range. */ + } + return 0; /**< Invalid address outside the range. */ +} + +/** + * @brief Finds the offset of the Link Register (LR) from the return address in a backtrace. + * + * This function attempts to determine the offset of the Link Register (LR) from the return + * address in a backtrace. It checks whether the LR corresponds to an IRQ handler exit address + * and adjusts accordingly. The function also checks the validity of the address and computes + * the instruction length based on the encoded instruction in memory. + * + * @param LR The address of the Link Register (LR) to be checked. + * @return The offset from the LR to the return address if valid, 0 if invalid or the address is + * within an IRQ handler exit region. + */ +static int riscv_backtrace_find_lr_offset(char *LR) { + char *LR_fixed; + uint16_t ins16; + int offset = 4; /**< Initial offset value for standard instruction length. */ + uint64_t *irq_entry = NULL; /**< Pointer to the IRQ entry (interrupt handler entry address). */ + + LR_fixed = LR; + + /* Check if the LR corresponds to the IRQ handler exit address. */ + if (LR_fixed == PC2ADDR(irq_entry)) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: 0x%08x\n", irq_entry); /**< Log IRQ entry address if match found. */ + return 0; /**< Return 0, indicating no valid offset. */ + } + + /* Validate that the address (LR - 4) points to executable code. */ + if (backtrace_check_address(LR_fixed - 4) == 0) { + return 0; /**< Return 0 if the address is invalid (not in valid text region). */ + } + + /* Retrieve the instruction at LR - 4 and compute the instruction length. */ + ins16 = *(uint16_t *) (LR_fixed - 4); /**< Fetch the instruction at LR-4. */ + offset = insn_length(ins16); /**< Compute the length of the instruction. */ + + printk(LOG_LEVEL_BACKTRACE, "backtrace: 0x%08x\n", LR_fixed - offset); /**< Log the address after offset adjustment. */ + + return offset; /**< Return the computed offset. */ +} + +/** + * @brief Determines the frame size for a push to the link register (LR) in a RISC-V instruction. + * + * This function analyzes a 32-bit RISC-V instruction to determine whether it corresponds to a + * "push" operation to the link register (LR) or the stack pointer (SP), and computes the + * associated frame size or offset. The function specifically handles instructions that + * manipulate the stack pointer or the link register. + * + * @param inst The 32-bit instruction to analyze. + * @param offset A pointer to an integer where the computed offset (in terms of long size) will be stored. + * @return int Returns 0 if the instruction is valid and corresponds to a push operation, -1 otherwise. + */ +int riscv_ins32_get_push_lr_framesize(uint32_t inst, int *offset) { + int ret = -1; + + printk_trace("BT: inst:0x%x\n", inst); + + // Check for 'sd ra, (offset)sp' instruction + if ((inst & 0x01FFF07F) == 0x113023) { + /* sd ra, (offset)sp */ + int immed = (inst & 0xF80); + immed >>= 7; + immed |= ((inst & 0xFE000000) >> 25) << 5; + if (((immed >> 11) & 0x01) != 0) { + immed = 0xFFF - immed + 1; + } + *offset = immed / sizeof(long); + ret = -1; + } + // Check for 'addi sp, sp, #imm' instruction + else if ((inst & 0x000FFFFF) == 0x10113) { + /* addi sp, sp, #imm */ + int immed = BITS(inst, 31, 20); + immed >>= 20; + immed &= 0xFFF; + if ((immed >> 11) != 0) { + immed = 0xFFF - immed + 1; + ret = 0; + } else { + ret = -1; + } + } +#if !defined(CONFIG_ARCH_RISCV32) /* RISCV32 not support addiw sp, sp, #imm */ + // Check for 'addiw sp, sp, #imm' instruction + else if ((inst & 0x000FFFFF) == 0x1011B) { + /* addiw sp, sp, #imm */ + int immed = BITS(inst, 31, 20); + immed >>= 20; + immed &= 0xFFF; + if ((immed >> 11) != 0) { + immed = 0xFFF - immed + 1; + ret = 0; + } else { + ret = -1; + } + } +#endif + + return ret; +} + +/** + * @brief Determines the frame size for a push to the link register (LR) in a RISC-V compressed instruction. + * + * This function analyzes a 16-bit RISC-V compressed instruction (C-extension) to determine if it corresponds + * to a "push" operation to the link register (LR) or the stack pointer (SP), and computes the associated + * frame size or offset. The function specifically handles instructions that manipulate the stack pointer + * or the link register in compressed RISC-V instructions. + * + * @param inst The 16-bit compressed instruction to analyze. + * @param offset A pointer to an integer where the computed offset (in terms of long size) will be stored. + * + * @return int Returns 0 if the instruction is valid and corresponds to a push operation, -1 otherwise. + */ +static int riscv_ins16_get_push_lr_framesize(uint16_t inst, int *offset) { + int ret = -1; + + printk_trace("BT: inst:0x%x: \n", inst); + + // Check for 'c.sdsp ra, (offset)sp' instruction + if ((inst & 0xE07E) == 0xE006) { + /* c.sdsp ra, (offset)sp */ + int immed_6_8 = (inst >> 7) & 0x07; + int immed_3_5 = (inst >> 10) & 0x07; + int immed = immed_6_8 << 6 | immed_3_5 << 3; + *offset = immed / sizeof(long); + printk_trace("BT: \tc.sdsp ra, (offset%p)sp, #immed=%d \n", offset, immed); + ret = -1; + } + // Check for 'c.swsp ra, (offset)sp' instruction + else if ((inst & 0xE07E) == 0xC006) { + /* c.swsp ra, (offset)sp */ + int immed_6_7 = (inst >> 7) & 0x03; + int immed_2_5 = (inst >> 9) & 0x0f; + int immed = immed_6_7 << 6 | immed_2_5 << 2; + *offset = immed / sizeof(long); + printk_trace("BT: \tc.swsp ra, (offset%p)sp, #immed=%d \n", offset, immed); + ret = -1; + } + // Check for 'c.addi16sp #imm' instruction + else if ((inst & 0xEF83) == 0x6101) { + /* c.addi16sp #imm */ + int immed_5 = (inst >> 2) & 0x01; + int immed_7_8 = (inst >> 3) & 0x3; + int immed_6 = (inst >> 5) & 0x1; + int immed_4 = (inst >> 6) & 0x1; + int immed_9 = (inst >> 12) & 0x1; + int immed = immed_5 << 5 | immed_7_8 << 7 | immed_6 << 6 | immed_4 << 4 | immed_9 << 9; + + printk_trace("BT: \tc.addi16sp #immed=%d \n", immed); + + if ((immed >> 9) != 0) { + immed = 0x3FF - immed + 1; + ret = 0; + } else { + ret = -1; + } + } + // Check for 'c.addi sp, sp, #imm' instruction + else if ((inst & 0xEF03) == 0x101) { + /* c.addi sp, sp, #imm */ + int immed_0_4 = (inst >> 2) & 0x1F; + int immed_5 = (inst >> 12) & 0x1; + int immed = immed_5 << 5 | immed_0_4; + + printk_trace("BT: \tc.addi sp, sp, #immed=%d \n", immed); + + if ((immed >> 5) != 0) { + immed = 0x3F - immed + 1; + ret = 0; + } else { + ret = -1; + } + } +#if !defined(CONFIG_ARCH_RISCV32) /* RISCV32 not support c.addiw sp */ + // Check for 'c.addiw sp, #imm' instruction + else if ((inst & 0xEF03) == 0x2101) { + /* c.addiw sp, #imm */ + int immed_0_4 = (inst >> 2) & 0x1F; + int immed_5 = (inst >> 12) & 0x1; + int immed = immed_5 << 5 | immed_0_4; + + printk_trace("BT: \tc.addiw sp, #immed=%d \n", immed); + + if ((immed >> 5) != 0) { + immed = 0x3F - immed + 1; + ret = 0; + } else { + ret = -1; + } + } +#endif + + printk_trace("BT: \tret = %d\n", ret); + return ret; +} + +/** + * @brief Checks if a RISC-V instruction corresponds to stack push instructions + * like `addi sp, sp, imm` and `addiw sp, sp, imm`, and calculates the + * effective stack push size based on the immediate value. + * + * This function examines a 32-bit RISC-V instruction and checks if it corresponds + * to one of two stack adjustment operations: + * - `addi sp, sp, imm` (add immediate to the stack pointer) + * - `addiw sp, sp, imm` (add immediate to the stack pointer, with word extension). + * + * If the instruction matches one of these operations, it calculates the immediate + * value and adjusts the stack pointer accordingly. The size of the stack push + * is calculated based on the immediate value, and the function returns this + * value divided by the size of a `long` type. + * + * If the instruction does not correspond to one of the stack push operations, + * the function returns `-1`. + * + * @param inst The 32-bit RISC-V instruction to check. + * + * @return int Returns the stack push size in terms of the number of `long` units + * if the instruction corresponds to a valid stack push operation, + * otherwise returns `-1`. + * + * @note The instruction must modify the stack pointer (`sp`) to be considered valid. + * The immediate value is expected to be a signed 12-bit value and may represent + * a positive or negative offset to the stack pointer. + */ +int riscv_ins32_backtrace_stask_push(uint32_t inst) { + int ret = -1; + + if ((inst & 0x000FFFFF) == 0x10113) { + /* addi sp, sp, #imm */ + int immed = BITS(inst, 31, 20); + immed >>= 20; + immed &= 0xFFF; + if ((immed >> 11) != 0) { + immed = 0xFFF - immed + 1; + ret = immed / sizeof(long); + } else { + ret = -1; + } + } +#if !defined(CONFIG_ARCH_RISCV32) /* RISCV32 not support addiw sp, sp, #imm */ + else if ((inst & 0x000FFFFF) == 0x1011B) { + /* addiw sp, sp, #imm */ + int immed = BITS(inst, 31, 20); + immed >>= 20; + immed &= 0xFFF; + if ((immed >> 11) != 0) { + immed = 0xFFF - immed + 1; + ret = immed / sizeof(long); + } else { + ret = -1; + } + } +#endif + printk_trace("BT: inst:0x%x, ret = %d\n", inst, ret); + + return ret; +} + +/** + * @brief Processes compressed RISC-V instructions related to stack pointer adjustments. + * + * This function checks if a 16-bit compressed RISC-V instruction corresponds to one of the + * following stack pointer modification operations: + * - `c.addi16sp` (compressed `addi16sp` instruction, used for modifying the stack pointer with a 9-bit signed immediate) + * - `c.addi sp` (compressed `addi` instruction for modifying `sp` with a 6-bit immediate) + * - `c.addiw sp` (compressed `addiw` instruction for modifying `sp` with a 6-bit immediate) + * + * If the instruction matches one of these formats, it extracts the immediate value and calculates the + * corresponding adjustment to the stack pointer, returning the size of the adjustment in terms of `long` units. + * The function returns `-1` if the instruction doesn't correspond to any recognized format or if the immediate + * value does not result in a valid stack adjustment. + * + * @param inst The 16-bit compressed RISC-V instruction to be analyzed. + * + * @return int Returns the stack adjustment size (in terms of `long` units) if the instruction is valid, + * otherwise returns `-1`. + * + * @note + * - The function assumes that the instruction is valid and checks for stack pointer adjustments only. + * - For `c.addi16sp`, the immediate is a 9-bit signed value that modifies the stack pointer (`sp`). + * - For `c.addi sp, sp, imm` and `c.addiw sp, imm`, the immediate is a 6-bit signed value used to modify `sp`. + * - The function divides the immediate value by `sizeof(long)` to return the number of `long` units adjusted. + */ +static int riscv_ins16_backtrace_stask_push(uint32_t inst) { + int ret = -1; + + if ((inst & 0xEF83) == 0x6101) { + /* c.addi16sp #imm */ + int immed_4 = (inst >> 6) & 0x01; + int immed_5 = (inst >> 2) & 0x01; + int immed_6 = (inst >> 5) & 0x01; + int immed_7_8 = (inst >> 3) & 0x3; + int immed_9 = (inst >> 12) & 0x1; + int immed = (immed_4 << 4) | (immed_5 << 5) | (immed_6 << 6) | (immed_7_8 << 7) | (immed_9 << 9); + if ((immed >> 9) != 0) { + immed = 0x3FF - immed + 1; + ret = immed / sizeof(long); + } else { + ret = -1; + } + } else if ((inst & 0xEF03) == 0x101) { + /* c.addi sp, sp, #imm */ + int immed_5 = (inst >> 12) & 0x01; + int immed_0_4 = (inst >> 2) & 0x1F; + int immed = (immed_0_4) | (immed_5 << 5); + if ((immed >> 5) != 0) { + immed = 0x3F - immed + 1; + ret = immed / sizeof(long); + } else { + ret = -1; + } + } +#if !defined(CONFIG_ARCH_RISCV32) /* RISCV32 not support c.addiw sp */ + else if ((inst & 0xEF03) == 0x2101) { + /* c.addiw sp, #imm */ + int immed_5 = (inst >> 12) & 0x01; + int immed_0_4 = (inst >> 2) & 0x1F; + int immed = (immed_0_4) | (immed_5 << 5); + if ((immed >> 5) != 0) { + immed = 0x3F - immed + 1; + ret = immed / sizeof(long); + } else { + ret = -1; + } + } +#endif + + printk_trace("BT: inst:0x%x, ret = %d\n", inst, ret); + + return ret; +} + +/** + * @brief Perform a backtrace from the current stack pointer and program counter. + * + * This function walks the stack to retrieve the calling function's information + * by analyzing the return address (`LR`) and corresponding program counter (`PC`) values. + * It starts by looking for instructions that push the link register (`LR`) to the stack, + * then works backwards through the stack frames. The function handles both 16-bit and + * 32-bit instructions in RISC-V architecture. + * + * The function attempts to find the appropriate return address and adjusts the + * stack pointer (`SP`) accordingly. It then calculates the program counter (`PC`) + * from the link register (`LR`) by finding the corresponding offset. The function + * is responsible for determining whether the address information is valid and updates + * the `SP` and `PC` pointers. + * + * The function returns `1` if a valid backtrace is successfully performed, + * or `0` if the link register's offset is zero. If an error is encountered + * at any point, the function prints an error message and returns `-1`. + * + * @param pSP Pointer to the stack pointer (`SP`) to be updated. + * @param pPC Pointer to the program counter (`PC`) to be updated. + * + * @return int Returns: + * - `1` if a valid backtrace is successfully performed. + * - `0` if the link register's offset is zero. + * - `-1` in case of failure (e.g., invalid addresses or instructions). + * + * @note The backtrace relies on the presence of valid instruction addresses and + * will fail if the stack pointer or program counter point to invalid regions. + * The function also uses `insn_length()` to determine instruction lengths + * and adjusts the stack and program counter accordingly. + */ +static int riscv_backtrace_from_stack(long **pSP, char **pPC, char **pLR) { + char *parse_addr = NULL; + long *SP = *pSP; + char *PC = *pPC; + char *LR = *pLR; + int i, temp, framesize = 0, offset = 0, result = 0; + uint32_t ins32 = 0; + uint16_t ins16 = 0, ins16_h = 0, ins16_l = 0; + + for (i = 2; i < BT_SCAN_MAX_LIMIT; i += 2) { + int result = 0; + parse_addr = PC - i; + if (backtrace_check_address(parse_addr) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr); + return -1; + } + ins16_h = *(uint16_t *) parse_addr; + + if (backtrace_check_address(parse_addr - 2) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr - 2); + return -1; + } + ins16_l = *(uint16_t *) (parse_addr - 2); + + if (insn_length(ins16_l) == 4) { + printk_trace("BT: insn len == 4, parse_addr = %p:\n", parse_addr); + ins32 = (ins16_h << 16) | ins16_l; + result = riscv_ins32_get_push_lr_framesize(ins32, &offset); + i += 2; + } else { + printk_trace("BT: insn len == 2, parse_addr = %p:\n", parse_addr); + ins16 = ins16_h; + result = riscv_ins16_get_push_lr_framesize(ins16, &offset); + } + + if (result >= 0) { + break; + } + } + + parse_addr = PC - i; + + printk_trace("BT: i = %d, parse_addr = %p, PC = %p, offset = %d\n", i, parse_addr, PC, offset); + + if (i == BT_SCAN_MAX_LIMIT) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. scope overflow\n"); + return -1; + } + + for (i = 0; parse_addr + i < PC; i += 2) { + if (backtrace_check_address(parse_addr + i) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr + i); + return -1; + } + ins16_l = *(uint16_t *) (parse_addr + i); + + if (backtrace_check_address(parse_addr + i + 2) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr + i + 2); + return -1; + } + ins16_h = *(uint16_t *) (parse_addr + i + 2); + + if (insn_length(ins16_l) == 4 || ins16_l == 0) { + ins32 = (ins16_h << 16) | ins16_l; + temp = riscv_ins32_backtrace_stask_push(ins32); + i += 2; + } else { + ins16 = ins16_l; + temp = riscv_ins16_backtrace_stask_push(ins16); + } + if (temp >= 0) { + framesize += temp; + } + } + + printk_trace("BT: i = %d, framesize = %d, SP = %p\n", i, framesize, SP); + + if (!offset) { + return -1; + } + + if (backtrace_check_address(SP + offset) == 0) + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", SP + offset); + + LR = (char *) *(SP + offset); + if (backtrace_check_address(LR) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); + return -1; + } + *pSP = SP + framesize; + offset = riscv_backtrace_find_lr_offset(LR); + *pPC = LR - offset; + + printk_trace("BT: *pSP = %p, offset = %d, *pPC = %p\n", *pSP, offset, *pPC); + + return offset == 0 ? 1 : 0; +} + +/** + * @brief Performs a backtrace from the current stack frame. + * + * This function is used to trace the call stack, starting from the provided program counter + * and stack pointer. Before performing the backtrace, it checks if the program counter is + * valid (i.e., points to executable code). If the program counter is invalid, the function + * returns an error code (-1). Otherwise, it delegates the actual backtrace work to + * `riscv_backtrace_from_stack`. + * + * @param[in,out] pSP Pointer to the stack pointer. The stack pointer is updated with the + * result of the backtrace. + * @param[in,out] pPC Pointer to the program counter. The program counter is updated with + * the result of the backtrace. + * + * @return 0 if the backtrace is successful and the program counter is updated correctly, + * or -1 if an invalid program counter is provided or the backtrace fails. + */ +static int backtrace_from_stack(long **pSP, char **pPC, char **pLR) { + if (backtrace_check_address(*pPC) == 0) { + return -1; + } + + return riscv_backtrace_from_stack(pSP, pPC, pLR); +} + +/** + * @brief Handles the backtrace return pop for a 32-bit instruction. + * + * This function checks if the provided 32-bit instruction matches the return + * address instruction and returns the corresponding result. + * + * @param inst The 32-bit instruction to check. + * @return 0 if the instruction matches the return instruction, -1 otherwise. + */ +static int riscv_ins32_backtrace_return_pop(uint32_t inst) { + int ret = -1; /**< Default return value is -1, indicating no match. */ + + if ((inst) == 0x00008067) { /**< Check if instruction matches return instruction. */ + ret = 0; /**< Set return value to 0 if it matches. */ + } + + printk_trace("BT: inst:0x%x, ret = %d\n", inst, ret); /**< Log the instruction and return value. */ + return ret; /**< Return the result. */ +} + +/** + * @brief Handles the backtrace return pop for a 16-bit instruction. + * + * This function checks if the provided 16-bit instruction matches the return + * address instruction and returns the corresponding result. + * + * @param inst The 16-bit instruction to check. + * @return 0 if the instruction matches the return instruction, -1 otherwise. + */ +static int riscv_ins16_backtrace_return_pop(uint16_t inst) { + int ret = -1; /**< Default return value is -1, indicating no match. */ + + if ((inst) == 0x8082) { /**< Check if instruction matches return instruction. */ + ret = 0; /**< Set return value to 0 if it matches. */ + } + + printk_trace("BT: inst:0x%x, ret = %d\n", inst, ret); /**< Log the instruction and return value. */ + return ret; /**< Return the result. */ +} + +/** + * @brief Handles the backtrace stack pop for a 32-bit instruction. + * + * This function checks if the instruction is a stack pointer adjustment (addi or addiw) + * and computes the corresponding stack adjustment. It handles both immediate values + * and calculates the stack width. + * + * @param inst The 32-bit instruction to check. + * @return The computed stack pop value, or -1 if no match is found. + */ +static int riscv_ins32_backtrace_stack_pop(unsigned int inst) { + int ret = -1; /**< Default return value is -1, indicating no match. */ + int stack_width = sizeof(long); /**< Define stack width based on long data type size. */ + + /* Check for "addi sp, sp, #imm" instruction. */ + if ((inst & 0x000FFFFF) == 0x10113) { + int immed = BITS(inst, 31, 20); /**< Extract immediate value from instruction. */ + immed >>= 20; /**< Shift to get the immediate. */ + immed &= 0xFFF; /**< Mask to get 12-bit immediate. */ + if ((immed >> 11) != 0) { + ret = -1; /**< Invalid immediate, return -1. */ + } else { + immed = 0xFFF - immed + 1; /**< Calculate adjusted immediate. */ + ret = immed / stack_width; /**< Convert to stack adjustment. */ + } + printk_trace("BT: \t addi sp, sp, #immed=%d \n", immed); /**< Log instruction and immediate value. */ + } +#if !defined(CONFIG_ARCH_RISCV32) /* RISCV32 does not support "addiw sp, sp, #imm" instruction */ + else if ((inst & 0x000FFFFF) == 0x1011B) { + /* Check for "addiw sp, sp, #imm" instruction. */ + int immed = BITS(inst, 31, 20); /**< Extract immediate value from instruction. */ + immed >>= 20; /**< Shift to get the immediate. */ + immed &= 0xFFF; /**< Mask to get 12-bit immediate. */ + if ((immed >> 11) != 0) { + ret = -1; /**< Invalid immediate, return -1. */ + } else { + immed = 0xFFF - immed + 1; /**< Calculate adjusted immediate. */ + ret = immed / stack_width; /**< Convert to stack adjustment. */ + } + printk_trace("BT: \t addiw sp, sp, #immed=%d \n", immed); /**< Log instruction and immediate value. */ + } +#endif + + printk_trace("BT: inst:0x%x, ret:%d\n", inst, ret); /**< Log instruction and return value. */ + return ret; /**< Return the result. */ +} + +/** + * @brief Handles the backtrace stack pop for a 16-bit instruction. + * + * This function checks if the provided 16-bit instruction is a stack pointer + * adjustment (either `c.addi16sp`, `c.addi sp`, or `c.addiw sp`) and computes + * the corresponding stack adjustment. + * + * @param inst The 16-bit instruction to check. + * @return The computed stack pop value, or -1 if no valid stack pop is found. + */ +static int riscv_ins16_backtrace_stack_pop(uint16_t inst) { + int ret = -1; /**< Default return value is -1, indicating no match. */ + int stack_width = sizeof(long); /**< Define stack width based on long data type size. */ + + /* Check for "c.addi16sp #imm" instruction. */ + if ((inst & 0xEF83) == 0x6101) { + int immed_4 = (inst >> 6) & 0x01; /**< Extract bit 6 for immediate part. */ + int immed_5 = (inst >> 2) & 0x01; /**< Extract bit 2 for immediate part. */ + int immed_6 = (inst >> 5) & 0x01; /**< Extract bit 5 for immediate part. */ + int immed_7_8 = (inst >> 3) & 0x3; /**< Extract bits 3-4 for immediate part. */ + int immed_9 = (inst >> 12) & 0x1; /**< Extract bit 12 for immediate part. */ + int immed = (immed_4 << 4) | (immed_5 << 5) | (immed_6 << 6) | (immed_7_8 << 7) | (immed_9 << 9); /**< Combine extracted bits into a full immediate value. */ + + if ((immed >> 9) != 0) { /**< If the immediate value is too large, adjust it. */ + immed = 0x3FF - immed + 1; /**< Adjust the immediate for negative values. */ + } + + printk_trace("BT: \tc.addi16sp #immed=%d \n", immed); /**< Log the immediate value. */ + ret = immed / stack_width; /**< Calculate the stack pop based on the immediate value. */ + } + /* Check for "c.addi sp, sp, #imm" instruction. */ + else if ((inst & 0xEF03) == 0x101) { + int immed_5 = (inst >> 12) & 0x01; /**< Extract bit 12 for immediate part. */ + int immed_0_4 = (inst >> 2) & 0x1F; /**< Extract bits 2-6 for immediate part. */ + int immed = (immed_0_4) | (immed_5 << 5); /**< Combine bits to form immediate value. */ + + if ((immed >> 5) != 0) { /**< Check if immediate value is too large. */ + ret = -1; /**< Return error if the immediate is invalid. */ + } else { + immed = 0x3F - immed + 1; /**< Adjust the immediate value for negative values. */ + } + + printk_trace("BT: \tc.addi sp, sp, #immed=%d \n", immed); /**< Log the immediate value. */ + ret = immed / stack_width; /**< Calculate the stack pop based on the immediate value. */ + } +#if !defined(CONFIG_ARCH_RISCV32) /* RISCV32 does not support "c.addiw sp, #imm" instruction */ + /* Check for "c.addiw sp, #imm" instruction. */ + else if ((inst & 0xEF03) == 0x2101) { + int immed_5 = (inst >> 12) & 0x01; /**< Extract bit 12 for immediate part. */ + int immed_0_4 = (inst >> 2) & 0x1F; /**< Extract bits 2-6 for immediate part. */ + int immed = (immed_0_4) | (immed_5 << 5); /**< Combine bits to form immediate value. */ + + if ((immed >> 5) != 0) { /**< Check if immediate value is too large. */ + ret = -1; /**< Return error if the immediate is invalid. */ + } else { + immed = 0x3F - immed + 1; /**< Adjust the immediate value for negative values. */ + } + + printk_trace("BT: \tc.addiw sp, #immed=%d \n", immed); /**< Log the immediate value. */ + ret = immed / stack_width; /**< Calculate the stack pop based on the immediate value. */ + } +#endif + + printk_trace("BT: inst:0x%x\n", inst); /**< Log the instruction. */ + return ret; /**< Return the result. */ +} + +/** + * @brief Reconstructs a backtrace using the link register (LR) and program counter (PC). + * + * This function inspects the instructions at the current PC and LR, computes the stack + * frames, and updates the SP and PC accordingly. It tries to decode 16-bit and 32-bit + * instructions and handles different instruction formats for backtrace purposes. + * + * @param pSP Pointer to the stack pointer to be updated. + * @param pPC Pointer to the program counter to be updated. + * @param LR Link register (return address) to start the backtrace from. + * + * @return 1 if successful, 0 if the link register offset is zero, -1 on failure. + */ +static int riscv_backtrace_from_lr(long **pSP, char **pPC, char *LR) { + long *SP = *pSP; /**< Local stack pointer. */ + char *PC = *pPC; /**< Local program counter. */ + char *parse_addr = NULL; /**< Temporary address for instruction parsing. */ + int i, temp, framesize = 0, offset = 0, result = 0; /**< Loop counters, temporary values, and result variables. */ + uint32_t ins32 = 0; /**< 32-bit instruction. */ + uint16_t ins16 = 0, ins16_h = 0, ins16_l = 0; /**< 16-bit instruction (low and high). */ + + /* Check if the current program counter is valid. */ + if (backtrace_check_address(PC) == 0) { + /* Check if the link register (LR) is valid. */ + if (backtrace_check_address(LR) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); /**< Log invalid LR. */ + return -1; + } + offset = riscv_backtrace_find_lr_offset(LR); /**< Find the LR offset. */ + PC = LR - offset; /**< Update PC based on LR offset. */ + *pPC = PC; /**< Set the new program counter. */ + return offset == 0 ? 1 : 0; /**< Return success if offset is 0, otherwise return 0. */ + } + + /* Scan the instructions at the current PC for backtrace. */ + for (i = 0; i < BT_SCAN_MAX_LIMIT; i += 2) { + parse_addr = PC + i; /**< Calculate the address for parsing instructions. */ + + /* Check if the current address is valid. */ + if (backtrace_check_address(parse_addr) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr); /**< Log failure. */ + return -1; + } + + /* Check the next address for a valid instruction. */ + if (backtrace_check_address(parse_addr + 2) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr + 2); /**< Log failure. */ + return -1; + } + + ins16_l = *(uint16_t *) parse_addr; /**< Fetch the low 16-bit instruction. */ + ins16_h = *(uint16_t *) (parse_addr + 2); /**< Fetch the high 16-bit instruction. */ + + /* Check if the instruction length is 4 bytes or invalid, then combine into 32-bit. */ + if (insn_length(ins16_l) == 4 || ins16_l == 0) { + ins32 = (ins16_h << 16) | ins16_l; /**< Combine high and low 16-bits into a 32-bit instruction. */ + result = riscv_ins32_backtrace_return_pop(ins32); /**< Check if it's a return pop for 32-bit instruction. */ + i += 2; /**< Adjust the loop index for 32-bit instruction. */ + parse_addr -= 4; /**< Move back by 4 bytes for 32-bit instruction. */ + } else { + ins16 = ins16_l; /**< Use the 16-bit instruction if it's valid. */ + result = riscv_ins16_backtrace_return_pop(ins16); /**< Check if it's a return pop for 16-bit instruction. */ + parse_addr -= 2; /**< Move back by 2 bytes for 16-bit instruction. */ + } + + /* If the result is valid, exit the loop. */ + if (result >= 0) { + break; + } + } + + printk_trace("BT: i = %d, parse_addr = %p, PC = %p, framesize = %d\n", i, parse_addr, PC, framesize); /**< Log backtrace progress. */ + + framesize = result; /**< Set the frame size from the result. */ + + /* If the scan limit is reached, report overflow error. */ + if (i == BT_SCAN_MAX_LIMIT) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. scope overflow\n"); /**< Log error on overflow. */ + return -1; + } + + /* Process the stack frames by checking the stack instructions. */ + for (i = 0; parse_addr - i >= PC; i += 2) { + /* Validate the address before processing the instruction. */ + if (backtrace_check_address(parse_addr - i) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr - i); /**< Log failed address. */ + return -1; + } + + /* Check the previous 2-byte instruction for validity. */ + if (backtrace_check_address(parse_addr - i - 2) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: failed. addr 0x%08x\n", parse_addr - i - 2); /**< Log failed address. */ + return -1; + } + + ins16_l = *(uint16_t *) (parse_addr - i - 2); /**< Fetch the low 16-bit instruction. */ + ins16_h = *(uint16_t *) (parse_addr - i); /**< Fetch the high 16-bit instruction. */ + + /* If the instruction is 4 bytes, process as 32-bit instruction. */ + if (insn_length(ins16_l) == 4) { + ins32 = (ins16_h << 16) | ins16_l; /**< Combine into a 32-bit instruction. */ + temp = riscv_ins32_backtrace_stack_pop(ins32); /**< Process stack pop for 32-bit instruction. */ + i += 2; /**< Adjust the loop counter for 32-bit instruction. */ + } else { + ins16 = ins16_h; /**< Use the high 16-bit instruction for 16-bit processing. */ + temp = riscv_ins16_backtrace_stack_pop(ins16); /**< Process stack pop for 16-bit instruction. */ + } + + /* If stack pop is valid, add the frame size. */ + if (temp >= 0) { + printk_trace("BT: framesize add %d\n", temp); /**< Log the frame size addition. */ + framesize += temp; /**< Add to the total frame size. */ + } + } + + printk_trace("BT: i = %d, parse_addr = %p, PC = %p, SP = %p, framesize = %d\n", i, parse_addr, PC, SP, framesize); /**< Log final backtrace details. */ + + /* Check if the LR is valid again before updating SP and PC. */ + if (backtrace_check_address(LR) == 0) { + printk(LOG_LEVEL_BACKTRACE, "backtrace: invalid lr 0x%08x\n", LR); /**< Log invalid LR. */ + return -1; + } + *pSP = SP + framesize; /**< Update stack pointer with the computed frame size. */ + offset = riscv_backtrace_find_lr_offset(LR); /**< Find the LR offset again. */ + *pPC = LR - offset; /**< Update program counter based on the LR and offset. */ + + printk_trace("BT: *pSP = %p, offset = %d, *pPC = %p\n", *pSP, offset, *pPC); /**< Log the updated SP and PC. */ + + return offset == 0 ? 1 : 0; /**< Return success if offset is 0, otherwise return 0. */ +} + +/** + * @brief Perform a backtrace from the given program counter (PC), stack pointer (SP), and link register (LR). + * + * This function tries to traverse the stack to generate a backtrace, logging the current PC at each level. + * If the stack backtrace fails, it attempts to trace using the LR as a fallback. + * + * @param PC Pointer to the program counter. + * @param SP Pointer to the stack pointer. + * @param LR Pointer to the link register (return address). + * + * @return The number of backtrace levels found, or 0 if the backtrace failed. + */ +int backtrace(char *PC, long *SP, char *LR) { + int level = 0;///< Backtrace level counter + int ret; ///< Return value for backtrace_from_stack + + char *_PC = PC;///< Program counter (PC) + long *_SP = SP;///< Stack pointer (SP) + char *_LR = LR;///< Link register (LR) + + // Log the current program counter (PC) + printk(LOG_LEVEL_BACKTRACE, "backtrace: 0x%08x\n", PC); + + // Traverse the stack and perform backtrace + for (level = 1; level < BT_LEVEL_LIMIT; level++) { + ret = backtrace_from_stack(&SP, &PC, &LR);///< Get the next backtrace level + if (ret != 0) { + break;///< Stop if backtrace fails + } + } + + /* If stack backtrace fails, try to trace using the link register (LR) */ + if (level == 1) { + ret = riscv_backtrace_from_lr(&_SP, &_PC, _LR);///< Try backtrace from LR + if (ret == 0) { + for (; level < BT_LEVEL_LIMIT; level++) { + ret = backtrace_from_stack(&SP, &PC, &LR);///< Continue stack backtrace if LR tracing succeeds + if (ret != 0) { + break; + } + } + } + } + + // Return the backtrace level, ensuring it's at least 0 + return level > 0 ? level : 0;///< Return the number of backtrace levels found +} + +/** + * @brief Dumps the current stack trace by fetching the program counter (PC), stack pointer (SP), and link register (LR). + * + * This function retrieves the current values of the stack pointer, program counter, and link register, + * then uses these to generate a backtrace. If either the stack pointer or program counter is invalid, it returns 0. + * + * @return The backtrace level, or 0 if SP or PC is invalid. + */ +int dump_stack(void) { + char *PC = NULL;///< Program counter (PC) + long *SP = NULL;///< Stack pointer (SP) + char *LR = NULL;///< Link register (LR) + + // Get the current stack pointer (SP) + asm volatile("mv %0, sp\n" + : "=r"(SP)); + + // Get the current program counter (PC) + asm volatile("auipc %0, 0\n" + : "=r"(PC)); + + // Get the return address (LR) + asm volatile("mv %0, ra\n" + : "=r"(LR)); + + // Check if stack pointer or program counter is invalid + if (SP == NULL || PC == NULL) { + return 0;///< Return 0 if SP or PC is invalid + } + + // Return the backtrace level, ensuring it's at least 0 + return backtrace(PC, SP, LR);///< Call backtrace function and return the result +} diff --git a/src/arch/riscv/riscv32_e907/exception.c b/src/arch/riscv/riscv32_e907/exception.c index ea4a1fc29..659b78b1a 100644 --- a/src/arch/riscv/riscv32_e907/exception.c +++ b/src/arch/riscv/riscv32_e907/exception.c @@ -1,8 +1,9 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include #include @@ -273,6 +274,9 @@ static void show_regs(struct pt_regs_t *regs) { printk_error("Bad address: 0x%08x\r\n", regs->badvaddr); printk_error("Stored ra: 0x%08x\r\n", regs->x[1]); printk_error("Stored sp: 0x%08x\r\n", regs->x[2]); + printk_error("========== backtrace ==========\n"); + dump_stack(); + backtrace((char *)regs->epc, (long *)regs->x[2], (char *)regs->x[1]); } static struct instruction_info_t *match_instruction(unsigned long insn) { diff --git a/src/arch/riscv/riscv32_e907/memcmp.c b/src/arch/riscv/riscv32_e907/memcmp.c index 9dda01412..210c9352a 100644 --- a/src/arch/riscv/riscv32_e907/memcmp.c +++ b/src/arch/riscv/riscv32_e907/memcmp.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/arch/riscv/riscv32_e907/memcpy.S b/src/arch/riscv/riscv32_e907/memcpy.S index 7d045ee49..c220a40dd 100644 --- a/src/arch/riscv/riscv32_e907/memcpy.S +++ b/src/arch/riscv/riscv32_e907/memcpy.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/src/arch/riscv/riscv32_e907/memset.S b/src/arch/riscv/riscv32_e907/memset.S index 8660c60f7..e47a686dc 100644 --- a/src/arch/riscv/riscv32_e907/memset.S +++ b/src/arch/riscv/riscv32_e907/memset.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/src/arch/riscv/riscv32_e907/timer.c b/src/arch/riscv/riscv32_e907/timer.c index 5979a2189..f2bb8062b 100644 --- a/src/arch/riscv/riscv32_e907/timer.c +++ b/src/arch/riscv/riscv32_e907/timer.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -22,13 +22,18 @@ uint32_t current_hosc_freq = 24; /**< Current frequency of the high-speed osc * * @return Current HOSC frequency in MHz (either 24 or 40). */ + static int sunxi_hosc_detect(void) { - uint32_t counter_val = 0; - writel(HOSC_FREQ_DET_HOSC_ENABLE_DETECT, CCU_HOSC_FREQ_DET_REG); + uint32_t val = readl(CCU_HOSC_FREQ_DET_REG); + + writel(val & (~HOSC_FREQ_DET_HOSC_CLEAR_MASK), CCU_HOSC_FREQ_DET_REG); + writel(val | HOSC_FREQ_DET_HOSC_ENABLE_DETECT, CCU_HOSC_FREQ_DET_REG); + while (!(HOSC_FREQ_DET_HOSC_FREQ_READY_CLEAR_MASK & readl(CCU_HOSC_FREQ_DET_REG))) ; - counter_val = (readl(CCU_HOSC_FREQ_DET_REG) & HOSC_FREQ_DET_HOSC_FREQ_DET_CLEAR_MASK) >> HOSC_FREQ_DET_HOSC_FREQ_DET_OFFSET; - if (counter_val < ((HOSC_24M_COUNTER + HOSC_40M_COUNTER) / 2)) { + + val = (readl(CCU_HOSC_FREQ_DET_REG) & HOSC_FREQ_DET_HOSC_FREQ_DET_CLEAR_MASK) >> HOSC_FREQ_DET_HOSC_FREQ_DET_OFFSET; + if (val < ((HOSC_24M_COUNTER + HOSC_40M_COUNTER) / 2)) { current_hosc_freq = HOSC_FREQ_24M; return HOSC_FREQ_24M; } else { diff --git a/src/arch/riscv/riscv64_ae350/CMakeLists.txt b/src/arch/riscv/riscv64_ae350/CMakeLists.txt deleted file mode 100644 index b19eb5892..000000000 --- a/src/arch/riscv/riscv64_ae350/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_library(arch-obj OBJECT - timer.c - exception.c - memcpy.S - memset.S - fprw.S - memcmp.c -) \ No newline at end of file diff --git a/src/arch/riscv/riscv64_ae350/exception.c b/src/arch/riscv/riscv64_ae350/exception.c deleted file mode 100644 index ba821e9d2..000000000 --- a/src/arch/riscv/riscv64_ae350/exception.c +++ /dev/null @@ -1,472 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include - -#if defined(__riscv_flen) -#if __riscv_flen >= 32 -extern void f32_read(int n, uint32_t *v); -extern void f32_write(int n, uint32_t *v); -#endif -#if __riscv_flen >= 64 -extern void f64_read(int n, uint64_t *v); -extern void f64_write(int n, uint64_t *v); -#endif -#endif - -#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which) -1))) -#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which) -1)))) - -#ifndef STRINGIFY -#define _STRINGIFY(x) #x -#define STRINGIFY(x) _STRINGIFY(x) -#endif - -#define DEFINE_MPRV_READ_FLAGS(name, type, insn, flags) \ - static inline type name(type *p) { \ - size_t mprv = flags; \ - type value; \ - __asm__ __volatile__( \ - "csrs mstatus, %1\n" STRINGIFY(insn) " %0, 0(%2)\n" \ - "csrc mstatus, %1\n" \ - : "=&r"(value) \ - : "r"(mprv), "r"(p) \ - : "memory"); \ - return value; \ - } - -#define DEFINE_MPRV_READ(name, type, insn) \ - DEFINE_MPRV_READ_FLAGS(name, type, insn, 0x00020000) - -#define DEFINE_MPRV_READ_MXR(name, type, insn) \ - DEFINE_MPRV_READ_FLAGS(name, type, insn, 0x00020000 | 0x00080000) - -#define DEFINE_MPRV_WRITE(name, type, insn) \ - static inline void name(type *p, type value) { \ - size_t mprv = 0x00020000; \ - __asm__ __volatile__( \ - "csrs mstatus, %0\n" STRINGIFY(insn) " %1, 0(%2)\n" \ - "csrc mstatus, %0\n" ::"r"(mprv), \ - "r"(value), "r"(p) \ - : "memory"); \ - } - -DEFINE_MPRV_READ(mprv_read_u8, uint8_t, lbu) -DEFINE_MPRV_READ(mprv_read_u16, uint16_t, lhu) -DEFINE_MPRV_READ(mprv_read_u32, uint32_t, lwu) -DEFINE_MPRV_READ(mprv_read_u64, uint64_t, ld) -DEFINE_MPRV_READ(mprv_read_long, long, ld) -DEFINE_MPRV_READ(mprv_read_ulong, unsigned long, ld) -DEFINE_MPRV_READ_MXR(mprv_read_mxr_u8, uint8_t, lbu) -DEFINE_MPRV_READ_MXR(mprv_read_mxr_u16, uint16_t, lhu) -DEFINE_MPRV_READ_MXR(mprv_read_mxr_u32, uint32_t, lwu) -DEFINE_MPRV_READ_MXR(mprv_read_mxr_u64, uint64_t, ld) -DEFINE_MPRV_READ_MXR(mprv_read_mxr_long, long, ld) -DEFINE_MPRV_READ_MXR(mprv_read_mxr_ulong, unsigned long, ld) -DEFINE_MPRV_WRITE(mprv_write_u8, uint8_t, sb) -DEFINE_MPRV_WRITE(mprv_write_u16, uint16_t, sh) -DEFINE_MPRV_WRITE(mprv_write_u32, uint32_t, sw) -DEFINE_MPRV_WRITE(mprv_write_u64, uint64_t, sd) -DEFINE_MPRV_WRITE(mprv_write_long, long, sd) -DEFINE_MPRV_WRITE(mprv_write_ulong, unsigned long, sd) - -struct pt_regs_t { - unsigned long x[32]; - unsigned long status; - unsigned long epc; - unsigned long badvaddr; - unsigned long cause; - unsigned long insn; -}; - -struct insn_fetch_t { - unsigned long error; - uint32_t insn; -}; - -union endian_buf_t { - uint8_t b[8]; - uint16_t h[4]; - uint32_t w[2]; - uint64_t d[1]; - unsigned long v; -}; - -struct instruction_info_t { - uint32_t opcode; - uint32_t mask; - unsigned int reg_shift; - unsigned int reg_mask; - unsigned int reg_addition; - unsigned int is_fp : 1; - unsigned int is_load : 1; - unsigned int width : 8; - unsigned int sign_extend : 1; -}; - -/** - * @brief Structure for IRQ handler - * - * @param data Pointer to data associated with the IRQ handler - * @param func Function pointer to the IRQ handler function - */ -typedef struct _irq_handler { - void *data; - void (*func)(void *data); -} irq_handler_t; - -static irq_handler_t core_interrupt_handler[8] = {0}; - -static struct instruction_info_t insn_info[] = { -#if __riscv_xlen == 128 - {0x00002000, 0x0000e003, 2, 7, 8, 0, 1, 16, 1}, /* C.LQ */ -#else - {0x00002000, 0x0000e003, 2, 7, 8, 1, 1, 8, 0}, /* C.FLD */ -#endif - {0x00004000, 0x0000e003, 2, 7, 8, 0, 1, 4, 1}, /* C.LW */ -#if __riscv_xlen == 32 - {0x00006000, 0x0000e003, 2, 7, 8, 1, 1, 4, 0}, /* C.FLW */ -#else - {0x00006000, 0x0000e003, 2, 7, 8, 0, 1, 8, 1}, /* C.LD */ -#endif - -#if __riscv_xlen == 128 - {0x0000a000, 0x0000e003, 2, 7, 8, 0, 0, 16, 0}, /* C.SQ */ -#else - {0x0000a000, 0x0000e003, 2, 7, 8, 1, 0, 8, 0}, /* C.FSD */ -#endif - {0x0000c000, 0x0000e003, 2, 7, 8, 0, 0, 4, 0}, /* C.SW */ -#if __riscv_xlen == 32 - {0x0000e000, 0x0000e003, 2, 7, 8, 1, 0, 4, 0}, /* C.FSW */ -#else - {0x0000e000, 0x0000e003, 2, 7, 8, 0, 0, 8, 0}, /* C.SD */ -#endif - -#if __riscv_xlen == 128 - {0x00002002, 0x0000e003, 7, 15, 0, 0, 1, 16, 1}, /* C.LQSP */ -#else - {0x00002002, 0x0000e003, 7, 15, 0, 1, 1, 8, 0}, /* C.FLDSP */ -#endif - {0x00004002, 0x0000e003, 7, 15, 0, 0, 1, 4, 1}, /* C.LWSP */ -#if __riscv_xlen == 32 - {0x00006002, 0x0000e003, 7, 15, 0, 1, 1, 4, 0}, /* C.FLWSP */ -#else - {0x00006002, 0x0000e003, 7, 15, 0, 0, 1, 8, 1}, /* C.LDSP */ -#endif - -#if __riscv_xlen == 128 - {0x0000a002, 0x0000e003, 2, 15, 0, 0, 0, 16, 0}, /* C.SQSP */ -#else - {0x0000a002, 0x0000e003, 2, 15, 0, 1, 0, 8, 0}, /* C.FSDSP */ -#endif - {0x0000c002, 0x0000e003, 2, 15, 0, 0, 0, 4, 0}, /* C.SWSP */ -#if __riscv_xlen == 32 - {0x0000e002, 0x0000e003, 2, 15, 0, 1, 0, 4, 0}, /* C.FSWSP */ -#else - {0x0000e002, 0x0000e003, 2, 15, 0, 0, 0, 8, 0}, /* C.SDSP */ -#endif - - {0x00000003, 0x0000707f, 7, 15, 0, 0, 1, 1, 1}, /* LB */ - {0x00001003, 0x0000707f, 7, 15, 0, 0, 1, 2, 1}, /* LH */ - {0x00002003, 0x0000707f, 7, 15, 0, 0, 1, 4, 1}, /* LW */ -#if __riscv_xlen > 32 - {0x00003003, 0x0000707f, 7, 15, 0, 0, 1, 8, 1}, /* LD */ -#endif - {0x00004003, 0x0000707f, 7, 15, 0, 0, 1, 1, 0}, /* LBU */ - {0x00005003, 0x0000707f, 7, 15, 0, 0, 1, 2, 0}, /* LHU */ - {0x00006003, 0x0000707f, 7, 15, 0, 0, 1, 4, 0}, /* LWU */ - - {0x00000023, 0x0000707f, 20, 15, 0, 0, 0, 1, 0}, /* SB */ - {0x00001023, 0x0000707f, 20, 15, 0, 0, 0, 2, 0}, /* SH */ - {0x00002023, 0x0000707f, 20, 15, 0, 0, 0, 4, 0}, /* SW */ -#if __riscv_xlen > 32 - {0x00003023, 0x0000707f, 20, 15, 0, 0, 0, 8, 0}, /* SD */ -#endif - -#if defined(__riscv_flen) -#if __riscv_flen >= 32 - {0x00002007, 0x0000707f, 7, 15, 0, 1, 1, 4, 0}, /* FLW */ - {0x00003007, 0x0000707f, 7, 15, 0, 1, 1, 8, 0}, /* FLD */ -#endif - -#if __riscv_flen >= 64 - {0x00002027, 0x0000707f, 20, 15, 0, 1, 0, 4, 0}, /* FSW */ - {0x00003027, 0x0000707f, 20, 15, 0, 1, 0, 8, 0}, /* FSD */ -#endif -#endif -}; - -static const char *interrupt_names[] = { - "User software interrupt", - "Supervisor software interrupt", - "Hypervisor software interrupt", - "Machine software interrupt", - "User timer interrupt", - "Supervisor timer interrupt", - "Hypervisor timer interrupt", - "Machine timer interrupt", - "User external interrupt", - "Supervisor external interrupt", - "Hypervisor external interrupt", - "Machine external interrupt", -}; - -static const char *exception_names[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store address misaligned", - "Store access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "Reserved (10)", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "Reserved (14)", - "Store page fault", -}; - -static const char *mstatus_to_previous_mode(unsigned long ms) { - switch ((ms >> 11) & 0x3) { - case 0x0: - return "User"; - case 0x1: - return "Supervisor"; - case 0x2: - return "Hypervisor"; - case 0x3: - return "Machine"; - default: - break; - } - return "unknown"; -} - -static void show_regs(struct pt_regs_t *regs) { - if (regs->cause & (1UL << 63)) { - if ((regs->cause & ~(1UL << 63)) < ARRAY_SIZE(interrupt_names)) - printk_error("Interrupt: %s\r\n", interrupt_names[regs->cause & ~(1UL << 63)]); - else - printk_error("Trap: Unknown cause %p\r\n", (void *) regs->cause); - } else { - if (regs->cause < ARRAY_SIZE(exception_names)) - printk_error("Exception: %s\r\n", exception_names[regs->cause]); - else - printk_error("Trap: Unknown cause %p\r\n", (void *) regs->cause); - } - printk_error("Previous mode: %s%s\r\n", mstatus_to_previous_mode(csr_read(mstatus)), (regs->status & (1 << 17)) ? " (MPRV)" : ""); - printk_error("Bad instruction pc: %p\r\n", (void *) regs->epc); - printk_error("Bad address: %p\r\n", (void *) regs->badvaddr); - printk_error("Stored ra: %p\r\n", (void *) regs->x[1]); - printk_error("Stored sp: %p\r\n", (void *) regs->x[2]); -} - -static struct instruction_info_t *match_instruction(unsigned long insn) { - int i; - for (i = 0; i < ARRAY_SIZE(insn_info); i++) - if ((insn_info[i].mask & insn) == insn_info[i].opcode) - return &(insn_info[i]); - return NULL; -} - -static int fetch_16bit_instruction(unsigned long vaddr, unsigned long *insn) { - uint16_t ins = mprv_read_mxr_u16((uint16_t *) vaddr); - if (EXTRACT_FIELD(ins, 0x3) != 3) { - *insn = ins; - return 0; - } - return -1; -} - -static int fetch_32bit_instruction(unsigned long vaddr, unsigned long *insn) { - uint32_t l = (uint32_t) mprv_read_mxr_u16((uint16_t *) vaddr + 0); - uint32_t h = (uint32_t) mprv_read_mxr_u16((uint16_t *) vaddr + 2); - uint32_t ins = (h << 16) | l; - if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) { - *insn = ins; - return 0; - } - return -1; -} - -static void redirect_trap(void) { - csr_write(sbadaddr, csr_read(mbadaddr)); - csr_write(sepc, csr_read(mepc)); - csr_write(scause, csr_read(mcause)); - csr_write(mepc, csr_read(stvec)); - - unsigned long status = csr_read(mstatus); - unsigned long mpp = EXTRACT_FIELD(status, 0x00001800); - status = INSERT_FIELD(status, 0x00001800, 1); - status = INSERT_FIELD(status, 0x00000100, mpp & 1); - csr_write(mstatus, status); -} - -static void handle_misaligned(struct pt_regs_t *regs) { - struct instruction_info_t *match; - unsigned long insn = 0; - union endian_buf_t buff; - uint8_t *addr; - int done, n; - - /* Try to fetch 16 / 32 bits instruction */ - if (fetch_16bit_instruction(regs->epc, &insn)) { - if (fetch_32bit_instruction(regs->epc, &insn)) - redirect_trap(); - } - - /* Matching instruction */ - match = match_instruction(insn); - if (!match) { - redirect_trap(); - return; - } - - n = ((insn >> match->reg_shift) & match->reg_mask); - n = n + match->reg_addition; - buff.v = 0; - if (match->is_load) { - /* Load operation */ - /* Reading from memory by bytes prevents misaligned memory access */ - for (int i = 0; i < match->width; i++) { - uint8_t *addr = (uint8_t *) (regs->badvaddr + i); - buff.b[i] = mprv_read_u8(addr); - } - - /* Sign extend for signed integer loading */ - if (match->sign_extend) { - if (buff.v >> (8 * match->width - 1)) - buff.v |= -1 << (8 * match->width); - } - - /* Write to register */ - if (match->is_fp) { - int done = 0; -#if defined(__riscv_flen) -#if __riscv_flen >= 32 - /* Single-precision floating-point */ - if (match->width == 4) { - f32_write(n, buff.w); - done = 1; - } -#endif -#if __riscv_flen >= 64 - /* Double-precision floating-point */ - if (match->width == 8) { - f64_write(n, buff.d); - done = 1; - } -#endif -#endif - if (!done) - redirect_trap(); - } else { - regs->x[n] = buff.v; - } - } else { - /* Store operation */ - /* Reading from register */ - if (match->is_fp) { - done = 0; -#if defined(__riscv_flen) -#if __riscv_flen >= 32 - if (match->width == 4) { - f32_read(n, buff.w); - done = 1; - } -#endif -#if __riscv_flen >= 64 - if (match->width == 8) { - f64_read(n, buff.d); - done = 1; - } -#endif -#endif - if (!done) - redirect_trap(); - } else { - buff.v = regs->x[n]; - } - - /* Writing to memory by bytes prevents misaligned memory access */ - for (int i = 0; i < match->width; i++) { - addr = (uint8_t *) (regs->badvaddr + i); - mprv_write_u8(addr, buff.b[i]); - } - } -} - -void riscv64_handle_exception(struct pt_regs_t *regs) { - csr_write(mscratch, regs); - if (regs->cause & (1UL << 63)) { - unsigned long cause = regs->cause & ~(1UL << 63); - unsigned long pending = csr_read(mip) & (1 << cause); - switch (cause) { - case 0: /* User software interrupt */ - case 1: /* Supervisor software interrupt */ - case 2: /* Hypervisor software interrupt */ - case 3: /* Machine software interrupt */ - case 4: /* User timer interrupt */ - case 5: /* Supervisor timer interrupt */ - case 6: /* Hypervisor timer interrupt */ - case 7: /* Machine timer interrupt */ - csr_clear(mip, pending); - (core_interrupt_handler[cause].func)(core_interrupt_handler[cause].data); - break; - case 8: /* User external interrupt */ - case 9: /* Supervisor external interrupt */ - case 10: /* Hypervisor external interrupt */ - case 11: /* Machine external interrupt */ - csr_clear(mip, pending); - break; - default: - show_regs(regs); - break; - } - } else { - switch (regs->cause) { - case 0x0: /* Misaligned fetch */ - case 0x1: /* Fetch access */ - case 0x2: /* Illegal instruction */ - case 0x3: /* Breakpoint */ - show_regs(regs); - break; - case 0x4: /* Misaligned load */ - handle_misaligned(regs); - break; - case 0x5: /* Load acces */ - show_regs(regs); - break; - case 0x6: /* Misaligned store */ - handle_misaligned(regs); - break; - case 0x7: /* Store accesss */ - case 0x8: /* User ecall */ - case 0x9: /* Supervisor ecall */ - case 0xa: /* Hypervisor ecall */ - case 0xb: /* Machine ecall */ - show_regs(regs); - break; - default: - show_regs(regs); - break; - } - } -} - -static void dummy_interrupt_function(void *data) { -} \ No newline at end of file diff --git a/src/arch/riscv/riscv64_ae350/fprw.S b/src/arch/riscv/riscv64_ae350/fprw.S deleted file mode 100644 index ec48c0b5b..000000000 --- a/src/arch/riscv/riscv64_ae350/fprw.S +++ /dev/null @@ -1,319 +0,0 @@ -#if defined(__riscv_flen) -#if __riscv_flen >= 32 -#define fread32(which) .Lr32_##which: fsw which, 0(a1); ret -#define fwrite32(which) .Lw32_##which: flw which, 0(a1); ret - .text - .align 3 - .globl f32_read -f32_read: - la a2, .Lr32_t - andi a0, a0, 31 - slli a0, a0, 1 - add a0, a0, a2 - lbu a0, 0(a0) - add a0, a0, a2 - jr a0 - .align 3 -.Lr32_t: - .half .Lr32_f0 - .Lr32_t - .half .Lr32_f1 - .Lr32_t - .half .Lr32_f2 - .Lr32_t - .half .Lr32_f3 - .Lr32_t - .half .Lr32_f4 - .Lr32_t - .half .Lr32_f5 - .Lr32_t - .half .Lr32_f6 - .Lr32_t - .half .Lr32_f7 - .Lr32_t - .half .Lr32_f8 - .Lr32_t - .half .Lr32_f9 - .Lr32_t - .half .Lr32_f10 - .Lr32_t - .half .Lr32_f11 - .Lr32_t - .half .Lr32_f12 - .Lr32_t - .half .Lr32_f13 - .Lr32_t - .half .Lr32_f14 - .Lr32_t - .half .Lr32_f15 - .Lr32_t - .half .Lr32_f16 - .Lr32_t - .half .Lr32_f17 - .Lr32_t - .half .Lr32_f18 - .Lr32_t - .half .Lr32_f19 - .Lr32_t - .half .Lr32_f20 - .Lr32_t - .half .Lr32_f21 - .Lr32_t - .half .Lr32_f22 - .Lr32_t - .half .Lr32_f23 - .Lr32_t - .half .Lr32_f24 - .Lr32_t - .half .Lr32_f25 - .Lr32_t - .half .Lr32_f26 - .Lr32_t - .half .Lr32_f27 - .Lr32_t - .half .Lr32_f28 - .Lr32_t - .half .Lr32_f29 - .Lr32_t - .half .Lr32_f30 - .Lr32_t - .half .Lr32_f31 - .Lr32_t - fread32(f0) - fread32(f1) - fread32(f2) - fread32(f3) - fread32(f4) - fread32(f5) - fread32(f6) - fread32(f7) - fread32(f8) - fread32(f9) - fread32(f10) - fread32(f11) - fread32(f12) - fread32(f13) - fread32(f14) - fread32(f15) - fread32(f16) - fread32(f17) - fread32(f18) - fread32(f19) - fread32(f20) - fread32(f21) - fread32(f22) - fread32(f23) - fread32(f24) - fread32(f25) - fread32(f26) - fread32(f27) - fread32(f28) - fread32(f29) - fread32(f30) - fread32(f31) - - .align 3 - .globl f32_write -f32_write: - la a2, .Lw32_t - andi a0, a0, 31 - slli a0, a0, 1 - add a0, a0, a2 - lbu a0, 0(a0) - add a0, a0, a2 - jr a0 - .align 3 -.Lw32_t: - .half .Lw32_f0 - .Lw32_t - .half .Lw32_f1 - .Lw32_t - .half .Lw32_f2 - .Lw32_t - .half .Lw32_f3 - .Lw32_t - .half .Lw32_f4 - .Lw32_t - .half .Lw32_f5 - .Lw32_t - .half .Lw32_f6 - .Lw32_t - .half .Lw32_f7 - .Lw32_t - .half .Lw32_f8 - .Lw32_t - .half .Lw32_f9 - .Lw32_t - .half .Lw32_f10 - .Lw32_t - .half .Lw32_f11 - .Lw32_t - .half .Lw32_f12 - .Lw32_t - .half .Lw32_f13 - .Lw32_t - .half .Lw32_f14 - .Lw32_t - .half .Lw32_f15 - .Lw32_t - .half .Lw32_f16 - .Lw32_t - .half .Lw32_f17 - .Lw32_t - .half .Lw32_f18 - .Lw32_t - .half .Lw32_f19 - .Lw32_t - .half .Lw32_f20 - .Lw32_t - .half .Lw32_f21 - .Lw32_t - .half .Lw32_f22 - .Lw32_t - .half .Lw32_f23 - .Lw32_t - .half .Lw32_f24 - .Lw32_t - .half .Lw32_f25 - .Lw32_t - .half .Lw32_f26 - .Lw32_t - .half .Lw32_f27 - .Lw32_t - .half .Lw32_f28 - .Lw32_t - .half .Lw32_f29 - .Lw32_t - .half .Lw32_f30 - .Lw32_t - .half .Lw32_f31 - .Lw32_t - fwrite32(f0) - fwrite32(f1) - fwrite32(f2) - fwrite32(f3) - fwrite32(f4) - fwrite32(f5) - fwrite32(f6) - fwrite32(f7) - fwrite32(f8) - fwrite32(f9) - fwrite32(f10) - fwrite32(f11) - fwrite32(f12) - fwrite32(f13) - fwrite32(f14) - fwrite32(f15) - fwrite32(f16) - fwrite32(f17) - fwrite32(f18) - fwrite32(f19) - fwrite32(f20) - fwrite32(f21) - fwrite32(f22) - fwrite32(f23) - fwrite32(f24) - fwrite32(f25) - fwrite32(f26) - fwrite32(f27) - fwrite32(f28) - fwrite32(f29) - fwrite32(f30) - fwrite32(f31) -#endif - -#if __riscv_flen >= 64 -#define fread64(which) .Lr64_##which: fsd which, 0(a1); ret -#define fwrite64(which) .Lw64_##which: fld which, 0(a1); ret - .text - .align 3 - .globl f64_read -f64_read: - la a2, .Lr64_t - andi a0, a0, 31 - slli a0, a0, 1 - add a0, a0, a2 - lbu a0, 0(a0) - add a0, a0, a2 - jr a0 - .align 3 -.Lr64_t: - .half .Lr64_f0 - .Lr64_t - .half .Lr64_f1 - .Lr64_t - .half .Lr64_f2 - .Lr64_t - .half .Lr64_f3 - .Lr64_t - .half .Lr64_f4 - .Lr64_t - .half .Lr64_f5 - .Lr64_t - .half .Lr64_f6 - .Lr64_t - .half .Lr64_f7 - .Lr64_t - .half .Lr64_f8 - .Lr64_t - .half .Lr64_f9 - .Lr64_t - .half .Lr64_f10 - .Lr64_t - .half .Lr64_f11 - .Lr64_t - .half .Lr64_f12 - .Lr64_t - .half .Lr64_f13 - .Lr64_t - .half .Lr64_f14 - .Lr64_t - .half .Lr64_f15 - .Lr64_t - .half .Lr64_f16 - .Lr64_t - .half .Lr64_f17 - .Lr64_t - .half .Lr64_f18 - .Lr64_t - .half .Lr64_f19 - .Lr64_t - .half .Lr64_f20 - .Lr64_t - .half .Lr64_f21 - .Lr64_t - .half .Lr64_f22 - .Lr64_t - .half .Lr64_f23 - .Lr64_t - .half .Lr64_f24 - .Lr64_t - .half .Lr64_f25 - .Lr64_t - .half .Lr64_f26 - .Lr64_t - .half .Lr64_f27 - .Lr64_t - .half .Lr64_f28 - .Lr64_t - .half .Lr64_f29 - .Lr64_t - .half .Lr64_f30 - .Lr64_t - .half .Lr64_f31 - .Lr64_t - fread64(f0) - fread64(f1) - fread64(f2) - fread64(f3) - fread64(f4) - fread64(f5) - fread64(f6) - fread64(f7) - fread64(f8) - fread64(f9) - fread64(f10) - fread64(f11) - fread64(f12) - fread64(f13) - fread64(f14) - fread64(f15) - fread64(f16) - fread64(f17) - fread64(f18) - fread64(f19) - fread64(f20) - fread64(f21) - fread64(f22) - fread64(f23) - fread64(f24) - fread64(f25) - fread64(f26) - fread64(f27) - fread64(f28) - fread64(f29) - fread64(f30) - fread64(f31) - - .align 3 - .globl f64_write -f64_write: - la a2, .Lw64_t - andi a0, a0, 31 - slli a0, a0, 1 - add a0, a0, a2 - lbu a0, 0(a0) - add a0, a0, a2 - jr a0 - .align 3 -.Lw64_t: - .half .Lw64_f0 - .Lw64_t - .half .Lw64_f1 - .Lw64_t - .half .Lw64_f2 - .Lw64_t - .half .Lw64_f3 - .Lw64_t - .half .Lw64_f4 - .Lw64_t - .half .Lw64_f5 - .Lw64_t - .half .Lw64_f6 - .Lw64_t - .half .Lw64_f7 - .Lw64_t - .half .Lw64_f8 - .Lw64_t - .half .Lw64_f9 - .Lw64_t - .half .Lw64_f10 - .Lw64_t - .half .Lw64_f11 - .Lw64_t - .half .Lw64_f12 - .Lw64_t - .half .Lw64_f13 - .Lw64_t - .half .Lw64_f14 - .Lw64_t - .half .Lw64_f15 - .Lw64_t - .half .Lw64_f16 - .Lw64_t - .half .Lw64_f17 - .Lw64_t - .half .Lw64_f18 - .Lw64_t - .half .Lw64_f19 - .Lw64_t - .half .Lw64_f20 - .Lw64_t - .half .Lw64_f21 - .Lw64_t - .half .Lw64_f22 - .Lw64_t - .half .Lw64_f23 - .Lw64_t - .half .Lw64_f24 - .Lw64_t - .half .Lw64_f25 - .Lw64_t - .half .Lw64_f26 - .Lw64_t - .half .Lw64_f27 - .Lw64_t - .half .Lw64_f28 - .Lw64_t - .half .Lw64_f29 - .Lw64_t - .half .Lw64_f30 - .Lw64_t - .half .Lw64_f31 - .Lw64_t - fwrite64(f0) - fwrite64(f1) - fwrite64(f2) - fwrite64(f3) - fwrite64(f4) - fwrite64(f5) - fwrite64(f6) - fwrite64(f7) - fwrite64(f8) - fwrite64(f9) - fwrite64(f10) - fwrite64(f11) - fwrite64(f12) - fwrite64(f13) - fwrite64(f14) - fwrite64(f15) - fwrite64(f16) - fwrite64(f17) - fwrite64(f18) - fwrite64(f19) - fwrite64(f20) - fwrite64(f21) - fwrite64(f22) - fwrite64(f23) - fwrite64(f24) - fwrite64(f25) - fwrite64(f26) - fwrite64(f27) - fwrite64(f28) - fwrite64(f29) - fwrite64(f30) - fwrite64(f31) -#endif -#endif \ No newline at end of file diff --git a/src/arch/riscv/riscv64_ae350/memcmp.c b/src/arch/riscv/riscv64_ae350/memcmp.c deleted file mode 100644 index 9dda01412..000000000 --- a/src/arch/riscv/riscv64_ae350/memcmp.c +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include -#include -#include -#include -#include -#include - -int memcmp(const void *s1, const void *s2, size_t n) { - const unsigned char *su1, *su2; - int res = 0; - - for (su1 = s1, su2 = s2; 0 < n; ++su1, ++su2, n--) - if ((res = *su1 - *su2) != 0) - break; - return res; -} \ No newline at end of file diff --git a/src/arch/riscv/riscv64_ae350/memcpy.S b/src/arch/riscv/riscv64_ae350/memcpy.S deleted file mode 100644 index 7d045ee49..000000000 --- a/src/arch/riscv/riscv64_ae350/memcpy.S +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include - - .global memcpy - .type memcpy, %function - .align 3 -memcpy: - move t6, a0 - sltiu a3, a2, 128 - bnez a3, 4f - andi a3, t6, REGSZ - 1 - andi a4, a1, REGSZ - 1 - bne a3, a4, 4f - beqz a3, 2f - andi a3, a1, ~(REGSZ - 1) - addi a3, a3, REGSZ - sub a4, a3, a1 -1: lb a5, 0(a1) - addi a1, a1, 1 - sb a5, 0(t6) - addi t6, t6, 1 - bltu a1, a3, 1b - sub a2, a2, a4 -2: andi a4, a2, ~((16 * REGSZ) - 1) - beqz a4, 4f - add a3, a1, a4 -3: LREG a4, 0(a1) - LREG a5, REGSZ(a1) - LREG a6, 2 * REGSZ(a1) - LREG a7, 3 * REGSZ(a1) - LREG t0, 4 * REGSZ(a1) - LREG t1, 5 * REGSZ(a1) - LREG t2, 6 * REGSZ(a1) - LREG t3, 7 * REGSZ(a1) - LREG t4, 8 * REGSZ(a1) - LREG t5, 9 * REGSZ(a1) - SREG a4, 0(t6) - SREG a5, REGSZ(t6) - SREG a6, 2 * REGSZ(t6) - SREG a7, 3 * REGSZ(t6) - SREG t0, 4 * REGSZ(t6) - SREG t1, 5 * REGSZ(t6) - SREG t2, 6 * REGSZ(t6) - SREG t3, 7 * REGSZ(t6) - SREG t4, 8 * REGSZ(t6) - SREG t5, 9 * REGSZ(t6) - LREG a4, 10 * REGSZ(a1) - LREG a5, 11 * REGSZ(a1) - LREG a6, 12 * REGSZ(a1) - LREG a7, 13 * REGSZ(a1) - LREG t0, 14 * REGSZ(a1) - LREG t1, 15 * REGSZ(a1) - addi a1, a1, 16 * REGSZ - SREG a4, 10 * REGSZ(t6) - SREG a5, 11 * REGSZ(t6) - SREG a6, 12 * REGSZ(t6) - SREG a7, 13 * REGSZ(t6) - SREG t0, 14 * REGSZ(t6) - SREG t1, 15 * REGSZ(t6) - addi t6, t6, 16 * REGSZ - bltu a1, a3, 3b - andi a2, a2, (16 * REGSZ) - 1 -4: beqz a2, 6f - add a3, a1, a2 - or a5, a1, t6 - or a5, a5, a3 - andi a5, a5, 3 - bnez a5, 5f -7: lw a4, 0(a1) - addi a1, a1, 4 - sw a4, 0(t6) - addi t6, t6, 4 - bltu a1, a3, 7b - ret -5: lb a4, 0(a1) - addi a1, a1, 1 - sb a4, 0(t6) - addi t6, t6, 1 - bltu a1, a3, 5b -6: ret \ No newline at end of file diff --git a/src/arch/riscv/riscv64_ae350/memset.S b/src/arch/riscv/riscv64_ae350/memset.S deleted file mode 100644 index 8660c60f7..000000000 --- a/src/arch/riscv/riscv64_ae350/memset.S +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include - - .global memset - .type memset, %function - .align 3 -memset: - move t0, a0 - sltiu a3, a2, 16 - bnez a3, 4f - addi a3, t0, REGSZ - 1 - andi a3, a3, ~(REGSZ - 1) - beq a3, t0, 2f - sub a4, a3, t0 -1: sb a1, 0(t0) - addi t0, t0, 1 - bltu t0, a3, 1b - sub a2, a2, a4 -2: andi a1, a1, 0xff - slli a3, a1, 8 - or a1, a3, a1 - slli a3, a1, 16 - or a1, a3, a1 -#if __riscv_xlen == 64 - slli a3, a1, 32 - or a1, a3, a1 -#endif - andi a4, a2, ~(REGSZ - 1) - add a3, t0, a4 - andi a4, a4, 31 * REGSZ - beqz a4, 3f - neg a4, a4 - addi a4, a4, 32 * REGSZ - sub t0, t0, a4 - la a5, 3f -#if __riscv_xlen == 64 - srli a4, a4, 1 -#endif - add a5, a5, a4 - jr a5 -3: SREG a1, 0(t0) - SREG a1, REGSZ(t0) - SREG a1, 2 * REGSZ(t0) - SREG a1, 3 * REGSZ(t0) - SREG a1, 4 * REGSZ(t0) - SREG a1, 5 * REGSZ(t0) - SREG a1, 6 * REGSZ(t0) - SREG a1, 7 * REGSZ(t0) - SREG a1, 8 * REGSZ(t0) - SREG a1, 9 * REGSZ(t0) - SREG a1, 10 * REGSZ(t0) - SREG a1, 11 * REGSZ(t0) - SREG a1, 12 * REGSZ(t0) - SREG a1, 13 * REGSZ(t0) - SREG a1, 14 * REGSZ(t0) - SREG a1, 15 * REGSZ(t0) - SREG a1, 16 * REGSZ(t0) - SREG a1, 17 * REGSZ(t0) - SREG a1, 18 * REGSZ(t0) - SREG a1, 19 * REGSZ(t0) - SREG a1, 20 * REGSZ(t0) - SREG a1, 21 * REGSZ(t0) - SREG a1, 22 * REGSZ(t0) - SREG a1, 23 * REGSZ(t0) - SREG a1, 24 * REGSZ(t0) - SREG a1, 25 * REGSZ(t0) - SREG a1, 26 * REGSZ(t0) - SREG a1, 27 * REGSZ(t0) - SREG a1, 28 * REGSZ(t0) - SREG a1, 29 * REGSZ(t0) - SREG a1, 30 * REGSZ(t0) - SREG a1, 31 * REGSZ(t0) - addi t0, t0, 32 * REGSZ - bltu t0, a3, 3b - andi a2, a2, REGSZ - 1 -4: beqz a2, 6f - add a3, t0, a2 -5: sb a1, 0(t0) - addi t0, t0, 1 - bltu t0, a3, 5b -6: ret \ No newline at end of file diff --git a/src/arch/riscv/riscv64_ae350/timer.c b/src/arch/riscv/riscv64_ae350/timer.c deleted file mode 100644 index 24140c3e7..000000000 --- a/src/arch/riscv/riscv64_ae350/timer.c +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include -#include -#include -#include -#include -#include - -#include - -#include - -static uint32_t init_timestamp = 0; - -void set_timer_count() { - init_timestamp = (uint32_t) time_us(); -} - -/* - * 64bit arch timer.CNTPCT - * Freq = 24000000Hz - */ -uint64_t get_arch_counter(void) { - uint64_t cnt = 0; - - asm volatile("csrr %0, time\n" - : "=r"(cnt) - : - : "memory"); - - return cnt; -} - -/* - * get current time.(millisecond) - */ -uint32_t time_ms(void) { - return get_arch_counter() / 24000; -} - -/* - * get current time.(microsecond) - */ -uint64_t time_us(void) { - return get_arch_counter() / (uint64_t) 24; -} - -void udelay(uint64_t us) { - uint64_t now; - - now = time_us(); - while (time_us() - now < us) { - }; -} - -void mdelay(uint32_t ms) { - udelay(ms * 1000); - uint32_t now; - - now = time_ms(); - while (time_ms() - now < ms) { - }; -} - -void sdelay(uint32_t loops) { - asm volatile( - "mv t0, %0\n"// Move the 'loops' value to register t0 - "1:\n" - "addi t0, t0, -1\n"// Decrement t0 by 1 - "bnez t0, 1b\n" // Branch back to label 1 if t0 is not zero - : // No output operands - : "r"(loops) // Input operand: loops - : "t0" // Clobbered registers: t0 - ); -} - -uint32_t get_init_timestamp() { - return init_timestamp; -} diff --git a/src/arch/riscv/riscv64_c906/CMakeLists.txt b/src/arch/riscv/riscv64_c906/CMakeLists.txt index b19eb5892..103d39327 100644 --- a/src/arch/riscv/riscv64_c906/CMakeLists.txt +++ b/src/arch/riscv/riscv64_c906/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_library(arch-obj OBJECT timer.c diff --git a/src/arch/riscv/riscv64_c906/exception.c b/src/arch/riscv/riscv64_c906/exception.c index ba821e9d2..dcdbcf7a9 100644 --- a/src/arch/riscv/riscv64_c906/exception.c +++ b/src/arch/riscv/riscv64_c906/exception.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/arch/riscv/riscv64_c906/memcmp.c b/src/arch/riscv/riscv64_c906/memcmp.c index 9dda01412..210c9352a 100644 --- a/src/arch/riscv/riscv64_c906/memcmp.c +++ b/src/arch/riscv/riscv64_c906/memcmp.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/arch/riscv/riscv64_c906/memcpy.S b/src/arch/riscv/riscv64_c906/memcpy.S index 7d045ee49..c220a40dd 100644 --- a/src/arch/riscv/riscv64_c906/memcpy.S +++ b/src/arch/riscv/riscv64_c906/memcpy.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/src/arch/riscv/riscv64_c906/memset.S b/src/arch/riscv/riscv64_c906/memset.S index 8660c60f7..e47a686dc 100644 --- a/src/arch/riscv/riscv64_c906/memset.S +++ b/src/arch/riscv/riscv64_c906/memset.S @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/src/arch/riscv/riscv64_c906/timer.c b/src/arch/riscv/riscv64_c906/timer.c index 24140c3e7..c4baab03a 100644 --- a/src/arch/riscv/riscv64_c906/timer.c +++ b/src/arch/riscv/riscv64_c906/timer.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/cli/commands.c b/src/cli/commands.c index a38a9f448..780c2c60b 100644 --- a/src/cli/commands.c +++ b/src/cli/commands.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/cli/history.c b/src/cli/history.c index 246b538ed..e1521ec57 100644 --- a/src/cli/history.c +++ b/src/cli/history.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/cli/lineedit.c b/src/cli/lineedit.c index bd4b9ded2..886b926f1 100644 --- a/src/cli/lineedit.c +++ b/src/cli/lineedit.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/cli/parse.c b/src/cli/parse.c index c332d7d76..04b5cddb4 100644 --- a/src/cli/parse.c +++ b/src/cli/parse.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/common.c b/src/common.c index 18df6cd7e..15a37b45c 100644 --- a/src/common.c +++ b/src/common.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include #include diff --git a/src/ctype.c b/src/ctype.c index 8e3d989f6..2104e22cc 100644 --- a/src/ctype.c +++ b/src/ctype.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/CMakeLists.txt b/src/drivers/CMakeLists.txt index 3e3dc326d..9947a219a 100644 --- a/src/drivers/CMakeLists.txt +++ b/src/drivers/CMakeLists.txt @@ -1,55 +1,19 @@ -set(DRIVER_PMU "") - -set(COMMON_DRIVER - sys-uart.c - sys-gpio.c -) - -set(USB_DRIVER "") -if (CONFIG_CHIP_USB) -set(USB_DRIVER - usb/usb.c - usb/usb_controller.c - usb/usb_device.c - usb/usb_dma.c - - usb/module/usb_detect.c - usb/module/usb_mass.c -) -endif() - -set(GIC_DRIVER "") -if (CONFIG_CHIP_GIC) -set(GIC_DRIVER - sys-gic.c -) -endif() - -if (CONFIG_CHIP_WITHPMU) - set(DRIVER_PMU - pmu/axp.c - pmu/axp1530.c - pmu/axp2101.c - pmu/axp2202.c - ) -endif() +add_syterkit_driver(gpio) +add_syterkit_driver(intc) +add_syterkit_driver(pmu) +add_syterkit_driver(mtd) +add_syterkit_driver(usb) +add_syterkit_driver(ufs) if (CONFIG_CHIP_MMC_V2) - set(MMC_DRIVER - mmc/sys-mmc.c - mmc/sys-sdhci.c - mmc/sys-sdcard.c - ) + add_syterkit_driver(mmc) else() - set(MMC_DRIVER - sdhci/sys-sdcard.c - sdhci/sys-sdhci.c - ) + add_syterkit_driver(sdhci) endif() -set(MTD_DRIVER - mtd/sys-spi-nand.c - mtd/sys-spi-nor.c +set(COMMON_DRIVER + sys-uart.c + ${DRIVER_GPIO} ) if (NOT CONFIG_CHIP_MINSYS) @@ -63,7 +27,7 @@ if (NOT CONFIG_CHIP_MINSYS) sys-i2c.c ${USB_DRIVER} - ${GIC_DRIVER} + ${INTC_DRIVER} ${MMC_DRIVER} ${MTD_DRIVER} ) diff --git a/src/drivers/chips/CMakeLists.txt b/src/drivers/chips/CMakeLists.txt index 99a0e8884..7a64fad39 100644 --- a/src/drivers/chips/CMakeLists.txt +++ b/src/drivers/chips/CMakeLists.txt @@ -10,8 +10,8 @@ elseif(CONFIG_CHIP_SUN55IW3) add_subdirectory(sun55iw3) elseif(CONFIG_CHIP_SUN50IW10) add_subdirectory(sun50iw10) -elseif(CONFIG_CHIP_SUN50IW10) - add_subdirectory(sun50iw10) elseif(CONFIG_CHIP_SUN20IW5) add_subdirectory(sun20iw5) +elseif(CONFIG_CHIP_SUN60IW2) + add_subdirectory(sun60iw2) endif() diff --git a/src/drivers/chips/sun20iw1/sys-clk.c b/src/drivers/chips/sun20iw1/sys-clk.c index 5c21aea78..cdd020f5d 100644 --- a/src/drivers/chips/sun20iw1/sys-clk.c +++ b/src/drivers/chips/sun20iw1/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun20iw1/sys-rproc.c b/src/drivers/chips/sun20iw1/sys-rproc.c index 1250ab31b..0ee310779 100644 --- a/src/drivers/chips/sun20iw1/sys-rproc.c +++ b/src/drivers/chips/sun20iw1/sys-rproc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun20iw1/sys-sdhci.c b/src/drivers/chips/sun20iw1/sys-sdhci.c new file mode 100644 index 000000000..0c691d2d2 --- /dev/null +++ b/src/drivers/chips/sun20iw1/sys-sdhci.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { + uint32_t reg_val = 0x0, sclk_hz = 0x0, div = 0x0; + + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + if (clk_hz <= 4000000) { + clk.clk_sel = 0; + sclk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; /* use hosc clk */ + } else { + if (clk.clk_sel && clk.parent_clk) { + sclk_hz = clk.parent_clk; + } else { + clk.clk_sel = 1; + sclk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; /* use 2x pll-per0 clock */ + } + } + + div = (2 * sclk_hz + clk_hz) / (2 * clk_hz); + div = (div == 0) ? 1 : div; + + if (div > 128) { + clk.factor_m = 1; + clk.factor_n = 0; + printk_warning("SMHC: Source clk is too high.\n"); + } else if (div > 64) { + clk.factor_n = 3; + clk.factor_m = div >> 3; + } else if (div > 32) { + clk.factor_n = 2; + clk.factor_m = div >> 2; + } else if (div > 16) { + clk.factor_n = 1; + clk.factor_m = div >> 1; + } else { + clk.factor_n = 0; + clk.factor_m = div; + } + + reg_val = BIT(31) | (clk.clk_sel << 24) | ((clk.factor_n) << clk.reg_factor_n_offset) | + ((clk.factor_m - 1) << clk.reg_factor_m_offset); + + writel(reg_val, clk.reg_base); + + printk_trace("SMHC: sdhci%d clk want %uHz parent %uHz, mclk=0x%08x clk_sel=%u, div=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, + clk.factor_n, clk.factor_m); + return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t clk_hz = 0x0; + uint32_t reg_val = 0x0; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + // Read the clock register value + reg_val = readl(clk.reg_base); + + // Extract the divider values and clock source from the register value + clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; + clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; + + // check clk sel, check if correct + if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { + clk.clk_sel = ((reg_val >> 24) & 0x3); + } + + // Calculate the current clock frequency based on the source and divider values + switch (clk.clk_sel) { + case 0: + clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; + break; + case 1: + if (clk.parent_clk && clk.clk_sel) { + clk_hz = clk.parent_clk; + } else { + clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; + } + break; + default: + printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); + break; + } + + printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); +} \ No newline at end of file diff --git a/src/drivers/chips/sun20iw1/sys-sid.c b/src/drivers/chips/sun20iw1/sys-sid.c index ed05c8e46..0051679a5 100644 --- a/src/drivers/chips/sun20iw1/sys-sid.c +++ b/src/drivers/chips/sun20iw1/sys-sid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun20iw1/sys-wdt.c b/src/drivers/chips/sun20iw1/sys-wdt.c index 4bce8b1fb..a827b79b9 100644 --- a/src/drivers/chips/sun20iw1/sys-wdt.c +++ b/src/drivers/chips/sun20iw1/sys-wdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun20iw5/CMakeLists.txt b/src/drivers/chips/sun20iw5/CMakeLists.txt index 41d913f58..6d888b9a6 100644 --- a/src/drivers/chips/sun20iw5/CMakeLists.txt +++ b/src/drivers/chips/sun20iw5/CMakeLists.txt @@ -4,4 +4,5 @@ add_library(chip_drivers-obj OBJECT sys-wdt.c sys-dram.c sys-rproc.c + sys-sdhci.c ) \ No newline at end of file diff --git a/src/drivers/chips/sun20iw5/sys-clk.c b/src/drivers/chips/sun20iw5/sys-clk.c index 2b6d48074..4e4455825 100644 --- a/src/drivers/chips/sun20iw5/sys-clk.c +++ b/src/drivers/chips/sun20iw5/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun20iw5/sys-rproc.c b/src/drivers/chips/sun20iw5/sys-rproc.c index 09cceddd0..255729365 100644 --- a/src/drivers/chips/sun20iw5/sys-rproc.c +++ b/src/drivers/chips/sun20iw5/sys-rproc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun20iw5/sys-sdhci.c b/src/drivers/chips/sun20iw5/sys-sdhci.c index 665b2760c..4043d7395 100644 --- a/src/drivers/chips/sun20iw5/sys-sdhci.c +++ b/src/drivers/chips/sun20iw5/sys-sdhci.c @@ -69,4 +69,53 @@ int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, clk.factor_n, clk.factor_m); return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t clk_hz = 0x0; + uint32_t reg_val = 0x0; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + // Read the clock register value + reg_val = readl(clk.reg_base); + + // Extract the divider values and clock source from the register value + clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; + clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; + + // check clk sel, check if correct + if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { + clk.clk_sel = ((reg_val >> 24) & 0x3); + } + + // Calculate the current clock frequency based on the source and divider values + switch (clk.clk_sel) { + case 0: + clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; + break; + case 1: + if (clk.parent_clk && clk.clk_sel) { + clk_hz = clk.parent_clk; + } else { + clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; + } + break; + default: + printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); + break; + } + + printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); } \ No newline at end of file diff --git a/src/drivers/chips/sun20iw5/sys-sid.c b/src/drivers/chips/sun20iw5/sys-sid.c index ed05c8e46..0051679a5 100644 --- a/src/drivers/chips/sun20iw5/sys-sid.c +++ b/src/drivers/chips/sun20iw5/sys-sid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun20iw5/sys-wdt.c b/src/drivers/chips/sun20iw5/sys-wdt.c index 4bce8b1fb..a827b79b9 100644 --- a/src/drivers/chips/sun20iw5/sys-wdt.c +++ b/src/drivers/chips/sun20iw5/sys-wdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw10/CMakeLists.txt b/src/drivers/chips/sun50iw10/CMakeLists.txt index 85ef89749..3820ccdbc 100644 --- a/src/drivers/chips/sun50iw10/CMakeLists.txt +++ b/src/drivers/chips/sun50iw10/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_library(chip_drivers-obj OBJECT sys-clk.c diff --git a/src/drivers/chips/sun50iw10/sys-clk.c b/src/drivers/chips/sun50iw10/sys-clk.c index 16d2db226..5d35ed1ab 100644 --- a/src/drivers/chips/sun50iw10/sys-clk.c +++ b/src/drivers/chips/sun50iw10/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw10/sys-dram.asm.c b/src/drivers/chips/sun50iw10/sys-dram.asm.c index 80a6f77d5..1ed315bde 100644 --- a/src/drivers/chips/sun50iw10/sys-dram.asm.c +++ b/src/drivers/chips/sun50iw10/sys-dram.asm.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw10/sys-dram.c b/src/drivers/chips/sun50iw10/sys-dram.c index 2af355791..39397c809 100644 --- a/src/drivers/chips/sun50iw10/sys-dram.c +++ b/src/drivers/chips/sun50iw10/sys-dram.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw10/sys-sdhci.c b/src/drivers/chips/sun50iw10/sys-sdhci.c new file mode 100644 index 000000000..0c691d2d2 --- /dev/null +++ b/src/drivers/chips/sun50iw10/sys-sdhci.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { + uint32_t reg_val = 0x0, sclk_hz = 0x0, div = 0x0; + + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + if (clk_hz <= 4000000) { + clk.clk_sel = 0; + sclk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; /* use hosc clk */ + } else { + if (clk.clk_sel && clk.parent_clk) { + sclk_hz = clk.parent_clk; + } else { + clk.clk_sel = 1; + sclk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; /* use 2x pll-per0 clock */ + } + } + + div = (2 * sclk_hz + clk_hz) / (2 * clk_hz); + div = (div == 0) ? 1 : div; + + if (div > 128) { + clk.factor_m = 1; + clk.factor_n = 0; + printk_warning("SMHC: Source clk is too high.\n"); + } else if (div > 64) { + clk.factor_n = 3; + clk.factor_m = div >> 3; + } else if (div > 32) { + clk.factor_n = 2; + clk.factor_m = div >> 2; + } else if (div > 16) { + clk.factor_n = 1; + clk.factor_m = div >> 1; + } else { + clk.factor_n = 0; + clk.factor_m = div; + } + + reg_val = BIT(31) | (clk.clk_sel << 24) | ((clk.factor_n) << clk.reg_factor_n_offset) | + ((clk.factor_m - 1) << clk.reg_factor_m_offset); + + writel(reg_val, clk.reg_base); + + printk_trace("SMHC: sdhci%d clk want %uHz parent %uHz, mclk=0x%08x clk_sel=%u, div=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, + clk.factor_n, clk.factor_m); + return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t clk_hz = 0x0; + uint32_t reg_val = 0x0; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + // Read the clock register value + reg_val = readl(clk.reg_base); + + // Extract the divider values and clock source from the register value + clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; + clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; + + // check clk sel, check if correct + if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { + clk.clk_sel = ((reg_val >> 24) & 0x3); + } + + // Calculate the current clock frequency based on the source and divider values + switch (clk.clk_sel) { + case 0: + clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; + break; + case 1: + if (clk.parent_clk && clk.clk_sel) { + clk_hz = clk.parent_clk; + } else { + clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; + } + break; + default: + printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); + break; + } + + printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); +} \ No newline at end of file diff --git a/src/drivers/chips/sun50iw10/sys-sid.c b/src/drivers/chips/sun50iw10/sys-sid.c index 685ef9fb6..13a3ee557 100644 --- a/src/drivers/chips/sun50iw10/sys-sid.c +++ b/src/drivers/chips/sun50iw10/sys-sid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw10/sys-wdt.c b/src/drivers/chips/sun50iw10/sys-wdt.c index 476fb51d0..74e25232a 100644 --- a/src/drivers/chips/sun50iw10/sys-wdt.c +++ b/src/drivers/chips/sun50iw10/sys-wdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw9/CMakeLists.txt b/src/drivers/chips/sun50iw9/CMakeLists.txt index 85ef89749..3820ccdbc 100644 --- a/src/drivers/chips/sun50iw9/CMakeLists.txt +++ b/src/drivers/chips/sun50iw9/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_library(chip_drivers-obj OBJECT sys-clk.c diff --git a/src/drivers/chips/sun50iw9/sys-clk.c b/src/drivers/chips/sun50iw9/sys-clk.c index 2dbe4b2dc..713ad4afd 100644 --- a/src/drivers/chips/sun50iw9/sys-clk.c +++ b/src/drivers/chips/sun50iw9/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw9/sys-dram.c b/src/drivers/chips/sun50iw9/sys-dram.c index 241e1c2a7..1cb74fab2 100644 --- a/src/drivers/chips/sun50iw9/sys-dram.c +++ b/src/drivers/chips/sun50iw9/sys-dram.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw9/sys-sdhci.c b/src/drivers/chips/sun50iw9/sys-sdhci.c new file mode 100644 index 000000000..0c691d2d2 --- /dev/null +++ b/src/drivers/chips/sun50iw9/sys-sdhci.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { + uint32_t reg_val = 0x0, sclk_hz = 0x0, div = 0x0; + + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + if (clk_hz <= 4000000) { + clk.clk_sel = 0; + sclk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; /* use hosc clk */ + } else { + if (clk.clk_sel && clk.parent_clk) { + sclk_hz = clk.parent_clk; + } else { + clk.clk_sel = 1; + sclk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; /* use 2x pll-per0 clock */ + } + } + + div = (2 * sclk_hz + clk_hz) / (2 * clk_hz); + div = (div == 0) ? 1 : div; + + if (div > 128) { + clk.factor_m = 1; + clk.factor_n = 0; + printk_warning("SMHC: Source clk is too high.\n"); + } else if (div > 64) { + clk.factor_n = 3; + clk.factor_m = div >> 3; + } else if (div > 32) { + clk.factor_n = 2; + clk.factor_m = div >> 2; + } else if (div > 16) { + clk.factor_n = 1; + clk.factor_m = div >> 1; + } else { + clk.factor_n = 0; + clk.factor_m = div; + } + + reg_val = BIT(31) | (clk.clk_sel << 24) | ((clk.factor_n) << clk.reg_factor_n_offset) | + ((clk.factor_m - 1) << clk.reg_factor_m_offset); + + writel(reg_val, clk.reg_base); + + printk_trace("SMHC: sdhci%d clk want %uHz parent %uHz, mclk=0x%08x clk_sel=%u, div=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, + clk.factor_n, clk.factor_m); + return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t clk_hz = 0x0; + uint32_t reg_val = 0x0; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + // Read the clock register value + reg_val = readl(clk.reg_base); + + // Extract the divider values and clock source from the register value + clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; + clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; + + // check clk sel, check if correct + if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { + clk.clk_sel = ((reg_val >> 24) & 0x3); + } + + // Calculate the current clock frequency based on the source and divider values + switch (clk.clk_sel) { + case 0: + clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; + break; + case 1: + if (clk.parent_clk && clk.clk_sel) { + clk_hz = clk.parent_clk; + } else { + clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; + } + break; + default: + printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); + break; + } + + printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); +} \ No newline at end of file diff --git a/src/drivers/chips/sun50iw9/sys-sid.c b/src/drivers/chips/sun50iw9/sys-sid.c index 685ef9fb6..13a3ee557 100644 --- a/src/drivers/chips/sun50iw9/sys-sid.c +++ b/src/drivers/chips/sun50iw9/sys-sid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun50iw9/sys-wdt.c b/src/drivers/chips/sun50iw9/sys-wdt.c index 476fb51d0..74e25232a 100644 --- a/src/drivers/chips/sun50iw9/sys-wdt.c +++ b/src/drivers/chips/sun50iw9/sys-wdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun55iw3/CMakeLists.txt b/src/drivers/chips/sun55iw3/CMakeLists.txt index 7619bcffc..be4341b17 100644 --- a/src/drivers/chips/sun55iw3/CMakeLists.txt +++ b/src/drivers/chips/sun55iw3/CMakeLists.txt @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: Apache-2.0 +# SPDX-License-Identifier: GPL-2.0+ add_library(chip_drivers-obj OBJECT sys-clk.c @@ -7,4 +7,5 @@ add_library(chip_drivers-obj OBJECT sys-rproc.c sys-sdhci.c sys-sid.c + sys-wdt.c ) \ No newline at end of file diff --git a/src/drivers/chips/sun55iw3/sys-clk.c b/src/drivers/chips/sun55iw3/sys-clk.c index f157146ea..aefbdd36d 100644 --- a/src/drivers/chips/sun55iw3/sys-clk.c +++ b/src/drivers/chips/sun55iw3/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun55iw3/sys-dram.c b/src/drivers/chips/sun55iw3/sys-dram.c index 28361d9d9..0755cfb74 100644 --- a/src/drivers/chips/sun55iw3/sys-dram.c +++ b/src/drivers/chips/sun55iw3/sys-dram.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun55iw3/sys-rproc.c b/src/drivers/chips/sun55iw3/sys-rproc.c index 3c68e3f80..24885b0b7 100644 --- a/src/drivers/chips/sun55iw3/sys-rproc.c +++ b/src/drivers/chips/sun55iw3/sys-rproc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun55iw3/sys-sdhci.c b/src/drivers/chips/sun55iw3/sys-sdhci.c index 6ec0e1794..1d88d075a 100644 --- a/src/drivers/chips/sun55iw3/sys-sdhci.c +++ b/src/drivers/chips/sun55iw3/sys-sdhci.c @@ -28,8 +28,8 @@ */ int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { uint32_t reg_val = 0x0; - - sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + mmc_t *mmc = sdhci->mmc; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; // Determine the clock source based on the requested frequency if (clk_hz <= 4000000) { @@ -38,31 +38,45 @@ int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { clk.clk_sel = 2;// SCLK = AHB PLL } + if ((mmc->speed_mode == MMC_HSDDR52_DDR50) && (mmc->bus_width == SMHC_WIDTH_8BIT)) { + clk_hz /= 4; + } else { + clk_hz /= 2; + } + // Set the clock divider values based on the requested frequency switch (clk_hz) { - case 400000: + case 0 ... 400000: clk.factor_n = 1; clk.factor_m = 0xe; break; - case 25000000: - case 26000000: + case 400001 ... 26000000: clk.factor_n = (sdhci->id == 2) ? 2 : 1; clk.factor_m = (sdhci->id == 2) ? 3 : 2; break; - case 50000000: - case 52000000: + case 26000001 ... 52000000: clk.factor_n = (sdhci->id == 2) ? 1 : 0; clk.factor_m = 2; break; - case 200000000: + case 52000001 ... 100000000: + clk.clk_sel = 1;// PERI0_800M + clk.factor_n = 0; + clk.factor_m = 3; + break; + case 100000001 ... 150000000: + clk.clk_sel = 1;// PERI0_800M + clk.factor_n = 0; + clk.factor_m = 2; + break; + case 150000001 ... 200000000: clk.clk_sel = 1;// PERI0_800M clk.factor_n = 0; clk.factor_m = 1; break; default: - clk.factor_n = 0; - clk.factor_m = 0; - printk_debug("SMHC: requested frequency does not match: freq=%d\n", clk_hz); + clk.factor_n = (sdhci->id == 2) ? 1 : 0; + clk.factor_m = 2; + printk_debug("SMHC: requested frequency does not match: freq=%d, default to 52000000\n", clk_hz); break; } @@ -114,124 +128,4 @@ uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { // Calculate the actual clock frequency based on the divider values return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); -} - -/** - * @brief Set the clock mode for the SDHC controller based on timing mode and other parameters. - * - * This function sets the clock mode for the SDHC controller based on the timing mode and other parameters. - * - * @param sdhci Pointer to the SDHC controller structure. - * @param clk Clock frequency. - * @return 0 on success, -1 on failure. - */ -int sunxi_sdhci_clock_mode(sunxi_sdhci_t *sdhci, uint32_t clk) { - int ret = 0; - uint32_t reg_val = 0x0; - sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; - sunxi_sdhci_timing_t *timing_data = sdhci->timing_data; - mmc_t *mmc = sdhci->mmc; - - uint32_t module_clk = 0x0; - - /* Reset mclk reg to default */ - writel(0x0, sdhci->sdhci_clk.reg_base); - - /* Setting mclk timing */ - if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) { - mmc_host->reg->ntsr |= BIT(31); - printk_trace("SMHC: rntsr 0x%x\n", mmc_host->reg->ntsr); - } else { - mmc_host->reg->ntsr = 0x0; - } - - if ((mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) || (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3)) { - /* If using DDR mod to 4 */ - if (mmc->speed_mode == MMC_HSDDR52_DDR50) { - module_clk = clk * 4; - } else { - module_clk = clk * 2; - } - } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { - /* If using DDR mod to 4 */ - if ((mmc->speed_mode == MMC_HSDDR52_DDR50) && (mmc->bus_width == SMHC_WIDTH_8BIT)) { - module_clk = clk * 4; - } else { - module_clk = clk * 2; - } - } - - /* Now set mclk */ - sunxi_sdhci_set_mclk(sdhci, clk); - - /* Now set clock by mclk we get */ - if ((mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) || (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3)) { - if (mmc->speed_mode == MMC_HSDDR52_DDR50) { - mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 4; - } else { - mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 2; - } - } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { - /* If using DDR mod to 4 */ - if ((mmc->speed_mode == MMC_HSDDR52_DDR50) && (mmc->bus_width == SMHC_WIDTH_8BIT)) { - mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 4; - } else { - mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 2; - } - } - /* Set host clock */ - printk_trace("SMHC: get round clk %luHz, mod_clk %luHz\n", mmc->clock, module_clk); - - /* enable mclk */ - setbits_le32(sdhci->sdhci_clk.reg_base, BIT(31)); - printk_trace("SMHC: mclkbase 0x%x\n", readl(sdhci->sdhci_clk.reg_base)); - - /* Configure SMHC_CLKDIV to open clock for devices */ - reg_val = mmc_host->reg->clkcr; - reg_val &= ~(0xff); - if ((mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) || (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3)) { - if (mmc->speed_mode == MMC_HSDDR52_DDR50) { - reg_val |= 0x1; - } - } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { - /* If using DDR mod to 4 */ - if ((mmc->speed_mode == MMC_HSDDR52_DDR50) && (mmc->bus_width == SMHC_WIDTH_8BIT)) { - reg_val |= 0x1; - } - } - mmc_host->reg->clkcr = reg_val; - - if (sunxi_sdhci_update_clk(sdhci)) { - return -1; - } - - /* config delay for mmc device */ - uint32_t freq_id = MMC_CLK_25M; - switch (clk) { - case 0 ... 400000: - freq_id = MMC_CLK_400K; - break; - case 400001 ... 26000000: - freq_id = MMC_CLK_25M; - break; - case 26000001 ... 52000000: - freq_id = MMC_CLK_50M; - break; - case 52000001 ... 100000000: - freq_id = MMC_CLK_100M; - break; - case 100000001 ... 150000000: - freq_id = MMC_CLK_150M; - break; - case 150000001 ... 200000000: - freq_id = MMC_CLK_200M; - break; - default: - freq_id = MMC_CLK_25M; - break; - } - - sunxi_sdhci_config_delay(sdhci, mmc->speed_mode, freq_id); - - return 0; } \ No newline at end of file diff --git a/src/drivers/chips/sun55iw3/sys-sid.c b/src/drivers/chips/sun55iw3/sys-sid.c index b20a02376..217dc5d73 100644 --- a/src/drivers/chips/sun55iw3/sys-sid.c +++ b/src/drivers/chips/sun55iw3/sys-sid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun55iw3/sys-wdt.c b/src/drivers/chips/sun55iw3/sys-wdt.c index 60374483b..7ee2b32b5 100644 --- a/src/drivers/chips/sun55iw3/sys-wdt.c +++ b/src/drivers/chips/sun55iw3/sys-wdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun60iw2/CMakeLists.txt b/src/drivers/chips/sun60iw2/CMakeLists.txt new file mode 100644 index 000000000..be4341b17 --- /dev/null +++ b/src/drivers/chips/sun60iw2/CMakeLists.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ + +add_library(chip_drivers-obj OBJECT + sys-clk.c + sys-dram.c + sys-wdt.c + sys-rproc.c + sys-sdhci.c + sys-sid.c + sys-wdt.c +) \ No newline at end of file diff --git a/src/drivers/chips/sun60iw2/sys-clk.c b/src/drivers/chips/sun60iw2/sys-clk.c new file mode 100644 index 000000000..f1323ec40 --- /dev/null +++ b/src/drivers/chips/sun60iw2/sys-clk.c @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#define PLL_REG_CONF(x) \ + { x, BIT(x##_PLL_FREF_SEL_OFFSET) } + +#define CPU_PLL_FACTOR_N_24M(x) (((x) + (24) - 1) / (24)) +#define CPU_PLL_FACTOR_N_26M(x) (((x) + (26) - 1) / (26)) + +const struct pll_reg_config { + uint32_t reg_addr; + uint32_t ref_sel_offset; +} pll_ctrl_regs[] = { + PLL_REG_CONF(PLL_DDR_CTRL_REG), + PLL_REG_CONF(PLL_PERI0_CTRL_REG), + PLL_REG_CONF(PLL_PERI1_CTRL_REG), + PLL_REG_CONF(PLL_GPU0_CTRL_REG), + PLL_REG_CONF(PLL_VIDEO0_CTRL_REG), + PLL_REG_CONF(PLL_VIDEO1_CTRL_REG), + PLL_REG_CONF(PLL_VIDEO2_CTRL_REG), + PLL_REG_CONF(PLL_VE0_CTRL_REG), + PLL_REG_CONF(PLL_VE1_CTRL_REG), + PLL_REG_CONF(PLL_AUDIO0_CTRL_REG), + PLL_REG_CONF(PLL_AUDIO1_CTRL_REG), + PLL_REG_CONF(PLL_NPU_CTRL_REG), + PLL_REG_CONF(PLL_DE_CTRL_REG), +}; + +static inline void set_pll_parent(void) { + for (size_t i = 0; i < sizeof(pll_ctrl_regs) / sizeof(pll_ctrl_regs[0]); i++) { + setbits_le32(SUNXI_CCU_BASE + pll_ctrl_regs[i].reg_addr, pll_ctrl_regs[i].ref_sel_offset); + } +} + +static inline void enable_pll(uint32_t addr, uint32_t m0, uint32_t n, uint32_t m1, uint32_t p) { + uint32_t reg_val; + + setbits_le32(addr, BIT(PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET)); + setbits_le32(addr, BIT(PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET)); + + reg_val = read32(addr); + reg_val &= ~((0x3 << 20) | (0xf << 16) | (0xff << 8) | (0xf << 0)); + reg_val |= ((m0 << 20) | (p << 16) | (n << 8) | (m1 << 0)); + write32(addr, reg_val); + + /* delay for pll */ + udelay(20); + + /* pll enable */ + setbits_le32(addr, BIT(PLL_CPU_CTRL_REG_PLL_EN_OFFSET)); + + /* lock enable */ + setbits_le32(addr, BIT(PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET)); + + /* enable update bit */ + setbits_le32(addr, BIT(26)); + + /* wait PLL_CPUX lockbit */ + while (read32(addr) & BIT(26)) + ; + + + for (int i = 0; i < 3; i++) { + while (!(read32(addr) & BIT(28))) + ; + } + udelay(20); +} + +static inline void set_pll(uint32_t addr, uint32_t m0, uint32_t n, uint32_t m1, uint32_t p) { + uint32_t reg_val; + + /* set pll source to 24M */ + clrbits_le32(addr + 0x1c, 0x3 << 24); + /* clear pll lock */ + clrbits_le32(addr, BIT(PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET) | BIT(PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET)); + reg_val = read32(addr); + reg_val &= ~((0x3 << 20) | (0xf << 16) | (0xff << 8) | (0xf << 0)); + reg_val |= ((m0 << 20) | (p << 16) | (n << 8) | (m1 << 0)); + write32(addr, reg_val); + + /* delay for pll */ + udelay(20); + + printk_trace("CLK: PLL CPU 0x%08x: 0x%08x, m0 = %d, n = %d, m1 = %d, p = %d\n", + addr, read32(addr), m0, n, m1, p); + + /* lock enable */ + setbits_le32(addr, BIT(PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET)); + + /* enable update bit */ + setbits_le32(addr, BIT(26)); + + /* wait PLL_CPUX lockbit */ + while (read32(addr) & BIT(26)) + ; + + for (int i = 0; i < 3; i++) { + while (!(read32(addr) & BIT(28))) + ; + } + udelay(20); + + /* enable pll output */ + setbits_le32(addr, BIT(PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET)); + printk_trace("CLK: PLL CPU 0x%08x: 0x%08x\n", addr, read32(addr)); + udelay(20); +} + +static inline void set_pll_cpux_axi(void) { + if (sunxi_clk_get_hosc_type() == 24) { + /* Set A76 Core 1.008GHz, A55 Core 1.008GHz, DSU 744MHz */ + enable_pll(CCU_PLL_CPU_L_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_24M(480), 0x0, 0x0); + set_pll(CCU_PLL_CPU_L_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_24M(1008), 0x0, 0x0); + enable_pll(CCU_PLL_CPU_B_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_24M(480), 0x0, 0x0); + set_pll(CCU_PLL_CPU_B_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_24M(1008), 0x0, 0x0); + enable_pll(CCU_PLL_CPU_DSU_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_24M(480), 0x0, 0x0); + set_pll(CCU_PLL_CPU_DSU_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_24M(744), 0x0, 0x0); + } else { + /* Set A76 Core 1.014GHz, A55 Core 1.014GHz, DSU 780MHz */ + enable_pll(CCU_PLL_CPU_L_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_26M(480), 0x0, 0x0); + set_pll(CCU_PLL_CPU_L_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_26M(1014), 0x0, 0x0); + enable_pll(CCU_PLL_CPU_B_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_26M(480), 0x0, 0x0); + set_pll(CCU_PLL_CPU_B_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_26M(1014), 0x0, 0x0); + enable_pll(CCU_PLL_CPU_DSU_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_26M(480), 0x0, 0x0); + set_pll(CCU_PLL_CPU_DSU_CTRL_REG, 0x0, CPU_PLL_FACTOR_N_26M(780), 0x0, 0x0); + } + printk_debug("CLK: PLL CPU_L: 0x%08x\n", read32(CCU_PLL_CPU_L_CTRL_REG)); + printk_debug("CLK: PLL CPU_B: 0x%08x\n", read32(CCU_PLL_CPU_B_CTRL_REG)); + printk_debug("CLK: PLL CPU_DSU: 0x%08x\n", read32(CCU_PLL_CPU_DSU_CTRL_REG)); + udelay(20); + clrsetbits_le32(CCU_PLL_CPU_L_CLK_REG, (0x07 << 24) | (0x03 << 16), (0x03 << 24) | (0x00 << 16)); + udelay(20); + clrsetbits_le32(CCU_PLL_CPU_B_CLK_REG, (0x07 << 24) | (0x03 << 16), (0x03 << 24) | (0x00 << 16)); + udelay(20); + clrsetbits_le32(CCU_PLL_DSU_CLK_REG, (0x07 << 24) | (0x03 << 16), (0x03 << 24) | (0x00 << 16)); +} + +static inline void set_apb1(void) { + clrsetbits_le32(SUNXI_CCU_BASE + APB1_CLK_REG, + APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK | APB1_CLK_REG_FACTOR_M_CLEAR_MASK, + APB1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M << APB1_CLK_REG_CLK_SRC_SEL_OFFSET | 0 << APB1_CLK_REG_FACTOR_M_OFFSET); +} + +static inline void set_pll_nsi(void) { + clrsetbits_le32(SUNXI_CCU_BASE + NSI_CLK_REG, + BIT(NSI_CLK_REG_NSI_CLK_GATING_OFFSET) | NSI_CLK_REG_NSI_DIV1_CLEAR_MASK, + (0x5 << NSI_CLK_REG_NSI_DIV1_OFFSET) | BIT(NSI_CLK_REG_NSI_UPD_OFFSET)); + while (read32(SUNXI_CCU_BASE + NSI_CLK_REG) & BIT(NSI_CLK_REG_NSI_UPD_OFFSET)) + ; + clrsetbits_le32(SUNXI_CCU_BASE + NSI_CLK_REG, + NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK, + (NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M << NSI_CLK_REG_NSI_CLK_SEL_OFFSET) | BIT(NSI_CLK_REG_NSI_CLK_GATING_OFFSET) | BIT(NSI_CLK_REG_NSI_UPD_OFFSET)); + while (read32(SUNXI_CCU_BASE + NSI_CLK_REG) & BIT(NSI_CLK_REG_NSI_UPD_OFFSET)) + ; +} + +void sunxi_clk_init(void) { + set_pll_parent(); + set_pll_cpux_axi(); + set_apb1(); + set_pll_nsi(); +} + +uint32_t sunxi_clk_get_hosc_type() { + if (read32(RTC_XO_CONTROL0_REG) & BIT(15)) { + return 26; + } else { + return 24; + } +} + +void sunxi_clk_reset(void) { +} + +uint32_t sunxi_clk_get_peri1x_rate() { + uint32_t reg32; + uint8_t plln, pllm, p0; + + /* PLL PERI */ + reg32 = read32(SUNXI_CCU_BASE + PLL_PERI0_CTRL_REG); + if (reg32 & (1 << 31)) { + plln = ((reg32 >> 8) & 0xff) + 1; + p0 = ((reg32 >> 20) & 0x03) + 1; + pllm = ((reg32 >> 1) & 0x01) + 1; + + return ((((24 * plln) / (pllm * p0))) * 1000 * 1000); + } + + return 0; +} + +static inline void sunxi_cpu_clk_dump(uint32_t pll_addr, uint32_t ctl_addr, char *name, uint32_t clk_hosc) { + uint32_t reg_val; + uint32_t clk_src; + uint32_t factor_n, div_m, div_m1; + uint8_t div_p; + uint32_t clock = 0; + char *clock_str; + + reg_val = readl(pll_addr); + clk_src = (reg_val >> 24) & 0x07; + + switch (clk_src) { + case 0: + case 1: + case 2: + clock = clk_hosc; + clock_str = "HOSC"; + break; + case 3://CPU_L_PP/P + reg_val = read32(ctl_addr); + factor_n = ((reg_val >> 8) & 0xff); + div_m = ((reg_val >> 0) & 0x3) + 1; + reg_val = read32(pll_addr); + div_p = 1 << ((reg_val >> 16) & 0x3); + clock = clk_hosc; + clock = clock * factor_n / div_m / div_p; + clock_str = "PLL_CPU_L"; + break; + case 4://PERI0PLL_DIV2 + reg_val = read32(SUNXI_CCU_BASE + PLL_PERI0_CTRL_REG); + factor_n = ((reg_val >> 8) & 0xff) + 1; + div_p = ((reg_val >> 20) & 0x3) + 1; + clock = 24 * factor_n / div_p; + clock_str = "PLL_PERI0(DIV2)"; + break; + default: + clock = clk_hosc; + clock_str = "HOSC"; + break; + } + printk_debug("CLK: PLL %s SRC=%s FREQ=%luMHz\r\n", name, clock_str, clock / 1000000); +} + +static inline void sunxi_peri_clk_dump(uint32_t addr, char *name, uint8_t pll_div) { + uint32_t reg_val; + uint32_t clk_src; + uint32_t factor_n, div_m, div_m1; + uint8_t div_p; + uint32_t clock = 0; + char *clock_str; + + reg_val = readl(addr); + clk_src = (reg_val >> 24) & 0x3; + div_m = ((reg_val >> 0) & 0x1f) + 1; + + switch (clk_src) { + case 0://OSC24M + clock = 24; + clock_str = "HOSC"; + break; + case 1://CCU_32K + clock = 32 / 1000; + clock_str = "32K"; + break; + case 2://RC16M + clock = 16; + clock_str = "RC16M"; + break; + case 3://PLL_PERI0(600M) + clock = sunxi_clk_get_peri1x_rate() / pll_div; + clock_str = "PLL_PERI0"; + break; + } + + clock = clock / div_m; + printk_debug("CLK: PLL %s SRC=%s FREQ=%luMHz\r\n", name, clock_str, clock / 1000000); +} + +void sunxi_clk_dump(void) { + uint32_t reg_val; + uint32_t clk_src; + uint32_t factor_n, div_m, div_m1; + uint8_t div_p; + uint32_t clock = 0, clk_hosc; + char *clock_str; + + clk_hosc = sunxi_clk_get_hosc_type() * 1000000; + printk_debug("CLK: PLL HOSC Type = %dMHz\n", clk_hosc / 1000000); + + sunxi_cpu_clk_dump(CCU_PLL_CPU_L_CLK_REG, CCU_PLL_CPU_L_CTRL_REG, "CPUL", clk_hosc); + sunxi_cpu_clk_dump(CCU_PLL_CPU_B_CLK_REG, CCU_PLL_CPU_B_CTRL_REG, "CPUB", clk_hosc); + + + reg_val = read32(SUNXI_CCU_BASE + PLL_DDR_CTRL_REG); + factor_n = ((reg_val >> 8) & 0xff) + 1; + div_m = ((reg_val >> 1) & 0x01) + 1; + div_m1 = ((reg_val >> 0) & 0x01) + 1; + printk_debug("CLK: PLL DDR FREQ=%luMHz\r\n", 24 * factor_n / div_m / div_m1); + + printk_debug("CLK: PLL PERI FREQ=%luMHz\r\n", sunxi_clk_get_peri1x_rate() / 1000000); + + sunxi_peri_clk_dump(SUNXI_CCU_BASE + AHB_CLK_REG, "AHB ", 2); + sunxi_peri_clk_dump(SUNXI_CCU_BASE + APB0_CLK_REG, "APB0", 2); + sunxi_peri_clk_dump(SUNXI_CCU_BASE + APB1_CLK_REG, "APB1", 1); +} diff --git a/src/drivers/chips/sun60iw2/sys-dram.c b/src/drivers/chips/sun60iw2/sys-dram.c new file mode 100644 index 000000000..0755cfb74 --- /dev/null +++ b/src/drivers/chips/sun60iw2/sys-dram.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#define INIT_DRAM_BIN_BASE 0x07280000 + +extern uint8_t __ddr_bin_start[]; +extern uint8_t __ddr_bin_end[]; + +uint32_t sunxi_dram_init(void *para) { + uint8_t *src = __ddr_bin_start; + uint8_t *dst = (uint8_t *) INIT_DRAM_BIN_BASE; + + if (para == NULL) { + printk_error("DRAM: please provide DRAM para\n"); + } + + uint32_t *para_data = (uint32_t *) para; + + /* Set DRAM driver clk and training data to */ + if (para_data[0] != 0x0) { + rtc_set_dram_para((uint32_t) para); + } + + printk_debug("DRAM: load dram init from 0x%08x -> 0x%08x size: %08x\n", src, dst, __ddr_bin_end - __ddr_bin_start); + memcpy(dst, src, __ddr_bin_end - __ddr_bin_start); + + /* Set RTC data to current time_ms(), Save in RTC_FEL_INDEX */ + rtc_set_start_time_ms(); + + printk_debug("DRAM: Now jump to 0x%08x run DRAMINIT\n", dst); + + __asm__ __volatile__("isb sy" + : + : + : "memory"); + __asm__ __volatile__("dsb sy" + : + : + : "memory"); + __asm__ __volatile__("dmb sy" + : + : + : "memory"); + ((void (*)(void))((void *) INIT_DRAM_BIN_BASE))(); + + uint32_t dram_size = rtc_read_data(RTC_FEL_INDEX); + + /* And Restore RTC Flag */ + rtc_clear_fel_flag(); + + return dram_size; +} diff --git a/src/drivers/chips/sun60iw2/sys-rproc.c b/src/drivers/chips/sun60iw2/sys-rproc.c new file mode 100644 index 000000000..e0ea51071 --- /dev/null +++ b/src/drivers/chips/sun60iw2/sys-rproc.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include diff --git a/src/drivers/chips/sun60iw2/sys-sdhci.c b/src/drivers/chips/sun60iw2/sys-sdhci.c new file mode 100644 index 000000000..0c691d2d2 --- /dev/null +++ b/src/drivers/chips/sun60iw2/sys-sdhci.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { + uint32_t reg_val = 0x0, sclk_hz = 0x0, div = 0x0; + + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + if (clk_hz <= 4000000) { + clk.clk_sel = 0; + sclk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; /* use hosc clk */ + } else { + if (clk.clk_sel && clk.parent_clk) { + sclk_hz = clk.parent_clk; + } else { + clk.clk_sel = 1; + sclk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; /* use 2x pll-per0 clock */ + } + } + + div = (2 * sclk_hz + clk_hz) / (2 * clk_hz); + div = (div == 0) ? 1 : div; + + if (div > 128) { + clk.factor_m = 1; + clk.factor_n = 0; + printk_warning("SMHC: Source clk is too high.\n"); + } else if (div > 64) { + clk.factor_n = 3; + clk.factor_m = div >> 3; + } else if (div > 32) { + clk.factor_n = 2; + clk.factor_m = div >> 2; + } else if (div > 16) { + clk.factor_n = 1; + clk.factor_m = div >> 1; + } else { + clk.factor_n = 0; + clk.factor_m = div; + } + + reg_val = BIT(31) | (clk.clk_sel << 24) | ((clk.factor_n) << clk.reg_factor_n_offset) | + ((clk.factor_m - 1) << clk.reg_factor_m_offset); + + writel(reg_val, clk.reg_base); + + printk_trace("SMHC: sdhci%d clk want %uHz parent %uHz, mclk=0x%08x clk_sel=%u, div=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, + clk.factor_n, clk.factor_m); + return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t clk_hz = 0x0; + uint32_t reg_val = 0x0; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + // Read the clock register value + reg_val = readl(clk.reg_base); + + // Extract the divider values and clock source from the register value + clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; + clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; + + // check clk sel, check if correct + if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { + clk.clk_sel = ((reg_val >> 24) & 0x3); + } + + // Calculate the current clock frequency based on the source and divider values + switch (clk.clk_sel) { + case 0: + clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; + break; + case 1: + if (clk.parent_clk && clk.clk_sel) { + clk_hz = clk.parent_clk; + } else { + clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; + } + break; + default: + printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); + break; + } + + printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); +} \ No newline at end of file diff --git a/src/drivers/chips/sun60iw2/sys-sid.c b/src/drivers/chips/sun60iw2/sys-sid.c new file mode 100644 index 000000000..b9d24c8dc --- /dev/null +++ b/src/drivers/chips/sun60iw2/sys-sid.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "sys-sid.h" diff --git a/src/drivers/chips/sun60iw2/sys-wdt.c b/src/drivers/chips/sun60iw2/sys-wdt.c new file mode 100644 index 000000000..b1e3f617d --- /dev/null +++ b/src/drivers/chips/sun60iw2/sys-wdt.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + diff --git a/src/drivers/chips/sun8iw20/sys-clk.c b/src/drivers/chips/sun8iw20/sys-clk.c index d5c729ba8..e8e95d44a 100644 --- a/src/drivers/chips/sun8iw20/sys-clk.c +++ b/src/drivers/chips/sun8iw20/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun8iw20/sys-rproc.c b/src/drivers/chips/sun8iw20/sys-rproc.c index 092a9069d..961d1ca9c 100644 --- a/src/drivers/chips/sun8iw20/sys-rproc.c +++ b/src/drivers/chips/sun8iw20/sys-rproc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun8iw20/sys-sdhci.c b/src/drivers/chips/sun8iw20/sys-sdhci.c new file mode 100644 index 000000000..0c691d2d2 --- /dev/null +++ b/src/drivers/chips/sun8iw20/sys-sdhci.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { + uint32_t reg_val = 0x0, sclk_hz = 0x0, div = 0x0; + + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + if (clk_hz <= 4000000) { + clk.clk_sel = 0; + sclk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; /* use hosc clk */ + } else { + if (clk.clk_sel && clk.parent_clk) { + sclk_hz = clk.parent_clk; + } else { + clk.clk_sel = 1; + sclk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; /* use 2x pll-per0 clock */ + } + } + + div = (2 * sclk_hz + clk_hz) / (2 * clk_hz); + div = (div == 0) ? 1 : div; + + if (div > 128) { + clk.factor_m = 1; + clk.factor_n = 0; + printk_warning("SMHC: Source clk is too high.\n"); + } else if (div > 64) { + clk.factor_n = 3; + clk.factor_m = div >> 3; + } else if (div > 32) { + clk.factor_n = 2; + clk.factor_m = div >> 2; + } else if (div > 16) { + clk.factor_n = 1; + clk.factor_m = div >> 1; + } else { + clk.factor_n = 0; + clk.factor_m = div; + } + + reg_val = BIT(31) | (clk.clk_sel << 24) | ((clk.factor_n) << clk.reg_factor_n_offset) | + ((clk.factor_m - 1) << clk.reg_factor_m_offset); + + writel(reg_val, clk.reg_base); + + printk_trace("SMHC: sdhci%d clk want %uHz parent %uHz, mclk=0x%08x clk_sel=%u, div=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, + clk.factor_n, clk.factor_m); + return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t clk_hz = 0x0; + uint32_t reg_val = 0x0; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + // Read the clock register value + reg_val = readl(clk.reg_base); + + // Extract the divider values and clock source from the register value + clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; + clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; + + // check clk sel, check if correct + if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { + clk.clk_sel = ((reg_val >> 24) & 0x3); + } + + // Calculate the current clock frequency based on the source and divider values + switch (clk.clk_sel) { + case 0: + clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; + break; + case 1: + if (clk.parent_clk && clk.clk_sel) { + clk_hz = clk.parent_clk; + } else { + clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; + } + break; + default: + printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); + break; + } + + printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); +} \ No newline at end of file diff --git a/src/drivers/chips/sun8iw20/sys-sid.c b/src/drivers/chips/sun8iw20/sys-sid.c index ed05c8e46..0051679a5 100644 --- a/src/drivers/chips/sun8iw20/sys-sid.c +++ b/src/drivers/chips/sun8iw20/sys-sid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun8iw20/sys-wdt.c b/src/drivers/chips/sun8iw20/sys-wdt.c index 4bce8b1fb..a827b79b9 100644 --- a/src/drivers/chips/sun8iw20/sys-wdt.c +++ b/src/drivers/chips/sun8iw20/sys-wdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun8iw21/sys-clk.c b/src/drivers/chips/sun8iw21/sys-clk.c index ccedd7e29..812adb83b 100644 --- a/src/drivers/chips/sun8iw21/sys-clk.c +++ b/src/drivers/chips/sun8iw21/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun8iw21/sys-rproc.c b/src/drivers/chips/sun8iw21/sys-rproc.c index 33d702490..1327ac58a 100644 --- a/src/drivers/chips/sun8iw21/sys-rproc.c +++ b/src/drivers/chips/sun8iw21/sys-rproc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun8iw21/sys-sdhci.c b/src/drivers/chips/sun8iw21/sys-sdhci.c new file mode 100644 index 000000000..0c691d2d2 --- /dev/null +++ b/src/drivers/chips/sun8iw21/sys-sdhci.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { + uint32_t reg_val = 0x0, sclk_hz = 0x0, div = 0x0; + + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + if (clk_hz <= 4000000) { + clk.clk_sel = 0; + sclk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; /* use hosc clk */ + } else { + if (clk.clk_sel && clk.parent_clk) { + sclk_hz = clk.parent_clk; + } else { + clk.clk_sel = 1; + sclk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; /* use 2x pll-per0 clock */ + } + } + + div = (2 * sclk_hz + clk_hz) / (2 * clk_hz); + div = (div == 0) ? 1 : div; + + if (div > 128) { + clk.factor_m = 1; + clk.factor_n = 0; + printk_warning("SMHC: Source clk is too high.\n"); + } else if (div > 64) { + clk.factor_n = 3; + clk.factor_m = div >> 3; + } else if (div > 32) { + clk.factor_n = 2; + clk.factor_m = div >> 2; + } else if (div > 16) { + clk.factor_n = 1; + clk.factor_m = div >> 1; + } else { + clk.factor_n = 0; + clk.factor_m = div; + } + + reg_val = BIT(31) | (clk.clk_sel << 24) | ((clk.factor_n) << clk.reg_factor_n_offset) | + ((clk.factor_m - 1) << clk.reg_factor_m_offset); + + writel(reg_val, clk.reg_base); + + printk_trace("SMHC: sdhci%d clk want %uHz parent %uHz, mclk=0x%08x clk_sel=%u, div=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, + clk.factor_n, clk.factor_m); + return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t clk_hz = 0x0; + uint32_t reg_val = 0x0; + sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; + + // Read the clock register value + reg_val = readl(clk.reg_base); + + // Extract the divider values and clock source from the register value + clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; + clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; + + // check clk sel, check if correct + if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { + clk.clk_sel = ((reg_val >> 24) & 0x3); + } + + // Calculate the current clock frequency based on the source and divider values + switch (clk.clk_sel) { + case 0: + clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; + break; + case 1: + if (clk.parent_clk && clk.clk_sel) { + clk_hz = clk.parent_clk; + } else { + clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; + } + break; + default: + printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); + break; + } + + printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", + sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); +} \ No newline at end of file diff --git a/src/drivers/chips/sun8iw21/sys-sid.c b/src/drivers/chips/sun8iw21/sys-sid.c index 11dc34c98..461cd7b97 100644 --- a/src/drivers/chips/sun8iw21/sys-sid.c +++ b/src/drivers/chips/sun8iw21/sys-sid.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/chips/sun8iw21/sys-wdt.c b/src/drivers/chips/sun8iw21/sys-wdt.c index 4bce8b1fb..a827b79b9 100644 --- a/src/drivers/chips/sun8iw21/sys-wdt.c +++ b/src/drivers/chips/sun8iw21/sys-wdt.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/gpio/CMakeModule.cmake b/src/drivers/gpio/CMakeModule.cmake new file mode 100644 index 000000000..f065347e6 --- /dev/null +++ b/src/drivers/gpio/CMakeModule.cmake @@ -0,0 +1,9 @@ +if (CONFIG_CHIP_GPIO_V1) +set(DRIVER_GPIO gpio/sys-gpio-v1.c) +elseif(CONFIG_CHIP_GPIO_V2) +set(DRIVER_GPIO gpio/sys-gpio-v2.c) +elseif(CONFIG_CHIP_GPIO_V3) +set(DRIVER_GPIO gpio/sys-gpio-v3.c) +else() +set(DRIVER_GPIO gpio/sys-gpio-v2.c) +endif() \ No newline at end of file diff --git a/src/drivers/gpio/sys-gpio-v1.c b/src/drivers/gpio/sys-gpio-v1.c new file mode 100644 index 000000000..9203db45f --- /dev/null +++ b/src/drivers/gpio/sys-gpio-v1.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +enum { + GPIO_CFG0 = 0x00, + GPIO_CFG1 = 0x04, + GPIO_CFG2 = 0x08, + GPIO_CFG3 = 0x0c, + GPIO_DAT = 0x10, + GPIO_DRV0 = 0x14, + GPIO_DRV1 = 0x18, + GPIO_PUL0 = 0x1c, + GPIO_PUL1 = 0x20, + GPIO_OFFSET = 0x24, + GPIO_CFG_MASK = 0x7, + GPIO_DRV_MASK = 0x3, +}; + +/** + * @brief Extracts the port number from a GPIO pin. + * + * This inline function extracts the port number from the given GPIO pin number. + * + * @param pin The GPIO pin number. + * @return The port number. + */ +static inline uint32_t _port_num(gpio_t pin) { + return pin >> PIO_NUM_IO_BITS; +} + +/** + * @brief Gets the base address of the port register for a GPIO pin. + * + * This function calculates and returns the base address of the port register + * for the specified GPIO pin. + * + * @param pin The GPIO pin number. + * @return The base address of the port register. + */ +static uint32_t _port_base_get(gpio_t pin) { + uint32_t port = pin >> PIO_NUM_IO_BITS; + + /* PL PM PN in R_PIO */ + if (port >= GPIO_PORTL) { + return SUNXI_RPIO_BASE + (port - GPIO_PORTL) * GPIO_OFFSET; + } + /* PA PB PC PD PE PF PG PH PI PJ PK in PIO */ + return SUNXI_PIO_BASE + port * GPIO_OFFSET; +} + +/** + * @brief Extracts the pin number within a port from a GPIO pin. + * + * This inline function extracts the pin number within a port from the given + * GPIO pin number. + * + * @param pin The GPIO pin number. + * @return The pin number within a port. + */ +static inline uint32_t _pin_num(gpio_t pin) { + return (pin & ((1 << PIO_NUM_IO_BITS) - 1)); +} + +/** + * @brief Initializes a Sunxi GPIO pin with the specified configuration. + * + * This function initializes a Sunxi GPIO pin with the specified configuration. It sets + * the pin's configuration based on the provided parameters. + * + * @param pin The GPIO pin to initialize. + * @param cfg The configuration value for the GPIO pin. + */ +void sunxi_gpio_init(gpio_t pin, int cfg) { + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t addr; + uint32_t val; + + addr = port_addr + GPIO_CFG0 + ((pin_num >> 3) << 2); + val = read32(addr); + val &= ~(0xf << ((pin_num & 0x7) << 2)); + val |= ((cfg & GPIO_CFG_MASK) << ((pin_num & 0x7) << 2)); + write32(addr, val); + + printk_trace("GPIO: MUX pin = %d, num in bank = %d, addr = 0x%08x, val = 0x%08x, set cfg = %d\n", + pin, pin_num, addr, read32(addr), cfg); +} + +/** + * @brief Sets the value of a Sunxi GPIO pin. + * + * This function sets the value of a Sunxi GPIO pin to the specified value (0 or 1). + * + * @param pin The GPIO pin to set the value for. + * @param value The value to set (0 or 1). + */ +void sunxi_gpio_set_value(gpio_t pin, int value) { + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t val; + + val = read32(port_addr + GPIO_DAT); + val &= ~(1 << pin_num); + val |= (!!value) << pin_num; + write32(port_addr + GPIO_DAT, val); +} + +/** + * @brief Reads the value of a Sunxi GPIO pin. + * + * This function reads the current value of a Sunxi GPIO pin and returns it. + * + * @param pin The GPIO pin to read the value from. + * @return The value of the GPIO pin (0 or 1). + */ +int sunxi_gpio_read(gpio_t pin) { + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t val; + + val = read32(port_addr + GPIO_DAT); + return !!(val & (1 << pin_num)); +} + +/** + * @brief Sets the pull configuration of a Sunxi GPIO pin. + * + * This function sets the pull-up, pull-down, or no pull configuration for the specified GPIO pin. + * + * @param pin The GPIO pin to set the pull configuration for. + * @param pull The pull configuration to set (GPIO_PULL_UP, GPIO_PULL_DOWN, or GPIO_PULL_NONE). + */ +void sunxi_gpio_set_pull(gpio_t pin, enum gpio_pull_t pull) { + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t addr; + uint32_t val, v; + + switch (pull) { + case GPIO_PULL_UP: + v = 0x1; + break; + + case GPIO_PULL_DOWN: + v = 0x2; + break; + + case GPIO_PULL_NONE: + v = 0x0; + break; + + default: + v = 0x0; + break; + } + + addr = port_addr + GPIO_PUL0 + ((pin_num >> 4) << 2); + val = read32(addr); + val &= ~(0x3 << ((pin_num & 0xf) << 1)); + val |= (v << ((pin_num & 0xf) << 1)); + write32(addr, val); + + printk_trace("GPIO: PULL pin = %d, addr = 0x%08x, val = 0x%08x, set pull = %d\n", + pin, addr, read32(addr), v); +} + +/** + * @brief Sets the drive strength of a Sunxi GPIO pin. + * + * This function sets the drive strength for the specified GPIO pin. + * + * @param pin The GPIO pin to set the drive strength for. + * @param drv The drive strength value to set (GPIO_DRV_LOW, GPIO_DRV_MEDIUM, or GPIO_DRV_HIGH). + */ +void sunxi_gpio_set_drv(gpio_t pin, gpio_drv_t drv) { + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t addr; + uint32_t val; + + addr = port_addr + GPIO_DRV0 + ((pin_num >> 4) << 2); + val = read32(addr); + val &= ~(0x3 << ((pin_num & 0xf) << 1)); + val |= (drv << ((pin_num & 0xf) << 1)); + write32(addr, val); + + printk_trace("GPIO: DRV pin = %d, addr = 0x%08x, val = 0x%08x, set drv = %d\n", + pin, addr, read32(addr), drv); +} diff --git a/src/drivers/sys-gpio.c b/src/drivers/gpio/sys-gpio-v2.c similarity index 93% rename from src/drivers/sys-gpio.c rename to src/drivers/gpio/sys-gpio-v2.c index 923db7c91..e063eb828 100644 --- a/src/drivers/sys-gpio.c +++ b/src/drivers/gpio/sys-gpio-v2.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -12,22 +12,6 @@ #include #include -#if defined(CONFIG_CHIP_GPIO_V1) -enum { - GPIO_CFG0 = 0x00, - GPIO_CFG1 = 0x04, - GPIO_CFG2 = 0x08, - GPIO_CFG3 = 0x0c, - GPIO_DAT = 0x10, - GPIO_DRV0 = 0x14, - GPIO_DRV1 = 0x18, - GPIO_PUL0 = 0x1c, - GPIO_PUL1 = 0x20, - GPIO_OFFSET = 0x24, - GPIO_CFG_MASK = 0x7, - GPIO_DRV_MASK = 0x3, -}; -#else enum { GPIO_CFG0 = 0x00, GPIO_CFG1 = 0x04, @@ -44,7 +28,6 @@ enum { GPIO_CFG_MASK = 0xf, GPIO_DRV_MASK = 0x3, }; -#endif /** * @brief Extracts the port number from a GPIO pin. @@ -71,7 +54,7 @@ static uint32_t _port_base_get(gpio_t pin) { uint32_t port = pin >> PIO_NUM_IO_BITS; /* PL PM PN in R_PIO */ - if (port > 10) { + if (port >= GPIO_PORTL) { return SUNXI_RPIO_BASE + (port - GPIO_PORTL) * GPIO_OFFSET; } /* PA PB PC PD PE PF PG PH PI PJ PK in PIO */ diff --git a/src/drivers/gpio/sys-gpio-v3.c b/src/drivers/gpio/sys-gpio-v3.c new file mode 100644 index 000000000..f357ce027 --- /dev/null +++ b/src/drivers/gpio/sys-gpio-v3.c @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +enum { + GPIO_CFG0 = 0x80, + GPIO_CFG1 = 0x84, + GPIO_CFG2 = 0x88, + GPIO_CFG3 = 0x8c, + GPIO_DAT = 0x90, + GPIO_DAT_SET = 0x94, + GPIO_DAT_CLR = 0x98, + GPIO_DRV0 = 0xa0, + GPIO_DRV1 = 0xa4, + GPIO_DRV2 = 0xa8, + GPIO_DRV3 = 0xac, + GPIO_PUL0 = 0xb0, + GPIO_PUL1 = 0xb4, + GPIO_OFFSET = 0x80, + GPIO_CFG_MASK = 0xf, + GPIO_DRV_MASK = 0x3, + + R_GPIO_CFG0 = 0x00, + R_GPIO_CFG1 = 0x04, + R_GPIO_CFG2 = 0x08, + R_GPIO_CFG3 = 0x0c, + R_GPIO_DAT = 0x10, + R_GPIO_DAT_SET = 0x504, + R_GPIO_DAT_CLR = 0x508, + R_GPIO_DRV0 = 0x14, + R_GPIO_DRV1 = 0x18, + R_GPIO_DRV2 = 0x1c, + R_GPIO_DRV3 = 0x20, + R_GPIO_PUL0 = 0x24, + R_GPIO_PUL1 = 0x28, + R_GPIO_OFFSET = 0x30, + R_GPIO_CFG_MASK = 0xf, + R_GPIO_DRV_MASK = 0x3, +}; + +/** + * @brief Extracts the port number from a GPIO pin. + * + * This inline function extracts the port number from the given GPIO pin number. + * + * @param pin The GPIO pin number. + * @return The port number. + */ +static inline uint32_t _port_num(gpio_t pin) { + return pin >> PIO_NUM_IO_BITS; +} + +/** + * @brief Gets the base address of the port register for a GPIO pin. + * + * This function calculates and returns the base address of the port register + * for the specified GPIO pin. + * + * @param pin The GPIO pin number. + * @return The base address of the port register. + */ +static uint32_t _port_base_get(gpio_t pin) { + uint32_t port = pin >> PIO_NUM_IO_BITS; + + /* PL PM PN in R_PIO */ + if (port >= GPIO_PORTL) { + return SUNXI_RPIO_BASE + (port - GPIO_PORTL) * R_GPIO_OFFSET; + } + /* PA PB PC PD PE PF PG PH PI PJ PK in PIO */ + return SUNXI_PIO_BASE + port * GPIO_OFFSET; +} + +/** + * @brief Extracts the pin number within a port from a GPIO pin. + * + * This inline function extracts the pin number within a port from the given + * GPIO pin number. + * + * @param pin The GPIO pin number. + * @return The pin number within a port. + */ +static inline uint32_t _pin_num(gpio_t pin) { + return (pin & ((1 << PIO_NUM_IO_BITS) - 1)); +} + +/** + * @brief Initializes a Sunxi GPIO pin with the specified configuration. + * + * This function initializes a Sunxi GPIO pin with the specified configuration. It sets + * the pin's configuration based on the provided parameters. + * + * @param pin The GPIO pin to initialize. + * @param cfg The configuration value for the GPIO pin. + */ +void sunxi_gpio_init(gpio_t pin, int cfg) { + uint32_t port_type = _port_num(pin); + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t addr; + uint32_t val; + + if (port_type >= GPIO_PORTL) { + addr = port_addr + R_GPIO_CFG0 + ((pin_num >> 3) << 2); + val = read32(addr); + val &= ~(0xf << ((pin_num & 0x7) << 2)); + val |= ((cfg & R_GPIO_CFG_MASK) << ((pin_num & 0x7) << 2)); + write32(addr, val); + } else { + addr = port_addr + GPIO_CFG0 + ((pin_num >> 3) << 2); + val = read32(addr); + val &= ~(0xf << ((pin_num & 0x7) << 2)); + val |= ((cfg & GPIO_CFG_MASK) << ((pin_num & 0x7) << 2)); + write32(addr, val); + } + + printk_trace("GPIO: MUX pin = %d, num in bank = %d, addr = 0x%08x, val = 0x%08x, set cfg = %d\n", + pin, pin_num, addr, read32(addr), cfg); +} + +/** + * @brief Sets the value of a Sunxi GPIO pin. + * + * This function sets the value of a Sunxi GPIO pin to the specified value (0 or 1). + * + * @param pin The GPIO pin to set the value for. + * @param value The value to set (0 or 1). + */ +void sunxi_gpio_set_value(gpio_t pin, int value) { + uint32_t port_type = _port_num(pin); + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t val; + if (port_type >= GPIO_PORTL) { + val = read32(port_addr + R_GPIO_DAT); + val &= ~(1 << pin_num); + val |= (!!value) << pin_num; + write32(port_addr + R_GPIO_DAT, val); + } else { + val = read32(port_addr + GPIO_DAT); + val &= ~(1 << pin_num); + val |= (!!value) << pin_num; + write32(port_addr + GPIO_DAT, val); + } +} + +/** + * @brief Reads the value of a Sunxi GPIO pin. + * + * This function reads the current value of a Sunxi GPIO pin and returns it. + * + * @param pin The GPIO pin to read the value from. + * @return The value of the GPIO pin (0 or 1). + */ +int sunxi_gpio_read(gpio_t pin) { + uint32_t port_type = _port_num(pin); + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t val; + if (port_type >= GPIO_PORTL) { + val = read32(port_addr + R_GPIO_DAT); + return !!(val & (1 << pin_num)); + } else { + val = read32(port_addr + GPIO_DAT); + return !!(val & (1 << pin_num)); + } +} + +/** + * @brief Sets the pull configuration of a Sunxi GPIO pin. + * + * This function sets the pull-up, pull-down, or no pull configuration for the specified GPIO pin. + * + * @param pin The GPIO pin to set the pull configuration for. + * @param pull The pull configuration to set (GPIO_PULL_UP, GPIO_PULL_DOWN, or GPIO_PULL_NONE). + */ +void sunxi_gpio_set_pull(gpio_t pin, enum gpio_pull_t pull) { + uint32_t port_type = _port_num(pin); + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t addr; + uint32_t val, v; + + switch (pull) { + case GPIO_PULL_UP: + v = 0x1; + break; + + case GPIO_PULL_DOWN: + v = 0x2; + break; + + case GPIO_PULL_NONE: + v = 0x0; + break; + + default: + v = 0x0; + break; + } + + if (port_type >= GPIO_PORTL) { + addr = port_addr + R_GPIO_PUL0 + ((pin_num >> 4) << 2); + val = read32(addr); + val &= ~(0x3 << ((pin_num & 0xf) << 1)); + val |= (v << ((pin_num & 0xf) << 1)); + write32(addr, val); + } else { + addr = port_addr + GPIO_PUL0 + ((pin_num >> 4) << 2); + val = read32(addr); + val &= ~(0x3 << ((pin_num & 0xf) << 1)); + val |= (v << ((pin_num & 0xf) << 1)); + write32(addr, val); + } + + printk_trace("GPIO: PULL pin = %d, addr = 0x%08x, val = 0x%08x, set pull = %d\n", + pin, addr, read32(addr), v); +} + +/** + * @brief Sets the drive strength of a Sunxi GPIO pin. + * + * This function sets the drive strength for the specified GPIO pin. + * + * @param pin The GPIO pin to set the drive strength for. + * @param drv The drive strength value to set (GPIO_DRV_LOW, GPIO_DRV_MEDIUM, or GPIO_DRV_HIGH). + */ +void sunxi_gpio_set_drv(gpio_t pin, gpio_drv_t drv) { + uint32_t port_type = _port_num(pin); + uint32_t port_addr = _port_base_get(pin); + uint32_t pin_num = _pin_num(pin); + uint32_t addr; + uint32_t val; + + if (port_type >= GPIO_PORTL) { + addr = port_addr + R_GPIO_DRV0 + ((pin_num >> 4) << 2); + val = read32(addr); + val &= ~(0x3 << ((pin_num & 0xf) << 1)); + val |= (drv << ((pin_num & 0xf) << 1)); + write32(addr, val); + } else { + addr = port_addr + GPIO_DRV0 + ((pin_num >> 4) << 2); + val = read32(addr); + val &= ~(0x3 << ((pin_num & 0xf) << 1)); + val |= (drv << ((pin_num & 0xf) << 1)); + write32(addr, val); + } + + printk_trace("GPIO: DRV pin = %d, addr = 0x%08x, val = 0x%08x, set drv = %d\n", + pin, addr, read32(addr), drv); +} diff --git a/src/drivers/intc/CMakeModule.cmake b/src/drivers/intc/CMakeModule.cmake new file mode 100644 index 000000000..a082f0989 --- /dev/null +++ b/src/drivers/intc/CMakeModule.cmake @@ -0,0 +1,5 @@ +if (CONFIG_CHIP_GIC) +set(INTC_DRIVER + intc/sys-gic.c +) +endif() \ No newline at end of file diff --git a/src/drivers/sys-gic.c b/src/drivers/intc/sys-gic.c similarity index 99% rename from src/drivers/sys-gic.c rename to src/drivers/intc/sys-gic.c index 5a16cd494..e3004572b 100644 --- a/src/drivers/sys-gic.c +++ b/src/drivers/intc/sys-gic.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -12,7 +12,7 @@ #include -#include "sys-gic.h" +#include static irq_handler_t sunxi_int_handlers[GIC_IRQ_NUM]; diff --git a/src/drivers/mmc/CMakeModule.cmake b/src/drivers/mmc/CMakeModule.cmake new file mode 100644 index 000000000..b025fd485 --- /dev/null +++ b/src/drivers/mmc/CMakeModule.cmake @@ -0,0 +1,5 @@ +set(MMC_DRIVER + mmc/sys-mmc.c + mmc/sys-sdhci.c + mmc/sys-sdcard.c +) \ No newline at end of file diff --git a/src/drivers/mmc/sys-sdhci.c b/src/drivers/mmc/sys-sdhci.c index 20aa3289c..04804a589 100644 --- a/src/drivers/mmc/sys-sdhci.c +++ b/src/drivers/mmc/sys-sdhci.c @@ -201,113 +201,6 @@ static int sunxi_sdhci_get_timing_config(sunxi_sdhci_t *sdhci, uint32_t spd_md_i return ret; } -/** - * @brief Set the SDHC controller's clock frequency. - * - * This function sets the clock frequency for the specified SDHC controller. - * - * @param sdhci Pointer to the SDHC controller structure. - * @param clk_hz Desired clock frequency in Hertz. - * @return Returns 0 on success, -1 on failure. - */ -int __attribute__((weak)) sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { - uint32_t reg_val = 0x0, sclk_hz = 0x0, div = 0x0; - - sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; - - if (clk_hz <= 4000000) { - clk.clk_sel = 0; - sclk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; /* use hosc clk */ - } else { - if (clk.clk_sel && clk.parent_clk) { - sclk_hz = clk.parent_clk; - } else { - clk.clk_sel = 1; - sclk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; /* use 2x pll-per0 clock */ - } - } - - div = (2 * sclk_hz + clk_hz) / (2 * clk_hz); - div = (div == 0) ? 1 : div; - - if (div > 128) { - clk.factor_m = 1; - clk.factor_n = 0; - printk_warning("SMHC: Source clk is too high.\n"); - } else if (div > 64) { - clk.factor_n = 3; - clk.factor_m = div >> 3; - } else if (div > 32) { - clk.factor_n = 2; - clk.factor_m = div >> 2; - } else if (div > 16) { - clk.factor_n = 1; - clk.factor_m = div >> 1; - } else { - clk.factor_n = 0; - clk.factor_m = div; - } - - reg_val = BIT(31) | (clk.clk_sel << 24) | ((clk.factor_n) << clk.reg_factor_n_offset) | - ((clk.factor_m - 1) << clk.reg_factor_m_offset); - - writel(reg_val, clk.reg_base); - - printk_trace("SMHC: sdhci%d clk want %uHz parent %uHz, mclk=0x%08x clk_sel=%u, div=%u, n=%u, m=%u\n", - sdhci->id, clk_hz, sclk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, div, - clk.factor_n, clk.factor_m); - return 0; -} - -/** - * @brief Get the current clock frequency of the SDHC controller. - * - * This function retrieves the current clock frequency of the specified SDHC controller. - * - * @param sdhci Pointer to the SDHC controller structure. - * @return Current clock frequency in Hertz. - */ -uint32_t __attribute__((weak)) sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { - uint32_t clk_hz = 0x0; - uint32_t reg_val = 0x0; - sunxi_sdhci_clk_t clk = sdhci->sdhci_clk; - - // Read the clock register value - reg_val = readl(clk.reg_base); - - // Extract the divider values and clock source from the register value - clk.factor_m = (reg_val >> clk.reg_factor_m_offset) & 0xf; - clk.factor_n = (reg_val >> clk.reg_factor_n_offset) & 0x3; - - // check clk sel, check if correct - if (clk.clk_sel != ((reg_val >> 24) & 0x3)) { - clk.clk_sel = ((reg_val >> 24) & 0x3); - } - - // Calculate the current clock frequency based on the source and divider values - switch (clk.clk_sel) { - case 0: - clk_hz = sunxi_clk_get_hosc_type() * 1000 * 1000; - break; - case 1: - if (clk.parent_clk && clk.clk_sel) { - clk_hz = clk.parent_clk; - } else { - clk_hz = sunxi_clk_get_peri1x_rate() * 2 * 1000 * 1000; - } - break; - default: - printk_debug("SMHC: wrong clock source %u\n", clk.clk_sel); - break; - } - - printk_trace("SMHC: sdhci%d clk parent %uHz, mclk=0x%08x clk_sel=%u, n=%u, m=%u\n", - sdhci->id, clk_hz, readl(sdhci->sdhci_clk.reg_base), clk.clk_sel, clk.factor_n + 1, clk.factor_m + 1); - - // Calculate the actual clock frequency based on the divider values - return clk_hz / (clk.factor_n + 1) / (clk.factor_m + 1); -} - /** * @brief Configure delay for the Sunxi SD Host Controller * @@ -427,7 +320,7 @@ static int sunxi_sdhci_config_delay(sunxi_sdhci_t *sdhci, uint32_t spd_md_id, ui * @param clk Clock frequency. * @return 0 on success, -1 on failure. */ -int __attribute__((weak)) sunxi_sdhci_clock_mode(sunxi_sdhci_t *sdhci, uint32_t clk) { +int sunxi_sdhci_clock_mode(sunxi_sdhci_t *sdhci, uint32_t clk) { int ret = 0; uint32_t reg_val = 0x0; sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; diff --git a/src/drivers/mtd/CMakeModule.cmake b/src/drivers/mtd/CMakeModule.cmake new file mode 100644 index 000000000..dcfffd38f --- /dev/null +++ b/src/drivers/mtd/CMakeModule.cmake @@ -0,0 +1,4 @@ +set(MTD_DRIVER + mtd/sys-spi-nand.c + mtd/sys-spi-nor.c +) diff --git a/src/drivers/mtd/sys-spi-nand.c b/src/drivers/mtd/sys-spi-nand.c index 45fea3869..6921a97e3 100644 --- a/src/drivers/mtd/sys-spi-nand.c +++ b/src/drivers/mtd/sys-spi-nand.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -36,7 +36,6 @@ enum { OPCODE_RESET = 0xff, }; - /* Micron calls it "feature", Winbond "status". We'll call it config for simplicity. */ enum { @@ -308,7 +307,8 @@ static int spi_nand_set_config(sunxi_spi_t *spi, uint8_t addr, uint8_t val) { * * @param spi Pointer to the sunxi_spi_t structure. */ -static void spi_nand_wait_while_busy(sunxi_spi_t *spi) { +static bool spi_nand_wait_while_busy(sunxi_spi_t *spi) { + uint32_t timeout = 0xffff; uint8_t tx[2]; /* Transmit buffer */ uint8_t rx[1]; /* Receive buffer */ int r; /* Return value */ @@ -321,7 +321,14 @@ static void spi_nand_wait_while_busy(sunxi_spi_t *spi) { r = sunxi_spi_transfer(spi, SPI_IO_SINGLE, tx, 2, rx, 1); /* Perform SPI transfer */ if (r < 0) break; + timeout--; + if (!timeout) { + printk_warning("SPI NAND: wait busy timeout\n"); + return false; + } } while ((rx[0] & 0x1) == 0x1); /* Check SR3 Busy bit */ + + return true; } /** @@ -334,7 +341,8 @@ int spi_nand_detect(sunxi_spi_t *spi) { uint8_t val; /* Configuration value */ spi_nand_reset(spi); - spi_nand_wait_while_busy(spi); + if(!spi_nand_wait_while_busy(spi)) + return -1; if (spi_nand_info(spi) == 0) { if ((spi_nand_get_config(spi, CONFIG_ADDR_PROTECT, &val) == 0) && (val != 0x0)) { @@ -352,7 +360,8 @@ int spi_nand_detect(sunxi_spi_t *spi) { } if (info.id.mfr == (uint8_t) SPI_NAND_MFR_GIGADEVICE || - info.id.mfr == (uint8_t) SPI_NAND_MFR_FORESEE) { + info.id.mfr == (uint8_t) SPI_NAND_MFR_FORESEE || + info.id.mfr == (uint8_t) SPI_NAND_MFR_XTX) { if ((spi_nand_get_config(spi, CONFIG_ADDR_OTP, &val) == 0) && !(val & 0x01)) { printk_debug("SPI-NAND: enable Quad mode\n"); val |= (1 << 0); @@ -437,7 +446,9 @@ uint32_t spi_nand_read(sunxi_spi_t *spi, uint8_t *buf, uint32_t addr, uint32_t r return -1; } - if (info.id.mfr == SPI_NAND_MFR_GIGADEVICE || info.id.mfr == SPI_NAND_MFR_FORESEE) { + if (info.id.mfr == SPI_NAND_MFR_GIGADEVICE || + info.id.mfr == SPI_NAND_MFR_FORESEE || + info.id.mfr == SPI_NAND_MFR_XTX) { while (cnt > 0) { ca = address & (info.page_size - 1); n = cnt > (info.page_size - ca) ? (info.page_size - ca) : cnt; diff --git a/src/drivers/mtd/sys-spi-nor.c b/src/drivers/mtd/sys-spi-nor.c index 81007a292..e671b7cea 100644 --- a/src/drivers/mtd/sys-spi-nor.c +++ b/src/drivers/mtd/sys-spi-nor.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -209,8 +209,14 @@ static inline void spi_nor_write_status_register(sunxi_spi_t *spi, uint8_t sr) { * @param spi Pointer to a `sunxi_spi_t` structure representing the SPI device. */ static inline void spi_nor_wait_for_busy(sunxi_spi_t *spi) { - while ((spi_nor_read_status_register(spi) & 0x1) == 0x1) - ; + uint32_t timeout = 0xffff; + while (((spi_nor_read_status_register(spi) & 0x1) == 0x1)) { + timeout--; + if (!timeout) { + printk_warning("SPI NAND: wait busy timeout\n"); + return; + } + } } /** diff --git a/src/drivers/pmu/CMakeModule.cmake b/src/drivers/pmu/CMakeModule.cmake new file mode 100644 index 000000000..d0f1b2c68 --- /dev/null +++ b/src/drivers/pmu/CMakeModule.cmake @@ -0,0 +1,9 @@ +if (CONFIG_CHIP_WITHPMU) + set(DRIVER_PMU + pmu/axp.c + pmu/axp1530.c + pmu/axp2101.c + pmu/axp2202.c + pmu/axp8191.c + ) +endif() \ No newline at end of file diff --git a/src/drivers/pmu/axp.c b/src/drivers/pmu/axp.c index ddf9c6583..9c46066b7 100644 --- a/src/drivers/pmu/axp.c +++ b/src/drivers/pmu/axp.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/pmu/axp1530.c b/src/drivers/pmu/axp1530.c index 8b50790a7..f462616f0 100644 --- a/src/drivers/pmu/axp1530.c +++ b/src/drivers/pmu/axp1530.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/pmu/axp2101.c b/src/drivers/pmu/axp2101.c index 4967dfc09..e8066bb6f 100644 --- a/src/drivers/pmu/axp2101.c +++ b/src/drivers/pmu/axp2101.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/pmu/axp2202.c b/src/drivers/pmu/axp2202.c index 869727c67..7c2973925 100644 --- a/src/drivers/pmu/axp2202.c +++ b/src/drivers/pmu/axp2202.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -69,27 +69,6 @@ static axp_contrl_info axp_ctrl_tbl[] = { }; /* clang-format on */ -/** - * Get control information from the table based on the given name. - * - * @param name The name of the control information to retrieve. - * @return A pointer to the axp_contrl_info structure corresponding to the given name, - * or NULL if the name is not found in the table. - */ -static axp_contrl_info *get_ctrl_info_from_tbl(char *name) { - int i = 0; - int size = ARRAY_SIZE(axp_ctrl_tbl); - for (i = 0; i < size; i++) { - if (!strncmp(name, axp_ctrl_tbl[i].name, strlen(axp_ctrl_tbl[i].name))) { - break; - } - } - if (i >= size) { - return NULL; - } - return (axp_ctrl_tbl + i); -} - int pmu_axp2202_init(sunxi_i2c_t *i2c_dev) { uint8_t axp_val; int ret; diff --git a/src/drivers/pmu/axp8191.c b/src/drivers/pmu/axp8191.c new file mode 100644 index 000000000..20716abb7 --- /dev/null +++ b/src/drivers/pmu/axp8191.c @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* clang-format off */ +static axp_contrl_info axp_ctrl_tbl[] = { + { "dcdc1", 1000, 3800, AXP8191_DC1OUT_VOL, 0x1f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 0, 0, + { {1000, 3800, 100}, } }, + + { "dcdc2", 500, 1540, AXP8191_DC2OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 1, 0, + { {500, 1200, 10}, {1220, 1540, 20}, } }, + + { "dcdc3", 500, 1540, AXP8191_DC3OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 2, 0, + { {500, 1200, 10}, {1220, 1540, 20}, } }, + + { "dcdc4", 500, 1540, AXP8191_DC4OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 3, 0, + { {500, 1200, 10}, {1220, 1540, 20}, } }, + + { "dcdc5", 500, 1540, AXP8191_DC5OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 4, 0, + { {500, 1200, 10}, {1220, 1540, 20}, {1800, 2400, 20}, {2440, 2760, 100}, } }, + + { "dcdc6", 500, 2760, AXP8191_DC6OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 5, 0, + { {500, 1200, 10}, {1220, 1540, 20}, {1800, 2400, 20}, {2440, 2760, 40}, } }, + + { "dcdc7", 500, 1840, AXP8191_DC7OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 6, 0, + { {500, 1200, 10}, {1220, 1840, 20} } }, + + { "dcdc8", 500, 3400, AXP8191_DC8OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL1, 7, 0, + { {500, 1200, 10}, {1220, 1540, 20}, {1900, 3400, 100}, } }, + + { "dcdc9", 500, 3400, AXP8191_DC9OUT_VOL, 0x7f, AXP8191_DCDC_POWER_ON_OFF_CTL2, 0, 0, + { {500, 1200, 10}, {1220, 1540, 20}, {1900, 3400, 100}, } }, + + { "aldo1", 500, 3400, AXP8191_ALDO1OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 0, 0, + { {500, 3400, 100}, } }, + + { "aldo2", 500, 3400, AXP8191_ALDO2OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 1, 0, + { {500, 3400, 100}, } }, + + { "aldo3", 500, 3400, AXP8191_ALDO3OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 2, 0, + { {500, 3400, 100}, } }, + + { "aldo4", 500, 3400, AXP8191_ALDO4OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 3, 0, + { {500, 3400, 100}, } }, + + { "aldo5", 500, 3400, AXP8191_ALDO5OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 4, 0, + { {500, 3400, 100}, } }, + + { "aldo6", 500, 3400, AXP8191_ALDO6OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 5, 0, + { {500, 3400, 100}, } }, + + { "bldo1", 500, 3400, AXP8191_BLDO1OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 6, 0, + { {500, 3400, 100}, } }, + + { "bldo2", 500, 3400, AXP8191_BLDO2OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL1, 7, 0, + { {500, 3400, 100}, } }, + + { "bldo3", 500, 3400, AXP8191_BLDO3OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 0, 0, + { {500, 3400, 100}, } }, + + { "bldo4", 500, 3400, AXP8191_BLDO4OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 1, 0, + { {500, 3400, 100}, } }, + + { "bldo5", 500, 3400, AXP8191_BLDO5OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 2, 0, + { {500, 3400, 100}, } }, + + { "cldo1", 500, 3400, AXP8191_CLDO1OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 3, 0, + { {500, 3400, 100}, } }, + + { "cldo2", 500, 3400, AXP8191_CLDO2OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 4, 0, + { {500, 3400, 100}, } }, + + { "cldo3", 500, 3400, AXP8191_CLDO3OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 5, 0, + { {500, 3400, 100}, } }, + + { "cldo4", 500, 3400, AXP8191_CLDO4OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 6, 0, + { {500, 3400, 100}, } }, + + { "cldo5", 500, 3400, AXP8191_CLDO5OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL2, 7, 0, + { {500, 3400, 100}, } }, + + { "dldo1", 500, 3400, AXP8191_DLDO1OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 0, 0, + { {500, 3400, 100}, } }, + + { "dldo2", 500, 3400, AXP8191_DLDO2OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 1, 0, + { {500, 3400, 100}, } }, + + { "dldo3", 500, 3400, AXP8191_DLDO3OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 2, 0, + { {500, 3400, 100}, } }, + + { "dldo4", 500, 3400, AXP8191_DLDO4OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 3, 0, + { {500, 3400, 100}, } }, + + { "dldo5", 500, 3400, AXP8191_DLDO5OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 4, 0, + { {500, 3400, 100}, } }, + + { "dldo5", 500, 3400, AXP8191_DLDO5OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 5, 0, + { {500, 3400, 100}, } }, + + { "eldo1", 500, 1500, AXP8191_ELDO1OUT_VOL, 0x3f, AXP8191_LDO_POWER_ON_OFF_CTL3, 6, 0, + { {500, 1500, 25}, } }, + + { "eldo2", 500, 1500, AXP8191_ELDO2OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 7, 0, + { {500, 1500, 100}, } }, + + { "eldo3", 500, 1500, AXP8191_ELDO3OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 0, 0, + { {500, 1500, 100}, } }, + + { "eldo4", 500, 1500, AXP8191_ELDO4OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL3, 1, 0, + { {500, 1500, 100}, } }, + + { "eldo5", 500, 1500, AXP8191_ELDO5OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL4, 2, 0, + { {500, 1500, 100}, } }, + + { "eldo5", 500, 1500, AXP8191_ELDO5OUT_VOL, 0x1f, AXP8191_LDO_POWER_ON_OFF_CTL4, 3, 0, + { {500, 1500, 100}, } }, +}; +/* clang-format on */ + +int pmu_axp8191_init(sunxi_i2c_t *i2c_dev) { + uint8_t axp_val; + int ret; + + if (!i2c_dev->status) { + printk_warning("PMU: I2C not init\n"); + return -1; + } + + if (ret = sunxi_i2c_read(i2c_dev, AXP8191_RUNTIME_ADDR, AXP8191_CHIP_ID, &axp_val)) { + printk_warning("PMU: Probe target device AXP8191 failed. ret = %d\n", ret); + return -1; + } + + if (axp_val == AXP8191_IC_TYPE) { + printk_info("PMU: Found AXP318W PMU, Addr 0x%02x\n", AXP8191_RUNTIME_ADDR); + } else { + printk_warning("PMU: AXP PMU Check error\n"); + return -1; + } + + sunxi_i2c_read(i2c_dev, AXP8191_DCDC_POWER_ON_OFF_CTL1, AXP8191_CHIP_ID, &axp_val); + axp_val |= 0x08; + sunxi_i2c_write(i2c_dev, AXP8191_DCDC_POWER_ON_OFF_CTL1, AXP8191_CHIP_ID, axp_val); + + /* enable dcdc2~dcdc9 dvm */ + for (int i = 0; i <= (AXP8191_DC9OUT_VOL - AXP8191_DC2OUT_VOL); i++) { + sunxi_i2c_read(i2c_dev, AXP8191_RUNTIME_ADDR, AXP8191_DC2OUT_VOL + i, &axp_val); + axp_val |= 0x80; + sunxi_i2c_write(i2c_dev, AXP8191_RUNTIME_ADDR, AXP8191_DC2OUT_VOL + i, axp_val); + } +} + +int pmu_axp8191_set_vol(sunxi_i2c_t *i2c_dev, char *name, int set_vol, int onoff) { + return axp_set_vol(i2c_dev, name, set_vol, onoff, axp_ctrl_tbl, ARRAY_SIZE(axp_ctrl_tbl), AXP8191_RUNTIME_ADDR); +} + +int pmu_axp8191_get_vol(sunxi_i2c_t *i2c_dev, char *name) { + return axp_get_vol(i2c_dev, name, axp_ctrl_tbl, ARRAY_SIZE(axp_ctrl_tbl), AXP8191_RUNTIME_ADDR); +} + +void pmu_axp8191_dump(sunxi_i2c_t *i2c_dev) { + for (int i = 0; i < ARRAY_SIZE(axp_ctrl_tbl); i++) { + printk_debug("PMU: axp8191 %s = %dmv\n", axp_ctrl_tbl[i].name, pmu_axp8191_get_vol(i2c_dev, axp_ctrl_tbl[i].name)); + } +} \ No newline at end of file diff --git a/src/drivers/sdhci/CMakeModule.cmake b/src/drivers/sdhci/CMakeModule.cmake new file mode 100644 index 000000000..03e001755 --- /dev/null +++ b/src/drivers/sdhci/CMakeModule.cmake @@ -0,0 +1,4 @@ +set(MMC_DRIVER + sdhci/sys-sdcard.c + sdhci/sys-sdhci.c +) diff --git a/src/drivers/sdhci/sys-sdcard.c b/src/drivers/sdhci/sys-sdcard.c index 5e53ab27e..c37d52c9e 100644 --- a/src/drivers/sdhci/sys-sdcard.c +++ b/src/drivers/sdhci/sys-sdcard.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/sdhci/sys-sdhci.c b/src/drivers/sdhci/sys-sdhci.c index 0095f2d7a..3e0483c9d 100644 --- a/src/drivers/sdhci/sys-sdhci.c +++ b/src/drivers/sdhci/sys-sdhci.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/sys-clk.c b/src/drivers/sys-clk.c index f31d31006..8f1b983ad 100644 --- a/src/drivers/sys-clk.c +++ b/src/drivers/sys-clk.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/sys-dma.c b/src/drivers/sys-dma.c index bb7a22bce..ac51a5f95 100644 --- a/src/drivers/sys-dma.c +++ b/src/drivers/sys-dma.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/sys-dram.c b/src/drivers/sys-dram.c index 6f5b3b1b1..409657c0b 100644 --- a/src/drivers/sys-dram.c +++ b/src/drivers/sys-dram.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/sys-i2c.c b/src/drivers/sys-i2c.c index 846dbe599..8908d9076 100644 --- a/src/drivers/sys-i2c.c +++ b/src/drivers/sys-i2c.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include @@ -537,8 +539,6 @@ static void sunxi_i2c_set_clock(sunxi_i2c_t *i2c_dev) { duty = TWI_CLK_DUTY; i2c->clk &= ~(duty); } - - printk_info("twi->clk %x\r\n", i2c->clk); } /** diff --git a/src/drivers/sys-rtc.c b/src/drivers/sys-rtc.c index 1f7dbc52e..e59dc98b9 100644 --- a/src/drivers/sys-rtc.c +++ b/src/drivers/sys-rtc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/drivers/sys-spi.c b/src/drivers/sys-spi.c index a6480f528..cda3fe8e2 100644 --- a/src/drivers/sys-spi.c +++ b/src/drivers/sys-spi.c @@ -1,6 +1,8 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ +#if LOG_LEVEL_DEFAULT <= LOG_LEVEL_DEBUG #define LOG_LEVEL_DEFAULT LOG_LEVEL_DEBUG +#endif #include #include diff --git a/src/drivers/sys-uart.c b/src/drivers/sys-uart.c index bc29b9dc7..b17cfb9af 100644 --- a/src/drivers/sys-uart.c +++ b/src/drivers/sys-uart.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/src/drivers/ufs/CMakeModule.cmake b/src/drivers/ufs/CMakeModule.cmake new file mode 100644 index 000000000..168a26da7 --- /dev/null +++ b/src/drivers/ufs/CMakeModule.cmake @@ -0,0 +1,5 @@ +if (CONFIG_CHIP_UFS) +set(UFS_DRIVER + ufs/ +) +endif() \ No newline at end of file diff --git a/src/drivers/ufs/scsi/scsi.c b/src/drivers/ufs/scsi/scsi.c new file mode 100644 index 000000000..e69de29bb diff --git a/src/drivers/ufs/ufs.c b/src/drivers/ufs/ufs.c new file mode 100644 index 000000000..e69de29bb diff --git a/src/drivers/usb/CMakeModule.cmake b/src/drivers/usb/CMakeModule.cmake new file mode 100644 index 000000000..7964535bf --- /dev/null +++ b/src/drivers/usb/CMakeModule.cmake @@ -0,0 +1,12 @@ +set(USB_DRIVER "") +if (CONFIG_CHIP_USB) +set(USB_DRIVER + usb/usb.c + usb/usb_controller.c + usb/usb_device.c + usb/usb_dma.c + + usb/module/usb_detect.c + usb/module/usb_mass.c +) +endif() \ No newline at end of file diff --git a/src/fdt_wrapper.c b/src/fdt_wrapper.c index ece4bd14d..7d1b0f7b9 100644 --- a/src/fdt_wrapper.c +++ b/src/fdt_wrapper.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include #include diff --git a/src/log/log.c b/src/log/log.c index 813d1b155..d942ad40b 100644 --- a/src/log/log.c +++ b/src/log/log.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include @@ -31,6 +31,8 @@ void printk(int level, const char *fmt, ...) { case LOG_LEVEL_ERROR: uart_printf("[%5lu.%06lu][\033[31mE\033[37m] ", seconds, milliseconds); break; + case LOG_LEVEL_BACKTRACE: + uart_printf("[%5lu.%06lu][\033[38;5;214mB\033[37m] ", seconds, milliseconds); case LOG_LEVEL_MUTE: default: break; diff --git a/src/os.c b/src/os.c index 47a236129..85696dd05 100644 --- a/src/os.c +++ b/src/os.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + #include #include #include diff --git a/src/smalloc.c b/src/smalloc.c index cd6ba1b3d..fe5e86d6b 100644 --- a/src/smalloc.c +++ b/src/smalloc.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/sstdlib.c b/src/sstdlib.c index f3e3e7d89..56de18312 100644 --- a/src/sstdlib.c +++ b/src/sstdlib.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/string.c b/src/string.c index c5dffa2e9..e516e60c6 100644 --- a/src/string.c +++ b/src/string.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/src/uart.c b/src/uart.c index ec9dd5d0c..b2b816553 100644 --- a/src/uart.c +++ b/src/uart.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/utils/bl33/include/linkage.h b/utils/bl33/include/linkage.h index f44139d35..b213f97b7 100644 --- a/utils/bl33/include/linkage.h +++ b/utils/bl33/include/linkage.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARM32_LINKAGE_H__ #define __ARM32_LINKAGE_H__ diff --git a/utils/bl33/source/string.c b/utils/bl33/source/string.c index 5bbacb135..b8ca1114a 100644 --- a/utils/bl33/source/string.c +++ b/utils/bl33/source/string.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/utils/bl33/source/timer.c b/utils/bl33/source/timer.c index 9a05a18da..141eace77 100644 --- a/utils/bl33/source/timer.c +++ b/utils/bl33/source/timer.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/utils/bl33_t527/include/linkage.h b/utils/bl33_t527/include/linkage.h index f44139d35..b213f97b7 100644 --- a/utils/bl33_t527/include/linkage.h +++ b/utils/bl33_t527/include/linkage.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ARM32_LINKAGE_H__ #define __ARM32_LINKAGE_H__ diff --git a/utils/bl33_t527/source/string.c b/utils/bl33_t527/source/string.c index 5bbacb135..b8ca1114a 100644 --- a/utils/bl33_t527/source/string.c +++ b/utils/bl33_t527/source/string.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/utils/bl33_t527/source/timer.c b/utils/bl33_t527/source/timer.c index 451466544..4bf1de1f6 100644 --- a/utils/bl33_t527/source/timer.c +++ b/utils/bl33_t527/source/timer.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include diff --git a/utils/driver-backup/sys-spi.c b/utils/driver-backup/sys-spi.c index a6ffafcee..b690b2c7f 100644 --- a/utils/driver-backup/sys-spi.c +++ b/utils/driver-backup/sys-spi.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ #include #include #include