From 0ea975e6e3969f4ca58130622e4f1600d0f5a8e6 Mon Sep 17 00:00:00 2001 From: James Gartrell Date: Thu, 16 Feb 2023 09:24:42 -0800 Subject: [PATCH 1/3] Add baseAddr function to HwPWM instance This allows for PWM configuration when direct register access is required. --- cores/nRF5/HardwarePWM.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/cores/nRF5/HardwarePWM.h b/cores/nRF5/HardwarePWM.h index 2002c8a1e..f85424d34 100644 --- a/cores/nRF5/HardwarePWM.h +++ b/cores/nRF5/HardwarePWM.h @@ -68,6 +68,12 @@ class HardwarePWM void setClockDiv(uint8_t div); // value is PWM_PRESCALER_PRESCALER_DIV_x, DIV1 is 16Mhz + // Direct access to peripheral base address + NRF_PWM_Type * const baseAddr(void) + { + return _pwm; + } + // Cooperative ownership sharing // returns true ONLY when (1) no PWM channel has a pin, and (2) the owner token is nullptr From a95d23e03a43a523b08d8bbfe3961ad07e7b845d Mon Sep 17 00:00:00 2001 From: James Gartrell Date: Thu, 16 Feb 2023 09:30:49 -0800 Subject: [PATCH 2/3] Add removeAllPins to HwPWM instance Given that no function exists to enumerate added pins, this allows for the HwPWM instance to be completely reset. --- cores/nRF5/HardwarePWM.cpp | 9 +++++++++ cores/nRF5/HardwarePWM.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/cores/nRF5/HardwarePWM.cpp b/cores/nRF5/HardwarePWM.cpp index d4d1d7715..cd8dc9dc8 100644 --- a/cores/nRF5/HardwarePWM.cpp +++ b/cores/nRF5/HardwarePWM.cpp @@ -205,6 +205,15 @@ bool HardwarePWM::removePin(uint8_t pin) return true; } +bool HardwarePWM::removeAllPins(void) +{ + for(int ch=0; ch Date: Fri, 23 Jun 2023 07:51:16 -0700 Subject: [PATCH 3/3] Remove baseAddr() since that could cause inconsistency when configured externally --- cores/nRF5/HardwarePWM.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/cores/nRF5/HardwarePWM.h b/cores/nRF5/HardwarePWM.h index d7de46c8d..dcf8fba5d 100644 --- a/cores/nRF5/HardwarePWM.h +++ b/cores/nRF5/HardwarePWM.h @@ -68,12 +68,6 @@ class HardwarePWM void setClockDiv(uint8_t div); // value is PWM_PRESCALER_PRESCALER_DIV_x, DIV1 is 16Mhz - // Direct access to peripheral base address - NRF_PWM_Type * const baseAddr(void) - { - return _pwm; - } - // Cooperative ownership sharing // returns true ONLY when (1) no PWM channel has a pin, and (2) the owner token is nullptr