src_files.yml

# Copyright 2020 ETH Zurich
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

cv32e40p_regfile_rtl:
  targets: [
    rtl,
    tsmc55,
    gf22,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./rtl/cv32e40p_register_file_latch.sv,
  ]

cv32e40p:
  vlog_opts: [
    -L fpnew_lib,
  ]
  incdirs: [
    ./rtl/include,
    ../../rtl/includes,
  ]
  files: [
    ./rtl/include/cv32e40p_apu_core_pkg.sv,
    ./rtl/include/cv32e40p_pkg.sv,
    ./bhv/include/cv32e40p_tracer_pkg.sv,
    ./rtl/cv32e40p_alu.sv,
    ./rtl/cv32e40p_alu_div.sv,
    ./rtl/cv32e40p_ff_one.sv,
    ./rtl/cv32e40p_popcnt.sv,
    ./rtl/cv32e40p_compressed_decoder.sv,
    ./rtl/cv32e40p_controller.sv,
    ./rtl/cv32e40p_cs_registers.sv,
    ./rtl/cv32e40p_decoder.sv,
    ./rtl/cv32e40p_int_controller.sv,
    ./rtl/cv32e40p_ex_stage.sv,
    ./rtl/cv32e40p_hwloop_regs.sv,
    ./rtl/cv32e40p_id_stage.sv,
    ./rtl/cv32e40p_if_stage.sv,
    ./rtl/cv32e40p_load_store_unit.sv,
    ./rtl/cv32e40p_mult.sv,
    ./rtl/cv32e40p_prefetch_buffer.sv,
    ./rtl/cv32e40p_prefetch_controller.sv,
    ./rtl/cv32e40p_obi_interface.sv,
    ./rtl/cv32e40p_aligner.sv,
    ./rtl/cv32e40p_sleep_unit.sv,
    ./rtl/cv32e40p_core.sv,
    ./rtl/cv32e40p_apu_disp.sv,
    ./rtl/cv32e40p_fifo.sv,
    ./rtl/cv32e40p_pmp.sv,
  ]

cv32e40p_vip_rtl:
  targets: [
    rtl,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./bhv/cv32e40p_sim_clock_gate.sv,
    ./bhv/cv32e40p_wrapper.sv,
    ./bhv/cv32e40p_tracer.sv,
    ./bhv/cv32e40p_core_log.sv,
    ./bhv/cv32e40p_apu_tracer.sv,
  ]
  defines: [
    CV32E40P_TRACE_EXECUTION,
    CV32E40P_APU_TRACE
  ]
  flags: [
    skip_synthesis,
  ]

cv32e40p_regfile_rtl:
  targets: [
    rtl,
    tsmc55,
    gf22,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./rtl/cv32e40p_register_file_latch.sv,
  ]

cv32e40p_regfile_verilator:
  targets: [
    verilator,
  ]
  files: [
    ./rtl/cv32e40p_register_file_ff.sv,
  ]
cv32e40p_regfile_fpga:
  targets: [
    xilinx,
  ]
  incdirs: [
    ./rtl/include,
  ]
  files: [
    ./rtl/cv32e40p_register_file_ff.sv,
  ]