diff --git a/llvm/lib/Target/SBF/AsmParser/SBFAsmParser.cpp b/llvm/lib/Target/SBF/AsmParser/SBFAsmParser.cpp index 927593a7492475..4d689b434534a8 100644 --- a/llvm/lib/Target/SBF/AsmParser/SBFAsmParser.cpp +++ b/llvm/lib/Target/SBF/AsmParser/SBFAsmParser.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/SBFMCTargetDesc.h" +#include "MCTargetDesc/SBFInstPrinter.h" #include "TargetInfo/SBFTargetInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -31,6 +32,10 @@ class SBFAsmParser : public MCTargetAsmParser { SMLoc getLoc() const { return getParser().getTok().getLoc(); } + bool isNewSyntax() { + return getParser().getAssemblerDialect() == 0; + } + bool PreMatchCheck(OperandVector &Operands); bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, @@ -45,21 +50,26 @@ class SBFAsmParser : public MCTargetAsmParser { bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; + bool parseOldInstruction(ParseInstructionInfo &Info, StringRef Name, + SMLoc NameLoc, OperandVector &Operands); + bool ParseDirective(AsmToken DirectiveID) override; - // "=" is used as assignment operator for assembly statment, so can't be used - // for symbol assignment. - bool equalIsAsmAssignment() override { return false; } + // "=" is used as assignment operator for assembly statement, so can't be used + // for symbol assignment (old syntax only). + bool equalIsAsmAssignment() override { return isNewSyntax(); } // "*" is used for dereferencing memory that it will be the start of - // statement. - bool starIsStartOfStatement() override { return true; } + // statement (old syntax only). + bool starIsStartOfStatement() override { return !isNewSyntax(); } #define GET_ASSEMBLER_HEADER #include "SBFGenAsmMatcher.inc" + bool parseOperand(OperandVector &Operands, StringRef Mnemonic); OperandMatchResultTy parseImmediate(OperandVector &Operands); OperandMatchResultTy parseRegister(OperandVector &Operands); OperandMatchResultTy parseOperandAsOperator(OperandVector &Operands); + OperandMatchResultTy parseMemOperand(OperandVector &Operands); public: enum SBFMatchResultTy { @@ -161,13 +171,20 @@ struct SBFOperand : public MCParsedAsmOperand { } void print(raw_ostream &OS) const override { + auto RegName = [](unsigned Reg) { + if (Reg) + return SBFInstPrinter::getRegisterName(Reg); + else + return "noreg"; + }; + switch (Kind) { case Immediate: OS << *getImm(); break; case Register: - OS << ""; + OS << ""; break; case Token: OS << "'" << getToken() << "'"; @@ -263,6 +280,10 @@ struct SBFOperand : public MCParsedAsmOperand { bool SBFAsmParser::PreMatchCheck(OperandVector &Operands) { + // These checks not needed for the new syntax. + if (isNewSyntax()) + return false; + if (Operands.size() == 4) { // check "reg1 = -reg2" and "reg1 = be16/be32/be64/le16/le32/le64 reg2", // reg1 must be the same as reg2 @@ -293,7 +314,9 @@ bool SBFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, if (PreMatchCheck(Operands)) return Error(IDLoc, "additional inst constraint not met"); - switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { + unsigned Dialect = getParser().getAssemblerDialect(); + switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm, + Dialect)) { default: break; case Match_Success: @@ -349,6 +372,9 @@ OperandMatchResultTy SBFAsmParser::tryParseRegister(unsigned &RegNo, OperandMatchResultTy SBFAsmParser::parseOperandAsOperator(OperandVector &Operands) { + if (isNewSyntax()) + llvm_unreachable("parseOperandAsOperator called for new syntax"); + SMLoc S = getLoc(); if (getLexer().getKind() == AsmToken::Identifier) { @@ -458,10 +484,108 @@ OperandMatchResultTy SBFAsmParser::parseImmediate(OperandVector &Operands) { return MatchOperand_Success; } -/// ParseInstruction - Parse an SBF instruction which is in SBF verifier -/// format. +OperandMatchResultTy SBFAsmParser::parseMemOperand(OperandVector &Operands) { + if (getLexer().isNot(AsmToken::LBrac)) { + return MatchOperand_ParseFail; + } + + getParser().Lex(); // Eat '['. + Operands.push_back(SBFOperand::createToken("[", getLoc())); + + if (parseRegister(Operands) != MatchOperand_Success) { + Error(getLoc(), "expected register"); + return MatchOperand_ParseFail; + } + + if (parseImmediate(Operands) != MatchOperand_Success) { + Error(getLoc(), "expected immediate offset"); + return MatchOperand_ParseFail; + } + + if (getLexer().isNot(AsmToken::RBrac)) { + Error(getLoc(), "expected ']'"); + return MatchOperand_ParseFail; + } + + getParser().Lex(); // Eat ']'. + Operands.push_back(SBFOperand::createToken("]", getLoc())); + + return MatchOperand_Success; +} + +/// Looks at a token type and creates the relevant operand from this +/// information, adding to Operands. If operand was parsed, returns false, else +/// true. +bool SBFAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { + if (!isNewSyntax()) + llvm_unreachable("parseOperand called for old syntax"); + + // Attempt to parse token as a register. + if (parseRegister(Operands) == MatchOperand_Success) + return false; + + // Attempt to parse token as an immediate. + if (parseImmediate(Operands) == MatchOperand_Success) { + return false; + } + + // Attempt to parse token sequence as a memory operand ("[reg+/-offset]"). + if (parseMemOperand(Operands) == MatchOperand_Success) { + return false; + } + + // Finally we have exhausted all options and must declare defeat. + Error(getLoc(), "unknown operand"); + return true; +} + +/// Parse an SBF instruction. bool SBFAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { + if (!isNewSyntax()) { + return parseOldInstruction(Info, Name, NameLoc, Operands); + } + + // First operand is token for instruction mnemonic. + Operands.push_back(SBFOperand::createToken(Name, NameLoc)); + + // If there are no more operands, then finish. + if (getLexer().is(AsmToken::EndOfStatement)) { + getParser().Lex(); // Consume the EndOfStatement. + return false; + } + + // Parse first operand. + if (parseOperand(Operands, Name)) + return true; + + // Parse until end of statement, consuming commas between operands. + while (getLexer().is(AsmToken::Comma)) { + // Consume comma token. + getLexer().Lex(); + + // Parse next operand. + if (parseOperand(Operands, Name)) + return true; + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + getParser().eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + + getParser().Lex(); // Consume the EndOfStatement. + return false; +} + +/// Parse an SBF instruction which is in SBF verifier format (old syntax). +bool SBFAsmParser::parseOldInstruction(ParseInstructionInfo &Info, + StringRef Name, SMLoc NameLoc, + OperandVector &Operands) { + if (isNewSyntax()) + llvm_unreachable("parseOldInstruction called for new syntax"); + // The first operand could be either register or actually an operator. unsigned RegNo = MatchRegisterName(Name); @@ -502,7 +626,24 @@ bool SBFAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, return false; } -bool SBFAsmParser::ParseDirective(AsmToken DirectiveID) { return true; } +bool SBFAsmParser::ParseDirective(AsmToken DirectiveID) { + // This returns false if this function recognizes the directive + // regardless of whether it is successfully handles or reports an + // error. Otherwise it returns true to give the generic parser a + // chance at recognizing it. + StringRef IDVal = DirectiveID.getString(); + + if (IDVal == ".syntax_old") { + getParser().setAssemblerDialect(1); + return false; + } + if (IDVal == ".syntax_new") { + getParser().setAssemblerDialect(0); + return false; + } + + return true; +} extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSBFAsmParser() { RegisterMCAsmParser XX(getTheSBFXTarget()); diff --git a/llvm/lib/Target/SBF/CMakeLists.txt b/llvm/lib/Target/SBF/CMakeLists.txt index cc8a9c7d1c0e9d..c7c1fc870f2fc6 100644 --- a/llvm/lib/Target/SBF/CMakeLists.txt +++ b/llvm/lib/Target/SBF/CMakeLists.txt @@ -4,6 +4,7 @@ set(LLVM_TARGET_DEFINITIONS SBF.td) tablegen(LLVM SBFGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM SBFGenAsmWriter.inc -gen-asm-writer) +tablegen(LLVM SBFGenAsmWriter1.inc -gen-asm-writer -asmwriternum=1) tablegen(LLVM SBFGenCallingConv.inc -gen-callingconv) tablegen(LLVM SBFGenDAGISel.inc -gen-dag-isel) tablegen(LLVM SBFGenDisassemblerTables.inc -gen-disassembler) diff --git a/llvm/lib/Target/SBF/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/SBF/MCTargetDesc/CMakeLists.txt index 23c8c21c548ee3..eec1732039fb42 100644 --- a/llvm/lib/Target/SBF/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/SBF/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ add_llvm_component_library(LLVMSBFDesc SBFMCTargetDesc.cpp SBFAsmBackend.cpp SBFInstPrinter.cpp + SBFMCAsmInfo.cpp SBFMCCodeEmitter.cpp SBFELFObjectWriter.cpp diff --git a/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp b/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp index cbd7e3abe592a4..1c81fa0e128ca3 100644 --- a/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp +++ b/llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp @@ -8,6 +8,7 @@ #include "MCTargetDesc/SBFMCTargetDesc.h" #include "llvm/BinaryFormat/ELF.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCObjectWriter.h" @@ -65,6 +66,10 @@ unsigned SBFELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, case FK_PCRel_4: // CALL instruction. return ELF::R_SBF_64_32; + case FK_PCRel_2: + // Branch instruction. + Ctx.reportError(Fixup.getLoc(), "2-byte relocations not supported"); + return ELF::R_SBF_NONE; case FK_Data_8: return (isSolana && !relocAbs64) ? ELF::R_SBF_64_64 : ELF::R_SBF_64_ABS64; case FK_Data_4: diff --git a/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.cpp b/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.cpp index c158bc31012903..5ecf2facc5448c 100644 --- a/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.cpp +++ b/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.cpp @@ -23,6 +23,7 @@ using namespace llvm; // Include the auto-generated portion of the assembly writer. #include "SBFGenAsmWriter.inc" +#include "SBFGenAsmWriter1.inc" void SBFInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, diff --git a/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.h b/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.h index 1f1e069e62d946..1cd4066e98119d 100644 --- a/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.h +++ b/llvm/lib/Target/SBF/MCTargetDesc/SBFInstPrinter.h @@ -36,6 +36,27 @@ class SBFInstPrinter : public MCInstPrinter { void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); }; + +class MachineInstr; + +class SBFLegacyInstPrinter : public SBFInstPrinter { +public: + SBFLegacyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MRI) + : SBFInstPrinter(MAI, MII, MRI) {} + + void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, + const MCSubtargetInfo &STI, raw_ostream &O) override { + printInstruction(MI, Address, O); + printAnnotation(O, Annot); + } + + // Autogenerated by tblgen. + std::pair getMnemonic(const MCInst *MI) override; + void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); + static const char *getRegisterName(unsigned RegNo); +}; + } #endif diff --git a/llvm/lib/Target/SBF/MCTargetDesc/SBFMCAsmInfo.cpp b/llvm/lib/Target/SBF/MCTargetDesc/SBFMCAsmInfo.cpp new file mode 100644 index 00000000000000..b62248c3151e96 --- /dev/null +++ b/llvm/lib/Target/SBF/MCTargetDesc/SBFMCAsmInfo.cpp @@ -0,0 +1,46 @@ +//===-- SBFMCAsmInfo.cpp - SBF Asm properties -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the declarations of the SBFMCAsmInfo properties. +// +//===----------------------------------------------------------------------===// + +#include "SBFMCAsmInfo.h" +#include "llvm/BinaryFormat/Dwarf.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/Support/CommandLine.h" + +using namespace llvm; + +cl::opt SBFAsmWriterVariant( + "sbf-output-asm-variant", cl::Hidden, cl::init(0), + cl::desc("Choose output assembly variant (0 = sbf[default], 1 = legacy)")); + +SBFMCAsmInfo::SBFMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { + AssemblerDialect = SBFAsmWriterVariant; + + PrivateGlobalPrefix = ".L"; + WeakRefDirective = "\t.weak\t"; + + UsesELFSectionDirectiveForBSS = true; + HasSingleParameterDotFile = true; + HasDotTypeDotSizeDirective = true; + + SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::DwarfCFI; + MinInstAlignment = 8; + + // The default is 4 and it only affects dwarf elf output. + // If not set correctly, the dwarf data will be + // messed up in random places by 4 bytes. .debug_line + // section will be parsable, but with odd offsets and + // line numbers, etc. + CodePointerSize = 8; + + UseIntegratedAssembler = false; +} diff --git a/llvm/lib/Target/SBF/MCTargetDesc/SBFMCAsmInfo.h b/llvm/lib/Target/SBF/MCTargetDesc/SBFMCAsmInfo.h index 08261d3aea67ef..fe884c622b2f2f 100644 --- a/llvm/lib/Target/SBF/MCTargetDesc/SBFMCAsmInfo.h +++ b/llvm/lib/Target/SBF/MCTargetDesc/SBFMCAsmInfo.h @@ -18,32 +18,10 @@ namespace llvm { +// TODO: This should likely be subclassing MCAsmInfoELF. class SBFMCAsmInfo : public MCAsmInfo { public: - explicit SBFMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { - if (TT.getArch() == Triple::bpfeb) - IsLittleEndian = false; - - PrivateGlobalPrefix = ".L"; - WeakRefDirective = "\t.weak\t"; - - UsesELFSectionDirectiveForBSS = true; - HasSingleParameterDotFile = true; - HasDotTypeDotSizeDirective = true; - - SupportsDebugInformation = true; - ExceptionsType = ExceptionHandling::DwarfCFI; - MinInstAlignment = 8; - - // the default is 4 and it only affects dwarf elf output - // so if not set correctly, the dwarf data will be - // messed up in random places by 4 bytes. .debug_line - // section will be parsable, but with odd offsets and - // line numbers, etc. - CodePointerSize = 8; - - UseIntegratedAssembler = false; - } + explicit SBFMCAsmInfo(const Triple &TT, const MCTargetOptions &Options); void setDwarfUsesRelocationsAcrossSections(bool enable) { DwarfUsesRelocationsAcrossSections = enable; @@ -53,6 +31,6 @@ class SBFMCAsmInfo : public MCAsmInfo { SupportsDebugInformation = enable; } }; -} +} #endif diff --git a/llvm/lib/Target/SBF/MCTargetDesc/SBFMCTargetDesc.cpp b/llvm/lib/Target/SBF/MCTargetDesc/SBFMCTargetDesc.cpp index 923d764efe5aa2..47c410ca11a713 100644 --- a/llvm/lib/Target/SBF/MCTargetDesc/SBFMCTargetDesc.cpp +++ b/llvm/lib/Target/SBF/MCTargetDesc/SBFMCTargetDesc.cpp @@ -81,6 +81,9 @@ static MCInstPrinter *createSBFMCInstPrinter(const Triple &T, const MCRegisterInfo &MRI) { if (SyntaxVariant == 0) return new SBFInstPrinter(MAI, MII, MRI); + if (SyntaxVariant == 1) + return new SBFLegacyInstPrinter(MAI, MII, MRI); + return nullptr; } diff --git a/llvm/lib/Target/SBF/SBF.td b/llvm/lib/Target/SBF/SBF.td index 4f0a45d0e6e2eb..ca4d689609e607 100644 --- a/llvm/lib/Target/SBF/SBF.td +++ b/llvm/lib/Target/SBF/SBF.td @@ -48,25 +48,50 @@ def : Proc<"v3", []>; def : Proc<"probe", []>; def : Proc<"sbfv2", [FeatureSolana, FeatureDynamicFrames, FeatureSdiv, FeatureRelocAbs64, FeatureStaticSyscalls]>; -def SBFInstPrinter : AsmWriter { +//===----------------------------------------------------------------------===// +// Assembly printer +//===----------------------------------------------------------------------===// + +def SBFAsmWriter : AsmWriter { string AsmWriterClassName = "InstPrinter"; + int Variant = 0; bit isMCAsmWriter = 1; } +def LegacyAsmWriter : AsmWriter { + let AsmWriterClassName = "LegacyInstPrinter"; + int Variant = 1; + int isMCAsmWriter = 1; +} + +//===----------------------------------------------------------------------===// +// Assembly parser +//===----------------------------------------------------------------------===// + def SBFAsmParser : AsmParser { bit HasMnemonicFirst = 0; } def SBFAsmParserVariant : AsmParserVariant { int Variant = 0; - string Name = "SBF"; + string Name = "sbf"; + string BreakCharacters = "."; +} + +def LegacyAsmParserVariant : AsmParserVariant { + int Variant = 1; + string Name = "legacy"; string BreakCharacters = "."; string TokenizingCharacters = "#()[]=:.<>!+*/"; } +//===----------------------------------------------------------------------===// +// Target Declaration +//===----------------------------------------------------------------------===// + def SBF : Target { let InstructionSet = SBFInstrInfo; - let AssemblyWriters = [SBFInstPrinter]; + let AssemblyWriters = [SBFAsmWriter, LegacyAsmWriter]; let AssemblyParsers = [SBFAsmParser]; - let AssemblyParserVariants = [SBFAsmParserVariant]; + let AssemblyParserVariants = [SBFAsmParserVariant, LegacyAsmParserVariant]; } diff --git a/llvm/lib/Target/SBF/SBFAsmPrinter.cpp b/llvm/lib/Target/SBF/SBFAsmPrinter.cpp index d9d58753fab277..52c5ef6580e042 100644 --- a/llvm/lib/Target/SBF/SBFAsmPrinter.cpp +++ b/llvm/lib/Target/SBF/SBFAsmPrinter.cpp @@ -34,6 +34,8 @@ using namespace llvm; #define DEBUG_TYPE "asm-printer" +extern cl::opt SBFAsmWriterVariant; + namespace { class SBFAsmPrinter : public AsmPrinter { public: @@ -132,10 +134,15 @@ bool SBFAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, if (ExtraCode) return true; // Unknown modifier. + if (SBFAsmWriterVariant == 1) + O << "("; + O << SBFInstPrinter::getRegisterName(BaseMO.getReg()); if (Offset < 0) - O << "(" << SBFInstPrinter::getRegisterName(BaseMO.getReg()) << " - " << -Offset << ")"; + O << " - " << -Offset; else - O << "(" << SBFInstPrinter::getRegisterName(BaseMO.getReg()) << " + " << Offset << ")"; + O << " + " << Offset; + if (SBFAsmWriterVariant == 1) + O << ")"; return false; } diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index 44a9abff447324..8fc42e2ae96350 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -155,11 +155,12 @@ class TYPE_LD_ST mode, bits<2> size, } // jump instructions -class JMP_RR +class JMP_RR : TYPE_ALU_JMP { bits<4> dst; bits<4> src; @@ -171,11 +172,12 @@ class JMP_RR let SBFClass = SBF_JMP; } -class JMP_RI +class JMP_RI : TYPE_ALU_JMP { bits<4> dst; bits<16> BrDst; @@ -187,11 +189,12 @@ class JMP_RI let SBFClass = SBF_JMP; } -class JMP_RR_32 +class JMP_RR_32 : TYPE_ALU_JMP { bits<4> dst; bits<4> src; @@ -203,11 +206,12 @@ class JMP_RR_32 let SBFClass = SBF_JMP32; } -class JMP_RI_32 +class JMP_RI_32 : TYPE_ALU_JMP { bits<4> dst; bits<16> BrDst; @@ -219,25 +223,26 @@ class JMP_RI_32 let SBFClass = SBF_JMP32; } -multiclass J { - def _rr : JMP_RR; - def _ri : JMP_RI; - def _rr_32 : JMP_RR_32; - def _ri_32 : JMP_RI_32; +multiclass J { + def _rr : JMP_RR; + def _ri : JMP_RI; + def _rr_32 : JMP_RR_32; + def _ri_32 : JMP_RI_32; } let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in { // cmp+goto instructions -defm JEQ : J; -defm JUGT : J", SBF_CC_GTU, SBF_CC_GTU_32>; -defm JUGE : J=", SBF_CC_GEU, SBF_CC_GEU_32>; -defm JNE : J", SBF_CC_GT, SBF_CC_GT_32>; -defm JSGE : J=", SBF_CC_GE, SBF_CC_GE_32>; -defm JULT : J; -defm JULE : J; -defm JSLE : J; +defm JUGT : J", SBF_CC_GTU, SBF_CC_GTU_32>; +defm JUGE : J=", SBF_CC_GEU, SBF_CC_GEU_32>; +defm JNE : J", SBF_CC_GT, SBF_CC_GT_32>; +defm JSGE : J=", SBF_CC_GE, SBF_CC_GE_32>; +defm JULT : J; +defm JULE : J; +defm JSLE : J; def _ri : ALU_RI; def _rr_32 : ALU_RR; def _ri_32 : ALU_RI; } let Constraints = "$dst = $src2" in { let isAsCheapAsAMove = 1 in { - defm ADD : ALU>=", srl>; - defm XOR : ALU>=", sra>; + defm ADD : ALU>=", srl>; + defm XOR : ALU>=", sra>; } - defm MUL : ALU; + defm MUL : ALU; let Predicates = [SBFSubtargetSolana] in { - defm SDIV : ALU; + defm SDIV : ALU; } } @@ -317,18 +327,19 @@ class NEG_RR; def NEG_32: NEG_RR; } -class LD_IMM64 Pseudo, string OpcodeStr> +class LD_IMM64 Pseudo, string Mnemonic, string OpcodeStr> : TYPE_LD_ST { bits<4> dst; @@ -342,26 +353,26 @@ class LD_IMM64 Pseudo, string OpcodeStr> } let isReMaterializable = 1, isAsCheapAsAMove = 1 in { -def LD_imm64 : LD_IMM64<0, "=">; +def LD_imm64 : LD_IMM64<0, "lddw", "=">; def MOV_rr : ALU_RR; def MOV_ri : ALU_RI; def MOV_rr_32 : ALU_RR; def MOV_ri_32 : ALU_RI; } @@ -399,11 +410,13 @@ def LD_pseudo } // STORE instructions -class STORE Pattern> +class STORE Pattern> : TYPE_LD_ST { bits<4> src; bits<20> addr; @@ -414,22 +427,25 @@ class STORE Pattern> let SBFClass = SBF_STX; } -class STOREi64 - : STORE; +class STOREi64 + : STORE; let Predicates = [SBFNoALU32] in { - def STW : STOREi64; - def STH : STOREi64; - def STB : STOREi64; + def STW : STOREi64; + def STH : STOREi64; + def STB : STOREi64; } -def STD : STOREi64; +def STD : STOREi64; // LOAD instructions -class LOAD Pattern> +class LOAD Pattern> : TYPE_LD_ST { bits<4> dst; bits<20> addr; @@ -440,8 +456,9 @@ class LOAD Pattern> let SBFClass = SBF_LDX; } -class LOADi64 - : LOAD; +class LOADi64 + : LOAD; let isCodeGenOnly = 1 in { def CORE_MEM : TYPE_LD_ST; - def LDH : LOADi64; - def LDB : LOADi64; + def LDW : LOADi64; + def LDH : LOADi64; + def LDB : LOADi64; } -def LDD : LOADi64; +def LDD : LOADi64; -class BRANCH Pattern> +class BRANCH Pattern> : TYPE_ALU_JMP { bits<16> BrDst; @@ -509,7 +528,7 @@ class CALLX // Jump always let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in { - def JMP : BRANCH; + def JMP : BRANCH; } // Jump and link @@ -624,11 +643,13 @@ let Predicates = [SBFNoALU32] in { } // Atomic XADD for SBFNoALU32 -class XADD +class XADD : TYPE_LD_ST { bits<4> dst; bits<20> addr; @@ -642,16 +663,17 @@ class XADD let Constraints = "$dst = $val" in { let Predicates = [SBFNoALU32] in { - def XADDW : XADD; + def XADDW : XADD; } } // Atomic add, and, or, xor -class ATOMIC_NOFETCH +class ATOMIC_NOFETCH : TYPE_LD_ST { bits<4> dst; bits<20> addr; @@ -663,11 +685,12 @@ class ATOMIC_NOFETCH let SBFClass = SBF_STX; } -class ATOMIC32_NOFETCH +class ATOMIC32_NOFETCH : TYPE_LD_ST { bits<4> dst; bits<20> addr; @@ -681,16 +704,16 @@ class ATOMIC32_NOFETCH let Constraints = "$dst = $val" in { let Predicates = [SBFHasALU32], DecoderNamespace = "SBFALU32" in { - def XADDW32 : ATOMIC32_NOFETCH; - def XANDW32 : ATOMIC32_NOFETCH; - def XORW32 : ATOMIC32_NOFETCH; - def XXORW32 : ATOMIC32_NOFETCH; + def XADDW32 : ATOMIC32_NOFETCH; + def XANDW32 : ATOMIC32_NOFETCH; + def XORW32 : ATOMIC32_NOFETCH; + def XXORW32 : ATOMIC32_NOFETCH; } - def XADDD : ATOMIC_NOFETCH; - def XANDD : ATOMIC_NOFETCH; - def XORD : ATOMIC_NOFETCH; - def XXORD : ATOMIC_NOFETCH; + def XADDD : ATOMIC_NOFETCH; + def XANDD : ATOMIC_NOFETCH; + def XORD : ATOMIC_NOFETCH; + def XXORD : ATOMIC_NOFETCH; } // Atomic Fetch-and- operations @@ -699,7 +722,8 @@ class XFALU64 { bits<4> dst; bits<20> addr; @@ -717,7 +741,8 @@ class XFALU32 { bits<4> dst; bits<20> addr; @@ -764,7 +789,8 @@ class XCHG : TYPE_LD_ST { bits<4> dst; bits<20> addr; @@ -781,7 +807,8 @@ class XCHG32 : TYPE_LD_ST { bits<4> dst; bits<20> addr; @@ -807,7 +834,8 @@ class CMPXCHG : TYPE_LD_ST { bits<4> new; bits<20> addr; @@ -824,7 +852,8 @@ class CMPXCHG32 : TYPE_LD_ST { bits<4> new; bits<20> addr; @@ -851,7 +880,8 @@ class BSWAP SizeOp, string OpcodeStr, SBFSrcType SrcType, list Pat : TYPE_ALU_JMP { bits<4> dst; @@ -876,11 +906,13 @@ let Constraints = "$dst = $src" in { let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1, hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in { -class LOAD_ABS +class LOAD_ABS : TYPE_LD_ST { bits<32> imm; @@ -888,11 +920,13 @@ class LOAD_ABS let SBFClass = SBF_LD; } -class LOAD_IND +class LOAD_IND : TYPE_LD_ST { bits<4> val; @@ -901,18 +935,18 @@ class LOAD_IND } } -def LD_ABS_B : LOAD_ABS; -def LD_ABS_H : LOAD_ABS; -def LD_ABS_W : LOAD_ABS; +def LD_ABS_B : LOAD_ABS; +def LD_ABS_H : LOAD_ABS; +def LD_ABS_W : LOAD_ABS; -def LD_IND_B : LOAD_IND; -def LD_IND_H : LOAD_IND; -def LD_IND_W : LOAD_IND; +def LD_IND_B : LOAD_IND; +def LD_IND_H : LOAD_IND; +def LD_IND_W : LOAD_IND; let isCodeGenOnly = 1 in { def MOV_32_64 : ALU_RR; + "{mov32 $dst, $src|$dst = $src}", []>; } def : Pat<(i64 (sext GPR32:$src)), @@ -928,11 +962,13 @@ def : Pat<(i32 (trunc GPR:$src)), def : Pat<(i64 (anyext GPR32:$src)), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; -class STORE32 Pattern> +class STORE32 Pattern> : TYPE_LD_ST { bits<4> src; bits<20> addr; @@ -943,20 +979,23 @@ class STORE32 Pattern> let SBFClass = SBF_STX; } -class STOREi32 - : STORE32; +class STOREi32 + : STORE32; let Predicates = [SBFHasALU32], DecoderNamespace = "SBFALU32" in { - def STW32 : STOREi32; - def STH32 : STOREi32; - def STB32 : STOREi32; + def STW32 : STOREi32; + def STH32 : STOREi32; + def STB32 : STOREi32; } -class LOAD32 Pattern> +class LOAD32 Pattern> : TYPE_LD_ST { bits<4> dst; bits<20> addr; @@ -967,13 +1006,14 @@ class LOAD32 Pattern> let SBFClass = SBF_LDX; } -class LOADi32 - : LOAD32; +class LOADi32 + : LOAD32; let Predicates = [SBFHasALU32], DecoderNamespace = "SBFALU32" in { - def LDW32 : LOADi32; - def LDH32 : LOADi32; - def LDB32 : LOADi32; + def LDW32 : LOADi32; + def LDH32 : LOADi32; + def LDB32 : LOADi32; } let Predicates = [SBFHasALU32] in { diff --git a/llvm/test/CodeGen/BPF/atomics_sbf.ll b/llvm/test/CodeGen/BPF/atomics_sbf.ll index 8e448e4aba13a2..cca1879d6b7538 100644 --- a/llvm/test/CodeGen/BPF/atomics_sbf.ll +++ b/llvm/test/CodeGen/BPF/atomics_sbf.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=sbf -mcpu=v3 -verify-machineinstrs | tee -i /tmp/log | FileCheck %s +; RUN: llc < %s -march=bpfel -mattr=+solana -mcpu=v3 -verify-machineinstrs | tee -i /tmp/log | FileCheck %s ; ; CHECK-LABEL: test_load_add_32 ; CHECK: w0 = *(u32 *)(r1 + 0) diff --git a/llvm/test/CodeGen/BPF/sdiv.ll b/llvm/test/CodeGen/BPF/sdiv.ll index 9a43614b01069f..2dadab49e9b270 100644 --- a/llvm/test/CodeGen/BPF/sdiv.ll +++ b/llvm/test/CodeGen/BPF/sdiv.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=bpf -mattr=+solana < %s | FileCheck %s -check-prefixes=CHECK-SBF -; RUN: llc -march=sbf < %s | FileCheck %s -check-prefixes=CHECK-SBF -; RUN: llc -march=sbf -mcpu=sbfv2 < %s | FileCheck %s -check-prefixes=CHECK-SBFV2 +; RUN: llc -march=bpfel -mattr=+solana < %s | FileCheck %s -check-prefixes=CHECK-SBF +; RUN: llc -march=bpfel -mattr=+solana -mcpu=sbfv2 < %s | FileCheck %s -check-prefixes=CHECK-SBFV2 ; Function Attrs: norecurse nounwind readnone define i32 @test(i32 %len) #0 { diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll index 30eafd6cbf2aab..17c13fa3215f11 100644 --- a/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll +++ b/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll @@ -120,21 +120,21 @@ define dso_local i32 @mov(i32 returned %a) local_unnamed_addr #0 { entry: ret i32 %a -; CHECK: w{{[0-9]+}} = w{{[0-9]+}} +; CHECK: mov32 w{{[0-9]+}}, w{{[0-9]+}} } ; Function Attrs: norecurse nounwind readnone define dso_local i32 @mov_ri() local_unnamed_addr #0 { entry: ret i32 255 -; CHECK: w{{[0-9]+}} = 255 +; CHECK: mov32 w{{[0-9]+}}, 255 } ; Function Attrs: norecurse nounwind readnone define dso_local i32 @add(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %add = add nsw i32 %b, %a -; CHECK: w{{[0-9]+}} += w{{[0-9]+}} +; CHECK: add32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %add } @@ -142,7 +142,7 @@ entry: define dso_local i32 @add_i(i32 %a) local_unnamed_addr #0 { entry: %add = add nsw i32 %a, 2147483647 -; CHECK: w{{[0-9]+}} += 2147483647 +; CHECK: add32 w{{[0-9]+}}, 2147483647 ret i32 %add } @@ -150,7 +150,7 @@ entry: define dso_local i32 @sub(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %sub = sub nsw i32 %a, %b -; CHECK: w{{[0-9]+}} -= w{{[0-9]+}} +; CHECK: sub32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %sub } @@ -158,7 +158,7 @@ entry: define dso_local i32 @sub_i(i32 %a) local_unnamed_addr #0 { entry: %sub = add i32 %a, 1 -; CHECK: w{{[0-9]+}} += 1 +; CHECK: add32 w{{[0-9]+}}, 1 ret i32 %sub } @@ -166,7 +166,7 @@ entry: define dso_local i32 @mul(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %mul = mul nsw i32 %b, %a -; CHECK: w{{[0-9]+}} *= w{{[0-9]+}} +; CHECK: mul32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %mul } @@ -174,7 +174,7 @@ entry: define dso_local i32 @mul_i(i32 %a) local_unnamed_addr #0 { entry: %mul = mul nsw i32 %a, 15 -; CHECK: w{{[0-9]+}} *= 15 +; CHECK: mul32 w{{[0-9]+}}, 15 ret i32 %mul } @@ -182,7 +182,7 @@ entry: define dso_local i32 @div(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %div = udiv i32 %a, %b -; CHECK: w{{[0-9]+}} /= w{{[0-9]+}} +; CHECK: div32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %div } @@ -190,7 +190,7 @@ entry: define dso_local i32 @div_i(i32 %a) local_unnamed_addr #0 { entry: %div = udiv i32 %a, 15 -; CHECK: w{{[0-9]+}} /= 15 +; CHECK: div32 w{{[0-9]+}}, 15 ret i32 %div } @@ -198,7 +198,7 @@ entry: define dso_local i32 @or(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %or = or i32 %b, %a -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: or32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %or } @@ -206,7 +206,7 @@ entry: define dso_local i32 @or_i(i32 %a) local_unnamed_addr #0 { entry: %or = or i32 %a, 255 -; CHECK: w{{[0-9]+}} |= 255 +; CHECK: or32 w{{[0-9]+}}, 255 ret i32 %or } @@ -214,7 +214,7 @@ entry: define dso_local i32 @xor(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %xor = xor i32 %b, %a -; CHECK: w{{[0-9]+}} ^= w{{[0-9]+}} +; CHECK: xor32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %xor } @@ -222,7 +222,7 @@ entry: define dso_local i32 @xor_i(i32 %a) local_unnamed_addr #0 { entry: %xor = xor i32 %a, 4095 -; CHECK: w{{[0-9]+}} ^= 4095 +; CHECK: xor32 w{{[0-9]+}}, 4095 ret i32 %xor } @@ -230,7 +230,7 @@ entry: define dso_local i32 @and(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %and = and i32 %b, %a -; CHECK: w{{[0-9]+}} &= w{{[0-9]+}} +; CHECK: and32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %and } @@ -238,7 +238,7 @@ entry: define dso_local i32 @and_i(i32 %a) local_unnamed_addr #0 { entry: %and = and i32 %a, 65535 -; CHECK: w{{[0-9]+}} &= 65535 +; CHECK: and32 w{{[0-9]+}}, 65535 ret i32 %and } @@ -246,7 +246,7 @@ entry: define dso_local i32 @sll(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %shl = shl i32 %a, %b -; CHECK: w{{[0-9]+}} <<= w{{[0-9]+}} +; CHECK: lsh32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %shl } @@ -254,7 +254,7 @@ entry: define dso_local i32 @sll_i(i32 %a) local_unnamed_addr #0 { entry: %shl = shl i32 %a, 17 -; CHECK: w{{[0-9]+}} <<= 17 +; CHECK: lsh32 w{{[0-9]+}}, 17 ret i32 %shl } @@ -262,7 +262,7 @@ entry: define dso_local i32 @srl(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %shr = lshr i32 %a, %b -; CHECK: w{{[0-9]+}} >>= w{{[0-9]+}} +; CHECK: rsh32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %shr } @@ -270,7 +270,7 @@ entry: define dso_local i32 @srl_i(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %shr = lshr i32 %a, 31 -; CHECK: w{{[0-9]+}} >>= 31 +; CHECK: rsh32 w{{[0-9]+}}, 31 ret i32 %shr } @@ -278,7 +278,7 @@ entry: define dso_local i32 @sra(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %shr = ashr i32 %a, %b -; CHECK: w{{[0-9]+}} s>>= w{{[0-9]+}} +; CHECK: arsh32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %shr } @@ -286,7 +286,7 @@ entry: define dso_local i32 @sra_i(i32 %a, i32 %b) local_unnamed_addr #0 { entry: %shr = ashr i32 %a, 7 -; CHECK: w{{[0-9]+}} s>>= 7 +; CHECK: arsh32 w{{[0-9]+}}, 7 ret i32 %shr } @@ -294,6 +294,6 @@ entry: define dso_local i32 @neg(i32 %a) local_unnamed_addr #0 { entry: %sub = sub nsw i32 0, %a -; CHECK: w{{[0-9]+}} = -w{{[0-9]+}} +; CHECK: mov32 w{{[0-9]+}}, w{{[0-9]+}} ret i32 %sub } diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-cond-select.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-cond-select.ll index 9076cda149a341..2ea3048a314e28 100644 --- a/llvm/test/CodeGen/SBF/32-bit-subreg-cond-select.ll +++ b/llvm/test/CodeGen/SBF/32-bit-subreg-cond-select.ll @@ -56,9 +56,9 @@ entry: ret i32 %c.d } ; CHECK-LABEL: select_cc_32 -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh64 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh64 r{{[0-9]+}}, 32 ; Function Attrs: norecurse nounwind readnone define dso_local i64 @select_cc_32_64(i32 %a, i32 %b, i64 %c, i64 %d) local_unnamed_addr #0 { @@ -68,9 +68,9 @@ entry: ret i64 %c.d } ; CHECK-LABEL: select_cc_32_64 -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh64 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh64 r{{[0-9]+}}, 32 ; Function Attrs: norecurse nounwind readnone define dso_local i32 @select_cc_64_32(i64 %a, i64 %b, i32 %c, i32 %d) local_unnamed_addr #0 { @@ -80,7 +80,7 @@ entry: ret i32 %c.d } ; CHECK-LABEL: select_cc_64_32 -; CHECK-NOT: r{{[0-9]+}} <<= 32 +; CHECK-NOT: lsh64 r{{[0-9]+}}, 32 ; Function Attrs: norecurse nounwind readnone define dso_local i32 @selecti_cc_32(i32 %a, i32 %c, i32 %d) local_unnamed_addr #0 { @@ -90,9 +90,9 @@ entry: ret i32 %c.d } ; CHECK-LABEL: selecti_cc_32 -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh64 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh64 r{{[0-9]+}}, 32 ; Function Attrs: norecurse nounwind readnone define dso_local i64 @selecti_cc_32_64(i32 %a, i64 %c, i64 %d) local_unnamed_addr #0 { @@ -102,9 +102,9 @@ entry: ret i64 %c.d } ; CHECK-LABEL: selecti_cc_32_64 -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh64 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh64 r{{[0-9]+}}, 32 ; Function Attrs: norecurse nounwind readnone define dso_local i32 @selecti_cc_64_32(i64 %a, i32 %c, i32 %d) local_unnamed_addr #0 { @@ -114,4 +114,4 @@ entry: ret i32 %c.d } ; CHECK-LABEL: selecti_cc_64_32 -; CHECK-NOT: r{{[0-9]+}} <<= 32 +; CHECK-NOT: lsh64 r{{[0-9]+}}, 32 diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-load-store.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-load-store.ll index 63645383dd06f4..e4fcde383c02f8 100644 --- a/llvm/test/CodeGen/SBF/32-bit-subreg-load-store.ll +++ b/llvm/test/CodeGen/SBF/32-bit-subreg-load-store.ll @@ -43,7 +43,7 @@ define dso_local zeroext i8 @loadu8(i8* nocapture readonly %p) local_unnamed_addr #0 { entry: %0 = load i8, i8* %p, align 1 -; CHECK: w{{[0-9]+}} = *(u8 *)(r{{[0-9]+}} + 0) +; CHECK: ldxb w{{[0-9]+}}, [r{{[0-9]+}} + 0] ret i8 %0 } @@ -51,7 +51,7 @@ entry: define dso_local zeroext i16 @loadu16(i16* nocapture readonly %p) local_unnamed_addr #0 { entry: %0 = load i16, i16* %p, align 2 -; CHECK: w{{[0-9]+}} = *(u16 *)(r{{[0-9]+}} + 0) +; CHECK: ldxh w{{[0-9]+}}, [r{{[0-9]+}} + 0] ret i16 %0 } @@ -59,7 +59,7 @@ entry: define dso_local i32 @loadu32(i32* nocapture readonly %p) local_unnamed_addr #0 { entry: %0 = load i32, i32* %p, align 4 -; CHECK: w{{[0-9]+}} = *(u32 *)(r{{[0-9]+}} + 0) +; CHECK: ldxw w{{[0-9]+}}, [r{{[0-9]+}} + 0] ret i32 %0 } @@ -67,7 +67,7 @@ entry: define dso_local i64 @loadu64(i64* nocapture readonly %p) local_unnamed_addr #0 { entry: %0 = load i64, i64* %p, align 8 -; CHECK: r{{[0-9]+}} = *(u64 *)(r{{[0-9]+}} + 0) +; CHECK: ldxdw r{{[0-9]+}}, [r{{[0-9]+}} + 0] ret i64 %0 } @@ -76,7 +76,7 @@ define dso_local void @storeu8(i8* nocapture %p, i64 %v) local_unnamed_addr #1 { entry: %conv = trunc i64 %v to i8 store i8 %conv, i8* %p, align 1 -; CHECK: *(u8 *)(r{{[0-9]+}} + 0) = w{{[0-9]+}} +; CHECK: stxb [r{{[0-9]+}} + 0], w{{[0-9]+}} ret void } @@ -85,7 +85,7 @@ define dso_local void @storeu16(i16* nocapture %p, i64 %v) local_unnamed_addr #1 entry: %conv = trunc i64 %v to i16 store i16 %conv, i16* %p, align 2 -; CHECK: *(u16 *)(r{{[0-9]+}} + 0) = w{{[0-9]+}} +; CHECK: stxh [r{{[0-9]+}} + 0], w{{[0-9]+}} ret void } @@ -94,7 +94,7 @@ define dso_local void @storeu32(i32* nocapture %p, i64 %v) local_unnamed_addr #1 entry: %conv = trunc i64 %v to i32 store i32 %conv, i32* %p, align 4 -; CHECK: *(u32 *)(r{{[0-9]+}} + 0) = w{{[0-9]+}} +; CHECK: stxw [r{{[0-9]+}} + 0], w{{[0-9]+}} ret void } @@ -102,6 +102,6 @@ entry: define dso_local void @storeu64(i64* nocapture %p, i64 %v) local_unnamed_addr #1 { entry: store i64 %v, i64* %p, align 8 -; CHECK: *(u64 *)(r{{[0-9]+}} + 0) = r{{[0-9]+}} +; CHECK: stxdw [r{{[0-9]+}} + 0], r{{[0-9]+}} ret void } diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-1.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-1.ll index 26012d19f0db23..701d30ccdeca08 100644 --- a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-1.ll +++ b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-1.ll @@ -27,8 +27,8 @@ entry: %call = tail call i32 @helper(i32 %conv) ret i32 %call } -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} >>= 32 -; CHECK: if r{{[0-9]+}} == r{{[0-9]+}} goto +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: rsh32 r{{[0-9]+}}, 32 +; CHECK: jeq r{{[0-9]+}}, r{{[0-9]+}}, declare dso_local i32 @helper(i32) local_unnamed_addr diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-2.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-2.ll index d8f301e70f247c..2fef555d3f4186 100644 --- a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-2.ll +++ b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-2.ll @@ -27,8 +27,8 @@ entry: %call = tail call i32 @helper(i32 %conv) ret i32 %call } -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK: if r{{[0-9]+}} == r{{[0-9]+}} goto +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK: jeq r{{[0-9]+}}, r{{[0-9]+}}, declare dso_local i32 @helper(i32) local_unnamed_addr diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-3.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-3.ll index 3c70c3940dcbc0..20d71af957fd16 100644 --- a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-3.ll +++ b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole-phi-3.ll @@ -44,10 +44,10 @@ for.body: ; preds = %for.body, %entry %exitcond = icmp eq i64 %inc, 100 br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !2 } -; CHECK: [[VAL:r[0-9]+]] = w{{[0-9]+}} -; CHECK-NOT: [[VAL:r[0-9]+]] <<= 32 -; CHECK-NOT: [[VAL]] >>= 32 -; CHECK: if [[VAL]] == 0 goto +; CHECK: mov32 [[VAL:r[0-9]+]], w{{[0-9]+}} +; CHECK-NOT: lsh32 [[VAL:r[0-9]+]], 32 +; CHECK-NOT: rsh32 [[VAL]], 32 +; CHECK: jeq [[VAL]], 0, !2 = distinct !{!2, !3} !3 = !{!"llvm.loop.unroll.disable"} diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole.ll index b5c7764f9150a9..6ade7e00390d0c 100644 --- a/llvm/test/CodeGen/SBF/32-bit-subreg-peephole.ll +++ b/llvm/test/CodeGen/SBF/32-bit-subreg-peephole.ll @@ -47,10 +47,10 @@ define dso_local i64 @select_u(i32 %a, i32 %b, i64 %c, i64 %d) local_unnamed_add entry: %cmp = icmp ugt i32 %a, %b %c.d = select i1 %cmp, i64 %c, i64 %d -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 -; CHECK: if r{{[0-9]+}} {{<|>}} r{{[0-9]+}} goto +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh32 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh32 r{{[0-9]+}}, 32 +; CHECK: {{jlt|jgt}} r{{[0-9]+}}, r{{[0-9]+}}, ret i64 %c.d } @@ -59,9 +59,9 @@ define dso_local i64 @select_u_2(i32 %a, i64 %b, i64 %c, i64 %d) local_unnamed_a ; CHECK-LABEL: select_u_2: entry: %conv = zext i32 %a to i64 -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh32 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh32 r{{[0-9]+}}, 32 %cmp = icmp ugt i64 %conv, %b %c.d = select i1 %cmp, i64 %c, i64 %d ret i64 %c.d @@ -73,9 +73,9 @@ define dso_local i64 @select_s(i32 %a, i32 %b, i64 %c, i64 %d) local_unnamed_add entry: %cmp = icmp sgt i32 %a, %b %c.d = select i1 %cmp, i64 %c, i64 %d -; CHECK: r{{[0-9]+}} <<= 32 -; CHECK-NEXT: r{{[0-9]+}} s>>= 32 -; CHECK: if r{{[0-9]+}} s{{<|>}} r{{[0-9]+}} goto +; CHECK: lsh64 r{{[0-9]+}}, 32 +; CHECK-NEXT: arsh64 r{{[0-9]+}}, 32 +; CHECK: {{jslt|jsgt}} r{{[0-9]+}}, r{{[0-9]+}}, ret i64 %c.d } @@ -88,11 +88,11 @@ entry: %cmp = icmp ult i32 %conv, 10 ; %call comes from function call returning i64 so the high bits will need ; to be cleared. -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh32 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh32 r{{[0-9]+}}, 32 %b.c = select i1 %cmp, i32 %b, i32 %c -; CHECK: if r{{[0-9]+}} {{<|>}} {{[0-9]+}} goto +; CHECK: {{jlt|jgt}} r{{[0-9]+}}, {{[0-9]+}}, ret i32 %b.c } @@ -103,9 +103,9 @@ define dso_local i32* @inc_p(i32* readnone %p, i32 %a) local_unnamed_addr #0 { ; CHECK-LABEL: inc_p: entry: %idx.ext = zext i32 %a to i64 -; CHECK: r{{[0-9]+}} = w{{[0-9]+}} -; CHECK-NOT: r{{[0-9]+}} <<= 32 -; CHECK-NOT: r{{[0-9]+}} >>= 32 +; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}} +; CHECK-NOT: lsh32 r{{[0-9]+}}, 32 +; CHECK-NOT: rsh32 r{{[0-9]+}}, 32 %add.ptr = getelementptr inbounds i32, i32* %p, i64 %idx.ext ret i32* %add.ptr } @@ -117,10 +117,10 @@ entry: %cmp = icmp sgt i32 %call, 6 ; The shifts can't be optimized out because %call comes from function call ; return i32 so the high bits might be invalid. -; CHECK: r{{[0-9]+}} <<= 32 -; CHECK-NEXT: r{{[0-9]+}} s>>= 32 +; CHECK: lsh64 r{{[0-9]+}}, 32 +; CHECK-NEXT: arsh64 r{{[0-9]+}}, 32 %cond = zext i1 %cmp to i32 -; CHECK: if r{{[0-9]+}} s{{<|>}} {{[0-9]+}} goto +; CHECK: {{jslt|jsgt}} r{{[0-9]+}}, {{[0-9]+}}, ret i32 %cond } declare dso_local i32 @helper(...) local_unnamed_addr diff --git a/llvm/test/CodeGen/SBF/adjust-opt-icmp1.ll b/llvm/test/CodeGen/SBF/adjust-opt-icmp1.ll index de28abf192b979..c71172f5872e6a 100644 --- a/llvm/test/CodeGen/SBF/adjust-opt-icmp1.ll +++ b/llvm/test/CodeGen/SBF/adjust-opt-icmp1.ll @@ -33,17 +33,17 @@ entry: %cmp = icmp sle i32 %1, 0 br i1 %cmp, label %if.then, label %lor.lhs.false -; CHECK: [[REG1:r[0-9]+]] <<= 32 -; CHECK: [[REG1]] s>>= 32 -; CHECK: [[REG2:r[0-9]+]] = 1 -; CHECK: if [[REG2]] s> [[REG1]] goto -; CHECK: if [[REG1]] s> 7 goto +; CHECK: lsh64 [[REG1:r[0-9]+]], 32 +; CHECK: arsh64 [[REG1]], 32 +; CHECK: mov64 [[REG2:r[0-9]+]], 1 +; CHECK: jsgt [[REG2]], [[REG1]], +; CHECK: jsgt [[REG1]], 7, -; CHECK-DISABLE: [[REG1:r[0-9]+]] += -8 -; CHECK-DISABLE: [[REG1]] <<= 32 -; CHECK-DISABLE: [[REG1]] >>= 32 -; CHECK-DISABLE: [[REG2:r[0-9]+]] = 4294967289 -; CHECK-DISABLE: if [[REG2]] > [[REG1]] goto +; CHECK-DISABLE: add64 [[REG1:r[0-9]+]], -8 +; CHECK-DISABLE: lsh64 [[REG1]], 32 +; CHECK-DISABLE: rsh64 [[REG1]], 32 +; CHECK-DISABLE: lddw [[REG2:r[0-9]+]], 4294967289 +; CHECK-DISABLE: jgt [[REG2]], [[REG1]], lor.lhs.false: ; preds = %entry %2 = load i32, i32* %ret, align 4, !tbaa !2 diff --git a/llvm/test/CodeGen/SBF/adjust-opt-icmp2.ll b/llvm/test/CodeGen/SBF/adjust-opt-icmp2.ll index dd3b7eee10c91e..b78c18365ad815 100644 --- a/llvm/test/CodeGen/SBF/adjust-opt-icmp2.ll +++ b/llvm/test/CodeGen/SBF/adjust-opt-icmp2.ll @@ -31,17 +31,17 @@ entry: %cmp = icmp sle i32 %1, 0 br i1 %cmp, label %if.then, label %if.end -; CHECK: [[REG1:r[0-9]+]] <<= 32 -; CHECK: [[REG1]] s>>= 32 -; CHECK: [[REG2:r[0-9]+]] = 1 -; CHECK: if [[REG2]] s> [[REG1]] goto -; CHECK: if [[REG1]] s> 7 goto +; CHECK: lsh64 [[REG1:r[0-9]+]], 32 +; CHECK: arsh64 [[REG1]], 32 +; CHECK: mov64 [[REG2:r[0-9]+]], 1 +; CHECK: jsgt [[REG2]], [[REG1]], +; CHECK: jsgt [[REG1]], 7, -; CHECK-DISABLE: [[REG1:r[0-9]+]] += -8 -; CHECK-DISABLE: [[REG1]] <<= 32 -; CHECK-DISABLE: [[REG1]] >>= 32 -; CHECK-DISABLE: [[REG2:r[0-9]+]] = 4294967289 -; CHECK-DISABLE: if [[REG2]] > [[REG1]] goto +; CHECK-DISABLE: add64 [[REG1:r[0-9]+]], -8 +; CHECK-DISABLE: lsh64 [[REG1]], 32 +; CHECK-DISABLE: rsh64 [[REG1]], 32 +; CHECK-DISABLE: lddw [[REG2:r[0-9]+]], 4294967289 +; CHECK-DISABLE: jgt [[REG2]], [[REG1]], if.then: ; preds = %entry store i32 0, i32* %retval, align 4 diff --git a/llvm/test/CodeGen/SBF/adjust-opt-icmp3.ll b/llvm/test/CodeGen/SBF/adjust-opt-icmp3.ll index f7eed6fea77d9b..28d932bbf5937f 100644 --- a/llvm/test/CodeGen/SBF/adjust-opt-icmp3.ll +++ b/llvm/test/CodeGen/SBF/adjust-opt-icmp3.ll @@ -40,8 +40,8 @@ return: ; preds = %if.end, %if.then } ; CHECK-LABEL: test1 -; CHECK-V1: if r[[#]] > r[[#]] goto -; CHECK-V3: if w[[#]] < 4 goto +; CHECK-V1: jgt r[[#]], r[[#]], +; CHECK-V3: jlt w[[#]], 4, ; Function Attrs: nounwind define dso_local i32 @test2(i64 %a) #0 { @@ -68,8 +68,8 @@ return: ; preds = %if.end, %if.then } ; CHECK-LABEL: test2 -; CHECK-V1: if r[[#]] > r[[#]] goto -; CHECK-V3: if w[[#]] < 4 goto +; CHECK-V1: jgt r[[#]], r[[#]], +; CHECK-V3: jlt w[[#]], 4, attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SBF/adjust-opt-icmp4.ll b/llvm/test/CodeGen/SBF/adjust-opt-icmp4.ll index ac079f5dbe533a..a3d202657847cc 100644 --- a/llvm/test/CodeGen/SBF/adjust-opt-icmp4.ll +++ b/llvm/test/CodeGen/SBF/adjust-opt-icmp4.ll @@ -40,8 +40,8 @@ return: ; preds = %if.end, %if.then } ; CHECK-LABEL: test1 -; CHECK-V1: if r[[#]] > 3 goto -; CHECK-V3: if w[[#]] > 3 goto +; CHECK-V1: jgt r[[#]], 3, +; CHECK-V3: jgt w[[#]], 3, ; Function Attrs: nounwind define dso_local i32 @test2(i64 %a) #0 { @@ -68,8 +68,8 @@ return: ; preds = %if.end, %if.then } ; CHECK-LABEL: test2 -; CHECK-V1: if r[[#]] > 3 goto -; CHECK-V3: if w[[#]] > 3 goto +; CHECK-V1: jgt r[[#]], 3, +; CHECK-V3: jgt w[[#]], 3, attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SBF/adjust-opt-speculative1.ll b/llvm/test/CodeGen/SBF/adjust-opt-speculative1.ll index 46a39411bedc2b..5f3ef42b6dc7e1 100644 --- a/llvm/test/CodeGen/SBF/adjust-opt-speculative1.ll +++ b/llvm/test/CodeGen/SBF/adjust-opt-speculative1.ll @@ -41,20 +41,20 @@ if.end: ; preds = %if.then, %entry call void @llvm.lifetime.end.p0i8(i64 8, i8* %5) #3 ret i8* %4 } -; CHECK-COMMON: [[REG6:r[0-9]+]] = r1 +; CHECK-COMMON: mov64 [[REG6:r[0-9]+]], r1 ; CHECK-COMMON: call foo -; CHECK: if r0 > 7 goto [[LABEL:.*]] -; CHECK: [[REG6]] += r0 +; CHECK: jgt r0, 7, [[LABEL:.*]] +; CHECK: add64 [[REG6]], r0 ; CHECK: [[LABEL]]: -; CHECK: r0 = [[REG6]] +; CHECK: mov64 r0, [[REG6]] -; CHECK-DISABLE: [[REG1:r[0-9]+]] = 8 -; CHECK-DISABLE: if [[REG1]] > r0 goto [[LABEL:.*]] -; CHECK-DISABLE: r0 = 0 +; CHECK-DISABLE: mov64 [[REG1:r[0-9]+]], 8 +; CHECK-DISABLE: jgt [[REG1]], r0, [[LABEL:.*]] +; CHECK-DISABLE: mov64 r0, 0 ; CHECK-DISABLE: [[LABEL]]: -; CHECK-DISABLE: [[REG6]] += r0 -; CHECK-DISABLE: r0 = [[REG6]] +; CHECK-DISABLE: add64 [[REG6]], r0 +; CHECK-DISABLE: mov64 r0, [[REG6]] ; CHECK-COMMON: exit diff --git a/llvm/test/CodeGen/SBF/adjust-opt-speculative2.ll b/llvm/test/CodeGen/SBF/adjust-opt-speculative2.ll index 8f663160dd7f92..371920a9cf9a95 100644 --- a/llvm/test/CodeGen/SBF/adjust-opt-speculative2.ll +++ b/llvm/test/CodeGen/SBF/adjust-opt-speculative2.ll @@ -43,27 +43,27 @@ if.end: ; preds = %if.then, %entry ret i8* %4 } -; CHECK-COMMON: [[REG6:r[0-9]+]] = r1 +; CHECK-COMMON: mov64 [[REG6:r[0-9]+]], r1 ; CHECK-COMMON: call foo -; CHECK: r0 <<= 32 -; CHECK: r0 >>= 32 -; CHECK: if r0 > 7 goto [[LABEL:.*]] -; CHECK: [[REG6]] += r0 +; CHECK: lsh64 r0, 32 +; CHECK: rsh64 r0, 32 +; CHECK: jgt r0, 7, [[LABEL:.*]] +; CHECK: add64 [[REG6]], r0 ; CHECK: [[LABEL]]: -; CHECK: r0 = [[REG6]] +; CHECK: mov64 r0, [[REG6]] -; CHECK-DISABLE: [[REG1:r[0-9]+]] = r0 -; CHECK-DISABLE: [[REG1]] <<= 32 -; CHECK-DISABLE: [[REG1]] >>= 32 -; CHECK-DISABLE: [[REG2:r[0-9]+]] = 8 -; CHECK-DISABLE: if [[REG2]] > [[REG1]] goto [[LABEL:.*]] -; CHECK-DISABLE: r0 = 0 +; CHECK-DISABLE: mov64 [[REG1:r[0-9]+]], r0 +; CHECK-DISABLE: lsh64 [[REG1]], 32 +; CHECK-DISABLE: rsh64 [[REG1]], 32 +; CHECK-DISABLE: mov64 [[REG2:r[0-9]+]], 8 +; CHECK-DISABLE: jgt [[REG2]], [[REG1]], [[LABEL:.*]] +; CHECK-DISABLE: mov64 r0, 0 ; CHECK-DISABLE: [[LABEL]]: -; CHECK-DISABLE: r0 <<= 32 -; CHECK-DISABLE: r0 >>= 32 -; CHECK-DISABLE: [[REG6]] += r0 -; CHECK-DISABLE: r0 = [[REG6]] +; CHECK-DISABLE: lsh64 r0, 32 +; CHECK-DISABLE: rsh64 r0, 32 +; CHECK-DISABLE: add64 [[REG6]], r0 +; CHECK-DISABLE: mov64 r0, [[REG6]] ; CHECK-COMMON: exit diff --git a/llvm/test/CodeGen/SBF/alu8.ll b/llvm/test/CodeGen/SBF/alu8.ll index 35e5f7e63dcb35..3843fab1d82689 100644 --- a/llvm/test/CodeGen/SBF/alu8.ll +++ b/llvm/test/CodeGen/SBF/alu8.ll @@ -2,36 +2,36 @@ define i8 @mov(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: mov: -; CHECK: r0 = r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: mov64 r0, r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00] ; CHECK: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00] ret i8 %b } define i8 @add(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: add: -; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00] -; CHECK: r0 += r2 # encoding: [0x0f,0x20,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: mov64 r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: add64 r0, r2 # encoding: [0x0f,0x20,0x00,0x00,0x00,0x00,0x00,0x00] %1 = add i8 %a, %b ret i8 %1 } define i8 @and(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: and: -; CHECK: r0 &= r2 # encoding: [0x5f,0x20,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: and64 r0, r2 # encoding: [0x5f,0x20,0x00,0x00,0x00,0x00,0x00,0x00] %1 = and i8 %a, %b ret i8 %1 } define i8 @bis(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: bis: -; CHECK: r0 |= r2 # encoding: [0x4f,0x20,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: or64 r0, r2 # encoding: [0x4f,0x20,0x00,0x00,0x00,0x00,0x00,0x00] %1 = or i8 %a, %b ret i8 %1 } define i8 @xorand(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: xorand: -; CHECK: r2 ^= -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff] +; CHECK: xor64 r2, -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff] %1 = xor i8 %b, -1 %2 = and i8 %a, %1 ret i8 %2 @@ -39,7 +39,7 @@ define i8 @xorand(i8 %a, i8 %b) nounwind { define i8 @xor(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: xor: -; CHECK: r0 ^= r2 # encoding: [0xaf,0x20,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: xor64 r0, r2 # encoding: [0xaf,0x20,0x00,0x00,0x00,0x00,0x00,0x00] %1 = xor i8 %a, %b ret i8 %1 } diff --git a/llvm/test/CodeGen/SBF/atomics_sbf.ll b/llvm/test/CodeGen/SBF/atomics_sbf.ll index 8e448e4aba13a2..4af68c876f20e8 100644 --- a/llvm/test/CodeGen/SBF/atomics_sbf.ll +++ b/llvm/test/CodeGen/SBF/atomics_sbf.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -march=sbf -mcpu=v3 -verify-machineinstrs | tee -i /tmp/log | FileCheck %s ; ; CHECK-LABEL: test_load_add_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: w3 += w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: add32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_load_add_32(i32* nocapture %p, i32 %v) local_unnamed_addr { entry: %0 = atomicrmw add i32* %p, i32 %v seq_cst @@ -12,10 +12,10 @@ entry: } ; CHECK-LABEL: test_load_add_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: r3 += r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: add64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i32 @test_load_add_64(i64* nocapture %p, i64 %v) local_unnamed_addr { entry: %0 = atomicrmw add i64* %p, i64 %v seq_cst @@ -24,10 +24,10 @@ entry: } ; CHECK-LABEL: test_load_sub_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: w3 -= w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: sub32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_load_sub_32(i32* nocapture %p, i32 %v) local_unnamed_addr { entry: %0 = atomicrmw sub i32* %p, i32 %v seq_cst @@ -35,10 +35,10 @@ entry: } ; CHECK-LABEL: test_load_sub_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: r3 -= r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: sub64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i32 @test_load_sub_64(i64* nocapture %p, i64 %v) local_unnamed_addr { entry: %0 = atomicrmw sub i64* %p, i64 %v seq_cst @@ -47,8 +47,8 @@ entry: } ; CHECK-LABEL: test_xchg_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: *(u32 *)(r1 + 0) = w2 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: stxw [r1 + 0], w2 define dso_local i32 @test_xchg_32(i32* nocapture %p, i32 %v) local_unnamed_addr { entry: %0 = atomicrmw xchg i32* %p, i32 %v seq_cst @@ -56,8 +56,8 @@ entry: } ; CHECK-LABEL: test_xchg_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: *(u64 *)(r1 + 0) = r2 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: stxdw [r1 + 0], r2 define dso_local i32 @test_xchg_64(i64* nocapture %p, i64 %v) local_unnamed_addr { entry: %0 = atomicrmw xchg i64* %p, i64 %v seq_cst @@ -66,10 +66,10 @@ entry: } ; CHECK-LABEL: test_cas_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: if w0 == w2 goto -; CHECK: w3 = w0 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: jeq w0, w2, +; CHECK: mov32 w3, w0 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_cas_32(i32* nocapture %p, i32 %old, i32 %new) local_unnamed_addr { entry: %0 = cmpxchg i32* %p, i32 %old, i32 %new seq_cst seq_cst @@ -78,10 +78,10 @@ entry: } ; CHECK-LABEL: test_cas_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: if r0 == r2 goto -; CHECK: r3 = r0 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: jeq r0, r2, +; CHECK: mov64 r3, r0 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_cas_64(i64* nocapture %p, i64 %old, i64 %new) local_unnamed_addr { entry: %0 = cmpxchg i64* %p, i64 %old, i64 %new seq_cst seq_cst @@ -90,10 +90,10 @@ entry: } ; CHECK-LABEL: test_load_and_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: w3 &= w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: and32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_load_and_32(i32* nocapture %p, i32 %v) local_unnamed_addr { entry: %0 = atomicrmw and i32* %p, i32 %v seq_cst @@ -101,10 +101,10 @@ entry: } ; CHECK-LABEL: test_load_and_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: r3 &= r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: and64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_load_and_64(i64* nocapture %p, i64 %v) local_unnamed_addr { entry: %0 = atomicrmw and i64* %p, i64 %v seq_cst @@ -112,11 +112,11 @@ entry: } ; CHECK-LABEL: test_load_nand_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: w3 &= w2 -; CHECK: w3 ^= -1 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: and32 w3, w2 +; CHECK: xor32 w3, -1 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_load_nand_32(i32* nocapture %p, i32 %v) local_unnamed_addr { entry: %0 = atomicrmw nand i32* %p, i32 %v seq_cst @@ -124,11 +124,11 @@ entry: } ; CHECK-LABEL: test_load_nand_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: r3 &= r2 -; CHECK: r3 ^= -1 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: and64 r3, r2 +; CHECK: xor64 r3, -1 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_load_nand_64(i64* nocapture %p, i64 %v) local_unnamed_addr { entry: %0 = atomicrmw nand i64* %p, i64 %v seq_cst @@ -136,10 +136,10 @@ entry: } ; CHECK-LABEL: test_load_or_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: w3 |= w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: or32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_load_or_32(i32* nocapture %p, i32 %v) local_unnamed_addr { entry: %0 = atomicrmw or i32* %p, i32 %v seq_cst @@ -147,10 +147,10 @@ entry: } ; CHECK-LABEL: test_load_or_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: r3 |= r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: or64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_load_or_64(i64* nocapture %p, i64 %v) local_unnamed_addr { entry: %0 = atomicrmw or i64* %p, i64 %v seq_cst @@ -158,10 +158,10 @@ entry: } ; CHECK-LABEL: test_load_xor_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: w3 ^= w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: xor32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_load_xor_32(i32* nocapture %p, i32 %v) local_unnamed_addr { entry: %0 = atomicrmw xor i32* %p, i32 %v seq_cst @@ -169,10 +169,10 @@ entry: } ; CHECK-LABEL: test_load_xor_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: r3 ^= r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: xor64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_load_xor_64(i64* nocapture %p, i64 %v) local_unnamed_addr { entry: %0 = atomicrmw xor i64* %p, i64 %v seq_cst @@ -180,11 +180,11 @@ entry: } ; CHECK-LABEL: test_min_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: if w0 s< w2 goto -; CHECK: w3 = w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: jslt w0, w2, +; CHECK: mov32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_min_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw min i32* %ptr, i32 %v release, align 1 @@ -192,11 +192,11 @@ entry: } ; CHECK-LABEL: test_min_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: if r0 s< r2 goto -; CHECK: r3 = r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: jslt r0, r2, +; CHECK: mov64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_min_64(i64* nocapture %ptr, i64 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw min i64* %ptr, i64 %v release, align 1 @@ -204,11 +204,11 @@ entry: } ; CHECK-LABEL: test_max_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: if w0 s> w2 goto -; CHECK: w3 = w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: jsgt w0, w2, +; CHECK: mov32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_max_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw max i32* %ptr, i32 %v release, align 1 @@ -216,11 +216,11 @@ entry: } ; CHECK-LABEL: test_max_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: if r0 s> r2 goto -; CHECK: r3 = r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: jsgt r0, r2, +; CHECK: mov64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_max_64(i64* nocapture %ptr, i64 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw max i64* %ptr, i64 %v release, align 1 @@ -228,11 +228,11 @@ entry: } ; CHECK-LABEL: test_umin_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: if w0 < w2 goto -; CHECK: w3 = w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: jlt w0, w2, +; CHECK: mov32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_umin_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw umin i32* %ptr, i32 %v release, align 1 @@ -240,11 +240,11 @@ entry: } ; CHECK-LABEL: test_umin_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: if r0 < r2 goto -; CHECK: r3 = r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: jlt r0, r2, +; CHECK: mov64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_umin_64(i64* nocapture %ptr, i64 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw umin i64* %ptr, i64 %v release, align 1 @@ -252,11 +252,11 @@ entry: } ; CHECK-LABEL: test_umax_32 -; CHECK: w0 = *(u32 *)(r1 + 0) -; CHECK: w3 = w0 -; CHECK: if w0 > w2 goto -; CHECK: w3 = w2 -; CHECK: *(u32 *)(r1 + 0) = w3 +; CHECK: ldxw w0, [r1 + 0] +; CHECK: mov32 w3, w0 +; CHECK: jgt w0, w2, +; CHECK: mov32 w3, w2 +; CHECK: stxw [r1 + 0], w3 define dso_local i32 @test_umax_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw umax i32* %ptr, i32 %v release, align 1 @@ -264,11 +264,11 @@ entry: } ; CHECK-LABEL: test_umax_64 -; CHECK: r0 = *(u64 *)(r1 + 0) -; CHECK: r3 = r0 -; CHECK: if r0 > r2 goto -; CHECK: r3 = r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r0, [r1 + 0] +; CHECK: mov64 r3, r0 +; CHECK: jgt r0, r2, +; CHECK: mov64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define dso_local i64 @test_umax_64(i64* nocapture %ptr, i64 %v) local_unnamed_addr #0 { entry: %0 = atomicrmw umax i64* %ptr, i64 %v release, align 1 diff --git a/llvm/test/CodeGen/SBF/basictest.ll b/llvm/test/CodeGen/SBF/basictest.ll index 5cc98bfaf65b8c..7af1db977e7ffc 100644 --- a/llvm/test/CodeGen/SBF/basictest.ll +++ b/llvm/test/CodeGen/SBF/basictest.ll @@ -4,12 +4,12 @@ define i32 @test0(i32 %X) { %tmp.1 = add i32 %X, 1 ret i32 %tmp.1 ; CHECK-LABEL: test0: -; CHECK: r0 += 1 +; CHECK: add64 r0, 1 } ; CHECK-LABEL: store_imm: -; CHECK: *(u32 *)(r1 + 0) = r{{[03]}} -; CHECK: *(u32 *)(r2 + 4) = r{{[03]}} +; CHECK: stxw [r1 + 0], r{{[03]}} +; CHECK: stxw [r2 + 4], r{{[03]}} define i32 @store_imm(i32* %a, i32* %b) { entry: store i32 0, i32* %a, align 4 @@ -23,6 +23,6 @@ define zeroext i8 @loadG() { %tmp = load i8, i8* @G ret i8 %tmp ; CHECK-LABEL: loadG: -; CHECK: r1 = -; CHECK: r0 = *(u8 *)(r1 + 0) +; CHECK: lddw r1, G +; CHECK: ldxb r0, [r1 + 0] } diff --git a/llvm/test/CodeGen/SBF/byval.ll b/llvm/test/CodeGen/SBF/byval.ll index ba24c7a99aa3ad..652b2a88a6ea51 100644 --- a/llvm/test/CodeGen/SBF/byval.ll +++ b/llvm/test/CodeGen/SBF/byval.ll @@ -5,10 +5,10 @@ ; Function Attrs: nounwind uwtable define void @bar(i32 %a) #0 { ; CHECK-LABEL: bar: -; CHECK: r2 = 8589934593 ll -; CHECK: *(u64 *)(r10 - 40) = r2 -; CHECK: r2 = r10 -; CHECK: r2 += -40 +; CHECK: lddw r2, 8589934593 +; CHECK: stxdw [r10 - 40], r2 +; CHECK: mov64 r2, r10 +; CHECK: add64 r2, -40 ; CHECK: call foo entry: %.compoundliteral = alloca %struct.S, align 8 diff --git a/llvm/test/CodeGen/SBF/cc_args.ll b/llvm/test/CodeGen/SBF/cc_args.ll index 5d4a26945b66c7..3b7f46eb74409e 100644 --- a/llvm/test/CodeGen/SBF/cc_args.ll +++ b/llvm/test/CodeGen/SBF/cc_args.ll @@ -4,32 +4,32 @@ define void @test() #0 { entry: ; CHECK: test: -; CHECK: r1 = 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00] +; CHECK: mov64 r1, 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00] ; CHECK: call f_i16 call void @f_i16(i16 123) -; CHECK: r1 = 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00] +; CHECK: mov64 r1, 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00] ; CHECK: call f_i32 call void @f_i32(i32 12345678) -; CHECK: r1 = 72623859790382856 ll # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01] +; CHECK: lddw r1, 72623859790382856 # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01] ; CHECK: call f_i64 call void @f_i64(i64 72623859790382856) -; CHECK: r1 = 1234 -; CHECK: r2 = 5678 +; CHECK: mov64 r1, 1234 +; CHECK: mov64 r2, 5678 ; CHECK: call f_i32_i32 call void @f_i32_i32(i32 1234, i32 5678) -; CHECK: r1 = 2 -; CHECK: r2 = 3 -; CHECK: r3 = 4 +; CHECK: mov64 r1, 2 +; CHECK: mov64 r2, 3 +; CHECK: mov64 r3, 4 ; CHECK: call f_i16_i32_i16 call void @f_i16_i32_i16(i16 2, i32 3, i16 4) -; CHECK: r1 = 5 -; CHECK: r2 = 7262385979038285 ll -; CHECK: r3 = 6 +; CHECK: mov64 r1, 5 +; CHECK: lddw r2, 7262385979038285 +; CHECK: mov64 r3, 6 ; CHECK: call f_i16_i64_i16 call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6) @@ -42,52 +42,52 @@ entry: define void @f_i16(i16 %a) #0 { ; CHECK: f_i16: -; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: stxh [r2 + 0], r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00] store volatile i16 %a, i16* @g_i16, align 2 ret void } define void @f_i32(i32 %a) #0 { ; CHECK: f_i32: -; CHECK: *(u32 *)(r2 + 0) = r1 # encoding: [0x63,0x12,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: stxw [r2 + 0], r1 # encoding: [0x63,0x12,0x00,0x00,0x00,0x00,0x00,0x00] store volatile i32 %a, i32* @g_i32, align 2 ret void } define void @f_i64(i64 %a) #0 { ; CHECK: f_i64: -; CHECK: *(u64 *)(r2 + 0) = r1 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: stxdw [r2 + 0], r1 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00] store volatile i64 %a, i64* @g_i64, align 2 ret void } define void @f_i32_i32(i32 %a, i32 %b) #0 { ; CHECK: f_i32_i32: -; CHECK: *(u32 *)(r3 + 0) = r1 +; CHECK: stxw [r3 + 0], r1 store volatile i32 %a, i32* @g_i32, align 4 -; CHECK: *(u32 *)(r3 + 0) = r2 +; CHECK: stxw [r3 + 0], r2 store volatile i32 %b, i32* @g_i32, align 4 ret void } define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 { ; CHECK: f_i16_i32_i16: -; CHECK: *(u16 *)(r4 + 0) = r1 +; CHECK: stxh [r4 + 0], r1 store volatile i16 %a, i16* @g_i16, align 2 -; CHECK: *(u32 *)(r1 + 0) = r2 +; CHECK: stxw [r1 + 0], r2 store volatile i32 %b, i32* @g_i32, align 4 -; CHECK: *(u16 *)(r4 + 0) = r3 +; CHECK: stxh [r4 + 0], r3 store volatile i16 %c, i16* @g_i16, align 2 ret void } define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 { ; CHECK: f_i16_i64_i16: -; CHECK: *(u16 *)(r4 + 0) = r1 +; CHECK: stxh [r4 + 0], r1 store volatile i16 %a, i16* @g_i16, align 2 -; CHECK: *(u64 *)(r1 + 0) = r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: stxdw [r1 + 0], r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00] store volatile i64 %b, i64* @g_i64, align 8 -; CHECK: *(u16 *)(r4 + 0) = r3 +; CHECK: stxh [r4 + 0], r3 store volatile i16 %c, i16* @g_i16, align 2 ret void } diff --git a/llvm/test/CodeGen/SBF/cc_ret.ll b/llvm/test/CodeGen/SBF/cc_ret.ll index 8625e548b8ff8d..12a22e2cb5ace1 100644 --- a/llvm/test/CodeGen/SBF/cc_ret.ll +++ b/llvm/test/CodeGen/SBF/cc_ret.ll @@ -5,17 +5,17 @@ entry: ; CHECK: test: ; CHECK: call f_i16 -; CHECK: *(u16 *)(r1 + 0) = r0 +; CHECK: stxh [r1 + 0], r0 %0 = call i16 @f_i16() store volatile i16 %0, i16* @g_i16 ; CHECK: call f_i32 -; CHECK: *(u32 *)(r1 + 0) = r0 +; CHECK: stxw [r1 + 0], r0 %1 = call i32 @f_i32() store volatile i32 %1, i32* @g_i32 ; CHECK: call f_i64 -; CHECK: *(u64 *)(r1 + 0) = r0 +; CHECK: stxdw [r1 + 0], r0 %2 = call i64 @f_i64() store volatile i64 %2, i64* @g_i64 @@ -28,21 +28,21 @@ entry: define i16 @f_i16() #0 { ; CHECK: f_i16: -; CHECK: r0 = 1 +; CHECK: mov64 r0, 1 ; CHECK: exit ret i16 1 } define i32 @f_i32() #0 { ; CHECK: f_i32: -; CHECK: r0 = 16909060 +; CHECK: mov64 r0, 16909060 ; CHECK: exit ret i32 16909060 } define i64 @f_i64() #0 { ; CHECK: f_i64: -; CHECK: r0 = 72623859790382856 ll +; CHECK: lddw r0, 72623859790382856 ; CHECK: exit ret i64 72623859790382856 } diff --git a/llvm/test/CodeGen/SBF/cmp.ll b/llvm/test/CodeGen/SBF/cmp.ll index 2f90b50bb2b112..328ba1d7b31848 100644 --- a/llvm/test/CodeGen/SBF/cmp.ll +++ b/llvm/test/CodeGen/SBF/cmp.ll @@ -17,7 +17,7 @@ define signext i8 @foo_cmp1(i8 signext %a, i8 signext %b) #0 { %.0 = phi i8 [ %3, %2 ], [ %5, %4 ] ret i8 %.0 ; CHECK-LABEL:foo_cmp1: -; CHECK: if r0 s>= r1 +; CHECK: jsge r0, r1 } ; Function Attrs: nounwind readnone uwtable @@ -37,7 +37,7 @@ define signext i8 @foo_cmp2(i8 signext %a, i8 signext %b) #0 { %.0 = phi i8 [ %3, %2 ], [ %5, %4 ] ret i8 %.0 ; CHECK-LABEL:foo_cmp2: -; CHECK: if r0 s> r1 +; CHECK: jsgt r0, r1 } ; Function Attrs: nounwind readnone uwtable @@ -57,7 +57,7 @@ define signext i8 @foo_cmp3(i8 signext %a, i8 signext %b) #0 { %.0 = phi i8 [ %3, %2 ], [ %5, %4 ] ret i8 %.0 ; CHECK-LABEL:foo_cmp3: -; CHECK: if r1 s>= r0 +; CHECK: jsge r1, r0 } ; Function Attrs: nounwind readnone uwtable @@ -77,7 +77,7 @@ define signext i8 @foo_cmp4(i8 signext %a, i8 signext %b) #0 { %.0 = phi i8 [ %3, %2 ], [ %5, %4 ] ret i8 %.0 ; CHECK-LABEL:foo_cmp4: -; CHECK: if r1 s> r0 +; CHECK: jsgt r1, r0 } ; Function Attrs: nounwind readnone uwtable @@ -86,9 +86,9 @@ define signext i8 @min(i8 signext %a, i8 signext %b) #0 { %a.b = select i1 %1, i8 %a, i8 %b ret i8 %a.b ; CHECK-LABEL:min: -; CHECK: r0 = r1 -; CHECK: if r2 s> r0 -; CHECK: r0 = r2 +; CHECK: mov64 r0, r1 +; CHECK: jsgt r2, r0 +; CHECK: mov64 r0, r2 } ; Function Attrs: nounwind readnone uwtable @@ -97,7 +97,7 @@ define zeroext i8 @minu(i8 zeroext %a, i8 zeroext %b) #0 { %a.b = select i1 %1, i8 %a, i8 %b ret i8 %a.b ; CHECK-LABEL:minu: -; CHECK: if r{{[0-9]+}} {{<|>}} r{{[0-9]+}} +; CHECK: {{jlt|jgt}} r{{[0-9]+}}, r{{[0-9]+}} } ; Function Attrs: nounwind readnone uwtable @@ -106,7 +106,7 @@ define signext i8 @max(i8 signext %a, i8 signext %b) #0 { %a.b = select i1 %1, i8 %a, i8 %b ret i8 %a.b ; CHECK-LABEL:max: -; CHECK: if r0 s> r2 +; CHECK: jsgt r0, r2 } ; Function Attrs: nounwind readnone uwtable @@ -115,5 +115,5 @@ define signext i8 @meq(i8 signext %a, i8 signext %b, i8 signext %c) #0 { %c.a = select i1 %1, i8 %c, i8 %a ret i8 %c.a ; CHECK-LABEL:meq: -; CHECK: if r1 == r2 +; CHECK: jeq r1, r2 } diff --git a/llvm/test/CodeGen/SBF/ex1.ll b/llvm/test/CodeGen/SBF/ex1.ll index 0a0f5f2e6d4f27..615e7c2b1c89c4 100644 --- a/llvm/test/CodeGen/SBF/ex1.ll +++ b/llvm/test/CodeGen/SBF/ex1.ll @@ -30,11 +30,11 @@ define i32 @bpf_prog1(%struct.bpf_context* nocapture %ctx) #0 section "events/ne ; CHECK-LABEL: bpf_prog1: ; CHECK: call 4 ; CHECK: call 9 -; CHECK: if r0 != 0 -; CHECK: r1 = 2946850620859748 ll -; CHECK: r1 = 7214898703899978611 ll +; CHECK: jne r0, 0 +; CHECK: lddw r1, 2946850620859748 +; CHECK: lddw r1, 7214898703899978611 ; CHECK: call 11 -; CHECK: r0 = 0 +; CHECK: mov64 r0, 0 ; CHECK: exit br label %13 diff --git a/llvm/test/CodeGen/SBF/f64-intrinsics.ll b/llvm/test/CodeGen/SBF/f64-intrinsics.ll index f71fb71c81c727..c1203dbe147775 100644 --- a/llvm/test/CodeGen/SBF/f64-intrinsics.ll +++ b/llvm/test/CodeGen/SBF/f64-intrinsics.ll @@ -14,8 +14,8 @@ define double @powi_f64(double %a, i32 %b) nounwind { ; ; CHECK64-LABEL: powi_f64: ; CHECK64: # %bb.0: -; CHECK64-NEXT: r2 <<= 32 -; CHECK64-NEXT: r2 s>>= 32 +; CHECK64-NEXT: lsh64 r2, 32 +; CHECK64-NEXT: arsh64 r2, 32 ; CHECK64-NEXT: call __powidf2 ; CHECK64-NEXT: exit %1 = call double @llvm.powi.f64.i32(double %a, i32 %b) diff --git a/llvm/test/CodeGen/SBF/fi_ri.ll b/llvm/test/CodeGen/SBF/fi_ri.ll index cb16d3c7448ed5..836728088db538 100644 --- a/llvm/test/CodeGen/SBF/fi_ri.ll +++ b/llvm/test/CodeGen/SBF/fi_ri.ll @@ -6,13 +6,13 @@ define i32 @test() #0 { %key = alloca %struct.key_t, align 4 %1 = bitcast %struct.key_t* %key to i8* -; CHECK: r1 = 0 -; CHECK: *(u32 *)(r10 - 8) = r1 -; CHECK: *(u64 *)(r10 - 16) = r1 -; CHECK: *(u64 *)(r10 - 24) = r1 +; CHECK: mov64 r1, 0 +; CHECK: stxw [r10 - 8], r1 +; CHECK: stxdw [r10 - 16], r1 +; CHECK: stxdw [r10 - 24], r1 call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 20, i1 false) -; CHECK: r1 = r10 -; CHECK: r1 += -20 +; CHECK: mov64 r1, r10 +; CHECK: add64 r1, -20 %2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0 ; CHECK: call test1 call void @test1(i8* %2) #3 diff --git a/llvm/test/CodeGen/SBF/i128.ll b/llvm/test/CodeGen/SBF/i128.ll index 373b89ef62e3d0..1c2bedc77438a0 100644 --- a/llvm/test/CodeGen/SBF/i128.ll +++ b/llvm/test/CodeGen/SBF/i128.ll @@ -32,10 +32,10 @@ entry: } ; CHECK-LABEL: test -; CHECK: r7 = r10 -; CHECK: r7 += -32 -; CHECK: r1 = r7 -; CHECK: *(u32 *)(r10 - 32) = r{{[0-9]+}} +; CHECK: mov64 r7, r10 +; CHECK: add64 r7, -32 +; CHECK: mov64 r1, r7 +; CHECK: stxw [r10 - 32], r{{[0-9]+}} ; Function Attrs: argmemonly nounwind willreturn declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 diff --git a/llvm/test/CodeGen/SBF/inline_asm.ll b/llvm/test/CodeGen/SBF/inline_asm.ll index 3e7dcd39a9dceb..141bc39c4135d0 100644 --- a/llvm/test/CodeGen/SBF/inline_asm.ll +++ b/llvm/test/CodeGen/SBF/inline_asm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=sbf -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -march=sbf -verify-machineinstrs --sbf-output-asm-variant=1 | FileCheck %s ; Source code: ; int g[2]; @@ -25,17 +25,17 @@ entry: %0 = bitcast i32* %a to i8* call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0) #2 store i32 4, i32* %a, align 4 - tail call void asm sideeffect "r0 = *(u16 *)skb[$0]", "i"(i32 2) #2 + tail call void asm sideeffect ".syntax_old r0 = *(u16 *)skb[$0]", "i"(i32 2) #2 ; CHECK: r0 = *(u16 *)skb[2] - tail call void asm sideeffect "r0 = *(u16 *)skb[$0]", "r"(i32 4) #2 + tail call void asm sideeffect ".syntax_old r0 = *(u16 *)skb[$0]", "r"(i32 4) #2 ; CHECK: r0 = *(u16 *)skb[r1] - %1 = tail call i32 asm sideeffect "$0 = $1", "=r,i"(i32 4) #2 + %1 = tail call i32 asm sideeffect ".syntax_old $0 = $1", "=r,i"(i32 4) #2 ; CHECK: r1 = 4 - %2 = tail call i32 asm sideeffect "$0 = $1 ll", "=r,i"(i64 333333333333) #2 + %2 = tail call i32 asm sideeffect ".syntax_old $0 = $1 ll", "=r,i"(i64 333333333333) #2 ; CHECK: r1 = 333333333333 ll - %3 = call i32 asm sideeffect "$0 = *(u16 *) $1", "=r,*m"(i32* elementtype(i32) nonnull %a) #2 + %3 = call i32 asm sideeffect ".syntax_old $0 = *(u16 *) $1", "=r,*m"(i32* elementtype(i32) nonnull %a) #2 ; CHECK: r1 = *(u16 *) (r10 - 4) - %4 = call i32 asm sideeffect "$0 = *(u32 *) $1", "=r,*m"(i32* elementtype(i32) getelementptr inbounds ([2 x i32], [2 x i32]* @g, i64 0, i64 1)) #2 + %4 = call i32 asm sideeffect ".syntax_old $0 = *(u32 *) $1", "=r,*m"(i32* elementtype(i32) getelementptr inbounds ([2 x i32], [2 x i32]* @g, i64 0, i64 1)) #2 ; CHECK: r1 = g ll ; CHECK: r0 = *(u32 *) (r1 + 4) call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0) #2 diff --git a/llvm/test/CodeGen/SBF/is_trunc_free.ll b/llvm/test/CodeGen/SBF/is_trunc_free.ll index f5b91089e23b46..12e671c7cc8994 100644 --- a/llvm/test/CodeGen/SBF/is_trunc_free.ll +++ b/llvm/test/CodeGen/SBF/is_trunc_free.ll @@ -58,8 +58,8 @@ cleanup: ; preds = %entry, %if.end10 ret i32 %retval.0 } -; CHECK: w{{[0-9]+}} = *(u32 *)(r{{[0-9]+}} + 0) -; CHECK-NOT: w{{[0-9]+}} = w{{[0-9]+}} +; CHECK: ldxw w{{[0-9]+}}, [r{{[0-9]+}} + 0] +; CHECK-NOT: mov32 w{{[0-9]+}}, w{{[0-9]+}} declare dso_local i32 @work(%struct.env_t*, i32) local_unnamed_addr #1 diff --git a/llvm/test/CodeGen/SBF/is_zext_free.ll b/llvm/test/CodeGen/SBF/is_zext_free.ll index cd267bc0066517..4011891ff47747 100644 --- a/llvm/test/CodeGen/SBF/is_zext_free.ll +++ b/llvm/test/CodeGen/SBF/is_zext_free.ll @@ -14,8 +14,8 @@ entry: ret i32 %conv } -; CHECK: r[[REG1:[0-9]+]] = r{{[0-9]+}} -; CHECK: w[[REG1]] &= w{{[0-9]+}} +; CHECK: mov64 r[[REG1:[0-9]+]], r{{[0-9]+}} +; CHECK: and32 w[[REG1]], w{{[0-9]+}} attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/SBF/load.ll b/llvm/test/CodeGen/SBF/load.ll index 78b8021bf8a36e..9710b7df111ef3 100644 --- a/llvm/test/CodeGen/SBF/load.ll +++ b/llvm/test/CodeGen/SBF/load.ll @@ -5,7 +5,7 @@ define i16 @am1(i16* %a) nounwind { ret i16 %1 } ; CHECK-LABEL: am1: -; CHECK: r0 = *(u16 *)(r1 + 0) +; CHECK: ldxh r0, [r1 + 0] @foo = external global i16 @@ -14,15 +14,15 @@ define i16 @am2() nounwind { ret i16 %1 } ; CHECK-LABEL: am2: -; CHECK: r0 = *(u16 *)(r1 + 0) +; CHECK: ldxh r0, [r1 + 0] define i16 @am4() nounwind { %1 = load volatile i16, i16* inttoptr(i16 32 to i16*) ret i16 %1 } ; CHECK-LABEL: am4: -; CHECK: r1 = 32 -; CHECK: r0 = *(u16 *)(r1 + 0) +; CHECK: mov64 r1, 32 +; CHECK: ldxh r0, [r1 + 0] define i16 @am5(i16* %a) nounwind { %1 = getelementptr i16, i16* %a, i16 2 @@ -30,7 +30,7 @@ define i16 @am5(i16* %a) nounwind { ret i16 %2 } ; CHECK-LABEL: am5: -; CHECK: r0 = *(u16 *)(r1 + 4) +; CHECK: ldxh r0, [r1 + 4] %S = type { i16, i16 } @baz = common global %S zeroinitializer, align 1 @@ -40,4 +40,4 @@ define i16 @am6() nounwind { ret i16 %1 } ; CHECK-LABEL: am6: -; CHECK: r0 = *(u16 *)(r1 + 2) +; CHECK: ldxh r0, [r1 + 2] diff --git a/llvm/test/CodeGen/SBF/loop-exit-cond.ll b/llvm/test/CodeGen/SBF/loop-exit-cond.ll index 016e7c06e2185f..e42467d05cb8c7 100644 --- a/llvm/test/CodeGen/SBF/loop-exit-cond.ll +++ b/llvm/test/CodeGen/SBF/loop-exit-cond.ll @@ -49,9 +49,9 @@ for.cond: ; preds = %for.inc, %if.then %cmp1 = icmp slt i32 %2, %3 br i1 %cmp1, label %for.body, label %for.cond.cleanup -; CHECK: w[[LEN:[0-9]+]] = w1 -; CHECK: w[[IDX:[0-9]+]] += 1 -; CHECK-NEXT: w[[IDX]] s< w[[LEN]] goto +; CHECK: mov32 w[[LEN:[0-9]+]], w1 +; CHECK: add32 w[[IDX:[0-9]+]], 1 +; CHECK-NEXT: jslt w[[IDX]], w[[LEN]], for.cond.cleanup: ; preds = %for.cond %4 = bitcast i32* %i to i8* diff --git a/llvm/test/CodeGen/SBF/loops.ll b/llvm/test/CodeGen/SBF/loops.ll index 13b5b46ab480a9..1ecf813bf94119 100644 --- a/llvm/test/CodeGen/SBF/loops.ll +++ b/llvm/test/CodeGen/SBF/loops.ll @@ -10,7 +10,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; [#uses=1] ; CHECK-LABEL: add: -; CHECK: r{{[0-9]+}} += r{{[0-9]+}} +; CHECK: add64 r{{[0-9]+}}, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; [#uses=1] %add = add i16 %tmp4, %sum.09 ; [#uses=2] %inc = add i16 %i.010, 1 ; [#uses=2] @@ -32,7 +32,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; [#uses=1] ; CHECK-LABEL: sub: -; CHECK: r{{[0-9]+}} -= r{{[0-9]+}} +; CHECK: sub64 r{{[0-9]+}}, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; [#uses=1] %add = sub i16 %tmp4, %sum.09 ; [#uses=2] %inc = add i16 %i.010, 1 ; [#uses=2] @@ -54,7 +54,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; [#uses=1] ; CHECK-LABEL: or: -; CHECK: r{{[0-9]+}} |= r{{[0-9]+}} +; CHECK: or64 r{{[0-9]+}}, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; [#uses=1] %add = or i16 %tmp4, %sum.09 ; [#uses=2] %inc = add i16 %i.010, 1 ; [#uses=2] @@ -76,7 +76,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; [#uses=1] ; CHECK-LABEL: xor: -; CHECK: r{{[0-9]+}} ^= r{{[0-9]+}} +; CHECK: xor64 r{{[0-9]+}}, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; [#uses=1] %add = xor i16 %tmp4, %sum.09 ; [#uses=2] %inc = add i16 %i.010, 1 ; [#uses=2] @@ -98,7 +98,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; [#uses=1] ; CHECK-LABEL: and: -; CHECK: r{{[0-9]+}} &= r{{[0-9]+}} +; CHECK: and64 r{{[0-9]+}}, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; [#uses=1] %add = and i16 %tmp4, %sum.09 ; [#uses=2] %inc = add i16 %i.010, 1 ; [#uses=2] diff --git a/llvm/test/CodeGen/SBF/many_args1.ll b/llvm/test/CodeGen/SBF/many_args1.ll index 3c6e277fa94249..18a7434e250b24 100644 --- a/llvm/test/CodeGen/SBF/many_args1.ll +++ b/llvm/test/CodeGen/SBF/many_args1.ll @@ -3,12 +3,12 @@ ; Function Attrs: nounwind uwtable define i32 @foo(i32 %a, i32 %b, i32 %c) #0 { ; CHECK-LABEL: foo: -; CHECK: r4 = 2 -; CHECK: *(u64 *)(r10 - 4096) = r4 -; CHECK: r4 = 3 -; CHECK: *(u64 *)(r10 - 4088) = r4 -; CHECK: r5 = r10 -; CHECK: r4 = 1 +; CHECK: mov64 r4, 2 +; CHECK: stxdw [r10 - 4096], r4 +; CHECK: mov64 r4, 3 +; CHECK: stxdw [r10 - 4088], r4 +; CHECK: mov64 r5, r10 +; CHECK: mov64 r4, 1 ; CHECK: call bar entry: %call = tail call i32 @bar(i32 %a, i32 %b, i32 %c, i32 1, i32 2, i32 3) #3 diff --git a/llvm/test/CodeGen/SBF/many_args2.ll b/llvm/test/CodeGen/SBF/many_args2.ll index 8db12aa47ba001..7b9151a5bd125a 100644 --- a/llvm/test/CodeGen/SBF/many_args2.ll +++ b/llvm/test/CodeGen/SBF/many_args2.ll @@ -3,7 +3,7 @@ ; Function Attrs: nounwind readnone uwtable define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) #0 { ; CHECK-LABEL: bar: -; CHECK: r0 = 1 +; CHECK: mov64 r0, 1 entry: ret i32 1 } @@ -11,7 +11,7 @@ entry: ; Function Attrs: nounwind readnone uwtable define i32 @foo(i32 %a, i32 %b, i32 %c) #0 { ; CHECK-LABEL: foo: -; CHECK: r0 = 1 +; CHECK: mov64 r0, 1 entry: ret i32 1 } diff --git a/llvm/test/CodeGen/SBF/mem_offset.ll b/llvm/test/CodeGen/SBF/mem_offset.ll index edce3e9975d0a3..90c850b38ece4f 100644 --- a/llvm/test/CodeGen/SBF/mem_offset.ll +++ b/llvm/test/CodeGen/SBF/mem_offset.ll @@ -2,8 +2,8 @@ ; Function Attrs: nounwind define i32 @bpf_prog1(i8* nocapture readnone) local_unnamed_addr #0 { -; CHECK: r1 += -1879113726 # encoding: [0x07,0x01,0x00,0x00,0x02,0x00,0xff,0x8f] -; CHECK: r0 = *(u64 *)(r1 + 0) # encoding: [0x79,0x10,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: add64 r1, -1879113726 # encoding: [0x07,0x01,0x00,0x00,0x02,0x00,0xff,0x8f] +; CHECK: ldxdw r0, [r1 + 0] # encoding: [0x79,0x10,0x00,0x00,0x00,0x00,0x00,0x00] %2 = alloca i64, align 8 %3 = bitcast i64* %2 to i8* store volatile i64 590618314553, i64* %2, align 8 diff --git a/llvm/test/CodeGen/SBF/memcpy-expand-in-order.ll b/llvm/test/CodeGen/SBF/memcpy-expand-in-order.ll index bec8bec61b13ac..2c59a27aab5967 100644 --- a/llvm/test/CodeGen/SBF/memcpy-expand-in-order.ll +++ b/llvm/test/CodeGen/SBF/memcpy-expand-in-order.ll @@ -66,13 +66,13 @@ entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %0, i8* align 8 %1, i64 27, i1 false) ret void } -; CHECK: [[SCRATCH_REG:r[0-9]]] = *(u64 *)([[SRC_REG:r[0-9]]] + 0) -; CHECK: *(u64 *)([[DST_REG:r[0-9]]] + 0) = [[SCRATCH_REG]] -; CHECK: [[SCRATCH_REG]] = *(u64 *)([[SRC_REG]] + 8) -; CHECK: *(u64 *)([[DST_REG]] + 8) = [[SCRATCH_REG]] -; CHECK: [[SCRATCH_REG]] = *(u64 *)([[SRC_REG]] + 16) -; CHECK: *(u64 *)([[DST_REG]] + 16) = [[SCRATCH_REG]] -; CHECK: [[SCRATCH_REG]] = *(u16 *)([[SRC_REG]] + 24) -; CHECK: *(u16 *)([[DST_REG]] + 24) = [[SCRATCH_REG]] -; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 26) -; CHECK: *(u8 *)([[DST_REG]] + 26) = [[SCRATCH_REG]] +; CHECK: ldxdw [[SCRATCH_REG:r[0-9]]], [[[SRC_REG:r[0-9]]] + 0] +; CHECK: stxdw [[[DST_REG:r[0-9]]] + 0], [[SCRATCH_REG]] +; CHECK: ldxdw [[SCRATCH_REG]], [[[SRC_REG]] + 8] +; CHECK: stxdw [[[DST_REG]] + 8], [[SCRATCH_REG]] +; CHECK: ldxdw [[SCRATCH_REG]], [[[SRC_REG]] + 16] +; CHECK: stxdw [[[DST_REG]] + 16], [[SCRATCH_REG]] +; CHECK: ldxh [[SCRATCH_REG]], [[[SRC_REG]] + 24] +; CHECK: stxh [[[DST_REG]] + 24], [[SCRATCH_REG]] +; CHECK: ldxb [[SCRATCH_REG]], [[[SRC_REG]] + 26] +; CHECK: stxb [[[DST_REG]] + 26], [[SCRATCH_REG]] diff --git a/llvm/test/CodeGen/SBF/ninline_asm.ll b/llvm/test/CodeGen/SBF/ninline_asm.ll new file mode 100644 index 00000000000000..f3412ac0b90ed4 --- /dev/null +++ b/llvm/test/CodeGen/SBF/ninline_asm.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=sbf -verify-machineinstrs | FileCheck %s + +@g = common global [2 x i32] zeroinitializer, align 4 + +; Function Attrs: nounwind +define i32 @test(i8* nocapture readnone %ctx) local_unnamed_addr #0 { +entry: + %a = alloca i32, align 4 + %0 = bitcast i32* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0) #2 + store i32 4, i32* %a, align 4 + tail call void asm sideeffect "ldabsh $0", "i"(i32 2) #2 +; CHECK: ldabsh 2 + tail call void asm sideeffect "ldindh $0", "r"(i32 4) #2 +; CHECK: ldindh r1 + %1 = tail call i32 asm sideeffect "mov64 $0, $1", "=r,i"(i32 4) #2 +; CHECK: mov64 r1, 4 + %2 = tail call i32 asm sideeffect "lddw $0, $1", "=r,i"(i64 333333333333) #2 +; CHECK: lddw r1, 333333333333 + %3 = call i32 asm sideeffect "ldxh $0, [$1]", "=r,*m"(i32* elementtype(i32) nonnull %a) #2 +; CHECK: ldxh r1, [r10 - 4] + %4 = call i32 asm sideeffect "ldxw $0, [$1]", "=r,*m"(i32* elementtype(i32) getelementptr inbounds ([2 x i32], [2 x i32]* @g, i64 0, i64 1)) #2 +; CHECK: lddw r1, g +; CHECK: ldxw r0, [r1 + 4] + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0) #2 + ret i32 %4 +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 + +attributes #0 = { nounwind } +attributes #1 = { argmemonly nounwind } +attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/SBF/objdump_atomics.ll b/llvm/test/CodeGen/SBF/objdump_atomics.ll index b87a3ae25a7e9e..d6f594a509aa81 100644 --- a/llvm/test/CodeGen/SBF/objdump_atomics.ll +++ b/llvm/test/CodeGen/SBF/objdump_atomics.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=sbf -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s ; CHECK-LABEL: test_load_add_32 -; CHECK: r3 = *(u32 *)(r1 + 0) -; CHECK: r3 += r2 -; CHECK: *(u32 *)(r1 + 0) = r3 +; CHECK: ldxw r3, [r1 + 0] +; CHECK: add64 r3, r2 +; CHECK: stxw [r1 + 0], r3 define void @test_load_add_32(i32* %p, i32 zeroext %v) { entry: atomicrmw add i32* %p, i32 %v seq_cst @@ -11,9 +11,9 @@ entry: } ; CHECK-LABEL: test_load_add_64 -; CHECK: r3 = *(u64 *)(r1 + 0) -; CHECK: r3 += r2 -; CHECK: *(u64 *)(r1 + 0) = r3 +; CHECK: ldxdw r3, [r1 + 0] +; CHECK: add64 r3, r2 +; CHECK: stxdw [r1 + 0], r3 define void @test_load_add_64(i64* %p, i64 zeroext %v) { entry: atomicrmw add i64* %p, i64 %v seq_cst diff --git a/llvm/test/CodeGen/SBF/objdump_cond_op.ll b/llvm/test/CodeGen/SBF/objdump_cond_op.ll index dab1dfb9d1c18b..1a9be7dbd5f9d0 100644 --- a/llvm/test/CodeGen/SBF/objdump_cond_op.ll +++ b/llvm/test/CodeGen/SBF/objdump_cond_op.ll @@ -25,40 +25,40 @@ define i32 @test(i32, i32) local_unnamed_addr #0 { %6 = shl i32 %5, 1 %7 = mul i32 %6, %5 br label %13 -; CHECK: r1 <<= 32 -; CHECK: r1 >>= 32 -; CHECK: if r1 != 2 goto +6 +; CHECK: lsh64 r1, 32 +; CHECK: rsh64 r1, 32 +; CHECK: jne r1, 2, +6 ;