diff --git a/Cargo.toml b/Cargo.toml
index 15ad670..d46f6e4 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -18,4 +18,4 @@ categories = ["os", "hardware-support", "memory-management", "no-std"]
 
 [patch.crates-io]
 # todo: update to new version of `memory_addr` on `crates.io` once it get released
-memory_addr = { git = "https://github.com/arceos-hypervisor/memory_addr.git", rev = "2b628c9" }
+memory_addr = { git = "https://github.com/arceos-org/memory_addr.git", rev = "46c06e5" }
diff --git a/page_table_entry/Cargo.toml b/page_table_entry/Cargo.toml
index f7d9c6e..41093e8 100644
--- a/page_table_entry/Cargo.toml
+++ b/page_table_entry/Cargo.toml
@@ -16,7 +16,7 @@ arm-el2 = []
 
 [dependencies]
 bitflags = "2.6"
-memory_addr = "0.2"
+memory_addr = "0.3"
 
 [target.'cfg(any(target_arch = "aarch64", doc))'.dependencies]
 aarch64-cpu = "9.4"
diff --git a/page_table_multiarch/Cargo.toml b/page_table_multiarch/Cargo.toml
index 29a10fe..4c9654b 100644
--- a/page_table_multiarch/Cargo.toml
+++ b/page_table_multiarch/Cargo.toml
@@ -13,7 +13,7 @@ categories.workspace = true
 
 [dependencies]
 log = "0.4"
-memory_addr = "0.2"
+memory_addr = "0.3"
 page_table_entry = { path = "../page_table_entry", version = "0.3" }
 
 [target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
diff --git a/page_table_multiarch/README.md b/page_table_multiarch/README.md
index f0d580c..d8a15f6 100644
--- a/page_table_multiarch/README.md
+++ b/page_table_multiarch/README.md
@@ -30,7 +30,7 @@ Currently supported architectures and page table structures:
 ## Examples (x86_64)
 
 ```rust
-use memory_addr::{PhysAddr, VirtAddr};
+use memory_addr::{MemoryAddr, PhysAddr, VirtAddr};
 use page_table_multiarch::x86_64::{X64PageTable};
 use page_table_multiarch::{MappingFlags, PagingHandler, PageSize};
 
diff --git a/page_table_multiarch/src/bits64.rs b/page_table_multiarch/src/bits64.rs
index 118a4da..2e45689 100644
--- a/page_table_multiarch/src/bits64.rs
+++ b/page_table_multiarch/src/bits64.rs
@@ -3,7 +3,7 @@ extern crate alloc;
 use crate::{GenericPTE, PagingHandler, PagingMetaData};
 use crate::{MappingFlags, PageSize, PagingError, PagingResult, TlbFlush, TlbFlushAll};
 use core::marker::PhantomData;
-use memory_addr::{PhysAddr, PAGE_SIZE_4K};
+use memory_addr::{PhysAddr, PAGE_SIZE_4K, MemoryAddr};
 
 const ENTRY_COUNT: usize = 512;
 
@@ -139,7 +139,7 @@ impl<M: PagingMetaData, PTE: GenericPTE, H: PagingHandler> PageTable64<M, PTE, H
             return Err(PagingError::NotMapped);
         }
         let off = size.align_offset(vaddr.into());
-        Ok((entry.paddr() + off, entry.flags(), size))
+        Ok((entry.paddr().add(off), entry.flags(), size))
     }
 
     /// Maps a contiguous virtual memory region to a contiguous physical memory