v1.33.0

• Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
• Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings
• Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions
• Several other minor fixes and improvements

v1.32.1

Changelog:

• Added support for Intel FRED and LKGS instructions
• Improved CMake build and install process:
  • Users no longer need to implement nd_vsnprintf_s and nd_memset (the old behavior can be enabled at build time)
  • Easier integration with other CMake projects: just use find_package/add_subdirectory/FetchContent and link against bddisasm::bddisasm or bddisasm::bdshemu

v1.31.8

Fixed RFLAGS setting issues for arithmetic and shift instructions.

v1.31.7

Added support for AESDEC, AESDECLAST and AESIMC emulation in bdshemu
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v1.31.2

On AMD, operand size is never forced to 64 bit - instead, it only defaults to 64 bit, which means that 0x66 can be used to encode 16 bit version of the instructions. By supplying the ND_VEND_AMD vendor hint, bddisasm will provide the operand size specific to AMD.
Added missing Default 64 flag for the ENTER instruction.
Fixed INTO and DMINT decoding in 64 bit mode (they are invalid).

v1.31.0

Initial bddisasm release.