diff --git a/CMakeLists.txt b/CMakeLists.txt index 3c6d536a0..5658b84aa 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -66,7 +66,7 @@ set(FREERTOS_PLUS_TCP_NETWORK_IF_LIST POSIX WIN_PCAP # Native Linux & Windows respectively RX SH2A - STM32FXX STM32HXX # ST Micro + STM32 # ST Micro MSP432 TM4C XILINX_ULTRASCALE ZYNQ # AMD/Xilinx @@ -107,8 +107,7 @@ if(NOT FREERTOS_PLUS_TCP_NETWORK_IF IN_LIST FREERTOS_PLUS_TCP_NETWORK_IF_LIST ) " PIC32MZEF_WIFI Target: pic32mzef Wifi Tested: TODO\n" " RX Target: RX Tested: TODO\n" " SH2A Target: SH2A Tested: TODO\n" - " STM32FXX Target: STM32Fxx Tested: TODO\n" - " STM32HXX Target: STM32Hxx Tested: TODO\n" + " STM32 Target: STM32 Tested: TODO\n" " MSP432 Target: MSP432 Tested: TODO\n" " TM4C Target: TM4C Tested: TODO\n" " WIN_PCAP Target: Windows Tested: TODO\n" diff --git a/source/portable/NetworkInterface/CMakeLists.txt b/source/portable/NetworkInterface/CMakeLists.txt index dcf98604d..923e0cccb 100644 --- a/source/portable/NetworkInterface/CMakeLists.txt +++ b/source/portable/NetworkInterface/CMakeLists.txt @@ -45,8 +45,7 @@ add_subdirectory(mw300_rd) add_subdirectory(pic32mzef) add_subdirectory(RX) add_subdirectory(SH2A) -add_subdirectory(STM32Fxx) -add_subdirectory(STM32Hxx) +add_subdirectory(STM32) add_subdirectory(ThirdParty/MSP432) add_subdirectory(TM4C) add_subdirectory(WinPCap) diff --git a/source/portable/NetworkInterface/STM32Hxx/CMakeLists.txt b/source/portable/NetworkInterface/STM32/CMakeLists.txt similarity index 75% rename from source/portable/NetworkInterface/STM32Hxx/CMakeLists.txt rename to source/portable/NetworkInterface/STM32/CMakeLists.txt index 016f1b927..4d019b1c2 100644 --- a/source/portable/NetworkInterface/STM32Hxx/CMakeLists.txt +++ b/source/portable/NetworkInterface/STM32/CMakeLists.txt @@ -1,4 +1,4 @@ -if (NOT ( (FREERTOS_PLUS_TCP_NETWORK_IF STREQUAL "STM32HXX") ) ) +if (NOT ( (FREERTOS_PLUS_TCP_NETWORK_IF STREQUAL "STM32") ) ) return() endif() @@ -8,9 +8,6 @@ add_library( freertos_plus_tcp_network_if STATIC ) target_sources( freertos_plus_tcp_network_if PRIVATE NetworkInterface.c - stm32h7xx_hal_eth.h - stm32hxx_hal_eth.c - stm32hxx_hal_eth.h ) target_link_libraries( freertos_plus_tcp_network_if diff --git a/source/portable/NetworkInterface/STM32/NetworkInterface.c b/source/portable/NetworkInterface/STM32/NetworkInterface.c new file mode 100644 index 000000000..17392a311 --- /dev/null +++ b/source/portable/NetworkInterface/STM32/NetworkInterface.c @@ -0,0 +1,863 @@ +/* + * Some constants, hardware definitions and comments taken from ST's HAL driver + * library, COPYRIGHT(c) 2015 STMicroelectronics. + */ + +/* + * FreeRTOS+TCP + * Copyright (C) 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" +#include "phyHandling.h" + +/* ST includes. */ +#if defined(STM32F4xx) + #include "stm32f4xx_hal_eth.h" +#elif defined(STM32F7xx) + #include "stm32f7xx_hal_eth.h" +#elif defined(STM32H7xx) + #include "stm32h7xx_hal_eth.h" +#elif defined(STM32H5xx) + /* #include "stm32h5xx_hal_eth.h" */ + #include "stm32h5xx_hal.h" +#else + #error Unknown STM32 Family for NetworkInterface +#endif + +/*-----------------------------------------------------------*/ + +/* TODO: Should these be moved to FreeRTOSIPConfigDefaults.h? */ +#ifndef ipconfigETHERNET_AN_ENABLE + #define ipconfigETHERNET_AN_ENABLE 1 +#endif + +#if ( ipconfigETHERNET_AN_ENABLE == 0 ) + #ifndef ipconfigETHERNET_USE_100MB + #define ipconfigETHERNET_USE_100MB 1 + #endif + + #ifndef ipconfigETHERNET_USE_FULL_DUPLEX + #define ipconfigETHERNET_USE_FULL_DUPLEX 1 + #endif +#endif + +#ifndef ipconfigETHERNET_AUTO_CROSS_ENABLE + #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1 +#endif + +#if ( ipconfigETHERNET_AUTO_CROSS_ENABLE == 0 ) + #ifndef ipconfigETHERNET_CROSSED_LINK + #define ipconfigETHERNET_CROSSED_LINK 0 + #endif +#endif + +#ifndef ipconfigUSE_RMII + #define ipconfigUSE_RMII 1 +#endif + +#ifndef ETH_RX_BUF_SIZE + #define ETH_RX_BUF_SIZE 1524 +#endif + +#ifndef ETH_TX_BUF_SIZE + #define ETH_TX_BUF_SIZE 1524 +#endif + +/*-----------------------------------------------------------*/ + +/* TODO: Verify this size */ +#define NETWORK_BUFFER_SIZE ( ( ( ETH_RX_BUF_SIZE + ipBUFFER_PADDING ) + 7 ) & ~0x7UL ) + +#define EMAC_IF_RX_EVENT 1UL +#define EMAC_IF_TX_EVENT 2UL +#define EMAC_IF_ERR_EVENT 4UL +#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT ) + +typedef enum +{ + eMACInit, + eMACPass, + eMACFailed +} eMAC_INIT_STATUS_TYPE; + +/*-----------------------------------------------------------*/ + +static BaseType_t prvNetworkInterfaceInput( void ); + +static void prvEMACHandlerTask( void * pvParameters ) __attribute__((__noreturn__)); + +static BaseType_t prvAcceptPacket( const uint8_t * const pucEthernetBuffer ); + +static BaseType_t prvPhyReadReg( BaseType_t xAddress, BaseType_t xRegister, uint32_t * pulValue ); + +static BaseType_t prvPhyWriteReg( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue ); + +static void prvEthernetUpdateConfig( void ); + +/*-----------------------------------------------------------*/ + +static ETH_HandleTypeDef xEthHandle; + +static ETH_DMADescTypeDef DMARxDscrTab[ ETH_RX_DESC_CNT ] __attribute__( ( section( ".RxDescripSection" ) ) ); + +/* TODO: implement ( ipconfigZERO_COPY_RX_DRIVER == 0 ) */ +/*#if ( ipconfigZERO_COPY_RX_DRIVER == 0 ) + __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RX_DESC_CNT ][ ETH_RX_BUF_SIZE ] __ALIGN_END; +#endif*/ + +static ETH_DMADescTypeDef DMATxDscrTab[ ETH_TX_DESC_CNT ] __attribute__( ( section( ".TxDescripSection" ) ) ); + +/* TODO: implement ( ipconfigZERO_COPY_TX_DRIVER == 0 ) */ +/*#if ( ipconfigZERO_COPY_TX_DRIVER == 0 ) + __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TX_DESC_CNT ][ ETH_TX_BUF_SIZE ] __ALIGN_END; +#endif*/ + +static ETH_TxPacketConfig xTxConfig; + +/* TODO: implement ( ipconfigUSE_LLMNR != 0 ) */ +/*#if ( ipconfigUSE_LLMNR != 0 ) + static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC }; +#endif*/ + +static NetworkInterface_t * pxMyInterface = NULL; + +static TaskHandle_t xEMACTaskHandle; + +static SemaphoreHandle_t xTxMutex; + +/* TODO: uncomment this after chaining Tx Buffers */ +/* xTxDescSem is not useful unless xTxBuffer.next != NULL */ +/* static SemaphoreHandle_t xTxDescSem; */ + +static EthernetPhy_t xPhyObject; + +static const PhyProperties_t xPHYProperties = +{ + #if ( ipconfigETHERNET_AN_ENABLE != 0 ) + .ucSpeed = PHY_SPEED_AUTO, + .ucDuplex = PHY_DUPLEX_AUTO, + #else + #if ( ipconfigETHERNET_USE_100MB != 0 ) + .ucSpeed = PHY_SPEED_100, + #else + .ucSpeed = PHY_SPEED_10, + #endif + + #if ( ipconfigETHERNET_USE_FULL_DUPLEX != 0 ) + .ucDuplex = PHY_DUPLEX_FULL, + #else + .ucDuplex = PHY_DUPLEX_HALF, + #endif + #endif + + #if ( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 ) + .ucMDI_X = PHY_MDIX_AUTO, + #elif ( ipconfigETHERNET_CROSSED_LINK != 0 ) + .ucMDI_X = PHY_MDIX_CROSSED, + #else + .ucMDI_X = PHY_MDIX_DIRECT, + #endif +}; + +/*-----------------------------------------------------------*/ + +void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) +{ + static uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ][ NETWORK_BUFFER_SIZE ] __attribute__( ( aligned( 4 ), section( ".EthBuffersSection" ) ) ); + + for( size_t ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ ) + { + pxNetworkBuffers[ ul ].pucEthernetBuffer = &( ucNetworkPackets[ ul ][ ipBUFFER_PADDING ] ); + *( ( uint32_t * ) &( ucNetworkPackets[ ul ][ 0 ] ) ) = ( uint32_t ) ( &( pxNetworkBuffers[ ul ] ) ); + } +} + +/*-----------------------------------------------------------*/ + +static BaseType_t xSTM32_GetPhyLinkStatus( NetworkInterface_t * pxInterface ) +{ + BaseType_t xReturn = pdFAIL; + + if( xPhyObject.ulLinkStatusMask != 0U ) + { + xReturn = pdPASS; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t xSTM32_NetworkInterfaceInitialise( NetworkInterface_t * pxInterface ) +{ + BaseType_t xResult = pdFAIL; + BaseType_t xPhyResult; + HAL_StatusTypeDef xHalResult; + NetworkEndPoint_t * pxEndPoint; + + static eMAC_INIT_STATUS_TYPE xMacInitStatus = eMACInit; + + if( xMacInitStatus == eMACInit ) + { + if( xEMACTaskHandle == NULL ) + { + #if ( configSUPPORT_STATIC_ALLOCATION != 0 ) + static StaticSemaphore_t xTxMutexBuf; + xTxMutex = xSemaphoreCreateMutexStatic( &xTxMutexBuf ); + + /* TODO: uncomment this after chaining Tx Buffers */ + /* static StaticSemaphore_t xTxDescSemBuf; + xTxDescSem = xSemaphoreCreateCountingStatic( ( UBaseType_t ) ETH_TX_DESC_CNT, ( UBaseType_t ) ETH_TX_DESC_CNT, &xTxDescSemBuf ); */ + + static StackType_t uxEMACTaskStack[ ( 2 * configMINIMAL_STACK_SIZE ) ]; + static StaticTask_t xEMACTaskTCB; + /* TODO: Allow stack size & priority to be defined */ + xEMACTaskHandle = xTaskCreateStatic( + prvEMACHandlerTask, + "EMAC", + ( 2 * configMINIMAL_STACK_SIZE ), + NULL, + ( configMAX_PRIORITIES - 1 ), + uxEMACTaskStack, + &xEMACTaskTCB + ); + #else + xTxMutex = xSemaphoreCreateMutex(); + + /* TODO: uncomment this after chaining Tx Buffers */ + /*xTxDescSem = xSemaphoreCreateCounting( + ( UBaseType_t ) ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS, + ( UBaseType_t ) ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + );*/ + + /* TODO: Allow stack size & priority to be defined */ + ( void ) xTaskCreate( + prvEMACHandlerTask, + "EMAC", + ( 2 * configMINIMAL_STACK_SIZE ), + NULL, + ( configMAX_PRIORITIES - 1 ), + &xEMACTaskHandle + ); + #endif + configASSERT( xTxMutex ); + vQueueAddToRegistry( xTxMutex, "TXMutex" ); + + /* TODO: uncomment this after chaining Tx Buffers */ + /*configASSERT( xTxDescSem ); + vQueueAddToRegistry( xTxDescSem, "xTxDescSem" );*/ + + configASSERT( xEMACTaskHandle ); + } + + if( xEthHandle.Instance == NULL ) + { + pxMyInterface = pxInterface; + + pxEndPoint = FreeRTOS_FirstEndPoint( pxInterface ); + configASSERT( pxEndPoint != NULL ); + + xEthHandle.Instance = ETH; + xEthHandle.Init.MACAddr = ( uint8_t * ) pxEndPoint->xMACAddress.ucBytes; + xEthHandle.Init.MediaInterface = ( ipconfigUSE_RMII != 0 ) ? HAL_ETH_RMII_MODE : HAL_ETH_MII_MODE; + xEthHandle.Init.TxDesc = DMATxDscrTab; + xEthHandle.Init.RxDesc = DMARxDscrTab; + /* TODO: Verify RxBuffLen size */ + xEthHandle.Init.RxBuffLen = ETH_RX_BUF_SIZE; + + memset( &DMATxDscrTab, 0, sizeof( DMATxDscrTab ) ); + memset( &DMARxDscrTab, 0, sizeof( DMARxDscrTab ) ); + + #if defined(STM32F7) || defined(STM32F4) + /* This function doesn't get called in Fxx driver */ + HAL_ETH_SetMDIOClockRange( &xEthHandle ); + #endif + + xHalResult = HAL_ETH_Init( &xEthHandle ); + configASSERT( xHalResult == HAL_OK ); + configASSERT( xEthHandle.ErrorCode == HAL_ETH_ERROR_NONE ); + configASSERT( xEthHandle.gState == HAL_ETH_STATE_READY ); + + /* TODO: uncomment & test these */ + /*#if ( ipconfigUSE_LLMNR != 0 ) || ( ipconfigUSE_MDNS != 0 ) + BaseType_t xMACEntry = ETH_MAC_ADDRESS1; + uint8_t pMACAddr[6]; + memset( &pMACAddr, 0, sizeof( pMACAddr ) ); + xHalResult = HAL_ETH_SetSourceMACAddrMatch( &xEthHandle, xMACEntry, pMACAddr ); + configASSERT( xHalResult == HAL_OK ); + #endif + + #if ( ipconfigUSE_MDNS != 0 ) + xHalResult = HAL_ETH_SetSourceMACAddrMatch( &xEthHandle, xMACEntry, ( uint8_t * ) xMDNS_MACAddressIPv4 ); + configASSERT( xHalResult == HAL_OK ); + xMACEntry += 8; + #endif + #if ( ipconfigUSE_LLMNR != 0 ) + xHalResult = HAL_ETH_SetSourceMACAddrMatch( &xEthHandle, xMACEntry, ( uint8_t * ) xLLMNR_MACAddress ); + configASSERT( xHalResult == HAL_OK ); + xMACEntry += 8; + #endif*/ + + memset( &xTxConfig, 0, sizeof( xTxConfig ) ); + xTxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CRCPAD; + xTxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + #if ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + xTxConfig.Attributes |= ETH_TX_PACKETS_FEATURES_CSUM; + xTxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + #else + xTxConfig.ChecksumCtrl = ETH_CHECKSUM_DISABLE; + #endif + xMacInitStatus = eMACPass; + } + } + + if( xMacInitStatus == eMACPass ) + { + vPhyInitialise( &xPhyObject, ( xApplicationPhyReadHook_t ) prvPhyReadReg, ( xApplicationPhyWriteHook_t ) prvPhyWriteReg ); + xPhyResult = xPhyDiscover( &xPhyObject ); + configASSERT( xPhyResult > 0 ); + xPhyResult = xPhyConfigure( &xPhyObject, &xPHYProperties ); + configASSERT( xPhyResult == 0 ); + xPhyResult = xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) ); + configASSERT( xPhyResult == 0 ); + } + + if ( xSTM32_GetPhyLinkStatus( pxInterface ) != pdFAIL ) + { + ETH_MACConfigTypeDef MACConf; + xHalResult = HAL_ETH_GetMACConfig( &xEthHandle , &MACConf ); + configASSERT( xHalResult == HAL_OK ); + MACConf.DuplexMode = ( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL ) ? ETH_FULLDUPLEX_MODE : ETH_HALFDUPLEX_MODE; + MACConf.Speed = ( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 ) ? ETH_SPEED_10M : ETH_SPEED_100M; + MACConf.ChecksumOffload = ( FunctionalState ) ( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM != 0 ); + xHalResult = HAL_ETH_SetMACConfig( &xEthHandle, &MACConf ); + configASSERT( xHalResult == HAL_OK ); + xHalResult = HAL_ETH_Start_IT( &xEthHandle ); + configASSERT( xHalResult == HAL_OK ); + xResult = pdPASS; + } + + return xResult; +} + +/*-----------------------------------------------------------*/ + +static BaseType_t xSTM32_NetworkInterfaceOutput( NetworkInterface_t * pxInterface, + NetworkBufferDescriptor_t * const pxDescriptor, + BaseType_t xReleaseAfterSend ) +{ + BaseType_t xResult = pdFAIL; + /* TODO: ipconfigZERO_COPY_TX_DRIVER */ + + if( pxDescriptor != NULL ) + { + if( xSTM32_GetPhyLinkStatus( pxInterface ) != pdFAIL ) + { + /* TODO: Tx Optimization by setting .next? */ + ETH_BufferTypeDef xTxBuffer = { + .buffer = ( uint8_t * ) pxDescriptor->pucEthernetBuffer, + .len = pxDescriptor->xDataLength, + .next = NULL + }; + + xTxConfig.Length = xTxBuffer.len; + xTxConfig.TxBuffer = &xTxBuffer; + xTxConfig.pData = pxDescriptor; + + if( xTxConfig.Length <= ETH_TX_BUF_SIZE - ipBUFFER_PADDING ) + { + /* TODO: uncomment this after chaining Tx Buffers */ + /* if( xSemaphoreTake( xTxDescSem, pdMS_TO_TICKS( 100U ) ) != pdFALSE ) + { */ + if( xSemaphoreTake( xTxMutex, pdMS_TO_TICKS( 20U ) ) != pdFALSE ) + { + xReleaseAfterSend = pdFALSE; + if( HAL_ETH_Transmit_IT( &xEthHandle, &xTxConfig ) == HAL_OK ) + { + xResult = pdPASS; + } + else + { + configASSERT( xEthHandle.ErrorCode != HAL_ETH_ERROR_PARAM ); + configASSERT( xEthHandle.gState == HAL_ETH_STATE_STARTED ); + } + xSemaphoreGive( xTxMutex ); + } + /* TODO: uncomment this after chaining Tx Buffers */ + /* else + { + xSemaphoreGive( xTxDescSem ); + } + } */ + } + } + + if( xReleaseAfterSend != pdFALSE ) + { + vReleaseNetworkBufferAndDescriptor( pxDescriptor ); + } + } + + return xResult; +} + +/*-----------------------------------------------------------*/ + +NetworkInterface_t * pxSTM32_FillInterfaceDescriptor( BaseType_t xEMACIndex, + NetworkInterface_t * pxInterface ) +{ + static char pcName[ 17 ]; + +/* This function pxSTM32Hxx_FillInterfaceDescriptor() adds a network-interface. + * Make sure that the object pointed to by 'pxInterface' + * is declared static or global, and that it will remain to exist. */ + + snprintf( pcName, sizeof( pcName ), "eth%u", ( unsigned ) xEMACIndex ); + + memset( pxInterface, '\0', sizeof( *pxInterface ) ); + pxInterface->pcName = pcName; /* Just for logging, debugging. */ + pxInterface->pvArgument = ( void * ) xEMACIndex; /* Has only meaning for the driver functions. */ + pxInterface->pfInitialise = xSTM32_NetworkInterfaceInitialise; + pxInterface->pfOutput = xSTM32_NetworkInterfaceOutput; + pxInterface->pfGetPhyLinkStatus = xSTM32_GetPhyLinkStatus; + + FreeRTOS_AddNetworkInterface( pxInterface ); + + return pxInterface; +} + +/*-----------------------------------------------------------*/ + +static BaseType_t prvNetworkInterfaceInput( void ) +{ + /* TODO: ipconfigZERO_COPY_RX_DRIVER */ + BaseType_t xResult = 0; + NetworkBufferDescriptor_t * pStartDescriptor = NULL; + while ( HAL_ETH_ReadData( &xEthHandle, ( void ** ) &pStartDescriptor ) == HAL_OK ) + { + xResult++; + if ( pStartDescriptor != NULL ) + { + const IPStackEvent_t xRxEvent = { + .eEventType = eNetworkRxEvent, + .pvData = ( void * ) pStartDescriptor + }; + + pStartDescriptor->pxInterface = pxMyInterface; + pStartDescriptor->pxEndPoint = FreeRTOS_MatchingEndpoint( pxMyInterface, pStartDescriptor->pucEthernetBuffer ); + + if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 0U ) != pdPASS ) + { + iptraceETHERNET_RX_EVENT_LOST(); + NetworkBufferDescriptor_t * pxDescriptorToClear = pStartDescriptor; + do { + #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + NetworkBufferDescriptor_t * pxNext = pxDescriptorToClear->pxNextBuffer; + #else + NetworkBufferDescriptor_t * pxNext = NULL; + #endif + vReleaseNetworkBufferAndDescriptor( pxDescriptorToClear ); + pxDescriptorToClear = pxNext; + } while( pxDescriptorToClear != NULL ); + } + } + } + configASSERT( xEthHandle.ErrorCode != HAL_ETH_ERROR_PARAM ); + configASSERT( xEthHandle.gState == HAL_ETH_STATE_STARTED ); + return ( BaseType_t ) ( xResult > 0 ); +} + +/*-----------------------------------------------------------*/ + +static void prvEMACHandlerTask( void * pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + BaseType_t xResult = 0U; + + uint32_t ulISREvents = 0U; + + if ( xTaskNotifyWait( 0U, EMAC_IF_ALL_EVENT, &ulISREvents, pdMS_TO_TICKS( 500UL ) ) == pdTRUE ) + { + if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 ) + { + iptraceNETWORK_INTERFACE_RECEIVE(); + xResult = prvNetworkInterfaceInput(); + } + + if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 ) + { + iptraceNETWORK_INTERFACE_TRANSMIT(); + if( xSemaphoreTake( xTxMutex, pdMS_TO_TICKS( 100U ) ) != pdFALSE ) + { + HAL_StatusTypeDef xHalResult = HAL_ETH_ReleaseTxPacket( &xEthHandle ); + configASSERT( xHalResult == HAL_OK ); + xSemaphoreGive( xTxMutex ); + } + } + + if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 ) + { + /* TODO: Does this recover from fatal bus error? */ + HAL_ETH_Stop_IT( &xEthHandle ); + /* FreeRTOS_NetworkDown() + if( xSemaphoreTake( xTxMutex, pdMS_TO_TICKS( 100U ) ) != pdFALSE ) + { + configASSERT( HAL_ETH_ReleaseTxPacket( &xEthHandle ) == HAL_OK ); + xSemaphoreGive( xTxMutex ); + }*/ + HAL_ETH_Start_IT( &xEthHandle ); + } + } + + if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 ) + { + prvEthernetUpdateConfig(); + } + } +} + +/*-----------------------------------------------------------*/ + +static BaseType_t prvAcceptPacket( const uint8_t * const pucEthernetBuffer ) +{ + BaseType_t xResult = pdFALSE; + + do { + uint32_t pErrorCode = 0; + HAL_StatusTypeDef xHalResult = HAL_ETH_GetRxDataErrorCode( &xEthHandle, &pErrorCode ); + configASSERT( xHalResult == HAL_OK ); + if ( pErrorCode != 0 ) + { + break; + } + + const ProtocolPacket_t * pxProtPacket = ( const ProtocolPacket_t * ) pucEthernetBuffer; + + const uint16_t usFrameType = pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType; + + #if ( ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 0 ) + if( usFrameType != ipARP_FRAME_TYPE && usFrameType != ipIPv4_FRAME_TYPE) + { + break; + } + #endif + #if ( ipconfigETHERNET_DRIVER_FILTERS_PACKETS != 0 ) + if( usFrameType == ipIPv4_FRAME_TYPE ) + { + const IPHeader_t * pxIPHeader = &( pxProtPacket->xTCPPacket.xIPHeader ); + + if( ( pxIPHeader->usFragmentOffset & ipFRAGMENT_OFFSET_BIT_MASK ) != 0U ) + { + break; + } + + if( ( pxIPHeader->ucVersionHeaderLength < 0x45 ) || ( pxIPHeader->ucVersionHeaderLength > 0x4F ) ) + { + break; + } + + const uint32_t ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress; + + if( ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) && ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) && ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) ) + { + break; + } + + if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP ) + { + if( ( xPortHasUDPSocket( pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort ) == pdFALSE )) + { + break; + } + /* TODO: uncomment these & test */ + /*#if ipconfigUSE_LLMNR == 1 + && ( usDestinationPort != ipLLMNR_PORT ) && + ( usSourcePort != ipLLMNR_PORT ) + #endif + #if ipconfigUSE_MDNS == 1 + && ( usDestinationPort != ipMDNS_PORT ) && + ( usSourcePort != ipMDNS_PORT ) + #endif + #if ipconfigUSE_NBNS == 1 + && ( usDestinationPort != ipNBNS_PORT ) && + ( usSourcePort != ipNBNS_PORT ) + #endif + #if ipconfigUSE_DNS == 1 + && ( usSourcePort != ipDNS_PORT ) + #endif + )*/ + } + } + #endif + + xResult = pdTRUE; + } while( ipFALSE_BOOL ); + + return xResult; +} + +/*-----------------------------------------------------------*/ + +static BaseType_t prvPhyReadReg( BaseType_t xAddress, BaseType_t xRegister, uint32_t * pulValue ) +{ + BaseType_t iResult = -1; + if( HAL_ETH_ReadPHYRegister( &xEthHandle, ( uint32_t ) xAddress, ( uint32_t ) xRegister, pulValue ) == HAL_OK ) + { + iResult = 0; + } + return iResult; +} + +/*-----------------------------------------------------------*/ + +static BaseType_t prvPhyWriteReg( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue ) +{ + BaseType_t iResult = -1; + if( HAL_ETH_WritePHYRegister( &xEthHandle, ( uint32_t ) xAddress, ( uint32_t ) xRegister, ulValue ) == HAL_OK ) + { + iResult = 0; + } + return iResult; +} + +/*-----------------------------------------------------------*/ + +static void prvEthernetUpdateConfig( void ) +{ + BaseType_t xPhyResult; + HAL_StatusTypeDef xHalResult; + /* TODO: xEthHandle.gState == Check HAL_ETH_STATE_STARTED */ + + if( xSTM32_GetPhyLinkStatus( pxMyInterface ) != pdFAIL ) + { + ETH_MACConfigTypeDef MACConf; + xHalResult = HAL_ETH_GetMACConfig( &xEthHandle , &MACConf ); + configASSERT( xHalResult == HAL_OK ); + + #if ( ipconfigETHERNET_AN_ENABLE != 0 ) + xPhyResult = xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) ); + configASSERT( xPhyResult == 0 ); + + MACConf.DuplexMode = ( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL ) ? ETH_FULLDUPLEX_MODE : ETH_HALFDUPLEX_MODE; + MACConf.Speed = ( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 ) ? ETH_SPEED_10M : ETH_SPEED_100M; + + xHalResult = HAL_ETH_SetMACConfig( &xEthHandle, &MACConf ); + configASSERT( xHalResult == HAL_OK ); + #else + xPhyObject.xPhyPreferences.ucDuplex = ( MACConf.DuplexMode == ETH_FULLDUPLEX_MODE ) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF; + xPhyObject.xPhyPreferences.ucSpeed = ( MACConf.Speed == ETH_SPEED_10M ) ? PHY_SPEED_10 : PHY_SPEED_100; + xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO; + xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) ); + #endif + + if( xSTM32_GetPhyLinkStatus( pxMyInterface ) != pdFAIL ) + { + ( void ) HAL_ETH_Start_IT( &xEthHandle ); + } + } + else + { + if( HAL_ETH_Stop_IT( &xEthHandle ) == HAL_OK ) + { + /* iptraceNETWORK_INTERFACE_STATUS_CHANGE(); */ + if( xSemaphoreTake( xTxMutex, pdMS_TO_TICKS( 100U ) ) != pdFALSE ) + { + xHalResult = HAL_ETH_ReleaseTxPacket( &xEthHandle ); + configASSERT( xHalResult == HAL_OK ); + memset( &DMATxDscrTab, 0, sizeof( DMATxDscrTab ) ); + ( void ) xSemaphoreGive( xTxMutex ); + } + } + } +} + +/*-----------------------------------------------------------*/ + +void ETH_IRQHandler( void ) +{ + HAL_ETH_IRQHandler( &xEthHandle ); +} + +/*-----------------------------------------------------------*/ + +void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ) +{ + static size_t uxMostRXDescsUsed = 0U; + + const size_t uxRxUsed = heth->RxDescList.RxDescCnt; + + if( uxMostRXDescsUsed < uxRxUsed ) + { + uxMostRXDescsUsed = uxRxUsed; + } + + if( xEMACTaskHandle != NULL ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xTaskNotifyFromISR( xEMACTaskHandle, EMAC_IF_RX_EVENT, eSetBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } +} + +/*-----------------------------------------------------------*/ + +void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ) +{ + static size_t uxMostTXDescsUsed = 0U; + + const size_t uxTxUsed = heth->TxDescList.BuffersInUse; + + if( uxMostTXDescsUsed < uxTxUsed ) + { + uxMostTXDescsUsed = uxTxUsed; + } + + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xTaskNotifyFromISR( xEMACTaskHandle, EMAC_IF_TX_EVENT, eSetBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); +} + +/*-----------------------------------------------------------*/ + +void HAL_ETH_ErrorCallback( ETH_HandleTypeDef *heth ) +{ + if( HAL_ETH_GetError( heth ) & HAL_ETH_ERROR_DMA ) + { + if( HAL_ETH_GetDMAError( heth ) ) + { + if( heth->gState == HAL_ETH_STATE_ERROR ) + { + /* fatal bus error occurred */ + /* F7 - ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS */ + /* H7 - ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS */ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xTaskNotifyFromISR( xEMACTaskHandle, EMAC_IF_ERR_EVENT, eSetBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + else + { + /* F7 - ETH_DMASR_ETS | ETH_DMASR_RWTS | ETH_DMASR_RBUS | ETH_DMASR_AIS */ + /* H7 - ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | ETH_DMACSR_RBU | ETH_DMACSR_AIS */ + /* TODO: Check if allocated in HAL_ETH_RxAllocateCallback before error interrupt, then release in task */ + /*if( ( HAL_ETH_GetDMAError(heth) & ETH_DMACSR_RBU ) == ETH_DMACSR_RBU ) + { + + }*/ + /* TODO: same as above but for Tx */ + /*if( ( HAL_ETH_GetDMAError(heth) & ETH_DMACSR_TBU ) == ETH_DMACSR_TBU ) + { + xSemaphoreGiveFromISR( xTxDescSem ); + }*/ + } + } + } + + #ifdef STM32H7 + if( HAL_ETH_GetError( heth ) & HAL_ETH_ERROR_MAC ) + { + if( HAL_ETH_GetMACError( heth ) ) + { + + } + } + #endif +} + +/*-----------------------------------------------------------*/ + +void HAL_ETH_RxAllocateCallback( uint8_t **buff ) +{ + /* TODO: Verify this size */ + NetworkBufferDescriptor_t * pxBufferDescriptor = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, pdMS_TO_TICKS( 20U ) ); + if( pxBufferDescriptor != NULL ) + { + *buff = pxBufferDescriptor->pucEthernetBuffer; + } +} + +/*-----------------------------------------------------------*/ + +void HAL_ETH_RxLinkCallback( void **pStart, void **pEnd, uint8_t *buff, uint16_t Length ) +{ + NetworkBufferDescriptor_t * pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( ( const void * ) buff ); + if( pxCurDescriptor != NULL ) + { + if ( prvAcceptPacket( pxCurDescriptor->pucEthernetBuffer ) == pdTRUE ) + { + NetworkBufferDescriptor_t ** pStartDescriptor = ( NetworkBufferDescriptor_t ** ) pStart; + NetworkBufferDescriptor_t ** pEndDescriptor = ( NetworkBufferDescriptor_t ** ) pEnd; + + pxCurDescriptor->xDataLength = Length; + #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + pxCurDescriptor->pxNextBuffer = NULL; + #endif + if( *pStartDescriptor == NULL ) + { + *pStartDescriptor = pxCurDescriptor; + } + #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + else if( pEndDescriptor != NULL ) + { + ( *pEndDescriptor )->pxNextBuffer = pxCurDescriptor; + } + #endif + *pEndDescriptor = pxCurDescriptor; + } + else + { + vReleaseNetworkBufferAndDescriptor( pxCurDescriptor ); + } + } +} + +/*-----------------------------------------------------------*/ + +void HAL_ETH_TxFreeCallback( uint32_t *buff ) +{ + NetworkBufferDescriptor_t * pxNetworkBuffer = ( NetworkBufferDescriptor_t * ) buff; + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + /* TODO: uncomment this after chaining Tx Buffers */ + /* xSemaphoreGive( xTxDescSem ); */ +} + +/*-----------------------------------------------------------*/ diff --git a/source/portable/NetworkInterface/STM32Fxx/CMakeLists.txt b/source/portable/NetworkInterface/STM32Fxx/CMakeLists.txt deleted file mode 100644 index cfe8f1c1f..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -if (NOT ( (FREERTOS_PLUS_TCP_NETWORK_IF STREQUAL "STM32FXX") ) ) - return() -endif() - -#------------------------------------------------------------------------------ -add_library( freertos_plus_tcp_network_if STATIC ) - -target_sources( freertos_plus_tcp_network_if - PRIVATE - NetworkInterface.c - # stm32f2xx_hal_eth.h - # stm32f4xx_hal_eth.h - stm32f7xx_hal_eth.h #TODO: Only one of these ? - stm32fxx_hal_eth.c - stm32fxx_hal_eth.h -) - -target_link_libraries( freertos_plus_tcp_network_if - PUBLIC - freertos_plus_tcp_port - freertos_plus_tcp_network_if_common - PRIVATE - freertos_kernel - freertos_plus_tcp -) diff --git a/source/portable/NetworkInterface/STM32Fxx/NetworkInterface.c b/source/portable/NetworkInterface/STM32Fxx/NetworkInterface.c deleted file mode 100644 index 0b20602ec..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/NetworkInterface.c +++ /dev/null @@ -1,1520 +0,0 @@ -/* - * Some constants, hardware definitions and comments taken from ST's HAL driver - * library, COPYRIGHT(c) 2015 STMicroelectronics. - */ - -/* - * FreeRTOS+TCP - * Copyright (C) 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://aws.amazon.com/freertos - * http://www.FreeRTOS.org - */ - -/* Standard includes. */ -#include -#include -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+TCP includes. */ -#include "FreeRTOS_IP.h" -#include "FreeRTOS_Sockets.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_DNS.h" -#include "FreeRTOS_ARP.h" -#include "NetworkBufferManagement.h" -#include "NetworkInterface.h" -#include "phyHandling.h" -#include "FreeRTOS_Routing.h" - -#include "stm32fxx_hal_eth.h" - -/* ST includes. */ -#if defined( STM32F7xx ) - #include "stm32f7xx_hal.h" - #define CACHE_LINE_SIZE 32u -#elif defined( STM32F4xx ) - #include "stm32f4xx_hal.h" -#elif defined( STM32F2xx ) - #include "stm32f2xx_hal.h" -#elif defined( STM32F1xx ) - #include "stm32f1xx_hal.h" -#elif !defined( _lint ) /* Lint does not like an #error */ - #error What part? -#endif /* if defined( STM32F7xx ) */ - - -/* Interrupt events to process. Currently only the Rx event is processed - * although code for other events is included to allow for possible future - * expansion. */ -#define EMAC_IF_RX_EVENT 1UL -#define EMAC_IF_TX_EVENT 2UL -#define EMAC_IF_ERR_EVENT 4UL -#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT ) - -/* Calculate the maximum packet size that the DMA can receive. */ -#define EMAC_DMA_BUFFER_SIZE ( ( uint32_t ) ( ETH_MAX_PACKET_SIZE - ipBUFFER_PADDING ) ) - -#define ETH_DMA_ALL_INTS \ - ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | \ - ETH_DMA_IT_AIS | ETH_DMA_IT_ER | ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | \ - ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | ETH_DMA_IT_TU | \ - ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) - -#ifndef NETWORK_BUFFER_HEADER_SIZE - #define NETWORK_BUFFER_HEADER_SIZE ( ipBUFFER_PADDING ) -#endif - -#ifndef niEMAC_HANDLER_TASK_PRIORITY - #define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1 -#endif - -#if ( ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 ) || ( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM == 0 ) ) - #warning Consider enabling checksum offloading -#endif - -#ifndef niDESCRIPTOR_WAIT_TIME_MS - #define niDESCRIPTOR_WAIT_TIME_MS 250uL -#endif - -/* - * Most users will want a PHY that negotiates about - * the connection properties: speed, dmix and duplex. - * On some rare cases, you want to select what is being - * advertised, properties like MDIX and duplex. - */ - -#if !defined( ipconfigETHERNET_AN_ENABLE ) - /* Enable auto-negotiation */ - #define ipconfigETHERNET_AN_ENABLE 1 -#endif - -#if !defined( ipconfigETHERNET_AUTO_CROSS_ENABLE ) - #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1 -#endif - -#if ( ipconfigETHERNET_AN_ENABLE == 0 ) - -/* - * The following three defines are only used in case there - * is no auto-negotiation. - */ - #if !defined( ipconfigETHERNET_CROSSED_LINK ) - #define ipconfigETHERNET_CROSSED_LINK 1 - #endif - - #if !defined( ipconfigETHERNET_USE_100MB ) - #define ipconfigETHERNET_USE_100MB 1 - #endif - - #if !defined( ipconfigETHERNET_USE_FULL_DUPLEX ) - #define ipconfigETHERNET_USE_FULL_DUPLEX 1 - #endif -#endif /* ipconfigETHERNET_AN_ENABLE == 0 */ - -/* Default the size of the stack used by the EMAC deferred handler task to twice - * the size of the stack used by the idle task - but allow this to be overridden in - * FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */ -#ifndef configEMAC_TASK_STACK_SIZE - #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE ) -#endif - -/* Two choices must be made: RMII versus MII, - * and the index of the PHY in use ( between 0 and 31 ). */ -#ifndef ipconfigUSE_RMII - #ifdef STM32F7xx - #define ipconfigUSE_RMII 1 - #warning Using RMII, make sure if this is correct - #else - #define ipconfigUSE_RMII 0 - #warning Using MII, make sure if this is correct - #endif /* STM32F7xx */ -#endif /* ipconfigUSE_RMII */ - -typedef enum -{ - eMACInit, /* Must initialise MAC. */ - eMACPass, /* Initialisation was successful. */ - eMACFailed, /* Initialisation failed. */ -} eMAC_INIT_STATUS_TYPE; - -static eMAC_INIT_STATUS_TYPE xMacInitStatus = eMACInit; - -/*-----------------------------------------------------------*/ - -/* - * A deferred interrupt handler task that processes - */ -static void prvEMACHandlerTask( void * pvParameters ); - -/* - * Force a negotiation with the Switch or Router and wait for LS. - */ -static void prvEthernetUpdateConfig( BaseType_t xForce ); - -/* - * See if there is a new packet and forward it to the IP-task. - */ -static BaseType_t prvNetworkInterfaceInput( void ); - - -/* - * For LLMNR, an extra MAC-address must be configured to - * be able to receive the multicast messages. - */ -static void prvMACAddressConfig( ETH_HandleTypeDef * heth, - uint32_t ulIndex, - uint8_t * Addr ); - -/* FreeRTOS+TCP/multi : - * Each network device has 3 access functions: - * - Initialise the device - * - Output a network packet - * - Return the PHY Link-Status (LS) - * They can be defined as static because the function addresses - * will be stored in struct NetworkInterface_t. The latter will be done in - * the function pxSTM32Fxx_FillInterfaceDescriptor(). */ - -static BaseType_t xSTM32F_NetworkInterfaceInitialise( NetworkInterface_t * pxInterface ); - -static BaseType_t xSTM32F_NetworkInterfaceOutput( NetworkInterface_t * pxInterface, - NetworkBufferDescriptor_t * const pxBuffer, - BaseType_t bReleaseAfterSend ); - -static BaseType_t xSTM32F_GetPhyLinkStatus( NetworkInterface_t * pxInterface ); - -NetworkInterface_t * pxSTM32Fxx_FillInterfaceDescriptor( BaseType_t xEMACIndex, - NetworkInterface_t * pxInterface ); - -/* - * Check if a given packet should be accepted. - */ -static BaseType_t xMayAcceptPacket( uint8_t * pucEthernetBuffer ); - -/* - * Initialise the TX descriptors. - */ -static void prvDMATxDescListInit( void ); - -/* - * Initialise the RX descriptors. - */ -static void prvDMARxDescListInit( void ); - -/* After packets have been sent, the network - * buffers will be released. */ -static void vClearTXBuffers( void ); - -/*-----------------------------------------------------------*/ - -#if ( ipconfigUSE_LLMNR == 1 ) - static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC }; -#endif - -#if ( ipconfigUSE_MDNS == 1 ) - static const uint8_t xMDNS_MACAddressIPv4[] = { 0x01, 0x00, 0x5e, 0x00, 0x00, 0xfb }; -#endif - -static EthernetPhy_t xPhyObject; - -/* Ethernet handle. */ -static ETH_HandleTypeDef xETH; - -/* xTXDescriptorSemaphore is a counting semaphore with - * a maximum count of ETH_TXBUFNB, which is the number of - * DMA TX descriptors. */ -static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; - -/* - * Note: it is advised to define both - * - * #define ipconfigZERO_COPY_RX_DRIVER 1 - * #define ipconfigZERO_COPY_TX_DRIVER 1 - * - * The method using memcpy is slower and probably uses more RAM memory. - * The possibility is left in the code just for comparison. - * - * It is advised to define ETH_TXBUFNB at least 4. Note that no - * TX buffers are allocated in a zero-copy driver. - */ -/* MAC buffers: ---------------------------------------------------------*/ - -/* Put the DMA descriptors in '.first_data'. - * This is important for STM32F7, which has an L1 data cache. - * The first 64KB of the SRAM is not cached. - * See README.TXT in this folder. */ - -/* Ethernet Rx MA Descriptor */ -__attribute__( ( aligned( 32 ) ) ) -#if defined( STM32F7xx ) - __attribute__( ( section( ".first_data" ) ) ) -#endif -ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ]; - -#if ( ipconfigZERO_COPY_RX_DRIVER == 0 ) - /* Ethernet Receive Buffer */ - __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END; -#endif - -/* Ethernet Tx DMA Descriptor */ -__attribute__( ( aligned( 32 ) ) ) -#if defined( STM32F7xx ) - __attribute__( ( section( ".first_data" ) ) ) -#endif -ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ]; - -#if ( ipconfigZERO_COPY_TX_DRIVER == 0 ) - /* Ethernet Transmit Buffer */ - __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END; -#endif - -/* DMATxDescToClear points to the next TX DMA descriptor - * that must be cleared by vClearTXBuffers(). */ -static __IO ETH_DMADescTypeDef * DMATxDescToClear; - -static NetworkInterface_t * pxMyInterface = NULL; - -/* Holds the handle of the task used as a deferred interrupt processor. The - * handle is used so direct notifications can be sent to the task for all EMAC/DMA - * related interrupts. */ -static TaskHandle_t xEMACTaskHandle = NULL; - -/* For local use only: describe the PHY's properties: */ -const PhyProperties_t xPHYProperties = -{ - #if ( ipconfigETHERNET_AN_ENABLE != 0 ) - .ucSpeed = PHY_SPEED_AUTO, - .ucDuplex = PHY_DUPLEX_AUTO, - #else - #if ( ipconfigETHERNET_USE_100MB != 0 ) - .ucSpeed = PHY_SPEED_100, - #else - .ucSpeed = PHY_SPEED_10, - #endif - - #if ( ipconfigETHERNET_USE_FULL_DUPLEX != 0 ) - .ucDuplex = PHY_DUPLEX_FULL, - #else - .ucDuplex = PHY_DUPLEX_HALF, - #endif - #endif /* if ( ipconfigETHERNET_AN_ENABLE != 0 ) */ - - #if ( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 ) - .ucMDI_X = PHY_MDIX_AUTO, - #elif ( ipconfigETHERNET_CROSSED_LINK != 0 ) - .ucMDI_X = PHY_MDIX_CROSSED, - #else - .ucMDI_X = PHY_MDIX_DIRECT, - #endif -}; - -/*-----------------------------------------------------------*/ - -BaseType_t xNetworkInterfaceInitialise( NetworkInterface_t * pxInterface ) -{ - return xSTM32F_NetworkInterfaceInitialise( pxInterface ); -} - -BaseType_t xNetworkInterfaceOutput( NetworkInterface_t * pxInterface, - NetworkBufferDescriptor_t * const pxBuffer, - BaseType_t bReleaseAfterSend ) -{ - return xSTM32F_NetworkInterfaceOutput( pxInterface, pxBuffer, bReleaseAfterSend ); -} - -#if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) - -/* Do not call the following function directly. It is there for downward compatibility. - * The function FreeRTOS_IPInit() will call it to initialice the interface and end-point - * objects. See the description in FreeRTOS_Routing.h. */ - - NetworkInterface_t * pxFillInterfaceDescriptor( BaseType_t xEMACIndex, - NetworkInterface_t * pxInterface ) - { - return pxSTM32Fxx_FillInterfaceDescriptor( xEMACIndex, pxInterface ); - } - -#endif - -BaseType_t xGetPhyLinkStatus( NetworkInterface_t * pxInterface ) -{ - return xSTM32F_GetPhyLinkStatus( pxInterface ); -} - -void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ) -{ - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - ( void ) heth; - - /* Pass an RX-event and wakeup the prvEMACHandlerTask. */ - if( xEMACTaskHandle != NULL ) - { - xTaskNotifyFromISR( xEMACTaskHandle, EMAC_IF_RX_EVENT, eSetBits, &( xHigherPriorityTaskWoken ) ); - portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); - } -} -/*-----------------------------------------------------------*/ - -void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ) -{ - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - ( void ) heth; - - /* Pass a TX-event and wakeup the prvEMACHandlerTask. */ - if( xEMACTaskHandle != NULL ) - { - xTaskNotifyFromISR( xEMACTaskHandle, EMAC_IF_TX_EVENT, eSetBits, &( xHigherPriorityTaskWoken ) ); - portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); - } -} -/*-----------------------------------------------------------*/ - -static void vClearTXBuffers() -{ - __IO ETH_DMADescTypeDef * txLastDescriptor = xETH.TxDesc; - size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore ); - - #if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) - NetworkBufferDescriptor_t * pxNetworkBuffer; - uint8_t * ucPayLoad; - #endif - - /* This function is called after a TX-completion interrupt. - * It will release each Network Buffer used in xNetworkInterfaceOutput(). - * 'uxCount' represents the number of descriptors given to DMA for transmission. - * After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */ - while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) ) - { - if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) ) - { - break; - } - - #if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) - { - ucPayLoad = ( uint8_t * ) DMATxDescToClear->Buffer1Addr; - - if( ucPayLoad != NULL ) - { - pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad ); - - if( pxNetworkBuffer != NULL ) - { - vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); - } - - DMATxDescToClear->Buffer1Addr = ( uint32_t ) 0u; - } - } - #endif /* ipconfigZERO_COPY_TX_DRIVER */ - - DMATxDescToClear = ( ETH_DMADescTypeDef * ) ( DMATxDescToClear->Buffer2NextDescAddr ); - - uxCount--; - /* Tell the counting semaphore that one more TX descriptor is available. */ - xSemaphoreGive( xTXDescriptorSemaphore ); - } -} -/*-----------------------------------------------------------*/ - -BaseType_t xSTM32F_NetworkInterfaceInitialise( NetworkInterface_t * pxInterface ) -{ - HAL_StatusTypeDef hal_eth_init_status; - BaseType_t xResult; - NetworkEndPoint_t * pxEndPoint; - - BaseType_t xMACEntry = ETH_MAC_ADDRESS1; /* ETH_MAC_ADDRESS0 reserved for the primary MAC-address. */ - - if( xMacInitStatus == eMACInit ) - { - xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB ); - - if( xTXDescriptorSemaphore == NULL ) - { - xMacInitStatus = eMACFailed; - } - else - { - /* Initialise ETH */ - pxMyInterface = pxInterface; - pxEndPoint = FreeRTOS_FirstEndPoint( pxInterface ); - configASSERT( pxEndPoint != NULL ); - - xETH.Instance = ETH; - xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; - xETH.Init.Speed = ETH_SPEED_100M; - xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; - /* Value of PhyAddress doesn't matter, will be probed for. */ - xETH.Init.PhyAddress = 0; - - xETH.Init.MACAddr = ( uint8_t * ) pxEndPoint->xMACAddress.ucBytes; - xETH.Init.RxMode = ETH_RXINTERRUPT_MODE; - - #if ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) - { - /* using the ETH_CHECKSUM_BY_HARDWARE option: - * both the IP and the protocol checksums will be calculated - * by the peripheral. */ - xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; - } - #else - { - xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE; - } - #endif - - #if ( ipconfigUSE_RMII != 0 ) - { - xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; - } - #else - { - xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII; - } - #endif /* ipconfigUSE_RMII */ - - hal_eth_init_status = HAL_ETH_Init( &xETH ); - - /* Only for inspection by debugger. */ - ( void ) hal_eth_init_status; - - /* Set the TxDesc and RxDesc pointers. */ - xETH.TxDesc = DMATxDscrTab; - xETH.RxDesc = DMARxDscrTab; - - /* Make sure that all unused fields are cleared. */ - memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) ); - memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) ); - - /* Initialize Tx Descriptors list: Chain Mode */ - DMATxDescToClear = DMATxDscrTab; - - /* Initialise TX-descriptors. */ - prvDMATxDescListInit(); - - /* Initialise RX-descriptors. */ - prvDMARxDescListInit(); - - #if ( ipconfigUSE_MDNS == 1 ) - { - /* Program the MDNS address. */ - prvMACAddressConfig( &xETH, xMACEntry, ( uint8_t * ) xMDNS_MACAddressIPv4 ); - xMACEntry += 8; - } - #endif - #if ( ( ipconfigUSE_MDNS == 1 ) && ( ipconfigUSE_IPv6 != 0 ) ) - { - prvMACAddressConfig( &xETH, xMACEntry, ( uint8_t * ) xMDNS_MACAdressIPv6.ucBytes ); - xMACEntry += 8; - } - #endif - #if ( ipconfigUSE_LLMNR == 1 ) - { - /* Program the LLMNR address. */ - prvMACAddressConfig( &xETH, xMACEntry, ( uint8_t * ) xLLMNR_MACAddress ); - xMACEntry += 8; - } - #endif - #if ( ( ipconfigUSE_LLMNR == 1 ) && ( ipconfigUSE_IPv6 != 0 ) ) - { - prvMACAddressConfig( &xETH, xMACEntry, ( uint8_t * ) xLLMNR_MacAdressIPv6.ucBytes ); - xMACEntry += 8; - } - #endif - - { - /* The EMAC address of the first end-point has been registered in HAL_ETH_Init(). */ - for( ; - pxEndPoint != NULL; - pxEndPoint = FreeRTOS_NextEndPoint( pxMyInterface, pxEndPoint ) ) - { - #if ( ipconfigUSE_IPv6 != 0 ) - if( pxEndPoint->bits.bIPv6 != pdFALSE_UNSIGNED ) - { - uint8_t ucMACAddress[ 6 ] = { 0x33, 0x33, 0xff, 0, 0, 0 }; - - ucMACAddress[ 3 ] = pxEndPoint->ipv6_settings.xIPAddress.ucBytes[ 13 ]; - ucMACAddress[ 4 ] = pxEndPoint->ipv6_settings.xIPAddress.ucBytes[ 14 ]; - ucMACAddress[ 5 ] = pxEndPoint->ipv6_settings.xIPAddress.ucBytes[ 15 ]; - prvMACAddressConfig( &xETH, xMACEntry, ucMACAddress ); - xMACEntry += 8; - } - else - #else /* if ( ipconfigUSE_IPv6 != 0 ) */ - { - if( xETH.Init.MACAddr != ( uint8_t * ) pxEndPoint->xMACAddress.ucBytes ) - { - prvMACAddressConfig( &xETH, xMACEntry, pxEndPoint->xMACAddress.ucBytes ); - xMACEntry += 8; - } - } - #endif /* if ( ipconfigUSE_IPv6 != 0 ) */ - if( xMACEntry > ( BaseType_t ) ETH_MAC_ADDRESS3 ) - { - /* No more locations available. */ - break; - } - } - } - #if ( ipconfigUSE_IPv6 != 0 ) - { - if( xMACEntry <= ( BaseType_t ) ETH_MAC_ADDRESS3 ) - { - /* 33:33:00:00:00:01 */ - uint8_t ucMACAddress[ 6 ] = { 0x33, 0x33, 0, 0, 0, 0x01 }; - - prvMACAddressConfig( &xETH, xMACEntry, ucMACAddress ); - xMACEntry += 8; - } - } - #endif /* ( ipconfigUSE_IPv6 != 0 ) */ - - /* Force a negotiation with the Switch or Router and wait for LS. */ - prvEthernetUpdateConfig( pdTRUE ); - - /* The deferred interrupt handler task is created at the highest - * possible priority to ensure the interrupt handler can return directly - * to it. The task's handle is stored in xEMACTaskHandle so interrupts can - * notify the task when there is something to process. */ - if( xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &xEMACTaskHandle ) == pdPASS ) - { - /* The xTXDescriptorSemaphore and the task are created successfully. */ - xMacInitStatus = eMACPass; - } - else - { - xMacInitStatus = eMACFailed; - } - } - } /* if( xMacInitStatus == eMACInit ) */ - - if( xMacInitStatus != eMACPass ) - { - /* EMAC initialisation failed, return pdFAIL. */ - xResult = pdFAIL; - } - else - { - if( xPhyObject.ulLinkStatusMask != 0U ) - { - xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS; - xResult = pdPASS; - FreeRTOS_printf( ( "Link Status is high\n" ) ); - } - else - { - /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running - * and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */ - xResult = pdFAIL; - } - } - - /* When returning non-zero, the stack will become active and - * start DHCP (in configured) */ - return xResult; -} -/*-----------------------------------------------------------*/ - -static void prvDMATxDescListInit() -{ - ETH_DMADescTypeDef * pxDMADescriptor; - BaseType_t xIndex; - - /* Get the pointer on the first member of the descriptor list */ - pxDMADescriptor = DMATxDscrTab; - - /* Fill each DMA descriptor with the right values */ - for( xIndex = 0; xIndex < ETH_TXBUFNB; xIndex++, pxDMADescriptor++ ) - { - /* Set Second Address Chained bit */ - pxDMADescriptor->Status = ETH_DMATXDESC_TCH; - - #if ( ipconfigZERO_COPY_TX_DRIVER == 0 ) - { - /* Set Buffer1 address pointer */ - pxDMADescriptor->Buffer1Addr = ( uint32_t ) ( Tx_Buff[ xIndex ] ); - } - #endif - - if( xETH.Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE ) - { - /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */ - pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; - } - else - { - pxDMADescriptor->Status &= ~( ( uint32_t ) ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ); - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if( xIndex < ETH_TXBUFNB - 1 ) - { - /* Set next descriptor address register with next descriptor base address */ - pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 ); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMATxDscrTab; - } - } - - /* Set Transmit Descriptor List Address Register */ - xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab; -} -/*-----------------------------------------------------------*/ - -static void prvDMARxDescListInit() -{ - ETH_DMADescTypeDef * pxDMADescriptor; - BaseType_t xIndex; - - /* - * RX-descriptors. - */ - - /* Get the pointer on the first member of the descriptor list */ - pxDMADescriptor = DMARxDscrTab; - - /* Fill each DMA descriptor with the right values */ - for( xIndex = 0; xIndex < ETH_RXBUFNB; xIndex++, pxDMADescriptor++ ) - { - /* Set Buffer1 size and Second Address Chained bit */ - pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | EMAC_DMA_BUFFER_SIZE; - - #if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) - { - /* Set Buffer1 address pointer */ - NetworkBufferDescriptor_t * pxBuffer; - - pxBuffer = pxGetNetworkBufferWithDescriptor( EMAC_DMA_BUFFER_SIZE, 100ul ); - - /* If the assert below fails, make sure that there are at least 'ETH_RXBUFNB' - * Network Buffers available during start-up ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) */ - configASSERT( pxBuffer != NULL ); - - if( pxBuffer != NULL ) - { - pxDMADescriptor->Buffer1Addr = ( uint32_t ) pxBuffer->pucEthernetBuffer; - pxDMADescriptor->Status = ETH_DMARXDESC_OWN; - } - } - #else /* if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) */ - { - /* Set Buffer1 address pointer */ - pxDMADescriptor->Buffer1Addr = ( uint32_t ) ( Rx_Buff[ xIndex ] ); - /* Set Own bit of the Rx descriptor Status */ - pxDMADescriptor->Status = ETH_DMARXDESC_OWN; - } - #endif /* if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) */ - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if( xIndex < ETH_RXBUFNB - 1 ) - { - /* Set next descriptor address register with next descriptor base address */ - pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 ); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMARxDscrTab; - } - } - - /* Set Receive Descriptor List Address Register */ - xETH.Instance->DMARDLAR = ( uint32_t ) DMARxDscrTab; -} -/*-----------------------------------------------------------*/ - - -static void prvMACAddressConfig( ETH_HandleTypeDef * heth, - uint32_t ulIndex, - uint8_t * Addr ) -{ - uint32_t ulTempReg; - - ( void ) heth; - - /* Calculate the selected MAC address high register. */ - ulTempReg = 0x80000000ul | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ]; - - /* Load the selected MAC address high register. */ - ( *( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + ulIndex ) ) ) = ulTempReg; - - /* Calculate the selected MAC address low register. */ - ulTempReg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ]; - - /* Load the selected MAC address low register */ - ( *( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + ulIndex ) ) ) = ulTempReg; -} - -/*-----------------------------------------------------------*/ - -static BaseType_t xSTM32F_NetworkInterfaceOutput( NetworkInterface_t * pxInterface, - NetworkBufferDescriptor_t * const pxDescriptor, - BaseType_t bReleaseAfterSend ) -{ - BaseType_t xReturn = pdFAIL; - uint32_t ulTransmitSize = 0; - __IO ETH_DMADescTypeDef * pxDmaTxDesc; -/* Do not wait too long for a free TX DMA buffer. */ - const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u ); - - /* As there is only a single instance of the EMAC, there is only one pxInterface object. */ - ( void ) pxInterface; - - /* Open a do {} while ( 0 ) loop to be able to call break. */ - do - { - if( xCheckLoopback( pxDescriptor, bReleaseAfterSend ) != 0 ) - { - /* The packet has been sent back to the IP-task. - * The IP-task will further handle it. - * Do not release the descriptor. */ - bReleaseAfterSend = pdFALSE; - break; - } - - #if ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) - { - const IPPacket_t * pxIPPacket; - - pxIPPacket = ( const IPPacket_t * ) pxDescriptor->pucEthernetBuffer; - #if ( ipconfigUSE_IPv6 != 0 ) - if( pxIPPacket->xEthernetHeader.usFrameType == ipIPv6_FRAME_TYPE ) - { - const IPHeader_IPv6_t * pxIPPacket_IPv6; - - pxIPPacket_IPv6 = ( const IPHeader_IPv6_t * ) &( pxDescriptor->pucEthernetBuffer[ ipSIZE_OF_ETH_HEADER ] ); - - if( pxIPPacket_IPv6->ucNextHeader == ( uint8_t ) ipPROTOCOL_ICMP_IPv6 ) - { - ICMPHeader_IPv6_t * pxICMPHeader_IPv6; - - pxICMPHeader_IPv6 = ( ICMPHeader_IPv6_t * ) &( pxDescriptor->pucEthernetBuffer[ ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv6_HEADER ] ); - pxICMPHeader_IPv6->usChecksum = 0U; - } - } - else - #endif /* if ( ipconfigUSE_IPv6 != 0 ) */ - - if( pxIPPacket->xEthernetHeader.usFrameType == ipIPv4_FRAME_TYPE ) - { - if( pxIPPacket->xIPHeader.ucProtocol == ( uint8_t ) ipPROTOCOL_ICMP ) - { - ICMPHeader_t * pxICMPHeader; - - pxICMPHeader = ( ICMPHeader_t * ) &( pxDescriptor->pucEthernetBuffer[ ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER ] ); - pxICMPHeader->usChecksum = ( uint16_t ) 0U; - } - } - } - #endif /* ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM */ - - if( xPhyObject.ulLinkStatusMask != 0 ) - { - if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) - { - /* Time-out waiting for a free TX descriptor. */ - break; - } - - /* This function does the actual transmission of the packet. The packet is - * contained in 'pxDescriptor' that is passed to the function. */ - pxDmaTxDesc = xETH.TxDesc; - - /* Is this buffer available? */ - configASSERT( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 ); - - { - /* Is this buffer available? */ - /* Get bytes in current buffer. */ - ulTransmitSize = pxDescriptor->xDataLength; - - if( ulTransmitSize > EMAC_DMA_BUFFER_SIZE ) - { - ulTransmitSize = EMAC_DMA_BUFFER_SIZE; - } - - #if ( ipconfigZERO_COPY_TX_DRIVER == 0 ) - { - /* Copy the bytes. */ - memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize ); - } - #else - { - configASSERT( bReleaseAfterSend != 0 ); - - /* Move the buffer. */ - pxDmaTxDesc->Buffer1Addr = ( uint32_t ) pxDescriptor->pucEthernetBuffer; - /* The Network Buffer has been passed to DMA, no need to release it. */ - bReleaseAfterSend = pdFALSE_UNSIGNED; - } - #endif /* ipconfigZERO_COPY_TX_DRIVER */ - - /* Ask to set the IPv4 checksum. - * Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */ - #if ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) - { - pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC; - } - #else - { - pxDmaTxDesc->Status &= ~( ( uint32_t ) ETH_DMATXDESC_CIC ); - pxDmaTxDesc->Status |= ETH_DMATXDESC_IC; - } - #endif - - - /* Prepare transmit descriptors to give to DMA. */ - - /* Set LAST and FIRST segment */ - pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; - /* Set frame size */ - pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 ); - - #if ( NETWORK_BUFFERS_CACHED != 0 ) - { - BaseType_t xlength = CACHE_LINE_SIZE * ( ( ulTransmitSize + NETWORK_BUFFER_HEADER_SIZE + CACHE_LINE_SIZE - 1 ) / CACHE_LINE_SIZE ); - uint32_t * pulBuffer = ( uint32_t ) ( pxDescriptor->pucEthernetBuffer - NETWORK_BUFFER_HEADER_SIZE ); - cache_clean_invalidate_by_addr( pulBuffer, xlength ); - } - #endif - - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN; - - /* Point to next descriptor */ - xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr ); - /* Ensure completion of memory access */ - __DSB(); - /* Resume DMA transmission*/ - xETH.Instance->DMATPDR = 0; - iptraceNETWORK_INTERFACE_TRANSMIT(); - xReturn = pdPASS; - } - } - else - { - /* The PHY has no Link Status, packet shall be dropped. */ - } - } while( 0 ); - - /* The buffer has been sent so can be released. */ - if( bReleaseAfterSend != pdFALSE ) - { - vReleaseNetworkBufferAndDescriptor( pxDescriptor ); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static BaseType_t xMayAcceptPacket( uint8_t * pucEthernetBuffer ) -{ - const ProtocolPacket_t * pxProtPacket = ( const ProtocolPacket_t * ) pucEthernetBuffer; - - switch( pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType ) - { - case ipARP_FRAME_TYPE: - /* Check it later. */ - return pdTRUE; - - #if ( ipconfigUSE_IPv6 != 0 ) - case ipIPv6_FRAME_TYPE: - /* Check it later. */ - return pdTRUE; - #endif - case ipIPv4_FRAME_TYPE: - /* Check it here. */ - break; - - default: - /* Refuse the packet. */ - return pdFALSE; - } - - #if ( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) - { - const IPHeader_t * pxIPHeader = &( pxProtPacket->xTCPPacket.xIPHeader ); - uint32_t ulDestinationIPAddress; - - /* Ensure that the incoming packet is not fragmented (only outgoing packets - * can be fragmented) as these are the only handled IP frames currently. */ - if( ( pxIPHeader->usFragmentOffset & ipFRAGMENT_OFFSET_BIT_MASK ) != 0U ) - { - return pdFALSE; - } - - /* HT: Might want to make the following configurable because - * most IP messages have a standard length of 20 bytes */ - - /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes - * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */ - if( ( pxIPHeader->ucVersionHeaderLength < 0x45 ) || ( pxIPHeader->ucVersionHeaderLength > 0x4F ) ) - { - return pdFALSE; - } - - ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress; - - /* Is the packet for this node? */ - if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) && - /* Is it a broadcast address x.x.x.255 ? */ - ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) && - #if ( ipconfigUSE_LLMNR == 1 ) - ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) && - #endif - ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) ) - { - FreeRTOS_printf( ( "Drop IP %lxip\n", FreeRTOS_ntohl( ulDestinationIPAddress ) ) ); - return pdFALSE; - } - - if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP ) - { - #if ( ipconfigUSE_LLMNR == 1 ) || ( ipconfigUSE_MDNS == 1 ) || ( ipconfigUSE_NBNS == 1 ) || ( ipconfigUSE_DNS == 1 ) - uint16_t usSourcePort = FreeRTOS_ntohs( pxProtPacket->xUDPPacket.xUDPHeader.usSourcePort ); - uint16_t usDestinationPort = FreeRTOS_ntohs( pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort ); - #endif - - if( ( xPortHasUDPSocket( pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort ) == pdFALSE ) - #if ipconfigUSE_LLMNR == 1 - && ( usDestinationPort != ipLLMNR_PORT ) && - ( usSourcePort != ipLLMNR_PORT ) - #endif - #if ipconfigUSE_MDNS == 1 - && ( usDestinationPort != ipMDNS_PORT ) && - ( usSourcePort != ipMDNS_PORT ) - #endif - #if ipconfigUSE_NBNS == 1 - && ( usDestinationPort != ipNBNS_PORT ) && - ( usSourcePort != ipNBNS_PORT ) - #endif - #if ipconfigUSE_DNS == 1 - && ( usSourcePort != ipDNS_PORT ) - #endif - ) - { - /* Drop this packet, not for this device. */ - /* FreeRTOS_printf( ( "Drop: UDP port %d -> %d\n", usSourcePort, usDestinationPort ) ); */ - return pdFALSE; - } - } - } - #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -static void prvPassEthMessages( NetworkBufferDescriptor_t * pxDescriptor ) -{ - IPStackEvent_t xRxEvent; - - xRxEvent.eEventType = eNetworkRxEvent; - xRxEvent.pvData = ( void * ) pxDescriptor; - - if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 1000 ) != pdPASS ) - { - /* The buffer could not be sent to the stack so must be released again. - * This is a deferred handler task, not a real interrupt, so it is ok to - * use the task level function here. */ - #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) - { - do - { - NetworkBufferDescriptor_t * pxNext = pxDescriptor->pxNextBuffer; - vReleaseNetworkBufferAndDescriptor( pxDescriptor ); - pxDescriptor = pxNext; - } while( pxDescriptor != NULL ); - } - #else - { - vReleaseNetworkBufferAndDescriptor( pxDescriptor ); - } - #endif /* ipconfigUSE_LINKED_RX_MESSAGES */ - iptraceETHERNET_RX_EVENT_LOST(); - FreeRTOS_printf( ( "prvPassEthMessages: Can not queue return packet!\n" ) ); - } - else - { - iptraceNETWORK_INTERFACE_RECEIVE(); - } -} - -static BaseType_t prvNetworkInterfaceInput( void ) -{ - #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) - NetworkBufferDescriptor_t * pxFirstDescriptor = NULL; - NetworkBufferDescriptor_t * pxLastDescriptor = NULL; - #endif - BaseType_t xReceivedLength = 0; - __IO ETH_DMADescTypeDef * pxDMARxDescriptor; - const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( niDESCRIPTOR_WAIT_TIME_MS ); - uint8_t * pucBuffer; - - pxDMARxDescriptor = xETH.RxDesc; - - while( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0u ) - { - NetworkBufferDescriptor_t * pxCurDescriptor; - NetworkBufferDescriptor_t * pxNewDescriptor = NULL; - BaseType_t xAccepted = pdTRUE; - - /* Get the Frame Length of the received packet: subtract 4 bytes of the CRC */ - xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4; - - pucBuffer = ( uint8_t * ) pxDMARxDescriptor->Buffer1Addr; - - /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */ - /* Chained Mode */ - /* Selects the next DMA Rx descriptor list for next buffer to read */ - xETH.RxDesc = ( ETH_DMADescTypeDef * ) pxDMARxDescriptor->Buffer2NextDescAddr; - - /* In order to make the code easier and faster, only packets in a single buffer - * will be accepted. This can be done by making the buffers large enough to - * hold a complete Ethernet packet, minus ipBUFFER_PADDING. - * Therefore, two sanity checks: */ - configASSERT( xReceivedLength <= EMAC_DMA_BUFFER_SIZE ); - - if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT ) - { - /* Not an Ethernet frame-type or a checksum error. */ - xAccepted = pdFALSE; - } - else - { - /* See if this packet must be handled. */ - xAccepted = xMayAcceptPacket( pucBuffer ); - } - - if( xAccepted != pdFALSE ) - { - /* The packet will be accepted, but check first if a new Network Buffer can - * be obtained. If not, the packet will still be dropped. */ - pxNewDescriptor = pxGetNetworkBufferWithDescriptor( EMAC_DMA_BUFFER_SIZE, xDescriptorWaitTime ); - - if( pxNewDescriptor == NULL ) - { - /* A new descriptor can not be allocated now. This packet will be dropped. */ - xAccepted = pdFALSE; - } - } - - #if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) - { - /* Find out which Network Buffer was originally passed to the descriptor. */ - pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer ); - configASSERT( pxCurDescriptor != NULL ); - configASSERT( pxCurDescriptor->pucEthernetBuffer != NULL ); - } - #else - { - /* In this mode, the two descriptors are the same. */ - pxCurDescriptor = pxNewDescriptor; - - if( pxNewDescriptor != NULL ) - { - /* The packet is accepted and a new Network Buffer was created, - * copy data to the Network Buffer. */ - memcpy( pxNewDescriptor->pucEthernetBuffer, pucBuffer, xReceivedLength ); - } - } - #endif /* if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) */ - - if( xAccepted != pdFALSE ) - { - pxCurDescriptor->xDataLength = xReceivedLength; - pxCurDescriptor->pxInterface = pxMyInterface; - pxCurDescriptor->pxEndPoint = FreeRTOS_MatchingEndpoint( pxMyInterface, pxCurDescriptor->pucEthernetBuffer ); - - #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) - { - pxCurDescriptor->pxNextBuffer = NULL; - - if( pxFirstDescriptor == NULL ) - { - /* Becomes the first message */ - pxFirstDescriptor = pxCurDescriptor; - } - else if( pxLastDescriptor != NULL ) - { - /* Add to the tail */ - pxLastDescriptor->pxNextBuffer = pxCurDescriptor; - } - - pxLastDescriptor = pxCurDescriptor; - } - #else /* if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) */ - { - prvPassEthMessages( pxCurDescriptor ); - } - #endif /* if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) */ - } - - /* Release descriptors to DMA */ - #if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) - { - /* Set Buffer1 address pointer */ - if( pxNewDescriptor != NULL ) - { - pxDMARxDescriptor->Buffer1Addr = ( uint32_t ) pxNewDescriptor->pucEthernetBuffer; - } - else - { - /* The packet was dropped and the same Network - * Buffer will be used to receive a new packet. */ - } - } - #endif /* ipconfigZERO_COPY_RX_DRIVER */ - - /* Set Buffer1 size and Second Address Chained bit */ - pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | EMAC_DMA_BUFFER_SIZE; - pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN; - - /* Ensure completion of memory access */ - __DSB(); - - /* When Rx Buffer unavailable flag is set clear it and resume - * reception. */ - if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 ) - { - /* Clear RBUS ETHERNET DMA flag. */ - xETH.Instance->DMASR = ETH_DMASR_RBUS; - - /* Resume DMA reception. */ - xETH.Instance->DMARPDR = 0; - } - - pxDMARxDescriptor = xETH.RxDesc; - } - - #if ( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) - { - if( pxFirstDescriptor != NULL ) - { - prvPassEthMessages( pxFirstDescriptor ); - } - } - #endif /* ipconfigUSE_LINKED_RX_MESSAGES */ - - return( xReceivedLength > 0 ); -} -/*-----------------------------------------------------------*/ - - -BaseType_t xSTM32_PhyRead( BaseType_t xAddress, - BaseType_t xRegister, - uint32_t * pulValue ) -{ - uint16_t usPrevAddress = xETH.Init.PhyAddress; - BaseType_t xResult; - HAL_StatusTypeDef xHALResult; - - xETH.Init.PhyAddress = xAddress; - xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t ) xRegister, pulValue ); - xETH.Init.PhyAddress = usPrevAddress; - - if( xHALResult == HAL_OK ) - { - xResult = 0; - } - else - { - xResult = -1; - } - - return xResult; -} -/*-----------------------------------------------------------*/ - -BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, - BaseType_t xRegister, - uint32_t ulValue ) -{ - uint16_t usPrevAddress = xETH.Init.PhyAddress; - BaseType_t xResult; - HAL_StatusTypeDef xHALResult; - - xETH.Init.PhyAddress = xAddress; - xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t ) xRegister, ulValue ); - xETH.Init.PhyAddress = usPrevAddress; - - if( xHALResult == HAL_OK ) - { - xResult = 0; - } - else - { - xResult = -1; - } - - return xResult; -} -/*-----------------------------------------------------------*/ - -void vMACBProbePhy( void ) -{ - vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite ); - xPhyDiscover( &xPhyObject ); - xPhyConfigure( &xPhyObject, &xPHYProperties ); -} -/*-----------------------------------------------------------*/ - -static void prvEthernetUpdateConfig( BaseType_t xForce ) -{ - FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n", - xPhyObject.ulLinkStatusMask, - ( int ) xForce ) ); - - if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) ) - { - /* Restart the auto-negotiation. */ - if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE ) - { - xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) ); - - /* Configure the MAC with the Duplex Mode fixed by the - * auto-negotiation process. */ - if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL ) - { - xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; - } - else - { - xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX; - } - - /* Configure the MAC with the speed fixed by the - * auto-negotiation process. */ - if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 ) - { - xETH.Init.Speed = ETH_SPEED_10M; - } - else - { - xETH.Init.Speed = ETH_SPEED_100M; - } - } - else /* AutoNegotiation Disable */ - { - /* Check parameters */ - assert_param( IS_ETH_SPEED( xETH.Init.Speed ) ); - assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) ); - - if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX ) - { - xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF; - } - else - { - xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL; - } - - if( xETH.Init.Speed == ETH_SPEED_10M ) - { - xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10; - } - else - { - xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100; - } - - xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO; - - /* Use predefined (fixed) configuration. */ - xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) ); - } - - /* ETHERNET MAC Re-Configuration */ - HAL_ETH_ConfigMAC( &xETH, ( ETH_MACInitTypeDef * ) NULL ); - - /* Optionally, pass all mutlicast */ - #if 0 - xETH.Instance->MACFFR |= ETH_MACFFR_PAM; - #endif - - /* Restart MAC interface */ - HAL_ETH_Start( &xETH ); - } - else - { - /* Stop MAC interface */ - HAL_ETH_Stop( &xETH ); - } -} -/*-----------------------------------------------------------*/ - -static BaseType_t xSTM32F_GetPhyLinkStatus( NetworkInterface_t * pxInterface ) -{ - BaseType_t xReturn; - - ( void ) pxInterface; - - if( xPhyObject.ulLinkStatusMask != 0 ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -/* Uncomment this in case BufferAllocation_1.c is used. */ - -void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) -{ - static - #if defined( STM32F7xx ) - __attribute__( ( section( ".first_data" ) ) ) - #endif - uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * ETH_MAX_PACKET_SIZE ] __attribute__( ( aligned( 32 ) ) ); - uint8_t * ucRAMBuffer = ucNetworkPackets; - uint32_t ul; - - for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ ) - { - pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING; - *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) ); - ucRAMBuffer += ETH_MAX_PACKET_SIZE; - } -} - -/*-----------------------------------------------------------*/ - -NetworkInterface_t * pxSTM32Fxx_FillInterfaceDescriptor( BaseType_t xEMACIndex, - NetworkInterface_t * pxInterface ) -{ - static char pcName[ 17 ]; - -/* This function pxSTM32Fxx_FillInterfaceDescriptor() adds a network-interface. - * Make sure that the object pointed to by 'pxInterface' - * is declared static or global, and that it will remain to exist. */ - - snprintf( pcName, sizeof( pcName ), "eth%u", ( unsigned ) xEMACIndex ); - - memset( pxInterface, '\0', sizeof( *pxInterface ) ); - pxInterface->pcName = pcName; /* Just for logging, debugging. */ - pxInterface->pvArgument = ( void * ) xEMACIndex; /* Has only meaning for the driver functions. */ - pxInterface->pfInitialise = xSTM32F_NetworkInterfaceInitialise; - pxInterface->pfOutput = xSTM32F_NetworkInterfaceOutput; - pxInterface->pfGetPhyLinkStatus = xSTM32F_GetPhyLinkStatus; - - FreeRTOS_AddNetworkInterface( pxInterface ); - - return pxInterface; -} -/*-----------------------------------------------------------*/ - -static void prvEMACHandlerTask( void * pvParameters ) -{ - UBaseType_t uxCurrentCount; - BaseType_t xResult; - const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); - uint32_t ulISREvents = 0U; - - /* Remove compiler warnings about unused parameters. */ - ( void ) pvParameters; - - for( ; ; ) - { - xResult = 0; - - #if ( ipconfigHAS_PRINTF != 0 ) - { - /* Call a function that monitors resources: the amount of free network - * buffers and the amount of free space on the heap. See FreeRTOS_IP.c - * for more detailed comments. */ - vPrintResourceStats(); - } - #endif /* ( ipconfigHAS_PRINTF != 0 ) */ - - if( xTXDescriptorSemaphore != NULL ) - { - static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1; - - uxCurrentCount = uxSemaphoreGetCount( xTXDescriptorSemaphore ); - - if( uxLowestSemCount > uxCurrentCount ) - { - uxLowestSemCount = uxCurrentCount; - FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) ); - } - } - - /* Wait for a new event or a time-out. */ - xTaskNotifyWait( 0U, /* ulBitsToClearOnEntry */ - EMAC_IF_ALL_EVENT, /* ulBitsToClearOnExit */ - &( ulISREvents ), /* pulNotificationValue */ - ulMaxBlockTime ); - - if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 ) - { - xResult = prvNetworkInterfaceInput(); - } - - if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 ) - { - /* Code to release TX buffers in case zero-copy is used. */ - /* Check if DMA packets have been delivered. */ - vClearTXBuffers(); - } - - if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 ) - { - /* Future extension: logging about errors that occurred. */ - } - - if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 ) - { - /* Something has changed to a Link Status, need re-check. */ - prvEthernetUpdateConfig( pdFALSE ); - - #if ( ipconfigSUPPORT_NETWORK_DOWN_EVENT != 0 ) - { - if( xGetPhyLinkStatus() == pdFALSE ) - { - FreeRTOS_NetworkDown(); - } - } - #endif /* ( ipconfigSUPPORT_NETWORK_DOWN_EVENT != 0 ) */ - } - } -} -/*-----------------------------------------------------------*/ - -void ETH_IRQHandler( void ) -{ - HAL_ETH_IRQHandler( &xETH ); -} diff --git a/source/portable/NetworkInterface/STM32Fxx/readme.md b/source/portable/NetworkInterface/STM32Fxx/readme.md deleted file mode 100644 index e644a1870..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/readme.md +++ /dev/null @@ -1,140 +0,0 @@ -This is a FreeeRTOS+TCP driver that works for STM32Fxx parts. - - -CONFIGURATION AND RUNNING -========================= - -The code of stm32fxx_hal_eth.c is based on the ETH drivers as provided by ST. - -These modules should be included: -- portable/NetworkInterface/STM32Fxx/NetworkInterface.c -- portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.c - -When initialising the EMAC, the driver will call the function `HAL_ETH_MspInit()`, which should do the following: - -- Enable the Ethernet interface clock using: -```cpp - __HAL_RCC_ETHMAC_CLK_ENABLE(); - __HAL_RCC_ETHMACTX_CLK_ENABLE(); - __HAL_RCC_ETHMACRX_CLK_ENABLE(); -``` - -- Initialize the related GPIO clocks - -- Configure Ethernet pin-out - Please check the schematic of your hardware to see which pins are used. - Also check if either MII or RMII is used ( define `ipconfigUSE_RMII` - as 0 or 1 ). - -- Configure Ethernet NVIC interrupt (IT mode) - Choose a proper interrupt priority, defined in FreeRTOSIPConfig.h as e.g. : - -```cpp - #define ipconfigMAC_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ) -``` - -The function `HAL_ETH_MspInit()` must be provided by the application. Make sure that your copy of the function is called, -and not a dummy defined as "weak". - -It is assumed that one of these macros is defined at the highest level: - - STM32F1xx - STM32F2xx - STM32F4xx - STM32F7xx - -For instance, you can pass it to the compiler with the `-D` option: - - gcc ... -D STM32F4xx=1 - -And sub-models may also be indicated, such as `STM32F401xC` or `STM32F407xx`. - -The driver has been tested on both Eval and Discovery boards with STM32F1, STM32F2, STM32F4 and STM32F7. The F1 and F2 boards -have only be tested by customers who reported about it on the FreeRTOS forum. - -Note that it is required to define `HAL_ETH_MODULE_ENABLED` in your STM32 configuration file. The name of this file is one out -of: - - stm32f1xx_hal_conf.h - stm32f2xx_hal_conf.h - stm32f4xx_hal_conf.h - stm32f7xx_hal_conf.h - -This configuration file defines the HAL modules that will be used. Here are some examples of the module macros: -~~~c -#define HAL_MODULE_ENABLED -#define HAL_ETH_MODULE_ENABLED /* <= this one is needed to get Ethernet. */ -#define HAL_SRAM_MODULE_ENABLED -#define HAL_RNG_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -/* etc. */ -~~~ - -Recommended settings for STM32Fxx Network Interface: - - -**Defined in FreeRTOSIPConfig.h** -```cpp -#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1 -#define ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM 1 -#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 -#define ipconfigZERO_COPY_RX_DRIVER 1 -#define ipconfigZERO_COPY_TX_DRIVER 1 -#define ipconfigUSE_LINKED_RX_MESSAGES 1 -#define ipconfigSUPPORT_NETWORK_DOWN_EVENT 1 -``` - -**Defined in stm32f4xx_hal_conf.h** -```cpp -#define ETH_RXBUFNB 3 or 4 -#define ETH_TXBUFNB 1 or 2 -#define ETH_RX_BUF_SIZE ( ipconfigNETWORK_MTU + 36 ) -#define ETH_TX_BUF_SIZE ( ipconfigNETWORK_MTU + 36 ) -``` - -The best size for `ETH_RXBUFNB` and `ETH_TXBUFNB` depends on the speed of the CPU. These macro's define the number of DMA buffers -for reception and for transmission. In general, if the CPU is very fast, you will need less buffers. You can obtain an estimate -empirically. - -The optimal value of `ETH_RX_BUF_SIZE` and `ETH_TX_BUF_SIZE` depends on the actual value of `ipconfigNETWORK_MTU`. -When MTU is 1500, MTU+36 becomes a well-aligned buffer of 1536 bytes ( 0x600 ). -When MTU is 1200, MTU+48 will make 1248 ( 0x4E0 ), which is also well aligned. - -Having well aligned buffers is important for CPU with memory cache. Often the caching system divides memory in blocks of 32 bytes. -When two buffers share the same cache buffer, you are bound to see data errors. - -Without memory caching, let the size be at least a multiple of 8 ( for DMA ), and make it at least "ipconfigNETWORK_MTU + 14". - -STM32F7xx only: - -NetworkInterface.c will place the 2 DMA tables in a special section called 'first_data'. -In case 'BufferAllocation_1.c' is used, the network packets will also be declared in this section 'first_data'. -As long as the part has no caching, this section can be placed anywhere in RAM. -On an STM32F7 with an L1 data cache, it shall be placed in the first 64KB of RAM, which is always uncached. -The linker script must be changed for this, for instance as follows: - -```assembly - .data : - { - . = ALIGN(4); - _sdata = .; // create a global symbol at data start -+ *(.first_data) // .first_data sections - *(.data) // .data sections - *(.data*) // .data* sections - - . = ALIGN(4); - _edata = .; // define a global symbol at data end - } >RAM AT> FLASH -``` - -The driver contains these files: -- NetworkInterface.c -- stm32fxx_hal_eth.c -- stm32f2xx_hal_eth.h -- stm32f4xx_hal_eth.h -- stm32f7xx_hal_eth.h -- stm32fxx_hal_eth.h - -These files are copied from ST's HAL library. These work both for STM32F4 and STM32F7. -Please remove or rename these files from the HAL distribution that you are using. - diff --git a/source/portable/NetworkInterface/STM32Fxx/stm32f2xx_hal_eth.h b/source/portable/NetworkInterface/STM32Fxx/stm32f2xx_hal_eth.h deleted file mode 100644 index 2251c673f..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/stm32f2xx_hal_eth.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to - * a single module that works for both parts: "stm32fxx_hal_eth" - */ - -#include "stm32fxx_hal_eth.h" diff --git a/source/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h b/source/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h deleted file mode 100644 index 2251c673f..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to - * a single module that works for both parts: "stm32fxx_hal_eth" - */ - -#include "stm32fxx_hal_eth.h" diff --git a/source/portable/NetworkInterface/STM32Fxx/stm32f7xx_hal_eth.h b/source/portable/NetworkInterface/STM32Fxx/stm32f7xx_hal_eth.h deleted file mode 100644 index 2251c673f..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/stm32f7xx_hal_eth.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to - * a single module that works for both parts: "stm32fxx_hal_eth" - */ - -#include "stm32fxx_hal_eth.h" diff --git a/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.c b/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.c deleted file mode 100644 index 303b327c1..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.c +++ /dev/null @@ -1,1546 +0,0 @@ -/** - ****************************************************************************** - * @file stm32fxx_hal_eth.c - * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 - * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * @verbatim - * ============================================================================== - ##### How to use this driver ##### - #####============================================================================== - #####[..] - #####(#)Declare a ETH_HandleTypeDef handle structure, for example: - ##### ETH_HandleTypeDef heth; - ##### - #####(#)Fill parameters of Init structure in heth handle - ##### - #####(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) - ##### - #####(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - ##### (##) Enable the Ethernet interface clock using - ##### (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); - ##### (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); - ##### (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - ##### - ##### (##) Initialize the related GPIO clocks - ##### (##) Configure Ethernet pin-out - ##### (##) Configure Ethernet NVIC interrupt (IT mode) - ##### - #####(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: - ##### (##) HAL_ETH_DMATxDescListInit(); for Transmission process - ##### (##) HAL_ETH_DMARxDescListInit(); for Reception process - ##### - #####(#)Enable MAC and DMA transmission and reception: - ##### (##) HAL_ETH_Start(); - ##### - #####(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer - ##### the frame to MAC TX FIFO: - ##### (##) HAL_ETH_TransmitFrame(); - ##### - #####(#)Poll for a received frame in ETH RX DMA Descriptors and get received - ##### frame parameters - ##### (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) - ##### - #####(#) Get a received frame when an ETH RX interrupt occurs: - ##### (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) - ##### - #####(#) Communicate with external PHY device: - ##### (##) Read a specific register from the PHY - ##### HAL_ETH_ReadPHYRegister(); - ##### (##) Write data to a specific RHY register: - ##### HAL_ETH_WritePHYRegister(); - ##### - #####(#) Configure the Ethernet MAC after ETH peripheral initialization - ##### HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - ##### - #####(#) Configure the Ethernet DMA after ETH peripheral initialization - ##### HAL_ETH_ConfigDMA(); all DMA parameters should be filled. - ##### - #####-@- The PTP protocol and the DMA descriptors ring mode are not supported - ##### in this driver - ##### - #####@endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32fxx_hal_eth.h" - -#if defined( STM32F7xx ) - #include "stm32f7xx_hal.h" - #define stm_is_F7 1 -#elif defined( STM32F4xx ) - #include "stm32f4xx_hal.h" - #define stm_is_F4 1 -#elif defined( STM32F2xx ) - #include "stm32f2xx_hal.h" - #define stm_is_F2 1 -#elif defined( STM32F1xx ) - #include "stm32f1xx_hal.h" - #define stm_is_F1 1 -#else /* if defined( STM32F7xx ) */ - #error For what part should this be compiled? -#endif /* if defined( STM32F7xx ) */ - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup ETH ETH - * @brief ETH HAL module driver - * @{ - */ - -#if !defined( ARRAY_SIZE ) - #define ARRAY_SIZE( x ) ( sizeof( x ) / sizeof( x )[ 0 ] ) -#endif - -#ifdef HAL_ETH_MODULE_ENABLED - - #if ( stm_is_F1 != 0 || stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 ) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup ETH_Private_Constants ETH Private Constants - * @{ - */ -/* Some macros have been renamed through time. */ - #ifndef ETH_MACMIIAR_CR_Div16 - #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_DIV16 - #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_DIV26 - #define ETH_MACMIIAR_CR_Div42 ETH_MACMIIAR_CR_DIV42 - #endif - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup ETH_Private_Functions ETH Private Functions - * @{ - */ - static void ETH_MACDMAConfig( ETH_HandleTypeDef * heth, - uint32_t err ); - static void ETH_MACAddressConfig( ETH_HandleTypeDef * heth, - uint32_t MacAddr, - uint8_t * Addr ); - static void ETH_MACReceptionEnable( ETH_HandleTypeDef * heth ); - static void ETH_MACReceptionDisable( ETH_HandleTypeDef * heth ); - static void ETH_MACTransmissionEnable( ETH_HandleTypeDef * heth ); - static void ETH_MACTransmissionDisable( ETH_HandleTypeDef * heth ); - static void ETH_DMATransmissionEnable( ETH_HandleTypeDef * heth ); - static void ETH_DMATransmissionDisable( ETH_HandleTypeDef * heth ); - static void ETH_DMAReceptionEnable( ETH_HandleTypeDef * heth ); - static void ETH_DMAReceptionDisable( ETH_HandleTypeDef * heth ); - static void ETH_FlushTransmitFIFO( ETH_HandleTypeDef * heth ); - -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Functions ETH Exported Functions - * @{ - */ - -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - * @verbatim - * =============================================================================== - ##### Initialization and de-initialization functions ##### - #####=============================================================================== - #####[..] This section provides functions allowing to: - #####(+) Initialize and configure the Ethernet peripheral - #####(+) De-initialize the Ethernet peripheral - ##### - #####@endverbatim - * @{ - */ - extern void vMACBProbePhy( void ); - -/** - * @brief Initializes the Ethernet MAC and DMA according to default - * parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef * heth ) - { - uint32_t tmpreg = 0uL; - uint32_t hclk = 60000000uL; - uint32_t err = ETH_SUCCESS; - - /* Check the ETH peripheral state */ - if( heth == NULL ) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param( IS_ETH_AUTONEGOTIATION( heth->Init.AutoNegotiation ) ); - assert_param( IS_ETH_RX_MODE( heth->Init.RxMode ) ); - assert_param( IS_ETH_CHECKSUM_MODE( heth->Init.ChecksumMode ) ); - assert_param( IS_ETH_MEDIA_INTERFACE( heth->Init.MediaInterface ) ); - - if( heth->State == HAL_ETH_STATE_RESET ) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspInit( heth ); - } - - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Select MII or RMII Mode*/ - SYSCFG->PMC &= ~( SYSCFG_PMC_MII_RMII_SEL ); - SYSCFG->PMC |= ( uint32_t ) heth->Init.MediaInterface; - - /* Ethernet Software reset */ - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - /* Also enable EDFE: Enhanced descriptor format enable. */ - heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE; - - /* Wait for software reset */ - while( ( heth->Instance->DMABMR & ETH_DMABMR_SR ) != ( uint32_t ) RESET ) - { - /* If your program hangs here, please check the value of 'ipconfigUSE_RMII'. */ - } - - /*-------------------------------- MAC Initialization ----------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg &= ETH_MACMIIAR_CR_MASK; - - /* Get hclk frequency value (e.g. 168,000,000) */ - hclk = HAL_RCC_GetHCLKFreq(); - #if !defined( STM32F2xx ) - /* Set CR bits depending on hclk value */ - if( ( hclk >= 20000000uL ) && ( hclk < 35000000uL ) ) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div16; - } - else if( ( hclk >= 35000000uL ) && ( hclk < 60000000uL ) ) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26; - } - else - { - #if ( stm_is_F1 != 0 ) - { - /* The STM32F1xx has a frequency up to 72 MHz. */ - /* CSR Clock Range between 60-72 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div42; - } - #else - { - if( ( hclk >= 60000000uL ) && ( hclk < 100000000uL ) ) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div42; - } - else if( ( hclk >= 100000000uL ) && ( hclk < 150000000uL ) ) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div62; - } - else /* ( ( hclk >= 150000000uL ) && ( hclk <= 183000000uL ) ) */ - { - /* CSR Clock Range between 150-183 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div102; - } - } - #endif /* if ( stm_is_F1 != 0 ) */ - } - #else /* if !defined( STM32F2xx ) */ - /* Clock settings for STM32F2 only. */ - /* Set CR bits depending on hclk value */ - if( ( hclk >= 20000000U ) && ( hclk < 35000000U ) ) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div16; - } - else if( ( hclk >= 35000000U ) && ( hclk < 60000000U ) ) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26; - } - else if( ( hclk >= 60000000U ) && ( hclk < 100000000U ) ) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div42; - } - else /* ((hclk >= 100000000)&&(hclk < 120000000)) */ - { - /* CSR Clock Range between 100-120 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div62; - } - #endif /* defined(STM32F2xx) */ - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - heth->Instance->MACMIIAR = ( uint32_t ) tmpreg; - - /* Initialise the MACB and set all PHY properties */ - vMACBProbePhy(); - - /* Config MAC and DMA */ - ETH_MACDMAConfig( heth, err ); - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* - * Disable the interrupts that are related to the MMC counters. - * These interrupts are enabled by default. The interrupt can - * only be acknowledged by reading the corresponding counter. - */ - - heth->Instance->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM; - heth->Instance->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM; - heth->Instance->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM; - - /* Return function status */ - return HAL_OK; - } - -/** - * @brief De-Initializes the ETH peripheral. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_DeInit( ETH_HandleTypeDef * heth ) - { - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspDeInit( heth ); - - /* Set ETH HAL state to Disabled */ - heth->State = HAL_ETH_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK( heth ); - - /* Return function status */ - return HAL_OK; - } - -/** - * @brief Initializes the ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_MspInit( ETH_HandleTypeDef * heth ) - { - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_MspInit could be implemented in the user file - */ - ( void ) heth; - } - -/** - * @brief DeInitializes ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_MspDeInit( ETH_HandleTypeDef * heth ) - { - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_MspDeInit could be implemented in the user file - */ - ( void ) heth; - } - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * - * @verbatim - * ============================================================================== - ##### IO operation functions ##### - #####============================================================================== - #####[..] This section provides functions allowing to: - ##### (+) Transmit a frame - ##### HAL_ETH_TransmitFrame(); - ##### (+) Receive a frame - ##### HAL_ETH_GetReceivedFrame(); - ##### HAL_ETH_GetReceivedFrame_IT(); - ##### (+) Read from an External PHY register - ##### HAL_ETH_ReadPHYRegister(); - ##### (+) Write to an External PHY register - ##### HAL_ETH_WritePHYRegister(); - ##### - #####@endverbatim - ##### - * @{ - */ - - #define ETH_DMA_ALL_INTS \ - ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \ - ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \ - ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) - - #define INT_MASK ( ( uint32_t ) ~( ETH_DMA_IT_TBU ) ) - void HAL_ETH_IRQHandler( ETH_HandleTypeDef * heth ) - { - uint32_t dmasr; - - dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS; - heth->Instance->DMASR = dmasr; - - /* Frame received */ - if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 ) - { - /* Receive complete callback */ - HAL_ETH_RxCpltCallback( heth ); - } - - /* Frame transmitted */ - if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 ) - { - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback( heth ); - } - - /* ETH DMA Error */ - if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 ) - { - /* Ethernet Error callback */ - HAL_ETH_ErrorCallback( heth ); - } - } - -/** - * @brief Tx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ) - { - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_TxCpltCallback could be implemented in the user file - */ - ( void ) heth; - } - -/** - * @brief Rx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ) - { - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_TxCpltCallback could be implemented in the user file - */ - ( void ) heth; - } - -/** - * @brief Ethernet transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_ErrorCallback( ETH_HandleTypeDef * heth ) - { - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_TxCpltCallback could be implemented in the user file - */ - ( void ) heth; - } - -/** - * @brief Reads a PHY register - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. - * More PHY register could be read depending on the used PHY - * @param RegValue: PHY register value - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef * heth, - uint16_t PHYReg, - uint32_t * RegValue ) - { - uint32_t tmpreg = 0uL; - uint32_t tickstart = 0uL; - HAL_StatusTypeDef xResult; - - /* Check parameters */ - assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) ); - - /* Check the ETH peripheral state */ - if( heth->State == HAL_ETH_STATE_BUSY_RD ) - { - xResult = HAL_BUSY; - } - else - { - __HAL_LOCK( heth ); - - /* Set ETH HAL State to BUSY_RD */ - heth->State = HAL_ETH_STATE_BUSY_RD; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII address register value */ - tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ - tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ - tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while( 1 ) - { - tmpreg = heth->Instance->MACMIIAR; - - if( ( tmpreg & ETH_MACMIIAR_MB ) == 0uL ) - { - /* Get MACMIIDR value */ - *RegValue = ( uint32_t ) heth->Instance->MACMIIDR; - xResult = HAL_OK; - break; - } - - /* Check for the Timeout */ - if( ( HAL_GetTick() - tickstart ) > PHY_READ_TO ) - { - xResult = HAL_TIMEOUT; - break; - } - } - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK( heth ); - } - - /* Return function status */ - return xResult; - } - -/** - * @brief Writes to a PHY register. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. - * More PHY register could be written depending on the used PHY - * @param RegValue: the value to write - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef * heth, - uint16_t PHYReg, - uint32_t RegValue ) - { - uint32_t tmpreg = 0; - uint32_t tickstart = 0; - HAL_StatusTypeDef xResult; - - /* Check parameters */ - assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) ); - - /* Check the ETH peripheral state */ - if( heth->State == HAL_ETH_STATE_BUSY_WR ) - { - xResult = HAL_BUSY; - } - else - { - __HAL_LOCK( heth ); - - /* Set ETH HAL State to BUSY_WR */ - heth->State = HAL_ETH_STATE_BUSY_WR; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII register address value */ - tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ - tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ - tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Give the value to the MII data register */ - heth->Instance->MACMIIDR = ( uint16_t ) RegValue; - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while( 1 ) - { - tmpreg = heth->Instance->MACMIIAR; - - if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul ) - { - xResult = HAL_OK; - break; - } - - /* Check for the Timeout */ - if( ( HAL_GetTick() - tickstart ) > PHY_WRITE_TO ) - { - xResult = HAL_TIMEOUT; - break; - } - } - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK( heth ); - } - - /* Return function status */ - return xResult; - } - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * - * @verbatim - * =============================================================================== - ##### Peripheral Control functions ##### - #####=============================================================================== - #####[..] This section provides functions allowing to: - #####(+) Enable MAC and DMA transmission and reception. - ##### HAL_ETH_Start(); - #####(+) Disable MAC and DMA transmission and reception. - ##### HAL_ETH_Stop(); - #####(+) Set the MAC configuration in runtime mode - ##### HAL_ETH_ConfigMAC(); - #####(+) Set the DMA configuration in runtime mode - ##### HAL_ETH_ConfigDMA(); - ##### - #####@endverbatim - * @{ - */ - -/** - * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef * heth ) - { - /* Process Locked */ - __HAL_LOCK( heth ); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionEnable( heth ); - - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionEnable( heth ); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO( heth ); - - /* Start DMA transmission */ - ETH_DMATransmissionEnable( heth ); - - /* Start DMA reception */ - ETH_DMAReceptionEnable( heth ); - - /* Set the ETH state to READY*/ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK( heth ); - - /* Return function status */ - return HAL_OK; - } - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Stop( ETH_HandleTypeDef * heth ) - { - /* Process Locked */ - __HAL_LOCK( heth ); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Stop DMA transmission */ - ETH_DMATransmissionDisable( heth ); - - /* Stop DMA reception */ - ETH_DMAReceptionDisable( heth ); - - /* Disable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionDisable( heth ); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO( heth ); - - /* Disable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionDisable( heth ); - - /* Set the ETH state*/ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK( heth ); - - /* Return function status */ - return HAL_OK; - } - - static void vRegisterDelay() - { - uint32_t uxCount; - - /* - * Regarding the HAL delay functions, I noticed that HAL delay is being used to workaround the - * "Successive write operations to the same register might not be fully taken into account" errata. - * The workaround requires a delay of four TX_CLK/RX_CLK clock cycles. For a 10 Mbit connection, - * these clocks are running at 2.5 MHz, so this delay would be at most 1.6 microseconds. - * 180 Mhz = 288 loops - * 168 Mhz = 269 loops - * 100 Mhz = 160 loops - * 84 Mhz = 134 loops - */ - #define WAIT_TIME_NS 1600uL /* 1.6 microseconds */ - #define CPU_MAX_FREQ SystemCoreClock /* 84, 100, 168 or 180 MHz */ - uint32_t NOP_COUNT = ( WAIT_TIME_NS * ( CPU_MAX_FREQ / 1000uL ) ) / 1000000uL; - - for( uxCount = NOP_COUNT; uxCount > 0uL; uxCount-- ) - { - __NOP(); - } - } - - static void prvWriteMACFCR( ETH_HandleTypeDef * heth, - uint32_t ulValue ) - { - /* Enable the MAC transmission */ - heth->Instance->MACFCR = ulValue; - - /* Wait until the write operation will be taken into account: - * at least four TX_CLK/RX_CLK clock cycles. - * Read it back, wait a ms and */ - ( void ) heth->Instance->MACFCR; - - vRegisterDelay(); - - heth->Instance->MACFCR = ulValue; - } - - static void prvWriteDMAOMR( ETH_HandleTypeDef * heth, - uint32_t ulValue ) - { - /* Enable the MAC transmission */ - heth->Instance->DMAOMR = ulValue; - - /* Wait until the write operation will be taken into account: - * at least four TX_CLK/RX_CLK clock cycles. - * Read it back, wait a ms and */ - ( void ) heth->Instance->DMAOMR; - - vRegisterDelay(); - - heth->Instance->DMAOMR = ulValue; - } - - static void prvWriteMACCR( ETH_HandleTypeDef * heth, - uint32_t ulValue ) - { - /* Enable the MAC transmission */ - heth->Instance->MACCR = ulValue; - - /* Wait until the write operation will be taken into account: - * at least four TX_CLK/RX_CLK clock cycles. - * Read it back, wait a ms and */ - ( void ) heth->Instance->MACCR; - - vRegisterDelay(); - - heth->Instance->MACCR = ulValue; - } - -/** - * @brief Set ETH MAC Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf: MAC Configuration structure - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_ConfigMAC( ETH_HandleTypeDef * heth, - ETH_MACInitTypeDef * macconf ) - { - uint32_t tmpreg = 0uL; - - /* Process Locked */ - __HAL_LOCK( heth ); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - assert_param( IS_ETH_SPEED( heth->Init.Speed ) ); - assert_param( IS_ETH_DUPLEX_MODE( heth->Init.DuplexMode ) ); - - if( macconf != NULL ) - { - /* Check the parameters */ - assert_param( IS_ETH_WATCHDOG( macconf->Watchdog ) ); - assert_param( IS_ETH_JABBER( macconf->Jabber ) ); - assert_param( IS_ETH_INTER_FRAME_GAP( macconf->InterFrameGap ) ); - assert_param( IS_ETH_CARRIER_SENSE( macconf->CarrierSense ) ); - assert_param( IS_ETH_RECEIVE_OWN( macconf->ReceiveOwn ) ); - assert_param( IS_ETH_LOOPBACK_MODE( macconf->LoopbackMode ) ); - assert_param( IS_ETH_CHECKSUM_OFFLOAD( macconf->ChecksumOffload ) ); - assert_param( IS_ETH_RETRY_TRANSMISSION( macconf->RetryTransmission ) ); - assert_param( IS_ETH_AUTOMATIC_PADCRC_STRIP( macconf->AutomaticPadCRCStrip ) ); - assert_param( IS_ETH_BACKOFF_LIMIT( macconf->BackOffLimit ) ); - assert_param( IS_ETH_DEFERRAL_CHECK( macconf->DeferralCheck ) ); - assert_param( IS_ETH_RECEIVE_ALL( macconf->ReceiveAll ) ); - assert_param( IS_ETH_SOURCE_ADDR_FILTER( macconf->SourceAddrFilter ) ); - assert_param( IS_ETH_CONTROL_FRAMES( macconf->PassControlFrames ) ); - assert_param( IS_ETH_BROADCAST_FRAMES_RECEPTION( macconf->BroadcastFramesReception ) ); - assert_param( IS_ETH_DESTINATION_ADDR_FILTER( macconf->DestinationAddrFilter ) ); - assert_param( IS_ETH_PROMISCUOUS_MODE( macconf->PromiscuousMode ) ); - assert_param( IS_ETH_MULTICAST_FRAMES_FILTER( macconf->MulticastFramesFilter ) ); - assert_param( IS_ETH_UNICAST_FRAMES_FILTER( macconf->UnicastFramesFilter ) ); - assert_param( IS_ETH_PAUSE_TIME( macconf->PauseTime ) ); - assert_param( IS_ETH_ZEROQUANTA_PAUSE( macconf->ZeroQuantaPause ) ); - assert_param( IS_ETH_PAUSE_LOW_THRESHOLD( macconf->PauseLowThreshold ) ); - assert_param( IS_ETH_UNICAST_PAUSE_FRAME_DETECT( macconf->UnicastPauseFrameDetect ) ); - assert_param( IS_ETH_RECEIVE_FLOWCONTROL( macconf->ReceiveFlowControl ) ); - assert_param( IS_ETH_TRANSMIT_FLOWCONTROL( macconf->TransmitFlowControl ) ); - assert_param( IS_ETH_VLAN_TAG_COMPARISON( macconf->VLANTagComparison ) ); - assert_param( IS_ETH_VLAN_TAG_IDENTIFIER( macconf->VLANTagIdentifier ) ); - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = heth->Instance->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; - - tmpreg |= ( uint32_t ) ( - macconf->Watchdog | - macconf->Jabber | - macconf->InterFrameGap | - macconf->CarrierSense | - heth->Init.Speed | - macconf->ReceiveOwn | - macconf->LoopbackMode | - heth->Init.DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | - macconf->DeferralCheck ); - - /* Write to ETHERNET MACCR */ - prvWriteMACCR( heth, tmpreg ); - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - heth->Instance->MACFFR = ( uint32_t ) ( - macconf->ReceiveAll | - macconf->SourceAddrFilter | - macconf->PassControlFrames | - macconf->BroadcastFramesReception | - macconf->DestinationAddrFilter | - macconf->PromiscuousMode | - macconf->MulticastFramesFilter | - macconf->UnicastFramesFilter ); - - /* Wait until the write operation will be taken into account : - * at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = heth->Instance->MACFFR; - vRegisterDelay(); - heth->Instance->MACFFR = tmpreg; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - heth->Instance->MACHTHR = ( uint32_t ) macconf->HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - heth->Instance->MACHTLR = ( uint32_t ) macconf->HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg = heth->Instance->MACFCR; - /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; - - tmpreg |= ( uint32_t ) ( ( - macconf->PauseTime << 16 ) | - macconf->ZeroQuantaPause | - macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | - macconf->ReceiveFlowControl | - macconf->TransmitFlowControl ); - - /* Write to ETHERNET MACFCR */ - prvWriteMACFCR( heth, tmpreg ); - - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - heth->Instance->MACVLANTR = ( uint32_t ) ( macconf->VLANTagComparison | - macconf->VLANTagIdentifier ); - - /* Wait until the write operation will be taken into account : - * at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = heth->Instance->MACVLANTR; - vRegisterDelay(); - heth->Instance->MACVLANTR = tmpreg; - } - else /* macconf == NULL : here we just configure Speed and Duplex mode */ - { - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = heth->Instance->MACCR; - - /* Clear FES and DM bits */ - tmpreg &= ~( ( uint32_t ) 0x00004800uL ); - - tmpreg |= ( uint32_t ) ( heth->Init.Speed | heth->Init.DuplexMode ); - - /* Write to ETHERNET MACCR */ - prvWriteMACCR( heth, tmpreg ); - } - - /* Set the ETH state to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK( heth ); - - /* Return function status */ - return HAL_OK; - } - -/** - * @brief Sets ETH DMA Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf: DMA Configuration structure - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_ConfigDMA( ETH_HandleTypeDef * heth, - ETH_DMAInitTypeDef * dmaconf ) - { - uint32_t tmpreg = 0uL; - - /* Process Locked */ - __HAL_LOCK( heth ); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Check parameters */ - assert_param( IS_ETH_DROP_TCPIP_CHECKSUM_FRAME( dmaconf->DropTCPIPChecksumErrorFrame ) ); - assert_param( IS_ETH_RECEIVE_STORE_FORWARD( dmaconf->ReceiveStoreForward ) ); - assert_param( IS_ETH_FLUSH_RECEIVE_FRAME( dmaconf->FlushReceivedFrame ) ); - assert_param( IS_ETH_TRANSMIT_STORE_FORWARD( dmaconf->TransmitStoreForward ) ); - assert_param( IS_ETH_TRANSMIT_THRESHOLD_CONTROL( dmaconf->TransmitThresholdControl ) ); - assert_param( IS_ETH_FORWARD_ERROR_FRAMES( dmaconf->ForwardErrorFrames ) ); - assert_param( IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES( dmaconf->ForwardUndersizedGoodFrames ) ); - assert_param( IS_ETH_RECEIVE_THRESHOLD_CONTROL( dmaconf->ReceiveThresholdControl ) ); - assert_param( IS_ETH_SECOND_FRAME_OPERATE( dmaconf->SecondFrameOperate ) ); - assert_param( IS_ETH_ADDRESS_ALIGNED_BEATS( dmaconf->AddressAlignedBeats ) ); - assert_param( IS_ETH_FIXED_BURST( dmaconf->FixedBurst ) ); - assert_param( IS_ETH_RXDMA_BURST_LENGTH( dmaconf->RxDMABurstLength ) ); - assert_param( IS_ETH_TXDMA_BURST_LENGTH( dmaconf->TxDMABurstLength ) ); - assert_param( IS_ETH_ENHANCED_DESCRIPTOR_FORMAT( dmaconf->EnhancedDescriptorFormat ) ); - assert_param( IS_ETH_DMA_DESC_SKIP_LENGTH( dmaconf->DescriptorSkipLength ) ); - assert_param( IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX( dmaconf->DMAArbitration ) ); - - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg = heth->Instance->DMAOMR; - /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; - - tmpreg |= ( uint32_t ) ( - dmaconf->DropTCPIPChecksumErrorFrame | - dmaconf->ReceiveStoreForward | - dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | - dmaconf->TransmitThresholdControl | - dmaconf->ForwardErrorFrames | - dmaconf->ForwardUndersizedGoodFrames | - dmaconf->ReceiveThresholdControl | - dmaconf->SecondFrameOperate ); - - /* Write to ETHERNET DMAOMR */ - prvWriteDMAOMR( heth, tmpreg ); - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - heth->Instance->DMABMR = ( uint32_t ) ( dmaconf->AddressAlignedBeats | - dmaconf->FixedBurst | - dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmaconf->TxDMABurstLength | - dmaconf->EnhancedDescriptorFormat | - ( dmaconf->DescriptorSkipLength << 2 ) | - dmaconf->DMAArbitration | - ETH_DMABMR_USP ); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - * at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = heth->Instance->DMABMR; - vRegisterDelay(); - heth->Instance->DMABMR = tmpreg; - - /* Set the ETH state to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK( heth ); - - /* Return function status */ - return HAL_OK; - } - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * - * @verbatim - * =============================================================================== - ##### Peripheral State functions ##### - #####=============================================================================== - #####[..] - #####This subsection permits to get in run-time the status of the peripheral - #####and the data flow. - ##### (+) Get the ETH handle state: - ##### HAL_ETH_GetState(); - ##### - ##### - #####@endverbatim - * @{ - */ - -/** - * @brief Return the ETH HAL state - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL state - */ - HAL_ETH_StateTypeDef HAL_ETH_GetState( ETH_HandleTypeDef * heth ) - { - /* Return ETH state */ - return heth->State; - } - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup ETH_Private_Functions - * @{ - */ - -/** - * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param err: Ethernet Init error - * @retval HAL status - */ - static void ETH_MACDMAConfig( ETH_HandleTypeDef * heth, - uint32_t err ) - { - ETH_MACInitTypeDef macinit; - ETH_DMAInitTypeDef dmainit; - uint32_t tmpreg = 0uL; - - if( err != ETH_SUCCESS ) /* Auto-negotiation failed */ - { - /* Set Ethernet duplex mode to Full-duplex */ - heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX; - - /* Set Ethernet speed to 100M */ - heth->Init.Speed = ETH_SPEED_100M; - } - - /* Ethernet MAC default initialization **************************************/ - macinit.Watchdog = ETH_WATCHDOG_ENABLE; - macinit.Jabber = ETH_JABBER_ENABLE; - macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; - macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; - macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; - macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; - - if( heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE ) - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; - } - else - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; - } - - macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; - macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; - macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; - macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; - macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; - macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; - macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; - macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; - macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; - macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - /* Allow all multicast addresses while testing. */ - /* macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; */ - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE; - macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - macinit.HashTableHigh = 0x0uL; - macinit.HashTableLow = 0x0uL; - macinit.PauseTime = 0x0uL; - macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; - macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; - macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; - macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; - macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - macinit.VLANTagIdentifier = 0x0uL; - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg = heth->Instance->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH Watchdog value */ - /* Set the JD: bit according to ETH Jabber value */ - /* Set the IFG bit according to ETH InterFrameGap value */ - /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ - /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ - /* Set the IPCO bit according to ETH ChecksumOffload value */ - /* Set the DR bit according to ETH RetryTransmission value */ - /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH BackOffLimit value */ - /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg |= ( uint32_t ) ( macinit.Watchdog | - macinit.Jabber | - macinit.InterFrameGap | - macinit.CarrierSense | - heth->Init.Speed | - macinit.ReceiveOwn | - macinit.LoopbackMode | - heth->Init.DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | - macinit.DeferralCheck ); - - /* Write to ETHERNET MACCR */ - prvWriteMACCR( heth, tmpreg ); - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ - /* Set the PCF bit according to ETH PassControlFrames value */ - /* Set the DBF bit according to ETH BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH DestinationAddrFilter value */ - /* Set the PR bit according to ETH PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - heth->Instance->MACFFR = ( uint32_t ) ( macinit.ReceiveAll | - macinit.SourceAddrFilter | - macinit.PassControlFrames | - macinit.BroadcastFramesReception | - macinit.DestinationAddrFilter | - macinit.PromiscuousMode | - macinit.MulticastFramesFilter | - macinit.UnicastFramesFilter ); - - /* Wait until the write operation will be taken into account: - * at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = heth->Instance->MACFFR; - vRegisterDelay(); - heth->Instance->MACFFR = tmpreg; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ - /* Write to ETHERNET MACHTHR */ - heth->Instance->MACHTHR = ( uint32_t ) macinit.HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - heth->Instance->MACHTLR = ( uint32_t ) macinit.HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg = heth->Instance->MACFCR; - /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH PauseTime value */ - /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ - /* Set the PLT bit according to ETH PauseLowThreshold value */ - /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg |= ( uint32_t ) ( ( macinit.PauseTime << 16 ) | - macinit.ZeroQuantaPause | - macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | - macinit.ReceiveFlowControl | - macinit.TransmitFlowControl ); - - /* Write to ETHERNET MACFCR */ - prvWriteMACFCR( heth, tmpreg ); - - /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ - /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - heth->Instance->MACVLANTR = ( uint32_t ) ( macinit.VLANTagComparison | - macinit.VLANTagIdentifier ); - - /* Wait until the write operation will be taken into account: - * at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = heth->Instance->MACVLANTR; - vRegisterDelay(); - heth->Instance->MACVLANTR = tmpreg; - - /* Ethernet DMA default initialization ************************************/ - dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; - dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; - dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; - dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; - dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; - dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; - dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; - dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; - dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; - dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; - dmainit.DescriptorSkipLength = 0x0uL; - dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - - /* Get the ETHERNET DMAOMR value */ - tmpreg = heth->Instance->DMAOMR; - /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH ReceiveStoreForward value */ - /* Set the DFF bit according to ETH FlushReceivedFrame value */ - /* Set the TSF bit according to ETH TransmitStoreForward value */ - /* Set the TTC bit according to ETH TransmitThresholdControl value */ - /* Set the FEF bit according to ETH ForwardErrorFrames value */ - /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg |= ( uint32_t ) ( dmainit.DropTCPIPChecksumErrorFrame | - dmainit.ReceiveStoreForward | - dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | - dmainit.TransmitThresholdControl | - dmainit.ForwardErrorFrames | - dmainit.ForwardUndersizedGoodFrames | - dmainit.ReceiveThresholdControl | - dmainit.SecondFrameOperate ); - - /* Write to ETHERNET DMAOMR */ - prvWriteDMAOMR( heth, tmpreg ); - - /*----------------------- ETHERNET DMABMR Configuration ------------------*/ - /* Set the AAL bit according to ETH AddressAlignedBeats value */ - /* Set the FB bit according to ETH FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ - /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ - /* Set the DSL bit according to ETH DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH DMAArbitration value */ - heth->Instance->DMABMR = ( uint32_t ) ( dmainit.AddressAlignedBeats | - dmainit.FixedBurst | - dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmainit.TxDMABurstLength | - dmainit.EnhancedDescriptorFormat | - ( dmainit.DescriptorSkipLength << 2 ) | - dmainit.DMAArbitration | - ETH_DMABMR_USP ); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - * at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = heth->Instance->DMABMR; - vRegisterDelay(); - heth->Instance->DMABMR = tmpreg; - - if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE ) - { - /* Enable the Ethernet Rx Interrupt */ - __HAL_ETH_DMA_ENABLE_IT( ( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R ); - } - - /* Initialize MAC address in ethernet MAC */ - ETH_MACAddressConfig( heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr ); - } - -/** - * @brief Configures the selected MAC address. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param MacAddr: The MAC address to configure - * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 - * @arg ETH_MAC_Address2: MAC Address2 - * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr: Pointer to MAC address buffer data (6 bytes) - * @retval HAL status - */ - static void ETH_MACAddressConfig( ETH_HandleTypeDef * heth, - uint32_t MacAddr, - uint8_t * Addr ) - { - uint32_t tmpreg; - - ( void ) heth; - - /* Check the parameters */ - assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) ); - - /* Calculate the selected MAC address high register */ - /* Register ETH_MACA0HR: Bit 31 MO: Always 1. */ - tmpreg = 0x80000000uL | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ]; - /* Load the selected MAC address high register */ - ( *( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg; - /* Calculate the selected MAC address low register */ - tmpreg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ]; - - /* Load the selected MAC address low register */ - ( *( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg; - } - -/** - * @brief Enables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_MACTransmissionEnable( ETH_HandleTypeDef * heth ) - { - uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE; - - prvWriteMACCR( heth, tmpreg ); - } - -/** - * @brief Disables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_MACTransmissionDisable( ETH_HandleTypeDef * heth ) - { - uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE ); - - prvWriteMACCR( heth, tmpreg ); - } - -/** - * @brief Enables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_MACReceptionEnable( ETH_HandleTypeDef * heth ) - { - __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE; - - prvWriteMACCR( heth, tmpreg ); - } - -/** - * @brief Disables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_MACReceptionDisable( ETH_HandleTypeDef * heth ) - { - __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE ); - - prvWriteMACCR( heth, tmpreg ); - } - -/** - * @brief Enables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_DMATransmissionEnable( ETH_HandleTypeDef * heth ) - { - /* Enable the DMA transmission */ - __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST; - - prvWriteDMAOMR( heth, tmpreg ); - } - -/** - * @brief Disables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_DMATransmissionDisable( ETH_HandleTypeDef * heth ) - { - /* Disable the DMA transmission */ - __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST ); - - prvWriteDMAOMR( heth, tmpreg ); - } - -/** - * @brief Enables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_DMAReceptionEnable( ETH_HandleTypeDef * heth ) - { - /* Enable the DMA reception */ - __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR; - - prvWriteDMAOMR( heth, tmpreg ); - } - -/** - * @brief Disables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_DMAReceptionDisable( ETH_HandleTypeDef * heth ) - { - /* Disable the DMA reception */ - __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR ); - - prvWriteDMAOMR( heth, tmpreg ); - } - -/** - * @brief Clears the ETHERNET transmit FIFO. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_FlushTransmitFIFO( ETH_HandleTypeDef * heth ) - { - /* Set the Flush Transmit FIFO bit */ - __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF; - - prvWriteDMAOMR( heth, tmpreg ); - } - -/** - * @} - */ - #endif /* stm_is_F1 != 0 || stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 */ - -#endif /* HAL_ETH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.h b/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.h deleted file mode 100644 index 32af04819..000000000 --- a/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.h +++ /dev/null @@ -1,2413 +0,0 @@ -/** - ****************************************************************************** - * @file stm32fxx_hal_eth.h - * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 - * @brief Header file of ETH HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32Fxx_HAL_ETH_H - #define __STM32Fxx_HAL_ETH_H - -/* make sure that the original ETH headers files won't be included after this. */ - #define __STM32F2xx_HAL_ETH_H - #define __STM32F4xx_HAL_ETH_H - #define __STM32F7xx_HAL_ETH_H - - #if defined( STM32F7xx ) - #include "stm32f7xx_hal.h" - #elif defined( STM32F407xx ) || defined( STM32F417xx ) || defined( STM32F427xx ) || defined( STM32F437xx ) || defined( STM32F429xx ) || defined( STM32F439xx ) - #include "stm32f4xx_hal.h" - #elif defined( STM32F2xx ) - #include "stm32f2xx_hal.h" - #endif - - #ifdef __cplusplus - extern "C" { - #endif - -/** @addtogroup STM32Fxx_HAL_Driver - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/** @addtogroup ETH_Private_Macros - * @{ - */ - #define IS_ETH_PHY_ADDRESS( ADDRESS ) ( ( ADDRESS ) <= 0x20 ) - #define IS_ETH_AUTONEGOTIATION( CMD ) \ - ( ( ( CMD ) == ETH_AUTONEGOTIATION_ENABLE ) || \ - ( ( CMD ) == ETH_AUTONEGOTIATION_DISABLE ) ) - #define IS_ETH_SPEED( SPEED ) \ - ( ( ( SPEED ) == ETH_SPEED_10M ) || \ - ( ( SPEED ) == ETH_SPEED_100M ) ) - #define IS_ETH_DUPLEX_MODE( MODE ) \ - ( ( ( MODE ) == ETH_MODE_FULLDUPLEX ) || \ - ( ( MODE ) == ETH_MODE_HALFDUPLEX ) ) - #define IS_ETH_DUPLEX_MODE( MODE ) \ - ( ( ( MODE ) == ETH_MODE_FULLDUPLEX ) || \ - ( ( MODE ) == ETH_MODE_HALFDUPLEX ) ) - #define IS_ETH_RX_MODE( MODE ) \ - ( ( ( MODE ) == ETH_RXPOLLING_MODE ) || \ - ( ( MODE ) == ETH_RXINTERRUPT_MODE ) ) - #define IS_ETH_RX_MODE( MODE ) \ - ( ( ( MODE ) == ETH_RXPOLLING_MODE ) || \ - ( ( MODE ) == ETH_RXINTERRUPT_MODE ) ) - #define IS_ETH_RX_MODE( MODE ) \ - ( ( ( MODE ) == ETH_RXPOLLING_MODE ) || \ - ( ( MODE ) == ETH_RXINTERRUPT_MODE ) ) - #define IS_ETH_CHECKSUM_MODE( MODE ) \ - ( ( ( MODE ) == ETH_CHECKSUM_BY_HARDWARE ) || \ - ( ( MODE ) == ETH_CHECKSUM_BY_SOFTWARE ) ) - #define IS_ETH_MEDIA_INTERFACE( MODE ) \ - ( ( ( MODE ) == ETH_MEDIA_INTERFACE_MII ) || \ - ( ( MODE ) == ETH_MEDIA_INTERFACE_RMII ) ) - #define IS_ETH_WATCHDOG( CMD ) \ - ( ( ( CMD ) == ETH_WATCHDOG_ENABLE ) || \ - ( ( CMD ) == ETH_WATCHDOG_DISABLE ) ) - #define IS_ETH_JABBER( CMD ) \ - ( ( ( CMD ) == ETH_JABBER_ENABLE ) || \ - ( ( CMD ) == ETH_JABBER_DISABLE ) ) - #define IS_ETH_INTER_FRAME_GAP( GAP ) \ - ( ( ( GAP ) == ETH_INTERFRAMEGAP_96BIT ) || \ - ( ( GAP ) == ETH_INTERFRAMEGAP_88BIT ) || \ - ( ( GAP ) == ETH_INTERFRAMEGAP_80BIT ) || \ - ( ( GAP ) == ETH_INTERFRAMEGAP_72BIT ) || \ - ( ( GAP ) == ETH_INTERFRAMEGAP_64BIT ) || \ - ( ( GAP ) == ETH_INTERFRAMEGAP_56BIT ) || \ - ( ( GAP ) == ETH_INTERFRAMEGAP_48BIT ) || \ - ( ( GAP ) == ETH_INTERFRAMEGAP_40BIT ) ) - #define IS_ETH_CARRIER_SENSE( CMD ) \ - ( ( ( CMD ) == ETH_CARRIERSENCE_ENABLE ) || \ - ( ( CMD ) == ETH_CARRIERSENCE_DISABLE ) ) - #define IS_ETH_RECEIVE_OWN( CMD ) \ - ( ( ( CMD ) == ETH_RECEIVEOWN_ENABLE ) || \ - ( ( CMD ) == ETH_RECEIVEOWN_DISABLE ) ) - #define IS_ETH_LOOPBACK_MODE( CMD ) \ - ( ( ( CMD ) == ETH_LOOPBACKMODE_ENABLE ) || \ - ( ( CMD ) == ETH_LOOPBACKMODE_DISABLE ) ) - #define IS_ETH_CHECKSUM_OFFLOAD( CMD ) \ - ( ( ( CMD ) == ETH_CHECKSUMOFFLAOD_ENABLE ) || \ - ( ( CMD ) == ETH_CHECKSUMOFFLAOD_DISABLE ) ) - #define IS_ETH_RETRY_TRANSMISSION( CMD ) \ - ( ( ( CMD ) == ETH_RETRYTRANSMISSION_ENABLE ) || \ - ( ( CMD ) == ETH_RETRYTRANSMISSION_DISABLE ) ) - #define IS_ETH_AUTOMATIC_PADCRC_STRIP( CMD ) \ - ( ( ( CMD ) == ETH_AUTOMATICPADCRCSTRIP_ENABLE ) || \ - ( ( CMD ) == ETH_AUTOMATICPADCRCSTRIP_DISABLE ) ) - #define IS_ETH_BACKOFF_LIMIT( LIMIT ) \ - ( ( ( LIMIT ) == ETH_BACKOFFLIMIT_10 ) || \ - ( ( LIMIT ) == ETH_BACKOFFLIMIT_8 ) || \ - ( ( LIMIT ) == ETH_BACKOFFLIMIT_4 ) || \ - ( ( LIMIT ) == ETH_BACKOFFLIMIT_1 ) ) - #define IS_ETH_DEFERRAL_CHECK( CMD ) \ - ( ( ( CMD ) == ETH_DEFFERRALCHECK_ENABLE ) || \ - ( ( CMD ) == ETH_DEFFERRALCHECK_DISABLE ) ) - #define IS_ETH_RECEIVE_ALL( CMD ) \ - ( ( ( CMD ) == ETH_RECEIVEALL_ENABLE ) || \ - ( ( CMD ) == ETH_RECEIVEAll_DISABLE ) ) - #define IS_ETH_SOURCE_ADDR_FILTER( CMD ) \ - ( ( ( CMD ) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE ) || \ - ( ( CMD ) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE ) || \ - ( ( CMD ) == ETH_SOURCEADDRFILTER_DISABLE ) ) - #define IS_ETH_CONTROL_FRAMES( PASS ) \ - ( ( ( PASS ) == ETH_PASSCONTROLFRAMES_BLOCKALL ) || \ - ( ( PASS ) == ETH_PASSCONTROLFRAMES_FORWARDALL ) || \ - ( ( PASS ) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ) ) - #define IS_ETH_BROADCAST_FRAMES_RECEPTION( CMD ) \ - ( ( ( CMD ) == ETH_BROADCASTFRAMESRECEPTION_ENABLE ) || \ - ( ( CMD ) == ETH_BROADCASTFRAMESRECEPTION_DISABLE ) ) - #define IS_ETH_DESTINATION_ADDR_FILTER( FILTER ) \ - ( ( ( FILTER ) == ETH_DESTINATIONADDRFILTER_NORMAL ) || \ - ( ( FILTER ) == ETH_DESTINATIONADDRFILTER_INVERSE ) ) - #define IS_ETH_PROMISCUOUS_MODE( CMD ) \ - ( ( ( CMD ) == ETH_PROMISCUOUS_MODE_ENABLE ) || \ - ( ( CMD ) == ETH_PROMISCUOUS_MODE_DISABLE ) ) - #define IS_ETH_MULTICAST_FRAMES_FILTER( FILTER ) \ - ( ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ) || \ - ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_HASHTABLE ) || \ - ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_PERFECT ) || \ - ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_NONE ) ) - #define IS_ETH_UNICAST_FRAMES_FILTER( FILTER ) \ - ( ( ( FILTER ) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ) || \ - ( ( FILTER ) == ETH_UNICASTFRAMESFILTER_HASHTABLE ) || \ - ( ( FILTER ) == ETH_UNICASTFRAMESFILTER_PERFECT ) ) - #define IS_ETH_PAUSE_TIME( TIME ) ( ( TIME ) <= 0xFFFF ) - #define IS_ETH_ZEROQUANTA_PAUSE( CMD ) \ - ( ( ( CMD ) == ETH_ZEROQUANTAPAUSE_ENABLE ) || \ - ( ( CMD ) == ETH_ZEROQUANTAPAUSE_DISABLE ) ) - #define IS_ETH_PAUSE_LOW_THRESHOLD( THRESHOLD ) \ - ( ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS4 ) || \ - ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS28 ) || \ - ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS144 ) || \ - ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS256 ) ) - #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT( CMD ) \ - ( ( ( CMD ) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ) || \ - ( ( CMD ) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ) ) - #define IS_ETH_RECEIVE_FLOWCONTROL( CMD ) \ - ( ( ( CMD ) == ETH_RECEIVEFLOWCONTROL_ENABLE ) || \ - ( ( CMD ) == ETH_RECEIVEFLOWCONTROL_DISABLE ) ) - #define IS_ETH_TRANSMIT_FLOWCONTROL( CMD ) \ - ( ( ( CMD ) == ETH_TRANSMITFLOWCONTROL_ENABLE ) || \ - ( ( CMD ) == ETH_TRANSMITFLOWCONTROL_DISABLE ) ) - #define IS_ETH_VLAN_TAG_COMPARISON( COMPARISON ) \ - ( ( ( COMPARISON ) == ETH_VLANTAGCOMPARISON_12BIT ) || \ - ( ( COMPARISON ) == ETH_VLANTAGCOMPARISON_16BIT ) ) - #define IS_ETH_VLAN_TAG_IDENTIFIER( IDENTIFIER ) ( ( IDENTIFIER ) <= 0xFFFF ) - #define IS_ETH_MAC_ADDRESS0123( ADDRESS ) \ - ( ( ( ADDRESS ) == ETH_MAC_ADDRESS0 ) || \ - ( ( ADDRESS ) == ETH_MAC_ADDRESS1 ) || \ - ( ( ADDRESS ) == ETH_MAC_ADDRESS2 ) || \ - ( ( ADDRESS ) == ETH_MAC_ADDRESS3 ) ) - #define IS_ETH_MAC_ADDRESS123( ADDRESS ) \ - ( ( ( ADDRESS ) == ETH_MAC_ADDRESS1 ) || \ - ( ( ADDRESS ) == ETH_MAC_ADDRESS2 ) || \ - ( ( ADDRESS ) == ETH_MAC_ADDRESS3 ) ) - #define IS_ETH_MAC_ADDRESS_FILTER( FILTER ) \ - ( ( ( FILTER ) == ETH_MAC_ADDRESSFILTER_SA ) || \ - ( ( FILTER ) == ETH_MAC_ADDRESSFILTER_DA ) ) - #define IS_ETH_MAC_ADDRESS_MASK( MASK ) \ - ( ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE6 ) || \ - ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE5 ) || \ - ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE4 ) || \ - ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE3 ) || \ - ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE2 ) || \ - ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE1 ) ) - #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME( CMD ) \ - ( ( ( CMD ) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ) || \ - ( ( CMD ) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ) ) - #define IS_ETH_RECEIVE_STORE_FORWARD( CMD ) \ - ( ( ( CMD ) == ETH_RECEIVESTOREFORWARD_ENABLE ) || \ - ( ( CMD ) == ETH_RECEIVESTOREFORWARD_DISABLE ) ) - #define IS_ETH_FLUSH_RECEIVE_FRAME( CMD ) \ - ( ( ( CMD ) == ETH_FLUSHRECEIVEDFRAME_ENABLE ) || \ - ( ( CMD ) == ETH_FLUSHRECEIVEDFRAME_DISABLE ) ) - #define IS_ETH_TRANSMIT_STORE_FORWARD( CMD ) \ - ( ( ( CMD ) == ETH_TRANSMITSTOREFORWARD_ENABLE ) || \ - ( ( CMD ) == ETH_TRANSMITSTOREFORWARD_DISABLE ) ) - #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL( THRESHOLD ) \ - ( ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ) || \ - ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ) || \ - ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ) || \ - ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ) || \ - ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ) || \ - ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ) || \ - ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ) || \ - ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ) ) - #define IS_ETH_FORWARD_ERROR_FRAMES( CMD ) \ - ( ( ( CMD ) == ETH_FORWARDERRORFRAMES_ENABLE ) || \ - ( ( CMD ) == ETH_FORWARDERRORFRAMES_DISABLE ) ) - #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES( CMD ) \ - ( ( ( CMD ) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ) || \ - ( ( CMD ) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ) ) - #define IS_ETH_RECEIVE_THRESHOLD_CONTROL( THRESHOLD ) \ - ( ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ) || \ - ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ) || \ - ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ) || \ - ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ) ) - #define IS_ETH_SECOND_FRAME_OPERATE( CMD ) \ - ( ( ( CMD ) == ETH_SECONDFRAMEOPERARTE_ENABLE ) || \ - ( ( CMD ) == ETH_SECONDFRAMEOPERARTE_DISABLE ) ) - #define IS_ETH_ADDRESS_ALIGNED_BEATS( CMD ) \ - ( ( ( CMD ) == ETH_ADDRESSALIGNEDBEATS_ENABLE ) || \ - ( ( CMD ) == ETH_ADDRESSALIGNEDBEATS_DISABLE ) ) - #define IS_ETH_FIXED_BURST( CMD ) \ - ( ( ( CMD ) == ETH_FIXEDBURST_ENABLE ) || \ - ( ( CMD ) == ETH_FIXEDBURST_DISABLE ) ) - #define IS_ETH_RXDMA_BURST_LENGTH( LENGTH ) \ - ( ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_1BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_2BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_8BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_16BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_32BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ) || \ - ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ) ) - #define IS_ETH_TXDMA_BURST_LENGTH( LENGTH ) \ - ( ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_1BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_2BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_8BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_16BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_32BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ) || \ - ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ) ) - #define IS_ETH_DMA_DESC_SKIP_LENGTH( LENGTH ) ( ( LENGTH ) <= 0x1F ) - #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX( RATIO ) \ - ( ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ) || \ - ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ) || \ - ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ) || \ - ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ) || \ - ( ( RATIO ) == ETH_DMAARBITRATION_RXPRIORTX ) ) - #define IS_ETH_DMATXDESC_GET_FLAG( FLAG ) \ - ( ( ( FLAG ) == ETH_DMATXDESC_OWN ) || \ - ( ( FLAG ) == ETH_DMATXDESC_IC ) || \ - ( ( FLAG ) == ETH_DMATXDESC_LS ) || \ - ( ( FLAG ) == ETH_DMATXDESC_FS ) || \ - ( ( FLAG ) == ETH_DMATXDESC_DC ) || \ - ( ( FLAG ) == ETH_DMATXDESC_DP ) || \ - ( ( FLAG ) == ETH_DMATXDESC_TTSE ) || \ - ( ( FLAG ) == ETH_DMATXDESC_TER ) || \ - ( ( FLAG ) == ETH_DMATXDESC_TCH ) || \ - ( ( FLAG ) == ETH_DMATXDESC_TTSS ) || \ - ( ( FLAG ) == ETH_DMATXDESC_IHE ) || \ - ( ( FLAG ) == ETH_DMATXDESC_ES ) || \ - ( ( FLAG ) == ETH_DMATXDESC_JT ) || \ - ( ( FLAG ) == ETH_DMATXDESC_FF ) || \ - ( ( FLAG ) == ETH_DMATXDESC_PCE ) || \ - ( ( FLAG ) == ETH_DMATXDESC_LCA ) || \ - ( ( FLAG ) == ETH_DMATXDESC_NC ) || \ - ( ( FLAG ) == ETH_DMATXDESC_LCO ) || \ - ( ( FLAG ) == ETH_DMATXDESC_EC ) || \ - ( ( FLAG ) == ETH_DMATXDESC_VF ) || \ - ( ( FLAG ) == ETH_DMATXDESC_CC ) || \ - ( ( FLAG ) == ETH_DMATXDESC_ED ) || \ - ( ( FLAG ) == ETH_DMATXDESC_UF ) || \ - ( ( FLAG ) == ETH_DMATXDESC_DB ) ) - #define IS_ETH_DMA_TXDESC_SEGMENT( SEGMENT ) \ - ( ( ( SEGMENT ) == ETH_DMATXDESC_LASTSEGMENTS ) || \ - ( ( SEGMENT ) == ETH_DMATXDESC_FIRSTSEGMENT ) ) - #define IS_ETH_DMA_TXDESC_CHECKSUM( CHECKSUM ) \ - ( ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMBYPASS ) || \ - ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMIPV4HEADER ) || \ - ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ) || \ - ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ) ) - #define IS_ETH_DMATXDESC_BUFFER_SIZE( SIZE ) ( ( SIZE ) <= 0x1FFF ) - #define IS_ETH_DMARXDESC_GET_FLAG( FLAG ) \ - ( ( ( FLAG ) == ETH_DMARXDESC_OWN ) || \ - ( ( FLAG ) == ETH_DMARXDESC_AFM ) || \ - ( ( FLAG ) == ETH_DMARXDESC_ES ) || \ - ( ( FLAG ) == ETH_DMARXDESC_DE ) || \ - ( ( FLAG ) == ETH_DMARXDESC_SAF ) || \ - ( ( FLAG ) == ETH_DMARXDESC_LE ) || \ - ( ( FLAG ) == ETH_DMARXDESC_OE ) || \ - ( ( FLAG ) == ETH_DMARXDESC_VLAN ) || \ - ( ( FLAG ) == ETH_DMARXDESC_FS ) || \ - ( ( FLAG ) == ETH_DMARXDESC_LS ) || \ - ( ( FLAG ) == ETH_DMARXDESC_IPV4HCE ) || \ - ( ( FLAG ) == ETH_DMARXDESC_LC ) || \ - ( ( FLAG ) == ETH_DMARXDESC_FT ) || \ - ( ( FLAG ) == ETH_DMARXDESC_RWT ) || \ - ( ( FLAG ) == ETH_DMARXDESC_RE ) || \ - ( ( FLAG ) == ETH_DMARXDESC_DBE ) || \ - ( ( FLAG ) == ETH_DMARXDESC_CE ) || \ - ( ( FLAG ) == ETH_DMARXDESC_MAMPCE ) ) - #define IS_ETH_DMA_RXDESC_BUFFER( BUFFER ) \ - ( ( ( BUFFER ) == ETH_DMARXDESC_BUFFER1 ) || \ - ( ( BUFFER ) == ETH_DMARXDESC_BUFFER2 ) ) - #define IS_ETH_PMT_GET_FLAG( FLAG ) \ - ( ( ( FLAG ) == ETH_PMT_FLAG_WUFR ) || \ - ( ( FLAG ) == ETH_PMT_FLAG_MPR ) ) - #define IS_ETH_DMA_FLAG( FLAG ) ( ( ( ( FLAG ) &( uint32_t ) 0xC7FE1800 ) == 0x00 ) && ( ( FLAG ) != 0x00 ) ) - #define IS_ETH_DMA_GET_FLAG( FLAG ) \ - ( ( ( FLAG ) == ETH_DMA_FLAG_TST ) || ( ( FLAG ) == ETH_DMA_FLAG_PMT ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_MMC ) || ( ( FLAG ) == ETH_DMA_FLAG_DATATRANSFERERROR ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_READWRITEERROR ) || ( ( FLAG ) == ETH_DMA_FLAG_ACCESSERROR ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_NIS ) || ( ( FLAG ) == ETH_DMA_FLAG_AIS ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_ER ) || ( ( FLAG ) == ETH_DMA_FLAG_FBE ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_ET ) || ( ( FLAG ) == ETH_DMA_FLAG_RWT ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_RPS ) || ( ( FLAG ) == ETH_DMA_FLAG_RBU ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_R ) || ( ( FLAG ) == ETH_DMA_FLAG_TU ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_RO ) || ( ( FLAG ) == ETH_DMA_FLAG_TJT ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_TBU ) || ( ( FLAG ) == ETH_DMA_FLAG_TPS ) || \ - ( ( FLAG ) == ETH_DMA_FLAG_T ) ) - #define IS_ETH_MAC_IT( IT ) ( ( ( ( IT ) &( uint32_t ) 0xFFFFFDF1 ) == 0x00 ) && ( ( IT ) != 0x00 ) ) - #define IS_ETH_MAC_GET_IT( IT ) \ - ( ( ( IT ) == ETH_MAC_IT_TST ) || ( ( IT ) == ETH_MAC_IT_MMCT ) || \ - ( ( IT ) == ETH_MAC_IT_MMCR ) || ( ( IT ) == ETH_MAC_IT_MMC ) || \ - ( ( IT ) == ETH_MAC_IT_PMT ) ) - #define IS_ETH_MAC_GET_FLAG( FLAG ) \ - ( ( ( FLAG ) == ETH_MAC_FLAG_TST ) || ( ( FLAG ) == ETH_MAC_FLAG_MMCT ) || \ - ( ( FLAG ) == ETH_MAC_FLAG_MMCR ) || ( ( FLAG ) == ETH_MAC_FLAG_MMC ) || \ - ( ( FLAG ) == ETH_MAC_FLAG_PMT ) ) - #define IS_ETH_DMA_IT( IT ) ( ( ( ( IT ) &( uint32_t ) 0xC7FE1800 ) == 0x00 ) && ( ( IT ) != 0x00 ) ) - #define IS_ETH_DMA_GET_IT( IT ) \ - ( ( ( IT ) == ETH_DMA_IT_TST ) || ( ( IT ) == ETH_DMA_IT_PMT ) || \ - ( ( IT ) == ETH_DMA_IT_MMC ) || ( ( IT ) == ETH_DMA_IT_NIS ) || \ - ( ( IT ) == ETH_DMA_IT_AIS ) || ( ( IT ) == ETH_DMA_IT_ER ) || \ - ( ( IT ) == ETH_DMA_IT_FBE ) || ( ( IT ) == ETH_DMA_IT_ET ) || \ - ( ( IT ) == ETH_DMA_IT_RWT ) || ( ( IT ) == ETH_DMA_IT_RPS ) || \ - ( ( IT ) == ETH_DMA_IT_RBU ) || ( ( IT ) == ETH_DMA_IT_R ) || \ - ( ( IT ) == ETH_DMA_IT_TU ) || ( ( IT ) == ETH_DMA_IT_RO ) || \ - ( ( IT ) == ETH_DMA_IT_TJT ) || ( ( IT ) == ETH_DMA_IT_TBU ) || \ - ( ( IT ) == ETH_DMA_IT_TPS ) || ( ( IT ) == ETH_DMA_IT_T ) ) - #define IS_ETH_DMA_GET_OVERFLOW( OVERFLOW ) \ - ( ( ( OVERFLOW ) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER ) || \ - ( ( OVERFLOW ) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ) ) - #define IS_ETH_MMC_IT( IT ) \ - ( ( ( ( ( IT ) &( uint32_t ) 0xFFDF3FFF ) == 0x00 ) || ( ( ( IT ) &( uint32_t ) 0xEFFDFF9F ) == 0x00 ) ) && \ - ( ( IT ) != 0x00 ) ) - #define IS_ETH_MMC_GET_IT( IT ) \ - ( ( ( IT ) == ETH_MMC_IT_TGF ) || ( ( IT ) == ETH_MMC_IT_TGFMSC ) || \ - ( ( IT ) == ETH_MMC_IT_TGFSC ) || ( ( IT ) == ETH_MMC_IT_RGUF ) || \ - ( ( IT ) == ETH_MMC_IT_RFAE ) || ( ( IT ) == ETH_MMC_IT_RFCE ) ) - #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT( CMD ) \ - ( ( ( CMD ) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE ) || \ - ( ( CMD ) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE ) ) - - -/** - * @} - */ - -/** @addtogroup ETH_Private_Defines - * @{ - */ -/* Delay to wait when writing to some Ethernet registers */ - #define ETH_REG_WRITE_DELAY ( ( uint32_t ) 0x00000001U ) - -/* Ethernet Errors */ - #define ETH_SUCCESS ( ( uint32_t ) 0U ) - #define ETH_ERROR ( ( uint32_t ) 1U ) - -/* Ethernet DMA Tx descriptors Collision Count Shift */ - #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ( ( uint32_t ) 3U ) - -/* Ethernet DMA Tx descriptors Buffer2 Size Shift */ - #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ( ( uint32_t ) 16U ) - -/* Ethernet DMA Rx descriptors Frame Length Shift */ - #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ( ( uint32_t ) 16U ) - -/* Ethernet DMA Rx descriptors Buffer2 Size Shift */ - #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ( ( uint32_t ) 16U ) - -/* Ethernet DMA Rx descriptors Frame length Shift */ - #define ETH_DMARXDESC_FRAMELENGTHSHIFT ( ( uint32_t ) 16U ) - -/* Ethernet MAC address offsets */ - #define ETH_MAC_ADDR_HBASE ( uint32_t ) ( ETH_MAC_BASE + ( uint32_t ) 0x40U ) /* Ethernet MAC address high offset */ - #define ETH_MAC_ADDR_LBASE ( uint32_t ) ( ETH_MAC_BASE + ( uint32_t ) 0x44U ) /* Ethernet MAC address low offset */ - -/* Ethernet MACMIIAR register Mask */ - #define ETH_MACMIIAR_CR_MASK ( ( uint32_t ) 0xFFFFFFE3U ) - -/* Ethernet MACCR register Mask */ - #define ETH_MACCR_CLEAR_MASK ( ( uint32_t ) 0xFF20810FU ) - -/* Ethernet MACFCR register Mask */ - #define ETH_MACFCR_CLEAR_MASK ( ( uint32_t ) 0x0000FF41U ) - -/* Ethernet DMAOMR register Mask */ - #define ETH_DMAOMR_CLEAR_MASK ( ( uint32_t ) 0xF8DE3F23U ) - -/* Ethernet Remote Wake-up frame register length */ - #define ETH_WAKEUP_REGISTER_LENGTH 8U - -/* Ethernet Missed frames counter Shift */ - #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U - -/** - * @} - */ - - #ifdef _lint - #ifdef __IO - #undef __IO - #endif - #define __IO - - #ifdef ETH_TypeDef - #undef ETH_TypeDef - #endif - #define ETH_TypeDef void - - #ifdef HAL_LockTypeDef - #undef HAL_LockTypeDef - #endif - #define HAL_LockTypeDef unsigned - - #ifdef ETH_RX_BUF_SIZE - #undef ETH_RX_BUF_SIZE - #endif - #define ETH_RX_BUF_SIZE 1536 - - #ifdef ETH_TX_BUF_SIZE - #undef ETH_TX_BUF_SIZE - #endif - #define ETH_TX_BUF_SIZE 1536 - #endif /* ifdef _lint */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Types ETH Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ - typedef enum - { - HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ - } HAL_ETH_StateTypeDef; - -/** - * @brief ETH Init Structure definition - */ - - typedef struct - { - uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY - * The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - * and the mode (half/full-duplex). - * This parameter can be a value of @ref ETH_AutoNegotiation */ - - uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. - * This parameter can be a value of @ref ETH_Speed */ - - uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - * This parameter can be a value of @ref ETH_Duplex_Mode */ - - uint16_t PhyAddress; /*!< Ethernet PHY address. - * This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint8_t * MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ - - uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. - * This parameter can be a value of @ref ETH_Rx_Mode */ - - uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. - * This parameter can be a value of @ref ETH_Checksum_Mode */ - - uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. - * This parameter can be a value of @ref ETH_Media_Interface */ - } ETH_InitTypeDef; - - -/** - * @brief ETH MAC Configuration Structure definition - */ - - typedef struct - { - uint32_t Watchdog; /*!< Selects or not the Watchdog timer - * When enabled, the MAC allows no more then 2048 bytes to be received. - * When disabled, the MAC can receive up to 16384 bytes. - * This parameter can be a value of @ref ETH_Watchdog */ - - uint32_t Jabber; /*!< Selects or not Jabber timer - * When enabled, the MAC allows no more then 2048 bytes to be sent. - * When disabled, the MAC can send up to 16384 bytes. - * This parameter can be a value of @ref ETH_Jabber */ - - uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. - * This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - - uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. - * This parameter can be a value of @ref ETH_Carrier_Sense */ - - uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, - * ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - * in Half-Duplex mode. - * This parameter can be a value of @ref ETH_Receive_Own */ - - uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. - * This parameter can be a value of @ref ETH_Loop_Back_Mode */ - - uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - * This parameter can be a value of @ref ETH_Checksum_Offload */ - - uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, - * when a collision occurs (Half-Duplex mode). - * This parameter can be a value of @ref ETH_Retry_Transmission */ - - uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. - * This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - - uint32_t BackOffLimit; /*!< Selects the BackOff limit value. - * This parameter can be a value of @ref ETH_Back_Off_Limit */ - - uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). - * This parameter can be a value of @ref ETH_Deferral_Check */ - - uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). - * This parameter can be a value of @ref ETH_Receive_All */ - - uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. - * This parameter can be a value of @ref ETH_Source_Addr_Filter */ - - uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - * This parameter can be a value of @ref ETH_Pass_Control_Frames */ - - uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. - * This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - - uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. - * This parameter can be a value of @ref ETH_Destination_Addr_Filter */ - - uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode - * This parameter can be a value of @ref ETH_Promiscuous_Mode */ - - uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. - * This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - - uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. - * This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - - uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. - * This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. - * This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. - * This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ - - uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. - * This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ - - uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for - * automatic retransmission of PAUSE Frame. - * This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - - uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 - * unicast address and unique multicast address). - * This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and - * disable its transmitter for a specified time (Pause Time) - * This parameter can be a value of @ref ETH_Receive_Flow_Control */ - - uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - * or the MAC back-pressure operation (Half-Duplex mode) - * This parameter can be a value of @ref ETH_Transmit_Flow_Control */ - - uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - * comparison and filtering. - * This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ - - uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ - } ETH_MACInitTypeDef; - - -/** - * @brief ETH DMA Configuration Structure definition - */ - - typedef struct - { - uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. - * This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. - * This parameter can be a value of @ref ETH_Receive_Store_Forward */ - - uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. - * This parameter can be a value of @ref ETH_Flush_Received_Frame */ - - uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. - * This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - - uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. - * This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - - uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. - * This parameter can be a value of @ref ETH_Forward_Error_Frames */ - - uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - * and length less than 64 bytes) including pad-bytes and CRC) - * This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. - * This parameter can be a value of @ref ETH_Receive_Threshold_Control */ - - uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second - * frame of Transmit data even before obtaining the status for the first frame. - * This parameter can be a value of @ref ETH_Second_Frame_Operate */ - - uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. - * This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - - uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. - * This parameter can be a value of @ref ETH_Fixed_Burst */ - - uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. - * This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. - * This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. - * This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ - - uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) - * This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. - * This parameter can be a value of @ref ETH_DMA_Arbitration */ - } ETH_DMAInitTypeDef; - - -/** - * @brief ETH DMA Descriptors data structure definition - */ - - typedef struct - { - __IO uint32_t Status; /*!< Status */ - - uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ - - uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ - - uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ - - /*!< Enhanced Ethernet DMA PTP Descriptors */ - uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ - - uint32_t Reserved1; /*!< Reserved */ - - uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ - - uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ - } ETH_DMADescTypeDef; - - -/** - * @brief Received Frame Informations structure definition - */ - typedef struct - { - ETH_DMADescTypeDef * FSRxDesc; /*!< First Segment Rx Desc */ - - ETH_DMADescTypeDef * LSRxDesc; /*!< Last Segment Rx Desc */ - - uint32_t SegCount; /*!< Segment count */ - - uint32_t length; /*!< Frame length */ - - uint32_t buffer; /*!< Frame buffer */ - } ETH_DMARxFrameInfos; - - -/** - * @brief ETH Handle Structure definition - */ - - typedef struct - { - ETH_TypeDef * Instance; /*!< Register base address */ - - ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ - - uint32_t LinkStatus; /*!< Ethernet link status */ - - ETH_DMADescTypeDef * RxDesc; /*!< Rx descriptor to Get */ - - ETH_DMADescTypeDef * TxDesc; /*!< Tx descriptor to Set */ - - ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ - - __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ - - HAL_LockTypeDef Lock; /*!< ETH Lock */ - } ETH_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Constants ETH Exported Constants - * @{ - */ - -/** @defgroup ETH_Buffers_setting ETH Buffers setting - * @{ - */ - #define ETH_MAX_PACKET_SIZE ( ( uint32_t ) 1536U ) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ - #define ETH_HEADER ( ( uint32_t ) 14U ) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ - #define ETH_CRC ( ( uint32_t ) 4U ) /*!< Ethernet CRC */ - #define ETH_EXTRA ( ( uint32_t ) 2U ) /*!< Extra bytes in some cases */ - #define ETH_VLAN_TAG ( ( uint32_t ) 4U ) /*!< optional 802.1q VLAN Tag */ - #define ETH_MIN_ETH_PAYLOAD ( ( uint32_t ) 46U ) /*!< Minimum Ethernet payload size */ - #define ETH_MAX_ETH_PAYLOAD ( ( uint32_t ) 1500U ) /*!< Maximum Ethernet payload size */ - #define ETH_JUMBO_FRAME_PAYLOAD ( ( uint32_t ) 9000U ) /*!< Jumbo frame payload size */ - -/* Ethernet driver receive buffers are organized in a chained linked-list, when - * an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO - * to the driver receive buffers memory. - * - * Depending on the size of the received Ethernet packet and the size of - * each Ethernet driver receive buffer, the received packet can take one or more - * Ethernet driver receive buffer. - * - * In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE - * and the total count of the driver receive buffers ETH_RXBUFNB. - * - * The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as - * example, they can be reconfigured in the application layer to fit the application - * needs */ - -/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet - * packet */ - #ifndef ETH_RX_BUF_SIZE - #error please define ETH_RX_BUF_SIZE - #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE - #endif - -/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ - #ifndef ETH_RXBUFNB - #define ETH_RXBUFNB ( ( uint32_t ) 5U ) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ - #endif - - -/* Ethernet driver transmit buffers are organized in a chained linked-list, when - * an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the - * driver transmit buffers memory to the TxFIFO. - * - * Depending on the size of the Ethernet packet to be transmitted and the size of - * each Ethernet driver transmit buffer, the packet to be transmitted can take - * one or more Ethernet driver transmit buffer. - * - * In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE - * and the total count of the driver transmit buffers ETH_TXBUFNB. - * - * The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as - * example, they can be reconfigured in the application layer to fit the application - * needs */ - -/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet - * packet */ - #ifndef ETH_TX_BUF_SIZE - #error please define ETH_TX_BUF_SIZE - #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE - #endif - -/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ - #ifndef ETH_TXBUFNB - #define ETH_TXBUFNB ( ( uint32_t ) 5U ) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ - #endif - -/** - * @} - */ - -/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor - * @{ - */ - -/* - * DMA Tx Descriptor - * ----------------------------------------------------------------------------------------------- - * TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - * ----------------------------------------------------------------------------------------------- - * TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - * ----------------------------------------------------------------------------------------------- - * TDES2 | Buffer1 Address [31:0] | - * ----------------------------------------------------------------------------------------------- - * TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - * ----------------------------------------------------------------------------------------------- - */ - -/** - * @brief Bit definition of TDES0 register: DMA Tx descriptor status register - */ - #define ETH_DMATXDESC_OWN ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine */ - #define ETH_DMATXDESC_IC ( ( uint32_t ) 0x40000000U ) /*!< Interrupt on Completion */ - #define ETH_DMATXDESC_LS ( ( uint32_t ) 0x20000000U ) /*!< Last Segment */ - #define ETH_DMATXDESC_FS ( ( uint32_t ) 0x10000000U ) /*!< First Segment */ - #define ETH_DMATXDESC_DC ( ( uint32_t ) 0x08000000U ) /*!< Disable CRC */ - #define ETH_DMATXDESC_DP ( ( uint32_t ) 0x04000000U ) /*!< Disable Padding */ - #define ETH_DMATXDESC_TTSE ( ( uint32_t ) 0x02000000U ) /*!< Transmit Time Stamp Enable */ - #define ETH_DMATXDESC_CIC ( ( uint32_t ) 0x00C00000U ) /*!< Checksum Insertion Control: 4 cases */ - #define ETH_DMATXDESC_CIC_BYPASS ( ( uint32_t ) 0x00000000U ) /*!< Do Nothing: Checksum Engine is bypassed */ - #define ETH_DMATXDESC_CIC_IPV4HEADER ( ( uint32_t ) 0x00400000U ) /*!< IPV4 header Checksum Insertion */ - #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ( ( uint32_t ) 0x00800000U ) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ - #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ( ( uint32_t ) 0x00C00000U ) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ - #define ETH_DMATXDESC_TER ( ( uint32_t ) 0x00200000U ) /*!< Transmit End of Ring */ - #define ETH_DMATXDESC_TCH ( ( uint32_t ) 0x00100000U ) /*!< Second Address Chained */ - #define ETH_DMATXDESC_TTSS ( ( uint32_t ) 0x00020000U ) /*!< Tx Time Stamp Status */ - #define ETH_DMATXDESC_IHE ( ( uint32_t ) 0x00010000U ) /*!< IP Header Error */ - #define ETH_DMATXDESC_ES ( ( uint32_t ) 0x00008000U ) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ - #define ETH_DMATXDESC_JT ( ( uint32_t ) 0x00004000U ) /*!< Jabber Timeout */ - #define ETH_DMATXDESC_FF ( ( uint32_t ) 0x00002000U ) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ - #define ETH_DMATXDESC_PCE ( ( uint32_t ) 0x00001000U ) /*!< Payload Checksum Error */ - #define ETH_DMATXDESC_LCA ( ( uint32_t ) 0x00000800U ) /*!< Loss of Carrier: carrier lost during transmission */ - #define ETH_DMATXDESC_NC ( ( uint32_t ) 0x00000400U ) /*!< No Carrier: no carrier signal from the transceiver */ - #define ETH_DMATXDESC_LCO ( ( uint32_t ) 0x00000200U ) /*!< Late Collision: transmission aborted due to collision */ - #define ETH_DMATXDESC_EC ( ( uint32_t ) 0x00000100U ) /*!< Excessive Collision: transmission aborted after 16 collisions */ - #define ETH_DMATXDESC_VF ( ( uint32_t ) 0x00000080U ) /*!< VLAN Frame */ - #define ETH_DMATXDESC_CC ( ( uint32_t ) 0x00000078U ) /*!< Collision Count */ - #define ETH_DMATXDESC_ED ( ( uint32_t ) 0x00000004U ) /*!< Excessive Deferral */ - #define ETH_DMATXDESC_UF ( ( uint32_t ) 0x00000002U ) /*!< Underflow Error: late data arrival from the memory */ - #define ETH_DMATXDESC_DB ( ( uint32_t ) 0x00000001U ) /*!< Deferred Bit */ - -/** - * @brief Bit definition of TDES1 register - */ - #define ETH_DMATXDESC_TBS2 ( ( uint32_t ) 0x1FFF0000U ) /*!< Transmit Buffer2 Size */ - #define ETH_DMATXDESC_TBS1 ( ( uint32_t ) 0x00001FFFU ) /*!< Transmit Buffer1 Size */ - -/** - * @brief Bit definition of TDES2 register - */ - #define ETH_DMATXDESC_B1AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of TDES3 register - */ - #define ETH_DMATXDESC_B2AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer2 Address Pointer */ - -/*--------------------------------------------------------------------------------------------- - * TDES6 | Transmit Time Stamp Low [31:0] | - * ----------------------------------------------------------------------------------------------- - * TDES7 | Transmit Time Stamp High [31:0] | - * ----------------------------------------------------------------------------------------------*/ - -/* Bit definition of TDES6 register */ - #define ETH_DMAPTPTXDESC_TTSL ( ( uint32_t ) 0xFFFFFFFFU ) /* Transmit Time Stamp Low */ - -/* Bit definition of TDES7 register */ - #define ETH_DMAPTPTXDESC_TTSH ( ( uint32_t ) 0xFFFFFFFFU ) /* Transmit Time Stamp High */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor - * @{ - */ - -/* - * DMA Rx Descriptor - * -------------------------------------------------------------------------------------------------------------------- - * RDES0 | OWN(31) | Status [30:0] | - * --------------------------------------------------------------------------------------------------------------------- - * RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - * --------------------------------------------------------------------------------------------------------------------- - * RDES2 | Buffer1 Address [31:0] | - * --------------------------------------------------------------------------------------------------------------------- - * RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - * --------------------------------------------------------------------------------------------------------------------- - */ - -/** - * @brief Bit definition of RDES0 register: DMA Rx descriptor status register - */ - #define ETH_DMARXDESC_OWN ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine */ - #define ETH_DMARXDESC_AFM ( ( uint32_t ) 0x40000000U ) /*!< DA Filter Fail for the rx frame */ - #define ETH_DMARXDESC_FL ( ( uint32_t ) 0x3FFF0000U ) /*!< Receive descriptor frame length */ - #define ETH_DMARXDESC_ES ( ( uint32_t ) 0x00008000U ) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ - #define ETH_DMARXDESC_DE ( ( uint32_t ) 0x00004000U ) /*!< Descriptor error: no more descriptors for receive frame */ - #define ETH_DMARXDESC_SAF ( ( uint32_t ) 0x00002000U ) /*!< SA Filter Fail for the received frame */ - #define ETH_DMARXDESC_LE ( ( uint32_t ) 0x00001000U ) /*!< Frame size not matching with length field */ - #define ETH_DMARXDESC_OE ( ( uint32_t ) 0x00000800U ) /*!< Overflow Error: Frame was damaged due to buffer overflow */ - #define ETH_DMARXDESC_VLAN ( ( uint32_t ) 0x00000400U ) /*!< VLAN Tag: received frame is a VLAN frame */ - #define ETH_DMARXDESC_FS ( ( uint32_t ) 0x00000200U ) /*!< First descriptor of the frame */ - #define ETH_DMARXDESC_LS ( ( uint32_t ) 0x00000100U ) /*!< Last descriptor of the frame */ - #define ETH_DMARXDESC_IPV4HCE ( ( uint32_t ) 0x00000080U ) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ - #define ETH_DMARXDESC_LC ( ( uint32_t ) 0x00000040U ) /*!< Late collision occurred during reception */ - #define ETH_DMARXDESC_FT ( ( uint32_t ) 0x00000020U ) /*!< Frame type - Ethernet, otherwise 802.3 */ - #define ETH_DMARXDESC_RWT ( ( uint32_t ) 0x00000010U ) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ - #define ETH_DMARXDESC_RE ( ( uint32_t ) 0x00000008U ) /*!< Receive error: error reported by MII interface */ - #define ETH_DMARXDESC_DBE ( ( uint32_t ) 0x00000004U ) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ - #define ETH_DMARXDESC_CE ( ( uint32_t ) 0x00000002U ) /*!< CRC error */ - #define ETH_DMARXDESC_MAMPCE ( ( uint32_t ) 0x00000001U ) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -/** - * @brief Bit definition of RDES1 register - */ - #define ETH_DMARXDESC_DIC ( ( uint32_t ) 0x80000000U ) /*!< Disable Interrupt on Completion */ - #define ETH_DMARXDESC_RBS2 ( ( uint32_t ) 0x1FFF0000U ) /*!< Receive Buffer2 Size */ - #define ETH_DMARXDESC_RER ( ( uint32_t ) 0x00008000U ) /*!< Receive End of Ring */ - #define ETH_DMARXDESC_RCH ( ( uint32_t ) 0x00004000U ) /*!< Second Address Chained */ - #define ETH_DMARXDESC_RBS1 ( ( uint32_t ) 0x00001FFFU ) /*!< Receive Buffer1 Size */ - -/** - * @brief Bit definition of RDES2 register - */ - #define ETH_DMARXDESC_B1AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of RDES3 register - */ - #define ETH_DMARXDESC_B2AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer2 Address Pointer */ - -/*--------------------------------------------------------------------------------------------------------------------- - * RDES4 | Reserved[31:15] | Extended Status [14:0] | - * --------------------------------------------------------------------------------------------------------------------- - * RDES5 | Reserved[31:0] | - * --------------------------------------------------------------------------------------------------------------------- - * RDES6 | Receive Time Stamp Low [31:0] | - * --------------------------------------------------------------------------------------------------------------------- - * RDES7 | Receive Time Stamp High [31:0] | - * --------------------------------------------------------------------------------------------------------------------*/ - -/* Bit definition of RDES4 register */ - #define ETH_DMAPTPRXDESC_PTPV ( ( uint32_t ) 0x00002000U ) /* PTP Version */ - #define ETH_DMAPTPRXDESC_PTPFT ( ( uint32_t ) 0x00001000U ) /* PTP Frame Type */ - #define ETH_DMAPTPRXDESC_PTPMT ( ( uint32_t ) 0x00000F00U ) /* PTP Message Type */ - #define ETH_DMAPTPRXDESC_PTPMT_SYNC ( ( uint32_t ) 0x00000100U ) /* SYNC message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ( ( uint32_t ) 0x00000200U ) /* FollowUp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ( ( uint32_t ) 0x00000300U ) /* DelayReq message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ( ( uint32_t ) 0x00000400U ) /* DelayResp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ( ( uint32_t ) 0x00000500U ) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ( ( uint32_t ) 0x00000600U ) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ( ( uint32_t ) 0x00000700U ) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_IPV6PR ( ( uint32_t ) 0x00000080U ) /* IPv6 Packet Received */ - #define ETH_DMAPTPRXDESC_IPV4PR ( ( uint32_t ) 0x00000040U ) /* IPv4 Packet Received */ - #define ETH_DMAPTPRXDESC_IPCB ( ( uint32_t ) 0x00000020U ) /* IP Checksum Bypassed */ - #define ETH_DMAPTPRXDESC_IPPE ( ( uint32_t ) 0x00000010U ) /* IP Payload Error */ - #define ETH_DMAPTPRXDESC_IPHE ( ( uint32_t ) 0x00000008U ) /* IP Header Error */ - #define ETH_DMAPTPRXDESC_IPPT ( ( uint32_t ) 0x00000007U ) /* IP Payload Type */ - #define ETH_DMAPTPRXDESC_IPPT_UDP ( ( uint32_t ) 0x00000001U ) /* UDP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_TCP ( ( uint32_t ) 0x00000002U ) /* TCP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_ICMP ( ( uint32_t ) 0x00000003U ) /* ICMP payload encapsulated in the IP datagram */ - -/* Bit definition of RDES6 register */ - #define ETH_DMAPTPRXDESC_RTSL ( ( uint32_t ) 0xFFFFFFFFU ) /* Receive Time Stamp Low */ - -/* Bit definition of RDES7 register */ - #define ETH_DMAPTPRXDESC_RTSH ( ( uint32_t ) 0xFFFFFFFFU ) /* Receive Time Stamp High */ - -/** - * @} - */ - -/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation - * @{ - */ - #define ETH_AUTONEGOTIATION_ENABLE ( ( uint32_t ) 0x00000001U ) - #define ETH_AUTONEGOTIATION_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Speed ETH Speed - * @{ - */ - #define ETH_SPEED_10M ( ( uint32_t ) 0x00000000U ) - #define ETH_SPEED_100M ( ( uint32_t ) 0x00004000U ) - -/** - * @} - */ - -/** @defgroup ETH_Duplex_Mode ETH Duplex Mode - * @{ - */ - #define ETH_MODE_FULLDUPLEX ( ( uint32_t ) 0x00000800U ) - #define ETH_MODE_HALFDUPLEX ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Rx_Mode ETH Rx Mode - * @{ - */ - #define ETH_RXPOLLING_MODE ( ( uint32_t ) 0x00000000U ) - #define ETH_RXINTERRUPT_MODE ( ( uint32_t ) 0x00000001U ) - -/** - * @} - */ - -/** @defgroup ETH_Checksum_Mode ETH Checksum Mode - * @{ - */ - #define ETH_CHECKSUM_BY_HARDWARE ( ( uint32_t ) 0x00000000U ) - #define ETH_CHECKSUM_BY_SOFTWARE ( ( uint32_t ) 0x00000001U ) - -/** - * @} - */ - -/** @defgroup ETH_Media_Interface ETH Media Interface - * @{ - */ - #define ETH_MEDIA_INTERFACE_MII ( ( uint32_t ) 0x00000000U ) - #define ETH_MEDIA_INTERFACE_RMII ( ( uint32_t ) SYSCFG_PMC_MII_RMII_SEL ) - -/** - * @} - */ - -/** @defgroup ETH_Watchdog ETH Watchdog - * @{ - */ - #define ETH_WATCHDOG_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_WATCHDOG_DISABLE ( ( uint32_t ) 0x00800000U ) - -/** - * @} - */ - -/** @defgroup ETH_Jabber ETH Jabber - * @{ - */ - #define ETH_JABBER_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_JABBER_DISABLE ( ( uint32_t ) 0x00400000U ) - -/** - * @} - */ - -/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap - * @{ - */ - #define ETH_INTERFRAMEGAP_96BIT ( ( uint32_t ) 0x00000000U ) /*!< minimum IFG between frames during transmission is 96Bit */ - #define ETH_INTERFRAMEGAP_88BIT ( ( uint32_t ) 0x00020000U ) /*!< minimum IFG between frames during transmission is 88Bit */ - #define ETH_INTERFRAMEGAP_80BIT ( ( uint32_t ) 0x00040000U ) /*!< minimum IFG between frames during transmission is 80Bit */ - #define ETH_INTERFRAMEGAP_72BIT ( ( uint32_t ) 0x00060000U ) /*!< minimum IFG between frames during transmission is 72Bit */ - #define ETH_INTERFRAMEGAP_64BIT ( ( uint32_t ) 0x00080000U ) /*!< minimum IFG between frames during transmission is 64Bit */ - #define ETH_INTERFRAMEGAP_56BIT ( ( uint32_t ) 0x000A0000U ) /*!< minimum IFG between frames during transmission is 56Bit */ - #define ETH_INTERFRAMEGAP_48BIT ( ( uint32_t ) 0x000C0000U ) /*!< minimum IFG between frames during transmission is 48Bit */ - #define ETH_INTERFRAMEGAP_40BIT ( ( uint32_t ) 0x000E0000U ) /*!< minimum IFG between frames during transmission is 40Bit */ - -/** - * @} - */ - -/** @defgroup ETH_Carrier_Sense ETH Carrier Sense - * @{ - */ - #define ETH_CARRIERSENCE_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_CARRIERSENCE_DISABLE ( ( uint32_t ) 0x00010000U ) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Own ETH Receive Own - * @{ - */ - #define ETH_RECEIVEOWN_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_RECEIVEOWN_DISABLE ( ( uint32_t ) 0x00002000U ) - -/** - * @} - */ - -/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode - * @{ - */ - #define ETH_LOOPBACKMODE_ENABLE ( ( uint32_t ) 0x00001000U ) - #define ETH_LOOPBACKMODE_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Checksum_Offload ETH Checksum Offload - * @{ - */ - #define ETH_CHECKSUMOFFLAOD_ENABLE ( ( uint32_t ) 0x00000400U ) - #define ETH_CHECKSUMOFFLAOD_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Retry_Transmission ETH Retry Transmission - * @{ - */ - #define ETH_RETRYTRANSMISSION_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_RETRYTRANSMISSION_DISABLE ( ( uint32_t ) 0x00000200U ) - -/** - * @} - */ - -/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip - * @{ - */ - #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ( ( uint32_t ) 0x00000080U ) - #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit - * @{ - */ - #define ETH_BACKOFFLIMIT_10 ( ( uint32_t ) 0x00000000U ) - #define ETH_BACKOFFLIMIT_8 ( ( uint32_t ) 0x00000020U ) - #define ETH_BACKOFFLIMIT_4 ( ( uint32_t ) 0x00000040U ) - #define ETH_BACKOFFLIMIT_1 ( ( uint32_t ) 0x00000060U ) - -/** - * @} - */ - -/** @defgroup ETH_Deferral_Check ETH Deferral Check - * @{ - */ - #define ETH_DEFFERRALCHECK_ENABLE ( ( uint32_t ) 0x00000010U ) - #define ETH_DEFFERRALCHECK_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Receive_All ETH Receive All - * @{ - */ - #define ETH_RECEIVEALL_ENABLE ( ( uint32_t ) 0x80000000U ) - #define ETH_RECEIVEAll_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter - * @{ - */ - #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ( ( uint32_t ) 0x00000200U ) - #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ( ( uint32_t ) 0x00000300U ) - #define ETH_SOURCEADDRFILTER_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames - * @{ - */ - #define ETH_PASSCONTROLFRAMES_BLOCKALL ( ( uint32_t ) 0x00000040U ) /*!< MAC filters all control frames from reaching the application */ - #define ETH_PASSCONTROLFRAMES_FORWARDALL ( ( uint32_t ) 0x00000080U ) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ( ( uint32_t ) 0x000000C0U ) /*!< MAC forwards control frames that pass the Address Filter. */ - -/** - * @} - */ - -/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception - * @{ - */ - #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ( ( uint32_t ) 0x00000020U ) - -/** - * @} - */ - -/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter - * @{ - */ - #define ETH_DESTINATIONADDRFILTER_NORMAL ( ( uint32_t ) 0x00000000U ) - #define ETH_DESTINATIONADDRFILTER_INVERSE ( ( uint32_t ) 0x00000008U ) - -/** - * @} - */ - -/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode - * @{ - */ - #define ETH_PROMISCUOUS_MODE_ENABLE ( ( uint32_t ) 0x00000001U ) - #define ETH_PROMISCUOUS_MODE_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter - * @{ - */ - #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ( ( uint32_t ) 0x00000404U ) - #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ( ( uint32_t ) 0x00000004U ) - #define ETH_MULTICASTFRAMESFILTER_PERFECT ( ( uint32_t ) 0x00000000U ) - #define ETH_MULTICASTFRAMESFILTER_NONE ( ( uint32_t ) 0x00000010U ) - -/** - * @} - */ - -/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter - * @{ - */ - #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ( ( uint32_t ) 0x00000402U ) - #define ETH_UNICASTFRAMESFILTER_HASHTABLE ( ( uint32_t ) 0x00000002U ) - #define ETH_UNICASTFRAMESFILTER_PERFECT ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause - * @{ - */ - #define ETH_ZEROQUANTAPAUSE_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_ZEROQUANTAPAUSE_DISABLE ( ( uint32_t ) 0x00000080U ) - -/** - * @} - */ - -/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold - * @{ - */ - #define ETH_PAUSELOWTHRESHOLD_MINUS4 ( ( uint32_t ) 0x00000000U ) /*!< Pause time minus 4 slot times */ - #define ETH_PAUSELOWTHRESHOLD_MINUS28 ( ( uint32_t ) 0x00000010U ) /*!< Pause time minus 28 slot times */ - #define ETH_PAUSELOWTHRESHOLD_MINUS144 ( ( uint32_t ) 0x00000020U ) /*!< Pause time minus 144 slot times */ - #define ETH_PAUSELOWTHRESHOLD_MINUS256 ( ( uint32_t ) 0x00000030U ) /*!< Pause time minus 256 slot times */ - -/** - * @} - */ - -/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect - * @{ - */ - #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ( ( uint32_t ) 0x00000008U ) - #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control - * @{ - */ - #define ETH_RECEIVEFLOWCONTROL_ENABLE ( ( uint32_t ) 0x00000004U ) - #define ETH_RECEIVEFLOWCONTROL_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control - * @{ - */ - #define ETH_TRANSMITFLOWCONTROL_ENABLE ( ( uint32_t ) 0x00000002U ) - #define ETH_TRANSMITFLOWCONTROL_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison - * @{ - */ - #define ETH_VLANTAGCOMPARISON_12BIT ( ( uint32_t ) 0x00010000U ) - #define ETH_VLANTAGCOMPARISON_16BIT ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses ETH MAC addresses - * @{ - */ - #define ETH_MAC_ADDRESS0 ( ( uint32_t ) 0x00000000U ) - #define ETH_MAC_ADDRESS1 ( ( uint32_t ) 0x00000008U ) - #define ETH_MAC_ADDRESS2 ( ( uint32_t ) 0x00000010U ) - #define ETH_MAC_ADDRESS3 ( ( uint32_t ) 0x00000018U ) - -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA - * @{ - */ - #define ETH_MAC_ADDRESSFILTER_SA ( ( uint32_t ) 0x00000000U ) - #define ETH_MAC_ADDRESSFILTER_DA ( ( uint32_t ) 0x00000008U ) - -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes - * @{ - */ - #define ETH_MAC_ADDRESSMASK_BYTE6 ( ( uint32_t ) 0x20000000U ) /*!< Mask MAC Address high reg bits [15:8] */ - #define ETH_MAC_ADDRESSMASK_BYTE5 ( ( uint32_t ) 0x10000000U ) /*!< Mask MAC Address high reg bits [7:0] */ - #define ETH_MAC_ADDRESSMASK_BYTE4 ( ( uint32_t ) 0x08000000U ) /*!< Mask MAC Address low reg bits [31:24] */ - #define ETH_MAC_ADDRESSMASK_BYTE3 ( ( uint32_t ) 0x04000000U ) /*!< Mask MAC Address low reg bits [23:16] */ - #define ETH_MAC_ADDRESSMASK_BYTE2 ( ( uint32_t ) 0x02000000U ) /*!< Mask MAC Address low reg bits [15:8] */ - #define ETH_MAC_ADDRESSMASK_BYTE1 ( ( uint32_t ) 0x01000000U ) /*!< Mask MAC Address low reg bits [70] */ - -/** - * @} - */ - -/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags - * @{ - */ - #ifndef ETH_MAC_TXFIFO_FULL - #define ETH_MAC_TXFIFO_FULL ( ( uint32_t ) 0x02000000 ) /* Tx FIFO full */ - #define ETH_MAC_TXFIFONOT_EMPTY ( ( uint32_t ) 0x01000000 ) /* Tx FIFO not empty */ - #define ETH_MAC_TXFIFO_WRITE_ACTIVE ( ( uint32_t ) 0x00400000 ) /* Tx FIFO write active */ - #define ETH_MAC_TXFIFO_IDLE ( ( uint32_t ) 0x00000000 ) /* Tx FIFO read status: Idle */ - #define ETH_MAC_TXFIFO_READ ( ( uint32_t ) 0x00100000 ) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ - #define ETH_MAC_TXFIFO_WAITING ( ( uint32_t ) 0x00200000 ) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ - #define ETH_MAC_TXFIFO_WRITING ( ( uint32_t ) 0x00300000 ) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ - #define ETH_MAC_TRANSMISSION_PAUSE ( ( uint32_t ) 0x00080000 ) /* MAC transmitter in pause */ - #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ( ( uint32_t ) 0x00000000 ) /* MAC transmit frame controller: Idle */ - #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ( ( uint32_t ) 0x00020000 ) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ - #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ( ( uint32_t ) 0x00040000 ) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ - #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ( ( uint32_t ) 0x00060000 ) /* MAC transmit frame controller: Transferring input frame for transmission */ - #define ETH_MAC_MII_TRANSMIT_ACTIVE ( ( uint32_t ) 0x00010000 ) /* MAC MII transmit engine active */ - #define ETH_MAC_RXFIFO_EMPTY ( ( uint32_t ) 0x00000000 ) /* Rx FIFO fill level: empty */ - #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ( ( uint32_t ) 0x00000100 ) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ - #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ( ( uint32_t ) 0x00000200 ) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ - #define ETH_MAC_RXFIFO_FULL ( ( uint32_t ) 0x00000300 ) /* Rx FIFO fill level: full */ - #define ETH_MAC_READCONTROLLER_IDLE ( ( uint32_t ) 0x00000060 ) /* Rx FIFO read controller IDLE state */ - #define ETH_MAC_READCONTROLLER_READING_DATA ( ( uint32_t ) 0x00000060 ) /* Rx FIFO read controller Reading frame data */ - #define ETH_MAC_READCONTROLLER_READING_STATUS ( ( uint32_t ) 0x00000060 ) /* Rx FIFO read controller Reading frame status (or time-stamp) */ - #define ETH_MAC_READCONTROLLER_ FLUSHING( ( uint32_t ) 0x00000060 ) /* Rx FIFO read controller Flushing the frame data and status */ - #define ETH_MAC_RXFIFO_WRITE_ACTIVE ( ( uint32_t ) 0x00000010 ) /* Rx FIFO write controller active */ - #define ETH_MAC_SMALL_FIFO_NOTACTIVE ( ( uint32_t ) 0x00000000 ) /* MAC small FIFO read / write controllers not active */ - #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ( ( uint32_t ) 0x00000002 ) /* MAC small FIFO read controller active */ - #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ( ( uint32_t ) 0x00000004 ) /* MAC small FIFO write controller active */ - #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ( ( uint32_t ) 0x00000006 ) /* MAC small FIFO read / write controllers active */ - #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ( ( uint32_t ) 0x00000001 ) /* MAC MII receive protocol engine active */ - #else /* ifndef ETH_MAC_TXFIFO_FULL */ - /* stm32_hal_legacy.h has probably been included. That file defines 'ETH_MAC_TXFIFO_FULL' and all macro's here below. */ - #endif /* ifndef ETH_MAC_TXFIFO_FULL */ - -/** - * @} - */ - -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame - * @{ - */ - #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ( ( uint32_t ) 0x04000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward - * @{ - */ - #define ETH_RECEIVESTOREFORWARD_ENABLE ( ( uint32_t ) 0x02000000U ) - #define ETH_RECEIVESTOREFORWARD_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame - * @{ - */ - #define ETH_FLUSHRECEIVEDFRAME_ENABLE ( ( uint32_t ) 0x00000000U ) - #define ETH_FLUSHRECEIVEDFRAME_DISABLE ( ( uint32_t ) 0x01000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward - * @{ - */ - #define ETH_TRANSMITSTOREFORWARD_ENABLE ( ( uint32_t ) 0x00200000U ) - #define ETH_TRANSMITSTOREFORWARD_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control - * @{ - */ - #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ( ( uint32_t ) 0x00000000U ) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ( ( uint32_t ) 0x00004000U ) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ( ( uint32_t ) 0x00008000U ) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ( ( uint32_t ) 0x0000C000U ) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ( ( uint32_t ) 0x00010000U ) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ( ( uint32_t ) 0x00014000U ) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ( ( uint32_t ) 0x00018000U ) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ( ( uint32_t ) 0x0001C000U ) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ - -/** - * @} - */ - -/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames - * @{ - */ - #define ETH_FORWARDERRORFRAMES_ENABLE ( ( uint32_t ) 0x00000080U ) - #define ETH_FORWARDERRORFRAMES_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames - * @{ - */ - #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ( ( uint32_t ) 0x00000040U ) - #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control - * @{ - */ - #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ( ( uint32_t ) 0x00000000U ) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ( ( uint32_t ) 0x00000008U ) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ( ( uint32_t ) 0x00000010U ) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ( ( uint32_t ) 0x00000018U ) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ - -/** - * @} - */ - -/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate - * @{ - */ - #define ETH_SECONDFRAMEOPERARTE_ENABLE ( ( uint32_t ) 0x00000004U ) - #define ETH_SECONDFRAMEOPERARTE_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats - * @{ - */ - #define ETH_ADDRESSALIGNEDBEATS_ENABLE ( ( uint32_t ) 0x02000000U ) - #define ETH_ADDRESSALIGNEDBEATS_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Fixed_Burst ETH Fixed Burst - * @{ - */ - #define ETH_FIXEDBURST_ENABLE ( ( uint32_t ) 0x00010000U ) - #define ETH_FIXEDBURST_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length - * @{ - */ - #define ETH_RXDMABURSTLENGTH_1BEAT ( ( uint32_t ) 0x00020000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_RXDMABURSTLENGTH_2BEAT ( ( uint32_t ) 0x00040000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_RXDMABURSTLENGTH_4BEAT ( ( uint32_t ) 0x00080000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_RXDMABURSTLENGTH_8BEAT ( ( uint32_t ) 0x00100000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_RXDMABURSTLENGTH_16BEAT ( ( uint32_t ) 0x00200000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_RXDMABURSTLENGTH_32BEAT ( ( uint32_t ) 0x00400000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ( ( uint32_t ) 0x01020000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ( ( uint32_t ) 0x01040000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ( ( uint32_t ) 0x01080000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ( ( uint32_t ) 0x01100000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ( ( uint32_t ) 0x01200000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ( ( uint32_t ) 0x01400000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ - -/** - * @} - */ - -/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length - * @{ - */ - #define ETH_TXDMABURSTLENGTH_1BEAT ( ( uint32_t ) 0x00000100U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_TXDMABURSTLENGTH_2BEAT ( ( uint32_t ) 0x00000200U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_TXDMABURSTLENGTH_4BEAT ( ( uint32_t ) 0x00000400U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_TXDMABURSTLENGTH_8BEAT ( ( uint32_t ) 0x00000800U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_TXDMABURSTLENGTH_16BEAT ( ( uint32_t ) 0x00001000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_TXDMABURSTLENGTH_32BEAT ( ( uint32_t ) 0x00002000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ( ( uint32_t ) 0x01000100U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ( ( uint32_t ) 0x01000200U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ( ( uint32_t ) 0x01000400U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ( ( uint32_t ) 0x01000800U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ( ( uint32_t ) 0x01001000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ( ( uint32_t ) 0x01002000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format - * @{ - */ - #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ( ( uint32_t ) 0x00000080U ) - #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ( ( uint32_t ) 0x00000000U ) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration - * @{ - */ - #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ( ( uint32_t ) 0x00000000U ) - #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ( ( uint32_t ) 0x00004000U ) - #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ( ( uint32_t ) 0x00008000U ) - #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ( ( uint32_t ) 0x0000C000U ) - #define ETH_DMAARBITRATION_RXPRIORTX ( ( uint32_t ) 0x00000002U ) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment - * @{ - */ - #define ETH_DMATXDESC_LASTSEGMENTS ( ( uint32_t ) 0x40000000U ) /*!< Last Segment */ - #define ETH_DMATXDESC_FIRSTSEGMENT ( ( uint32_t ) 0x20000000U ) /*!< First Segment */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control - * @{ - */ - #define ETH_DMATXDESC_CHECKSUMBYPASS ( ( uint32_t ) 0x00000000U ) /*!< Checksum engine bypass */ - #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ( ( uint32_t ) 0x00400000U ) /*!< IPv4 header checksum insertion */ - #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ( ( uint32_t ) 0x00800000U ) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ - #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ( ( uint32_t ) 0x00C00000U ) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers - * @{ - */ - #define ETH_DMARXDESC_BUFFER1 ( ( uint32_t ) 0x00000000U ) /*!< DMA Rx Desc Buffer1 */ - #define ETH_DMARXDESC_BUFFER2 ( ( uint32_t ) 0x00000001U ) /*!< DMA Rx Desc Buffer2 */ - -/** - * @} - */ - -/** @defgroup ETH_PMT_Flags ETH PMT Flags - * @{ - */ - #define ETH_PMT_FLAG_WUFFRPR ( ( uint32_t ) 0x80000000U ) /*!< Wake-Up Frame Filter Register Pointer Reset */ - #define ETH_PMT_FLAG_WUFR ( ( uint32_t ) 0x00000040U ) /*!< Wake-Up Frame Received */ - #define ETH_PMT_FLAG_MPR ( ( uint32_t ) 0x00000020U ) /*!< Magic Packet Received */ - -/** - * @} - */ - -/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts - * @{ - */ - #define ETH_MMC_IT_TGF ( ( uint32_t ) 0x00200000U ) /*!< When Tx good frame counter reaches half the maximum value */ - #define ETH_MMC_IT_TGFMSC ( ( uint32_t ) 0x00008000U ) /*!< When Tx good multi col counter reaches half the maximum value */ - #define ETH_MMC_IT_TGFSC ( ( uint32_t ) 0x00004000U ) /*!< When Tx good single col counter reaches half the maximum value */ - -/** - * @} - */ - -/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts - * @{ - */ - #define ETH_MMC_IT_RGUF ( ( uint32_t ) 0x10020000U ) /*!< When Rx good unicast frames counter reaches half the maximum value */ - #define ETH_MMC_IT_RFAE ( ( uint32_t ) 0x10000040U ) /*!< When Rx alignment error counter reaches half the maximum value */ - #define ETH_MMC_IT_RFCE ( ( uint32_t ) 0x10000020U ) /*!< When Rx crc error counter reaches half the maximum value */ - -/** - * @} - */ - -/** @defgroup ETH_MAC_Flags ETH MAC Flags - * @{ - */ - #define ETH_MAC_FLAG_TST ( ( uint32_t ) 0x00000200U ) /*!< Time stamp trigger flag (on MAC) */ - #define ETH_MAC_FLAG_MMCT ( ( uint32_t ) 0x00000040U ) /*!< MMC transmit flag */ - #define ETH_MAC_FLAG_MMCR ( ( uint32_t ) 0x00000020U ) /*!< MMC receive flag */ - #define ETH_MAC_FLAG_MMC ( ( uint32_t ) 0x00000010U ) /*!< MMC flag (on MAC) */ - #define ETH_MAC_FLAG_PMT ( ( uint32_t ) 0x00000008U ) /*!< PMT flag (on MAC) */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_Flags ETH DMA Flags - * @{ - */ - #define ETH_DMA_FLAG_TST ( ( uint32_t ) 0x20000000U ) /*!< Time-stamp trigger interrupt (on DMA) */ - #define ETH_DMA_FLAG_PMT ( ( uint32_t ) 0x10000000U ) /*!< PMT interrupt (on DMA) */ - #define ETH_DMA_FLAG_MMC ( ( uint32_t ) 0x08000000U ) /*!< MMC interrupt (on DMA) */ - #define ETH_DMA_FLAG_DATATRANSFERERROR ( ( uint32_t ) 0x00800000U ) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ - #define ETH_DMA_FLAG_READWRITEERROR ( ( uint32_t ) 0x01000000U ) /*!< Error bits 0-write transfer, 1-read transfer */ - #define ETH_DMA_FLAG_ACCESSERROR ( ( uint32_t ) 0x02000000U ) /*!< Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMA_FLAG_NIS ( ( uint32_t ) 0x00010000U ) /*!< Normal interrupt summary flag */ - #define ETH_DMA_FLAG_AIS ( ( uint32_t ) 0x00008000U ) /*!< Abnormal interrupt summary flag */ - #define ETH_DMA_FLAG_ER ( ( uint32_t ) 0x00004000U ) /*!< Early receive flag */ - #define ETH_DMA_FLAG_FBE ( ( uint32_t ) 0x00002000U ) /*!< Fatal bus error flag */ - #define ETH_DMA_FLAG_ET ( ( uint32_t ) 0x00000400U ) /*!< Early transmit flag */ - #define ETH_DMA_FLAG_RWT ( ( uint32_t ) 0x00000200U ) /*!< Receive watchdog timeout flag */ - #define ETH_DMA_FLAG_RPS ( ( uint32_t ) 0x00000100U ) /*!< Receive process stopped flag */ - #define ETH_DMA_FLAG_RBU ( ( uint32_t ) 0x00000080U ) /*!< Receive buffer unavailable flag */ - #define ETH_DMA_FLAG_R ( ( uint32_t ) 0x00000040U ) /*!< Receive flag */ - #define ETH_DMA_FLAG_TU ( ( uint32_t ) 0x00000020U ) /*!< Underflow flag */ - #define ETH_DMA_FLAG_RO ( ( uint32_t ) 0x00000010U ) /*!< Overflow flag */ - #define ETH_DMA_FLAG_TJT ( ( uint32_t ) 0x00000008U ) /*!< Transmit jabber timeout flag */ - #define ETH_DMA_FLAG_TBU ( ( uint32_t ) 0x00000004U ) /*!< Transmit buffer unavailable flag */ - #define ETH_DMA_FLAG_TPS ( ( uint32_t ) 0x00000002U ) /*!< Transmit process stopped flag */ - #define ETH_DMA_FLAG_T ( ( uint32_t ) 0x00000001U ) /*!< Transmit flag */ - -/** - * @} - */ - -/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts - * @{ - */ - #define ETH_MAC_IT_TST ( ( uint32_t ) 0x00000200U ) /*!< Time stamp trigger interrupt (on MAC) */ - #define ETH_MAC_IT_MMCT ( ( uint32_t ) 0x00000040U ) /*!< MMC transmit interrupt */ - #define ETH_MAC_IT_MMCR ( ( uint32_t ) 0x00000020U ) /*!< MMC receive interrupt */ - #define ETH_MAC_IT_MMC ( ( uint32_t ) 0x00000010U ) /*!< MMC interrupt (on MAC) */ - #define ETH_MAC_IT_PMT ( ( uint32_t ) 0x00000008U ) /*!< PMT interrupt (on MAC) */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts - * @{ - */ - #define ETH_DMA_IT_TST ( ( uint32_t ) 0x20000000U ) /*!< Time-stamp trigger interrupt (on DMA) */ - #define ETH_DMA_IT_PMT ( ( uint32_t ) 0x10000000U ) /*!< PMT interrupt (on DMA) */ - #define ETH_DMA_IT_MMC ( ( uint32_t ) 0x08000000U ) /*!< MMC interrupt (on DMA) */ - #define ETH_DMA_IT_NIS ( ( uint32_t ) 0x00010000U ) /*!< Normal interrupt summary */ - #define ETH_DMA_IT_AIS ( ( uint32_t ) 0x00008000U ) /*!< Abnormal interrupt summary */ - #define ETH_DMA_IT_ER ( ( uint32_t ) 0x00004000U ) /*!< Early receive interrupt */ - #define ETH_DMA_IT_FBE ( ( uint32_t ) 0x00002000U ) /*!< Fatal bus error interrupt */ - #define ETH_DMA_IT_ET ( ( uint32_t ) 0x00000400U ) /*!< Early transmit interrupt */ - #define ETH_DMA_IT_RWT ( ( uint32_t ) 0x00000200U ) /*!< Receive watchdog timeout interrupt */ - #define ETH_DMA_IT_RPS ( ( uint32_t ) 0x00000100U ) /*!< Receive process stopped interrupt */ - #define ETH_DMA_IT_RBU ( ( uint32_t ) 0x00000080U ) /*!< Receive buffer unavailable interrupt */ - #define ETH_DMA_IT_R ( ( uint32_t ) 0x00000040U ) /*!< Receive interrupt */ - #define ETH_DMA_IT_TU ( ( uint32_t ) 0x00000020U ) /*!< Underflow interrupt */ - #define ETH_DMA_IT_RO ( ( uint32_t ) 0x00000010U ) /*!< Overflow interrupt */ - #define ETH_DMA_IT_TJT ( ( uint32_t ) 0x00000008U ) /*!< Transmit jabber timeout interrupt */ - #define ETH_DMA_IT_TBU ( ( uint32_t ) 0x00000004U ) /*!< Transmit buffer unavailable interrupt */ - #define ETH_DMA_IT_TPS ( ( uint32_t ) 0x00000002U ) /*!< Transmit process stopped interrupt */ - #define ETH_DMA_IT_T ( ( uint32_t ) 0x00000001U ) /*!< Transmit interrupt */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state - * @{ - */ - #define ETH_DMA_TRANSMITPROCESS_STOPPED ( ( uint32_t ) 0x00000000U ) /*!< Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMA_TRANSMITPROCESS_FETCHING ( ( uint32_t ) 0x00100000U ) /*!< Running - fetching the Tx descriptor */ - #define ETH_DMA_TRANSMITPROCESS_WAITING ( ( uint32_t ) 0x00200000U ) /*!< Running - waiting for status */ - #define ETH_DMA_TRANSMITPROCESS_READING ( ( uint32_t ) 0x00300000U ) /*!< Running - reading the data from host memory */ - #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ( ( uint32_t ) 0x00600000U ) /*!< Suspended - Tx Descriptor unavailable */ - #define ETH_DMA_TRANSMITPROCESS_CLOSING ( ( uint32_t ) 0x00700000U ) /*!< Running - closing Rx descriptor */ - -/** - * @} - */ - - -/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state - * @{ - */ - #define ETH_DMA_RECEIVEPROCESS_STOPPED ( ( uint32_t ) 0x00000000U ) /*!< Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMA_RECEIVEPROCESS_FETCHING ( ( uint32_t ) 0x00020000U ) /*!< Running - fetching the Rx descriptor */ - #define ETH_DMA_RECEIVEPROCESS_WAITING ( ( uint32_t ) 0x00060000U ) /*!< Running - waiting for packet */ - #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ( ( uint32_t ) 0x00080000U ) /*!< Suspended - Rx Descriptor unavailable */ - #define ETH_DMA_RECEIVEPROCESS_CLOSING ( ( uint32_t ) 0x000A0000U ) /*!< Running - closing descriptor */ - #define ETH_DMA_RECEIVEPROCESS_QUEUING ( ( uint32_t ) 0x000E0000U ) /*!< Running - queuing the receive frame into host memory */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_overflow ETH DMA overflow - * @{ - */ - #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ( ( uint32_t ) 0x10000000U ) /*!< Overflow bit for FIFO overflow counter */ - #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ( ( uint32_t ) 0x00010000U ) /*!< Overflow bit for missed frame counter */ - -/** - * @} - */ - -/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP - * @{ - */ - #define ETH_EXTI_LINE_WAKEUP ( ( uint32_t ) 0x00080000U ) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Macros ETH Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/** @brief Reset ETH handle state - * @param __HANDLE__: specifies the ETH handle. - * @retval None - */ - #define __HAL_ETH_RESET_HANDLE_STATE( __HANDLE__ ) ( ( __HANDLE__ )->State = HAL_ETH_STATE_RESET ) - -/** - * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of TDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ - #define __HAL_ETH_DMATXDESC_GET_FLAG( __HANDLE__, __FLAG__ ) ( ( __HANDLE__ )->TxDesc->Status & ( __FLAG__ ) == ( __FLAG__ ) ) - -/** - * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of RDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ - #define __HAL_ETH_DMARXDESC_GET_FLAG( __HANDLE__, __FLAG__ ) ( ( __HANDLE__ )->RxDesc->Status & ( __FLAG__ ) == ( __FLAG__ ) ) - -/** - * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMARXDESC_ENABLE_IT( __HANDLE__ ) ( ( __HANDLE__ )->RxDesc->ControlBufferSize &= ( ~( uint32_t ) ETH_DMARXDESC_DIC ) ) - -/** - * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMARXDESC_DISABLE_IT( __HANDLE__ ) ( ( __HANDLE__ )->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC ) - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMARXDESC_SET_OWN_BIT( __HANDLE__ ) ( ( __HANDLE__ )->RxDesc->Status |= ETH_DMARXDESC_OWN ) - -/** - * @brief Returns the specified Ethernet DMA Tx Desc collision count. - * @param __HANDLE__: ETH Handle - * @retval The Transmit descriptor collision counter value. - */ - #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT( __HANDLE__ ) ( ( ( __HANDLE__ )->TxDesc->Status & ETH_DMATXDESC_CC ) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT ) - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMATXDESC_SET_OWN_BIT( __HANDLE__ ) ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_OWN ) - -/** - * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMATXDESC_ENABLE_IT( __HANDLE__ ) ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_IC ) - -/** - * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMATXDESC_DISABLE_IT( __HANDLE__ ) ( ( __HANDLE__ )->TxDesc->Status &= ~ETH_DMATXDESC_IC ) - -/** - * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion. - * @param __HANDLE__: ETH Handle - * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ - #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION( __HANDLE__, __CHECKSUM__ ) ( ( __HANDLE__ )->TxDesc->Status |= ( __CHECKSUM__ ) ) - -/** - * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMATXDESC_CRC_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->TxDesc->Status &= ~ETH_DMATXDESC_DC ) - -/** - * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMATXDESC_CRC_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_DC ) - -/** - * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->TxDesc->Status &= ~ETH_DMATXDESC_DP ) - -/** - * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_DP ) - -/** - * @brief Enables the specified Ethernet MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ - #define __HAL_ETH_MAC_ENABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MACIMR |= ( __INTERRUPT__ ) ) - -/** - * @brief Disables the specified Ethernet MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ - #define __HAL_ETH_MAC_DISABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MACIMR &= ~( __INTERRUPT__ ) ) - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACFCR |= ETH_MACFCR_FCBBPA ) - -/** - * @brief Checks whether the Ethernet flow control busy bit is set or not. - * @param __HANDLE__: ETH Handle - * @retval The new state of flow control busy status bit (SET or RESET). - */ - #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS( __HANDLE__ ) ( ( ( __HANDLE__ )->Instance->MACFCR & ETH_MACFCR_FCBBPA ) == ETH_MACFCR_FCBBPA ) - -/** - * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACFCR |= ETH_MACFCR_FCBBPA ) - -/** - * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA ) - -/** - * @brief Checks whether the specified Ethernet MAC flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of Ethernet MAC flag. - */ - #define __HAL_ETH_MAC_GET_FLAG( __HANDLE__, __FLAG__ ) ( ( ( __HANDLE__ )->Instance->MACSR & ( __FLAG__ ) ) == ( __FLAG__ ) ) - -/** - * @brief Enables the specified Ethernet DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be - * enabled @ref ETH_DMA_Interrupts - * @retval None - */ - #define __HAL_ETH_DMA_ENABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMAIER |= ( __INTERRUPT__ ) ) - -/** - * @brief Disables the specified Ethernet DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be - * disabled. @ref ETH_DMA_Interrupts - * @retval None - */ - #define __HAL_ETH_DMA_DISABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMAIER &= ~( __INTERRUPT__ ) ) - -/** - * @brief Clears the Ethernet DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ - #define __HAL_ETH_DMA_CLEAR_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMASR = ( __INTERRUPT__ ) ) - -/** - * @brief Checks whether the specified Ethernet DMA flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ - #define __HAL_ETH_DMA_GET_FLAG( __HANDLE__, __FLAG__ ) ( ( ( __HANDLE__ )->Instance->DMASR & ( __FLAG__ ) ) == ( __FLAG__ ) ) - -/** - * @brief Checks whether the specified Ethernet DMA flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ - #define __HAL_ETH_DMA_CLEAR_FLAG( __HANDLE__, __FLAG__ ) ( ( __HANDLE__ )->Instance->DMASR = ( __FLAG__ ) ) - -/** - * @brief Checks whether the specified Ethernet DMA overflow flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __OVERFLOW__: specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of Ethernet DMA overflow Flag (SET or RESET). - */ - #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS( __HANDLE__, __OVERFLOW__ ) ( ( ( __HANDLE__ )->Instance->DMAMFBOCR & ( __OVERFLOW__ ) ) == ( __OVERFLOW__ ) ) - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__: ETH Handle - * @param __VALUE__: DMA Receive status watchdog timer register value - * @retval None - */ - #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER( __HANDLE__, __VALUE__ ) ( ( __HANDLE__ )->Instance->DMARSWTR = ( __VALUE__ ) ) - -/** - * @brief Enables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU ) - -/** - * @brief Disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU ) - -/** - * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE ) - -/** - * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE ) - -/** - * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE ) - -/** - * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE ) - -/** - * @brief Enables the MAC Power Down. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_POWER_DOWN_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD ) - -/** - * @brief Disables the MAC Power Down. - * @param __HANDLE__: ETH Handle - * @retval None - */ - #define __HAL_ETH_POWER_DOWN_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD ) - -/** - * @brief Checks whether the specified Ethernet PMT flag is set or not. - * @param __HANDLE__: ETH Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of Ethernet PMT Flag (SET or RESET). - */ - #define __HAL_ETH_GET_PMT_FLAG_STATUS( __HANDLE__, __FLAG__ ) ( ( ( __HANDLE__ )->Instance->MACPMTCSR & ( __FLAG__ ) ) == ( __FLAG__ ) ) - -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_MMC_COUNTER_FULL_PRESET( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR |= ( ETH_MMCCR_MCFHP | ETH_MMCCR_MCP ) ) - -/** - * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_MMC_COUNTER_HALF_PRESET( __HANDLE__ ) \ - do { ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_MCFHP; \ - ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_MCP; } while( 0 ) - -/** - * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_MCF ) - -/** - * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_MCF ) - -/** - * @brief Enables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_ROR ) - -/** - * @brief Disables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_ROR ) - -/** - * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_CSR ) - -/** - * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_CSR ) - -/** - * @brief Resets the MMC Counters. - * @param __HANDLE__: ETH Handle. - * @retval None - */ - #define __HAL_ETH_MMC_COUNTERS_RESET( __HANDLE__ ) ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_CR ) - -/** - * @brief Enables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ - #define __HAL_ETH_MMC_RX_IT_ENABLE( __HANDLE__, __INTERRUPT__ ) ( __HANDLE__ )->Instance->MMCRIMR &= ~( ( __INTERRUPT__ ) & 0xEFFFFFFF ) - -/** - * @brief Disables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ - #define __HAL_ETH_MMC_RX_IT_DISABLE( __HANDLE__, __INTERRUPT__ ) ( __HANDLE__ )->Instance->MMCRIMR |= ( ( __INTERRUPT__ ) & 0xEFFFFFFF ) - -/** - * @brief Enables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ - #define __HAL_ETH_MMC_TX_IT_ENABLE( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MMCRIMR &= ~( __INTERRUPT__ ) ) - -/** - * @brief Disables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ - #define __HAL_ETH_MMC_TX_IT_DISABLE( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MMCRIMR |= ( __INTERRUPT__ ) ) - -/** - * @brief Enables the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= ( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Disables the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Enable event on ETH External event line. - * @retval None. - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= ( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Disable event on ETH External event line - * @retval None. - */ - #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Get flag of the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & ( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Clear flag of the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = ( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Enables rising edge trigger to the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables the rising edge trigger to the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Enables falling edge trigger to the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= ( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Disables falling edge trigger to the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Enables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() \ - EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP; \ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() \ - EXTI->RTSR &= ~( ETH_EXTI_LINE_WAKEUP ); \ - EXTI->FTSR &= ~( ETH_EXTI_LINE_WAKEUP ) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ - #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER |= ETH_EXTI_LINE_WAKEUP - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup ETH_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ - -/** @addtogroup ETH_Exported_Functions_Group1 - * @{ - */ - HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_DeInit( ETH_HandleTypeDef * heth ); - void HAL_ETH_MspInit( ETH_HandleTypeDef * heth ); - void HAL_ETH_MspDeInit( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_DMATxDescListInit( ETH_HandleTypeDef * heth, - ETH_DMADescTypeDef * DMATxDescTab, - uint8_t * TxBuff, - uint32_t TxBuffCount ); - HAL_StatusTypeDef HAL_ETH_DMARxDescListInit( ETH_HandleTypeDef * heth, - ETH_DMADescTypeDef * DMARxDescTab, - uint8_t * RxBuff, - uint32_t RxBuffCount ); - -/** - * @} - */ -/* IO operation functions ****************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group2 - * @{ - */ - HAL_StatusTypeDef HAL_ETH_TransmitFrame( ETH_HandleTypeDef * heth, - uint32_t FrameLength ); - HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef * heth ); -/* Communication with PHY functions*/ - HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef * heth, - uint16_t PHYReg, - uint32_t * RegValue ); - HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef * heth, - uint16_t PHYReg, - uint32_t RegValue ); -/* Non-Blocking mode: Interrupt */ - HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef * heth ); - void HAL_ETH_IRQHandler( ETH_HandleTypeDef * heth ); -/* Callback in non blocking modes (Interrupt) */ - void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_ErrorCallback( ETH_HandleTypeDef * heth ); - -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ - -/** @addtogroup ETH_Exported_Functions_Group3 - * @{ - */ - - HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_Stop( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_ConfigMAC( ETH_HandleTypeDef * heth, - ETH_MACInitTypeDef * macconf ); - HAL_StatusTypeDef HAL_ETH_ConfigDMA( ETH_HandleTypeDef * heth, - ETH_DMAInitTypeDef * dmaconf ); - -/** - * @} - */ - -/* Peripheral State functions ************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group4 - * @{ - */ - HAL_ETH_StateTypeDef HAL_ETH_GetState( ETH_HandleTypeDef * heth ); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus - } - #endif - -#endif /* __STM32Fxx_HAL_ETH_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/source/portable/NetworkInterface/STM32Hxx/NetworkInterface.c b/source/portable/NetworkInterface/STM32Hxx/NetworkInterface.c deleted file mode 100644 index 7105ca26a..000000000 --- a/source/portable/NetworkInterface/STM32Hxx/NetworkInterface.c +++ /dev/null @@ -1,1015 +0,0 @@ -/* - * Some constants, hardware definitions and comments taken from ST's HAL driver - * library, COPYRIGHT(c) 2015 STMicroelectronics. - */ - -/* - * FreeRTOS+TCP V2.3.2 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://aws.amazon.com/freertos - * http://www.FreeRTOS.org - */ - -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* FreeRTOS+TCP includes. */ -#include "FreeRTOS_IP.h" -#include "FreeRTOS_Sockets.h" -#include "FreeRTOS_IP_Private.h" -#include "FreeRTOS_DNS.h" -#include "FreeRTOS_Routing.h" -#include "NetworkBufferManagement.h" -#include "NetworkInterface.h" - -#include "phyHandling.h" - -/* ST includes. */ -#include "stm32h7xx_hal.h" - -#ifndef STM32Hxx_HAL_ETH_H - -/* - * The ST HAL library provides stm32h7xx_hal_eth.{c,h}. - * This FreeRTOS+TCP driver renamed these files to stm32hxx_hal_eth.{c,h} - * by removing the '7'. - * Please make sure that "portable/NetworkInterface/STM32Hxx" is included - * in the include paths earlier than "STM32H7xx_HAL_Driver/Inc". - * and also make sure that you have defined 'HAL_ETH_MODULE_ENABLED' - * in your copy of "stm32h7xx_hal_conf". - */ - #error stm32hxx_hal_eth.h is possibly not included -#endif - -/* Interrupt events to process: reception, transmission and error handling. */ -#define EMAC_IF_RX_EVENT 1UL -#define EMAC_IF_TX_EVENT 2UL -#define EMAC_IF_ERR_EVENT 4UL - - -#ifndef niEMAC_HANDLER_TASK_NAME - #define niEMAC_HANDLER_TASK_NAME "EMAC-task" -#endif - -#ifndef niEMAC_HANDLER_TASK_STACK_SIZE - #define niEMAC_HANDLER_TASK_STACK_SIZE ( 4 * configMINIMAL_STACK_SIZE ) -#endif - -#ifndef niEMAC_HANDLER_TASK_PRIORITY - #define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1 -#endif - - -/* Bit map of outstanding ETH interrupt events for processing. */ -static volatile uint32_t ulISREvents; - -typedef enum -{ - eMACInit, /* Must initialise MAC. */ - eMACPass, /* Initialisation was successful. */ - eMACFailed, /* Initialisation failed. */ -} eMAC_INIT_STATUS_TYPE; - -static eMAC_INIT_STATUS_TYPE xMacInitStatus = eMACInit; - -/* xTXDescriptorSemaphore is shared with stm32h7xx_hal_eth.c. */ -SemaphoreHandle_t xTXDescriptorSemaphore = NULL; - -/* Both the IP-task and the EMAC task use the TX channel. Use - * a mutex to protect it against synchronous access by both tasks. */ -static SemaphoreHandle_t xTransmissionMutex; - -/* Global Ethernet handle */ -static ETH_HandleTypeDef xEthHandle; -static ETH_TxPacketConfig xTxConfig; - -static NetworkInterface_t * pxMyInterface = NULL; - -/* - * About the section ".ethernet_data" : the DMA wants the descriptors and buffers allocated in the - * RAM3 memory, which can be added to the .LD file as follows:: - * - * RAM3 (xrw) : ORIGIN = 0x24040000, LENGTH = 0x8000 - * - * .ethernet_data : - * { - * PROVIDE_HIDDEN (__ethernet_data_start = .); - * KEEP (*(SORT(.ethernet_data.*))) - * KEEP (*(.ethernet_data*)) - * PROVIDE_HIDDEN (__ethernet_data_end = .); - * } >RAM3 - * - */ -/* Ethernet Rx DMA Descriptors */ -ETH_DMADescTypeDef DMARxDscrTab[ ETH_RX_DESC_CNT ] __attribute__( ( section( ".ethernet_data" ), aligned( 32 ) ) ); - -/* Ethernet Receive Buffer */ -#if ( ipconfigZERO_COPY_TX_DRIVER == 0 ) - uint8_t Rx_Buff[ ETH_RX_DESC_CNT ][ ETH_RX_BUF_SIZE ] __attribute__( ( section( ".ethernet_data" ), aligned( 32 ) ) ); -#endif - -/* Ethernet Tx DMA Descriptors */ -ETH_DMADescTypeDef DMATxDscrTab[ ETH_TX_DESC_CNT ] __attribute__( ( section( ".ethernet_data" ), aligned( 32 ) ) ); - -/* Ethernet Transmit Buffer */ -#if ( ipconfigZERO_COPY_TX_DRIVER == 0 ) - uint8_t Tx_Buff[ ETH_TX_DESC_CNT ][ ETH_TX_BUF_SIZE ] __attribute__( ( section( ".ethernet_data" ), aligned( 32 ) ) ); -#endif - -/* This function binds PHY IO functions, then inits and configures */ -static void prvMACBProbePhy( void ); - -/* Force a negotiation with the Switch or Router and wait for LS. */ -static void prvEthernetUpdateConfig( BaseType_t xForce ); - -/* Holds the handle of the task used as a deferred interrupt processor. The - * handle is used so direct notifications can be sent to the task for all EMAC/DMA - * related interrupts. */ -static TaskHandle_t xEMACTaskHandle = NULL; - -/* - * A deferred interrupt handler task that processes - */ -static void prvEMACHandlerTask( void * pvParameters ); - -/* - * See if there is a new packet and forward it to the IP-task. - */ -static BaseType_t prvNetworkInterfaceInput( void ); - -/* Private PHY IO functions and properties */ -static int32_t ETH_PHY_IO_ReadReg( uint32_t DevAddr, - uint32_t RegAddr, - uint32_t * pRegVal ); -static int32_t ETH_PHY_IO_WriteReg( uint32_t DevAddr, - uint32_t RegAddr, - uint32_t RegVal ); - -static void vClearOptionBit( volatile uint32_t * pulValue, - uint32_t ulValue ); - -static size_t uxGetOwnCount( ETH_HandleTypeDef * heth ); - -/* FreeRTOS+TCP/multi : - * Each network device has 3 access functions: - * - Initialise the device - * - Output a network packet - * - Return the PHY Link-Status (LS) - * They can be defined as static because the function addresses - * addresses will be stored in struct NetworkInterface_t. */ - -static BaseType_t xSTM32H_NetworkInterfaceInitialise( NetworkInterface_t * pxInterface ); - -static BaseType_t xSTM32H_NetworkInterfaceOutput( NetworkInterface_t * pxInterface, - NetworkBufferDescriptor_t * const pxBuffer, - BaseType_t xReleaseAfterSend ); - -static BaseType_t xSTM32H_GetPhyLinkStatus( NetworkInterface_t * pxInterface ); - -NetworkInterface_t * pxSTM32H_FillInterfaceDescriptor( BaseType_t xEMACIndex, - NetworkInterface_t * pxInterface ); -/*-----------------------------------------------------------*/ - -static EthernetPhy_t xPhyObject; -/* For local use only: describe the PHY's properties: */ -const PhyProperties_t xPHYProperties = -{ - .ucSpeed = PHY_SPEED_AUTO, - .ucDuplex = PHY_DUPLEX_AUTO, - .ucMDI_X = PHY_MDIX_DIRECT -}; -/*-----------------------------------------------------------*/ - - - -/******************************************************************************* -* Network Interface API Functions -*******************************************************************************/ - -static uint8_t * pucGetRXBuffer( size_t uxSize ) -{ - TickType_t uxBlockTimeTicks = ipMS_TO_MIN_TICKS( 10U ); - NetworkBufferDescriptor_t * pxBufferDescriptor; - uint8_t * pucReturn = NULL; - - pxBufferDescriptor = pxGetNetworkBufferWithDescriptor( uxSize, uxBlockTimeTicks ); - - if( pxBufferDescriptor != NULL ) - { - pucReturn = pxBufferDescriptor->pucEthernetBuffer; - } - - return pucReturn; -} -/*-----------------------------------------------------------*/ - -static BaseType_t xSTM32H_NetworkInterfaceInitialise( NetworkInterface_t * pxInterface ) -{ - BaseType_t xResult; - NetworkEndPoint_t * pxEndPoint; - HAL_StatusTypeDef xHalEthInitStatus; - size_t uxIndex = 0; - - if( xMacInitStatus == eMACInit ) - { - pxMyInterface = pxInterface; - - pxEndPoint = FreeRTOS_FirstEndPoint( pxInterface ); - configASSERT( pxEndPoint != NULL ); - - /* - * Initialize ETH Handler - * It assumes that Ethernet GPIO and clock configuration - * are already done in the ETH_MspInit() - */ - xEthHandle.Instance = ETH; - xEthHandle.Init.MACAddr = ( uint8_t * ) pxEndPoint->xMACAddress.ucBytes; - xEthHandle.Init.MediaInterface = HAL_ETH_RMII_MODE; - xEthHandle.Init.TxDesc = DMATxDscrTab; - xEthHandle.Init.RxDesc = DMARxDscrTab; - xEthHandle.Init.RxBuffLen = ( ETH_RX_BUF_SIZE - ipBUFFER_PADDING ) & ~( ( uint32_t ) 3U ); - - /* Make sure that all unused fields are cleared. */ - memset( &( DMATxDscrTab ), '\0', sizeof( DMATxDscrTab ) ); - memset( &( DMARxDscrTab ), '\0', sizeof( DMARxDscrTab ) ); - - xHalEthInitStatus = HAL_ETH_Init( &( xEthHandle ) ); - - /* Only for inspection by debugger. */ - ( void ) xHalEthInitStatus; - - /* Configuration for HAL_ETH_Transmit(_IT). */ - memset( &( xTxConfig ), 0, sizeof( ETH_TxPacketConfig ) ); - xTxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CRCPAD; - - #if ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) - { - /*xTxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; */ - xTxConfig.Attributes |= ETH_TX_PACKETS_FEATURES_CSUM; - xTxConfig.ChecksumCtrl = ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC; - } - #else - { - xTxConfig.ChecksumCtrl = ETH_CHECKSUM_DISABLE; - } - #endif - xTxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; - - /* This counting semaphore will count the number of free TX DMA descriptors. */ - xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TX_DESC_CNT, ( UBaseType_t ) ETH_TX_DESC_CNT ); - configASSERT( xTXDescriptorSemaphore ); - - xTransmissionMutex = xSemaphoreCreateMutex(); - configASSERT( xTransmissionMutex ); - - /* Assign Rx memory buffers to a DMA Rx descriptor */ - for( uxIndex = 0; uxIndex < ETH_RX_DESC_CNT; uxIndex++ ) - { - uint8_t * pucBuffer; - - #if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) - { - pucBuffer = pucGetRXBuffer( ETH_RX_BUF_SIZE ); - configASSERT( pucBuffer != NULL ); - } - #else - { - pucBuffer = Rx_Buff[ uxIndex ]; - } - #endif - - HAL_ETH_DescAssignMemory( &( xEthHandle ), uxIndex, pucBuffer, NULL ); - } - - /* Initialize the MACB and set all PHY properties */ - prvMACBProbePhy(); - - /* Force a negotiation with the Switch or Router and wait for LS. */ - prvEthernetUpdateConfig( pdTRUE ); - - /* The deferred interrupt handler task is created at the highest - * possible priority to ensure the interrupt handler can return directly - * to it. The task's handle is stored in xEMACTaskHandle so interrupts can - * notify the task when there is something to process. */ - if( xTaskCreate( prvEMACHandlerTask, niEMAC_HANDLER_TASK_NAME, niEMAC_HANDLER_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &( xEMACTaskHandle ) ) == pdPASS ) - { - /* The task was created successfully. */ - xMacInitStatus = eMACPass; - } - else - { - xMacInitStatus = eMACFailed; - } - } /* ( xMacInitStatus == eMACInit ) */ - - if( xMacInitStatus != eMACPass ) - { - /* EMAC initialisation failed, return pdFAIL. */ - xResult = pdFAIL; - } - else - { - if( xPhyObject.ulLinkStatusMask != 0uL ) - { - xResult = pdPASS; - FreeRTOS_printf( ( "Link Status is high\n" ) ); - } - else - { - /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running - * and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */ - xResult = pdFAIL; - } - } - - return xResult; -} -/*-----------------------------------------------------------*/ - -static BaseType_t xSTM32H_GetPhyLinkStatus( NetworkInterface_t * pxInterface ) -{ - BaseType_t xReturn; - - if( xPhyObject.ulLinkStatusMask != 0U ) - { - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) - -/* Do not call the following function directly. It is there for downward compatibility. - * The function FreeRTOS_IPInit() will call it to initialice the interface and end-point - * objects. See the description in FreeRTOS_Routing.h. */ - NetworkInterface_t * pxFillInterfaceDescriptor( BaseType_t xEMACIndex, - NetworkInterface_t * pxInterface ) - { - pxSTM32Hxx_FillInterfaceDescriptor( xEMACIndex, pxInterface ); - } - -#endif -/*-----------------------------------------------------------*/ - -NetworkInterface_t * pxSTM32H_FillInterfaceDescriptor( BaseType_t xEMACIndex, - NetworkInterface_t * pxInterface ) -{ - static char pcName[ 17 ]; - -/* This function pxSTM32Hxx_FillInterfaceDescriptor() adds a network-interface. - * Make sure that the object pointed to by 'pxInterface' - * is declared static or global, and that it will remain to exist. */ - - snprintf( pcName, sizeof( pcName ), "eth%u", ( unsigned ) xEMACIndex ); - - memset( pxInterface, '\0', sizeof( *pxInterface ) ); - pxInterface->pcName = pcName; /* Just for logging, debugging. */ - pxInterface->pvArgument = ( void * ) xEMACIndex; /* Has only meaning for the driver functions. */ - pxInterface->pfInitialise = xSTM32H_NetworkInterfaceInitialise; - pxInterface->pfOutput = xSTM32H_NetworkInterfaceOutput; - pxInterface->pfGetPhyLinkStatus = xSTM32H_GetPhyLinkStatus; - - FreeRTOS_AddNetworkInterface( pxInterface ); - - return pxInterface; -} -/*-----------------------------------------------------------*/ - -static BaseType_t xSTM32H_NetworkInterfaceOutput( NetworkInterface_t * pxInterface, - NetworkBufferDescriptor_t * const pxBuffer, - BaseType_t xReleaseAfterSend ) -{ - BaseType_t xResult = pdFAIL; - TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 100U ); - uint8_t * pucTXBuffer; - - if( xGetPhyLinkStatus( pxInterface ) == = pdPASS ) - { - #if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) - /* Zero-copy method, pass the buffer. */ - pucTXBuffer = pxBuffer->pucEthernetBuffer; - - /* As the buffer is passed to the driver, it must exist. - * The library takes care of this. */ - configASSERT( xReleaseAfterSend != pdFALSE ); - #else - pucTXBuffer = Tx_Buff[ xEthHandle.TxDescList.CurTxDesc ]; - /* The copy method, left here for educational purposes. */ - configASSERT( pxBuffer->xDataLength <= sizeof( Tx_Buff[ 0 ] ) ); - #endif - - ETH_BufferTypeDef xTransmitBuffer = - { - .buffer = pucTXBuffer, - .len = pxBuffer->xDataLength, - .next = NULL /* FreeRTOS+TCP does not use linked buffers. */ - }; - /* This is the total length, which is equal to the buffer. */ - xTxConfig.Length = pxBuffer->xDataLength; - xTxConfig.TxBuffer = &( xTransmitBuffer ); - - /* This counting semaphore counts the number of free TX DMA descriptors. */ - if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) - { - /* If the logging routine is using the network, the following message - * may cause a new error message. */ - FreeRTOS_printf( ( "emacps_send_message: Time-out waiting for TX buffer\n" ) ); - } - else - { - /* Memory barrier: Make sure that the data written to the packet buffer got written. */ - __DSB(); - - /* Get exclusive accces to the TX process. - * Both the IP-task and the EMAC task will work on the TX process. */ - if( xSemaphoreTake( xTransmissionMutex, xBlockTimeTicks ) != pdFAIL ) - { - #if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) - { - /* Do not release the buffer. */ - xReleaseAfterSend = pdFALSE; - } - #else - { - memcpy( pucTXBuffer, pxBuffer->pucEthernetBuffer, pxBuffer->xDataLength ); - - /* A memory barrier to make sure that the outgoing packets has been written - * to the physical memory. */ - __DSB(); - } - #endif /* if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) */ - - if( HAL_ETH_Transmit_IT( &( xEthHandle ), &( xTxConfig ) ) == HAL_OK ) - { - xResult = pdPASS; - } - - /* And release the mutex. */ - xSemaphoreGive( xTransmissionMutex ); - } - - /* Call the standard trace macro to log the send event. */ - iptraceNETWORK_INTERFACE_TRANSMIT(); - } - } - - if( xReleaseAfterSend != pdFALSE ) - { - vReleaseNetworkBufferAndDescriptor( pxBuffer ); - } - - return xResult; -} -/*-----------------------------------------------------------*/ - -/******************************************************************************* -* END Network Interface API Functions -*******************************************************************************/ - - - -/******************************************************************************* -* Network Interface Static Functions -*******************************************************************************/ - -static void prvMACBProbePhy( void ) -{ - /* Bind the write and read access functions. */ - vPhyInitialise( &( xPhyObject ), - ( xApplicationPhyReadHook_t ) ETH_PHY_IO_ReadReg, - ( xApplicationPhyWriteHook_t ) ETH_PHY_IO_WriteReg ); - /* Poll the bus for all connected PHY's. */ - xPhyDiscover( &( xPhyObject ) ); - /* Configure them using the properties provided. */ - xPhyConfigure( &( xPhyObject ), &( xPHYProperties ) ); -} -/*-----------------------------------------------------------*/ - -static void prvEthernetUpdateConfig( BaseType_t xForce ) -{ - ETH_MACConfigTypeDef MACConf; - uint32_t speed = 0, duplex = 0; - - FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n", - xPhyObject.ulLinkStatusMask, - ( int ) xForce ) ); - - if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) ) - { - /* Restart the auto-negotiation. */ - xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &( xPhyObject ) ) ); - - /* Configure the MAC with the Duplex Mode fixed by the - * auto-negotiation process. */ - if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL ) - { - duplex = ETH_FULLDUPLEX_MODE; - } - else - { - duplex = ETH_HALFDUPLEX_MODE; - } - - /* Configure the MAC with the speed fixed by the - * auto-negotiation process. */ - if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 ) - { - speed = ETH_SPEED_10M; - } - else - { - speed = ETH_SPEED_100M; - } - - /* Get MAC and configure it */ - HAL_ETH_GetMACConfig( &( xEthHandle ), &( MACConf ) ); - MACConf.DuplexMode = duplex; - MACConf.Speed = speed; - HAL_ETH_SetMACConfig( &( xEthHandle ), &( MACConf ) ); - #if ( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM != 0 ) - { - MACConf.ChecksumOffload = ENABLE; - } - #else - { - MACConf.ChecksumOffload = DISABLE; - } - #endif /* ( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM != 0 ) */ - - /* Restart MAC interface */ - HAL_ETH_Start_IT( &( xEthHandle ) ); - } - else - { - /* Stop MAC interface */ - HAL_ETH_Stop_IT( &( xEthHandle ) ); - } -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvNetworkInterfaceInput( void ) -{ - BaseType_t xReturn = 0; - - /* For as long as a packet is immediately available. */ - for( ; ; ) - { - NetworkBufferDescriptor_t * pxBufferDescriptor; - NetworkBufferDescriptor_t * pxReceivedBuffer = NULL; - ETH_BufferTypeDef data_buffer; - size_t uxDataLength; - size_t uxLength; - - uxDataLength = HAL_ETH_GetRxData( &( xEthHandle ), &( data_buffer ) ); - - if( uxDataLength == 0U ) - { - /* No more packets received. */ - break; - } - - xReturn++; - - #if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) - { - /* Reserve the maximum length for the next reception. */ - uxLength = ETH_RX_BUF_SIZE; - - if( data_buffer.buffer != NULL ) - { - pxReceivedBuffer = pxPacketBuffer_to_NetworkBuffer( data_buffer.buffer ); - #if ( ipconfigTCP_IP_SANITY != 0 ) - { - configASSERT( bIsValidNetworkDescriptor( pxReceivedBuffer ) != 0 ); - } - #endif - } - - if( pxReceivedBuffer == NULL ) - { - FreeRTOS_printf( ( "Strange: no descriptor received\n" ) ); - } - } - #else /* if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) */ - { - /* Reserve the length of the packet that was just received. */ - uxLength = uxDataLength; - } - #endif /* if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) */ - - pxBufferDescriptor = pxGetNetworkBufferWithDescriptor( uxLength, 0u ); - - if( pxBufferDescriptor == NULL ) - { - /* The event was lost because a network buffer was not available. - * Call the standard trace macro to log the occurrence. */ - iptraceETHERNET_RX_EVENT_LOST(); - } - - #if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) - { - if( pxBufferDescriptor == NULL ) - { - /* Can not receive this packet. Buffer will be re-used. */ - pxReceivedBuffer = NULL; - } - else if( pxReceivedBuffer != NULL ) - { - pxReceivedBuffer->xDataLength = uxDataLength; - } - else - { - /* Allocating a new buffer failed. */ - } - } - #else /* if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) */ - { - if( pxBufferDescriptor != NULL ) - { - pxReceivedBuffer = pxBufferDescriptor; - /* The copy method. */ - memcpy( pxReceivedBuffer->pucEthernetBuffer, data_buffer.buffer, uxDataLength ); - pxReceivedBuffer->xDataLength = uxDataLength; - /* Make sure that the descriptor isn't used any more. */ - pxBufferDescriptor = NULL; - } - } - #endif /* if ( ipconfigZERO_COPY_RX_DRIVER != 0 ) */ - - { - uint8_t * pucBuffer = NULL; - - if( pxBufferDescriptor != NULL ) - { - pucBuffer = pxBufferDescriptor->pucEthernetBuffer; - } - - /* Assign an RX buffer to the descriptor, so that - * a next packet can be received. */ - HAL_ETH_BuildRxDescriptors( &( xEthHandle ), pucBuffer ); - } - - /* See if the data contained in the received Ethernet frame needs - * to be processed. NOTE! It is preferable to do this in - * the interrupt service routine itself, which would remove the need - * to unblock this task for packets that don't need processing. */ - - if( pxReceivedBuffer != NULL ) - { - BaseType_t xDoRelease = pdFALSE; - - if( eConsiderFrameForProcessing( pxReceivedBuffer->pucEthernetBuffer ) != eProcessBuffer ) - { - /* The Ethernet frame can be dropped, but the Ethernet buffer must be released. */ - xDoRelease = pdTRUE; - } - else - { - /* The event about to be sent to the TCP/IP is an Rx event. - * pvData is used to point to the network buffer descriptor that - * now references the received data. */ - - IPStackEvent_t xRxEvent = - { - .eEventType = eNetworkRxEvent, - .pvData = ( void * ) pxReceivedBuffer - }; - - pxReceivedBuffer->pxInterface = pxMyInterface; - pxReceivedBuffer->pxEndPoint = FreeRTOS_MatchingEndpoint( pxMyInterface, pxReceivedBuffer->pucEthernetBuffer ); - - /* Send the data to the TCP/IP stack. */ - if( xSendEventStructToIPTask( &( xRxEvent ), 0 ) != pdFALSE ) - { - /* The message was successfully sent to the TCP/IP stack. - * Call the standard trace macro to log the occurrence. */ - iptraceNETWORK_INTERFACE_RECEIVE(); - } - else - { - xDoRelease = pdTRUE; - - /* The buffer could not be sent to the IP task so the buffer - * must be released. */ - - /* Make a call to the standard trace macro to log the - * occurrence. */ - iptraceETHERNET_RX_EVENT_LOST(); - } - } - - if( xDoRelease != pdFALSE ) - { - vReleaseNetworkBufferAndDescriptor( pxReceivedBuffer ); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -/******************************************************************************* -* END Network Interface Static Functions -*******************************************************************************/ - - - -/******************************************************************************* -* PHY IO Functions -*******************************************************************************/ - -/** - * @brief Read a PHY register through the MDIO interface. - * @param DevAddr: PHY port address - * @param RegAddr: PHY register address - * @param pRegVal: pointer to hold the register value - * @retval 0 if OK -1 if Error - */ -static int32_t ETH_PHY_IO_ReadReg( uint32_t ulDevAddr, - uint32_t ulRegAddr, - uint32_t * pulRegVal ) -{ - int32_t iResult = -1; - - if( HAL_ETH_ReadPHYRegister( &( xEthHandle ), ulDevAddr, ulRegAddr, pulRegVal ) == HAL_OK ) - { - iResult = 0; - } - - return iResult; -} -/*-----------------------------------------------------------*/ - -/** - * @brief Write a value to a PHY register through the MDIO interface. - * @param DevAddr: PHY port address - * @param RegAddr: PHY register address - * @param RegVal: Value to be written - * @retval 0 if OK -1 if Error - */ -static int32_t ETH_PHY_IO_WriteReg( uint32_t ulDevAddr, - uint32_t ulRegAddr, - uint32_t pulRegVal ) -{ - int32_t iResult = -1; - - if( HAL_ETH_WritePHYRegister( &( xEthHandle ), ulDevAddr, ulRegAddr, pulRegVal ) == HAL_OK ) - { - iResult = 0; - } - - return iResult; -} -/*-----------------------------------------------------------*/ - -/******************************************************************************* -* END PHY IO Functions -*******************************************************************************/ - - - -/******************************************************************************* -* Ethernet Handling Functions -*******************************************************************************/ - -void ETH_IRQHandler( void ) -{ - HAL_ETH_IRQHandler( &( xEthHandle ) ); -} -/*-----------------------------------------------------------*/ - -static void prvSetFlagsAndNotify( uint32_t ulFlags ) -{ - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - /* Ethernet RX-Complete callback function, elsewhere declared as weak. - * No critical section needed, this function is called from an ISR. */ - ulISREvents |= ulFlags; - - /* Wakeup the prvEMACHandlerTask. */ - if( xEMACTaskHandle != NULL ) - { - vTaskNotifyGiveFromISR( xEMACTaskHandle, &( xHigherPriorityTaskWoken ) ); - portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); - } -} -/*-----------------------------------------------------------*/ - -void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ) -{ - ( void ) heth; - prvSetFlagsAndNotify( EMAC_IF_TX_EVENT ); -} -/*-----------------------------------------------------------*/ - -void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ) -{ - ( void ) heth; - prvSetFlagsAndNotify( EMAC_IF_RX_EVENT ); -} -/*-----------------------------------------------------------*/ - -void HAL_ETH_DMAErrorCallback( ETH_HandleTypeDef * heth ) -{ - ( void ) heth; - prvSetFlagsAndNotify( EMAC_IF_ERR_EVENT ); -} -/*-----------------------------------------------------------*/ - -/******************************************************************************* -* END Ethernet Handling Functions -*******************************************************************************/ - -uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * ETH_RX_BUF_SIZE ] -#if ( ipconfigZERO_COPY_RX_DRIVER != 0 || ipconfigZERO_COPY_TX_DRIVER != 0 ) - __attribute__( ( section( ".ethernet_data" ) ) ) -#endif /* ( ipconfigZERO_COPY_RX_DRIVER != 0 || ipconfigZERO_COPY_TX_DRIVER != 0 ) */ -__attribute__( ( aligned( 32 ) ) ); - -void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) -{ - uint8_t * ucRAMBuffer = ucNetworkPackets; - uint32_t ul; - - for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ ) - { - pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING; - *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) ); - ucRAMBuffer += ETH_RX_BUF_SIZE; - } -} -/*-----------------------------------------------------------*/ - -#define __NOP() __ASM volatile ( "nop" ) - -static void vClearOptionBit( volatile uint32_t * pulValue, - uint32_t ulValue ) -{ - portENTER_CRITICAL(); - *( pulValue ) &= ~( ulValue ); - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static size_t uxGetOwnCount( ETH_HandleTypeDef * heth ) -{ - BaseType_t xIndex; - BaseType_t xCount = 0; - ETH_RxDescListTypeDef * dmarxdesclist = &heth->RxDescList; - - /* Count the number of RX descriptors that are owned by DMA. */ - for( xIndex = 0; xIndex < ETH_RX_DESC_CNT; xIndex++ ) - { - __IO const ETH_DMADescTypeDef * dmarxdesc = - ( __IO const ETH_DMADescTypeDef * )dmarxdesclist->RxDesc[ xIndex ]; - - if( ( dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_OWN ) != 0U ) - { - xCount++; - } - } - - return xCount; -} -/*-----------------------------------------------------------*/ - -static void prvEMACHandlerTask( void * pvParameters ) -{ -/* When sending a packet, all descriptors in the transmission channel may - * be occupied. In stat case, the program will wait (block) for the counting - * semaphore. */ - const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); - size_t uxTXDescriptorsUsed = 0U; - size_t uxRXDescriptorsUsed = ETH_RX_DESC_CNT; - - ( void ) pvParameters; - - for( ; ; ) - { - BaseType_t xResult = 0; - - #if ( ipconfigHAS_PRINTF != 0 ) - { - size_t uxUsed; - size_t uxOwnCount; - - /* Call a function that monitors resources: the amount of free network - * buffers and the amount of free space on the heap. See FreeRTOS_IP.c - * for more detailed comments. */ - vPrintResourceStats(); - - /* Some more statistics: number of free descriptors. */ - uxUsed = ETH_TX_DESC_CNT - uxSemaphoreGetCount( xTXDescriptorSemaphore ); - - if( uxTXDescriptorsUsed < uxUsed ) - { - uxTXDescriptorsUsed = uxUsed; - FreeRTOS_printf( ( "TX descriptors %u/%u\n", - uxTXDescriptorsUsed, - ETH_TX_DESC_CNT ) ); - } - - uxOwnCount = uxGetOwnCount( &( xEthHandle ) ); - - if( uxRXDescriptorsUsed > uxOwnCount ) - { - uxRXDescriptorsUsed = uxOwnCount; - FreeRTOS_printf( ( "RX descriptors %u/%u\n", - uxRXDescriptorsUsed, - ETH_RX_DESC_CNT ) ); - } - } - #endif /* ( ipconfigHAS_PRINTF != 0 ) */ - - ulTaskNotifyTake( pdFALSE, ulMaxBlockTime ); - - /* Wait for the Ethernet MAC interrupt to indicate that another packet - * has been received. */ - if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0U ) - { - vClearOptionBit( &( ulISREvents ), EMAC_IF_RX_EVENT ); - xResult = prvNetworkInterfaceInput(); - } - - /* When a packet has been transmitted, the descriptor must be - * prepared for a next transmission. - * When using zero-copy, the network buffer must be released - * ( i.e. returned to the pool of network buffers ). */ - - if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0U ) - { - vClearOptionBit( &( ulISREvents ), EMAC_IF_TX_EVENT ); - - if( xSemaphoreTake( xTransmissionMutex, 10000U ) != pdFAIL ) - { - ETH_Clear_Tx_Descriptors( &( xEthHandle ) ); - xSemaphoreGive( xTransmissionMutex ); - } - } - - /* Some error has occurred, possibly an overflow or an underflow. */ - if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0U ) - { - vClearOptionBit( &( ulISREvents ), EMAC_IF_ERR_EVENT ); - - xEthHandle.gState = HAL_ETH_STATE_READY; - /* Enable all interrupts */ - HAL_ETH_Start_IT( &( xEthHandle ) ); - xResult += prvNetworkInterfaceInput(); - } - - if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 ) - { - /* - * The function xPhyCheckLinkStatus() returns pdTRUE if the - * Link Status has changes since it was called the last time. - */ - if( xGetPhyLinkStatus( pxMyInterface ) == pdFALSE ) - { - /* Stop the DMA transfer. */ - HAL_ETH_Stop_IT( &( xEthHandle ) ); - /* Clear the Transmit buffers. */ - memset( &( DMATxDscrTab ), '\0', sizeof( DMATxDscrTab ) ); - /* Since the link is down, clear the descriptors. */ - ETH_Clear_Tx_Descriptors( &( xEthHandle ) ); - } - else - { - /* Something has changed to a Link Status, need re-check. */ - prvEthernetUpdateConfig( pdFALSE ); - } - } - } -} - -/*-----------------------------------------------------------*/ diff --git a/source/portable/NetworkInterface/STM32Hxx/readme.md b/source/portable/NetworkInterface/STM32Hxx/readme.md deleted file mode 100644 index 6ea535633..000000000 --- a/source/portable/NetworkInterface/STM32Hxx/readme.md +++ /dev/null @@ -1,122 +0,0 @@ - -FreeRTOS+TCP driver for STM32H7xx. - -Some STM32 network settings are stored in 'stm32h7xx_hal_conf.h'. - -Number of DMA descriptors, for transmission and for reception. - -The descriptors for transmission are protected with a counting semaphore. -By the time that a packet has been sent, the other TX descriptor becomes -available already. -The number of descriptors has an incluence on the performance. But that also depends on the size -of the TCP buffers and TCP window sizes. - -When ETH_RX_DESC_CNT is too low, the adapter may miss incoming packets, they will be dropped. -When ETH_RX_DESC_CNT is low, sending packets becomes slower. - -Here are settings give a high performance for iperf3: - -~~~ -/* ########################### Ethernet Configuration ######################### */ -#define ETH_TX_DESC_CNT 14U /* number of Ethernet Tx DMA descriptors */ -#define ETH_RX_DESC_CNT 8U /* number of Ethernet Rx DMA descriptors */ -~~~ - -Two more defines that are needed: - -~~~ -#define HAL_ETH_MODULE_ENABLED -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -~~~ - -The following macro's are **not** used by the FreeRTOS driver: - - #define ETH_MAC_ADDR0 ((uint8_t)0x02) - #define ETH_MAC_ADDR1 ((uint8_t)0x00) - ... - -All memory that is shared between the CPU and the DMA ETH peripheral, should be -located in special RAM area called ".ethernet_data". This shall be declared in -the linker file. - -It is possible to use the AXI SRAM for this, but RAM{1,2,3} are also connected -to the Ethernet MAC. - -Here is an example of the changes to the linker file: - - AXI_RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* .ethernet_data declared here. */ - .ethernet_data : - { - PROVIDE_HIDDEN (__ethernet_data_start = .); - KEEP (*(SORT(.ethernet_data.*))) - KEEP (*(.ethernet_data*)) - PROVIDE_HIDDEN (__ethernet_data_end = .); - } >AXI_RAM - -Here is a table of 3 types of STH32H7 : - -|RAM area |H747|H743|H742|Location | -|-----------|----|----|----|----------| -|DTCM |128k|128k|128k|0x20000000| -|AXI-SRAM |511k|511k|384k|0x24000000| -|SRAM1 |128k|128k|32k |0x30000000| -|SRAM2 |128k|128k|16k |0x30020000| -|SRAM3 |32k | 32k| - |0x30040000| -|SRAM4 |64k |64k |64k |0x38000000| -|Backup SRAM|4k |4k |4k |0x38800000| - - -Please make sure that the addresses and lengths are correct for your model of STM32H7xx. -If you use a memory that is not supported, it will result in a DMA errors. - -In FreeRTOSIPConfig.h : - -Define the total number of network buffer descriptors, e.g. 64: - -~~~ - #define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ( 64 ) -~~~ - -It is recommended to use the zero-copy method for both reception and transmission: - -~~~ - #define ipconfigZERO_COPY_RX_DRIVER ( 1 ) - #define ipconfigZERO_COPY_TX_DRIVER ( 1 ) -~~~ - -The copy-method also works well, may just a little slower. - -Checksum cal be calculated in the Ethernet MAC, which is faster than doing manual calculations: - -~~~ - /* The checksums will be checked and calculated by the STM32F4x ETH peripheral. */ - #define ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM ( 1 ) - #define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM ( 1 ) -~~~ - -The most important DMAC registers, along with their names which are used in the reference manual: - - __IO uint32_t DMAMR; // ETH_DMAMR DMA mode register - __IO uint32_t DMAISR; // ETH_DMAISR DMA Interrupt status register - __IO uint32_t DMADSR; // ETH_DMADSR DMA Debug status register - __IO uint32_t DMACCR; // ETH_DMACCR DMA Channel control register - __IO uint32_t DMACTCR; // ETH_DMACTXCR Channel Tx transmit control register - __IO uint32_t DMACRCR; // ETH_DMACRXCR Channel Rx receive control register - __IO uint32_t DMACTDLAR; // ETH_DMACTXDLAR Channel Tx descriptor list address register - __IO uint32_t DMACRDLAR; // ETH_DMACRXDLAR Channel Rx descriptor list address register - __IO uint32_t DMACTDTPR; // ETH_DMACTXDTPR Channel TX tail pointer - __IO uint32_t DMACRDTPR; // ETH_DMACRXDTPR Channel RX tail pointer - __IO uint32_t DMACTDRLR; // ETH_DMACTXRLR Channel Tx descriptor ring length register - __IO uint32_t DMACRDRLR; // ETH_DMACRXRLR Channel Rx descriptor ring length register - __IO uint32_t DMACIER; // ETH_DMACIER Channel interrupt enable register - __IO uint32_t DMACRIWTR; // ETH_DMACRXIWTR Channel Rx interrupt watchdog timer register - __IO uint32_t DMACCATDR; // ETH_DMACCATXDR Channel Tx current application transmit descriptor register - __IO uint32_t DMACCARDR; // ETH_DMACCARXDR Channel Rx current application receive descriptor register - __IO uint32_t DMACCATBR; // ETH_DMACCATXBR Channel Tx current application transmit buffer register - __IO uint32_t DMACCARBR; // ETH_DMACCARXBR Channel Rx current application receive buffer register - __IO uint32_t DMACSR; // ETH_DMACSR Channel status register - - -As most EMAC's, the STM32H7 EMAC is able to put packets in multiple linked DMA segments. -FreeRTOS+TCP never uses this feature. Each packet is stored in a single buffer called -`NetworkBufferDescriptor_t`. diff --git a/source/portable/NetworkInterface/STM32Hxx/stm32h7xx_hal_eth.h b/source/portable/NetworkInterface/STM32Hxx/stm32h7xx_hal_eth.h deleted file mode 100644 index 0a0002c42..000000000 --- a/source/portable/NetworkInterface/STM32Hxx/stm32h7xx_hal_eth.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to - * a single module that works for both parts: "stm32hxx_hal_eth" - */ - -#include "stm32hxx_hal_eth.h" diff --git a/source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.c b/source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.c deleted file mode 100644 index 0a44278bb..000000000 --- a/source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.c +++ /dev/null @@ -1,2983 +0,0 @@ -/** - ****************************************************************************** - * @file stm32hxx_hal_eth.c - * @author MCD Application Team - * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and deinitialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * @verbatim - * ============================================================================== - ##### How to use this driver ##### - #####============================================================================== - #####[..] - #####The ETH HAL driver can be used as follows: - ##### - #####(#)Declare a ETH_HandleTypeDef handle structure, for example: - ##### ETH_HandleTypeDef heth; - ##### - #####(#)Fill parameters of Init structure in heth handle - ##### - #####(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) - ##### - #####(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - ##### (##) Enable the Ethernet interface clock using - ##### (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE() - ##### (+++) __HAL_RCC_ETH1TX_CLK_ENABLE() - ##### (+++) __HAL_RCC_ETH1RX_CLK_ENABLE() - ##### - ##### (##) Initialize the related GPIO clocks - ##### (##) Configure Ethernet pinout - ##### (##) Configure Ethernet NVIC interrupt (in Interrupt mode) - ##### - #####(#) Ethernet data reception is asynchronous, so call the following API - ##### to start the listening mode: - ##### (##) HAL_ETH_Start(): - ##### This API starts the MAC and DMA transmission and reception process, - ##### without enabling end of transfer interrupts, in this mode user - ##### has to poll for data availability by calling HAL_ETH_IsRxDataAvailable() - ##### (##) HAL_ETH_Start_IT(): - ##### This API starts the MAC and DMA transmission and reception process, - ##### end of transfer interrupts are enabled in this mode, - ##### HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received - ##### - #####(#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt - ##### occurred), user can call the following APIs to get received data: - ##### (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame - ##### (##) HAL_ETH_GetRxDataLength(): Get received frame length - ##### (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info, - ##### please refer to ETH_RxPacketInfo typedef structure - ##### - #####(#) For transmission path, two APIs are available: - ##### (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode - ##### (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode, - ##### HAL_ETH_TxCpltCallback() will be executed when end of transfer occur - ##### - #####(#) Communication with an external PHY device: - ##### (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY - ##### (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register - ##### - #####(#) Configure the Ethernet MAC after ETH peripheral initialization - ##### (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef - ##### (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef - ##### - #####(#) Configure the Ethernet DMA after ETH peripheral initialization - ##### (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef - ##### (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef - ##### - #####-@- The PTP protocol offload APIs are not supported in this driver. - ##### - *** Callback registration *** - ***============================================= - *** - ***The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 - ***allows the user to configure dynamically the driver callbacks. - ***Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback. - *** - ***Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks: - ***(+) TxCpltCallback : Tx Complete Callback. - ***(+) RxCpltCallback : Rx Complete Callback. - ***(+) DMAErrorCallback : DMA Error Callback. - ***(+) MACErrorCallback : MAC Error Callback. - ***(+) PMTCallback : Power Management Callback - ***(+) EEECallback : EEE Callback. - ***(+) WakeUpCallback : Wake UP Callback - ***(+) MspInitCallback : MspInit Callback. - ***(+) MspDeInitCallback: MspDeInit Callback. - *** - ***This function takes as parameters the HAL peripheral handle, the Callback ID - ***and a pointer to the user callback function. - *** - ***Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default - ***weak function. - ***@ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, - ***and the Callback ID. - ***This function allows to reset following callbacks: - ***(+) TxCpltCallback : Tx Complete Callback. - ***(+) RxCpltCallback : Rx Complete Callback. - ***(+) DMAErrorCallback : DMA Error Callback. - ***(+) MACErrorCallback : MAC Error Callback. - ***(+) PMTCallback : Power Management Callback - ***(+) EEECallback : EEE Callback. - ***(+) WakeUpCallback : Wake UP Callback - ***(+) MspInitCallback : MspInit Callback. - ***(+) MspDeInitCallback: MspDeInit Callback. - *** - ***By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET - ***all callbacks are set to the corresponding weak functions: - ***examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback(). - ***Exception done for MspInit and MspDeInit functions that are - ***reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when - ***these callbacks are null (not registered beforehand). - ***if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit - ***keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - *** - ***Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. - ***Exception done MspInit/MspDeInit that can be registered/unregistered - ***in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, - ***thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - ***In that case first register the MspInit/MspDeInit user callbacks - ***using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit - ***or HAL_ETH_Init function. - *** - ***When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or - ***not defined, the callback registration feature is not available and all callbacks - ***are set to the corresponding weak functions. - *** - ***@endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* - * The contents of the files stm32hxx_hal_eth.{c,h} is based on the ETH HAL driver - * stm32h7xx_hal_eth.{c,h} as provided by ST Electronics. - * It is slightly adapted for the needs of FreeRTOS+TCP. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -#include "stm32h7xx_hal.h" - -#include "FreeRTOS_IP.h" -#include "NetworkBufferManagement.h" -#include "FreeRTOS_IP_Private.h" - -#ifndef ARRAY_SIZE - #define ARRAY_SIZE( x ) ( ( BaseType_t ) ( sizeof( x ) / sizeof( ( x )[ 0 ] ) ) ) -#endif - -/* A semaphore that indicates the number of freeTX DMA descriptors. */ -extern SemaphoreHandle_t xTXDescriptorSemaphore; - -/** @addtogroup STM32H7xx_HAL_Driver - * @{ - */ -#ifdef HAL_ETH_MODULE_ENABLED - - static void set_error_state( ETH_HandleTypeDef * heth, - uint32_t ulState ) - { - heth->gState = ulState; - } - - #if defined( ETH ) - -/** @defgroup ETH ETH - * @brief ETH HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @addtogroup ETH_Private_Constants ETH Private Constants - * @{ - */ - #define ETH_MACCR_MASK ( ( uint32_t ) 0xFFFB7F7CU ) - #define ETH_MACECR_MASK ( ( uint32_t ) 0x3F077FFFU ) - #define ETH_MACPFR_MASK ( ( uint32_t ) 0x800007FFU ) - #define ETH_MACWTR_MASK ( ( uint32_t ) 0x0000010FU ) - #define ETH_MACTFCR_MASK ( ( uint32_t ) 0xFFFF00F2U ) - #define ETH_MACRFCR_MASK ( ( uint32_t ) 0x00000003U ) - #define ETH_MTLTQOMR_MASK ( ( uint32_t ) 0x00000072U ) - #define ETH_MTLRQOMR_MASK ( ( uint32_t ) 0x0000007BU ) - - #define ETH_DMAMR_MASK ( ( uint32_t ) 0x00007802U ) - #define ETH_DMASBMR_MASK ( ( uint32_t ) 0x0000D001U ) - #define ETH_DMACCR_MASK ( ( uint32_t ) 0x00013FFFU ) - #define ETH_DMACTCR_MASK ( ( uint32_t ) 0x003F1010U ) - #define ETH_DMACRCR_MASK ( ( uint32_t ) 0x803F0000U ) - #define ETH_MACPCSR_MASK \ - ( ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \ - ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \ - ETH_MACPCSR_RWKPFE ) - -/* Timeout values */ - #define ETH_SWRESET_TIMEOUT ( ( uint32_t ) 500U ) - #define ETH_MDIO_BUS_TIMEOUT ( ( uint32_t ) 1000U ) - - #define ETH_DMARXNDESCWBF_ERRORS_MASK \ - ( ( uint32_t ) ( ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \ - ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT | \ - ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE ) ) - - #define ETH_MAC_US_TICK ( ( uint32_t ) 1000000U ) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup ETH_Private_Macros ETH Private Macros - * @{ - */ -/* Helper macros for TX descriptor handling */ - #define INCR_TX_DESC_INDEX( inx, offset ) \ - do { \ - ( inx ) += ( offset ); \ - if( ( inx ) >= ( uint32_t ) ETH_TX_DESC_CNT ) { \ - ( inx ) = ( ( inx ) - ( uint32_t ) ETH_TX_DESC_CNT ); } \ - } while( 0 ) - -/* Helper macros for RX descriptor handling */ - #define INCR_RX_DESC_INDEX( inx, offset ) \ - do { \ - ( inx ) += ( offset ); \ - if( ( inx ) >= ( uint32_t ) ETH_RX_DESC_CNT ) { \ - ( inx ) = ( ( inx ) - ( uint32_t ) ETH_RX_DESC_CNT ); } \ - } while( 0 ) - -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup ETH_Private_Functions ETH Private Functions - * @{ - */ - static void ETH_MAC_MDIO_ClkConfig( ETH_HandleTypeDef * heth ); - static void ETH_SetMACConfig( ETH_HandleTypeDef * heth, - ETH_MACConfigTypeDef * macconf ); - static void ETH_SetDMAConfig( ETH_HandleTypeDef * heth, - ETH_DMAConfigTypeDef * dmaconf ); - static void ETH_MACDMAConfig( ETH_HandleTypeDef * heth ); - static void ETH_DMATxDescListInit( ETH_HandleTypeDef * heth ); - static void ETH_DMARxDescListInit( ETH_HandleTypeDef * heth ); - static uint32_t ETH_Prepare_Tx_Descriptors( ETH_HandleTypeDef * heth, - ETH_TxPacketConfig * pTxConfig, - uint32_t ItMode ); - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - static void ETH_InitCallbacksToDefault( ETH_HandleTypeDef * heth ); - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup ETH_Exported_Functions ETH Exported Functions - * @{ - */ - -/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions - * @brief Initialization and Configuration functions - * - * @verbatim - * =============================================================================== - ##### Initialization and Configuration functions ##### - #####=============================================================================== - #####[..] This subsection provides a set of functions allowing to initialize and - ##### deinitialize the ETH peripheral: - ##### - #####(+) User must Implement HAL_ETH_MspInit() function in which he configures - ##### all related peripherals resources (CLOCK, GPIO and NVIC ). - ##### - #####(+) Call the function HAL_ETH_Init() to configure the selected device with - ##### the selected configuration: - ##### (++) MAC address - ##### (++) Media interface (MII or RMII) - ##### (++) Rx DMA Descriptors Tab - ##### (++) Tx DMA Descriptors Tab - ##### (++) Length of Rx Buffers - ##### - #####(+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers - ##### for each Rx DMA Descriptor - ##### - #####(+) Call the function HAL_ETH_DeInit() to restore the default configuration - ##### of the selected ETH peripheral. - ##### - #####@endverbatim - * @{ - */ - -/** - * @brief Initialize the Ethernet peripheral registers. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef * heth ) - { - uint32_t tickstart; - - if( heth == NULL ) - { - return HAL_ERROR; - } - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - if( heth->gState == HAL_ETH_STATE_RESET ) - { - /* Allocate lock resource and initialize it */ - heth->Lock = HAL_UNLOCKED; - - ETH_InitCallbacksToDefault( heth ); - - if( heth->MspInitCallback == NULL ) - { - heth->MspInitCallback = HAL_ETH_MspInit; - } - - /* Init the low level hardware */ - heth->MspInitCallback( heth ); - } - #else /* if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) */ - /* Check the ETH peripheral state */ - if( heth->gState == HAL_ETH_STATE_RESET ) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspInit( heth ); - } - #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ - - heth->gState = HAL_ETH_STATE_BUSY; - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - if( heth->Init.MediaInterface == HAL_ETH_MII_MODE ) - { - HAL_SYSCFG_ETHInterfaceSelect( SYSCFG_ETH_MII ); - } - else - { - HAL_SYSCFG_ETHInterfaceSelect( SYSCFG_ETH_RMII ); - } - - /* Ethernet Software reset */ - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - SET_BIT( heth->Instance->DMAMR, ETH_DMAMR_SWR ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for software reset */ - while( READ_BIT( heth->Instance->DMAMR, ETH_DMAMR_SWR ) > 0U ) - { - if( ( ( HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT ) ) - { - /* Set Error Code */ - heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; - /* Set State as Error */ - set_error_state( heth, HAL_ETH_STATE_ERROR ); - /* Return Error */ - return HAL_ERROR; - } - } - - /*------------------ MDIO CSR Clock Range Configuration --------------------*/ - ETH_MAC_MDIO_ClkConfig( heth ); - - /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/ - WRITE_REG( heth->Instance->MAC1USTCR, ( ( ( uint32_t ) HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK ) - 1U ) ); - - /*------------------ MAC, MTL and DMA default Configuration ----------------*/ - ETH_MACDMAConfig( heth ); - - /* SET DSL to 64 bit */ - MODIFY_REG( heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT ); - - /* Set Receive Buffers Length (must be a multiple of 4) */ - if( ( heth->Init.RxBuffLen % 0x4U ) != 0x0U ) - { - /* Set Error Code */ - heth->ErrorCode = HAL_ETH_ERROR_PARAM; - /* Set State as Error */ - set_error_state( heth, HAL_ETH_STATE_ERROR ); - /* Return Error */ - return HAL_ERROR; - } - else - { - MODIFY_REG( heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ( ( heth->Init.RxBuffLen ) << 1 ) ); - } - - /*------------------ DMA Tx Descriptors Configuration ----------------------*/ - ETH_DMATxDescListInit( heth ); - - /*------------------ DMA Rx Descriptors Configuration ----------------------*/ - ETH_DMARxDescListInit( heth ); - - /*--------------------- ETHERNET MAC Address Configuration ------------------*/ - /* Set MAC addr bits 32 to 47 */ - heth->Instance->MACA0HR = ( ( ( uint32_t ) ( heth->Init.MACAddr[ 5 ] ) << 8 ) | ( uint32_t ) heth->Init.MACAddr[ 4 ] ); - /* Set MAC addr bits 0 to 31 */ - heth->Instance->MACA0LR = ( ( ( uint32_t ) ( heth->Init.MACAddr[ 3 ] ) << 24 ) | ( ( uint32_t ) ( heth->Init.MACAddr[ 2 ] ) << 16 ) | - ( ( uint32_t ) ( heth->Init.MACAddr[ 1 ] ) << 8 ) | ( uint32_t ) heth->Init.MACAddr[ 0 ] ); - - heth->ErrorCode = HAL_ETH_ERROR_NONE; - heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_READY; - - /* - * Disable the interrupts that are related to the MMC counters. - * These interrupts are enabled by default. The interrupt can - * only be acknowledged by reading the corresponding counter. - */ - - heth->Instance->MMCRIMR = - ETH_MMCRIMR_RXLPITRCIM | /* RXLPITRC */ - ETH_MMCRIMR_RXLPIUSCIM | /* RXLPIUSC */ - ETH_MMCRIMR_RXUCGPIM | /* RXUCASTG */ - ETH_MMCRIMR_RXALGNERPIM | /* RXALGNERR */ - ETH_MMCRIMR_RXCRCERPIM; /* RXCRCERR */ - - heth->Instance->MMCTIMR = - ETH_MMCTIMR_TXLPITRCIM | /* TXLPITRC */ - ETH_MMCTIMR_TXLPIUSCIM | /* TXLPIUSC */ - ETH_MMCTIMR_TXGPKTIM | /* TXPKTG */ - ETH_MMCTIMR_TXMCOLGPIM | /* TXMULTCOLG */ - ETH_MMCTIMR_TXSCOLGPIM; /* TXSNGLCOLG */ - - return HAL_OK; - } - -/*/ ** */ -/** @brief DeInitializes the ETH peripheral. */ -/** @param heth: pointer to a ETH_HandleTypeDef structure that contains */ -/** the configuration information for ETHERNET module */ -/** @retval HAL status */ -/** / */ -/*HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) */ -/*{ */ -/*/ * Set the ETH peripheral state to BUSY * / */ -/*heth->gState = HAL_ETH_STATE_BUSY; */ -/* */ -/*#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) */ -/* */ -/*if(heth->MspDeInitCallback == NULL) */ -/*{ */ -/*heth->MspDeInitCallback = HAL_ETH_MspDeInit; */ -/*} */ -/*/ * DeInit the low level hardware * / */ -/*heth->MspDeInitCallback(heth); */ -/*#else */ -/* */ -/*/ * De-Init the low level hardware : GPIO, CLOCK, NVIC. * / */ -/*HAL_ETH_MspDeInit(heth); */ -/* */ -/*#endif / * (USE_HAL_ETH_REGISTER_CALLBACKS) * / */ -/* */ -/*/ * Set ETH HAL state to Disabled * / */ -/*heth->gState= HAL_ETH_STATE_RESET; */ -/* */ -/*/ * Return function status * / */ -/*return HAL_OK; */ -/*} */ - -/** - * @brief Initializes the ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_MspInit( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_MspInit could be implemented in the user file - */ - } - -/** - * @brief DeInitializes ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_MspDeInit( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_MspDeInit could be implemented in the user file - */ - } - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - -/** - * @brief Register a User ETH Callback - * To be used instead of the weak predefined callback - * @param heth eth handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID - * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID - * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID - * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID - * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID - * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ - HAL_StatusTypeDef HAL_ETH_RegisterCallback( ETH_HandleTypeDef * heth, - HAL_ETH_CallbackIDTypeDef CallbackID, - pETH_CallbackTypeDef pCallback ) - { - HAL_StatusTypeDef status = HAL_OK; - - if( pCallback == NULL ) - { - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK( heth ); - - if( heth->gState == HAL_ETH_STATE_READY ) - { - switch( CallbackID ) - { - case HAL_ETH_TX_COMPLETE_CB_ID: - heth->TxCpltCallback = pCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID: - heth->RxCpltCallback = pCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID: - heth->DMAErrorCallback = pCallback; - break; - - case HAL_ETH_MAC_ERROR_CB_ID: - heth->MACErrorCallback = pCallback; - break; - - case HAL_ETH_PMT_CB_ID: - heth->PMTCallback = pCallback; - break; - - case HAL_ETH_EEE_CB_ID: - heth->EEECallback = pCallback; - break; - - case HAL_ETH_WAKEUP_CB_ID: - heth->WakeUpCallback = pCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID: - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID: - heth->MspDeInitCallback = pCallback; - break; - - default: - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if( heth->gState == HAL_ETH_STATE_RESET ) - { - switch( CallbackID ) - { - case HAL_ETH_MSPINIT_CB_ID: - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID: - heth->MspDeInitCallback = pCallback; - break; - - default: - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK( heth ); - - return status; - } - -/** - * @brief Unregister an ETH Callback - * ETH callabck is redirected to the weak predefined callback - * @param heth eth handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID - * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID - * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID - * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID - * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID - * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval status - */ - HAL_StatusTypeDef HAL_ETH_UnRegisterCallback( ETH_HandleTypeDef * heth, - HAL_ETH_CallbackIDTypeDef CallbackID ) - { - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK( heth ); - - if( heth->gState == HAL_ETH_STATE_READY ) - { - switch( CallbackID ) - { - case HAL_ETH_TX_COMPLETE_CB_ID: - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID: - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID: - heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; - break; - - case HAL_ETH_MAC_ERROR_CB_ID: - heth->MACErrorCallback = HAL_ETH_MACErrorCallback; - break; - - case HAL_ETH_PMT_CB_ID: - heth->PMTCallback = HAL_ETH_PMTCallback; - break; - - case HAL_ETH_EEE_CB_ID: - heth->EEECallback = HAL_ETH_EEECallback; - break; - - case HAL_ETH_WAKEUP_CB_ID: - heth->WakeUpCallback = HAL_ETH_WakeUpCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID: - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID: - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default: - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if( heth->gState == HAL_ETH_STATE_RESET ) - { - switch( CallbackID ) - { - case HAL_ETH_MSPINIT_CB_ID: - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID: - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default: - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK( heth ); - - return status; - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @brief Assign memory buffers to a DMA Rx descriptor - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param Index : index of the DMA Rx descriptor - * this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1) - * @param pBuffer1: address of buffer 1 - * @param pBuffer2: address of buffer 2 if available - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_DescAssignMemory( ETH_HandleTypeDef * heth, - uint32_t Index, - uint8_t * pBuffer1, - uint8_t * pBuffer2 ) - { - ETH_DMADescTypeDef * dmarxdesc = ( ETH_DMADescTypeDef * ) heth->RxDescList.RxDesc[ Index ]; - - if( ( pBuffer1 == NULL ) || ( Index >= ( uint32_t ) ETH_RX_DESC_CNT ) ) - { - /* Set Error Code */ - heth->ErrorCode = HAL_ETH_ERROR_PARAM; - /* Return Error */ - return HAL_ERROR; - } - - /* write buffer address to RDES0 */ - WRITE_REG( dmarxdesc->DESC0, ( uint32_t ) pBuffer1 ); - /* store buffer address */ - WRITE_REG( dmarxdesc->BackupAddr0, ( uint32_t ) pBuffer1 ); - /* set buffer address valid bit to RDES3 */ - SET_BIT( dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V ); - -/* Not used for FreeRTOS+TCP */ -/* if(pBuffer2 != NULL) */ -/* { */ -/* / * write buffer 2 address to RDES1 * / */ -/* WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2); */ -/* / * store buffer 2 address * / */ -/* WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2); */ -/* / * set buffer 2 address valid bit to RDES3 * / */ -/* SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V); */ -/* } */ - - /* set OWN bit to RDES3 */ - SET_BIT( dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN ); - ( void ) dmarxdesc->DESC3; - - return HAL_OK; - } - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief ETH Transmit and Receive functions - * - * @verbatim - * ============================================================================== - ##### IO operation functions ##### - #####============================================================================== - #####[..] - #####This subsection provides a set of functions allowing to manage the ETH - #####data transfer. - ##### - #####@endverbatim - * @{ - */ - -/** - * @brief Enables Ethernet MAC and DMA reception and transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef * heth ) - { - if( heth->gState == HAL_ETH_STATE_READY ) - { - heth->gState = HAL_ETH_STATE_BUSY; - - /* Enable the MAC transmission */ - SET_BIT( heth->Instance->MACCR, ETH_MACCR_TE ); - - /* Enable the MAC reception */ - SET_BIT( heth->Instance->MACCR, ETH_MACCR_RE ); - - /* Set the Flush Transmit FIFO bit */ - SET_BIT( heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ ); - - /* Enable the DMA transmission */ - SET_BIT( heth->Instance->DMACTCR, ETH_DMACTCR_ST ); - - /* Enable the DMA reception */ - SET_BIT( heth->Instance->DMACRCR, ETH_DMACRCR_SR ); - - /* Clear Tx and Rx process stopped flags */ - heth->Instance->DMACSR |= ( ETH_DMACSR_TPS | ETH_DMACSR_RPS ); - - heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_BUSY_RX; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Start_IT( ETH_HandleTypeDef * heth ) - { - uint32_t desc_index; - - if( heth->gState == HAL_ETH_STATE_READY ) - { - heth->gState = HAL_ETH_STATE_BUSY; - - /* Set IOC bit (Interrupt Enabled on Completion) to all Rx descriptors */ - for( desc_index = 0; desc_index < ( uint32_t ) ETH_RX_DESC_CNT; desc_index++ ) - { - ETH_DMADescTypeDef * dma_rx_desc; - - dma_rx_desc = ( ETH_DMADescTypeDef * ) heth->RxDescList.RxDesc[ desc_index ]; - SET_BIT( dma_rx_desc->DESC3, ETH_DMARXNDESCRF_IOC ); - } - - /* save IT mode to ETH Handle */ - heth->RxDescList.ItMode = 1U; - - /* Enable the MAC transmission */ - SET_BIT( heth->Instance->MACCR, ETH_MACCR_TE ); - - /* Enable the MAC reception */ - SET_BIT( heth->Instance->MACCR, ETH_MACCR_RE ); - - /* Set the Flush Transmit FIFO bit */ - SET_BIT( heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ ); - - /* Enable the DMA transmission */ - SET_BIT( heth->Instance->DMACTCR, ETH_DMACTCR_ST ); - - /* Enable the DMA reception */ - SET_BIT( heth->Instance->DMACRCR, ETH_DMACRCR_SR ); - - /* Clear Tx and Rx process stopped flags */ - heth->Instance->DMACSR |= ( ETH_DMACSR_TPS | ETH_DMACSR_RPS ); - - /* Enable ETH DMA interrupts: - * - Tx complete interrupt - * - Rx complete interrupt - * - Fatal bus interrupt - */ - __HAL_ETH_DMA_ENABLE_IT( heth, - ETH_DMACIER_NIE | /* Normal Interrupt Summary Enable */ - ETH_DMACIER_RIE | /* Receive Interrupt Enable */ - ETH_DMACIER_TIE | /* Transmit Interrupt Enable */ - ETH_DMACIER_FBEE | /* Fatal Bus Error Enable */ - ETH_DMACIER_AIE ); /* Abnormal Interrupt Summary Enable */ - - heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_BUSY_RX; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Stop( ETH_HandleTypeDef * heth ) - { - if( heth->gState != HAL_ETH_STATE_RESET ) - { - /* Set the ETH peripheral state to BUSY */ - heth->gState = HAL_ETH_STATE_BUSY; - - /* Disable the DMA transmission */ - CLEAR_BIT( heth->Instance->DMACTCR, ETH_DMACTCR_ST ); - - /* Disable the DMA reception */ - CLEAR_BIT( heth->Instance->DMACRCR, ETH_DMACRCR_SR ); - - /* Disable the MAC reception */ - CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE ); - - /* Set the Flush Transmit FIFO bit */ - SET_BIT( heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ ); - - /* Disable the MAC transmission */ - CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_TE ); - - heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Stop_IT( ETH_HandleTypeDef * heth ) - { - ETH_DMADescTypeDef * dmarxdesc; - uint32_t descindex; - - if( heth->gState != HAL_ETH_STATE_RESET ) - { - /* Set the ETH peripheral state to BUSY */ - heth->gState = HAL_ETH_STATE_BUSY; - - /* Disable intrrupts: - * - Tx complete interrupt - * - Rx complete interrupt - * - Fatal bus interrupt - */ - __HAL_ETH_DMA_DISABLE_IT( heth, ( ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | - ETH_DMACIER_FBEE | ETH_DMACIER_AIE ) ); - - /* Disable the DMA transmission */ - CLEAR_BIT( heth->Instance->DMACTCR, ETH_DMACTCR_ST ); - - /* Disable the DMA reception */ - CLEAR_BIT( heth->Instance->DMACRCR, ETH_DMACRCR_SR ); - - /* Disable the MAC reception */ - CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE ); - - /* Set the Flush Transmit FIFO bit */ - SET_BIT( heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ ); - - /* Disable the MAC transmission */ - CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_TE ); - - /* Clear IOC bit (Interrupt Enabled on Completion) to all Rx descriptors */ - for( descindex = 0; descindex < ( uint32_t ) ETH_RX_DESC_CNT; descindex++ ) - { - dmarxdesc = ( ETH_DMADescTypeDef * ) heth->RxDescList.RxDesc[ descindex ]; - CLEAR_BIT( dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC ); - } - - heth->RxDescList.ItMode = 0U; - - heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Sends an Ethernet Packet in polling mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pTxConfig: Hold the configuration of packet to be transmitted - * @param Timeout: timeout value - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Transmit( ETH_HandleTypeDef * heth, - ETH_TxPacketConfig * pTxConfig, - uint32_t Timeout ) - { - uint32_t tickstart; - const ETH_DMADescTypeDef * dmatxdesc; - - if( pTxConfig == NULL ) - { - heth->ErrorCode |= HAL_ETH_ERROR_PARAM; - return HAL_ERROR; - } - - if( heth->gState == HAL_ETH_STATE_READY ) - { - /* Config DMA Tx descriptor by Tx Packet info */ - if( ETH_Prepare_Tx_Descriptors( heth, pTxConfig, 0 ) != HAL_ETH_ERROR_NONE ) - { - /* Set the ETH error code */ - heth->ErrorCode |= HAL_ETH_ERROR_BUSY; - return HAL_ERROR; - } - - dmatxdesc = ( ETH_DMADescTypeDef * ) ( &heth->TxDescList )->TxDesc[ heth->TxDescList.CurTxDesc ]; - - /* Incr current tx desc index */ - INCR_TX_DESC_INDEX( heth->TxDescList.CurTxDesc, 1U ); - - /* Start transmission */ - /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ - WRITE_REG( heth->Instance->DMACTDTPR, ( uint32_t ) ( heth->TxDescList.TxDesc[ heth->TxDescList.CurTxDesc ] ) ); - - READ_REG( heth->Instance->DMACTDTPR ); - - tickstart = HAL_GetTick(); - - /* Wait for data to be transmitted or timeout occured */ - while( ( dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN ) != ( uint32_t ) RESET ) - { - if( ( heth->Instance->DMACSR & ETH_DMACSR_FBE ) != ( uint32_t ) RESET ) - { - heth->ErrorCode |= HAL_ETH_ERROR_DMA; - heth->DMAErrorCode = heth->Instance->DMACSR; - /* Set ETH HAL State to Ready */ - set_error_state( heth, HAL_ETH_STATE_ERROR ); - /* Return function status */ - return HAL_ERROR; - } - - /* Check for the Timeout */ - if( Timeout != HAL_MAX_DELAY ) - { - if( ( ( HAL_GetTick() - tickstart ) > Timeout ) || ( Timeout == 0U ) ) - { - heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; - set_error_state( heth, HAL_ETH_STATE_ERROR ); - return HAL_ERROR; - } - } - } - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Sends an Ethernet Packet in interrupt mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pTxConfig: Hold the configuration of packet to be transmitted - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_Transmit_IT( ETH_HandleTypeDef * heth, - ETH_TxPacketConfig * pTxConfig ) - { - if( pTxConfig == NULL ) - { - heth->ErrorCode |= HAL_ETH_ERROR_PARAM; - return HAL_ERROR; - } - - if( heth->gState == HAL_ETH_STATE_READY ) - { - /* Config DMA Tx descriptor by Tx Packet info */ - if( ETH_Prepare_Tx_Descriptors( heth, pTxConfig, 1 ) != HAL_ETH_ERROR_NONE ) - { - heth->ErrorCode |= HAL_ETH_ERROR_BUSY; - return HAL_ERROR; - } - - /* Incr current tx desc index */ - INCR_TX_DESC_INDEX( heth->TxDescList.CurTxDesc, 1U ); - - /* - * Start transmission. - * issue a poll command to Tx DMA by writing address of next immediate free descriptor. - * DMACTDTPR: "Channel Tx descriptor tail pointer register (ETH_DMACTXDTPR) - * The hardware tries to transmit all packets referenced by the - * descriptors between the head and the tail pointer registers. - */ - - WRITE_REG( heth->Instance->DMACTDTPR, ( uint32_t ) ( heth->TxDescList.TxDesc[ heth->TxDescList.CurTxDesc ] ) ); - /* Memory barrier. */ - __DSB(); - /* Read-back the value just written. */ - ( void ) heth->Instance->DMACTDTPR; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Checks for received Packets. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval 1: A Packet is received - * 0: no Packet received - */ - uint8_t HAL_ETH_IsRxDataAvailable( ETH_HandleTypeDef * heth ) - { - ETH_RxDescListTypeDef * dmarxdesclist = &heth->RxDescList; - uint32_t desc_index = dmarxdesclist->CurRxDesc; - ETH_DMADescTypeDef * dmarxdesc = ( ETH_DMADescTypeDef * ) dmarxdesclist->RxDesc[ desc_index ]; - uint32_t desc_scan_count = 0; - uint32_t app_desc_count = 0; /* Number of descriptors in received packet. */ - uint32_t first_app_desc_index = 0; /* Index of the first descriptor of received packet.. */ - - /* Check if descriptor is not owned by DMA */ - while( ( READ_BIT( dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN ) == ( uint32_t ) RESET ) && - ( desc_scan_count < ( uint32_t ) ETH_RX_DESC_CNT ) ) - { - uint32_t ulDesc3 = dmarxdesc->DESC3; - desc_scan_count++; - - /* FreeRTOS+TCP only handles packets that fit in 1 descriptor. */ - configASSERT( ( ( ulDesc3 & ETH_DMATXNDESCWBF_FD ) != 0U ) && ( ( ulDesc3 & ETH_DMATXNDESCWBF_LD ) != 0U ) ); - - /* Check if last descriptor */ - if( READ_BIT( ulDesc3, ETH_DMARXNDESCWBF_LD ) != ( uint32_t ) RESET ) - { - /* Increment the number of descriptors to be passed to the application */ - app_desc_count += 1U; - - if( app_desc_count == 1U ) - { - first_app_desc_index = desc_index; - } - - /* Increment current rx descriptor index */ - INCR_RX_DESC_INDEX( desc_index, 1U ); - - /* Check for Context descriptor */ - /* Get current descriptor address */ - dmarxdesc = ( ETH_DMADescTypeDef * ) dmarxdesclist->RxDesc[ desc_index ]; - - if( READ_BIT( dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN ) == ( uint32_t ) RESET ) - { - /* If IEEE 1588 timestamp feature is enabled, the DMA stores the timestamp - * (if available). The DMA writes the context descriptor after the last - * descriptor for the current packet (in the next available descriptor). */ - if( READ_BIT( dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT ) != ( uint32_t ) RESET ) - { - /* Increment the number of descriptors to be passed to the application */ - dmarxdesclist->AppContextDesc = 1; - /* Increment current rx descriptor index */ - INCR_RX_DESC_INDEX( desc_index, 1U ); - } - } - - /* Fill information to Rx descriptors list */ - dmarxdesclist->CurRxDesc = desc_index; - dmarxdesclist->FirstAppDesc = first_app_desc_index; - dmarxdesclist->AppDescNbr = app_desc_count; - - /* Return function status */ - return 1; - } - -/* / * Check if first descriptor * / */ -/* else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) */ -/* { */ -/*configASSERT( 1 == 0 ); */ -/* first_app_desc_index = desc_index; */ -/* / * Increment the number of descriptors to be passed to the application * / */ -/* app_desc_count = 1U; */ -/* */ -/* / * Increment current rx descriptor index * / */ -/* INCR_RX_DESC_INDEX(desc_index, 1U); */ -/* / * Get current descriptor address * / */ -/* dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[desc_index]; */ -/* } */ -/* / * It should be an intermediate descriptor * / */ -/* else */ -/* { */ -/*configASSERT( 1 == 0 ); */ -/* / * Increment the number of descriptors to be passed to the application * / */ -/* app_desc_count += 1U; */ -/* */ -/* / * Increment current rx descriptor index * / */ -/* INCR_RX_DESC_INDEX(desc_index, 1U); */ -/* / * Get current descriptor address * / */ -/* dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[desc_index]; */ -/* } */ - } /* while ( OWN == 0 ) */ - - configASSERT( app_desc_count == 0 ); - -/* / * Build Descriptors if an incomplete Packet is received * / */ -/* if(app_desc_count > 0U) */ -/* { */ -/* dmarxdesclist->CurRxDesc = desc_index; */ -/* dmarxdesclist->FirstAppDesc = first_app_desc_index; */ -/* desc_index = first_app_desc_index; */ -/* dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[desc_index]; */ -/* */ -/* for(desc_scan_count = 0; ipTRUE_BOOL; desc_scan_count++) */ -/* { */ -/* WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0); */ -/* WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V); */ -/* */ -/* if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET)) */ -/* { */ -/* WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1); */ -/* SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V); */ -/* } */ -/* */ -/* SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN); */ -/* */ -/* if(dmarxdesclist->ItMode != ((uint32_t)RESET)) */ -/* { */ -/* SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); */ -/* } */ -/* if(desc_scan_count >= (app_desc_count - 1U)) */ -/* { */ -/* break; */ -/* } */ -/* / * Increment rx descriptor index * / */ -/* INCR_RX_DESC_INDEX(desc_index, 1U); */ -/* / * Get descriptor address * / */ -/* dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[desc_index]; */ -/* } */ -/* */ -/* / * Set the Tail pointer address to the last rx descriptor hold by the app * / */ -/* WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc); */ -/* } */ - - /* Fill information to Rx descriptors list: No received Packet */ - dmarxdesclist->AppDescNbr = 0U; - - return 0; - } - -/** - * @brief This function gets the buffer address of last received Packet. - * @note Please insure to allocate the RxBuffer structure before calling this function - * how to use example: - * HAL_ETH_GetRxDataLength(heth, &Length); - * BuffersNbr = (Length / heth->Init.RxBuffLen) + 1; - * RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef)); - * HAL_ETH_GetRxDataBuffer(heth, RxBuffer); - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param RxBuffer: Pointer to a ETH_BufferTypeDef structure - * @retval HAL status - */ - size_t HAL_ETH_GetRxData( ETH_HandleTypeDef * heth, - ETH_BufferTypeDef * RxBuffer ) - { - ETH_RxDescListTypeDef * dmarxdesclist = &( heth->RxDescList ); - uint32_t desc_index; - uint32_t packet_length; - __IO const ETH_DMADescTypeDef * dma_rx_desc; - - configASSERT( RxBuffer != NULL ); - - if( HAL_ETH_IsRxDataAvailable( heth ) == 0U ) - { - /* No data to be transferred to the application */ - return 0U; - } - - desc_index = dmarxdesclist->FirstAppDesc; - dma_rx_desc = ( ETH_DMADescTypeDef * ) dmarxdesclist->RxDesc[ desc_index ]; - - configASSERT( dmarxdesclist->AppDescNbr == 1 ); - - /* last descriptor data length */ - packet_length = READ_BIT( dma_rx_desc->DESC3, ETH_DMARXNDESCWBF_PL ); - - RxBuffer->buffer = ( uint8_t * ) dma_rx_desc->BackupAddr0; - RxBuffer->len = packet_length; - - /* data is in only one buffer */ - configASSERT( packet_length <= heth->Init.RxBuffLen ); - - return packet_length; - } - -/*/ ** */ -/* * @brief This function gets the length of last received Packet. */ -/* * @param heth: pointer to a ETH_HandleTypeDef structure that contains */ -/* * the configuration information for ETHERNET module */ -/* * @param Length: parameter to hold Rx packet length */ -/* * @retval HAL Status */ -/* * / */ -/*HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length) */ -/*{ */ -/* ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList; */ -/* uint32_t descidx = dmarxdesclist->FirstAppDesc; */ -/* __IO const ETH_DMADescTypeDef *dmarxdesc; */ -/* */ -/* if(dmarxdesclist->AppDescNbr == 0U) */ -/* { */ -/* if(HAL_ETH_IsRxDataAvailable(heth) == 0U) */ -/* { */ -/* / * No data to be transferred to the application * / */ -/* return HAL_ERROR; */ -/* } */ -/* } */ -/* */ -/* / * Get index of last descriptor * / */ -/* INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U)); */ -/* / * Point to last descriptor * / */ -/* dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; */ -/* */ -/* *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL); */ -/* */ -/* return HAL_OK; */ -/*} */ - -/** - * @brief Get the Rx data info (Packet type, VLAN tag, Filters status, ...) - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param RxPacketInfo: parameter to hold info of received buffer - * @retval HAL status - */ -/*HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo) */ -/*{ */ -/* ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList; */ -/* uint32_t descidx = dmarxdesclist->FirstAppDesc; */ -/* __IO const ETH_DMADescTypeDef *dmarxdesc; */ -/* */ -/* if(dmarxdesclist->AppDescNbr == 0U) */ -/* { */ -/* if(HAL_ETH_IsRxDataAvailable(heth) == 0U) */ -/* { */ -/* / * No data to be transferred to the application * / */ -/* return HAL_ERROR; */ -/* } */ -/* } */ -/* */ -/* / * Get index of last descriptor * / */ -/* INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U)); */ -/* / * Point to last descriptor * / */ -/* dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; */ -/* */ -/* if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET) */ -/* { */ -/* RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK); */ -/* } */ -/* else */ -/* { */ -/* if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U) */ -/* { */ -/* */ -/* if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN) */ -/* { */ -/* RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT); */ -/* RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16; */ -/* } */ -/* else */ -/* { */ -/* RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT); */ -/* } */ -/* } */ -/* */ -/* if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U) */ -/* { */ -/* / * Get Payload type * / */ -/* RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT); */ -/* / * Get Header type * / */ -/* RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6)); */ -/* / * Get Checksum status * / */ -/* RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE)); */ -/* } */ -/* */ -/* if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U) */ -/* { */ -/* RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF)); */ -/* RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)); */ -/* RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)); */ -/* } */ -/* } */ -/* */ -/* / * Get the segment count * / */ -/* WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr); */ -/* */ -/* return HAL_OK; */ -/*} */ - -/** - * @brief This function gives back Rx Desc of the last received Packet - * to the DMA, so ETH DMA will be able to use these descriptors - * to receive next Packets. - * It should be called after processing the received Packet. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status. - */ - HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors( ETH_HandleTypeDef * heth, - uint8_t * pucNewBuffer ) - { - ETH_RxDescListTypeDef * dmarxdesclist = &heth->RxDescList; - uint32_t desc_index = dmarxdesclist->FirstAppDesc; - __IO ETH_DMADescTypeDef * dmarxdesc = ( ETH_DMADescTypeDef * ) dmarxdesclist->RxDesc[ desc_index ]; - uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr; - uint32_t descscan; - - if( dmarxdesclist->AppDescNbr == 0U ) - { - /* No Rx descriptors to build */ - return HAL_ERROR; - } - - if( dmarxdesclist->AppContextDesc != 0U ) - { - /* A context descriptor is available */ - totalappdescnbr += 1U; - } - - for( descscan = 0; ipTRUE_BOOL; descscan++ ) - { - uint32_t DESC3; - uint8_t * pucBuffer; - - if( pucNewBuffer != NULL ) - { - /* Earlier zero-copy RX only: buffer was passed to the application. */ - pucBuffer = pucNewBuffer; - dmarxdesc->BackupAddr0 = ( uint32_t ) pucNewBuffer; - } - else - { - /* Keep on using the same buffer as before. */ - pucBuffer = ( uint8_t * ) dmarxdesc->BackupAddr0; - } - - WRITE_REG( dmarxdesc->DESC0, ( uint32_t ) pucBuffer ); - /* Buffer 1 Address Valid */ - - DESC3 = READ_REG( dmarxdesc->DESC3 ); - WRITE_REG( DESC3, ETH_DMARXNDESCRF_BUF1V ); - -/* BackupAddr1 is not used in FreeRTOS+TCP */ -/* if (READ_REG(dmarxdesc->BackupAddr1) != 0U) */ -/* { */ -/* WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1); */ -/* SET_BIT(DESC3, ETH_DMARXNDESCRF_BUF2V); */ -/* } */ - - /* Should be the last change. */ -/* SET_BIT(DESC3, ETH_DMARXNDESCRF_OWN); */ - - if( dmarxdesclist->ItMode != 0U ) - { - /* Interrupt Enabled on Completion */ - SET_BIT( DESC3, ETH_DMARXNDESCRF_IOC ); - } - - /* Now all is ready.. */ - SET_BIT( DESC3, ETH_DMARXNDESCRF_OWN ); - - WRITE_REG( dmarxdesc->DESC3, DESC3 ); - - __DSB(); - - /* And read it back. */ - ( void ) dmarxdesc->DESC3; - - if( descscan >= ( totalappdescnbr - 1U ) ) - { - break; - } - - /* Increment rx descriptor index */ - INCR_RX_DESC_INDEX( desc_index, 1U ); - /* Get descriptor address */ - dmarxdesc = ( ETH_DMADescTypeDef * ) dmarxdesclist->RxDesc[ desc_index ]; - } - - /* Set the Tail pointer address to the last rx descriptor hold by the app */ - WRITE_REG( heth->Instance->DMACRDTPR, ( uint32_t ) dmarxdesc ); - - /* reset the Application desc number */ - dmarxdesclist->AppDescNbr = 0; - - /* reset the application context descriptor */ - WRITE_REG( heth->RxDescList.AppContextDesc, 0 ); - - return HAL_OK; - } - - -/** - * @brief This function handles ETH interrupt request. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - void HAL_ETH_IRQHandler( ETH_HandleTypeDef * heth ) - { - /* ETH interrupt. See heth->DMACSR for details. - */ - - if( __HAL_ETH_DMA_GET_IT( heth, ETH_DMACSR_RI ) ) - { - if( __HAL_ETH_DMA_GET_IT_SOURCE( heth, ETH_DMACIER_RIE ) ) - { - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /*Call registered Receive complete callback*/ - heth->RxCpltCallback( heth ); - } - #else - { - /* Receive complete callback */ - HAL_ETH_RxCpltCallback( heth ); - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT( heth, ETH_DMACSR_RI | ETH_DMACSR_NIS ); - } - } - - /* Packet transmitted */ - if( __HAL_ETH_DMA_GET_IT( heth, ETH_DMACSR_TI ) ) - { - if( __HAL_ETH_DMA_GET_IT_SOURCE( heth, ETH_DMACIER_TIE ) ) - { - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /*Call registered Transmit complete callback*/ - heth->TxCpltCallback( heth ); - } - #else - { - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback( heth ); - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT( heth, ETH_DMACSR_TI | ETH_DMACSR_NIS ); - } - } - - /* ETH DMA Error */ - if( __HAL_ETH_DMA_GET_IT( heth, ETH_DMACSR_AIS ) ) - { - if( __HAL_ETH_DMA_GET_IT_SOURCE( heth, ETH_DMACIER_AIE ) ) - { - heth->ErrorCode |= HAL_ETH_ERROR_DMA; - - /* if fatal bus error occured */ - if( __HAL_ETH_DMA_GET_IT( heth, ETH_DMACSR_FBE ) ) - { - /* Get DMA error code */ - heth->DMAErrorCode = READ_BIT( heth->Instance->DMACSR, ( ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS ) ); - - /* Disable all interrupts */ - __HAL_ETH_DMA_DISABLE_IT( heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE ); - - /* Set HAL state to ERROR */ - set_error_state( heth, HAL_ETH_STATE_ERROR ); - } - else - { - /* Get DMA error status */ - heth->DMAErrorCode = READ_BIT( heth->Instance->DMACSR, ( ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | - ETH_DMACSR_RBU | ETH_DMACSR_AIS ) ); - - /* Clear the interrupt summary flag */ - __HAL_ETH_DMA_CLEAR_IT( heth, ( ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | - ETH_DMACSR_RBU | ETH_DMACSR_AIS ) ); - } - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /* Call registered DMA Error callback*/ - heth->DMAErrorCallback( heth ); - } - #else - { - /* Ethernet DMA Error callback */ - HAL_ETH_DMAErrorCallback( heth ); - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } - } - - /* ETH MAC Error IT */ - if( __HAL_ETH_MAC_GET_IT( heth, ( ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE ) ) ) - { - /* Get MAC Rx Tx status and clear Status register pending bit */ - heth->MACErrorCode = READ_REG( heth->Instance->MACRXTXSR ); - - set_error_state( heth, HAL_ETH_STATE_ERROR ); - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /* Call registered MAC Error callback*/ - heth->DMAErrorCallback( heth ); - } - #else - { - /* Ethernet MAC Error callback */ - HAL_ETH_MACErrorCallback( heth ); - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - heth->MACErrorCode = ( uint32_t ) ( 0x0U ); - } - - /* ETH PMT IT */ - if( __HAL_ETH_MAC_GET_IT( heth, ETH_MAC_PMT_IT ) ) - { - /* Get MAC Wake-up source and clear the status register pending bit */ - heth->MACWakeUpEvent = READ_BIT( heth->Instance->MACPCSR, ( ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD ) ); - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /* Call registered PMT callback*/ - heth->PMTCallback( heth ); - } - #else - { - /* Ethernet PMT callback */ - HAL_ETH_PMTCallback( heth ); - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - heth->MACWakeUpEvent = ( uint32_t ) ( 0x0U ); - } - - /* ETH EEE IT */ - if( __HAL_ETH_MAC_GET_IT( heth, ETH_MAC_LPI_IT ) ) - { - /* Get MAC LPI interrupt source and clear the status register pending bit */ - heth->MACLPIEvent = READ_BIT( heth->Instance->MACPCSR, 0x0000000FU ); - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /* Call registered EEE callback*/ - heth->EEECallback( heth ); - } - #else - { - /* Ethernet EEE callback */ - HAL_ETH_EEECallback( heth ); - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - heth->MACLPIEvent = ( uint32_t ) ( 0x0U ); - } - - #if defined( DUAL_CORE ) - if( HAL_GetCurrentCPUID() == CM7_CPUID ) - { - /* check ETH WAKEUP exti flag */ - if( __HAL_ETH_WAKEUP_EXTI_GET_FLAG( ETH_WAKEUP_EXTI_LINE ) != ( uint32_t ) RESET ) - { - /* Clear ETH WAKEUP Exti pending bit */ - __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG( ETH_WAKEUP_EXTI_LINE ); - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /* Call registered WakeUp callback*/ - heth->WakeUpCallback( heth ); - } - #else - { - /* ETH WAKEUP callback */ - HAL_ETH_WakeUpCallback( heth ); - } - #endif - } - } - else - { - /* check ETH WAKEUP exti flag */ - if( __HAL_ETH_WAKEUP_EXTID2_GET_FLAG( ETH_WAKEUP_EXTI_LINE ) != ( uint32_t ) RESET ) - { - /* Clear ETH WAKEUP Exti pending bit */ - __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG( ETH_WAKEUP_EXTI_LINE ); - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /* Call registered WakeUp callback*/ - heth->WakeUpCallback( heth ); - } - #else - { - /* ETH WAKEUP callback */ - HAL_ETH_WakeUpCallback( heth ); - } - #endif - } - } - #else /* #if defined(DUAL_CORE) */ - /* check ETH WAKEUP exti flag */ - if( __HAL_ETH_WAKEUP_EXTI_GET_FLAG( ETH_WAKEUP_EXTI_LINE ) != ( uint32_t ) RESET ) - { - /* Clear ETH WAKEUP Exti pending bit */ - __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG( ETH_WAKEUP_EXTI_LINE ); - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - { - /* Call registered WakeUp callback*/ - heth->WakeUpCallback( heth ); - } - #else - { - /* ETH WAKEUP callback */ - HAL_ETH_WakeUpCallback( heth ); - } - #endif - } - #endif /* #if defined(DUAL_CORE) */ - } - -/** - * @brief Tx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_TxCpltCallback could be implemented in the user file - */ - } - -/** - * @brief Rx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_RxCpltCallback could be implemented in the user file - */ - } - -/** - * @brief Ethernet DMA transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_DMAErrorCallback( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_DMAErrorCallback could be implemented in the user file - */ - } - -/** - * @brief Ethernet MAC transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_MACErrorCallback( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_MACErrorCallback could be implemented in the user file - */ - } - -/** - * @brief Ethernet Power Management module IT callback - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_PMTCallback( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_PMTCallback could be implemented in the user file - */ - } - -/** - * @brief Energy Efficient Etherent IT callback - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_EEECallback( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_EEECallback could be implemented in the user file - */ - } - -/** - * @brief ETH WAKEUP interrupt callback - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - __weak void HAL_ETH_WakeUpCallback( ETH_HandleTypeDef * heth ) - { - /* Prevent unused argument(s) compilation warning */ - UNUSED( heth ); - - /* NOTE : This function Should not be modified, when the callback is needed, - * the HAL_ETH_WakeUpCallback could be implemented in the user file - */ - } - -/** - * @brief Read a PHY register - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYAddr: PHY port address, must be a value from 0 to 31 - * @param PHYReg: PHY register address, must be a value from 0 to 31 - * @param pRegValue: parameter to hold read value - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef * heth, - uint32_t PHYAddr, - uint32_t PHYReg, - uint32_t * pRegValue ) - { - uint32_t tmpreg, tickstart; - - /* Check for the Busy flag */ - if( READ_BIT( heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB ) != 0U ) - { - return HAL_ERROR; - } - - /* Get the MACMDIOAR value */ - WRITE_REG( tmpreg, heth->Instance->MACMDIOAR ); - - /* Prepare the MDIO Address Register value - * - Set the PHY device address - * - Set the PHY register address - * - Set the read mode - * - Set the MII Busy bit */ - - MODIFY_REG( tmpreg, ETH_MACMDIOAR_PA, ( PHYAddr << 21 ) ); - MODIFY_REG( tmpreg, ETH_MACMDIOAR_RDA, ( PHYReg << 16 ) ); - MODIFY_REG( tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD ); - SET_BIT( tmpreg, ETH_MACMDIOAR_MB ); - - /* Write the result value into the MDII Address register */ - WRITE_REG( heth->Instance->MACMDIOAR, tmpreg ); - - tickstart = HAL_GetTick(); - - /* Wait for the Busy flag */ - while( READ_BIT( heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB ) > 0U ) - { - if( ( ( HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT ) ) - { - return HAL_ERROR; - } - } - - /* Get MACMIIDR value */ - WRITE_REG( *pRegValue, ( uint16_t ) heth->Instance->MACMDIODR ); - - return HAL_OK; - } - - -/** - * @brief Writes to a PHY register. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYAddr: PHY port address, must be a value from 0 to 31 - * @param PHYReg: PHY register address, must be a value from 0 to 31 - * @param RegValue: the value to write - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef * heth, - uint32_t PHYAddr, - uint32_t PHYReg, - uint32_t RegValue ) - { - uint32_t tmpreg, tickstart; - - /* Check for the Busy flag */ - if( READ_BIT( heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB ) != 0U ) - { - return HAL_ERROR; - } - - /* Get the MACMDIOAR value */ - WRITE_REG( tmpreg, heth->Instance->MACMDIOAR ); - - /* Prepare the MDIO Address Register value - * - Set the PHY device address - * - Set the PHY register address - * - Set the write mode - * - Set the MII Busy bit */ - - MODIFY_REG( tmpreg, ETH_MACMDIOAR_PA, ( PHYAddr << 21 ) ); - MODIFY_REG( tmpreg, ETH_MACMDIOAR_RDA, ( PHYReg << 16 ) ); - MODIFY_REG( tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR ); - SET_BIT( tmpreg, ETH_MACMDIOAR_MB ); - - - /* Give the value to the MII data register */ - WRITE_REG( ETH->MACMDIODR, ( uint16_t ) RegValue ); - - /* Write the result value into the MII Address register */ - WRITE_REG( ETH->MACMDIOAR, tmpreg ); - - tickstart = HAL_GetTick(); - - /* Wait for the Busy flag */ - while( READ_BIT( heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB ) > 0U ) - { - if( ( ( HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT ) ) - { - return HAL_ERROR; - } - } - - return HAL_OK; - } - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief ETH control functions - * - * @verbatim - * ============================================================================== - ##### Peripheral Control functions ##### - #####============================================================================== - #####[..] - #####This subsection provides a set of functions allowing to control the ETH - #####peripheral. - ##### - #####@endverbatim - * @{ - */ - -/** - * @brief Get the configuration of the MAC and MTL subsystems. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold - * the configuration of the MAC. - * @retval HAL Status - */ - HAL_StatusTypeDef HAL_ETH_GetMACConfig( ETH_HandleTypeDef * heth, - ETH_MACConfigTypeDef * macconf ) - { - if( macconf == NULL ) - { - return HAL_ERROR; - } - - /* Get MAC parameters */ - macconf->PreambleLength = READ_BIT( heth->Instance->MACCR, ETH_MACCR_PRELEN ); - macconf->DeferralCheck = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_DC ) >> 4 ) > 0U ) ? ENABLE : DISABLE; - macconf->BackOffLimit = READ_BIT( heth->Instance->MACCR, ETH_MACCR_BL ); - macconf->RetryTransmission = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_DR ) >> 8 ) == 0U ) ? ENABLE : DISABLE; - macconf->CarrierSenseDuringTransmit = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_DCRS ) >> 9 ) > 0U ) ? ENABLE : DISABLE; - macconf->ReceiveOwn = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_DO ) >> 10 ) == 0U ) ? ENABLE : DISABLE; - macconf->CarrierSenseBeforeTransmit = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_ECRSFD ) >> 11 ) > 0U ) ? ENABLE : DISABLE; - macconf->LoopbackMode = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_LM ) >> 12 ) > 0U ) ? ENABLE : DISABLE; - macconf->DuplexMode = READ_BIT( heth->Instance->MACCR, ETH_MACCR_DM ); - macconf->Speed = READ_BIT( heth->Instance->MACCR, ETH_MACCR_FES ); - macconf->JumboPacket = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_JE ) >> 16 ) > 0U ) ? ENABLE : DISABLE; - macconf->Jabber = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_JD ) >> 17 ) == 0U ) ? ENABLE : DISABLE; - macconf->Watchdog = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_WD ) >> 19 ) == 0U ) ? ENABLE : DISABLE; - macconf->AutomaticPadCRCStrip = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_ACS ) >> 20 ) > 0U ) ? ENABLE : DISABLE; - macconf->CRCStripTypePacket = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_CST ) >> 21 ) > 0U ) ? ENABLE : DISABLE; - macconf->Support2KPacket = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_S2KP ) >> 22 ) > 0U ) ? ENABLE : DISABLE; - macconf->GiantPacketSizeLimitControl = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_GPSLCE ) >> 23 ) > 0U ) ? ENABLE : DISABLE; - macconf->InterPacketGapVal = READ_BIT( heth->Instance->MACCR, ETH_MACCR_IPG ); - macconf->ChecksumOffload = ( ( READ_BIT( heth->Instance->MACCR, ETH_MACCR_IPC ) >> 27 ) > 0U ) ? ENABLE : DISABLE; - macconf->SourceAddrControl = READ_BIT( heth->Instance->MACCR, ETH_MACCR_SARC ); - - macconf->GiantPacketSizeLimit = READ_BIT( heth->Instance->MACECR, ETH_MACECR_GPSL ); - macconf->CRCCheckingRxPackets = ( ( READ_BIT( heth->Instance->MACECR, ETH_MACECR_DCRCC ) >> 16 ) == 0U ) ? ENABLE : DISABLE; - macconf->SlowProtocolDetect = ( ( READ_BIT( heth->Instance->MACECR, ETH_MACECR_SPEN ) >> 17 ) > 0U ) ? ENABLE : DISABLE; - macconf->UnicastSlowProtocolPacketDetect = ( ( READ_BIT( heth->Instance->MACECR, ETH_MACECR_USP ) >> 18 ) > 0U ) ? ENABLE : DISABLE; - macconf->ExtendedInterPacketGap = ( ( READ_BIT( heth->Instance->MACECR, ETH_MACECR_EIPGEN ) >> 24 ) > 0U ) ? ENABLE : DISABLE; - macconf->ExtendedInterPacketGapVal = READ_BIT( heth->Instance->MACECR, ETH_MACECR_EIPG ) >> 25; - - - macconf->ProgrammableWatchdog = ( ( READ_BIT( heth->Instance->MACWTR, ETH_MACWTR_PWE ) >> 8 ) > 0U ) ? ENABLE : DISABLE; - macconf->WatchdogTimeout = READ_BIT( heth->Instance->MACWTR, ETH_MACWTR_WTO ); - - macconf->TransmitFlowControl = ( ( READ_BIT( heth->Instance->MACTFCR, ETH_MACTFCR_TFE ) >> 1 ) > 0U ) ? ENABLE : DISABLE; - macconf->ZeroQuantaPause = ( ( READ_BIT( heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ ) >> 7 ) == 0U ) ? ENABLE : DISABLE; - macconf->PauseLowThreshold = READ_BIT( heth->Instance->MACTFCR, ETH_MACTFCR_PLT ); - macconf->PauseTime = ( READ_BIT( heth->Instance->MACTFCR, ETH_MACTFCR_PT ) >> 16 ); - - - macconf->ReceiveFlowControl = ( READ_BIT( heth->Instance->MACRFCR, ETH_MACRFCR_RFE ) > 0U ) ? ENABLE : DISABLE; - macconf->UnicastPausePacketDetect = ( ( READ_BIT( heth->Instance->MACRFCR, ETH_MACRFCR_UP ) >> 1 ) > 0U ) ? ENABLE : DISABLE; - - macconf->TransmitQueueMode = READ_BIT( heth->Instance->MTLTQOMR, ( ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF ) ); - - macconf->ReceiveQueueMode = READ_BIT( heth->Instance->MTLRQOMR, ( ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF ) ); - macconf->ForwardRxUndersizedGoodPacket = ( ( READ_BIT( heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP ) >> 3 ) > 0U ) ? ENABLE : DISABLE; - macconf->ForwardRxErrorPacket = ( ( READ_BIT( heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP ) >> 4 ) > 0U ) ? ENABLE : DISABLE; - macconf->DropTCPIPChecksumErrorPacket = ( ( READ_BIT( heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF ) >> 6 ) == 0U ) ? ENABLE : DISABLE; - - return HAL_OK; - } - -/** - * @brief Get the configuration of the DMA. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold - * the configuration of the ETH DMA. - * @retval HAL Status - */ - HAL_StatusTypeDef HAL_ETH_GetDMAConfig( ETH_HandleTypeDef * heth, - ETH_DMAConfigTypeDef * dmaconf ) - { - if( dmaconf == NULL ) - { - return HAL_ERROR; - } - - dmaconf->AddressAlignedBeats = ( ( READ_BIT( heth->Instance->DMASBMR, ETH_DMASBMR_AAL ) >> 12 ) > 0U ) ? ENABLE : DISABLE; - dmaconf->BurstMode = READ_BIT( heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB ); - dmaconf->RebuildINCRxBurst = ( ( READ_BIT( heth->Instance->DMASBMR, ETH_DMASBMR_RB ) >> 15 ) > 0U ) ? ENABLE : DISABLE; - - dmaconf->DMAArbitration = READ_BIT( heth->Instance->DMAMR, ( ETH_DMAMR_TXPR | ETH_DMAMR_PR | ETH_DMAMR_DA ) ); - - dmaconf->PBLx8Mode = ( ( READ_BIT( heth->Instance->DMACCR, ETH_DMACCR_8PBL ) >> 16 ) > 0U ) ? ENABLE : DISABLE; - dmaconf->MaximumSegmentSize = READ_BIT( heth->Instance->DMACCR, ETH_DMACCR_MSS ); - - dmaconf->FlushRxPacket = ( ( READ_BIT( heth->Instance->DMACRCR, ETH_DMACRCR_RPF ) >> 31 ) > 0U ) ? ENABLE : DISABLE; - dmaconf->RxDMABurstLength = READ_BIT( heth->Instance->DMACRCR, ETH_DMACRCR_RPBL ); - - dmaconf->SecondPacketOperate = ( ( READ_BIT( heth->Instance->DMACTCR, ETH_DMACTCR_OSP ) >> 4 ) > 0U ) ? ENABLE : DISABLE; - dmaconf->TCPSegmentation = ( ( READ_BIT( heth->Instance->DMACTCR, ETH_DMACTCR_TSE ) >> 12 ) > 0U ) ? ENABLE : DISABLE; - dmaconf->TxDMABurstLength = READ_BIT( heth->Instance->DMACTCR, ETH_DMACTCR_TPBL ); - - return HAL_OK; - } - -/** - * @brief Set the MAC configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains - * the configuration of the MAC. - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_SetMACConfig( ETH_HandleTypeDef * heth, - ETH_MACConfigTypeDef * macconf ) - { - if( macconf == NULL ) - { - return HAL_ERROR; - } - - if( heth->RxState == HAL_ETH_STATE_READY ) - { - ETH_SetMACConfig( heth, macconf ); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Set the ETH DMA configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold - * the configuration of the ETH DMA. - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_SetDMAConfig( ETH_HandleTypeDef * heth, - ETH_DMAConfigTypeDef * dmaconf ) - { - if( dmaconf == NULL ) - { - return HAL_ERROR; - } - - if( heth->RxState == HAL_ETH_STATE_READY ) - { - ETH_SetDMAConfig( heth, dmaconf ); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - -/** - * @brief Set the ETH MAC (L2) Filters configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains - * the configuration of the ETH MAC filters. - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig( ETH_HandleTypeDef * heth, - ETH_MACFilterConfigTypeDef * pFilterConfig ) - { - uint32_t filterconfig; - - if( pFilterConfig == NULL ) - { - return HAL_ERROR; - } - - filterconfig = ( ( uint32_t ) pFilterConfig->PromiscuousMode | - ( ( uint32_t ) pFilterConfig->HashUnicast << 1 ) | - ( ( uint32_t ) pFilterConfig->HashMulticast << 2 ) | - ( ( uint32_t ) pFilterConfig->DestAddrInverseFiltering << 3 ) | - ( ( uint32_t ) pFilterConfig->PassAllMulticast << 4 ) | - ( ( uint32_t ) ( ( pFilterConfig->BroadcastFilter == DISABLE ) ? 1U : 0U ) << 5 ) | - ( ( uint32_t ) pFilterConfig->SrcAddrInverseFiltering << 8 ) | - ( ( uint32_t ) pFilterConfig->SrcAddrFiltering << 9 ) | - ( ( uint32_t ) pFilterConfig->HachOrPerfectFilter << 10 ) | - ( ( uint32_t ) pFilterConfig->ReceiveAllMode << 31 ) | - pFilterConfig->ControlPacketsFilter ); - - MODIFY_REG( heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig ); - - return HAL_OK; - } - -/** - * @brief Get the ETH MAC (L2) Filters configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold - * the configuration of the ETH MAC filters. - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig( ETH_HandleTypeDef * heth, - ETH_MACFilterConfigTypeDef * pFilterConfig ) - { - if( pFilterConfig == NULL ) - { - return HAL_ERROR; - } - - pFilterConfig->PromiscuousMode = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_PR ) ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->HashUnicast = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_HUC ) >> 1 ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->HashMulticast = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_HMC ) >> 2 ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->DestAddrInverseFiltering = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_DAIF ) >> 3 ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->PassAllMulticast = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_PM ) >> 4 ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_DBF ) >> 5 ) == 0U ) ? ENABLE : DISABLE; - pFilterConfig->ControlPacketsFilter = READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_PCF ); - pFilterConfig->SrcAddrInverseFiltering = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_SAIF ) >> 8 ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->SrcAddrFiltering = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_SAF ) >> 9 ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->HachOrPerfectFilter = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_HPF ) >> 10 ) > 0U ) ? ENABLE : DISABLE; - pFilterConfig->ReceiveAllMode = ( ( READ_BIT( heth->Instance->MACPFR, ETH_MACPFR_RA ) >> 31 ) > 0U ) ? ENABLE : DISABLE; - - return HAL_OK; - } - -/** - * @brief Set the source MAC Address to be matched. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param AddrNbr: The MAC address to configure - * This parameter must be a value of the following: - * ETH_MAC_ADDRESS1 - * ETH_MAC_ADDRESS2 - * ETH_MAC_ADDRESS3 - * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch( ETH_HandleTypeDef * heth, - uint32_t AddrNbr, - uint8_t * pMACAddr ) - { - uint32_t macaddrhr, macaddrlr; - - if( pMACAddr == NULL ) - { - return HAL_ERROR; - } - - /* Get mac addr high reg offset */ - macaddrhr = ( ( uint32_t ) &( heth->Instance->MACA0HR ) + AddrNbr ); - /* Get mac addr low reg offset */ - macaddrlr = ( ( uint32_t ) &( heth->Instance->MACA0LR ) + AddrNbr ); - - /* Set MAC addr bits 32 to 47 */ - ( *( __IO uint32_t * ) macaddrhr ) = ( ( ( uint32_t ) ( pMACAddr[ 5 ] ) << 8 ) | ( uint32_t ) pMACAddr[ 4 ] ); - /* Set MAC addr bits 0 to 31 */ - ( *( __IO uint32_t * ) macaddrlr ) = ( ( ( uint32_t ) ( pMACAddr[ 3 ] ) << 24 ) | ( ( uint32_t ) ( pMACAddr[ 2 ] ) << 16 ) | - ( ( uint32_t ) ( pMACAddr[ 1 ] ) << 8 ) | ( uint32_t ) pMACAddr[ 0 ] ); - - /* Enable address and set source address bit */ - ( *( __IO uint32_t * ) macaddrhr ) |= ( ETH_MACAHR_SA | ETH_MACAHR_AE ); - - return HAL_OK; - } - -/** - * @brief Set the ETH Hash Table Value. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pHashTable: pointer to a table of two 32 bit values, that contains - * the 64 bits of the hash table. - * @retval HAL status - */ - HAL_StatusTypeDef HAL_ETH_SetHashTable( ETH_HandleTypeDef * heth, - uint32_t * pHashTable ) - { - if( pHashTable == NULL ) - { - return HAL_ERROR; - } - - heth->Instance->MACHT0R = pHashTable[ 0 ]; - heth->Instance->MACHT1R = pHashTable[ 1 ]; - - return HAL_OK; - } - -/** - * @brief Set the VLAN Identifier for Rx packets - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param ComparisonBits: 12 or 16 bit comparison mode - * must be a value of @ref ETH_VLAN_Tag_Comparison - * @param VLANIdentifier: VLAN Identifier value - * @retval None - */ - void HAL_ETH_SetRxVLANIdentifier( ETH_HandleTypeDef * heth, - uint32_t ComparisonBits, - uint32_t VLANIdentifier ) - { - if( ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT ) - { - MODIFY_REG( heth->Instance->MACVTR, ETH_MACVTR_VL, VLANIdentifier ); - CLEAR_BIT( heth->Instance->MACVTR, ETH_MACVTR_ETV ); - } - else - { - MODIFY_REG( heth->Instance->MACVTR, ETH_MACVTR_VL_VID, VLANIdentifier ); - SET_BIT( heth->Instance->MACVTR, ETH_MACVTR_ETV ); - } - } - -/** - * @brief Enters the Power down mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure - * that contains the Power Down configration - * @retval None. - */ - void HAL_ETH_EnterPowerDownMode( ETH_HandleTypeDef * heth, - ETH_PowerDownConfigTypeDef * pPowerDownConfig ) - { - uint32_t powerdownconfig; - - powerdownconfig = ( ( ( uint32_t ) pPowerDownConfig->MagicPacket << 1 ) | - ( ( uint32_t ) pPowerDownConfig->WakeUpPacket << 2 ) | - ( ( uint32_t ) pPowerDownConfig->GlobalUnicast << 9 ) | - ( ( uint32_t ) pPowerDownConfig->WakeUpForward << 10 ) | - ETH_MACPCSR_PWRDWN ); - - /* Enable PMT interrupt */ - __HAL_ETH_MAC_ENABLE_IT( heth, ETH_MACIER_PMTIE ); - - MODIFY_REG( heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig ); - } - -/*/ ** */ -/* * @brief Exits from the Power down mode. */ -/* * @param heth: pointer to a ETH_HandleTypeDef structure that contains */ -/* * the configuration information for ETHERNET module */ -/* * @retval None. */ -/* * / */ -/*void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) */ -/*{ */ -/* / * clear wake up sources * / */ -/* CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE); */ -/* */ -/* if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U) */ -/* { */ -/* / * Exit power down mode * / */ -/* CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN); */ -/* } */ -/* */ -/* / * Disable PMT interrupt * / */ -/* __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE); */ -/*} */ -/* */ -/*/ ** */ -/* * @brief Set the WakeUp filter. */ -/* * @param heth: pointer to a ETH_HandleTypeDef structure that contains */ -/* * the configuration information for ETHERNET module */ -/* * @param pFilter: pointer to filter registers values */ -/* * @param Count: number of filter registers, must be from 1 to 8. */ -/* * @retval None. */ -/* * / */ -/*HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count) */ -/*{ */ -/* uint32_t regindex; */ -/* */ -/* if(pFilter == NULL) */ -/* { */ -/* return HAL_ERROR; */ -/* } */ -/* */ -/* / * Reset Filter Pointer * / */ -/* SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST); */ -/* */ -/* / * Wake up packet filter config * / */ -/* for(regindex = 0; regindex < Count; regindex++) */ -/* { */ -/* / * Write filter regs * / */ -/* WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]); */ -/* } */ -/* */ -/* return HAL_OK; */ -/*} */ - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief ETH State and Errors functions - * - * @verbatim - * ============================================================================== - ##### Peripheral State and Errors functions ##### - #####============================================================================== - #####[..] - #####This subsection provides a set of functions allowing to return the State of - #####ETH communication process, return Peripheral Errors occurred during communication - #####process - ##### - ##### - #####@endverbatim - * @{ - */ - -/** - * @brief Returns the ETH state. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL state - */ - HAL_ETH_StateTypeDef HAL_ETH_GetState( ETH_HandleTypeDef * heth ) - { - HAL_ETH_StateTypeDef ret; - HAL_ETH_StateTypeDef gstate = heth->gState; - HAL_ETH_StateTypeDef rxstate = heth->RxState; - - ret = gstate; - ret |= rxstate; - return ret; - } - -/** - * @brief Returns the ETH error code - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH Error Code - */ - uint32_t HAL_ETH_GetError( ETH_HandleTypeDef * heth ) - { - return heth->ErrorCode; - } - -/** - * @brief Returns the ETH DMA error code - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH DMA Error Code - */ - uint32_t HAL_ETH_GetDMAError( ETH_HandleTypeDef * heth ) - { - return heth->DMAErrorCode; - } - -/** - * @brief Returns the ETH MAC error code - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH MAC Error Code - */ - uint32_t HAL_ETH_GetMACError( ETH_HandleTypeDef * heth ) - { - return heth->MACErrorCode; - } - -/** - * @brief Returns the ETH MAC WakeUp event source - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH MAC WakeUp event source - */ - uint32_t HAL_ETH_GetMACWakeUpSource( ETH_HandleTypeDef * heth ) - { - return heth->MACWakeUpEvent; - } - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup ETH_Private_Functions ETH Private Functions - * @{ - */ - - static void ETH_SetMACConfig( ETH_HandleTypeDef * heth, - ETH_MACConfigTypeDef * macconf ) - { - uint32_t macregval; - - /*------------------------ MACCR Configuration --------------------*/ - macregval = ( macconf->InterPacketGapVal | - macconf->SourceAddrControl | - ( ( uint32_t ) macconf->ChecksumOffload << 27 ) | - ( ( uint32_t ) macconf->GiantPacketSizeLimitControl << 23 ) | - ( ( uint32_t ) macconf->Support2KPacket << 22 ) | - ( ( uint32_t ) macconf->CRCStripTypePacket << 21 ) | - ( ( uint32_t ) macconf->AutomaticPadCRCStrip << 20 ) | - ( ( uint32_t ) ( ( macconf->Watchdog == DISABLE ) ? 1U : 0U ) << 19 ) | - ( ( uint32_t ) ( ( macconf->Jabber == DISABLE ) ? 1U : 0U ) << 17 ) | - ( ( uint32_t ) macconf->JumboPacket << 16 ) | - macconf->Speed | - macconf->DuplexMode | - ( ( uint32_t ) macconf->LoopbackMode << 12 ) | - ( ( uint32_t ) macconf->CarrierSenseBeforeTransmit << 11 ) | - ( ( uint32_t ) ( ( macconf->ReceiveOwn == DISABLE ) ? 1U : 0U ) << 10 ) | - ( ( uint32_t ) macconf->CarrierSenseDuringTransmit << 9 ) | - ( ( uint32_t ) ( ( macconf->RetryTransmission == DISABLE ) ? 1U : 0U ) << 8 ) | - macconf->BackOffLimit | - ( ( uint32_t ) macconf->DeferralCheck << 4 ) | - macconf->PreambleLength ); - - /* Write to MACCR */ - MODIFY_REG( heth->Instance->MACCR, ETH_MACCR_MASK, macregval ); - - /*------------------------ MACECR Configuration --------------------*/ - macregval = ( ( macconf->ExtendedInterPacketGapVal << 25 ) | - ( ( uint32_t ) macconf->ExtendedInterPacketGap << 24 ) | - ( ( uint32_t ) macconf->UnicastSlowProtocolPacketDetect << 18 ) | - ( ( uint32_t ) macconf->SlowProtocolDetect << 17 ) | - ( ( uint32_t ) ( ( macconf->CRCCheckingRxPackets == DISABLE ) ? 1U : 0U ) << 16 ) | - macconf->GiantPacketSizeLimit ); - - /* Write to MACECR */ - MODIFY_REG( heth->Instance->MACECR, ETH_MACECR_MASK, macregval ); - - /*------------------------ MACWTR Configuration --------------------*/ - macregval = ( ( ( uint32_t ) macconf->ProgrammableWatchdog << 8 ) | - macconf->WatchdogTimeout ); - - /* Write to MACWTR */ - MODIFY_REG( heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval ); - - /*------------------------ MACTFCR Configuration --------------------*/ - macregval = ( ( ( uint32_t ) macconf->TransmitFlowControl << 1 ) | - macconf->PauseLowThreshold | - ( ( uint32_t ) ( ( macconf->ZeroQuantaPause == DISABLE ) ? 1U : 0U ) << 7 ) | - ( macconf->PauseTime << 16 ) ); - - /* Write to MACTFCR */ - MODIFY_REG( heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval ); - - /*------------------------ MACRFCR Configuration --------------------*/ - macregval = ( ( uint32_t ) macconf->ReceiveFlowControl | - ( ( uint32_t ) macconf->UnicastPausePacketDetect << 1 ) ); - - /* Write to MACRFCR */ - MODIFY_REG( heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval ); - - /*------------------------ MTLTQOMR Configuration --------------------*/ - /* Write to MTLTQOMR */ - MODIFY_REG( heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode ); - - /*------------------------ MTLRQOMR Configuration --------------------*/ - macregval = ( macconf->ReceiveQueueMode | - ( ( uint32_t ) ( ( macconf->DropTCPIPChecksumErrorPacket == DISABLE ) ? 1U : 0U ) << 6 ) | - ( ( uint32_t ) macconf->ForwardRxErrorPacket << 4 ) | - ( ( uint32_t ) macconf->ForwardRxUndersizedGoodPacket << 3 ) ); - - /* Write to MTLRQOMR */ - MODIFY_REG( heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval ); - } - - static void ETH_SetDMAConfig( ETH_HandleTypeDef * heth, - ETH_DMAConfigTypeDef * dmaconf ) - { - uint32_t dmaregval; - - /*------------------------ DMAMR Configuration --------------------*/ - MODIFY_REG( heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration ); - - /*------------------------ DMASBMR Configuration --------------------*/ - dmaregval = ( ( ( uint32_t ) dmaconf->AddressAlignedBeats << 12 ) | - dmaconf->BurstMode | - ( ( uint32_t ) dmaconf->RebuildINCRxBurst << 15 ) ); - - MODIFY_REG( heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval ); - - /*------------------------ DMACCR Configuration --------------------*/ - dmaregval = ( ( ( uint32_t ) dmaconf->PBLx8Mode << 16 ) | - dmaconf->MaximumSegmentSize ); - - MODIFY_REG( heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval ); - - /*------------------------ DMACTCR Configuration --------------------*/ - dmaregval = ( dmaconf->TxDMABurstLength | - ( ( uint32_t ) dmaconf->SecondPacketOperate << 4 ) | - ( ( uint32_t ) dmaconf->TCPSegmentation << 12 ) ); - - MODIFY_REG( heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval ); - - /*------------------------ DMACRCR Configuration --------------------*/ - dmaregval = ( ( ( uint32_t ) dmaconf->FlushRxPacket << 31 ) | - dmaconf->RxDMABurstLength ); - - /* Write to DMACRCR */ - MODIFY_REG( heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval ); - } - -/** - * @brief Configures Ethernet MAC and DMA with default parameters. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ - static void ETH_MACDMAConfig( ETH_HandleTypeDef * heth ) - { - ETH_MACConfigTypeDef macDefaultConf; - ETH_DMAConfigTypeDef dmaDefaultConf; - - /*--------------- ETHERNET MAC registers default Configuration --------------*/ - macDefaultConf.AutomaticPadCRCStrip = ENABLE; - macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; - macDefaultConf.CarrierSenseBeforeTransmit = DISABLE; - macDefaultConf.CarrierSenseDuringTransmit = DISABLE; - macDefaultConf.ChecksumOffload = ENABLE; - macDefaultConf.CRCCheckingRxPackets = ENABLE; - macDefaultConf.CRCStripTypePacket = ENABLE; - macDefaultConf.DeferralCheck = DISABLE; - macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE; - macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; - macDefaultConf.ExtendedInterPacketGap = DISABLE; - macDefaultConf.ExtendedInterPacketGapVal = 0x0; - macDefaultConf.ForwardRxErrorPacket = DISABLE; - macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE; - macDefaultConf.GiantPacketSizeLimit = 0x618; - macDefaultConf.GiantPacketSizeLimitControl = DISABLE; - macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT; - macDefaultConf.Jabber = ENABLE; - macDefaultConf.JumboPacket = DISABLE; - macDefaultConf.LoopbackMode = DISABLE; - macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4; - macDefaultConf.PauseTime = 0x0; - macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7; - macDefaultConf.ProgrammableWatchdog = DISABLE; - macDefaultConf.ReceiveFlowControl = DISABLE; - macDefaultConf.ReceiveOwn = ENABLE; - macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD; - macDefaultConf.RetryTransmission = ENABLE; - macDefaultConf.SlowProtocolDetect = DISABLE; - macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0; - macDefaultConf.Speed = ETH_SPEED_100M; - macDefaultConf.Support2KPacket = DISABLE; - macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD; - macDefaultConf.TransmitFlowControl = DISABLE; - macDefaultConf.UnicastPausePacketDetect = DISABLE; - macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; - macDefaultConf.Watchdog = ENABLE; - macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB; - macDefaultConf.ZeroQuantaPause = ENABLE; - - /* MAC default configuration */ - ETH_SetMACConfig( heth, &macDefaultConf ); - - /*--------------- ETHERNET DMA registers default Configuration --------------*/ - dmaDefaultConf.AddressAlignedBeats = ENABLE; - dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; - dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1; - dmaDefaultConf.FlushRxPacket = DISABLE; - dmaDefaultConf.PBLx8Mode = DISABLE; - dmaDefaultConf.RebuildINCRxBurst = DISABLE; - dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmaDefaultConf.SecondPacketOperate = DISABLE; - dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmaDefaultConf.TCPSegmentation = DISABLE; - dmaDefaultConf.MaximumSegmentSize = 536; - - /* DMA default configuration */ - ETH_SetDMAConfig( heth, &dmaDefaultConf ); - } - -/** - * @brief Configures the Clock range of SMI interface. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_MAC_MDIO_ClkConfig( ETH_HandleTypeDef * heth ) - { - uint32_t tmpreg, hclk; - - /* Get the ETHERNET MACMDIOAR value */ - tmpreg = ( heth->Instance )->MACMDIOAR; - - /* Clear CSR Clock Range bits */ - tmpreg &= ~ETH_MACMDIOAR_CR; - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - /* Set CR bits depending on hclk value */ - if( ( hclk >= 20000000U ) && ( hclk < 35000000U ) ) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV16; - } - else if( ( hclk >= 35000000U ) && ( hclk < 60000000U ) ) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV26; - } - else if( ( hclk >= 60000000U ) && ( hclk < 100000000U ) ) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV42; - } - else if( ( hclk >= 100000000U ) && ( hclk < 150000000U ) ) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV62; - } - else /* (hclk >= 150000000)&&(hclk <= 200000000) */ - { - /* CSR Clock Range between 150-200 MHz */ - tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV102; - } - - /* Configure the CSR Clock Range */ - ( heth->Instance )->MACMDIOAR = ( uint32_t ) tmpreg; - } - -/** - * @brief Initializes the DMA Tx descriptors. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_DMATxDescListInit( ETH_HandleTypeDef * heth ) - { - ETH_DMADescTypeDef * dmatxdesc; - uint32_t i; - - /* Fill each DMATxDesc descriptor with the right values */ - for( i = 0; i < ( uint32_t ) ETH_TX_DESC_CNT; i++ ) - { - dmatxdesc = heth->Init.TxDesc + i; - - WRITE_REG( dmatxdesc->DESC0, 0x0 ); - WRITE_REG( dmatxdesc->DESC1, 0x0 ); - WRITE_REG( dmatxdesc->DESC2, 0x0 ); - WRITE_REG( dmatxdesc->DESC3, 0x0 ); - - WRITE_REG( heth->TxDescList.TxDesc[ i ], ( uint32_t ) dmatxdesc ); - } - - heth->TxDescList.CurTxDesc = 0; - heth->TxDescList.TailTxDesc = 0; - - /* Set Transmit Descriptor Ring Length */ - WRITE_REG( heth->Instance->DMACTDRLR, ( ETH_TX_DESC_CNT - 1 ) ); - - /* Set Transmit Descriptor List Address */ - /* Channel Tx descriptor list address register (ETH_DMACTXDLAR)). */ - WRITE_REG( heth->Instance->DMACTDLAR, ( uint32_t ) heth->Init.TxDesc ); - - /* Set Transmit Descriptor Tail pointer */ - WRITE_REG( heth->Instance->DMACTDTPR, ( uint32_t ) heth->Init.TxDesc ); - } - -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ - static void ETH_DMARxDescListInit( ETH_HandleTypeDef * heth ) - { - ETH_DMADescTypeDef * dmarxdesc; - uint32_t i; - - for( i = 0; i < ( uint32_t ) ETH_RX_DESC_CNT; i++ ) - { - dmarxdesc = heth->Init.RxDesc + i; - - WRITE_REG( dmarxdesc->DESC0, 0x0 ); - WRITE_REG( dmarxdesc->DESC1, 0x0 ); - WRITE_REG( dmarxdesc->DESC2, 0x0 ); - WRITE_REG( dmarxdesc->DESC3, 0x0 ); - WRITE_REG( dmarxdesc->BackupAddr0, 0x0 ); - WRITE_REG( dmarxdesc->BackupAddr1, 0x0 ); - - /* Set Rx descritors adresses */ - WRITE_REG( heth->RxDescList.RxDesc[ i ], ( uint32_t ) dmarxdesc ); - } - - WRITE_REG( heth->RxDescList.CurRxDesc, 0 ); - WRITE_REG( heth->RxDescList.FirstAppDesc, 0 ); - WRITE_REG( heth->RxDescList.AppDescNbr, 0 ); - WRITE_REG( heth->RxDescList.ItMode, 0 ); - WRITE_REG( heth->RxDescList.AppContextDesc, 0 ); - - /* Set Receive Descriptor Ring Length */ - WRITE_REG( heth->Instance->DMACRDRLR, ( uint32_t ) ( ETH_RX_DESC_CNT - 1 ) ); - - /* Set Receive Descriptor List Address */ - /* Channel Rx descriptor list address register (ETH_DMACRXDLAR)). */ - WRITE_REG( heth->Instance->DMACRDLAR, ( uint32_t ) heth->Init.RxDesc ); - - /* Set Receive Descriptor Tail pointer Address */ - WRITE_REG( heth->Instance->DMACRDTPR, ( ( uint32_t ) ( heth->Init.RxDesc + ( uint32_t ) ( ETH_RX_DESC_CNT - 1 ) ) ) ); - } - - void ETH_Clear_Tx_Descriptors( ETH_HandleTypeDef * heth ) - { - uint32_t ulTailTxDesc = heth->TxDescList.TailTxDesc; - - while( ( uxSemaphoreGetCount( xTXDescriptorSemaphore ) ) != ETH_TX_DESC_CNT ) - { - ETH_DMADescTypeDef * xDMATxDescriptor = ( ETH_DMADescTypeDef * ) heth->TxDescList.TxDesc[ ulTailTxDesc ]; - - if( ( xDMATxDescriptor->DESC3 & ETH_DMATXNDESCRF_OWN ) != 0 ) - { - /* No buffer is assigned or DMA still OWNs this descriptor. */ - break; - } - - #if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) - { - NetworkBufferDescriptor_t * pxNetworkBuffer; - uint8_t * ucPayLoad; - - ucPayLoad = ( uint8_t * ) xDMATxDescriptor->DESC0; - - if( ucPayLoad == NULL ) - { - /* No buffer is assigned or DMA still OWNs this descriptor. */ - break; - } - - pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad ); - - if( pxNetworkBuffer != NULL ) - { - vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); - } - } - #endif /* if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) */ - - xDMATxDescriptor->DESC0 = ( uint32_t ) 0u; - - INCR_TX_DESC_INDEX( ulTailTxDesc, 1U ); - heth->TxDescList.TailTxDesc = ulTailTxDesc; - - __DSB(); - - xSemaphoreGive( xTXDescriptorSemaphore ); - } - } - -/** - * @brief Prepare Tx DMA descriptor before transmission. - * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pTxConfig: Tx packet configuration - * @param ItMode: Enable or disable Tx EOT interrept - * @retval Status - */ - static uint32_t ETH_Prepare_Tx_Descriptors( ETH_HandleTypeDef * heth, - ETH_TxPacketConfig * pTxConfig, - uint32_t ItMode ) - { - ETH_TxDescListTypeDef * dmatxdesclist = &heth->TxDescList; - uint32_t firstdescidx = dmatxdesclist->CurTxDesc; - uint32_t DESC3; - ETH_DMADescTypeDef * dmatxdesc = ( ETH_DMADescTypeDef * ) dmatxdesclist->TxDesc[ firstdescidx ]; - ETH_BufferTypeDef * txbuffer = pTxConfig->TxBuffer; - - /* FreeRTOS+TCP doesn't support linked buffers. */ - txbuffer->next = NULL; - DESC3 = READ_REG( dmatxdesc->DESC3 ); - - /* Current TX Descriptor Owned by DMA: cannot be used by the application */ - if( READ_BIT( DESC3, ETH_DMATXNDESCWBF_OWN ) != 0U ) - { - /* Should not get here because TX descriptors are protected by a counting semaphore. */ - return HAL_ETH_ERROR_BUSY; - } - - /***************************************************************************/ - /***************** Normal descriptors configuration *****************/ - /***************************************************************************/ - - /* Set header or buffer 1 address */ - WRITE_REG( dmatxdesc->DESC0, ( uint32_t ) txbuffer->buffer ); - /* Set header or buffer 1 Length */ - MODIFY_REG( dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len ); - - WRITE_REG( dmatxdesc->DESC1, 0x0 ); - /* Set buffer 2 Length to zero */ - MODIFY_REG( dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U ); - - MODIFY_REG( DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length ); - - if( READ_BIT( pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM ) != 0U ) - { - MODIFY_REG( DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl ); - } - - if( READ_BIT( pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD ) != 0U ) - { - MODIFY_REG( DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl ); - } - - /* Mark it as First and the last Descriptor */ - SET_BIT( DESC3, ETH_DMATXNDESCRF_FD | ETH_DMATXNDESCRF_LD ); - - /* Mark it as NORMAL descriptor */ - CLEAR_BIT( DESC3, ETH_DMATXNDESCRF_CTXT ); - - /* set OWN bit of FIRST descriptor */ - SET_BIT( DESC3, ETH_DMATXNDESCRF_OWN ); - - if( ItMode != ( ( uint32_t ) RESET ) ) - { - /* Set Interrupt on competition bit */ - SET_BIT( dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC ); - } - else - { - /* Clear Interrupt on competition bit */ - CLEAR_BIT( dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC ); - } - - WRITE_REG( dmatxdesc->DESC3, DESC3 ); - - /* Read back the value. */ - if( READ_REG( dmatxdesc->DESC3 ) ) - { - } - - __DSB(); - - /* Return function status */ - return HAL_ETH_ERROR_NONE; - } - - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - static void ETH_InitCallbacksToDefault( ETH_HandleTypeDef * heth ) - { - /* Init the ETH Callback settings */ - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ - heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; /* Legacy weak DMAErrorCallback */ - heth->MACErrorCallback = HAL_ETH_MACErrorCallback; /* Legacy weak MACErrorCallback */ - heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ - heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */ - heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ - } - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - - #endif /* ETH */ - -#endif /* HAL_ETH_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.h b/source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.h deleted file mode 100644 index 519d8c659..000000000 --- a/source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.h +++ /dev/null @@ -1,1876 +0,0 @@ -/** - ****************************************************************************** - * @file stm32hxx_hal_eth.h - * @author MCD Application Team - * @brief Header file of ETH HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32Hxx_HAL_ETH_H - #define STM32Hxx_HAL_ETH_H - - #define STM32H7xx_HAL_ETH_H - - #ifdef __cplusplus - extern "C" { - #endif - - -/* Includes ------------------------------------------------------------------*/ - #include "stm32h7xx_hal_def.h" - - #if defined( ETH ) - -/** @addtogroup STM32H7xx_HAL_Driver - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - #ifndef ETH_TX_DESC_CNT - #error Please define ETH_TX_DESC_CNT in your stm32h7xx_hal_conf.h - #endif - - #ifndef ETH_RX_DESC_CNT - #error Please define ETH_RX_DESC_CNT in your stm32h7xx_hal_conf.h - #endif - -/*********************** Descriptors struct def section ************************/ - -/** @defgroup ETH_Exported_Types ETH Exported Types - * @{ - */ - struct xErrorFields - { - uint16_t - ERR_IHE : 1, /* IP Header Error */ - ERR_DB : 1, /* Deferred Bit */ - ERR_Umderflow : 1, /* Underflow Error */ - ERR_ExcDefer : 1, /* Excessive Deferral */ - ERR_CC : 4, /* Collision count. */ - ERR_EC : 1, /* Excessive Collision */ - ERR_LC : 1, /* Late collision. */ - ERR_NC : 1, /* No carrier. */ - ERR_LoC : 1, /* Loss of Carrier: carrier lost during transmission */ - ERR_PCE : 1, /* Payload Checksum Error */ - ERR_FF : 1, /* Packet Flushed: DMA/MTL flushed the packet due to SW flush */ - ERR_JT : 1, /* Jabber Timeout */ - ERR_SUMMARY : 1; - } - __attribute__( ( packed ) ); - -/** - * @brief ETH DMA Descriptor structure definition - */ - typedef struct - { - union - { - __IO uint32_t DESC0; /* The buffer */ - uint32_t Buffer_1____; - }; - union - { - __IO uint32_t DESC1; - uint32_t Buffer_2____; - }; - union - { - __IO uint32_t DESC2; /* Buffer 1 length (0x00003FFFU) Buffer 2 Length (0x3FFF0000) */ - struct - { - unsigned - Buff1_Length : 14, /* Buffer 1 Length */ - VTIR________ : 2, /* VLAN Tag Insertion or Replacement mask */ - Buff2_Length : 14, /* Buffer 2 Length */ - TTSE________ : 1, /* Transmit Timestamp Enable */ - IOC_________ : 1; /* Interrupt on Completion */ - }; - }; - union - { - __IO uint32_t DESC3; /* bit 31 is the OWN (by DMA) bit */ - struct - { - struct xErrorFields ERR_FIELDS; - struct - { - uint16_t - - Reserved_1__ : 1, - TIMESTAMP___ : 1, /*!< Tx Timestamp Status */ - Reserved_3__ : 10, - LAST_DESC___ : 1, /*!< Last Descriptor */ - FIRST_DESC__ : 1, /*!< First Descriptor */ - STATUS_CTX__ : 1, /*!< Context Type */ - OWN_________ : 1; - } __attribute__( ( packed ) ); - }; - }; - uint32_t BackupAddr0; /* used to store rx buffer 1 address */ - uint32_t BackupAddr1; /* used to store rx buffer 2 address */ - } ETH_DMADescTypeDef; - -/* - * Channel status register ( see field DMACSR, or "ETH_DMACSR". - */ - typedef struct - { - union - { - uint32_t ulValue; - struct - { - uint32_t - TI_Transmit_Interrupt__________ : 1, - TPS_Transmit_Process_Stopped___ : 1, - TBU_Transmit_Buffer_Unavailable : 1, - R_0 : 3, - RI_Receive_Interrupt___________ : 1, - RBU_Receive_Buffer_Unavailable_ : 1, - RPS_Receive_Process_Stopped____ : 1, - RWT_Receive_Watchdog_Timeout___ : 1, - ETI_Early_Transmit_Interrupt___ : 1, - ERI_Early_Receive_Interrupt____ : 1, - FBE_Fatal_Bus_Error____________ : 1, - CDE_Context_Descriptor_Error___ : 1, - AIS_Abnormal_Interrupt_Summary_ : 1, - NIS_Normal_Interrupt_Summary___ : 1, - - REB_0_Error_during_read_transfer_when_1__________ : 1, - REB_1_Error_during_descriptor_access_when_1______ : 1, - REB_2_Error_during_data_transfer_by_Rx_DMA_when_1 : 1, - - TEB_0_Error_during_read_transfer_when_1__________ : 1, - TEB_1_Error_during_descriptor_access_when_1______ : 1, - TEB_2_Error_during_data_transfer_by_Tx_DMA_when_1 : 1, - - R_1 : 10; - }; - }; - } IntStatus_t; - -/** - * - */ - -/** - * @brief ETH Buffers List structure definition - */ - typedef struct __ETH_BufferTypeDef - { - uint8_t * buffer; /*gState = HAL_ETH_STATE_RESET; \ - ( __HANDLE__ )->RxState = HAL_ETH_STATE_RESET; \ - ( __HANDLE__ )->MspInitCallback = NULL; \ - ( __HANDLE__ )->MspDeInitCallback = NULL; \ - } while( 0 ) - #else - #define __HAL_ETH_RESET_HANDLE_STATE( __HANDLE__ ) \ - do { \ - ( __HANDLE__ )->gState = HAL_ETH_STATE_RESET; \ - ( __HANDLE__ )->RxState = HAL_ETH_STATE_RESET; \ - } while( 0 ) - #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @brief Enables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be - * enabled @ref ETH_DMA_Interrupts - * @retval None - */ - #define __HAL_ETH_DMA_ENABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMACIER |= ( __INTERRUPT__ ) ) - -/** - * @brief Disables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be - * disabled. @ref ETH_DMA_Interrupts - * @retval None - */ - #define __HAL_ETH_DMA_DISABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMACIER &= ~( __INTERRUPT__ ) ) - -/** - * @brief Gets the ETHERNET DMA IT source enabled or disabled. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts - * @retval The ETH DMA IT Source enabled or disabled - */ - #define __HAL_ETH_DMA_GET_IT_SOURCE( __HANDLE__, __INTERRUPT__ ) ( ( ( __HANDLE__ )->Instance->DMACIER & ( __INTERRUPT__ ) ) == ( __INTERRUPT__ ) ) - -/** - * @brief Gets the ETHERNET DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts - * @retval The state of ETH DMA IT (SET or RESET) - */ - #define __HAL_ETH_DMA_GET_IT( __HANDLE__, __INTERRUPT__ ) ( ( ( __HANDLE__ )->Instance->DMACSR & ( __INTERRUPT__ ) ) == ( __INTERRUPT__ ) ) - -/** - * @brief Clears the ETHERNET DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ - #define __HAL_ETH_DMA_CLEAR_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMACSR = ( __INTERRUPT__ ) ) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags - * @retval The state of ETH DMA FLAG (SET or RESET). - */ - #define __HAL_ETH_DMA_GET_FLAG( __HANDLE__, __FLAG__ ) ( ( ( __HANDLE__ )->Instance->DMACSR & ( __FLAG__ ) ) == ( __FLAG__ ) ) - -/** - * @brief Clears the specified ETHERNET DMA flag. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags - * @retval The state of ETH DMA FLAG (SET or RESET). - */ - #define __HAL_ETH_DMA_CLEAR_FLAG( __HANDLE__, __FLAG__ ) ( ( __HANDLE__ )->Instance->DMACSR = ( __FLAG__ ) ) - -/** - * @brief Enables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be - * enabled @ref ETH_MAC_Interrupts - * @retval None - */ - #define __HAL_ETH_MAC_ENABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MACIER |= ( __INTERRUPT__ ) ) - -/** - * @brief Disables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be - * enabled @ref ETH_MAC_Interrupts - * @retval None - */ - #define __HAL_ETH_MAC_DISABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MACIER &= ~( __INTERRUPT__ ) ) - -/** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts - * @retval The state of ETH MAC IT (SET or RESET). - */ - #define __HAL_ETH_MAC_GET_IT( __HANDLE__, __INTERRUPT__ ) ( ( ( __HANDLE__ )->Instance->MACISR & ( __INTERRUPT__ ) ) == ( __INTERRUPT__ ) ) - -/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ - #define ETH_WAKEUP_EXTI_LINE ( ( uint32_t ) 0x00400000U ) /* !< 86 - 64 = 22 */ - -/** - * @brief Enable the ETH WAKEUP Exti Line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None. - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT( __EXTI_LINE__ ) ( EXTI_D1->IMR3 |= ( __EXTI_LINE__ ) ) - -/** - * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval EXTI ETH WAKEUP Line Status. - */ - #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG( __EXTI_LINE__ ) ( EXTI_D1->PR3 & ( __EXTI_LINE__ ) ) - -/** - * @brief Clear the ETH WAKEUP Exti flag. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None. - */ - #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG( __EXTI_LINE__ ) ( EXTI_D1->PR3 = ( __EXTI_LINE__ ) ) - - #if defined( DUAL_CORE ) - -/** - * @brief Enable the ETH WAKEUP Exti Line by Core2. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None. - */ - #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT( __EXTI_LINE__ ) ( EXTI_D2->IMR3 |= ( __EXTI_LINE__ ) ) - -/** - * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval EXTI ETH WAKEUP Line Status. - */ - #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG( __EXTI_LINE__ ) ( EXTI_D2->PR3 & ( __EXTI_LINE__ ) ) - -/** - * @brief Clear the ETH WAKEUP Exti flag. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None. - */ - #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG( __EXTI_LINE__ ) ( EXTI_D2->PR3 = ( __EXTI_LINE__ ) ) - #endif - -/** - * @brief enable rising edge interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE( __EXTI_LINE__ ) \ - ( EXTI->FTSR3 &= ~( __EXTI_LINE__ ) ); \ - ( EXTI->RTSR3 |= ( __EXTI_LINE__ ) ) - -/** - * @brief enable falling edge interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE( __EXTI_LINE__ ) \ - ( EXTI->RTSR3 &= ~( __EXTI_LINE__ ) ); \ - ( EXTI->FTSR3 |= ( __EXTI_LINE__ ) ) - -/** - * @brief enable falling edge interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE( __EXTI_LINE__ ) \ - ( EXTI->RTSR3 |= ( __EXTI_LINE__ ) ); \ - ( EXTI->FTSR3 |= ( __EXTI_LINE__ ) ) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ - #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT( __EXTI_LINE__ ) ( EXTI->SWIER3 |= ( __EXTI_LINE__ ) ) - -/** - * @} - */ - -/* Include ETH HAL Extension module */ - #include "stm32h7xx_hal_eth_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup ETH_Exported_Functions - * @{ - */ - -/** @addtogroup ETH_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de initialization functions **********************************/ - HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_DeInit( ETH_HandleTypeDef * heth ); - void HAL_ETH_MspInit( ETH_HandleTypeDef * heth ); - void HAL_ETH_MspDeInit( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_DescAssignMemory( ETH_HandleTypeDef * heth, - uint32_t Index, - uint8_t * pBuffer1, - uint8_t * pBuffer2 ); - -/* Callbacks Register/UnRegister functions ***********************************/ - #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) - HAL_StatusTypeDef HAL_ETH_RegisterCallback( ETH_HandleTypeDef * heth, - HAL_ETH_CallbackIDTypeDef CallbackID, - pETH_CallbackTypeDef pCallback ); - HAL_StatusTypeDef HAL_ETH_UnRegisterCallback( ETH_HandleTypeDef * heth, - HAL_ETH_CallbackIDTypeDef CallbackID ); - #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup ETH_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *******************************************************/ - HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_Start_IT( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_Stop( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_Stop_IT( ETH_HandleTypeDef * heth ); - - uint8_t HAL_ETH_IsRxDataAvailable( ETH_HandleTypeDef * heth ); -/* The following 2 functions are replaced with a single function: HAL_ETH_GetRxData(). */ -/* HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer); */ -/* HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length); */ - - size_t HAL_ETH_GetRxData( ETH_HandleTypeDef * heth, - ETH_BufferTypeDef * RxBuffer ); - - HAL_StatusTypeDef HAL_ETH_GetRxDataInfo( ETH_HandleTypeDef * heth, - ETH_RxPacketInfo * RxPacketInfo ); - HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors( ETH_HandleTypeDef * heth, - uint8_t * pucNewBuffer ); - - HAL_StatusTypeDef HAL_ETH_Transmit( ETH_HandleTypeDef * heth, - ETH_TxPacketConfig * pTxConfig, - uint32_t Timeout ); - HAL_StatusTypeDef HAL_ETH_Transmit_IT( ETH_HandleTypeDef * heth, - ETH_TxPacketConfig * pTxConfig ); - - void ETH_Clear_Tx_Descriptors( ETH_HandleTypeDef * heth ); - - - HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef * heth, - uint32_t PHYAddr, - uint32_t PHYReg, - uint32_t RegValue ); - HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef * heth, - uint32_t PHYAddr, - uint32_t PHYReg, - uint32_t * pRegValue ); - - void HAL_ETH_IRQHandler( ETH_HandleTypeDef * heth ); - void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_DMAErrorCallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_MACErrorCallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_PMTCallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_EEECallback( ETH_HandleTypeDef * heth ); - void HAL_ETH_WakeUpCallback( ETH_HandleTypeDef * heth ); - -/** - * @} - */ - -/** @addtogroup ETH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions **********************************************/ -/* MAC & DMA Configuration APIs **********************************************/ - HAL_StatusTypeDef HAL_ETH_GetMACConfig( ETH_HandleTypeDef * heth, - ETH_MACConfigTypeDef * macconf ); - HAL_StatusTypeDef HAL_ETH_GetDMAConfig( ETH_HandleTypeDef * heth, - ETH_DMAConfigTypeDef * dmaconf ); - HAL_StatusTypeDef HAL_ETH_SetMACConfig( ETH_HandleTypeDef * heth, - ETH_MACConfigTypeDef * macconf ); - HAL_StatusTypeDef HAL_ETH_SetDMAConfig( ETH_HandleTypeDef * heth, - ETH_DMAConfigTypeDef * dmaconf ); - -/* MAC VLAN Processing APIs ************************************************/ - void HAL_ETH_SetRxVLANIdentifier( ETH_HandleTypeDef * heth, - uint32_t ComparisonBits, - uint32_t VLANIdentifier ); - -/* MAC L2 Packet Filtering APIs **********************************************/ - HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig( ETH_HandleTypeDef * heth, - ETH_MACFilterConfigTypeDef * pFilterConfig ); - HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig( ETH_HandleTypeDef * heth, - ETH_MACFilterConfigTypeDef * pFilterConfig ); - HAL_StatusTypeDef HAL_ETH_SetHashTable( ETH_HandleTypeDef * heth, - uint32_t * pHashTable ); - HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch( ETH_HandleTypeDef * heth, - uint32_t AddrNbr, - uint8_t * pMACAddr ); - -/* MAC Power Down APIs *****************************************************/ - void HAL_ETH_EnterPowerDownMode( ETH_HandleTypeDef * heth, - ETH_PowerDownConfigTypeDef * pPowerDownConfig ); - void HAL_ETH_ExitPowerDownMode( ETH_HandleTypeDef * heth ); - HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter( ETH_HandleTypeDef * heth, - uint32_t * pFilter, - uint32_t Count ); - -/** - * @} - */ - -/** @addtogroup ETH_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions **************************************************/ - HAL_ETH_StateTypeDef HAL_ETH_GetState( ETH_HandleTypeDef * heth ); - uint32_t HAL_ETH_GetError( ETH_HandleTypeDef * heth ); - uint32_t HAL_ETH_GetDMAError( ETH_HandleTypeDef * heth ); - uint32_t HAL_ETH_GetMACError( ETH_HandleTypeDef * heth ); - uint32_t HAL_ETH_GetMACWakeUpSource( ETH_HandleTypeDef * heth ); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - #endif /* ETH */ - - #ifdef __cplusplus - } - #endif - -#endif /* STM32Hxx_HAL_ETH_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/