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DE2_i2sound.qsf.bak
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DE2_i2sound.qsf.bak
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# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# DE2_i2sound_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:19:12 OCTOBER 26, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name BDF_FILE DE2_i2sound.bdf
set_global_assignment -name VERILOG_FILE CLOCK_500.v
set_global_assignment -name VERILOG_FILE i2c.v
set_global_assignment -name VERILOG_FILE keytr.v
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_G26 -to KEY0
set_location_assignment PIN_N2 -to 50MHZ
set_location_assignment PIN_AE22 -to ACK
set_location_assignment PIN_A6 -to I2C_SCLK
set_location_assignment PIN_B6 -to I2C_SDAT
set_location_assignment PIN_C5 -to AUD_ADCLRCK
set_location_assignment PIN_B5 -to AUD_ADCDAT
set_location_assignment PIN_C6 -to AUD_DACLRCK
set_location_assignment PIN_A4 -to AUD_DACDAT
set_location_assignment PIN_A5 -to AUD_XCK
set_location_assignment PIN_B4 -to AUD_BCLK
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY DE2_i2sound
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id 50MHZ
set_instance_assignment -name CLOCK_SETTINGS 50MHZ -to 50MHZ
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE processing.v
set_global_assignment -name VERILOG_FILE audio_serial_to_parallel.v
set_global_assignment -name VERILOG_FILE audio_parallel_to_serial.v
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_AE23 -to LEDR0
set_location_assignment PIN_AF23 -to LEDR1
set_location_assignment PIN_AB21 -to LEDR2
set_location_assignment PIN_AC22 -to LEDR3
set_global_assignment -name VERILOG_FILE LED_STATUS.v
set_location_assignment PIN_N23 -to KEY1
set_location_assignment PIN_AD22 -to LEDR4
set_location_assignment PIN_AD23 -to LEDR5
set_location_assignment PIN_AD21 -to LEDR6
set_location_assignment PIN_AC21 -to LEDR7
set_location_assignment PIN_AA14 -to LEDR8
set_location_assignment PIN_Y13 -to LEDR9
set_location_assignment PIN_AA13 -to LEDR10
set_location_assignment PIN_AC14 -to LEDR11
set_location_assignment PIN_AD15 -to LEDR12
set_location_assignment PIN_AE15 -to LEDR13
set_location_assignment PIN_AF13 -to LEDR14
set_location_assignment PIN_AE13 -to LEDR15
set_location_assignment PIN_V2 -to SW17
set_global_assignment -name VERILOG_FILE "MUX-16bit.v"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 50000
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_AE22 -to LEDG0
set_global_assignment -name VERILOG_FILE decimator.v
set_global_assignment -name VERILOG_FILE CICfilter.v
set_global_assignment -name VERILOG_FILE audio_deserializer2.v
set_global_assignment -name VERILOG_FILE I2S_Reserializer.v
set_global_assignment -name VERILOG_FILE "FIR-LPF-1kHz.v"
set_location_assignment PIN_AD12 -to LEDR17
set_location_assignment PIN_V1 -to SW16
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VERILOG_FILE audio_serial_to_parallel_testbench.v
set_global_assignment -name VERILOG_FILE audio_parallel_to_serial_testbench.v
set_global_assignment -name VERILOG_FILE audio_passthrough_testbench.v
set_global_assignment -name VERILOG_FILE audio_passthrough_testbench_with_gap.v
set_global_assignment -name VERILOG_FILE delayBy1bit.v
set_location_assignment PIN_K25 -to gpio1_0
set_location_assignment PIN_M22 -to gpio1_2
set_location_assignment PIN_M19 -to gpio1_4
set_location_assignment PIN_N20 -to gpio1_6
set_location_assignment PIN_M24 -to gpio1_8
set_location_assignment PIN_N24 -to gpio1_10
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top